k3conf_0.3/0000775000175000017500000000000014605602073007546 5ustar k3conf_0.3/LICENSE0000664000175000017500000000276114502337202010554 0ustar Copyright (C) 2010-2023 Texas Instruments Incorporated - https://www.ti.com/ Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. k3conf_0.3/README.md0000664000175000017500000000330214560756656011044 0ustar ############################################################################### # # # K3CONF # # # # A Powerful Diagnostic Tool for Texas Instruments K3 based Processors # ############################################################################### INTRODUCTION: ------------- K3CONF is a Linux user-space standalone application designed to provide a quick'n easy way to dynamically diagnose Texas Instruments' K3 architecture based processors. K3CONF is intended to provide similar experience to that of OMAPCONF that runs on legacy TI platforms. **WARNING**: This is work in progress! Don't expect things to be complete in any dimension. Use at your own risk. And keep the reset button in reach. SUPPORT: -------- K3CONF currently supports AM654, J721E, J7200, AM64x, AM62x, J721S2, J784S4, AM62Ax and AM62Px devices. Legacy OMAP and DRA7 platforms are not supported. Build Instructions: ------------------- Install build dependencies (Debian based example): # sudo apt install build-essential cmake If cross-compiling, install and set your cross-compiler: # sudo apt install gcc-aarch64-linux-gnu # export CC=aarch64-linux-gnu-gcc To build the output binary file run the following commands: # mkdir build # cd build # cmake .. # make Copy the output binary "k3conf" to your Filesystem. That's it!! Help: ----- Type "./k3conf --help" to get complete list of available commands and options. Note that in case of incorrect command/option, help will also be displayed. k3conf_0.3/soc/0000775000175000017500000000000014511032107010321 5ustar k3conf_0.3/soc/am64x/0000775000175000017500000000000014504336513011272 5ustar k3conf_0.3/soc/am64x/am64x_devices_info.c0000664000175000017500000001443514375734376015140 0ustar /* * AM64X Devices Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_devices_info am64x_devices_info[] = { {0, "AM64X_DEV_ADC0"}, {1, "AM64X_DEV_CMP_EVENT_INTROUTER0"}, {2, "AM64X_DEV_DBGSUSPENDROUTER0"}, {3, "AM64X_DEV_MAIN_GPIOMUX_INTROUTER0"}, {5, "AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0"}, {6, "AM64X_DEV_TIMESYNC_EVENT_INTROUTER0"}, {7, "AM64X_DEV_MCU_M4FSS0"}, {9, "AM64X_DEV_MCU_M4FSS0_CORE0"}, {13, "AM64X_DEV_CPSW0"}, {14, "AM64X_DEV_CPT2_AGGR0"}, {15, "AM64X_DEV_STM0"}, {16, "AM64X_DEV_DCC0"}, {17, "AM64X_DEV_DCC1"}, {18, "AM64X_DEV_DCC2"}, {19, "AM64X_DEV_DCC3"}, {20, "AM64X_DEV_DCC4"}, {21, "AM64X_DEV_DCC5"}, {22, "AM64X_DEV_DMSC0"}, {23, "AM64X_DEV_MCU_DCC0"}, {24, "AM64X_DEV_DEBUGSS_WRAP0"}, {25, "AM64X_DEV_DMASS0"}, {26, "AM64X_DEV_DMASS0_BCDMA_0"}, {27, "AM64X_DEV_DMASS0_CBASS_0"}, {28, "AM64X_DEV_DMASS0_INTAGGR_0"}, {29, "AM64X_DEV_DMASS0_IPCSS_0"}, {30, "AM64X_DEV_DMASS0_PKTDMA_0"}, {31, "AM64X_DEV_DMASS0_PSILCFG_0"}, {32, "AM64X_DEV_DMASS0_PSILSS_0"}, {33, "AM64X_DEV_DMASS0_RINGACC_0"}, {35, "AM64X_DEV_MCU_TIMER0"}, {36, "AM64X_DEV_TIMER0"}, {37, "AM64X_DEV_TIMER1"}, {38, "AM64X_DEV_TIMER2"}, {39, "AM64X_DEV_TIMER3"}, {40, "AM64X_DEV_TIMER4"}, {41, "AM64X_DEV_TIMER5"}, {42, "AM64X_DEV_TIMER6"}, {43, "AM64X_DEV_TIMER7"}, {44, "AM64X_DEV_TIMER8"}, {45, "AM64X_DEV_TIMER9"}, {46, "AM64X_DEV_TIMER10"}, {47, "AM64X_DEV_TIMER11"}, {48, "AM64X_DEV_MCU_TIMER1"}, {49, "AM64X_DEV_MCU_TIMER2"}, {50, "AM64X_DEV_MCU_TIMER3"}, {51, "AM64X_DEV_ECAP0"}, {52, "AM64X_DEV_ECAP1"}, {53, "AM64X_DEV_ECAP2"}, {54, "AM64X_DEV_ELM0"}, {55, "AM64X_DEV_EMIF_DATA_0_VD"}, {57, "AM64X_DEV_MMCSD0"}, {58, "AM64X_DEV_MMCSD1"}, {59, "AM64X_DEV_EQEP0"}, {60, "AM64X_DEV_EQEP1"}, {61, "AM64X_DEV_GTC0"}, {62, "AM64X_DEV_EQEP2"}, {63, "AM64X_DEV_ESM0"}, {64, "AM64X_DEV_MCU_ESM0"}, {65, "AM64X_DEV_FSIRX0"}, {66, "AM64X_DEV_FSIRX1"}, {67, "AM64X_DEV_FSIRX2"}, {68, "AM64X_DEV_FSIRX3"}, {69, "AM64X_DEV_FSIRX4"}, {70, "AM64X_DEV_FSIRX5"}, {71, "AM64X_DEV_FSITX0"}, {72, "AM64X_DEV_FSITX1"}, {73, "AM64X_DEV_FSS0"}, {74, "AM64X_DEV_FSS0_FSAS_0"}, {75, "AM64X_DEV_FSS0_OSPI_0"}, {76, "AM64X_DEV_GICSS0"}, {77, "AM64X_DEV_GPIO0"}, {78, "AM64X_DEV_GPIO1"}, {79, "AM64X_DEV_MCU_GPIO0"}, {80, "AM64X_DEV_GPMC0"}, {81, "AM64X_DEV_PRU_ICSSG0"}, {82, "AM64X_DEV_PRU_ICSSG1"}, {83, "AM64X_DEV_LED0"}, {84, "AM64X_DEV_CPTS0"}, {85, "AM64X_DEV_DDPA0"}, {86, "AM64X_DEV_EPWM0"}, {87, "AM64X_DEV_EPWM1"}, {88, "AM64X_DEV_EPWM2"}, {89, "AM64X_DEV_EPWM3"}, {90, "AM64X_DEV_EPWM4"}, {91, "AM64X_DEV_EPWM5"}, {92, "AM64X_DEV_EPWM6"}, {93, "AM64X_DEV_EPWM7"}, {94, "AM64X_DEV_EPWM8"}, {95, "AM64X_DEV_VTM0"}, {96, "AM64X_DEV_MAILBOX0"}, {97, "AM64X_DEV_MAIN2MCU_VD"}, {98, "AM64X_DEV_MCAN0"}, {99, "AM64X_DEV_MCAN1"}, {100, "AM64X_DEV_MCU_MCRC64_0"}, {101, "AM64X_DEV_MCU2MAIN_VD"}, {102, "AM64X_DEV_I2C0"}, {103, "AM64X_DEV_I2C1"}, {104, "AM64X_DEV_I2C2"}, {105, "AM64X_DEV_I2C3"}, {106, "AM64X_DEV_MCU_I2C0"}, {107, "AM64X_DEV_MCU_I2C1"}, {108, "AM64X_DEV_MSRAM_256K0"}, {109, "AM64X_DEV_MSRAM_256K1"}, {110, "AM64X_DEV_MSRAM_256K2"}, {111, "AM64X_DEV_MSRAM_256K3"}, {112, "AM64X_DEV_MSRAM_256K4"}, {113, "AM64X_DEV_MSRAM_256K5"}, {114, "AM64X_DEV_PCIE0"}, {115, "AM64X_DEV_POSTDIV1_16FFT1"}, {116, "AM64X_DEV_POSTDIV4_16FF0"}, {117, "AM64X_DEV_POSTDIV4_16FF2"}, {118, "AM64X_DEV_PSRAMECC0"}, {119, "AM64X_DEV_R5FSS0"}, {120, "AM64X_DEV_R5FSS1"}, {121, "AM64X_DEV_R5FSS0_CORE0"}, {122, "AM64X_DEV_R5FSS0_CORE1"}, {123, "AM64X_DEV_R5FSS1_CORE0"}, {124, "AM64X_DEV_R5FSS1_CORE1"}, {125, "AM64X_DEV_RTI0"}, {126, "AM64X_DEV_RTI1"}, {127, "AM64X_DEV_RTI8"}, {128, "AM64X_DEV_RTI9"}, {130, "AM64X_DEV_RTI10"}, {131, "AM64X_DEV_RTI11"}, {132, "AM64X_DEV_MCU_RTI0"}, {133, "AM64X_DEV_SA2_UL0"}, {134, "AM64X_DEV_COMPUTE_CLUSTER0"}, {135, "AM64X_DEV_A53SS0_CORE_0"}, {136, "AM64X_DEV_A53SS0_CORE_1"}, {137, "AM64X_DEV_A53SS0"}, {138, "AM64X_DEV_DDR16SS0"}, {139, "AM64X_DEV_PSC0"}, {140, "AM64X_DEV_MCU_PSC0"}, {141, "AM64X_DEV_MCSPI0"}, {142, "AM64X_DEV_MCSPI1"}, {143, "AM64X_DEV_MCSPI2"}, {144, "AM64X_DEV_MCSPI3"}, {145, "AM64X_DEV_MCSPI4"}, {146, "AM64X_DEV_UART0"}, {147, "AM64X_DEV_MCU_MCSPI0"}, {148, "AM64X_DEV_MCU_MCSPI1"}, {149, "AM64X_DEV_MCU_UART0"}, {150, "AM64X_DEV_SPINLOCK0"}, {151, "AM64X_DEV_TIMERMGR0"}, {152, "AM64X_DEV_UART1"}, {153, "AM64X_DEV_UART2"}, {154, "AM64X_DEV_UART3"}, {155, "AM64X_DEV_UART4"}, {156, "AM64X_DEV_UART5"}, {157, "AM64X_DEV_BOARD0"}, {158, "AM64X_DEV_UART6"}, {160, "AM64X_DEV_MCU_UART1"}, {161, "AM64X_DEV_USB0"}, {162, "AM64X_DEV_SERDES_10G0"}, {163, "AM64X_DEV_PBIST0"}, {164, "AM64X_DEV_PBIST1"}, {165, "AM64X_DEV_PBIST2"}, {166, "AM64X_DEV_PBIST3"}, {167, "AM64X_DEV_COMPUTE_CLUSTER0_PBIST_0"}, }; k3conf_0.3/soc/am64x/am64x_sec_proxy_info.h0000664000175000017500000000351014504336513015507 0ustar /* * AM64X Sec Proxy Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM64X_SEC_PROXY_INFO_H #define __AM64X_SEC_PROXY_INFO_H #define AM64X_MAIN_SEC_PROXY_THREADS 28 extern struct ti_sci_sec_proxy_info am64x_main_sp_info[]; #endif /* __AM64X_SEC_PROXY_INFO_H */ k3conf_0.3/soc/am64x/am64x_host_info.h0000664000175000017500000000444314504336513014457 0ustar /* * AM64X Host Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM64X_HOST_INFO_H #define __AM64X_HOST_INFO_H #define AM64X_HOST_ID_DMSC 0 #define AM64X_HOST_ID_MAIN_0_R5_0 35 #define AM64X_HOST_ID_MAIN_0_R5_1 36 #define AM64X_HOST_ID_MAIN_0_R5_2 37 #define AM64X_HOST_ID_MAIN_0_R5_3 38 #define AM64X_HOST_ID_A53_0 10 #define AM64X_HOST_ID_A53_1 11 #define AM64X_HOST_ID_A53_2 12 #define AM64X_HOST_ID_A53_3 13 #define AM64X_HOST_ID_M4_0 30 #define AM64X_HOST_ID_MAIN_1_R5_0 40 #define AM64X_HOST_ID_MAIN_1_R5_1 41 #define AM64X_HOST_ID_MAIN_1_R5_2 42 #define AM64X_HOST_ID_MAIN_1_R5_3 43 #define AM64X_HOST_ID_ICSSG_0 50 #define AM64X_MAX_HOST_IDS 15 extern struct ti_sci_host_info am64x_host_info[]; #endif /* __AM64X_HOST_INFO_H */ k3conf_0.3/soc/am64x/am64x_rm_info.c0000664000175000017500000001257014375734376014132 0ustar /* * AM64X RM Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_rm_info am64x_rm_info[] = { {0x0040, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x00C0, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x0140, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x0180, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x0682, "RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER"}, {0x0683, "RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG"}, {0x068D, "RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN"}, {0x068E, "RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN"}, {0x068F, "RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN"}, {0x06A0, "RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN"}, {0x06A1, "RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN"}, {0x06A2, "RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN"}, {0x070A, "RESASG_SUBTYPE_IA_VINT"}, {0x070D, "RESASG_SUBTYPE_GLOBAL_EVENT_SEVT"}, {0x070F, "RESASG_SUBTYPE_IA_TIMERMGR_EVT_OES"}, {0x0710, "RESASG_SUBTYPE_IA_PKTDMA_TX_CHAN_ERROR_OES"}, {0x0711, "RESASG_SUBTYPE_IA_PKTDMA_TX_FLOW_COMPLETION_OES"}, {0x0712, "RESASG_SUBTYPE_IA_PKTDMA_RX_CHAN_ERROR_OES"}, {0x0713, "RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_COMPLETION_OES"}, {0x0714, "RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_STARVATION_OES"}, {0x0715, "RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_FIREWALL_OES"}, {0x0716, "RESASG_SUBTYPE_IA_BCDMA_CHAN_ERROR_OES"}, {0x0717, "RESASG_SUBTYPE_IA_BCDMA_CHAN_DATA_COMPLETION_OES"}, {0x0718, "RESASG_SUBTYPE_IA_BCDMA_CHAN_RING_COMPLETION_OES"}, {0x0719, "RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_ERROR_OES"}, {0x071A, "RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_DATA_COMPLETION_OES"}, {0x071B, "RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_RING_COMPLETION_OES"}, {0x071C, "RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_ERROR_OES"}, {0x071D, "RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_DATA_COMPLETION_OES"}, {0x071E, "RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_RING_COMPLETION_OES"}, {0x0783, "RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG"}, {0x0790, "RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN"}, {0x0791, "RESASG_SUBTYPE_PKTDMA_RING_CPSW_TX_CHAN"}, {0x0792, "RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_0_CHAN"}, {0x0793, "RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_1_CHAN"}, {0x0794, "RESASG_SUBTYPE_PKTDMA_RING_ICSSG_0_TX_CHAN"}, {0x0795, "RESASG_SUBTYPE_PKTDMA_RING_ICSSG_1_TX_CHAN"}, {0x0796, "RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN"}, {0x0797, "RESASG_SUBTYPE_PKTDMA_RING_CPSW_RX_CHAN"}, {0x0798, "RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_0_CHAN"}, {0x0799, "RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_1_CHAN"}, {0x079A, "RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_2_CHAN"}, {0x079B, "RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_3_CHAN"}, {0x079C, "RESASG_SUBTYPE_PKTDMA_RING_ICSSG_0_RX_CHAN"}, {0x079D, "RESASG_SUBTYPE_PKTDMA_RING_ICSSG_1_RX_CHAN"}, {0x07A3, "RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN"}, {0x07A4, "RESASG_SUBTYPE_PKTDMA_CPSW_TX_CHAN"}, {0x07A5, "RESASG_SUBTYPE_PKTDMA_SAUL_TX_0_CHAN"}, {0x07A6, "RESASG_SUBTYPE_PKTDMA_SAUL_TX_1_CHAN"}, {0x07A7, "RESASG_SUBTYPE_PKTDMA_ICSSG_0_TX_CHAN"}, {0x07A8, "RESASG_SUBTYPE_PKTDMA_ICSSG_1_TX_CHAN"}, {0x07A9, "RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN"}, {0x07AA, "RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN"}, {0x07AB, "RESASG_SUBTYPE_PKTDMA_CPSW_RX_CHAN"}, {0x07AC, "RESASG_SUBTYPE_PKTDMA_FLOW_CPSW_RX_CHAN"}, {0x07AD, "RESASG_SUBTYPE_PKTDMA_SAUL_RX_0_CHAN"}, {0x07AE, "RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_0_CHAN"}, {0x07AF, "RESASG_SUBTYPE_PKTDMA_SAUL_RX_1_CHAN"}, {0x07B0, "RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_1_CHAN"}, {0x07B1, "RESASG_SUBTYPE_PKTDMA_SAUL_RX_2_CHAN"}, {0x07B2, "RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_2_CHAN"}, {0x07B3, "RESASG_SUBTYPE_PKTDMA_SAUL_RX_3_CHAN"}, {0x07B4, "RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_3_CHAN"}, {0x07B5, "RESASG_SUBTYPE_PKTDMA_ICSSG_0_RX_CHAN"}, {0x07B6, "RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_0_RX_CHAN"}, {0x07B7, "RESASG_SUBTYPE_PKTDMA_ICSSG_1_RX_CHAN"}, {0x07B8, "RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_1_RX_CHAN"}, {0x0840, "RESASG_SUBTYPE_RA_ERROR_OES"}, {0x084A, "RESASG_SUBTYPE_RA_VIRTID"}, {0x084C, "RESASG_SUBTYPE_RA_GENERIC_IPC"}, }; k3conf_0.3/soc/am64x/am64x_rm_info.h0000664000175000017500000000342114504336513014113 0ustar /* * AM64X RM Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM64X_RM_INFO_H #define __AM64X_RM_INFO_H #define AM64X_MAX_RES 70 extern struct ti_sci_rm_info am64x_rm_info[]; #endif /* __AM64X_RM_INFO_H */ k3conf_0.3/soc/am64x/am64x_clocks_info.c0000664000175000017500000024374014375734376014777 0ustar /* * AM64X Clocks Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_clocks_info am64x_clocks_info[] = { {137, 0, "DEV_A53SS0_COREPAC_ARM_CLK_CLK", "Input clock"}, {137, 1, "DEV_A53SS0_PLL_CTRL_CLK", "Input clock"}, {137, 2, "DEV_A53SS0_A53_DIVH_CLK4_OBSCLK_OUT_CLK", "Output clock"}, {135, 0, "DEV_A53SS0_CORE_0_A53_CORE0_ARM_CLK_CLK", "Input clock"}, {136, 0, "DEV_A53SS0_CORE_1_A53_CORE1_ARM_CLK_CLK", "Input clock"}, {0, 0, "DEV_ADC0_ADC_CLK", "Input muxed clock"}, {0, 1, "DEV_ADC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_ADC0_ADC_CLK"}, {0, 2, "DEV_ADC0_ADC_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK", "Parent input clock option to DEV_ADC0_ADC_CLK"}, {0, 3, "DEV_ADC0_ADC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK", "Parent input clock option to DEV_ADC0_ADC_CLK"}, {0, 4, "DEV_ADC0_ADC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ADC0_ADC_CLK"}, {0, 5, "DEV_ADC0_SYS_CLK", "Input clock"}, {0, 6, "DEV_ADC0_VBUS_CLK", "Input clock"}, {157, 0, "DEV_BOARD0_FSI_TX0_CLK_IN", "Input clock"}, {157, 1, "DEV_BOARD0_FSI_TX1_CLK_IN", "Input clock"}, {157, 2, "DEV_BOARD0_GPMC0_CLKLB_IN", "Input clock"}, {157, 3, "DEV_BOARD0_GPMC0_CLK_IN", "Input clock"}, {157, 4, "DEV_BOARD0_GPMC0_FCLK_MUX_IN", "Input muxed clock"}, {157, 5, "DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_BOARD0_GPMC0_FCLK_MUX_IN"}, {157, 6, "DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK", "Parent input clock option to DEV_BOARD0_GPMC0_FCLK_MUX_IN"}, {157, 7, "DEV_BOARD0_I2C0_SCL_IN", "Input clock"}, {157, 8, "DEV_BOARD0_I2C1_SCL_IN", "Input clock"}, {157, 9, "DEV_BOARD0_I2C2_SCL_IN", "Input clock"}, {157, 10, "DEV_BOARD0_I2C3_SCL_IN", "Input clock"}, {157, 11, "DEV_BOARD0_MCU_I2C0_SCL_IN", "Input clock"}, {157, 12, "DEV_BOARD0_MCU_I2C1_SCL_IN", "Input clock"}, {157, 13, "DEV_BOARD0_MCU_OBSCLK0_IN", "Input muxed clock"}, {157, 14, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"}, {157, 15, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"}, {157, 16, "DEV_BOARD0_MCU_SPI0_CLK_IN", "Input clock"}, {157, 17, "DEV_BOARD0_MCU_SPI1_CLK_IN", "Input clock"}, {157, 18, "DEV_BOARD0_MCU_SYSCLKOUT0_IN", "Input clock"}, {157, 19, "DEV_BOARD0_MCU_TIMER_IO0_IN", "Input clock"}, {157, 20, "DEV_BOARD0_MCU_TIMER_IO1_IN", "Input clock"}, {157, 21, "DEV_BOARD0_MCU_TIMER_IO2_IN", "Input clock"}, {157, 22, "DEV_BOARD0_MCU_TIMER_IO3_IN", "Input clock"}, {157, 23, "DEV_BOARD0_MMC1_CLK_IN", "Input clock"}, {157, 24, "DEV_BOARD0_OBSCLK0_IN", "Input clock"}, {157, 25, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 26, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 27, "DEV_BOARD0_OBSCLK0_IN_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 28, "DEV_BOARD0_OBSCLK0_IN_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 29, "DEV_BOARD0_OBSCLK0_IN_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 30, "DEV_BOARD0_OBSCLK0_IN_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 31, "DEV_BOARD0_OBSCLK0_IN_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 32, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 33, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 34, "DEV_BOARD0_OBSCLK0_IN_PARENT_SAM64_A53_256KB_WRAP_MAIN_0_ARM_COREPACK_0_A53_DIVH_CLK4_OBSCLK_OUT_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 35, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 36, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 37, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 38, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 39, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 40, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 41, "DEV_BOARD0_OSPI0_LBCLKO_IN", "Input clock"}, {157, 42, "DEV_BOARD0_PRG0_MDIO0_MDC_IN", "Input clock"}, {157, 43, "DEV_BOARD0_PRG0_RGMII1_TXC_IN", "Input clock"}, {157, 44, "DEV_BOARD0_PRG0_RGMII2_TXC_IN", "Input clock"}, {157, 45, "DEV_BOARD0_PRG1_MDIO0_MDC_IN", "Input clock"}, {157, 46, "DEV_BOARD0_PRG1_RGMII1_TXC_IN", "Input clock"}, {157, 47, "DEV_BOARD0_PRG1_RGMII2_TXC_IN", "Input clock"}, {157, 48, "DEV_BOARD0_RGMII1_TXC_IN", "Input clock"}, {157, 49, "DEV_BOARD0_RGMII2_TXC_IN", "Input clock"}, {157, 50, "DEV_BOARD0_SPI0_CLK_IN", "Input clock"}, {157, 51, "DEV_BOARD0_SPI1_CLK_IN", "Input clock"}, {157, 52, "DEV_BOARD0_SPI2_CLK_IN", "Input clock"}, {157, 53, "DEV_BOARD0_SPI3_CLK_IN", "Input clock"}, {157, 54, "DEV_BOARD0_SPI4_CLK_IN", "Input clock"}, {157, 55, "DEV_BOARD0_SYSCLKOUT0_IN", "Input clock"}, {157, 56, "DEV_BOARD0_TIMER_IO0_IN", "Input clock"}, {157, 57, "DEV_BOARD0_TIMER_IO10_IN", "Input clock"}, {157, 58, "DEV_BOARD0_TIMER_IO11_IN", "Input clock"}, {157, 59, "DEV_BOARD0_TIMER_IO1_IN", "Input clock"}, {157, 60, "DEV_BOARD0_TIMER_IO2_IN", "Input clock"}, {157, 61, "DEV_BOARD0_TIMER_IO3_IN", "Input clock"}, {157, 62, "DEV_BOARD0_TIMER_IO4_IN", "Input clock"}, {157, 63, "DEV_BOARD0_TIMER_IO5_IN", "Input clock"}, {157, 64, "DEV_BOARD0_TIMER_IO6_IN", "Input clock"}, {157, 65, "DEV_BOARD0_TIMER_IO7_IN", "Input clock"}, {157, 66, "DEV_BOARD0_TIMER_IO8_IN", "Input clock"}, {157, 67, "DEV_BOARD0_TIMER_IO9_IN", "Input clock"}, {157, 68, "DEV_BOARD0_CPTS0_RFT_CLK_OUT", "Output clock"}, {157, 69, "DEV_BOARD0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Output clock"}, {157, 70, "DEV_BOARD0_EXT_REFCLK1_OUT", "Output clock"}, {157, 71, "DEV_BOARD0_FSI_RX0_CLK_OUT", "Output clock"}, {157, 72, "DEV_BOARD0_FSI_RX1_CLK_OUT", "Output clock"}, {157, 73, "DEV_BOARD0_FSI_RX2_CLK_OUT", "Output clock"}, {157, 74, "DEV_BOARD0_FSI_RX3_CLK_OUT", "Output clock"}, {157, 75, "DEV_BOARD0_FSI_RX4_CLK_OUT", "Output clock"}, {157, 76, "DEV_BOARD0_FSI_RX5_CLK_OUT", "Output clock"}, {157, 77, "DEV_BOARD0_GPMC0_CLKLB_OUT", "Output clock"}, {157, 78, "DEV_BOARD0_I2C0_SCL_OUT", "Output clock"}, {157, 79, "DEV_BOARD0_I2C1_SCL_OUT", "Output clock"}, {157, 80, "DEV_BOARD0_I2C2_SCL_OUT", "Output clock"}, {157, 81, "DEV_BOARD0_I2C3_SCL_OUT", "Output clock"}, {157, 82, "DEV_BOARD0_LED_CLK_OUT", "Output clock"}, {157, 83, "DEV_BOARD0_MCU_EXT_REFCLK0_OUT", "Output clock"}, {157, 84, "DEV_BOARD0_MCU_I2C0_SCL_OUT", "Output clock"}, {157, 85, "DEV_BOARD0_MCU_I2C1_SCL_OUT", "Output clock"}, {157, 86, "DEV_BOARD0_MCU_SPI0_CLK_OUT", "Output clock"}, {157, 87, "DEV_BOARD0_MCU_SPI1_CLK_OUT", "Output clock"}, {157, 88, "DEV_BOARD0_MMC1_CLKLB_OUT", "Output clock"}, {157, 89, "DEV_BOARD0_OSPI0_DQS_OUT", "Output clock"}, {157, 90, "DEV_BOARD0_OSPI0_LBCLKO_OUT", "Output clock"}, {157, 91, "DEV_BOARD0_PRG0_RGMII1_RXC_OUT", "Output clock"}, {157, 92, "DEV_BOARD0_PRG0_RGMII1_TXC_OUT", "Output clock"}, {157, 93, "DEV_BOARD0_PRG0_RGMII2_RXC_OUT", "Output clock"}, {157, 94, "DEV_BOARD0_PRG0_RGMII2_TXC_OUT", "Output clock"}, {157, 95, "DEV_BOARD0_PRG1_RGMII1_RXC_OUT", "Output clock"}, {157, 96, "DEV_BOARD0_PRG1_RGMII1_TXC_OUT", "Output clock"}, {157, 97, "DEV_BOARD0_PRG1_RGMII2_RXC_OUT", "Output clock"}, {157, 98, "DEV_BOARD0_PRG1_RGMII2_TXC_OUT", "Output clock"}, {157, 99, "DEV_BOARD0_RGMII1_RXC_OUT", "Output clock"}, {157, 100, "DEV_BOARD0_RGMII1_TXC_OUT", "Output clock"}, {157, 101, "DEV_BOARD0_RGMII2_RXC_OUT", "Output clock"}, {157, 102, "DEV_BOARD0_RGMII2_TXC_OUT", "Output clock"}, {157, 103, "DEV_BOARD0_RMII_REF_CLK_OUT", "Output clock"}, {157, 104, "DEV_BOARD0_SPI0_CLK_OUT", "Output clock"}, {157, 105, "DEV_BOARD0_SPI1_CLK_OUT", "Output clock"}, {157, 106, "DEV_BOARD0_SPI2_CLK_OUT", "Output clock"}, {157, 107, "DEV_BOARD0_SPI3_CLK_OUT", "Output clock"}, {157, 108, "DEV_BOARD0_SPI4_CLK_OUT", "Output clock"}, {157, 109, "DEV_BOARD0_TCK_OUT", "Output clock"}, {1, 0, "DEV_CMP_EVENT_INTROUTER0_INTR_CLK", "Input clock"}, {13, 0, "DEV_CPSW0_CPPI_CLK_CLK", "Input clock"}, {13, 1, "DEV_CPSW0_CPTS_RFT_CLK", "Input muxed clock"}, {13, 2, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {13, 3, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {13, 4, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {13, 5, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {13, 6, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {13, 7, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {13, 8, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {13, 9, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {13, 10, "DEV_CPSW0_GMII1_MR_CLK", "Input clock"}, {13, 11, "DEV_CPSW0_GMII1_MT_CLK", "Input clock"}, {13, 12, "DEV_CPSW0_GMII2_MR_CLK", "Input clock"}, {13, 13, "DEV_CPSW0_GMII2_MT_CLK", "Input clock"}, {13, 14, "DEV_CPSW0_GMII_RFT_CLK", "Input clock"}, {13, 15, "DEV_CPSW0_RGMII1_RXC_I", "Input clock"}, {13, 16, "DEV_CPSW0_RGMII1_TXC_I", "Input clock"}, {13, 17, "DEV_CPSW0_RGMII2_RXC_I", "Input clock"}, {13, 18, "DEV_CPSW0_RGMII2_TXC_I", "Input clock"}, {13, 19, "DEV_CPSW0_RGMII_MHZ_250_CLK", "Input clock"}, {13, 20, "DEV_CPSW0_RGMII_MHZ_50_CLK", "Input clock"}, {13, 21, "DEV_CPSW0_RGMII_MHZ_5_CLK", "Input clock"}, {13, 22, "DEV_CPSW0_RMII_MHZ_50_CLK", "Input clock"}, {13, 23, "DEV_CPSW0_CPTS_GENF0", "Output clock"}, {13, 24, "DEV_CPSW0_CPTS_GENF1", "Output clock"}, {13, 25, "DEV_CPSW0_RGMII1_TXC_O", "Output clock"}, {13, 26, "DEV_CPSW0_RGMII2_TXC_O", "Output clock"}, {14, 0, "DEV_CPT2_AGGR0_VCLK_CLK", "Input clock"}, {84, 0, "DEV_CPTS0_CPTS_RFT_CLK", "Input muxed clock"}, {84, 1, "DEV_CPTS0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK", "Parent input clock option to DEV_CPTS0_CPTS_RFT_CLK"}, {84, 2, "DEV_CPTS0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_CPTS0_CPTS_RFT_CLK"}, {84, 3, "DEV_CPTS0_CPTS_RFT_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPTS0_CPTS_RFT_CLK"}, {84, 4, "DEV_CPTS0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPTS0_CPTS_RFT_CLK"}, {84, 5, "DEV_CPTS0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_CPTS0_CPTS_RFT_CLK"}, {84, 6, "DEV_CPTS0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_CPTS0_CPTS_RFT_CLK"}, {84, 7, "DEV_CPTS0_CPTS_RFT_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK", "Parent input clock option to DEV_CPTS0_CPTS_RFT_CLK"}, {84, 8, "DEV_CPTS0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_CPTS0_CPTS_RFT_CLK"}, {84, 9, "DEV_CPTS0_VBUSP_CLK", "Input clock"}, {84, 10, "DEV_CPTS0_CPTS_GENF1", "Output clock"}, {84, 11, "DEV_CPTS0_CPTS_GENF2", "Output clock"}, {84, 12, "DEV_CPTS0_CPTS_GENF3", "Output clock"}, {84, 13, "DEV_CPTS0_CPTS_GENF4", "Output clock"}, {2, 0, "DEV_DBGSUSPENDROUTER0_INTR_CLK", "Input clock"}, {16, 0, "DEV_DCC0_DCC_CLKSRC0_CLK", "Input clock"}, {16, 1, "DEV_DCC0_DCC_CLKSRC1_CLK", "Input clock"}, {16, 2, "DEV_DCC0_DCC_CLKSRC2_CLK", "Input clock"}, {16, 3, "DEV_DCC0_DCC_CLKSRC3_CLK", "Input clock"}, {16, 4, "DEV_DCC0_DCC_CLKSRC4_CLK", "Input clock"}, {16, 5, "DEV_DCC0_DCC_CLKSRC5_CLK", "Input clock"}, {16, 6, "DEV_DCC0_DCC_CLKSRC6_CLK", "Input clock"}, {16, 7, "DEV_DCC0_DCC_CLKSRC7_CLK", "Input clock"}, {16, 8, "DEV_DCC0_DCC_INPUT00_CLK", "Input clock"}, {16, 9, "DEV_DCC0_DCC_INPUT01_CLK", "Input clock"}, {16, 10, "DEV_DCC0_DCC_INPUT02_CLK", "Input clock"}, {16, 11, "DEV_DCC0_DCC_INPUT10_CLK", "Input clock"}, {16, 12, "DEV_DCC0_VBUS_CLK", "Input clock"}, {17, 0, "DEV_DCC1_DCC_CLKSRC0_CLK", "Input clock"}, {17, 1, "DEV_DCC1_DCC_CLKSRC1_CLK", "Input clock"}, {17, 2, "DEV_DCC1_DCC_CLKSRC2_CLK", "Input clock"}, {17, 3, "DEV_DCC1_DCC_CLKSRC3_CLK", "Input clock"}, {17, 4, "DEV_DCC1_DCC_CLKSRC4_CLK", "Input clock"}, {17, 5, "DEV_DCC1_DCC_CLKSRC5_CLK", "Input clock"}, {17, 6, "DEV_DCC1_DCC_CLKSRC6_CLK", "Input clock"}, {17, 7, "DEV_DCC1_DCC_CLKSRC7_CLK", "Input clock"}, {17, 8, "DEV_DCC1_DCC_INPUT00_CLK", "Input clock"}, {17, 9, "DEV_DCC1_DCC_INPUT01_CLK", "Input clock"}, {17, 10, "DEV_DCC1_DCC_INPUT02_CLK", "Input clock"}, {17, 11, "DEV_DCC1_DCC_INPUT10_CLK", "Input clock"}, {17, 12, "DEV_DCC1_VBUS_CLK", "Input clock"}, {18, 0, "DEV_DCC2_DCC_CLKSRC0_CLK", "Input clock"}, {18, 1, "DEV_DCC2_DCC_CLKSRC1_CLK", "Input clock"}, {18, 2, "DEV_DCC2_DCC_CLKSRC2_CLK", "Input clock"}, {18, 3, "DEV_DCC2_DCC_CLKSRC3_CLK", "Input clock"}, {18, 4, "DEV_DCC2_DCC_CLKSRC4_CLK", "Input clock"}, {18, 5, "DEV_DCC2_DCC_CLKSRC5_CLK", "Input clock"}, {18, 6, "DEV_DCC2_DCC_CLKSRC6_CLK", "Input clock"}, {18, 7, "DEV_DCC2_DCC_CLKSRC7_CLK", "Input clock"}, {18, 8, "DEV_DCC2_DCC_INPUT00_CLK", "Input clock"}, {18, 9, "DEV_DCC2_DCC_INPUT01_CLK", "Input clock"}, {18, 10, "DEV_DCC2_DCC_INPUT02_CLK", "Input clock"}, {18, 11, "DEV_DCC2_DCC_INPUT10_CLK", "Input clock"}, {18, 12, "DEV_DCC2_VBUS_CLK", "Input clock"}, {19, 0, "DEV_DCC3_DCC_CLKSRC0_CLK", "Input clock"}, {19, 1, "DEV_DCC3_DCC_CLKSRC1_CLK", "Input clock"}, {19, 2, "DEV_DCC3_DCC_CLKSRC2_CLK", "Input clock"}, {19, 3, "DEV_DCC3_DCC_CLKSRC3_CLK", "Input clock"}, {19, 4, "DEV_DCC3_DCC_CLKSRC4_CLK", "Input clock"}, {19, 5, "DEV_DCC3_DCC_CLKSRC5_CLK", "Input clock"}, {19, 6, "DEV_DCC3_DCC_CLKSRC6_CLK", "Input clock"}, {19, 7, "DEV_DCC3_DCC_CLKSRC7_CLK", "Input clock"}, {19, 8, "DEV_DCC3_DCC_INPUT00_CLK", "Input clock"}, {19, 9, "DEV_DCC3_DCC_INPUT01_CLK", "Input clock"}, {19, 10, "DEV_DCC3_DCC_INPUT02_CLK", "Input clock"}, {19, 11, "DEV_DCC3_DCC_INPUT10_CLK", "Input clock"}, {19, 12, "DEV_DCC3_VBUS_CLK", "Input clock"}, {20, 0, "DEV_DCC4_DCC_CLKSRC0_CLK", "Input muxed clock"}, {20, 1, "DEV_DCC4_DCC_CLKSRC0_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_DCC4_DCC_CLKSRC0_CLK"}, {20, 2, "DEV_DCC4_DCC_CLKSRC0_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK", "Parent input clock option to DEV_DCC4_DCC_CLKSRC0_CLK"}, {20, 3, "DEV_DCC4_DCC_CLKSRC1_CLK", "Input clock"}, {20, 4, "DEV_DCC4_DCC_CLKSRC2_CLK", "Input clock"}, {20, 5, "DEV_DCC4_DCC_CLKSRC3_CLK", "Input clock"}, {20, 6, "DEV_DCC4_DCC_CLKSRC4_CLK", "Input clock"}, {20, 7, "DEV_DCC4_DCC_CLKSRC5_CLK", "Input clock"}, {20, 8, "DEV_DCC4_DCC_CLKSRC6_CLK", "Input clock"}, {20, 9, "DEV_DCC4_DCC_CLKSRC7_CLK", "Input clock"}, {20, 10, "DEV_DCC4_DCC_INPUT00_CLK", "Input clock"}, {20, 11, "DEV_DCC4_DCC_INPUT01_CLK", "Input clock"}, {20, 12, "DEV_DCC4_DCC_INPUT02_CLK", "Input clock"}, {20, 13, "DEV_DCC4_DCC_INPUT10_CLK", "Input clock"}, {20, 14, "DEV_DCC4_VBUS_CLK", "Input clock"}, {21, 0, "DEV_DCC5_DCC_CLKSRC0_CLK", "Input clock"}, {21, 1, "DEV_DCC5_DCC_CLKSRC1_CLK", "Input clock"}, {21, 2, "DEV_DCC5_DCC_CLKSRC2_CLK", "Input clock"}, {21, 3, "DEV_DCC5_DCC_CLKSRC3_CLK", "Input clock"}, {21, 4, "DEV_DCC5_DCC_CLKSRC4_CLK", "Input clock"}, {21, 5, "DEV_DCC5_DCC_CLKSRC5_CLK", "Input clock"}, {21, 6, "DEV_DCC5_DCC_CLKSRC6_CLK", "Input clock"}, {21, 7, "DEV_DCC5_DCC_CLKSRC7_CLK", "Input clock"}, {21, 8, "DEV_DCC5_DCC_INPUT00_CLK", "Input clock"}, {21, 9, "DEV_DCC5_DCC_INPUT01_CLK", "Input clock"}, {21, 10, "DEV_DCC5_DCC_INPUT02_CLK", "Input clock"}, {21, 11, "DEV_DCC5_DCC_INPUT10_CLK", "Input clock"}, {21, 12, "DEV_DCC5_VBUS_CLK", "Input clock"}, {85, 0, "DEV_DDPA0_DDPA_CLK", "Input clock"}, {138, 0, "DEV_DDR16SS0_DDRSS_DDR_PLL_CLK", "Input clock"}, {138, 1, "DEV_DDR16SS0_PLL_CTRL_CLK", "Input clock"}, {24, 0, "DEV_DEBUGSS_WRAP0_ATB_CLK", "Input clock"}, {24, 1, "DEV_DEBUGSS_WRAP0_CORE_CLK", "Input clock"}, {24, 2, "DEV_DEBUGSS_WRAP0_JTAG_TCK", "Input clock"}, {24, 3, "DEV_DEBUGSS_WRAP0_TREXPT_CLK", "Input clock"}, {26, 0, "DEV_DMASS0_BCDMA_0_CLK", "Input clock"}, {27, 0, "DEV_DMASS0_CBASS_0_CLK", "Input clock"}, {28, 0, "DEV_DMASS0_INTAGGR_0_CLK", "Input clock"}, {29, 0, "DEV_DMASS0_IPCSS_0_CLK", "Input clock"}, {30, 0, "DEV_DMASS0_PKTDMA_0_CLK", "Input clock"}, {31, 0, "DEV_DMASS0_PSILCFG_0_CLK", "Input clock"}, {32, 0, "DEV_DMASS0_PSILSS_0_PDMA_MAIN0_CLK", "Input clock"}, {32, 1, "DEV_DMASS0_PSILSS_0_PDMA_MAIN1_CLK", "Input clock"}, {32, 2, "DEV_DMASS0_PSILSS_0_VD2CLK", "Input clock"}, {33, 0, "DEV_DMASS0_RINGACC_0_CLK", "Input clock"}, {51, 0, "DEV_ECAP0_VBUS_CLK", "Input clock"}, {52, 0, "DEV_ECAP1_VBUS_CLK", "Input clock"}, {53, 0, "DEV_ECAP2_VBUS_CLK", "Input clock"}, {54, 0, "DEV_ELM0_VBUSP_CLK", "Input clock"}, {86, 0, "DEV_EPWM0_VBUSP_CLK", "Input clock"}, {87, 0, "DEV_EPWM1_VBUSP_CLK", "Input clock"}, {88, 0, "DEV_EPWM2_VBUSP_CLK", "Input clock"}, {89, 0, "DEV_EPWM3_VBUSP_CLK", "Input clock"}, {90, 0, "DEV_EPWM4_VBUSP_CLK", "Input clock"}, {91, 0, "DEV_EPWM5_VBUSP_CLK", "Input clock"}, {92, 0, "DEV_EPWM6_VBUSP_CLK", "Input clock"}, {93, 0, "DEV_EPWM7_VBUSP_CLK", "Input clock"}, {94, 0, "DEV_EPWM8_VBUSP_CLK", "Input clock"}, {59, 0, "DEV_EQEP0_VBUS_CLK", "Input clock"}, {60, 0, "DEV_EQEP1_VBUS_CLK", "Input clock"}, {62, 0, "DEV_EQEP2_VBUS_CLK", "Input clock"}, {63, 0, "DEV_ESM0_CLK", "Input clock"}, {65, 0, "DEV_FSIRX0_FSI_RX_CK", "Input clock"}, {65, 1, "DEV_FSIRX0_FSI_RX_LPBK_CK", "Input clock"}, {65, 2, "DEV_FSIRX0_FSI_RX_VBUS_CLK", "Input clock"}, {66, 0, "DEV_FSIRX1_FSI_RX_CK", "Input clock"}, {66, 1, "DEV_FSIRX1_FSI_RX_LPBK_CK", "Input clock"}, {66, 2, "DEV_FSIRX1_FSI_RX_VBUS_CLK", "Input clock"}, {67, 0, "DEV_FSIRX2_FSI_RX_CK", "Input clock"}, {67, 1, "DEV_FSIRX2_FSI_RX_LPBK_CK", "Input clock"}, {67, 2, "DEV_FSIRX2_FSI_RX_VBUS_CLK", "Input clock"}, {68, 0, "DEV_FSIRX3_FSI_RX_CK", "Input clock"}, {68, 1, "DEV_FSIRX3_FSI_RX_LPBK_CK", "Input clock"}, {68, 2, "DEV_FSIRX3_FSI_RX_VBUS_CLK", "Input clock"}, {69, 0, "DEV_FSIRX4_FSI_RX_CK", "Input clock"}, {69, 1, "DEV_FSIRX4_FSI_RX_LPBK_CK", "Input clock"}, {69, 2, "DEV_FSIRX4_FSI_RX_VBUS_CLK", "Input clock"}, {70, 0, "DEV_FSIRX5_FSI_RX_CK", "Input clock"}, {70, 1, "DEV_FSIRX5_FSI_RX_LPBK_CK", "Input clock"}, {70, 2, "DEV_FSIRX5_FSI_RX_VBUS_CLK", "Input clock"}, {71, 0, "DEV_FSITX0_FSI_TX_PLL_CLK", "Input clock"}, {71, 1, "DEV_FSITX0_FSI_TX_VBUS_CLK", "Input clock"}, {71, 2, "DEV_FSITX0_FSI_TX_CK", "Output clock"}, {72, 0, "DEV_FSITX1_FSI_TX_PLL_CLK", "Input clock"}, {72, 1, "DEV_FSITX1_FSI_TX_VBUS_CLK", "Input clock"}, {72, 2, "DEV_FSITX1_FSI_TX_CK", "Output clock"}, {74, 0, "DEV_FSS0_FSAS_0_GCLK", "Input clock"}, {75, 0, "DEV_FSS0_OSPI_0_OSPI_DQS_CLK", "Input clock"}, {75, 1, "DEV_FSS0_OSPI_0_OSPI_HCLK_CLK", "Input clock"}, {75, 2, "DEV_FSS0_OSPI_0_OSPI_ICLK_CLK", "Input muxed clock"}, {75, 3, "DEV_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI0_DQS_OUT", "Parent input clock option to DEV_FSS0_OSPI_0_OSPI_ICLK_CLK"}, {75, 4, "DEV_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI0_LBCLKO_OUT", "Parent input clock option to DEV_FSS0_OSPI_0_OSPI_ICLK_CLK"}, {75, 5, "DEV_FSS0_OSPI_0_OSPI_PCLK_CLK", "Input clock"}, {75, 6, "DEV_FSS0_OSPI_0_OSPI_RCLK_CLK", "Input muxed clock"}, {75, 7, "DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_FSS0_OSPI_0_OSPI_RCLK_CLK"}, {75, 8, "DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT5_CLK", "Parent input clock option to DEV_FSS0_OSPI_0_OSPI_RCLK_CLK"}, {75, 9, "DEV_FSS0_OSPI_0_OSPI_OCLK_CLK", "Output clock"}, {76, 0, "DEV_GICSS0_VCLK_CLK", "Input clock"}, {77, 0, "DEV_GPIO0_MMR_CLK", "Input clock"}, {78, 0, "DEV_GPIO1_MMR_CLK", "Input clock"}, {80, 0, "DEV_GPMC0_FUNC_CLK", "Input muxed clock"}, {80, 1, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_GPMC0_FUNC_CLK"}, {80, 2, "DEV_GPMC0_FUNC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK", "Parent input clock option to DEV_GPMC0_FUNC_CLK"}, {80, 3, "DEV_GPMC0_PI_GPMC_RET_CLK", "Input clock"}, {80, 4, "DEV_GPMC0_VBUSM_CLK", "Input clock"}, {80, 5, "DEV_GPMC0_PO_GPMC_DEV_CLK", "Output clock"}, {61, 0, "DEV_GTC0_GTC_CLK", "Input muxed clock"}, {61, 1, "DEV_GTC0_GTC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 2, "DEV_GTC0_GTC_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 3, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 4, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 5, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 6, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 7, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 8, "DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 9, "DEV_GTC0_VBUSP_CLK", "Input clock"}, {102, 0, "DEV_I2C0_CLK", "Input clock"}, {102, 1, "DEV_I2C0_PISCL", "Input clock"}, {102, 2, "DEV_I2C0_PISYS_CLK", "Input clock"}, {102, 3, "DEV_I2C0_PORSCL", "Output clock"}, {103, 0, "DEV_I2C1_CLK", "Input clock"}, {103, 1, "DEV_I2C1_PISCL", "Input clock"}, {103, 2, "DEV_I2C1_PISYS_CLK", "Input clock"}, {103, 3, "DEV_I2C1_PORSCL", "Output clock"}, {104, 0, "DEV_I2C2_CLK", "Input clock"}, {104, 1, "DEV_I2C2_PISCL", "Input clock"}, {104, 2, "DEV_I2C2_PISYS_CLK", "Input clock"}, {104, 3, "DEV_I2C2_PORSCL", "Output clock"}, {105, 0, "DEV_I2C3_CLK", "Input clock"}, {105, 1, "DEV_I2C3_PISCL", "Input clock"}, {105, 2, "DEV_I2C3_PISYS_CLK", "Input clock"}, {105, 3, "DEV_I2C3_PORSCL", "Output clock"}, {83, 0, "DEV_LED0_LED_CLK", "Input clock"}, {83, 1, "DEV_LED0_VBUSP_CLK", "Input clock"}, {3, 0, "DEV_MAIN_GPIOMUX_INTROUTER0_INTR_CLK", "Input clock"}, {98, 0, "DEV_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"}, {98, 1, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, {98, 2, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, {98, 3, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, {98, 4, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, {98, 5, "DEV_MCAN0_MCANSS_HCLK_CLK", "Input clock"}, {99, 0, "DEV_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"}, {99, 1, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, {99, 2, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, {99, 3, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, {99, 4, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, {99, 5, "DEV_MCAN1_MCANSS_HCLK_CLK", "Input clock"}, {141, 0, "DEV_MCSPI0_CLKSPIREF_CLK", "Input clock"}, {141, 1, "DEV_MCSPI0_IO_CLKSPII_CLK", "Input muxed clock"}, {141, 2, "DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI0_CLK_OUT", "Parent input clock option to DEV_MCSPI0_IO_CLKSPII_CLK"}, {141, 3, "DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MAIN_0_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI0_IO_CLKSPII_CLK"}, {141, 4, "DEV_MCSPI0_VBUSP_CLK", "Input clock"}, {141, 5, "DEV_MCSPI0_IO_CLKSPIO_CLK", "Output clock"}, {142, 0, "DEV_MCSPI1_CLKSPIREF_CLK", "Input clock"}, {142, 1, "DEV_MCSPI1_IO_CLKSPII_CLK", "Input muxed clock"}, {142, 2, "DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI1_CLK_OUT", "Parent input clock option to DEV_MCSPI1_IO_CLKSPII_CLK"}, {142, 3, "DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_1_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI1_IO_CLKSPII_CLK"}, {142, 4, "DEV_MCSPI1_VBUSP_CLK", "Input clock"}, {142, 5, "DEV_MCSPI1_IO_CLKSPIO_CLK", "Output clock"}, {143, 0, "DEV_MCSPI2_CLKSPIREF_CLK", "Input clock"}, {143, 1, "DEV_MCSPI2_IO_CLKSPII_CLK", "Input muxed clock"}, {143, 2, "DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI2_CLK_OUT", "Parent input clock option to DEV_MCSPI2_IO_CLKSPII_CLK"}, {143, 3, "DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_SPI_MAIN_2_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI2_IO_CLKSPII_CLK"}, {143, 4, "DEV_MCSPI2_VBUSP_CLK", "Input clock"}, {143, 5, "DEV_MCSPI2_IO_CLKSPIO_CLK", "Output clock"}, {144, 0, "DEV_MCSPI3_CLKSPIREF_CLK", "Input clock"}, {144, 1, "DEV_MCSPI3_IO_CLKSPII_CLK", "Input muxed clock"}, {144, 2, "DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI3_CLK_OUT", "Parent input clock option to DEV_MCSPI3_IO_CLKSPII_CLK"}, {144, 3, "DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI3_IO_CLKSPII_CLK"}, {144, 4, "DEV_MCSPI3_VBUSP_CLK", "Input clock"}, {144, 5, "DEV_MCSPI3_IO_CLKSPIO_CLK", "Output clock"}, {145, 0, "DEV_MCSPI4_CLKSPIREF_CLK", "Input clock"}, {145, 1, "DEV_MCSPI4_IO_CLKSPII_CLK", "Input muxed clock"}, {145, 2, "DEV_MCSPI4_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI4_CLK_OUT", "Parent input clock option to DEV_MCSPI4_IO_CLKSPII_CLK"}, {145, 3, "DEV_MCSPI4_IO_CLKSPII_CLK_PARENT_SPI_MAIN_4_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI4_IO_CLKSPII_CLK"}, {145, 4, "DEV_MCSPI4_VBUSP_CLK", "Input clock"}, {145, 5, "DEV_MCSPI4_IO_CLKSPIO_CLK", "Output clock"}, {23, 0, "DEV_MCU_DCC0_DCC_CLKSRC0_CLK", "Input clock"}, {23, 1, "DEV_MCU_DCC0_DCC_CLKSRC1_CLK", "Input clock"}, {23, 2, "DEV_MCU_DCC0_DCC_CLKSRC2_CLK", "Input clock"}, {23, 3, "DEV_MCU_DCC0_DCC_CLKSRC3_CLK", "Input clock"}, {23, 4, "DEV_MCU_DCC0_DCC_CLKSRC4_CLK", "Input clock"}, {23, 5, "DEV_MCU_DCC0_DCC_CLKSRC5_CLK", "Input clock"}, {23, 6, "DEV_MCU_DCC0_DCC_CLKSRC6_CLK", "Input clock"}, {23, 7, "DEV_MCU_DCC0_DCC_CLKSRC7_CLK", "Input clock"}, {23, 8, "DEV_MCU_DCC0_DCC_INPUT00_CLK", "Input clock"}, {23, 9, "DEV_MCU_DCC0_DCC_INPUT01_CLK", "Input clock"}, {23, 10, "DEV_MCU_DCC0_DCC_INPUT02_CLK", "Input clock"}, {23, 11, "DEV_MCU_DCC0_DCC_INPUT10_CLK", "Input clock"}, {23, 12, "DEV_MCU_DCC0_VBUS_CLK", "Input clock"}, {64, 0, "DEV_MCU_ESM0_CLK", "Input clock"}, {79, 0, "DEV_MCU_GPIO0_MMR_CLK", "Input clock"}, {106, 0, "DEV_MCU_I2C0_CLK", "Input clock"}, {106, 1, "DEV_MCU_I2C0_PISCL", "Input clock"}, {106, 2, "DEV_MCU_I2C0_PISYS_CLK", "Input clock"}, {106, 3, "DEV_MCU_I2C0_PORSCL", "Output clock"}, {107, 0, "DEV_MCU_I2C1_CLK", "Input clock"}, {107, 1, "DEV_MCU_I2C1_PISCL", "Input clock"}, {107, 2, "DEV_MCU_I2C1_PISYS_CLK", "Input clock"}, {107, 3, "DEV_MCU_I2C1_PORSCL", "Output clock"}, {9, 0, "DEV_MCU_M4FSS0_CORE0_DAP_CLK", "Input clock"}, {9, 1, "DEV_MCU_M4FSS0_CORE0_VBUS_CLK", "Input muxed clock"}, {9, 2, "DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_M4FSS0_CORE0_VBUS_CLK"}, {9, 3, "DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_M4FSS0_CORE0_VBUS_CLK"}, {100, 0, "DEV_MCU_MCRC64_0_CLK", "Input clock"}, {147, 0, "DEV_MCU_MCSPI0_CLKSPIREF_CLK", "Input clock"}, {147, 1, "DEV_MCU_MCSPI0_IO_CLKSPII_CLK", "Input muxed clock"}, {147, 2, "DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI0_CLK_OUT", "Parent input clock option to DEV_MCU_MCSPI0_IO_CLKSPII_CLK"}, {147, 3, "DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MCU_0_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCU_MCSPI0_IO_CLKSPII_CLK"}, {147, 4, "DEV_MCU_MCSPI0_VBUSP_CLK", "Input clock"}, {147, 5, "DEV_MCU_MCSPI0_IO_CLKSPIO_CLK", "Output clock"}, {148, 0, "DEV_MCU_MCSPI1_CLKSPIREF_CLK", "Input clock"}, {148, 1, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK", "Input muxed clock"}, {148, 2, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI1_CLK_OUT", "Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK"}, {148, 3, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MCU_1_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK"}, {148, 4, "DEV_MCU_MCSPI1_VBUSP_CLK", "Input clock"}, {148, 5, "DEV_MCU_MCSPI1_IO_CLKSPIO_CLK", "Output clock"}, {5, 0, "DEV_MCU_MCU_GPIOMUX_INTROUTER0_INTR_CLK", "Input clock"}, {140, 0, "DEV_MCU_PSC0_CLK", "Input clock"}, {140, 1, "DEV_MCU_PSC0_SLOW_CLK", "Input clock"}, {132, 0, "DEV_MCU_RTI0_RTI_CLK", "Input muxed clock"}, {132, 1, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, {132, 2, "DEV_MCU_RTI0_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, {132, 3, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, {132, 4, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, {132, 5, "DEV_MCU_RTI0_VBUSP_CLK", "Input clock"}, {35, 0, "DEV_MCU_TIMER0_TIMER_HCLK_CLK", "Input clock"}, {35, 1, "DEV_MCU_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"}, {35, 2, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 3, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 4, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 5, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 6, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 7, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 8, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 9, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 10, "DEV_MCU_TIMER0_TIMER_PWM", "Output clock"}, {48, 0, "DEV_MCU_TIMER1_TIMER_HCLK_CLK", "Input clock"}, {48, 1, "DEV_MCU_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"}, {48, 2, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, {48, 3, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, {48, 4, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, {48, 5, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, {48, 6, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, {48, 7, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, {48, 8, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, {48, 9, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, {48, 10, "DEV_MCU_TIMER1_TIMER_PWM", "Output clock"}, {49, 0, "DEV_MCU_TIMER2_TIMER_HCLK_CLK", "Input clock"}, {49, 1, "DEV_MCU_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"}, {49, 2, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {49, 3, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {49, 4, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {49, 5, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {49, 6, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {49, 7, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {49, 8, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {49, 9, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {49, 10, "DEV_MCU_TIMER2_TIMER_PWM", "Output clock"}, {50, 0, "DEV_MCU_TIMER3_TIMER_HCLK_CLK", "Input clock"}, {50, 1, "DEV_MCU_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"}, {50, 2, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, {50, 3, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, {50, 4, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, {50, 5, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, {50, 6, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, {50, 7, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, {50, 8, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, {50, 9, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, {50, 10, "DEV_MCU_TIMER3_TIMER_PWM", "Output clock"}, {149, 0, "DEV_MCU_UART0_FCLK_CLK", "Input clock"}, {149, 1, "DEV_MCU_UART0_VBUSP_CLK", "Input clock"}, {160, 0, "DEV_MCU_UART1_FCLK_CLK", "Input clock"}, {160, 1, "DEV_MCU_UART1_VBUSP_CLK", "Input clock"}, {57, 0, "DEV_MMCSD0_EMMCSS_VBUS_CLK", "Input clock"}, {57, 1, "DEV_MMCSD0_EMMCSS_XIN_CLK", "Input muxed clock"}, {57, 2, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"}, {57, 3, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"}, {58, 0, "DEV_MMCSD1_EMMCSDSS_IO_CLK_I", "Input muxed clock"}, {58, 1, "DEV_MMCSD1_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC1_CLKLB_OUT", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_IO_CLK_I"}, {58, 2, "DEV_MMCSD1_EMMCSDSS_IO_CLK_I_PARENT_EMMCSD4SS_MAIN_0_EMMCSDSS_IO_CLK_O", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_IO_CLK_I"}, {58, 3, "DEV_MMCSD1_EMMCSDSS_VBUS_CLK", "Input clock"}, {58, 4, "DEV_MMCSD1_EMMCSDSS_XIN_CLK", "Input muxed clock"}, {58, 5, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"}, {58, 6, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"}, {58, 7, "DEV_MMCSD1_EMMCSDSS_IO_CLK_O", "Output clock"}, {108, 0, "DEV_MSRAM_256K0_CCLK_CLK", "Input clock"}, {108, 1, "DEV_MSRAM_256K0_VCLK_CLK", "Input clock"}, {109, 0, "DEV_MSRAM_256K1_CCLK_CLK", "Input clock"}, {109, 1, "DEV_MSRAM_256K1_VCLK_CLK", "Input clock"}, {110, 0, "DEV_MSRAM_256K2_CCLK_CLK", "Input clock"}, {110, 1, "DEV_MSRAM_256K2_VCLK_CLK", "Input clock"}, {111, 0, "DEV_MSRAM_256K3_CCLK_CLK", "Input clock"}, {111, 1, "DEV_MSRAM_256K3_VCLK_CLK", "Input clock"}, {112, 0, "DEV_MSRAM_256K4_CCLK_CLK", "Input clock"}, {112, 1, "DEV_MSRAM_256K4_VCLK_CLK", "Input clock"}, {113, 0, "DEV_MSRAM_256K5_CCLK_CLK", "Input clock"}, {113, 1, "DEV_MSRAM_256K5_VCLK_CLK", "Input clock"}, {163, 0, "DEV_PBIST0_CLK8_CLK", "Input clock"}, {164, 0, "DEV_PBIST1_CLK8_CLK", "Input clock"}, {165, 0, "DEV_PBIST2_CLK8_CLK", "Input clock"}, {166, 0, "DEV_PBIST3_CLK8_CLK", "Input clock"}, {114, 0, "DEV_PCIE0_PCIE_CBA_CLK", "Input clock"}, {114, 1, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK", "Input muxed clock"}, {114, 2, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {114, 3, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {114, 4, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {114, 5, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {114, 6, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {114, 7, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {114, 8, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {114, 9, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {114, 10, "DEV_PCIE0_PCIE_LANE0_REFCLK", "Input clock"}, {114, 11, "DEV_PCIE0_PCIE_LANE0_RXCLK", "Input clock"}, {114, 12, "DEV_PCIE0_PCIE_LANE0_RXFCLK", "Input clock"}, {114, 13, "DEV_PCIE0_PCIE_LANE0_TXFCLK", "Input clock"}, {114, 14, "DEV_PCIE0_PCIE_LANE0_TXMCLK", "Input clock"}, {114, 15, "DEV_PCIE0_PCIE_PM_CLK", "Input clock"}, {114, 16, "DEV_PCIE0_PCIE_LANE0_TXCLK", "Output clock"}, {115, 0, "DEV_POSTDIV1_16FFT1_FREF_CLK", "Input clock"}, {115, 1, "DEV_POSTDIV1_16FFT1_POSTDIV_CLKIN_CLK", "Input clock"}, {115, 2, "DEV_POSTDIV1_16FFT1_HSDIVOUT5_CLK", "Output clock"}, {115, 3, "DEV_POSTDIV1_16FFT1_HSDIVOUT6_CLK", "Output clock"}, {116, 0, "DEV_POSTDIV4_16FF0_FREF_CLK", "Input clock"}, {116, 1, "DEV_POSTDIV4_16FF0_POSTDIV_CLKIN_CLK", "Input clock"}, {116, 2, "DEV_POSTDIV4_16FF0_HSDIVOUT5_CLK", "Output clock"}, {116, 3, "DEV_POSTDIV4_16FF0_HSDIVOUT6_CLK", "Output clock"}, {116, 4, "DEV_POSTDIV4_16FF0_HSDIVOUT7_CLK", "Output clock"}, {116, 5, "DEV_POSTDIV4_16FF0_HSDIVOUT8_CLK", "Output clock"}, {116, 6, "DEV_POSTDIV4_16FF0_HSDIVOUT9_CLK", "Output clock"}, {117, 0, "DEV_POSTDIV4_16FF2_FREF_CLK", "Input clock"}, {117, 1, "DEV_POSTDIV4_16FF2_POSTDIV_CLKIN_CLK", "Input clock"}, {117, 2, "DEV_POSTDIV4_16FF2_HSDIVOUT5_CLK", "Output clock"}, {117, 3, "DEV_POSTDIV4_16FF2_HSDIVOUT6_CLK", "Output clock"}, {117, 4, "DEV_POSTDIV4_16FF2_HSDIVOUT7_CLK", "Output clock"}, {117, 5, "DEV_POSTDIV4_16FF2_HSDIVOUT8_CLK", "Output clock"}, {117, 6, "DEV_POSTDIV4_16FF2_HSDIVOUT9_CLK", "Output clock"}, {81, 0, "DEV_PRU_ICSSG0_CORE_CLK", "Input muxed clock"}, {81, 1, "DEV_PRU_ICSSG0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_PRU_ICSSG0_CORE_CLK"}, {81, 2, "DEV_PRU_ICSSG0_CORE_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT9_CLK", "Parent input clock option to DEV_PRU_ICSSG0_CORE_CLK"}, {81, 3, "DEV_PRU_ICSSG0_IEP_CLK", "Input muxed clock"}, {81, 4, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, {81, 5, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, {81, 6, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, {81, 7, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, {81, 8, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, {81, 9, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, {81, 10, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, {81, 11, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, {81, 12, "DEV_PRU_ICSSG0_PR1_RGMII0_RXC_I", "Input clock"}, {81, 13, "DEV_PRU_ICSSG0_PR1_RGMII0_TXC_I", "Input clock"}, {81, 14, "DEV_PRU_ICSSG0_PR1_RGMII1_RXC_I", "Input clock"}, {81, 15, "DEV_PRU_ICSSG0_PR1_RGMII1_TXC_I", "Input clock"}, {81, 16, "DEV_PRU_ICSSG0_RGMII_MHZ_250_CLK", "Input clock"}, {81, 17, "DEV_PRU_ICSSG0_RGMII_MHZ_50_CLK", "Input clock"}, {81, 18, "DEV_PRU_ICSSG0_RGMII_MHZ_5_CLK", "Input clock"}, {81, 19, "DEV_PRU_ICSSG0_UCLK_CLK", "Input clock"}, {81, 20, "DEV_PRU_ICSSG0_VCLK_CLK", "Input clock"}, {81, 21, "DEV_PRU_ICSSG0_PR1_MDIO_MDCLK_O", "Output clock"}, {81, 22, "DEV_PRU_ICSSG0_PR1_RGMII0_TXC_O", "Output clock"}, {81, 23, "DEV_PRU_ICSSG0_PR1_RGMII1_TXC_O", "Output clock"}, {82, 0, "DEV_PRU_ICSSG1_CORE_CLK", "Input muxed clock"}, {82, 1, "DEV_PRU_ICSSG1_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_PRU_ICSSG1_CORE_CLK"}, {82, 2, "DEV_PRU_ICSSG1_CORE_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT9_CLK", "Parent input clock option to DEV_PRU_ICSSG1_CORE_CLK"}, {82, 3, "DEV_PRU_ICSSG1_IEP_CLK", "Input muxed clock"}, {82, 4, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, {82, 5, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, {82, 6, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, {82, 7, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, {82, 8, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, {82, 9, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, {82, 10, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, {82, 11, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, {82, 12, "DEV_PRU_ICSSG1_PR1_RGMII0_RXC_I", "Input clock"}, {82, 13, "DEV_PRU_ICSSG1_PR1_RGMII0_TXC_I", "Input clock"}, {82, 14, "DEV_PRU_ICSSG1_PR1_RGMII1_RXC_I", "Input clock"}, {82, 15, "DEV_PRU_ICSSG1_PR1_RGMII1_TXC_I", "Input clock"}, {82, 16, "DEV_PRU_ICSSG1_RGMII_MHZ_250_CLK", "Input clock"}, {82, 17, "DEV_PRU_ICSSG1_RGMII_MHZ_50_CLK", "Input clock"}, {82, 18, "DEV_PRU_ICSSG1_RGMII_MHZ_5_CLK", "Input clock"}, {82, 19, "DEV_PRU_ICSSG1_UCLK_CLK", "Input clock"}, {82, 20, "DEV_PRU_ICSSG1_VCLK_CLK", "Input clock"}, {82, 21, "DEV_PRU_ICSSG1_PR1_MDIO_MDCLK_O", "Output clock"}, {82, 22, "DEV_PRU_ICSSG1_PR1_RGMII0_TXC_O", "Output clock"}, {82, 23, "DEV_PRU_ICSSG1_PR1_RGMII1_TXC_O", "Output clock"}, {139, 0, "DEV_PSC0_CLK", "Input clock"}, {139, 1, "DEV_PSC0_SLOW_CLK", "Input clock"}, {118, 0, "DEV_PSRAMECC0_CLK_CLK", "Input clock"}, {121, 0, "DEV_R5FSS0_CORE0_CPU_CLK", "Input clock"}, {121, 1, "DEV_R5FSS0_CORE0_INTERFACE_CLK", "Input clock"}, {122, 0, "DEV_R5FSS0_CORE1_CPU_CLK", "Input clock"}, {122, 1, "DEV_R5FSS0_CORE1_INTERFACE_CLK", "Input clock"}, {123, 0, "DEV_R5FSS1_CORE0_CPU_CLK", "Input clock"}, {123, 1, "DEV_R5FSS1_CORE0_INTERFACE_CLK", "Input clock"}, {124, 0, "DEV_R5FSS1_CORE1_CPU_CLK", "Input clock"}, {124, 1, "DEV_R5FSS1_CORE1_INTERFACE_CLK", "Input clock"}, {125, 0, "DEV_RTI0_RTI_CLK", "Input muxed clock"}, {125, 1, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {125, 2, "DEV_RTI0_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {125, 3, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {125, 4, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {125, 5, "DEV_RTI0_VBUSP_CLK", "Input clock"}, {126, 0, "DEV_RTI1_RTI_CLK", "Input muxed clock"}, {126, 1, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {126, 2, "DEV_RTI1_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {126, 3, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {126, 4, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {126, 5, "DEV_RTI1_VBUSP_CLK", "Input clock"}, {130, 0, "DEV_RTI10_RTI_CLK", "Input muxed clock"}, {130, 1, "DEV_RTI10_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI10_RTI_CLK"}, {130, 2, "DEV_RTI10_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_RTI10_RTI_CLK"}, {130, 3, "DEV_RTI10_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI10_RTI_CLK"}, {130, 4, "DEV_RTI10_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_RTI10_RTI_CLK"}, {130, 5, "DEV_RTI10_VBUSP_CLK", "Input clock"}, {131, 0, "DEV_RTI11_RTI_CLK", "Input muxed clock"}, {131, 1, "DEV_RTI11_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI11_RTI_CLK"}, {131, 2, "DEV_RTI11_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_RTI11_RTI_CLK"}, {131, 3, "DEV_RTI11_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI11_RTI_CLK"}, {131, 4, "DEV_RTI11_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_RTI11_RTI_CLK"}, {131, 5, "DEV_RTI11_VBUSP_CLK", "Input clock"}, {127, 0, "DEV_RTI8_RTI_CLK", "Input muxed clock"}, {127, 1, "DEV_RTI8_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI8_RTI_CLK"}, {127, 2, "DEV_RTI8_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_RTI8_RTI_CLK"}, {127, 3, "DEV_RTI8_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI8_RTI_CLK"}, {127, 4, "DEV_RTI8_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_RTI8_RTI_CLK"}, {127, 5, "DEV_RTI8_VBUSP_CLK", "Input clock"}, {128, 0, "DEV_RTI9_RTI_CLK", "Input muxed clock"}, {128, 1, "DEV_RTI9_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI9_RTI_CLK"}, {128, 2, "DEV_RTI9_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_RTI9_RTI_CLK"}, {128, 3, "DEV_RTI9_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI9_RTI_CLK"}, {128, 4, "DEV_RTI9_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_RTI9_RTI_CLK"}, {128, 5, "DEV_RTI9_VBUSP_CLK", "Input clock"}, {133, 0, "DEV_SA2_UL0_PKA_IN_CLK", "Input clock"}, {133, 1, "DEV_SA2_UL0_X1_CLK", "Input clock"}, {133, 2, "DEV_SA2_UL0_X2_CLK", "Input clock"}, {162, 0, "DEV_SERDES_10G0_CLK", "Input clock"}, {162, 1, "DEV_SERDES_10G0_CORE_REF_CLK", "Input muxed clock"}, {162, 2, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"}, {162, 3, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"}, {162, 4, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"}, {162, 5, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"}, {162, 6, "DEV_SERDES_10G0_IP1_LN0_TXCLK", "Input clock"}, {162, 7, "DEV_SERDES_10G0_IP2_LN0_TXCLK", "Input clock"}, {162, 8, "DEV_SERDES_10G0_IP1_LN0_REFCLK", "Output clock"}, {162, 9, "DEV_SERDES_10G0_IP1_LN0_RXCLK", "Output clock"}, {162, 10, "DEV_SERDES_10G0_IP1_LN0_RXFCLK", "Output clock"}, {162, 11, "DEV_SERDES_10G0_IP1_LN0_TXFCLK", "Output clock"}, {162, 12, "DEV_SERDES_10G0_IP1_LN0_TXMCLK", "Output clock"}, {162, 13, "DEV_SERDES_10G0_IP2_LN0_REFCLK", "Output clock"}, {162, 14, "DEV_SERDES_10G0_IP2_LN0_RXCLK", "Output clock"}, {162, 15, "DEV_SERDES_10G0_IP2_LN0_RXFCLK", "Output clock"}, {162, 16, "DEV_SERDES_10G0_IP2_LN0_TXFCLK", "Output clock"}, {162, 17, "DEV_SERDES_10G0_IP2_LN0_TXMCLK", "Output clock"}, {162, 18, "DEV_SERDES_10G0_REF_OUT_CLK", "Output clock"}, {150, 0, "DEV_SPINLOCK0_VCLK_CLK", "Input clock"}, {15, 0, "DEV_STM0_ATB_CLK", "Input clock"}, {15, 1, "DEV_STM0_CORE_CLK", "Input clock"}, {15, 2, "DEV_STM0_VBUSP_CLK", "Input clock"}, {36, 0, "DEV_TIMER0_TIMER_HCLK_CLK", "Input clock"}, {36, 1, "DEV_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"}, {36, 2, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 3, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 4, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 5, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 6, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 7, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 8, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 9, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 10, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 11, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 12, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 13, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 14, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 15, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 16, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 17, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 18, "DEV_TIMER0_TIMER_PWM", "Output clock"}, {37, 0, "DEV_TIMER1_TIMER_HCLK_CLK", "Input clock"}, {37, 1, "DEV_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"}, {37, 2, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {37, 3, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {37, 4, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {37, 5, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {37, 6, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {37, 7, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {37, 8, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {37, 9, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {37, 10, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {37, 11, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {37, 12, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {37, 13, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {37, 14, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {37, 15, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {37, 16, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {37, 17, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {37, 18, "DEV_TIMER1_TIMER_PWM", "Output clock"}, {46, 0, "DEV_TIMER10_TIMER_HCLK_CLK", "Input clock"}, {46, 1, "DEV_TIMER10_TIMER_TCLK_CLK", "Input muxed clock"}, {46, 2, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {46, 3, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {46, 4, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {46, 5, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {46, 6, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {46, 7, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {46, 8, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {46, 9, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {46, 10, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {46, 11, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {46, 12, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {46, 13, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {46, 14, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {46, 15, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {46, 16, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {46, 17, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {46, 18, "DEV_TIMER10_TIMER_PWM", "Output clock"}, {47, 0, "DEV_TIMER11_TIMER_HCLK_CLK", "Input clock"}, {47, 1, "DEV_TIMER11_TIMER_TCLK_CLK", "Input muxed clock"}, {47, 2, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, {47, 3, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, {47, 4, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, {47, 5, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, {47, 6, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, {47, 7, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, {47, 8, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, {47, 9, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, {47, 10, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, {47, 11, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, {47, 12, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, {47, 13, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, {47, 14, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, {47, 15, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, {47, 16, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, {47, 17, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, {47, 18, "DEV_TIMER11_TIMER_PWM", "Output clock"}, {38, 0, "DEV_TIMER2_TIMER_HCLK_CLK", "Input clock"}, {38, 1, "DEV_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"}, {38, 2, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 3, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 4, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 5, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 6, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 7, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 8, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 9, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 10, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 11, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 12, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 13, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 14, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 15, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 16, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 17, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 18, "DEV_TIMER2_TIMER_PWM", "Output clock"}, {39, 0, "DEV_TIMER3_TIMER_HCLK_CLK", "Input clock"}, {39, 1, "DEV_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"}, {39, 2, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {39, 3, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {39, 4, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {39, 5, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {39, 6, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {39, 7, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {39, 8, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {39, 9, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {39, 10, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {39, 11, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {39, 12, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {39, 13, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {39, 14, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {39, 15, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {39, 16, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {39, 17, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {39, 18, "DEV_TIMER3_TIMER_PWM", "Output clock"}, {40, 0, "DEV_TIMER4_TIMER_HCLK_CLK", "Input clock"}, {40, 1, "DEV_TIMER4_TIMER_TCLK_CLK", "Input muxed clock"}, {40, 2, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 3, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 4, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 5, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 6, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 7, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 8, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 9, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 10, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 11, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 12, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 13, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 14, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 15, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 16, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 17, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 18, "DEV_TIMER4_TIMER_PWM", "Output clock"}, {41, 0, "DEV_TIMER5_TIMER_HCLK_CLK", "Input clock"}, {41, 1, "DEV_TIMER5_TIMER_TCLK_CLK", "Input muxed clock"}, {41, 2, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {41, 3, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {41, 4, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {41, 5, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {41, 6, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {41, 7, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {41, 8, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {41, 9, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {41, 10, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {41, 11, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {41, 12, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {41, 13, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {41, 14, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {41, 15, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {41, 16, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {41, 17, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {41, 18, "DEV_TIMER5_TIMER_PWM", "Output clock"}, {42, 0, "DEV_TIMER6_TIMER_HCLK_CLK", "Input clock"}, {42, 1, "DEV_TIMER6_TIMER_TCLK_CLK", "Input muxed clock"}, {42, 2, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 3, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 4, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 5, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 6, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 7, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 8, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 9, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 10, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 11, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 12, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 13, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 14, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 15, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 16, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 17, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 18, "DEV_TIMER6_TIMER_PWM", "Output clock"}, {43, 0, "DEV_TIMER7_TIMER_HCLK_CLK", "Input clock"}, {43, 1, "DEV_TIMER7_TIMER_TCLK_CLK", "Input muxed clock"}, {43, 2, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {43, 3, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {43, 4, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {43, 5, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {43, 6, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {43, 7, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {43, 8, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {43, 9, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {43, 10, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {43, 11, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {43, 12, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {43, 13, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {43, 14, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {43, 15, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {43, 16, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {43, 17, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {43, 18, "DEV_TIMER7_TIMER_PWM", "Output clock"}, {44, 0, "DEV_TIMER8_TIMER_HCLK_CLK", "Input clock"}, {44, 1, "DEV_TIMER8_TIMER_TCLK_CLK", "Input muxed clock"}, {44, 2, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {44, 3, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {44, 4, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {44, 5, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {44, 6, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {44, 7, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {44, 8, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {44, 9, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {44, 10, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {44, 11, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {44, 12, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {44, 13, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {44, 14, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {44, 15, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {44, 16, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {44, 17, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {44, 18, "DEV_TIMER8_TIMER_PWM", "Output clock"}, {45, 0, "DEV_TIMER9_TIMER_HCLK_CLK", "Input clock"}, {45, 1, "DEV_TIMER9_TIMER_TCLK_CLK", "Input muxed clock"}, {45, 2, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, {45, 3, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, {45, 4, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, {45, 5, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, {45, 6, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, {45, 7, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, {45, 8, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, {45, 9, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, {45, 10, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, {45, 11, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, {45, 12, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, {45, 13, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, {45, 14, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, {45, 15, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, {45, 16, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, {45, 17, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, {45, 18, "DEV_TIMER9_TIMER_PWM", "Output clock"}, {151, 0, "DEV_TIMERMGR0_VCLK_CLK", "Input clock"}, {6, 0, "DEV_TIMESYNC_EVENT_INTROUTER0_INTR_CLK", "Input clock"}, {146, 0, "DEV_UART0_FCLK_CLK", "Input muxed clock"}, {146, 1, "DEV_UART0_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT0", "Parent input clock option to DEV_UART0_FCLK_CLK"}, {146, 2, "DEV_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART0_FCLK_CLK"}, {146, 3, "DEV_UART0_VBUSP_CLK", "Input clock"}, {152, 0, "DEV_UART1_FCLK_CLK", "Input muxed clock"}, {152, 1, "DEV_UART1_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT1", "Parent input clock option to DEV_UART1_FCLK_CLK"}, {152, 2, "DEV_UART1_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART1_FCLK_CLK"}, {152, 3, "DEV_UART1_VBUSP_CLK", "Input clock"}, {153, 0, "DEV_UART2_FCLK_CLK", "Input muxed clock"}, {153, 1, "DEV_UART2_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT2", "Parent input clock option to DEV_UART2_FCLK_CLK"}, {153, 2, "DEV_UART2_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART2_FCLK_CLK"}, {153, 3, "DEV_UART2_VBUSP_CLK", "Input clock"}, {154, 0, "DEV_UART3_FCLK_CLK", "Input muxed clock"}, {154, 1, "DEV_UART3_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT3", "Parent input clock option to DEV_UART3_FCLK_CLK"}, {154, 2, "DEV_UART3_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART3_FCLK_CLK"}, {154, 3, "DEV_UART3_VBUSP_CLK", "Input clock"}, {155, 0, "DEV_UART4_FCLK_CLK", "Input muxed clock"}, {155, 1, "DEV_UART4_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT4", "Parent input clock option to DEV_UART4_FCLK_CLK"}, {155, 2, "DEV_UART4_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART4_FCLK_CLK"}, {155, 3, "DEV_UART4_VBUSP_CLK", "Input clock"}, {156, 0, "DEV_UART5_FCLK_CLK", "Input muxed clock"}, {156, 1, "DEV_UART5_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT5", "Parent input clock option to DEV_UART5_FCLK_CLK"}, {156, 2, "DEV_UART5_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART5_FCLK_CLK"}, {156, 3, "DEV_UART5_VBUSP_CLK", "Input clock"}, {158, 0, "DEV_UART6_FCLK_CLK", "Input muxed clock"}, {158, 1, "DEV_UART6_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT6", "Parent input clock option to DEV_UART6_FCLK_CLK"}, {158, 2, "DEV_UART6_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART6_FCLK_CLK"}, {158, 3, "DEV_UART6_VBUSP_CLK", "Input clock"}, {161, 0, "DEV_USB0_ACLK_CLK", "Input clock"}, {161, 1, "DEV_USB0_CLK_LPM_CLK", "Input clock"}, {161, 2, "DEV_USB0_PCLK_CLK", "Input clock"}, {161, 3, "DEV_USB0_PIPE_REFCLK", "Input clock"}, {161, 4, "DEV_USB0_PIPE_RXCLK", "Input clock"}, {161, 5, "DEV_USB0_PIPE_RXFCLK", "Input clock"}, {161, 6, "DEV_USB0_PIPE_TXFCLK", "Input clock"}, {161, 7, "DEV_USB0_PIPE_TXMCLK", "Input clock"}, {161, 8, "DEV_USB0_USB2_APB_PCLK_CLK", "Input clock"}, {161, 9, "DEV_USB0_USB2_REFCLOCK_CLK", "Input muxed clock"}, {161, 10, "DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK"}, {161, 11, "DEV_USB0_USB2_REFCLOCK_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK"}, {161, 12, "DEV_USB0_PIPE_TXCLK", "Output clock"}, {95, 0, "DEV_VTM0_FIX_REF2_CLK", "Input clock"}, {95, 1, "DEV_VTM0_FIX_REF_CLK", "Input clock"}, {95, 2, "DEV_VTM0_VBUSP_CLK", "Input clock"}, }; k3conf_0.3/soc/am64x/am64x_processors_info.h0000664000175000017500000000350614504336513015703 0ustar /* * AM64X Processor Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM64X_PROCESSOR_INFO_H #define __AM64X_PROCESSOR_INFO_H #define AM64X_MAX_PROCESSORS_IDS 7 extern struct ti_sci_processors_info am64x_processors_info[]; #endif /* __AM64X_PROCESSOR_INFO_H */ k3conf_0.3/soc/am64x/am64x_clocks_info.h0000664000175000017500000000345514504336513014762 0ustar /* * AM64X Clocks Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM64X_CLOCKS_INFO_H #define __AM64X_CLOCKS_INFO_H #define AM64X_MAX_CLOCKS 950 extern struct ti_sci_clocks_info am64x_clocks_info[]; #endif /* __AM64X_CLOCKS_INFO_H */ k3conf_0.3/soc/am64x/am64x_processors_info.c0000664000175000017500000000371414375734376015716 0ustar /* * AM64X Processor Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_processors_info am64x_processors_info[] = { {135, 0, 0x20, "A53SS0_CORE_0"}, {136, 0, 0x21, "A53SS0_CORE_1"}, {9, 0, 0x18, "MCU_M4FSS0_CORE0"}, {121, 0, 0x01, "R5FSS0_CORE0"}, {122, 0, 0x02, "R5FSS0_CORE1"}, {123, 0, 0x06, "R5FSS1_CORE0"}, {124, 0, 0x07, "R5FSS1_CORE1"}, }; k3conf_0.3/soc/am64x/am64x_sec_proxy_info.c0000664000175000017500000000570514375734376015531 0ustar /* * AM64X Sec Proxy Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_sec_proxy_info am64x_main_sp_info[] = { {0, "read", 11, "MAIN_0_R5_0", "response"}, {1, "write", 10, "MAIN_0_R5_0", "low_priority"}, {2, "read", 11, "MAIN_0_R5_1", "response"}, {3, "write", 10, "MAIN_0_R5_1", "low_priority"}, {4, "read", 2, "MAIN_0_R5_2", "response"}, {5, "write", 1, "MAIN_0_R5_2", "low_priority"}, {6, "read", 2, "MAIN_0_R5_3", "response"}, {7, "write", 1, "MAIN_0_R5_3", "low_priority"}, {8, "read", 11, "A53_0", "response"}, {9, "write", 10, "A53_0", "low_priority"}, {10, "read", 6, "A53_1", "response"}, {11, "write", 5, "A53_1", "low_priority"}, {12, "read", 6, "A53_2", "response"}, {13, "write", 5, "A53_2", "low_priority"}, {14, "read", 6, "A53_3", "response"}, {15, "write", 5, "A53_3", "low_priority"}, {16, "read", 6, "M4_0", "response"}, {17, "write", 5, "M4_0", "low_priority"}, {18, "read", 6, "MAIN_1_R5_0", "response"}, {19, "write", 5, "MAIN_1_R5_0", "low_priority"}, {20, "read", 6, "MAIN_1_R5_1", "response"}, {21, "write", 5, "MAIN_1_R5_1", "low_priority"}, {22, "read", 2, "MAIN_1_R5_2", "response"}, {23, "write", 1, "MAIN_1_R5_2", "low_priority"}, {24, "read", 2, "MAIN_1_R5_3", "response"}, {25, "write", 1, "MAIN_1_R5_3", "low_priority"}, {26, "read", 2, "ICSSG_0", "response"}, {27, "write", 1, "ICSSG_0", "low_priority"}, }; k3conf_0.3/soc/am64x/am64x_devices_info.h0000664000175000017500000000346414504336513015126 0ustar /* * AM64X Devices Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM64X_DEVICES_INFO_H #define __AM64X_DEVICES_INFO_H #define AM64X_MAX_DEVICES 159 extern struct ti_sci_devices_info am64x_devices_info[]; #endif /* __AM64X_DEVICES_INFO_H */ k3conf_0.3/soc/am64x/am64x_host_info.c0000664000175000017500000000540114375734376014464 0ustar /* * AM64X Hosts Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_host_info am64x_host_info[] = { {0, "DMSC", "Secure", "Device Management and Security Control"}, {35, "MAIN_0_R5_0", "Secure", "Cortex R5_0 context 0 on Main island(BOOT)"}, {36, "MAIN_0_R5_1", "Non Secure", "Cortex R5_0 context 1 on Main island"}, {37, "MAIN_0_R5_2", "Secure", "Cortex R5_0 context 2 on Main island"}, {38, "MAIN_0_R5_3", "Non Secure", "Cortex R5_0 context 3 on Main island"}, {10, "A53_0", "Secure", "Cortex a53 context 0 on Main islana - ATF"}, {11, "A53_1", "Non Secure", "Cortex A53 context 1 on Main island - EL2/Hyp"}, {12, "A53_2", "Non Secure", "Cortex A53 context 2 on Main island - VM/OS1"}, {13, "A53_3", "Non Secure", "Cortex A53 context 3 on Main island - VM2/OS2"}, {30, "M4_0", "Non Secure", "M4"}, {40, "MAIN_1_R5_0", "Secure", "Cortex R5_1 context 0 on Main island"}, {41, "MAIN_1_R5_1", "Non Secure", "Cortex R5_1 context 1 on Main island"}, {42, "MAIN_1_R5_2", "Secure", "Cortex R5_1 context 2 on Main island"}, {43, "MAIN_1_R5_3", "Non Secure", "Cortex R5_1 context 3 on Main island"}, {50, "ICSSG_0", "Non Secure", "ICSSG context 0 on Main island"}, }; k3conf_0.3/soc/am65x_sr2/0000775000175000017500000000000014504336513012061 5ustar k3conf_0.3/soc/am65x_sr2/am65x_sr2_rm_info.h0000664000175000017500000000345114504336513015474 0ustar /* * AM65X_SR2 RM Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM65X_SR2_RM_INFO_H #define __AM65X_SR2_RM_INFO_H #define AM65X_SR2_MAX_RES 52 extern struct ti_sci_rm_info am65x_sr2_rm_info[]; #endif /* __AM65X_SR2_RM_INFO_H */ k3conf_0.3/soc/am65x_sr2/am65x_sr2_host_info.h0000664000175000017500000000465514504336513016042 0ustar /* * AM65X_SR2 Host Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM65X_SR2_HOST_INFO_H #define __AM65X_SR2_HOST_INFO_H #define AM65X_SR2_HOST_ID_DMSC 0 #define AM65X_SR2_HOST_ID_R5_0 3 #define AM65X_SR2_HOST_ID_R5_1 4 #define AM65X_SR2_HOST_ID_R5_2 5 #define AM65X_SR2_HOST_ID_R5_3 6 #define AM65X_SR2_HOST_ID_A53_0 10 #define AM65X_SR2_HOST_ID_A53_1 11 #define AM65X_SR2_HOST_ID_A53_2 12 #define AM65X_SR2_HOST_ID_A53_3 13 #define AM65X_SR2_HOST_ID_A53_4 14 #define AM65X_SR2_HOST_ID_A53_5 15 #define AM65X_SR2_HOST_ID_A53_6 16 #define AM65X_SR2_HOST_ID_A53_7 17 #define AM65X_SR2_HOST_ID_GPU_0 30 #define AM65X_SR2_HOST_ID_GPU_1 31 #define AM65X_SR2_HOST_ID_ICSSG_0 50 #define AM65X_SR2_HOST_ID_ICSSG_1 51 #define AM65X_SR2_HOST_ID_ICSSG_2 52 #define AM65X_SR2_MAX_HOST_IDS 18 extern struct ti_sci_host_info am65x_sr2_host_info[]; #endif /* __AM65X_SR2_HOST_INFO_H */ k3conf_0.3/soc/am65x_sr2/am65x_sr2_processors_info.h0000664000175000017500000000353614504336513017264 0ustar /* * AM65X_SR2 Processor Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM65X_SR2_PROCESSOR_INFO_H #define __AM65X_SR2_PROCESSOR_INFO_H #define AM65X_SR2_MAX_PROCESSORS_IDS 6 extern struct ti_sci_processors_info am65x_sr2_processors_info[]; #endif /* __AM65X_SR2_PROCESSOR_INFO_H */ k3conf_0.3/soc/am65x_sr2/am65x_sr2_host_info.c0000664000175000017500000000560214375734376016045 0ustar /* * AM65X_SR2 Hosts Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_host_info am65x_sr2_host_info[] = { {0, "DMSC", "Secure", "Device Management and Security Control"}, {3, "R5_0", "Non Secure", "Cortex R5 Context 0 on MCU island"}, {4, "R5_1", "Secure", "Cortex R5 Context 1 on MCU island(Boot)"}, {5, "R5_2", "Non Secure", "Cortex R5 Context 2 on MCU island"}, {6, "R5_3", "Secure", "Cortex R5 Context 3 on MCU island"}, {10, "A53_0", "Secure", "Cortex A53 context 0 on Main island"}, {11, "A53_1", "Secure", "Cortex A53 context 1 on Main island"}, {12, "A53_2", "Non Secure", "Cortex A53 context 2 on Main island"}, {13, "A53_3", "Non Secure", "Cortex A53 context 3 on Main island"}, {14, "A53_4", "Non Secure", "Cortex A53 context 4 on Main island"}, {15, "A53_5", "Non Secure", "Cortex A53 context 5 on Main island"}, {16, "A53_6", "Non Secure", "Cortex A53 context 6 on Main island"}, {17, "A53_7", "Non Secure", "Cortex A53 context 7 on Main island"}, {30, "GPU_0", "Non Secure", "SGX544 Context 0 on Main island"}, {31, "GPU_1", "Non Secure", "SGX544 Context 1 on Main island"}, {50, "ICSSG_0", "Non Secure", "ICSS Context 0 on Main island"}, {51, "ICSSG_1", "Non Secure", "ICSS Context 1 on Main island"}, {52, "ICSSG_2", "Non Secure", "ICSS Context 2 on Main island"}, }; k3conf_0.3/soc/am65x_sr2/am65x_sr2_sec_proxy_info.c0000664000175000017500000001236614375734376017110 0ustar /* * AM65X_SR2 Sec Proxy Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_sec_proxy_info am65x_sr2_main_sp_info[] = { {0, "read", 2, "A53_0", "notify"}, {1, "read", 30, "A53_0", "response"}, {2, "write", 10, "A53_0", "high_priority"}, {3, "write", 20, "A53_0", "low_priority"}, {4, "write", 2, "A53_0", "notify_resp"}, {5, "read", 2, "A53_1", "notify"}, {6, "read", 30, "A53_1", "response"}, {7, "write", 10, "A53_1", "high_priority"}, {8, "write", 20, "A53_1", "low_priority"}, {9, "write", 2, "A53_1", "notify_resp"}, {10, "read", 2, "A53_2", "notify"}, {11, "read", 22, "A53_2", "response"}, {12, "write", 2, "A53_2", "high_priority"}, {13, "write", 20, "A53_2", "low_priority"}, {14, "write", 2, "A53_2", "notify_resp"}, {15, "read", 2, "A53_3", "notify"}, {16, "read", 7, "A53_3", "response"}, {17, "write", 2, "A53_3", "high_priority"}, {18, "write", 5, "A53_3", "low_priority"}, {19, "write", 2, "A53_3", "notify_resp"}, {20, "read", 2, "A53_4", "notify"}, {21, "read", 5, "A53_4", "response"}, {22, "write", 2, "A53_4", "high_priority"}, {23, "write", 5, "A53_4", "low_priority"}, {24, "write", 2, "A53_4", "notify_resp"}, {25, "read", 2, "A53_5", "notify"}, {26, "read", 5, "A53_5", "response"}, {27, "write", 2, "A53_5", "high_priority"}, {28, "write", 5, "A53_5", "low_priority"}, {29, "write", 2, "A53_5", "notify_resp"}, {30, "read", 2, "A53_6", "notify"}, {31, "read", 5, "A53_6", "response"}, {32, "write", 2, "A53_6", "high_priority"}, {33, "write", 5, "A53_6", "low_priority"}, {34, "write", 2, "A53_6", "notify_resp"}, {35, "read", 2, "A53_7", "notify"}, {36, "read", 5, "A53_7", "response"}, {37, "write", 2, "A53_7", "high_priority"}, {38, "write", 5, "A53_7", "low_priority"}, {39, "write", 2, "A53_7", "notify_resp"}, {40, "read", 2, "ICSSG_0", "notify"}, {41, "read", 7, "ICSSG_0", "response"}, {42, "write", 2, "ICSSG_0", "high_priority"}, {43, "write", 5, "ICSSG_0", "low_priority"}, {44, "write", 2, "ICSSG_0", "notify_resp"}, {45, "read", 2, "ICSSG_1", "notify"}, {46, "read", 4, "ICSSG_1", "response"}, {47, "write", 2, "ICSSG_1", "high_priority"}, {48, "write", 2, "ICSSG_1", "low_priority"}, {49, "write", 2, "ICSSG_1", "notify_resp"}, {50, "read", 2, "ICSSG_2", "notify"}, {51, "read", 4, "ICSSG_2", "response"}, {52, "write", 2, "ICSSG_2", "high_priority"}, {53, "write", 2, "ICSSG_2", "low_priority"}, {54, "write", 2, "ICSSG_2", "notify_resp"}, {55, "read", 2, "GPU_0", "notify"}, {56, "read", 7, "GPU_0", "response"}, {57, "write", 2, "GPU_0", "high_priority"}, {58, "write", 5, "GPU_0", "low_priority"}, {59, "write", 2, "GPU_0", "notify_resp"}, {60, "read", 2, "GPU_1", "notify"}, {61, "read", 5, "GPU_1", "response"}, {62, "write", 2, "GPU_1", "high_priority"}, {63, "write", 3, "GPU_1", "low_priority"}, {64, "write", 2, "GPU_1", "notify_resp"}, }; struct ti_sci_sec_proxy_info am65x_sr2_mcu_sp_info[] = { {0, "read", 2, "R5_0", "notify"}, {1, "read", 20, "R5_0", "response"}, {2, "write", 10, "R5_0", "high_priority"}, {3, "write", 10, "R5_0", "low_priority"}, {4, "write", 2, "R5_0", "notify_resp"}, {5, "read", 2, "R5_1", "notify"}, {6, "read", 20, "R5_1", "response"}, {7, "write", 10, "R5_1", "high_priority"}, {8, "write", 10, "R5_1", "low_priority"}, {9, "write", 2, "R5_1", "notify_resp"}, {10, "read", 1, "R5_2", "notify"}, {11, "read", 2, "R5_2", "response"}, {12, "write", 1, "R5_2", "high_priority"}, {13, "write", 1, "R5_2", "low_priority"}, {14, "write", 1, "R5_2", "notify_resp"}, {15, "read", 1, "R5_3", "notify"}, {16, "read", 2, "R5_3", "response"}, {17, "write", 1, "R5_3", "high_priority"}, {18, "write", 1, "R5_3", "low_priority"}, {19, "write", 1, "R5_3", "notify_resp"}, }; k3conf_0.3/soc/am65x_sr2/am65x_sr2_devices_info.h0000664000175000017500000000351414504336513016500 0ustar /* * AM65X_SR2 Devices Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM65X_SR2_DEVICES_INFO_H #define __AM65X_SR2_DEVICES_INFO_H #define AM65X_SR2_MAX_DEVICES 244 extern struct ti_sci_devices_info am65x_sr2_devices_info[]; #endif /* __AM65X_SR2_DEVICES_INFO_H */ k3conf_0.3/soc/am65x_sr2/am65x_sr2_sec_proxy_info.h0000664000175000017500000000371014504336513017067 0ustar /* * AM65X_SR2 Sec Proxy Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM65X_SR2_SEC_PROXY_INFO_H #define __AM65X_SR2_SEC_PROXY_INFO_H #define AM65X_SR2_MAIN_SEC_PROXY_THREADS 65 #define AM65X_SR2_MCU_SEC_PROXY_THREADS 20 extern struct ti_sci_sec_proxy_info am65x_sr2_main_sp_info[]; extern struct ti_sci_sec_proxy_info am65x_sr2_mcu_sp_info[]; #endif /* __AM65X_SR2_SEC_PROXY_INFO_H */ k3conf_0.3/soc/am65x_sr2/am65x_sr2_devices_info.c0000664000175000017500000002317114375734376016513 0ustar /* * AM65X_SR2 Devices Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_devices_info am65x_sr2_devices_info[] = { {0, "AM6_DEV_MCU_ADC0"}, {1, "AM6_DEV_MCU_ADC1"}, {2, "AM6_DEV_CAL0"}, {3, "AM6_DEV_CMPEVENT_INTRTR0"}, {5, "AM6_DEV_MCU_CPSW0"}, {6, "AM6_DEV_CPT2_AGGR0"}, {7, "AM6_DEV_MCU_CPT2_AGGR0"}, {8, "AM6_DEV_STM0"}, {9, "AM6_DEV_DCC0"}, {10, "AM6_DEV_DCC1"}, {11, "AM6_DEV_DCC2"}, {12, "AM6_DEV_DCC3"}, {13, "AM6_DEV_DCC4"}, {14, "AM6_DEV_DCC5"}, {15, "AM6_DEV_DCC6"}, {16, "AM6_DEV_DCC7"}, {17, "AM6_DEV_MCU_DCC0"}, {18, "AM6_DEV_MCU_DCC1"}, {19, "AM6_DEV_MCU_DCC2"}, {20, "AM6_DEV_DDRSS0"}, {21, "AM6_DEV_DEBUGSS_WRAP0"}, {22, "AM6_DEV_WKUP_DMSC0"}, {23, "AM6_DEV_TIMER0"}, {24, "AM6_DEV_TIMER1"}, {25, "AM6_DEV_TIMER10"}, {26, "AM6_DEV_TIMER11"}, {27, "AM6_DEV_TIMER2"}, {28, "AM6_DEV_TIMER3"}, {29, "AM6_DEV_TIMER4"}, {30, "AM6_DEV_TIMER5"}, {31, "AM6_DEV_TIMER6"}, {32, "AM6_DEV_TIMER7"}, {33, "AM6_DEV_TIMER8"}, {34, "AM6_DEV_TIMER9"}, {35, "AM6_DEV_MCU_TIMER0"}, {36, "AM6_DEV_MCU_TIMER1"}, {37, "AM6_DEV_MCU_TIMER2"}, {38, "AM6_DEV_MCU_TIMER3"}, {39, "AM6_DEV_ECAP0"}, {40, "AM6_DEV_EHRPWM0"}, {41, "AM6_DEV_EHRPWM1"}, {42, "AM6_DEV_EHRPWM2"}, {43, "AM6_DEV_EHRPWM3"}, {44, "AM6_DEV_EHRPWM4"}, {45, "AM6_DEV_EHRPWM5"}, {46, "AM6_DEV_ELM0"}, {47, "AM6_DEV_MMCSD0"}, {48, "AM6_DEV_MMCSD1"}, {49, "AM6_DEV_EQEP0"}, {50, "AM6_DEV_EQEP1"}, {51, "AM6_DEV_EQEP2"}, {52, "AM6_DEV_ESM0"}, {53, "AM6_DEV_MCU_ESM0"}, {54, "AM6_DEV_WKUP_ESM0"}, {55, "AM6_DEV_FSS_MCU_0"}, {56, "AM6_DEV_GIC0"}, {57, "AM6_DEV_GPIO0"}, {58, "AM6_DEV_GPIO1"}, {59, "AM6_DEV_WKUP_GPIO0"}, {60, "AM6_DEV_GPMC0"}, {61, "AM6_DEV_GTC0"}, {62, "AM6_DEV_PRU_ICSSG0"}, {63, "AM6_DEV_PRU_ICSSG1"}, {64, "AM6_DEV_PRU_ICSSG2"}, {65, "AM6_DEV_GPU0"}, {66, "AM6_DEV_CCDEBUGSS0"}, {67, "AM6_DEV_DSS0"}, {68, "AM6_DEV_DEBUGSS0"}, {69, "AM6_DEV_EFUSE0"}, {70, "AM6_DEV_PSC0"}, {71, "AM6_DEV_MCU_DEBUGSS0"}, {72, "AM6_DEV_MCU_EFUSE0"}, {73, "AM6_DEV_PBIST0"}, {74, "AM6_DEV_PBIST1"}, {75, "AM6_DEV_MCU_PBIST0"}, {76, "AM6_DEV_PLLCTRL0"}, {77, "AM6_DEV_WKUP_PLLCTRL0"}, {78, "AM6_DEV_MCU_ROM0"}, {79, "AM6_DEV_WKUP_PSC0"}, {80, "AM6_DEV_WKUP_VTM0"}, {81, "AM6_DEV_DEBUGSUSPENDRTR0"}, {82, "AM6_DEV_CBASS0"}, {83, "AM6_DEV_CBASS_DEBUG0"}, {84, "AM6_DEV_CBASS_FW0"}, {85, "AM6_DEV_CBASS_INFRA0"}, {86, "AM6_DEV_ECC_AGGR0"}, {87, "AM6_DEV_ECC_AGGR1"}, {88, "AM6_DEV_ECC_AGGR2"}, {89, "AM6_DEV_MCU_CBASS0"}, {90, "AM6_DEV_MCU_CBASS_DEBUG0"}, {91, "AM6_DEV_MCU_CBASS_FW0"}, {92, "AM6_DEV_MCU_ECC_AGGR0"}, {93, "AM6_DEV_MCU_ECC_AGGR1"}, {94, "AM6_DEV_WKUP_CBASS0"}, {95, "AM6_DEV_WKUP_ECC_AGGR0"}, {96, "AM6_DEV_WKUP_CBASS_FW0"}, {97, "AM6_DEV_MAIN2MCU_LVL_INTRTR0"}, {98, "AM6_DEV_MAIN2MCU_PLS_INTRTR0"}, {99, "AM6_DEV_CTRL_MMR0"}, {100, "AM6_DEV_GPIOMUX_INTRTR0"}, {101, "AM6_DEV_PLL_MMR0"}, {102, "AM6_DEV_MCU_MCAN0"}, {103, "AM6_DEV_MCU_MCAN1"}, {104, "AM6_DEV_MCASP0"}, {105, "AM6_DEV_MCASP1"}, {106, "AM6_DEV_MCASP2"}, {107, "AM6_DEV_MCU_CTRL_MMR0"}, {108, "AM6_DEV_MCU_PLL_MMR0"}, {109, "AM6_DEV_MCU_SEC_MMR0"}, {110, "AM6_DEV_I2C0"}, {111, "AM6_DEV_I2C1"}, {112, "AM6_DEV_I2C2"}, {113, "AM6_DEV_I2C3"}, {114, "AM6_DEV_MCU_I2C0"}, {115, "AM6_DEV_WKUP_I2C0"}, {116, "AM6_DEV_MCU_MSRAM0"}, {117, "AM6_DEV_DFTSS0"}, {118, "AM6_DEV_NAVSS0"}, {119, "AM6_DEV_MCU_NAVSS0"}, {120, "AM6_DEV_PCIE0"}, {121, "AM6_DEV_PCIE1"}, {122, "AM6_DEV_PDMA_DEBUG0"}, {123, "AM6_DEV_PDMA0"}, {124, "AM6_DEV_PDMA1"}, {125, "AM6_DEV_MCU_PDMA0"}, {126, "AM6_DEV_MCU_PDMA1"}, {127, "AM6_DEV_MCU_PSRAM0"}, {128, "AM6_DEV_PSRAMECC0"}, {129, "AM6_DEV_MCU_ARMSS0"}, {130, "AM6_DEV_RTI0"}, {131, "AM6_DEV_RTI1"}, {132, "AM6_DEV_RTI2"}, {133, "AM6_DEV_RTI3"}, {134, "AM6_DEV_MCU_RTI0"}, {135, "AM6_DEV_MCU_RTI1"}, {136, "AM6_DEV_SA2_UL0"}, {137, "AM6_DEV_MCSPI0"}, {138, "AM6_DEV_MCSPI1"}, {139, "AM6_DEV_MCSPI2"}, {140, "AM6_DEV_MCSPI3"}, {141, "AM6_DEV_MCSPI4"}, {142, "AM6_DEV_MCU_MCSPI0"}, {143, "AM6_DEV_MCU_MCSPI1"}, {144, "AM6_DEV_MCU_MCSPI2"}, {145, "AM6_DEV_TIMESYNC_INTRTR0"}, {146, "AM6_DEV_UART0"}, {147, "AM6_DEV_UART1"}, {148, "AM6_DEV_UART2"}, {149, "AM6_DEV_MCU_UART0"}, {150, "AM6_DEV_WKUP_UART0"}, {151, "AM6_DEV_USB3SS0"}, {152, "AM6_DEV_USB3SS1"}, {153, "AM6_DEV_SERDES0"}, {154, "AM6_DEV_SERDES1"}, {155, "AM6_DEV_WKUP_CTRL_MMR0"}, {156, "AM6_DEV_WKUP_GPIOMUX_INTRTR0"}, {157, "AM6_DEV_BOARD0"}, {159, "AM6_DEV_MCU_ARMSS0_CPU0"}, {161, "AM6_DEV_WKUP_DMSC0_CORTEX_M3_0"}, {163, "AM6_DEV_NAVSS0_CPTS0"}, {164, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER0"}, {165, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER1"}, {166, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER2"}, {167, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER3"}, {168, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER4"}, {169, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER5"}, {170, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER6"}, {171, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER7"}, {172, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER8"}, {173, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER9"}, {174, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER10"}, {175, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER11"}, {176, "AM6_DEV_NAVSS0_MCRC0"}, {177, "AM6_DEV_NAVSS0_PVU0"}, {178, "AM6_DEV_NAVSS0_PVU1"}, {179, "AM6_DEV_NAVSS0_UDMASS_INTA0"}, {180, "AM6_DEV_NAVSS0_MODSS_INTA0"}, {181, "AM6_DEV_NAVSS0_MODSS_INTA1"}, {182, "AM6_DEV_NAVSS0_INTR_ROUTER_0"}, {183, "AM6_DEV_NAVSS0_TIMER_MGR0"}, {184, "AM6_DEV_NAVSS0_TIMER_MGR1"}, {185, "AM6_DEV_NAVSS0_PROXY0"}, {187, "AM6_DEV_NAVSS0_RINGACC0"}, {188, "AM6_DEV_NAVSS0_UDMAP0"}, {189, "AM6_DEV_MCU_NAVSS0_INTR_AGGR_0"}, {190, "AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0"}, {191, "AM6_DEV_MCU_NAVSS0_PROXY0"}, {193, "AM6_DEV_MCU_NAVSS0_MCRC0"}, {194, "AM6_DEV_MCU_NAVSS0_UDMAP0"}, {195, "AM6_DEV_MCU_NAVSS0_RINGACC0"}, {196, "AM6_DEV_COMPUTE_CLUSTER_MSMC0"}, {197, "AM6_DEV_COMPUTE_CLUSTER_PBIST0"}, {198, "AM6_DEV_COMPUTE_CLUSTER_CPAC0"}, {199, "AM6_DEV_COMPUTE_CLUSTER_CPAC_PBIST0"}, {200, "AM6_DEV_COMPUTE_CLUSTER_CPAC1"}, {201, "AM6_DEV_COMPUTE_CLUSTER_CPAC_PBIST1"}, {202, "AM6_DEV_COMPUTE_CLUSTER_A53_0"}, {203, "AM6_DEV_COMPUTE_CLUSTER_A53_1"}, {204, "AM6_DEV_COMPUTE_CLUSTER_A53_2"}, {205, "AM6_DEV_COMPUTE_CLUSTER_A53_3"}, {206, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4"}, {207, "AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3"}, {208, "AM6_DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0"}, {209, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3"}, {210, "AM6_DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1"}, {211, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5"}, {212, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6"}, {213, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0"}, {214, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2"}, {215, "AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2"}, {216, "AM6_DEV_OLDI_TX_CORE_MAIN_0"}, {217, "AM6_DEV_K3_ARM_ATB_FUNNEL_3_32_MCU_0"}, {218, "AM6_DEV_ICEMELTER_WKUP_0"}, {219, "AM6_DEV_K3_LED_MAIN_0"}, {220, "AM6_DEV_VDC_DATA_VBUSM_32B_REF_WKUP2MCU"}, {221, "AM6_DEV_VDC_DATA_VBUSM_32B_REF_MCU2WKUP"}, {222, "AM6_DEV_VDC_DATA_VBUSM_64B_REF_MAIN2MCU"}, {223, "AM6_DEV_VDC_DATA_VBUSM_64B_REF_MCU2MAIN"}, {224, "AM6_DEV_VDC_DMSC_DBG_VBUSP_32B_REF_DBG2DMSC"}, {225, "AM6_DEV_VDC_INFRA_VBUSP_32B_REF_WKUP2MAIN_INFRA"}, {226, "AM6_DEV_VDC_INFRA_VBUSP_32B_REF_MCU2MAIN_INFRA"}, {227, "AM6_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWWKUP2MCU"}, {228, "AM6_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWMCU2MAIN"}, {229, "AM6_DEV_VDC_MCU_DBG_VBUSP_32B_REF_DBGMAIN2MCU"}, {230, "AM6_DEV_VDC_NAV_PSIL_128B_REF_MAIN2MCU"}, {231, "AM6_DEV_GS80PRG_SOC_WRAP_WKUP_0"}, {232, "AM6_DEV_GS80PRG_MCU_WRAP_WKUP_0"}, {233, "AM6_DEV_MX_WAKEUP_RESET_SYNC_WKUP_0"}, {234, "AM6_DEV_MX_EFUSE_MAIN_CHAIN_MAIN_0"}, {235, "AM6_DEV_MX_EFUSE_MCU_CHAIN_MCU_0"}, {236, "AM6_DEV_DUMMY_IP_LPSC_WKUP2MCU_VD"}, {237, "AM6_DEV_DUMMY_IP_LPSC_WKUP2MAIN_INFRA_VD"}, {238, "AM6_DEV_DUMMY_IP_LPSC_DEBUG2DMSC_VD"}, {239, "AM6_DEV_DUMMY_IP_LPSC_DMSC_VD"}, {240, "AM6_DEV_DUMMY_IP_LPSC_MCU2MAIN_INFRA_VD"}, {241, "AM6_DEV_DUMMY_IP_LPSC_MCU2MAIN_VD"}, {242, "AM6_DEV_DUMMY_IP_LPSC_MCU2WKUP_VD"}, {243, "AM6_DEV_DUMMY_IP_LPSC_MAIN2MCU_VD"}, {244, "AM6_DEV_DUMMY_IP_LPSC_EMIF_DATA_VD"}, {245, "AM6_DEV_MCU_ARMSS0_CPU1"}, {246, "AM6_DEV_MCU_FSS0_FSAS_0"}, {247, "AM6_DEV_MCU_FSS0_HYPERBUS0"}, {248, "AM6_DEV_MCU_FSS0_OSPI_0"}, {249, "AM6_DEV_MCU_FSS0_OSPI_1"}, }; k3conf_0.3/soc/am65x_sr2/am65x_sr2_clocks_info.c0000664000175000017500000027540014375734376016353 0ustar /* * AM65X_SR2 Clocks Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_clocks_info am65x_sr2_clocks_info[] = { {157, 5, "DEV_BOARD0_BUS_MCU_OSPI1CLK_IN", "Input clock"}, {157, 7, "DEV_BOARD0_BUS_REFCLK1P_IN", "Input muxed clock"}, {157, 8, "DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN"}, {157, 9, "DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN"}, {157, 10, "DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN"}, {157, 11, "DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN"}, {157, 12, "DEV_BOARD0_BUS_MCU_OSPI1LBCLKO_IN", "Input clock"}, {157, 13, "DEV_BOARD0_BUS_MCU_OBSCLK_IN", "Input clock"}, {157, 14, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, {157, 15, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, {157, 16, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, {157, 17, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_CLKOUT_CLK_DUP0", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, {157, 18, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, {157, 19, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, {157, 20, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, {157, 21, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, {157, 22, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, {157, 23, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, {157, 24, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, {157, 25, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, {157, 26, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, {157, 27, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, {157, 28, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK_DUP0", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, {157, 29, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, {157, 36, "DEV_BOARD0_BUS_OBSCLK_IN", "Input clock"}, {157, 37, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, {157, 38, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, {157, 39, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, {157, 40, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, {157, 41, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, {157, 42, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, {157, 43, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_WRAP_MAIN_4_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, {157, 44, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLM_WRAP_MAIN_6_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, {157, 45, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, {157, 46, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, {157, 47, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, {157, 48, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLM_WRAP_MAIN_7_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, {157, 54, "DEV_BOARD0_BUS_MCU_OSPI0CLK_IN", "Input clock"}, {157, 55, "DEV_BOARD0_BUS_DSS0PCLK_IN", "Input clock"}, {157, 58, "DEV_BOARD0_BUS_REFCLK0P_IN", "Input muxed clock"}, {157, 59, "DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN"}, {157, 60, "DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN"}, {157, 61, "DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN"}, {157, 62, "DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN"}, {157, 68, "DEV_BOARD0_BUS_MCU_OSPI0LBCLKO_IN", "Input clock"}, {157, 69, "DEV_BOARD0_BUS_MCU_CLKOUT_IN", "Input muxed clock"}, {157, 70, "DEV_BOARD0_BUS_MCU_CLKOUT_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_BOARD0_BUS_MCU_CLKOUT_IN"}, {157, 71, "DEV_BOARD0_BUS_MCU_CLKOUT_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK10", "Parent input clock option to DEV_BOARD0_BUS_MCU_CLKOUT_IN"}, {157, 73, "DEV_BOARD0_BUS_SYSCLKOUT_IN", "Input clock"}, {157, 74, "DEV_BOARD0_BUS_MCU_SYSCLKOUT_IN", "Input clock"}, {157, 75, "DEV_BOARD0_BUS_PRG1_RGMII1_RCLK_OUT", "Output clock"}, {157, 76, "DEV_BOARD0_BUS_PRG1_RGMII2_RCLK_OUT", "Output clock"}, {157, 77, "DEV_BOARD0_BUS_GPMCCLK_OUT", "Output clock"}, {157, 78, "DEV_BOARD0_BUS_MCASP2AHCLKX_OUT", "Output clock"}, {157, 79, "DEV_BOARD0_BUS_MCASP2AHCLKR_OUT", "Output clock"}, {157, 80, "DEV_BOARD0_BUS_PRG2_RGMII2_RCLK_OUT", "Output clock"}, {157, 81, "DEV_BOARD0_BUS_CPTS_RFT_CLK_OUT", "Output clock"}, {157, 82, "DEV_BOARD0_BUS_MCASP0ACLKR_OUT", "Output clock"}, {157, 83, "DEV_BOARD0_BUS_MCASP0ACLKX_OUT", "Output clock"}, {157, 84, "DEV_BOARD0_BUS_EXT_REFCLK1_OUT", "Output clock"}, {157, 85, "DEV_BOARD0_BUS_PRG0_RGMII2_RCLK_OUT", "Output clock"}, {157, 86, "DEV_BOARD0_BUS_MCU_OSPI0DQS_OUT", "Output clock"}, {157, 88, "DEV_BOARD0_BUS_DSS0EXTPCLKIN_OUT", "Output clock"}, {157, 89, "DEV_BOARD0_BUS_SPI1CLK_OUT", "Output clock"}, {157, 90, "DEV_BOARD0_BUS_MCASP2ACLKR_OUT", "Output clock"}, {157, 91, "DEV_BOARD0_BUS_MCASP1ACLKX_OUT", "Output clock"}, {157, 92, "DEV_BOARD0_BUS_MCASP1ACLKR_OUT", "Output clock"}, {157, 93, "DEV_BOARD0_BUS_MCASP2ACLKX_OUT", "Output clock"}, {157, 94, "DEV_BOARD0_BUS_MCU_RMII1_REFCLK_OUT", "Output clock"}, {157, 95, "DEV_BOARD0_BUS_MCU_CPTS_RFT_CLK_OUT", "Output clock"}, {157, 96, "DEV_BOARD0_BUS_MCU_RGMII1_TCLK_OUT", "Output clock"}, {157, 97, "DEV_BOARD0_BUS_MCU_SPI0CLK_OUT", "Output clock"}, {157, 98, "DEV_BOARD0_BUS_MCU_SPI1CLK_OUT", "Output clock"}, {157, 99, "DEV_BOARD0_BUS_PRG0_RGMII1_RCLK_OUT", "Output clock"}, {157, 100, "DEV_BOARD0_BUS_SPI2CLK_OUT", "Output clock"}, {157, 101, "DEV_BOARD0_BUS_WKUP_TCK_OUT", "Output clock"}, {157, 102, "DEV_BOARD0_BUS_SPI3CLK_OUT", "Output clock"}, {157, 104, "DEV_BOARD0_BUS_MCU_RGMII1_RCLK_OUT", "Output clock"}, {157, 105, "DEV_BOARD0_BUS_MCASP0AHCLKR_OUT", "Output clock"}, {157, 106, "DEV_BOARD0_BUS_MCU_EXT_REFCLK0_OUT", "Output clock"}, {157, 107, "DEV_BOARD0_BUS_MCASP0AHCLKX_OUT", "Output clock"}, {157, 108, "DEV_BOARD0_BUS_CCDC0_PCLK_OUT", "Output clock"}, {157, 109, "DEV_BOARD0_HFOSC1_CLK_OUT", "Output clock"}, {157, 110, "DEV_BOARD0_BUS_MCU_OSPI1DQS_OUT", "Output clock"}, {157, 111, "DEV_BOARD0_BUS_MCASP1AHCLKX_OUT", "Output clock"}, {157, 113, "DEV_BOARD0_BUS_MCASP1AHCLKR_OUT", "Output clock"}, {157, 115, "DEV_BOARD0_BUS_PRG2_RGMII1_RCLK_OUT", "Output clock"}, {157, 116, "DEV_BOARD0_BUS_SPI0CLK_OUT", "Output clock"}, {157, 119, "DEV_BOARD0_BUS_PRG1_RGMII1_TCLK_OUT", "Output clock"}, {157, 120, "DEV_BOARD0_BUS_PRG2_RGMII2_TCLK_OUT", "Output clock"}, {157, 121, "DEV_BOARD0_BUS_PRG0_RGMII2_TCLK_OUT", "Output clock"}, {157, 122, "DEV_BOARD0_BUS_PRG1_RGMII2_TCLK_OUT", "Output clock"}, {157, 123, "DEV_BOARD0_BUS_PRG0_RGMII1_TCLK_OUT", "Output clock"}, {157, 124, "DEV_BOARD0_BUS_PRG2_RGMII1_TCLK_OUT", "Output clock"}, {2, 0, "DEV_CAL0_BUS_CLK", "Input clock"}, {2, 1, "DEV_CAL0_BUS_CP_C_CLK", "Input clock"}, {82, 0, "DEV_CBASS0_BUS_MAIN_SYSCLK0_2_CLK", "Input clock"}, {82, 1, "DEV_CBASS0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"}, {83, 0, "DEV_CBASS_DEBUG0_BUS_MAIN_SYSCLK0_2_CLK", "Input clock"}, {83, 1, "DEV_CBASS_DEBUG0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"}, {84, 0, "DEV_CBASS_FW0_BUS_MAIN_SYSCLK0_2_CLK", "Input clock"}, {84, 1, "DEV_CBASS_FW0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"}, {85, 0, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK", "Input muxed clock"}, {85, 1, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"}, {85, 2, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"}, {85, 3, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"}, {85, 4, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"}, {85, 5, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"}, {85, 6, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"}, {85, 7, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"}, {85, 8, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"}, {85, 9, "DEV_CBASS_INFRA0_BUS_MAIN_SYSCLK0_2_CLK", "Input clock"}, {85, 10, "DEV_CBASS_INFRA0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"}, {66, 0, "DEV_CCDEBUGSS0_BUS_ATB1_CLK", "Input clock"}, {66, 1, "DEV_CCDEBUGSS0_BUS_ATB0_CLK", "Input clock"}, {66, 2, "DEV_CCDEBUGSS0_BUS_SYS_CLK", "Input clock"}, {66, 3, "DEV_CCDEBUGSS0_BUS_DBG_CLK", "Input clock"}, {66, 4, "DEV_CCDEBUGSS0_BUS_CFG_CLK", "Input clock"}, {3, 0, "DEV_CMPEVENT_INTRTR0_BUS_INTR_CLK", "Input clock"}, {202, 0, "DEV_COMPUTE_CLUSTER_A53_0_BUS_ARM0_CLK", "Input clock"}, {203, 0, "DEV_COMPUTE_CLUSTER_A53_1_BUS_ARM0_CLK", "Input clock"}, {204, 0, "DEV_COMPUTE_CLUSTER_A53_2_BUS_ARM1_CLK", "Input clock"}, {205, 0, "DEV_COMPUTE_CLUSTER_A53_3_BUS_ARM1_CLK", "Input clock"}, {196, 2, "DEV_COMPUTE_CLUSTER_MSMC0_BUS_MSMC_CLK", "Input clock"}, {197, 0, "DEV_COMPUTE_CLUSTER_PBIST0_BUS_DIVH_CLK4_CLK_CLK", "Input clock"}, {197, 1, "DEV_COMPUTE_CLUSTER_PBIST0_BUS_DIVP_CLK1_CLK_CLK", "Input clock"}, {6, 0, "DEV_CPT2_AGGR0_BUS_VCLK_CLK", "Input clock"}, {213, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0_BUS_VBUS_CLK", "Input clock"}, {213, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0_BUS_PROBE_CLK", "Input clock"}, {214, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2_BUS_VBUS_CLK", "Input clock"}, {214, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2_BUS_PROBE_CLK", "Input clock"}, {211, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5_BUS_VBUS_CLK", "Input clock"}, {211, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5_BUS_PROBE_CLK", "Input clock"}, {212, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6_BUS_VBUS_CLK", "Input clock"}, {212, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6_BUS_PROBE_CLK", "Input clock"}, {209, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3_BUS_VBUS_CLK", "Input clock"}, {209, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3_BUS_PROBE_CLK", "Input clock"}, {206, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4_BUS_VBUS_CLK", "Input clock"}, {206, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4_BUS_PROBE_CLK", "Input clock"}, {208, 0, "DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0_BUS_VBUS_CLK", "Input clock"}, {208, 1, "DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0_BUS_PROBE_CLK", "Input clock"}, {215, 0, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2_BUS_VBUS_CLK", "Input clock"}, {215, 1, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2_BUS_PROBE_CLK", "Input clock"}, {207, 0, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3_BUS_VBUS_CLK", "Input clock"}, {207, 1, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3_BUS_PROBE_CLK", "Input clock"}, {210, 0, "DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1_BUS_VBUS_CLK", "Input clock"}, {210, 1, "DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1_BUS_PROBE_CLK", "Input clock"}, {99, 0, "DEV_CTRL_MMR0_BUS_VBUSP_CLK", "Input clock"}, {9, 0, "DEV_DCC0_BUS_DCC_INPUT00_CLK", "Input clock"}, {9, 1, "DEV_DCC0_BUS_DCC_CLKSRC4_CLK", "Input clock"}, {9, 2, "DEV_DCC0_BUS_DCC_CLKSRC3_CLK", "Input clock"}, {9, 3, "DEV_DCC0_BUS_VBUS_CLK", "Input clock"}, {9, 4, "DEV_DCC0_BUS_DCC_CLKSRC1_CLK", "Input clock"}, {9, 5, "DEV_DCC0_BUS_DCC_INPUT01_CLK", "Input clock"}, {9, 6, "DEV_DCC0_BUS_DCC_CLKSRC5_CLK", "Input clock"}, {9, 7, "DEV_DCC0_BUS_DCC_INPUT02_CLK", "Input clock"}, {9, 8, "DEV_DCC0_BUS_DCC_CLKSRC0_CLK", "Input clock"}, {9, 9, "DEV_DCC0_BUS_DCC_CLKSRC6_CLK", "Input clock"}, {9, 10, "DEV_DCC0_BUS_DCC_INPUT10_CLK", "Input clock"}, {9, 11, "DEV_DCC0_BUS_DCC_CLKSRC2_CLK", "Input clock"}, {10, 0, "DEV_DCC1_BUS_DCC_INPUT00_CLK", "Input clock"}, {10, 1, "DEV_DCC1_BUS_DCC_CLKSRC7_CLK", "Input clock"}, {10, 2, "DEV_DCC1_BUS_DCC_CLKSRC4_CLK", "Input clock"}, {10, 3, "DEV_DCC1_BUS_DCC_CLKSRC3_CLK", "Input clock"}, {10, 4, "DEV_DCC1_BUS_VBUS_CLK", "Input clock"}, {10, 5, "DEV_DCC1_BUS_DCC_CLKSRC1_CLK", "Input clock"}, {10, 6, "DEV_DCC1_BUS_DCC_INPUT01_CLK", "Input clock"}, {10, 7, "DEV_DCC1_BUS_DCC_CLKSRC5_CLK", "Input clock"}, {10, 8, "DEV_DCC1_BUS_DCC_INPUT02_CLK", "Input clock"}, {10, 9, "DEV_DCC1_BUS_DCC_CLKSRC0_CLK", "Input clock"}, {10, 10, "DEV_DCC1_BUS_DCC_CLKSRC6_CLK", "Input clock"}, {10, 11, "DEV_DCC1_BUS_DCC_INPUT10_CLK", "Input clock"}, {10, 12, "DEV_DCC1_BUS_DCC_CLKSRC2_CLK", "Input clock"}, {11, 0, "DEV_DCC2_BUS_DCC_INPUT00_CLK", "Input clock"}, {11, 1, "DEV_DCC2_BUS_DCC_CLKSRC7_CLK", "Input clock"}, {11, 2, "DEV_DCC2_BUS_DCC_CLKSRC4_CLK", "Input clock"}, {11, 3, "DEV_DCC2_BUS_DCC_CLKSRC3_CLK", "Input clock"}, {11, 4, "DEV_DCC2_BUS_VBUS_CLK", "Input clock"}, {11, 5, "DEV_DCC2_BUS_DCC_CLKSRC1_CLK", "Input clock"}, {11, 6, "DEV_DCC2_BUS_DCC_INPUT01_CLK", "Input clock"}, {11, 7, "DEV_DCC2_BUS_DCC_CLKSRC5_CLK", "Input clock"}, {11, 8, "DEV_DCC2_BUS_DCC_INPUT02_CLK", "Input clock"}, {11, 9, "DEV_DCC2_BUS_DCC_CLKSRC0_CLK", "Input clock"}, {11, 10, "DEV_DCC2_BUS_DCC_CLKSRC6_CLK", "Input clock"}, {11, 11, "DEV_DCC2_BUS_DCC_INPUT10_CLK", "Input clock"}, {11, 12, "DEV_DCC2_BUS_DCC_CLKSRC2_CLK", "Input clock"}, {12, 0, "DEV_DCC3_BUS_DCC_INPUT00_CLK", "Input clock"}, {12, 1, "DEV_DCC3_BUS_DCC_CLKSRC7_CLK", "Input clock"}, {12, 2, "DEV_DCC3_BUS_DCC_CLKSRC4_CLK", "Input clock"}, {12, 3, "DEV_DCC3_BUS_DCC_CLKSRC3_CLK", "Input clock"}, {12, 4, "DEV_DCC3_BUS_VBUS_CLK", "Input clock"}, {12, 5, "DEV_DCC3_BUS_DCC_CLKSRC1_CLK", "Input clock"}, {12, 6, "DEV_DCC3_BUS_DCC_INPUT01_CLK", "Input clock"}, {12, 7, "DEV_DCC3_BUS_DCC_CLKSRC5_CLK", "Input clock"}, {12, 8, "DEV_DCC3_BUS_DCC_INPUT02_CLK", "Input clock"}, {12, 9, "DEV_DCC3_BUS_DCC_CLKSRC0_CLK", "Input clock"}, {12, 10, "DEV_DCC3_BUS_DCC_INPUT10_CLK", "Input clock"}, {12, 11, "DEV_DCC3_BUS_DCC_CLKSRC2_CLK", "Input clock"}, {13, 0, "DEV_DCC4_BUS_DCC_INPUT00_CLK", "Input clock"}, {13, 1, "DEV_DCC4_BUS_DCC_CLKSRC7_CLK", "Input clock"}, {13, 2, "DEV_DCC4_BUS_DCC_CLKSRC4_CLK", "Input clock"}, {13, 3, "DEV_DCC4_BUS_DCC_CLKSRC3_CLK", "Input clock"}, {13, 4, "DEV_DCC4_BUS_VBUS_CLK", "Input clock"}, {13, 5, "DEV_DCC4_BUS_DCC_INPUT01_CLK", "Input clock"}, {13, 6, "DEV_DCC4_BUS_DCC_CLKSRC5_CLK", "Input clock"}, {13, 7, "DEV_DCC4_BUS_DCC_INPUT02_CLK", "Input clock"}, {13, 8, "DEV_DCC4_BUS_DCC_CLKSRC0_CLK", "Input clock"}, {13, 9, "DEV_DCC4_BUS_DCC_CLKSRC6_CLK", "Input clock"}, {13, 10, "DEV_DCC4_BUS_DCC_INPUT10_CLK", "Input clock"}, {13, 11, "DEV_DCC4_BUS_DCC_CLKSRC2_CLK", "Input clock"}, {14, 0, "DEV_DCC5_BUS_DCC_INPUT00_CLK", "Input clock"}, {14, 1, "DEV_DCC5_BUS_DCC_CLKSRC7_CLK", "Input clock"}, {14, 2, "DEV_DCC5_BUS_DCC_CLKSRC4_CLK", "Input clock"}, {14, 3, "DEV_DCC5_BUS_DCC_CLKSRC3_CLK", "Input clock"}, {14, 4, "DEV_DCC5_BUS_VBUS_CLK", "Input clock"}, {14, 5, "DEV_DCC5_BUS_DCC_CLKSRC1_CLK", "Input clock"}, {14, 6, "DEV_DCC5_BUS_DCC_INPUT01_CLK", "Input clock"}, {14, 7, "DEV_DCC5_BUS_DCC_CLKSRC5_CLK", "Input clock"}, {14, 8, "DEV_DCC5_BUS_DCC_INPUT02_CLK", "Input clock"}, {14, 9, "DEV_DCC5_BUS_DCC_CLKSRC0_CLK", "Input clock"}, {14, 10, "DEV_DCC5_BUS_DCC_CLKSRC6_CLK", "Input clock"}, {14, 11, "DEV_DCC5_BUS_DCC_INPUT10_CLK", "Input clock"}, {14, 12, "DEV_DCC5_BUS_DCC_CLKSRC2_CLK", "Input clock"}, {15, 0, "DEV_DCC6_BUS_DCC_INPUT00_CLK", "Input clock"}, {15, 1, "DEV_DCC6_BUS_DCC_CLKSRC7_CLK", "Input clock"}, {15, 2, "DEV_DCC6_BUS_DCC_CLKSRC4_CLK", "Input clock"}, {15, 3, "DEV_DCC6_BUS_DCC_CLKSRC3_CLK", "Input clock"}, {15, 4, "DEV_DCC6_BUS_VBUS_CLK", "Input clock"}, {15, 5, "DEV_DCC6_BUS_DCC_CLKSRC1_CLK", "Input clock"}, {15, 6, "DEV_DCC6_BUS_DCC_INPUT01_CLK", "Input clock"}, {15, 7, "DEV_DCC6_BUS_DCC_CLKSRC5_CLK", "Input clock"}, {15, 8, "DEV_DCC6_BUS_DCC_INPUT02_CLK", "Input clock"}, {15, 9, "DEV_DCC6_BUS_DCC_CLKSRC0_CLK", "Input clock"}, {15, 10, "DEV_DCC6_BUS_DCC_CLKSRC6_CLK", "Input clock"}, {15, 11, "DEV_DCC6_BUS_DCC_INPUT10_CLK", "Input clock"}, {15, 12, "DEV_DCC6_BUS_DCC_CLKSRC2_CLK", "Input clock"}, {16, 0, "DEV_DCC7_BUS_DCC_INPUT00_CLK", "Input clock"}, {16, 1, "DEV_DCC7_BUS_DCC_CLKSRC7_CLK", "Input clock"}, {16, 2, "DEV_DCC7_BUS_DCC_CLKSRC4_CLK", "Input clock"}, {16, 3, "DEV_DCC7_BUS_DCC_CLKSRC3_CLK", "Input clock"}, {16, 4, "DEV_DCC7_BUS_VBUS_CLK", "Input clock"}, {16, 5, "DEV_DCC7_BUS_DCC_CLKSRC1_CLK", "Input clock"}, {16, 6, "DEV_DCC7_BUS_DCC_INPUT01_CLK", "Input clock"}, {16, 7, "DEV_DCC7_BUS_DCC_CLKSRC5_CLK", "Input clock"}, {16, 8, "DEV_DCC7_BUS_DCC_INPUT02_CLK", "Input clock"}, {16, 9, "DEV_DCC7_BUS_DCC_CLKSRC0_CLK", "Input clock"}, {16, 10, "DEV_DCC7_BUS_DCC_CLKSRC6_CLK", "Input clock"}, {16, 11, "DEV_DCC7_BUS_DCC_INPUT10_CLK", "Input clock"}, {16, 12, "DEV_DCC7_BUS_DCC_CLKSRC2_CLK", "Input clock"}, {20, 0, "DEV_DDRSS0_BUS_DDRSS_VBUS_CLK", "Input clock"}, {20, 1, "DEV_DDRSS0_BUS_DDRSS_BYP_4X_CLK", "Input clock"}, {20, 2, "DEV_DDRSS0_BUS_DDRSS_CTL_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"}, {20, 3, "DEV_DDRSS0_BUS_DDRSS_TCLK", "Input clock"}, {20, 4, "DEV_DDRSS0_BUS_DDRSS_PHY_CTL_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"}, {20, 5, "DEV_DDRSS0_BUS_DDRSS_PHY_CTL_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"}, {20, 6, "DEV_DDRSS0_BUS_DDRSS_CFG_CLK", "Input clock"}, {20, 7, "DEV_DDRSS0_BUS_DDRSS_CTL_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"}, {20, 8, "DEV_DDRSS0_BUS_DDRSS_BYP_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"}, {20, 9, "DEV_DDRSS0_BUS_DDRSS_BYP_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"}, {68, 0, "DEV_DEBUGSS0_BUS_ATB1_CLK", "Input clock"}, {68, 1, "DEV_DEBUGSS0_BUS_ATB5_CLK", "Input clock"}, {68, 2, "DEV_DEBUGSS0_BUS_ATB0_CLK", "Input clock"}, {68, 3, "DEV_DEBUGSS0_BUS_SYS_CLK", "Input clock"}, {68, 4, "DEV_DEBUGSS0_BUS_ATB4_CLK", "Input clock"}, {68, 5, "DEV_DEBUGSS0_BUS_CFG_CLK", "Input clock"}, {68, 6, "DEV_DEBUGSS0_BUS_ATB2_CLK", "Input clock"}, {68, 7, "DEV_DEBUGSS0_BUS_DBG_CLK", "Input clock"}, {68, 8, "DEV_DEBUGSS0_BUS_ATB3_CLK", "Input clock"}, {21, 0, "DEV_DEBUGSS_WRAP0_BUS_JTAG_TCK", "Input clock"}, {21, 1, "DEV_DEBUGSS_WRAP0_BUS_ATB_CLK", "Input clock"}, {21, 2, "DEV_DEBUGSS_WRAP0_BUS_TREXPT_CLK", "Input clock"}, {21, 3, "DEV_DEBUGSS_WRAP0_BUS_CORE_CLK", "Input clock"}, {81, 0, "DEV_DEBUGSUSPENDRTR0_BUS_INTR_CLK", "Input clock"}, {117, 0, "DEV_DFTSS0_BUS_VBUSP_CLK_CLK", "Input clock"}, {67, 0, "DEV_DSS0_BUS_DPI_0_IN_CLK_BUS_IN1_DSS_BUS_OUT0", "Input clock"}, {67, 1, "DEV_DSS0_BUS_DSS_FUNC_CLK", "Input clock"}, {67, 2, "DEV_DSS0_BUS_DPI_1_IN_CLK", "Input muxed clock"}, {67, 3, "DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_DSS_BUS_OUT07", "Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK"}, {67, 4, "DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_BOARD_0_BUS_DSS0EXTPCLKIN_OUT", "Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK"}, {67, 5, "DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_DSS_BUS_OUT1", "Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK"}, {67, 6, "DEV_DSS0_BUS_DPI_0_IN_CLK_BUS_IN0_DSS_BUS_OUT0", "Input clock"}, {67, 7, "DEV_DSS0_BUS_DPI_1_OUT_CLK", "Output clock"}, {39, 0, "DEV_ECAP0_BUS_VBUS_CLK", "Input clock"}, {86, 0, "DEV_ECC_AGGR0_BUS_AGGR_CLK", "Input clock"}, {87, 0, "DEV_ECC_AGGR1_BUS_AGGR_CLK", "Input clock"}, {88, 0, "DEV_ECC_AGGR2_BUS_AGGR_CLK", "Input clock"}, {69, 0, "DEV_EFUSE0_BUS_VBUSP_PLL_CLK_CLK", "Input clock"}, {40, 0, "DEV_EHRPWM0_BUS_VBUSP_CLK", "Input clock"}, {41, 0, "DEV_EHRPWM1_BUS_VBUSP_CLK", "Input clock"}, {42, 0, "DEV_EHRPWM2_BUS_VBUSP_CLK", "Input clock"}, {43, 0, "DEV_EHRPWM3_BUS_VBUSP_CLK", "Input clock"}, {44, 0, "DEV_EHRPWM4_BUS_VBUSP_CLK", "Input clock"}, {45, 0, "DEV_EHRPWM5_BUS_VBUSP_CLK", "Input clock"}, {46, 0, "DEV_ELM0_BUS_VBUSP_CLK", "Input clock"}, {49, 0, "DEV_EQEP0_BUS_VBUS_CLK", "Input clock"}, {50, 0, "DEV_EQEP1_BUS_VBUS_CLK", "Input clock"}, {51, 0, "DEV_EQEP2_BUS_VBUS_CLK", "Input clock"}, {52, 0, "DEV_ESM0_BUS_CLK", "Input clock"}, {56, 0, "DEV_GIC0_BUS_VCLK_CLK", "Input clock"}, {57, 0, "DEV_GPIO0_BUS_MMR_CLK", "Input clock"}, {58, 0, "DEV_GPIO1_BUS_MMR_CLK", "Input clock"}, {100, 0, "DEV_GPIOMUX_INTRTR0_BUS_INTR_CLK", "Input clock"}, {60, 0, "DEV_GPMC0_BUS_FUNC_CLK", "Input muxed clock"}, {60, 1, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"}, {60, 2, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK3", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"}, {60, 3, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK2", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"}, {60, 4, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_BUS_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"}, {60, 5, "DEV_GPMC0_BUS_PI_GPMC_RET_CLK", "Input clock"}, {60, 6, "DEV_GPMC0_BUS_VBUSP_CLK", "Input clock"}, {60, 7, "DEV_GPMC0_BUS_PO_GPMC_DEV_CLK", "Output clock"}, {65, 0, "DEV_GPU0_BUS_MEM_CLK", "Input clock"}, {65, 1, "DEV_GPU0_BUS_HYD_CORE_CLK", "Input clock"}, {65, 2, "DEV_GPU0_BUS_SGX_CORE_CLK", "Input clock"}, {65, 3, "DEV_GPU0_BUS_SYS_CLK", "Input clock"}, {232, 0, "DEV_GS80PRG_MCU_WRAP_WKUP_0_BUS_OSC_CLK", "Input clock"}, {232, 1, "DEV_GS80PRG_MCU_WRAP_WKUP_0_BUS_CLK", "Input clock"}, {231, 0, "DEV_GS80PRG_SOC_WRAP_WKUP_0_BUS_OSC_CLK", "Input clock"}, {231, 1, "DEV_GS80PRG_SOC_WRAP_WKUP_0_BUS_CLK", "Input clock"}, {61, 0, "DEV_GTC0_BUS_VBUSP_CLK", "Input muxed clock"}, {61, 1, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"}, {61, 2, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"}, {61, 3, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"}, {61, 4, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"}, {61, 5, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"}, {61, 6, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"}, {61, 7, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"}, {61, 8, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"}, {110, 0, "DEV_I2C0_BUS_CLK", "Input clock"}, {110, 1, "DEV_I2C0_BUS_PISYS_CLK", "Input clock"}, {111, 0, "DEV_I2C1_BUS_CLK", "Input clock"}, {111, 1, "DEV_I2C1_BUS_PISYS_CLK", "Input clock"}, {112, 0, "DEV_I2C2_BUS_CLK", "Input clock"}, {112, 1, "DEV_I2C2_BUS_PISYS_CLK", "Input clock"}, {113, 0, "DEV_I2C3_BUS_CLK", "Input clock"}, {113, 1, "DEV_I2C3_BUS_PISYS_CLK", "Input clock"}, {217, 0, "DEV_K3_ARM_ATB_FUNNEL_3_32_MCU_0_BUS_DBG_CLK", "Input clock"}, {97, 0, "DEV_MAIN2MCU_LVL_INTRTR0_BUS_INTR_CLK", "Input clock"}, {98, 0, "DEV_MAIN2MCU_PLS_INTRTR0_BUS_INTR_CLK", "Input clock"}, {104, 0, "DEV_MCASP0_BUS_AUX_CLK", "Input muxed clock"}, {104, 1, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"}, {104, 2, "DEV_MCASP0_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"}, {104, 3, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"}, {104, 4, "DEV_MCASP0_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"}, {104, 5, "DEV_MCASP0_BUS_AUX_CLK_PARENT_MCASP_ARM1_PLL_DIV_BUS_OUT0", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"}, {104, 6, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"}, {104, 7, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"}, {104, 8, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"}, {104, 9, "DEV_MCASP0_BUS_VBUSP_CLK", "Input clock"}, {105, 0, "DEV_MCASP1_BUS_AUX_CLK", "Input muxed clock"}, {105, 1, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"}, {105, 2, "DEV_MCASP1_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"}, {105, 3, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"}, {105, 4, "DEV_MCASP1_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"}, {105, 5, "DEV_MCASP1_BUS_AUX_CLK_PARENT_MCASP_ARM1_PLL_DIV_BUS_OUT1", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"}, {105, 6, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"}, {105, 7, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"}, {105, 8, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"}, {105, 9, "DEV_MCASP1_BUS_VBUSP_CLK", "Input clock"}, {106, 0, "DEV_MCASP2_BUS_AUX_CLK", "Input muxed clock"}, {106, 1, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"}, {106, 2, "DEV_MCASP2_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"}, {106, 3, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"}, {106, 4, "DEV_MCASP2_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"}, {106, 5, "DEV_MCASP2_BUS_AUX_CLK_PARENT_MCASP_ARM1_PLL_DIV_BUS_OUT2", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"}, {106, 6, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"}, {106, 7, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"}, {106, 8, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"}, {106, 9, "DEV_MCASP2_BUS_VBUSP_CLK", "Input clock"}, {137, 0, "DEV_MCSPI0_BUS_IO_CLKSPII_CLK", "Input clock"}, {137, 1, "DEV_MCSPI0_BUS_CLKSPIREF_CLK", "Input clock"}, {137, 2, "DEV_MCSPI0_BUS_VBUSP_CLK", "Input clock"}, {137, 3, "DEV_MCSPI0_BUS_IO_CLKSPIO_CLK", "Output clock"}, {138, 0, "DEV_MCSPI1_BUS_IO_CLKSPII_CLK", "Input clock"}, {138, 1, "DEV_MCSPI1_BUS_CLKSPIREF_CLK", "Input clock"}, {138, 2, "DEV_MCSPI1_BUS_VBUSP_CLK", "Input clock"}, {138, 3, "DEV_MCSPI1_BUS_IO_CLKSPIO_CLK", "Output clock"}, {139, 0, "DEV_MCSPI2_BUS_IO_CLKSPII_CLK", "Input clock"}, {139, 1, "DEV_MCSPI2_BUS_CLKSPIREF_CLK", "Input clock"}, {139, 2, "DEV_MCSPI2_BUS_VBUSP_CLK", "Input clock"}, {139, 3, "DEV_MCSPI2_BUS_IO_CLKSPIO_CLK", "Output clock"}, {140, 0, "DEV_MCSPI3_BUS_IO_CLKSPII_CLK", "Input clock"}, {140, 1, "DEV_MCSPI3_BUS_CLKSPIREF_CLK", "Input clock"}, {140, 2, "DEV_MCSPI3_BUS_VBUSP_CLK", "Input clock"}, {140, 3, "DEV_MCSPI3_BUS_IO_CLKSPIO_CLK", "Output clock"}, {141, 0, "DEV_MCSPI4_BUS_CLKSPIREF_CLK", "Input clock"}, {141, 1, "DEV_MCSPI4_BUS_VBUSP_CLK", "Input clock"}, {141, 2, "DEV_MCSPI4_BUS_IO_CLKSPII_CLK", "Input clock"}, {141, 3, "DEV_MCSPI4_BUS_IO_CLKSPIO_CLK", "Output clock"}, {0, 0, "DEV_MCU_ADC0_BUS_VBUS_CLK", "Input clock"}, {0, 1, "DEV_MCU_ADC0_BUS_SYS_CLK", "Input clock"}, {0, 2, "DEV_MCU_ADC0_BUS_ADC_CLK", "Input muxed clock"}, {0, 3, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"}, {0, 4, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"}, {0, 5, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"}, {0, 6, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"}, {1, 0, "DEV_MCU_ADC1_BUS_VBUS_CLK", "Input clock"}, {1, 1, "DEV_MCU_ADC1_BUS_SYS_CLK", "Input clock"}, {1, 2, "DEV_MCU_ADC1_BUS_ADC_CLK", "Input muxed clock"}, {1, 3, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"}, {1, 4, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"}, {1, 5, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"}, {1, 6, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"}, {159, 0, "DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_CLK", "Input clock"}, {159, 1, "DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE", "Input muxed clock"}, {159, 2, "DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE"}, {159, 3, "DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK", "Input muxed clock"}, {159, 4, "DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK"}, {159, 5, "DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK"}, {245, 0, "DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_CLK", "Input clock"}, {245, 1, "DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE", "Input muxed clock"}, {245, 2, "DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE"}, {245, 3, "DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK", "Input muxed clock"}, {245, 4, "DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK"}, {245, 5, "DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK"}, {89, 0, "DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_8_CLK", "Input clock"}, {89, 1, "DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_4_CLK", "Input clock"}, {89, 2, "DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_2_CLK", "Input clock"}, {90, 0, "DEV_MCU_CBASS_DEBUG0_BUS_MCU_SYSCLK0_2_CLK", "Input clock"}, {91, 0, "DEV_MCU_CBASS_FW0_BUS_MCU_SYSCLK0_4_CLK", "Input clock"}, {91, 1, "DEV_MCU_CBASS_FW0_BUS_MCU_SYSCLK0_2_CLK", "Input clock"}, {5, 0, "DEV_MCU_CPSW0_BUS_GMII1_MR_CLK", "Input clock"}, {5, 1, "DEV_MCU_CPSW0_BUS_RGMII_MHZ_250_CLK", "Input clock"}, {5, 2, "DEV_MCU_CPSW0_BUS_CPTS_RFT_CLK", "Input clock"}, {5, 3, "DEV_MCU_CPSW0_BUS_GMII1_MT_CLK", "Input clock"}, {5, 4, "DEV_MCU_CPSW0_BUS_RGMII_MHZ_5_CLK", "Input clock"}, {5, 5, "DEV_MCU_CPSW0_BUS_RGMII_MHZ_50_CLK", "Input clock"}, {5, 6, "DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK", "Input muxed clock"}, {5, 7, "DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK"}, {5, 8, "DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK_PARENT_BOARD_0_BUS_MCU_RMII1_REFCLK_OUT", "Parent input clock option to DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK"}, {5, 9, "DEV_MCU_CPSW0_BUS_GMII_RFT_CLK", "Input clock"}, {5, 10, "DEV_MCU_CPSW0_BUS_CPPI_CLK_CLK", "Input clock"}, {7, 0, "DEV_MCU_CPT2_AGGR0_BUS_VCLK_CLK", "Input clock"}, {107, 0, "DEV_MCU_CTRL_MMR0_BUS_VBUSP_CLK", "Input clock"}, {17, 0, "DEV_MCU_DCC0_BUS_DCC_INPUT00_CLK", "Input clock"}, {17, 1, "DEV_MCU_DCC0_BUS_DCC_CLKSRC7_CLK", "Input clock"}, {17, 2, "DEV_MCU_DCC0_BUS_DCC_CLKSRC4_CLK", "Input clock"}, {17, 3, "DEV_MCU_DCC0_BUS_DCC_CLKSRC3_CLK", "Input clock"}, {17, 4, "DEV_MCU_DCC0_BUS_VBUS_CLK", "Input clock"}, {17, 5, "DEV_MCU_DCC0_BUS_DCC_CLKSRC1_CLK", "Input clock"}, {17, 6, "DEV_MCU_DCC0_BUS_DCC_INPUT01_CLK", "Input clock"}, {17, 7, "DEV_MCU_DCC0_BUS_DCC_CLKSRC5_CLK", "Input clock"}, {17, 8, "DEV_MCU_DCC0_BUS_DCC_INPUT02_CLK", "Input clock"}, {17, 9, "DEV_MCU_DCC0_BUS_DCC_CLKSRC0_CLK", "Input clock"}, {17, 10, "DEV_MCU_DCC0_BUS_DCC_CLKSRC6_CLK", "Input clock"}, {17, 11, "DEV_MCU_DCC0_BUS_DCC_INPUT10_CLK", "Input clock"}, {17, 12, "DEV_MCU_DCC0_BUS_DCC_CLKSRC2_CLK", "Input clock"}, {18, 0, "DEV_MCU_DCC1_BUS_DCC_INPUT00_CLK", "Input clock"}, {18, 1, "DEV_MCU_DCC1_BUS_DCC_CLKSRC7_CLK", "Input clock"}, {18, 2, "DEV_MCU_DCC1_BUS_DCC_CLKSRC4_CLK", "Input clock"}, {18, 3, "DEV_MCU_DCC1_BUS_DCC_CLKSRC3_CLK", "Input clock"}, {18, 4, "DEV_MCU_DCC1_BUS_VBUS_CLK", "Input clock"}, {18, 5, "DEV_MCU_DCC1_BUS_DCC_CLKSRC1_CLK", "Input clock"}, {18, 6, "DEV_MCU_DCC1_BUS_DCC_INPUT01_CLK", "Input clock"}, {18, 7, "DEV_MCU_DCC1_BUS_DCC_CLKSRC5_CLK", "Input clock"}, {18, 8, "DEV_MCU_DCC1_BUS_DCC_INPUT02_CLK", "Input clock"}, {18, 9, "DEV_MCU_DCC1_BUS_DCC_CLKSRC0_CLK", "Input clock"}, {18, 10, "DEV_MCU_DCC1_BUS_DCC_CLKSRC6_CLK", "Input clock"}, {18, 11, "DEV_MCU_DCC1_BUS_DCC_INPUT10_CLK", "Input clock"}, {18, 12, "DEV_MCU_DCC1_BUS_DCC_CLKSRC2_CLK", "Input clock"}, {19, 0, "DEV_MCU_DCC2_BUS_DCC_INPUT00_CLK", "Input clock"}, {19, 1, "DEV_MCU_DCC2_BUS_DCC_CLKSRC7_CLK", "Input clock"}, {19, 2, "DEV_MCU_DCC2_BUS_DCC_CLKSRC4_CLK", "Input clock"}, {19, 3, "DEV_MCU_DCC2_BUS_DCC_CLKSRC3_CLK", "Input clock"}, {19, 4, "DEV_MCU_DCC2_BUS_VBUS_CLK", "Input clock"}, {19, 5, "DEV_MCU_DCC2_BUS_DCC_CLKSRC1_CLK", "Input clock"}, {19, 6, "DEV_MCU_DCC2_BUS_DCC_INPUT01_CLK", "Input clock"}, {19, 7, "DEV_MCU_DCC2_BUS_DCC_CLKSRC5_CLK", "Input clock"}, {19, 8, "DEV_MCU_DCC2_BUS_DCC_INPUT02_CLK", "Input clock"}, {19, 9, "DEV_MCU_DCC2_BUS_DCC_CLKSRC0_CLK", "Input clock"}, {19, 10, "DEV_MCU_DCC2_BUS_DCC_CLKSRC6_CLK", "Input clock"}, {19, 11, "DEV_MCU_DCC2_BUS_DCC_INPUT10_CLK", "Input clock"}, {19, 12, "DEV_MCU_DCC2_BUS_DCC_CLKSRC2_CLK", "Input clock"}, {71, 0, "DEV_MCU_DEBUGSS0_BUS_ATB1_CLK", "Input clock"}, {71, 1, "DEV_MCU_DEBUGSS0_BUS_ATB0_CLK", "Input clock"}, {71, 2, "DEV_MCU_DEBUGSS0_BUS_SYS_CLK", "Input clock"}, {71, 3, "DEV_MCU_DEBUGSS0_BUS_CFG_CLK", "Input clock"}, {71, 4, "DEV_MCU_DEBUGSS0_BUS_ATB2_CLK", "Input clock"}, {71, 5, "DEV_MCU_DEBUGSS0_BUS_DBG_CLK", "Input clock"}, {71, 6, "DEV_MCU_DEBUGSS0_BUS_ATB3_CLK", "Input clock"}, {92, 0, "DEV_MCU_ECC_AGGR0_BUS_AGGR_CLK", "Input clock"}, {93, 0, "DEV_MCU_ECC_AGGR1_BUS_AGGR_CLK", "Input clock"}, {72, 0, "DEV_MCU_EFUSE0_BUS_VBUSP_CLK_CLK", "Input clock"}, {53, 0, "DEV_MCU_ESM0_BUS_CLK", "Input clock"}, {247, 0, "DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX1_INV_CLK", "Input clock"}, {247, 1, "DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX1_CLK", "Input clock"}, {247, 2, "DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX2_CLK", "Input clock"}, {247, 3, "DEV_MCU_FSS0_HYPERBUS0_BUS_CBA_CLK", "Input clock"}, {248, 0, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_RCLK_CLK", "Input muxed clock"}, {248, 1, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI_RCLK_CLK"}, {248, 2, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI_RCLK_CLK"}, {248, 3, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_ICLK_CLK", "Input muxed clock"}, {248, 4, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_ICLK_CLK_PARENT_BOARD_0_BUS_MCU_OSPI0DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI_ICLK_CLK"}, {248, 5, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_BUS_OSPI_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI_ICLK_CLK"}, {248, 6, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_PCLK_CLK", "Input clock"}, {248, 7, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_DQS_CLK", "Input clock"}, {248, 8, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_HCLK_CLK", "Input clock"}, {248, 9, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_OCLK_CLK", "Output clock"}, {249, 0, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_PCLK_CLK", "Input clock"}, {249, 1, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_ICLK_CLK", "Input muxed clock"}, {249, 2, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_ICLK_CLK_PARENT_BOARD_0_BUS_MCU_OSPI1DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI_ICLK_CLK"}, {249, 3, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_1_BUS_OSPI_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI_ICLK_CLK"}, {249, 4, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_HCLK_CLK", "Input clock"}, {249, 5, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_DQS_CLK", "Input clock"}, {249, 6, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_RCLK_CLK", "Input muxed clock"}, {249, 7, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI_RCLK_CLK"}, {249, 8, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI_RCLK_CLK"}, {249, 9, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_OCLK_CLK", "Output clock"}, {114, 0, "DEV_MCU_I2C0_BUS_CLK", "Input clock"}, {114, 1, "DEV_MCU_I2C0_BUS_PISYS_CLK", "Input clock"}, {102, 0, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK", "Input muxed clock"}, {102, 1, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"}, {102, 2, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK2", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"}, {102, 3, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK2", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"}, {102, 4, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"}, {102, 5, "DEV_MCU_MCAN0_BUS_MCANSS_HCLK_CLK", "Input clock"}, {103, 0, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK", "Input muxed clock"}, {103, 1, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"}, {103, 2, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK2", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"}, {103, 3, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK2", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"}, {103, 4, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"}, {103, 5, "DEV_MCU_MCAN1_BUS_MCANSS_HCLK_CLK", "Input clock"}, {142, 0, "DEV_MCU_MCSPI0_BUS_IO_CLKSPII_CLK", "Input clock"}, {142, 1, "DEV_MCU_MCSPI0_BUS_CLKSPIREF_CLK", "Input clock"}, {142, 2, "DEV_MCU_MCSPI0_BUS_VBUSP_CLK", "Input clock"}, {142, 3, "DEV_MCU_MCSPI0_BUS_IO_CLKSPIO_CLK", "Output clock"}, {143, 0, "DEV_MCU_MCSPI1_BUS_IO_CLKSPII_CLK", "Input clock"}, {143, 1, "DEV_MCU_MCSPI1_BUS_CLKSPIREF_CLK", "Input clock"}, {143, 2, "DEV_MCU_MCSPI1_BUS_VBUSP_CLK", "Input clock"}, {143, 3, "DEV_MCU_MCSPI1_BUS_IO_CLKSPIO_CLK", "Output clock"}, {144, 0, "DEV_MCU_MCSPI2_BUS_CLKSPIREF_CLK", "Input clock"}, {144, 1, "DEV_MCU_MCSPI2_BUS_VBUSP_CLK", "Input clock"}, {144, 2, "DEV_MCU_MCSPI2_BUS_IO_CLKSPII_CLK", "Input clock"}, {144, 3, "DEV_MCU_MCSPI2_BUS_IO_CLKSPIO_CLK", "Output clock"}, {116, 0, "DEV_MCU_MSRAM0_BUS_CCLK_CLK", "Input clock"}, {116, 1, "DEV_MCU_MSRAM0_BUS_VCLK_CLK", "Input clock"}, {119, 1, "DEV_MCU_NAVSS0_BUS_CPSW0CLK", "Input clock"}, {119, 2, "DEV_MCU_NAVSS0_BUS_MODSS_VD2CLK", "Input clock"}, {119, 3, "DEV_MCU_NAVSS0_BUS_PDMA_MCU1CLK", "Input clock"}, {75, 0, "DEV_MCU_PBIST0_BUS_CLK1_CLK", "Input clock"}, {75, 1, "DEV_MCU_PBIST0_BUS_CLK4_CLK", "Input clock"}, {75, 2, "DEV_MCU_PBIST0_BUS_CLK2_CLK", "Input clock"}, {125, 0, "DEV_MCU_PDMA0_BUS_VCLK", "Input clock"}, {126, 0, "DEV_MCU_PDMA1_BUS_VCLK", "Input clock"}, {108, 0, "DEV_MCU_PLL_MMR0_BUS_VBUSP_CLK", "Input clock"}, {127, 0, "DEV_MCU_PSRAM0_BUS_CLK_CLK", "Input clock"}, {78, 0, "DEV_MCU_ROM0_BUS_CLK_CLK", "Input clock"}, {134, 0, "DEV_MCU_RTI0_BUS_RTI_CLK", "Input muxed clock"}, {134, 1, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"}, {134, 2, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"}, {134, 3, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"}, {134, 4, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"}, {134, 5, "DEV_MCU_RTI0_BUS_VBUSP_CLK", "Input clock"}, {135, 0, "DEV_MCU_RTI1_BUS_RTI_CLK", "Input muxed clock"}, {135, 1, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"}, {135, 2, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"}, {135, 3, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"}, {135, 4, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"}, {135, 5, "DEV_MCU_RTI1_BUS_VBUSP_CLK", "Input clock"}, {109, 0, "DEV_MCU_SEC_MMR0_BUS_VBUSP_CLK", "Input clock"}, {35, 0, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, {35, 1, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"}, {35, 2, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"}, {35, 3, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"}, {35, 4, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"}, {35, 5, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"}, {35, 6, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"}, {35, 8, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"}, {35, 9, "DEV_MCU_TIMER0_BUS_TIMER_HCLK_CLK", "Input clock"}, {36, 0, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, {36, 1, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"}, {36, 2, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"}, {36, 3, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"}, {36, 4, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"}, {36, 5, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"}, {36, 6, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"}, {36, 8, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"}, {36, 9, "DEV_MCU_TIMER1_BUS_TIMER_HCLK_CLK", "Input clock"}, {37, 0, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, {37, 1, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"}, {37, 2, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"}, {37, 3, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"}, {37, 4, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"}, {37, 5, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"}, {37, 6, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"}, {37, 8, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"}, {37, 9, "DEV_MCU_TIMER2_BUS_TIMER_HCLK_CLK", "Input clock"}, {38, 0, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, {38, 1, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"}, {38, 2, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"}, {38, 3, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"}, {38, 4, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"}, {38, 5, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"}, {38, 6, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"}, {38, 8, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"}, {38, 9, "DEV_MCU_TIMER3_BUS_TIMER_HCLK_CLK", "Input clock"}, {149, 0, "DEV_MCU_UART0_BUS_FCLK_CLK", "Input muxed clock"}, {149, 1, "DEV_MCU_UART0_BUS_FCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_MCU_UART0_BUS_FCLK_CLK"}, {149, 2, "DEV_MCU_UART0_BUS_FCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_MCU_UART0_BUS_FCLK_CLK"}, {149, 3, "DEV_MCU_UART0_BUS_VBUSP_CLK", "Input clock"}, {47, 0, "DEV_MMCSD0_BUS_EMMCSDSS_VBUS_CLK", "Input clock"}, {47, 1, "DEV_MMCSD0_BUS_EMMCSDSS_XIN_CLK", "Input clock"}, {48, 0, "DEV_MMCSD1_BUS_EMMCSDSS_VBUS_CLK", "Input clock"}, {48, 1, "DEV_MMCSD1_BUS_EMMCSDSS_XIN_CLK", "Input clock"}, {118, 1, "DEV_NAVSS0_BUS_ICSS_G2CLK", "Input clock"}, {118, 2, "DEV_NAVSS0_BUS_ICSS_G0CLK", "Input clock"}, {118, 3, "DEV_NAVSS0_BUS_RCLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Input clock"}, {118, 4, "DEV_NAVSS0_BUS_MSMC0CLK", "Input clock"}, {118, 5, "DEV_NAVSS0_BUS_RCLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Input clock"}, {118, 6, "DEV_NAVSS0_BUS_RCLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Input clock"}, {118, 8, "DEV_NAVSS0_BUS_RCLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Input clock"}, {118, 9, "DEV_NAVSS0_BUS_PDMA_MAIN1CLK", "Input clock"}, {118, 10, "DEV_NAVSS0_BUS_NBSS_VCLK", "Input clock"}, {118, 11, "DEV_NAVSS0_BUS_RCLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Input clock"}, {118, 12, "DEV_NAVSS0_BUS_NBSS_VD2CLK", "Input clock"}, {118, 13, "DEV_NAVSS0_BUS_ICSS_G1CLK", "Input clock"}, {118, 14, "DEV_NAVSS0_BUS_RCLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1_OUT", "Input clock"}, {216, 0, "DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_PLL_CLK", "Input clock"}, {216, 1, "DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_0_FWD_P_CLK_BUS_IN1_DSS_BUS_OUT0", "Input clock"}, {216, 2, "DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_0_FWD_P_CLK_BUS_IN0_DSS_BUS_OUT0", "Input clock"}, {73, 0, "DEV_PBIST0_BUS_CLK1_CLK", "Input clock"}, {73, 1, "DEV_PBIST0_BUS_CLK4_CLK", "Input clock"}, {73, 2, "DEV_PBIST0_BUS_CLK2_CLK", "Input clock"}, {74, 0, "DEV_PBIST1_BUS_CLK1_CLK", "Input clock"}, {74, 1, "DEV_PBIST1_BUS_CLK4_CLK", "Input clock"}, {74, 2, "DEV_PBIST1_BUS_CLK2_CLK", "Input clock"}, {120, 0, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1_OUT", "Input clock"}, {120, 1, "DEV_PCIE0_BUS_PCIE_CBA_CLK", "Input clock"}, {120, 2, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Input clock"}, {120, 3, "DEV_PCIE0_BUS_PCIE_TXI0_CLK", "Input clock"}, {120, 4, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Input clock"}, {120, 5, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Input clock"}, {120, 6, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Input clock"}, {120, 7, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Input clock"}, {120, 8, "DEV_PCIE0_BUS_PCIE_TXR1_CLK", "Output clock"}, {120, 9, "DEV_PCIE0_BUS_PCIE_TXR0_CLK", "Output clock"}, {121, 0, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1_OUT", "Input clock"}, {121, 1, "DEV_PCIE1_BUS_PCIE_CBA_CLK", "Input clock"}, {121, 2, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Input clock"}, {121, 3, "DEV_PCIE1_BUS_PCIE_TXI0_CLK", "Input clock"}, {121, 4, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Input clock"}, {121, 5, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Input clock"}, {121, 6, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Input clock"}, {121, 7, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Input clock"}, {121, 8, "DEV_PCIE1_BUS_PCIE_TXR0_CLK", "Output clock"}, {123, 0, "DEV_PDMA0_BUS_VCLK", "Input clock"}, {124, 0, "DEV_PDMA1_BUS_VCLK", "Input clock"}, {122, 0, "DEV_PDMA_DEBUG0_BUS_VCLK", "Input clock"}, {76, 0, "DEV_PLLCTRL0_BUS_VBUS_SLV_REFCLK_CLK", "Input clock"}, {76, 1, "DEV_PLLCTRL0_BUS_PLL_CLKOUT_CLK", "Input clock"}, {76, 2, "DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK", "Input muxed clock"}, {76, 3, "DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK"}, {76, 4, "DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK"}, {101, 0, "DEV_PLL_MMR0_BUS_VBUSP_CLK", "Input clock"}, {62, 0, "DEV_PRU_ICSSG0_BUS_RGMII_MHZ_5_CLK", "Input clock"}, {62, 1, "DEV_PRU_ICSSG0_BUS_WIZ1_TX_SLV_CLK", "Input clock"}, {62, 2, "DEV_PRU_ICSSG0_BUS_WIZ0_RX_SLV_CLK", "Input clock"}, {62, 3, "DEV_PRU_ICSSG0_BUS_VCLK_CLK", "Input clock"}, {62, 4, "DEV_PRU_ICSSG0_BUS_UCLK_CLK", "Input clock"}, {62, 5, "DEV_PRU_ICSSG0_BUS_WIZ0_TX_SLV_CLK", "Input clock"}, {62, 6, "DEV_PRU_ICSSG0_BUS_WIZ1_RX_SLV_CLK", "Input clock"}, {62, 8, "DEV_PRU_ICSSG0_BUS_RGMII_MHZ_250_CLK", "Input clock"}, {62, 9, "DEV_PRU_ICSSG0_BUS_RGMII_MHZ_50_CLK", "Input clock"}, {62, 10, "DEV_PRU_ICSSG0_BUS_IEP_CLK", "Input muxed clock"}, {62, 11, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"}, {62, 12, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"}, {62, 13, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"}, {62, 14, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"}, {62, 15, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"}, {62, 16, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"}, {62, 17, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"}, {62, 18, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"}, {62, 19, "DEV_PRU_ICSSG0_BUS_CORE_CLK", "Input muxed clock"}, {62, 20, "DEV_PRU_ICSSG0_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_CORE_CLK"}, {62, 21, "DEV_PRU_ICSSG0_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_CORE_CLK"}, {63, 0, "DEV_PRU_ICSSG1_BUS_RGMII_MHZ_5_CLK", "Input clock"}, {63, 1, "DEV_PRU_ICSSG1_BUS_WIZ1_TX_SLV_CLK", "Input clock"}, {63, 2, "DEV_PRU_ICSSG1_BUS_WIZ0_RX_SLV_CLK", "Input clock"}, {63, 3, "DEV_PRU_ICSSG1_BUS_VCLK_CLK", "Input clock"}, {63, 4, "DEV_PRU_ICSSG1_BUS_UCLK_CLK", "Input clock"}, {63, 5, "DEV_PRU_ICSSG1_BUS_WIZ0_TX_SLV_CLK", "Input clock"}, {63, 6, "DEV_PRU_ICSSG1_BUS_WIZ1_RX_SLV_CLK", "Input clock"}, {63, 8, "DEV_PRU_ICSSG1_BUS_RGMII_MHZ_250_CLK", "Input clock"}, {63, 9, "DEV_PRU_ICSSG1_BUS_RGMII_MHZ_50_CLK", "Input clock"}, {63, 10, "DEV_PRU_ICSSG1_BUS_IEP_CLK", "Input muxed clock"}, {63, 11, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"}, {63, 12, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"}, {63, 13, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"}, {63, 14, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"}, {63, 15, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"}, {63, 16, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"}, {63, 17, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"}, {63, 18, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"}, {63, 19, "DEV_PRU_ICSSG1_BUS_CORE_CLK", "Input muxed clock"}, {63, 20, "DEV_PRU_ICSSG1_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_CORE_CLK"}, {63, 21, "DEV_PRU_ICSSG1_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_CORE_CLK"}, {64, 0, "DEV_PRU_ICSSG2_BUS_RGMII_MHZ_5_CLK", "Input clock"}, {64, 1, "DEV_PRU_ICSSG2_BUS_WIZ1_TX_SLV_CLK", "Input clock"}, {64, 2, "DEV_PRU_ICSSG2_BUS_WIZ0_RX_SLV_CLK", "Input clock"}, {64, 3, "DEV_PRU_ICSSG2_BUS_VCLK_CLK", "Input clock"}, {64, 4, "DEV_PRU_ICSSG2_BUS_UCLK_CLK", "Input clock"}, {64, 5, "DEV_PRU_ICSSG2_BUS_WIZ0_TX_SLV_CLK", "Input clock"}, {64, 6, "DEV_PRU_ICSSG2_BUS_WIZ1_RX_SLV_CLK", "Input clock"}, {64, 8, "DEV_PRU_ICSSG2_BUS_RGMII_MHZ_250_CLK", "Input clock"}, {64, 9, "DEV_PRU_ICSSG2_BUS_RGMII_MHZ_50_CLK", "Input clock"}, {64, 10, "DEV_PRU_ICSSG2_BUS_IEP_CLK", "Input muxed clock"}, {64, 11, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"}, {64, 12, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"}, {64, 13, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"}, {64, 14, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"}, {64, 15, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"}, {64, 16, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"}, {64, 17, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"}, {64, 18, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"}, {64, 19, "DEV_PRU_ICSSG2_BUS_CORE_CLK", "Input muxed clock"}, {64, 20, "DEV_PRU_ICSSG2_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_CORE_CLK"}, {64, 21, "DEV_PRU_ICSSG2_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_CORE_CLK"}, {64, 25, "DEV_PRU_ICSSG2_BUS_WIZ1_TX_MST_CLK", "Output clock"}, {64, 26, "DEV_PRU_ICSSG2_BUS_WIZ0_TX_MST_CLK", "Output clock"}, {70, 0, "DEV_PSC0_BUS_CLK", "Input clock"}, {70, 1, "DEV_PSC0_BUS_SLOW_CLK", "Input clock"}, {128, 0, "DEV_PSRAMECC0_BUS_CLK_CLK", "Input clock"}, {130, 0, "DEV_RTI0_BUS_RTI_CLK", "Input muxed clock"}, {130, 1, "DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"}, {130, 2, "DEV_RTI0_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"}, {130, 3, "DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"}, {130, 4, "DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"}, {130, 5, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"}, {130, 6, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"}, {130, 7, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"}, {130, 8, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"}, {130, 9, "DEV_RTI0_BUS_VBUSP_CLK", "Input clock"}, {131, 0, "DEV_RTI1_BUS_RTI_CLK", "Input muxed clock"}, {131, 1, "DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"}, {131, 2, "DEV_RTI1_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"}, {131, 3, "DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"}, {131, 4, "DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"}, {131, 5, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"}, {131, 6, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"}, {131, 7, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"}, {131, 8, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"}, {131, 9, "DEV_RTI1_BUS_VBUSP_CLK", "Input clock"}, {132, 0, "DEV_RTI2_BUS_RTI_CLK", "Input muxed clock"}, {132, 1, "DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"}, {132, 2, "DEV_RTI2_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"}, {132, 3, "DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"}, {132, 4, "DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"}, {132, 5, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"}, {132, 6, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"}, {132, 7, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"}, {132, 8, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"}, {132, 9, "DEV_RTI2_BUS_VBUSP_CLK", "Input clock"}, {133, 0, "DEV_RTI3_BUS_RTI_CLK", "Input muxed clock"}, {133, 1, "DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"}, {133, 2, "DEV_RTI3_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"}, {133, 3, "DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"}, {133, 4, "DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"}, {133, 5, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"}, {133, 6, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"}, {133, 7, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"}, {133, 8, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"}, {133, 9, "DEV_RTI3_BUS_VBUSP_CLK", "Input clock"}, {136, 0, "DEV_SA2_UL0_BUS_PKA_IN_CLK", "Input clock"}, {136, 1, "DEV_SA2_UL0_BUS_X1_CLK", "Input clock"}, {136, 2, "DEV_SA2_UL0_BUS_X2_CLK", "Input clock"}, {153, 0, "DEV_SERDES0_BUS_IP3_LN0_TXRCLK", "Input clock"}, {153, 2, "DEV_SERDES0_BUS_CLK", "Input clock"}, {153, 3, "DEV_SERDES0_BUS_IP2_LN0_TXRCLK", "Input clock"}, {153, 4, "DEV_SERDES0_BUS_LI_REFCLK", "Input muxed clock"}, {153, 5, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"}, {153, 6, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"}, {153, 7, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"}, {153, 8, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"}, {153, 10, "DEV_SERDES0_BUS_LN0_TXCLK", "Output clock"}, {153, 11, "DEV_SERDES0_BUS_LN0_RXCLK", "Output clock"}, {154, 0, "DEV_SERDES1_BUS_IP3_LN0_TXRCLK", "Input clock"}, {154, 2, "DEV_SERDES1_BUS_CLK", "Input clock"}, {154, 3, "DEV_SERDES1_BUS_IP1_LN0_TXRCLK", "Input clock"}, {154, 4, "DEV_SERDES1_BUS_IP2_LN0_TXRCLK", "Input clock"}, {154, 5, "DEV_SERDES1_BUS_RI_REFCLK", "Input muxed clock"}, {154, 6, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"}, {154, 7, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"}, {154, 8, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"}, {154, 9, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"}, {154, 11, "DEV_SERDES1_BUS_LN0_TXCLK", "Output clock"}, {154, 12, "DEV_SERDES1_BUS_LN0_RXCLK", "Output clock"}, {8, 0, "DEV_STM0_BUS_CORE_CLK", "Input clock"}, {8, 1, "DEV_STM0_BUS_ATB_CLK", "Input clock"}, {8, 2, "DEV_STM0_BUS_VBUSP_CLK", "Input clock"}, {23, 0, "DEV_TIMER0_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, {23, 1, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, {23, 2, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, {23, 3, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, {23, 4, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, {23, 5, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, {23, 6, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, {23, 7, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, {23, 8, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, {23, 9, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, {23, 10, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, {23, 11, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, {23, 12, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, {23, 17, "DEV_TIMER0_BUS_TIMER_HCLK_CLK", "Input clock"}, {24, 0, "DEV_TIMER1_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, {24, 1, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, {24, 2, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, {24, 3, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, {24, 4, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, {24, 5, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, {24, 6, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, {24, 7, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, {24, 8, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, {24, 9, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, {24, 10, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, {24, 11, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, {24, 12, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, {24, 17, "DEV_TIMER1_BUS_TIMER_HCLK_CLK", "Input clock"}, {25, 0, "DEV_TIMER10_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, {25, 1, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, {25, 2, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, {25, 3, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, {25, 4, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, {25, 5, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, {25, 6, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, {25, 7, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, {25, 8, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, {25, 9, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, {25, 10, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, {25, 11, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, {25, 12, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, {25, 17, "DEV_TIMER10_BUS_TIMER_HCLK_CLK", "Input clock"}, {26, 0, "DEV_TIMER11_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, {26, 1, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, {26, 2, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, {26, 3, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, {26, 4, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, {26, 5, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, {26, 6, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, {26, 7, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, {26, 8, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, {26, 9, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, {26, 10, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, {26, 11, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, {26, 12, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, {26, 17, "DEV_TIMER11_BUS_TIMER_HCLK_CLK", "Input clock"}, {27, 0, "DEV_TIMER2_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, {27, 1, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, {27, 2, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, {27, 3, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, {27, 4, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, {27, 5, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, {27, 6, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, {27, 7, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, {27, 8, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, {27, 9, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, {27, 10, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, {27, 11, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, {27, 12, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, {27, 17, "DEV_TIMER2_BUS_TIMER_HCLK_CLK", "Input clock"}, {28, 0, "DEV_TIMER3_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, {28, 1, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, {28, 2, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, {28, 3, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, {28, 4, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, {28, 5, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, {28, 6, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, {28, 7, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, {28, 8, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, {28, 9, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, {28, 10, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, {28, 11, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, {28, 12, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, {28, 17, "DEV_TIMER3_BUS_TIMER_HCLK_CLK", "Input clock"}, {29, 0, "DEV_TIMER4_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, {29, 1, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, {29, 2, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, {29, 3, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, {29, 4, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, {29, 5, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, {29, 6, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, {29, 7, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, {29, 8, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, {29, 9, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, {29, 10, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, {29, 11, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, {29, 12, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, {29, 17, "DEV_TIMER4_BUS_TIMER_HCLK_CLK", "Input clock"}, {30, 0, "DEV_TIMER5_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, {30, 1, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, {30, 2, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, {30, 3, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, {30, 4, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, {30, 5, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, {30, 6, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, {30, 7, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, {30, 8, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, {30, 9, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, {30, 10, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, {30, 11, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, {30, 12, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, {30, 17, "DEV_TIMER5_BUS_TIMER_HCLK_CLK", "Input clock"}, {31, 0, "DEV_TIMER6_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, {31, 1, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, {31, 2, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, {31, 3, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, {31, 4, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, {31, 5, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, {31, 6, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, {31, 7, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, {31, 8, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, {31, 9, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, {31, 10, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, {31, 11, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, {31, 12, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, {31, 17, "DEV_TIMER6_BUS_TIMER_HCLK_CLK", "Input clock"}, {32, 0, "DEV_TIMER7_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, {32, 1, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, {32, 2, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, {32, 3, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, {32, 4, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, {32, 5, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, {32, 6, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, {32, 7, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, {32, 8, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, {32, 9, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, {32, 10, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, {32, 11, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, {32, 12, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, {32, 17, "DEV_TIMER7_BUS_TIMER_HCLK_CLK", "Input clock"}, {33, 0, "DEV_TIMER8_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, {33, 1, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, {33, 2, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, {33, 3, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, {33, 4, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, {33, 5, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, {33, 6, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, {33, 7, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, {33, 8, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, {33, 9, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, {33, 10, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, {33, 11, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, {33, 12, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, {33, 17, "DEV_TIMER8_BUS_TIMER_HCLK_CLK", "Input clock"}, {34, 0, "DEV_TIMER9_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, {34, 1, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, {34, 2, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, {34, 3, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, {34, 4, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, {34, 5, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, {34, 6, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, {34, 7, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, {34, 8, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, {34, 9, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, {34, 10, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, {34, 11, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, {34, 12, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, {34, 17, "DEV_TIMER9_BUS_TIMER_HCLK_CLK", "Input clock"}, {145, 0, "DEV_TIMESYNC_INTRTR0_BUS_INTR_CLK", "Input clock"}, {146, 0, "DEV_UART0_BUS_FCLK_CLK", "Input clock"}, {146, 1, "DEV_UART0_BUS_VBUSP_CLK", "Input clock"}, {147, 0, "DEV_UART1_BUS_FCLK_CLK", "Input clock"}, {147, 1, "DEV_UART1_BUS_VBUSP_CLK", "Input clock"}, {148, 0, "DEV_UART2_BUS_FCLK_CLK", "Input clock"}, {148, 1, "DEV_UART2_BUS_VBUSP_CLK", "Input clock"}, {151, 0, "DEV_USB3SS0_BUS_SUSP_CLK", "Input clock"}, {151, 1, "DEV_USB3SS0_BUS_PHY2_REFCLK960M_CLK", "Input clock"}, {151, 2, "DEV_USB3SS0_BUS_REF_CLK", "Input muxed clock"}, {151, 3, "DEV_USB3SS0_BUS_REF_CLK_PARENT_HFOSC_SEL_BUS_OUT0", "Parent input clock option to DEV_USB3SS0_BUS_REF_CLK"}, {151, 4, "DEV_USB3SS0_BUS_REF_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK48", "Parent input clock option to DEV_USB3SS0_BUS_REF_CLK"}, {151, 5, "DEV_USB3SS0_BUS_HSIC_CLK_CLK", "Input clock"}, {151, 6, "DEV_USB3SS0_BUS_BUS_CLK", "Input clock"}, {151, 7, "DEV_USB3SS0_BUS_PIPE3_TXB_CLK", "Input muxed clock"}, {151, 8, "DEV_USB3SS0_BUS_PIPE3_TXB_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_USB3SS0_BUS_PIPE3_TXB_CLK"}, {151, 9, "DEV_USB3SS0_BUS_PIPE3_TXB_CLK_PARENT_USB0_PIPE3_CLK_SEL_DIV_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_USB3SS0_BUS_PIPE3_TXB_CLK"}, {151, 10, "DEV_USB3SS0_BUS_UTMI_CLK_CLK", "Input clock"}, {152, 0, "DEV_USB3SS1_BUS_SUSP_CLK", "Input clock"}, {152, 1, "DEV_USB3SS1_BUS_PHY2_REFCLK960M_CLK", "Input clock"}, {152, 2, "DEV_USB3SS1_BUS_REF_CLK", "Input muxed clock"}, {152, 3, "DEV_USB3SS1_BUS_REF_CLK_PARENT_HFOSC_SEL_BUS_OUT0", "Parent input clock option to DEV_USB3SS1_BUS_REF_CLK"}, {152, 4, "DEV_USB3SS1_BUS_REF_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK48", "Parent input clock option to DEV_USB3SS1_BUS_REF_CLK"}, {152, 5, "DEV_USB3SS1_BUS_HSIC_CLK_CLK", "Input clock"}, {152, 6, "DEV_USB3SS1_BUS_BUS_CLK", "Input clock"}, {152, 7, "DEV_USB3SS1_BUS_PIPE3_TXB_CLK", "Input clock"}, {152, 8, "DEV_USB3SS1_BUS_UTMI_CLK_CLK", "Input clock"}, {94, 0, "DEV_WKUP_CBASS0_BUS_WKUP_MCU_PLL_OUT_2_CLK", "Input clock"}, {94, 1, "DEV_WKUP_CBASS0_BUS_WKUP_MCU_PLL_OUT_4_CLK", "Input clock"}, {96, 0, "DEV_WKUP_CBASS_FW0_BUS_WKUP_MCU_PLL_OUT_2_CLK", "Input clock"}, {155, 0, "DEV_WKUP_CTRL_MMR0_BUS_VBUSP_CLK", "Input clock"}, {95, 0, "DEV_WKUP_ECC_AGGR0_BUS_AGGR_CLK", "Input clock"}, {54, 0, "DEV_WKUP_ESM0_BUS_CLK", "Input clock"}, {59, 0, "DEV_WKUP_GPIO0_BUS_MMR_CLK", "Input muxed clock"}, {59, 1, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"}, {59, 2, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK4_DUP0", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"}, {59, 3, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"}, {59, 4, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"}, {156, 0, "DEV_WKUP_GPIOMUX_INTRTR0_BUS_INTR_CLK", "Input clock"}, {115, 0, "DEV_WKUP_I2C0_BUS_CLK", "Input clock"}, {115, 1, "DEV_WKUP_I2C0_BUS_PISYS_CLK", "Input muxed clock"}, {115, 2, "DEV_WKUP_I2C0_BUS_PISYS_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_WKUP_I2C0_BUS_PISYS_CLK"}, {115, 3, "DEV_WKUP_I2C0_BUS_PISYS_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_WKUP_I2C0_BUS_PISYS_CLK"}, {77, 0, "DEV_WKUP_PLLCTRL0_BUS_VBUS_SLV_REFCLK_CLK", "Input clock"}, {77, 1, "DEV_WKUP_PLLCTRL0_BUS_PLL_CLKOUT_CLK", "Input clock"}, {77, 2, "DEV_WKUP_PLLCTRL0_BUS_PLL_REFCLK_CLK", "Input clock"}, {79, 0, "DEV_WKUP_PSC0_BUS_CLK", "Input clock"}, {79, 1, "DEV_WKUP_PSC0_BUS_SLOW_CLK", "Input clock"}, {150, 0, "DEV_WKUP_UART0_BUS_FCLK_CLK", "Input muxed clock"}, {150, 1, "DEV_WKUP_UART0_BUS_FCLK_CLK_PARENT_WKUPUSART_CLK_SEL_BUS_OUT0", "Parent input clock option to DEV_WKUP_UART0_BUS_FCLK_CLK"}, {150, 2, "DEV_WKUP_UART0_BUS_FCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_WKUP_UART0_BUS_FCLK_CLK"}, {150, 3, "DEV_WKUP_UART0_BUS_VBUSP_CLK", "Input clock"}, {80, 0, "DEV_WKUP_VTM0_BUS_FIX_REF_CLK", "Input clock"}, {80, 1, "DEV_WKUP_VTM0_BUS_VBUSP_CLK", "Input clock"}, }; k3conf_0.3/soc/am65x_sr2/am65x_sr2_rm_info.c0000664000175000017500000000760114375734376015507 0ustar /* * AM65X_SR2 RM Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_rm_info am65x_sr2_rm_info[] = { {0x00C0, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x1840, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x1880, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x1900, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x2440, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x2700, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x2CCA, "RESASG_SUBTYPE_IA_VINT"}, {0x2CCD, "RESASG_SUBTYPE_GLOBAL_EVENT_SEVT"}, {0x2D0A, "RESASG_SUBTYPE_IA_VINT"}, {0x2D0D, "RESASG_SUBTYPE_GLOBAL_EVENT_SEVT"}, {0x2D4A, "RESASG_SUBTYPE_IA_VINT"}, {0x2D4D, "RESASG_SUBTYPE_GLOBAL_EVENT_SEVT"}, {0x2D80, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x2E40, "RESASG_SUBTYPE_PROXY_PROXIES"}, {0x2EC0, "RESASG_SUBTYPE_RA_ERROR_OES"}, {0x2EC1, "RESASG_SUBTYPE_RA_GP"}, {0x2EC2, "RESASG_SUBTYPE_RA_UDMAP_RX"}, {0x2EC3, "RESASG_SUBTYPE_RA_UDMAP_TX"}, {0x2EC4, "RESASG_SUBTYPE_RA_UDMAP_TX_EXT"}, {0x2EC5, "RESASG_SUBTYPE_RA_UDMAP_RX_H"}, {0x2EC7, "RESASG_SUBTYPE_RA_UDMAP_TX_H"}, {0x2ECA, "RESASG_SUBTYPE_RA_VIRTID"}, {0x2ECB, "RESASG_SUBTYPE_RA_MONITORS"}, {0x2F00, "RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON"}, {0x2F01, "RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES"}, {0x2F02, "RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER"}, {0x2F03, "RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG"}, {0x2F0A, "RESASG_SUBTYPE_UDMAP_RX_CHAN"}, {0x2F0B, "RESASG_SUBTYPE_UDMAP_RX_HCHAN"}, {0x2F0D, "RESASG_SUBTYPE_UDMAP_TX_CHAN"}, {0x2F0E, "RESASG_SUBTYPE_UDMAP_TX_ECHAN"}, {0x2F0F, "RESASG_SUBTYPE_UDMAP_TX_HCHAN"}, {0x2F4A, "RESASG_SUBTYPE_IA_VINT"}, {0x2F4D, "RESASG_SUBTYPE_GLOBAL_EVENT_SEVT"}, {0x2F80, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x2FC0, "RESASG_SUBTYPE_PROXY_PROXIES"}, {0x3080, "RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON"}, {0x3081, "RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES"}, {0x3082, "RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER"}, {0x3083, "RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG"}, {0x308A, "RESASG_SUBTYPE_UDMAP_RX_CHAN"}, {0x308B, "RESASG_SUBTYPE_UDMAP_RX_HCHAN"}, {0x308D, "RESASG_SUBTYPE_UDMAP_TX_CHAN"}, {0x308F, "RESASG_SUBTYPE_UDMAP_TX_HCHAN"}, {0x30C0, "RESASG_SUBTYPE_RA_ERROR_OES"}, {0x30C1, "RESASG_SUBTYPE_RA_GP"}, {0x30C2, "RESASG_SUBTYPE_RA_UDMAP_RX"}, {0x30C3, "RESASG_SUBTYPE_RA_UDMAP_TX"}, {0x30C5, "RESASG_SUBTYPE_RA_UDMAP_RX_H"}, {0x30C7, "RESASG_SUBTYPE_RA_UDMAP_TX_H"}, {0x30CA, "RESASG_SUBTYPE_RA_VIRTID"}, {0x30CB, "RESASG_SUBTYPE_RA_MONITORS"}, }; k3conf_0.3/soc/am65x_sr2/am65x_sr2_clocks_info.h0000664000175000017500000000350614504336513016335 0ustar /* * AM65X_SR2 Clocks Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM65X_SR2_CLOCKS_INFO_H #define __AM65X_SR2_CLOCKS_INFO_H #define AM65X_SR2_MAX_CLOCKS 1010 extern struct ti_sci_clocks_info am65x_sr2_clocks_info[]; #endif /* __AM65X_SR2_CLOCKS_INFO_H */ k3conf_0.3/soc/am65x_sr2/am65x_sr2_processors_info.c0000664000175000017500000000364114375734376017273 0ustar /* * AM65X_SR2 Processor Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_processors_info am65x_sr2_processors_info[] = { {202, 0, 0x20, "A53_CL0_C0"}, {203, 0, 0x21, "A53_CL0_C1"}, {204, 0, 0x22, "A53_CL1_C0"}, {205, 0, 0x23, "A53_CL1_C1"}, {159, 0, 0x01, "R5_CL0_C0"}, {245, 0, 0x02, "R5_CL0_C1"}, }; k3conf_0.3/soc/am62x/0000775000175000017500000000000014504336530011267 5ustar k3conf_0.3/soc/am62x/am62x_sec_proxy_info.c0000664000175000017500000000654414375734376015527 0ustar /* * AM62X Sec Proxy Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_sec_proxy_info am62x_main_sp_info[] = { {70, "read", 35, "DM", "nonsec_low_priority_rx"}, {69, "write", 11, "DM", "nonsec_MAIN_0_R5_1_response_tx"}, {68, "write", 2, "DM", "nonsec_MAIN_0_R5_3_response_tx"}, {67, "write", 6, "DM", "nonsec_A53_1_response_tx"}, {66, "write", 6, "DM", "nonsec_A53_2_response_tx"}, {65, "write", 6, "DM", "nonsec_A53_3_response_tx"}, {64, "write", 6, "DM", "nonsec_M4_0_response_tx"}, {63, "write", 2, "DM", "nonsec_GPU_response_tx"}, {62, "write", 2, "DM", "nonsec_ICSSG_0_response_tx"}, {61, "write", 4, "DM", "nonsec_TIFS2DM_response_tx"}, {0, "read", 11, "MAIN_0_R5_0", "response"}, {1, "write", 10, "MAIN_0_R5_0", "low_priority"}, {2, "read", 11, "MAIN_0_R5_1", "response"}, {3, "write", 10, "MAIN_0_R5_1", "low_priority"}, {4, "read", 2, "MAIN_0_R5_2", "response"}, {5, "write", 1, "MAIN_0_R5_2", "low_priority"}, {6, "read", 2, "MAIN_0_R5_3", "response"}, {7, "write", 1, "MAIN_0_R5_3", "low_priority"}, {8, "read", 11, "A53_0", "response"}, {9, "write", 10, "A53_0", "low_priority"}, {10, "read", 6, "A53_1", "response"}, {11, "write", 5, "A53_1", "low_priority"}, {12, "read", 6, "A53_2", "response"}, {13, "write", 5, "A53_2", "low_priority"}, {14, "read", 6, "A53_3", "response"}, {15, "write", 5, "A53_3", "low_priority"}, {16, "read", 6, "M4_0", "response"}, {17, "write", 5, "M4_0", "low_priority"}, {18, "read", 2, "GPU", "response"}, {19, "write", 1, "GPU", "low_priority"}, {20, "read", 2, "ICSSG_0", "response"}, {21, "write", 1, "ICSSG_0", "low_priority"}, {22, "read", 4, "DM2TIFS", "response"}, {23, "write", 2, "DM2TIFS", "low_priority"}, {24, "read", 4, "TIFS2DM", "response"}, {25, "write", 2, "TIFS2DM", "low_priority"}, }; k3conf_0.3/soc/am62x/am62x_sec_proxy_info.h0000664000175000017500000000351014504336513015503 0ustar /* * AM62X Sec Proxy Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM62X_SEC_PROXY_INFO_H #define __AM62X_SEC_PROXY_INFO_H #define AM62X_MAIN_SEC_PROXY_THREADS 36 extern struct ti_sci_sec_proxy_info am62x_main_sp_info[]; #endif /* __AM62X_SEC_PROXY_INFO_H */ k3conf_0.3/soc/am62x/am62x_clocks_info.c0000664000175000017500000022462614375734376014775 0ustar /* * AM62X Clocks Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_clocks_info am62x_clocks_info[] = { {166, 2, "DEV_A53SS0_A53_DIVH_CLK4_OBSCLK_OUT_CLK", "Output clock"}, {166, 3, "DEV_A53SS0_COREPAC_ARM_CLK_CLK", "Input clock"}, {166, 5, "DEV_A53SS0_PLL_CTRL_CLK", "Input clock"}, {135, 0, "DEV_A53SS0_CORE_0_A53_CORE0_ARM_CLK_CLK", "Input clock"}, {136, 0, "DEV_A53SS0_CORE_1_A53_CORE1_ARM_CLK_CLK", "Input clock"}, {137, 0, "DEV_A53SS0_CORE_2_A53_CORE2_ARM_CLK_CLK", "Input clock"}, {138, 0, "DEV_A53SS0_CORE_3_A53_CORE3_ARM_CLK_CLK", "Input clock"}, {172, 0, "DEV_A53_RS_BW_LIMITER0_CLK_CLK", "Input clock"}, {173, 0, "DEV_A53_WS_BW_LIMITER1_CLK_CLK", "Input clock"}, {157, 0, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN", "Input muxed clock"}, {157, 1, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 2, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 3, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 4, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 5, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 6, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 7, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 8, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 9, "DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT", "Output clock"}, {157, 10, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN", "Input muxed clock"}, {157, 11, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 12, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 13, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 14, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 15, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 16, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 17, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 18, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 19, "DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT", "Output clock"}, {157, 20, "DEV_BOARD0_CLKOUT0_IN", "Input muxed clock"}, {157, 21, "DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK5", "Parent input clock option to DEV_BOARD0_CLKOUT0_IN"}, {157, 22, "DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK10", "Parent input clock option to DEV_BOARD0_CLKOUT0_IN"}, {157, 23, "DEV_BOARD0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Output clock"}, {157, 24, "DEV_BOARD0_DDR0_CK0_IN", "Input clock"}, {157, 25, "DEV_BOARD0_DDR0_CK0_N_IN", "Input clock"}, {157, 27, "DEV_BOARD0_DDR0_CK0_OUT", "Output clock"}, {157, 33, "DEV_BOARD0_EXT_REFCLK1_OUT", "Output clock"}, {157, 34, "DEV_BOARD0_GPMC0_CLKLB_IN", "Input clock"}, {157, 35, "DEV_BOARD0_GPMC0_CLKLB_OUT", "Output clock"}, {157, 36, "DEV_BOARD0_GPMC0_CLK_IN", "Input clock"}, {157, 37, "DEV_BOARD0_GPMC0_FCLK_MUX_IN", "Input muxed clock"}, {157, 38, "DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_BOARD0_GPMC0_FCLK_MUX_IN"}, {157, 39, "DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK", "Parent input clock option to DEV_BOARD0_GPMC0_FCLK_MUX_IN"}, {157, 40, "DEV_BOARD0_I2C0_SCL_IN", "Input clock"}, {157, 41, "DEV_BOARD0_I2C0_SCL_OUT", "Output clock"}, {157, 42, "DEV_BOARD0_I2C1_SCL_IN", "Input clock"}, {157, 43, "DEV_BOARD0_I2C1_SCL_OUT", "Output clock"}, {157, 44, "DEV_BOARD0_I2C2_SCL_IN", "Input clock"}, {157, 45, "DEV_BOARD0_I2C2_SCL_OUT", "Output clock"}, {157, 46, "DEV_BOARD0_I2C3_SCL_IN", "Input clock"}, {157, 47, "DEV_BOARD0_I2C3_SCL_OUT", "Output clock"}, {157, 49, "DEV_BOARD0_MCASP0_ACLKR_IN", "Input clock"}, {157, 50, "DEV_BOARD0_MCASP0_ACLKR_OUT", "Output clock"}, {157, 51, "DEV_BOARD0_MCASP0_ACLKX_IN", "Input clock"}, {157, 52, "DEV_BOARD0_MCASP0_ACLKX_OUT", "Output clock"}, {157, 53, "DEV_BOARD0_MCASP0_AFSR_IN", "Input clock"}, {157, 54, "DEV_BOARD0_MCASP0_AFSX_IN", "Input clock"}, {157, 55, "DEV_BOARD0_MCASP1_ACLKR_IN", "Input clock"}, {157, 56, "DEV_BOARD0_MCASP1_ACLKR_OUT", "Output clock"}, {157, 57, "DEV_BOARD0_MCASP1_ACLKX_IN", "Input clock"}, {157, 58, "DEV_BOARD0_MCASP1_ACLKX_OUT", "Output clock"}, {157, 59, "DEV_BOARD0_MCASP1_AFSR_IN", "Input clock"}, {157, 60, "DEV_BOARD0_MCASP1_AFSX_IN", "Input clock"}, {157, 61, "DEV_BOARD0_MCASP2_ACLKR_IN", "Input clock"}, {157, 62, "DEV_BOARD0_MCASP2_ACLKR_OUT", "Output clock"}, {157, 63, "DEV_BOARD0_MCASP2_ACLKX_IN", "Input clock"}, {157, 64, "DEV_BOARD0_MCASP2_ACLKX_OUT", "Output clock"}, {157, 65, "DEV_BOARD0_MCASP2_AFSR_IN", "Input clock"}, {157, 66, "DEV_BOARD0_MCASP2_AFSX_IN", "Input clock"}, {157, 67, "DEV_BOARD0_MCU_EXT_REFCLK0_OUT", "Output clock"}, {157, 68, "DEV_BOARD0_MCU_I2C0_SCL_IN", "Input clock"}, {157, 69, "DEV_BOARD0_MCU_I2C0_SCL_OUT", "Output clock"}, {157, 70, "DEV_BOARD0_MCU_OBSCLK0_IN", "Input muxed clock"}, {157, 71, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"}, {157, 72, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"}, {157, 73, "DEV_BOARD0_MCU_SPI0_CLK_IN", "Input clock"}, {157, 75, "DEV_BOARD0_MCU_SPI1_CLK_IN", "Input clock"}, {157, 77, "DEV_BOARD0_MCU_SYSCLKOUT0_IN", "Input clock"}, {157, 78, "DEV_BOARD0_MCU_TIMER_IO0_IN", "Input clock"}, {157, 79, "DEV_BOARD0_MCU_TIMER_IO1_IN", "Input clock"}, {157, 80, "DEV_BOARD0_MCU_TIMER_IO2_IN", "Input clock"}, {157, 81, "DEV_BOARD0_MCU_TIMER_IO3_IN", "Input clock"}, {157, 82, "DEV_BOARD0_MDIO0_MDC_IN", "Input clock"}, {157, 83, "DEV_BOARD0_MMC0_CLKLB_IN", "Input clock"}, {157, 84, "DEV_BOARD0_MMC0_CLKLB_OUT", "Output clock"}, {157, 86, "DEV_BOARD0_MMC0_CLK_OUT", "Output clock"}, {157, 87, "DEV_BOARD0_MMC1_CLKLB_IN", "Input clock"}, {157, 88, "DEV_BOARD0_MMC1_CLKLB_OUT", "Output clock"}, {157, 89, "DEV_BOARD0_MMC1_CLK_IN", "Input clock"}, {157, 90, "DEV_BOARD0_MMC1_CLK_OUT", "Output clock"}, {157, 91, "DEV_BOARD0_MMC2_CLKLB_IN", "Input clock"}, {157, 92, "DEV_BOARD0_MMC2_CLKLB_OUT", "Output clock"}, {157, 93, "DEV_BOARD0_MMC2_CLK_IN", "Input clock"}, {157, 94, "DEV_BOARD0_MMC2_CLK_OUT", "Output clock"}, {157, 95, "DEV_BOARD0_OBSCLK0_IN", "Input clock"}, {157, 96, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 97, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 98, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 99, "DEV_BOARD0_OBSCLK0_IN_PARENT_SAM62_A53_512KB_WRAP_MAIN_0_ARM_COREPACK_0_A53_DIVH_CLK4_OBSCLK_OUT_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 100, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 101, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 102, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 103, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 104, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 105, "DEV_BOARD0_OBSCLK0_IN_PARENT_MAIN_OBSCLK0_MUX_SEL_DIV_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 106, "DEV_BOARD0_OBSCLK0_IN_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 107, "DEV_BOARD0_OBSCLK0_IN_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 108, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 109, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 110, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 111, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 112, "DEV_BOARD0_OBSCLK0_IN_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 113, "DEV_BOARD0_OBSCLK0_IN_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 128, "DEV_BOARD0_OSPI0_DQS_OUT", "Output clock"}, {157, 129, "DEV_BOARD0_OSPI0_LBCLKO_IN", "Input clock"}, {157, 130, "DEV_BOARD0_OSPI0_LBCLKO_OUT", "Output clock"}, {157, 131, "DEV_BOARD0_RGMII1_RXC_OUT", "Output clock"}, {157, 132, "DEV_BOARD0_RGMII1_TXC_IN", "Input clock"}, {157, 133, "DEV_BOARD0_RGMII1_TXC_OUT", "Output clock"}, {157, 134, "DEV_BOARD0_RGMII2_RXC_OUT", "Output clock"}, {157, 135, "DEV_BOARD0_RGMII2_TXC_IN", "Input clock"}, {157, 136, "DEV_BOARD0_RGMII2_TXC_OUT", "Output clock"}, {157, 137, "DEV_BOARD0_RMII1_REF_CLK_OUT", "Output clock"}, {157, 138, "DEV_BOARD0_RMII2_REF_CLK_OUT", "Output clock"}, {157, 139, "DEV_BOARD0_SPI0_CLK_IN", "Input clock"}, {157, 141, "DEV_BOARD0_SPI1_CLK_IN", "Input clock"}, {157, 143, "DEV_BOARD0_SPI2_CLK_IN", "Input clock"}, {157, 145, "DEV_BOARD0_SYSCLKOUT0_IN", "Input clock"}, {157, 146, "DEV_BOARD0_TCK_OUT", "Output clock"}, {157, 147, "DEV_BOARD0_TIMER_IO0_IN", "Input clock"}, {157, 148, "DEV_BOARD0_TIMER_IO1_IN", "Input clock"}, {157, 149, "DEV_BOARD0_TIMER_IO2_IN", "Input clock"}, {157, 150, "DEV_BOARD0_TIMER_IO3_IN", "Input clock"}, {157, 151, "DEV_BOARD0_TIMER_IO4_IN", "Input clock"}, {157, 152, "DEV_BOARD0_TIMER_IO5_IN", "Input clock"}, {157, 153, "DEV_BOARD0_TIMER_IO6_IN", "Input clock"}, {157, 154, "DEV_BOARD0_TIMER_IO7_IN", "Input clock"}, {157, 155, "DEV_BOARD0_TRC_CLK_IN", "Input clock"}, {157, 156, "DEV_BOARD0_VOUT0_EXTPCLKIN_OUT", "Output clock"}, {157, 157, "DEV_BOARD0_VOUT0_PCLK_IN", "Input clock"}, {157, 158, "DEV_BOARD0_WKUP_CLKOUT0_IN", "Input muxed clock"}, {157, 159, "DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_WKUP_CLKOUT0_IN"}, {157, 160, "DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_LFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_WKUP_CLKOUT0_IN"}, {157, 161, "DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_WKUP_CLKOUT0_IN"}, {157, 162, "DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_WKUP_CLKOUT0_IN"}, {157, 163, "DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT9_CLK", "Parent input clock option to DEV_BOARD0_WKUP_CLKOUT0_IN"}, {157, 164, "DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_BOARD0_WKUP_CLKOUT0_IN"}, {157, 165, "DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_BOARD0_WKUP_CLKOUT0_IN"}, {157, 166, "DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT_DUP0", "Parent input clock option to DEV_BOARD0_WKUP_CLKOUT0_IN"}, {193, 0, "DEV_CLK_32K_RC_SEL_DEV_VD_CLK", "Input muxed clock"}, {193, 1, "DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_CLK_32K_RC_SEL_DEV_VD_CLK"}, {193, 2, "DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_CLK_32K_RC_SEL_DEV_VD_CLK"}, {193, 3, "DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_CLK_32K_RC_SEL_DIV_CLKOUT", "Parent input clock option to DEV_CLK_32K_RC_SEL_DEV_VD_CLK"}, {193, 4, "DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_LFOSC0_CLKOUT", "Parent input clock option to DEV_CLK_32K_RC_SEL_DEV_VD_CLK"}, {1, 0, "DEV_CMP_EVENT_INTROUTER0_INTR_CLK", "Input clock"}, {13, 0, "DEV_CPSW0_CPPI_CLK_CLK", "Input clock"}, {13, 1, "DEV_CPSW0_CPTS_GENF0", "Output clock"}, {13, 2, "DEV_CPSW0_CPTS_GENF1", "Output clock"}, {13, 3, "DEV_CPSW0_CPTS_RFT_CLK", "Input muxed clock"}, {13, 4, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {13, 5, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {13, 6, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {13, 8, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {13, 9, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {13, 10, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {13, 11, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {13, 13, "DEV_CPSW0_GMII1_MR_CLK", "Input clock"}, {13, 14, "DEV_CPSW0_GMII1_MT_CLK", "Input clock"}, {13, 15, "DEV_CPSW0_GMII2_MR_CLK", "Input clock"}, {13, 16, "DEV_CPSW0_GMII2_MT_CLK", "Input clock"}, {13, 17, "DEV_CPSW0_GMII_RFT_CLK", "Input clock"}, {13, 18, "DEV_CPSW0_MDIO_MDCLK_O", "Output clock"}, {13, 19, "DEV_CPSW0_RGMII1_RXC_I", "Input clock"}, {13, 20, "DEV_CPSW0_RGMII1_TXC_I", "Input clock"}, {13, 21, "DEV_CPSW0_RGMII1_TXC_O", "Output clock"}, {13, 22, "DEV_CPSW0_RGMII2_RXC_I", "Input clock"}, {13, 23, "DEV_CPSW0_RGMII2_TXC_I", "Input clock"}, {13, 24, "DEV_CPSW0_RGMII2_TXC_O", "Output clock"}, {13, 25, "DEV_CPSW0_RGMII_MHZ_250_CLK", "Input clock"}, {13, 26, "DEV_CPSW0_RGMII_MHZ_50_CLK", "Input clock"}, {13, 27, "DEV_CPSW0_RGMII_MHZ_5_CLK", "Input clock"}, {13, 28, "DEV_CPSW0_RMII1_MHZ_50_CLK", "Input clock"}, {13, 29, "DEV_CPSW0_RMII2_MHZ_50_CLK", "Input clock"}, {14, 0, "DEV_CPT2_AGGR0_VCLK_CLK", "Input clock"}, {181, 0, "DEV_CPT2_AGGR1_VCLK_CLK", "Input clock"}, {182, 0, "DEV_CSI_RX_IF0_MAIN_CLK_CLK", "Input clock"}, {182, 2, "DEV_CSI_RX_IF0_PPI_RX_BYTE_CLK", "Input clock"}, {182, 3, "DEV_CSI_RX_IF0_VBUS_CLK_CLK", "Input clock"}, {182, 4, "DEV_CSI_RX_IF0_VP_CLK_CLK", "Input clock"}, {2, 0, "DEV_DBGSUSPENDROUTER0_INTR_CLK", "Input clock"}, {16, 0, "DEV_DCC0_DCC_CLKSRC0_CLK", "Input clock"}, {16, 1, "DEV_DCC0_DCC_CLKSRC1_CLK", "Input clock"}, {16, 2, "DEV_DCC0_DCC_CLKSRC2_CLK", "Input clock"}, {16, 3, "DEV_DCC0_DCC_CLKSRC3_CLK", "Input clock"}, {16, 4, "DEV_DCC0_DCC_CLKSRC4_CLK", "Input clock"}, {16, 5, "DEV_DCC0_DCC_CLKSRC5_CLK", "Input clock"}, {16, 6, "DEV_DCC0_DCC_CLKSRC6_CLK", "Input clock"}, {16, 7, "DEV_DCC0_DCC_CLKSRC7_CLK", "Input clock"}, {16, 8, "DEV_DCC0_DCC_INPUT00_CLK", "Input clock"}, {16, 9, "DEV_DCC0_DCC_INPUT01_CLK", "Input clock"}, {16, 10, "DEV_DCC0_DCC_INPUT02_CLK", "Input clock"}, {16, 11, "DEV_DCC0_DCC_INPUT10_CLK", "Input clock"}, {16, 12, "DEV_DCC0_VBUS_CLK", "Input clock"}, {17, 0, "DEV_DCC1_DCC_CLKSRC0_CLK", "Input clock"}, {17, 1, "DEV_DCC1_DCC_CLKSRC1_CLK", "Input clock"}, {17, 2, "DEV_DCC1_DCC_CLKSRC2_CLK", "Input clock"}, {17, 3, "DEV_DCC1_DCC_CLKSRC3_CLK", "Input clock"}, {17, 4, "DEV_DCC1_DCC_CLKSRC4_CLK", "Input clock"}, {17, 5, "DEV_DCC1_DCC_CLKSRC5_CLK", "Input clock"}, {17, 6, "DEV_DCC1_DCC_CLKSRC6_CLK", "Input clock"}, {17, 7, "DEV_DCC1_DCC_CLKSRC7_CLK", "Input clock"}, {17, 8, "DEV_DCC1_DCC_INPUT00_CLK", "Input clock"}, {17, 9, "DEV_DCC1_DCC_INPUT01_CLK", "Input clock"}, {17, 10, "DEV_DCC1_DCC_INPUT02_CLK", "Input clock"}, {17, 11, "DEV_DCC1_DCC_INPUT10_CLK", "Input clock"}, {17, 12, "DEV_DCC1_VBUS_CLK", "Input clock"}, {18, 0, "DEV_DCC2_DCC_CLKSRC0_CLK", "Input clock"}, {18, 1, "DEV_DCC2_DCC_CLKSRC1_CLK", "Input clock"}, {18, 2, "DEV_DCC2_DCC_CLKSRC2_CLK", "Input clock"}, {18, 3, "DEV_DCC2_DCC_CLKSRC3_CLK", "Input clock"}, {18, 4, "DEV_DCC2_DCC_CLKSRC4_CLK", "Input clock"}, {18, 5, "DEV_DCC2_DCC_CLKSRC5_CLK", "Input clock"}, {18, 6, "DEV_DCC2_DCC_CLKSRC6_CLK", "Input clock"}, {18, 7, "DEV_DCC2_DCC_CLKSRC7_CLK", "Input clock"}, {18, 8, "DEV_DCC2_DCC_INPUT00_CLK", "Input clock"}, {18, 9, "DEV_DCC2_DCC_INPUT01_CLK", "Input clock"}, {18, 10, "DEV_DCC2_DCC_INPUT02_CLK", "Input clock"}, {18, 11, "DEV_DCC2_DCC_INPUT10_CLK", "Input clock"}, {18, 12, "DEV_DCC2_VBUS_CLK", "Input clock"}, {19, 0, "DEV_DCC3_DCC_CLKSRC0_CLK", "Input clock"}, {19, 1, "DEV_DCC3_DCC_CLKSRC1_CLK", "Input clock"}, {19, 3, "DEV_DCC3_DCC_CLKSRC3_CLK", "Input clock"}, {19, 4, "DEV_DCC3_DCC_CLKSRC4_CLK", "Input clock"}, {19, 5, "DEV_DCC3_DCC_CLKSRC5_CLK", "Input clock"}, {19, 6, "DEV_DCC3_DCC_CLKSRC6_CLK", "Input clock"}, {19, 7, "DEV_DCC3_DCC_CLKSRC7_CLK", "Input clock"}, {19, 8, "DEV_DCC3_DCC_INPUT00_CLK", "Input clock"}, {19, 9, "DEV_DCC3_DCC_INPUT01_CLK", "Input clock"}, {19, 10, "DEV_DCC3_DCC_INPUT02_CLK", "Input clock"}, {19, 11, "DEV_DCC3_DCC_INPUT10_CLK", "Input clock"}, {19, 12, "DEV_DCC3_VBUS_CLK", "Input clock"}, {20, 0, "DEV_DCC4_DCC_CLKSRC0_CLK", "Input clock"}, {20, 1, "DEV_DCC4_DCC_CLKSRC1_CLK", "Input clock"}, {20, 2, "DEV_DCC4_DCC_CLKSRC2_CLK", "Input clock"}, {20, 3, "DEV_DCC4_DCC_CLKSRC3_CLK", "Input clock"}, {20, 4, "DEV_DCC4_DCC_CLKSRC4_CLK", "Input clock"}, {20, 5, "DEV_DCC4_DCC_CLKSRC5_CLK", "Input clock"}, {20, 6, "DEV_DCC4_DCC_CLKSRC6_CLK", "Input clock"}, {20, 7, "DEV_DCC4_DCC_CLKSRC7_CLK", "Input clock"}, {20, 8, "DEV_DCC4_DCC_INPUT00_CLK", "Input clock"}, {20, 9, "DEV_DCC4_DCC_INPUT01_CLK", "Input clock"}, {20, 10, "DEV_DCC4_DCC_INPUT02_CLK", "Input clock"}, {20, 11, "DEV_DCC4_DCC_INPUT10_CLK", "Input clock"}, {20, 12, "DEV_DCC4_VBUS_CLK", "Input clock"}, {21, 0, "DEV_DCC5_DCC_CLKSRC0_CLK", "Input clock"}, {21, 1, "DEV_DCC5_DCC_CLKSRC1_CLK", "Input clock"}, {21, 2, "DEV_DCC5_DCC_CLKSRC2_CLK", "Input clock"}, {21, 3, "DEV_DCC5_DCC_CLKSRC3_CLK", "Input clock"}, {21, 4, "DEV_DCC5_DCC_CLKSRC4_CLK", "Input clock"}, {21, 5, "DEV_DCC5_DCC_CLKSRC5_CLK", "Input clock"}, {21, 6, "DEV_DCC5_DCC_CLKSRC6_CLK", "Input clock"}, {21, 7, "DEV_DCC5_DCC_CLKSRC7_CLK", "Input clock"}, {21, 8, "DEV_DCC5_DCC_INPUT00_CLK", "Input clock"}, {21, 9, "DEV_DCC5_DCC_INPUT01_CLK", "Input clock"}, {21, 10, "DEV_DCC5_DCC_INPUT02_CLK", "Input clock"}, {21, 11, "DEV_DCC5_DCC_INPUT10_CLK", "Input clock"}, {21, 12, "DEV_DCC5_VBUS_CLK", "Input clock"}, {183, 0, "DEV_DCC6_DCC_CLKSRC0_CLK", "Input clock"}, {183, 1, "DEV_DCC6_DCC_CLKSRC1_CLK", "Input clock"}, {183, 2, "DEV_DCC6_DCC_CLKSRC2_CLK", "Input clock"}, {183, 3, "DEV_DCC6_DCC_CLKSRC3_CLK", "Input clock"}, {183, 4, "DEV_DCC6_DCC_CLKSRC4_CLK", "Input clock"}, {183, 5, "DEV_DCC6_DCC_CLKSRC5_CLK", "Input clock"}, {183, 6, "DEV_DCC6_DCC_CLKSRC6_CLK", "Input clock"}, {183, 7, "DEV_DCC6_DCC_CLKSRC7_CLK", "Input clock"}, {183, 8, "DEV_DCC6_DCC_INPUT00_CLK", "Input clock"}, {183, 9, "DEV_DCC6_DCC_INPUT01_CLK", "Input clock"}, {183, 10, "DEV_DCC6_DCC_INPUT02_CLK", "Input clock"}, {183, 11, "DEV_DCC6_DCC_INPUT10_CLK", "Input clock"}, {183, 12, "DEV_DCC6_VBUS_CLK", "Input clock"}, {85, 0, "DEV_DDPA0_DDPA_CLK", "Input clock"}, {170, 0, "DEV_DDR16SS0_DDRSS_DDR_PLL_CLK", "Input clock"}, {170, 1, "DEV_DDR16SS0_DDRSS_TCK", "Input clock"}, {170, 2, "DEV_DDR16SS0_PLL_CTRL_CLK", "Input clock"}, {171, 0, "DEV_DEBUGSS0_CFG_CLK", "Input clock"}, {171, 1, "DEV_DEBUGSS0_DBG_CLK", "Input clock"}, {171, 2, "DEV_DEBUGSS0_SYS_CLK", "Input clock"}, {24, 0, "DEV_DEBUGSS_WRAP0_ATB_CLK", "Input clock"}, {24, 1, "DEV_DEBUGSS_WRAP0_CORE_CLK", "Input clock"}, {24, 2, "DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK", "Output clock"}, {24, 20, "DEV_DEBUGSS_WRAP0_JTAG_TCK", "Input clock"}, {24, 22, "DEV_DEBUGSS_WRAP0_TREXPT_CLK", "Input clock"}, {26, 0, "DEV_DMASS0_BCDMA_0_CLK", "Input clock"}, {27, 0, "DEV_DMASS0_CBASS_0_CLK", "Input clock"}, {28, 0, "DEV_DMASS0_INTAGGR_0_CLK", "Input clock"}, {29, 0, "DEV_DMASS0_IPCSS_0_CLK", "Input clock"}, {30, 0, "DEV_DMASS0_PKTDMA_0_CLK", "Input clock"}, {33, 0, "DEV_DMASS0_RINGACC_0_CLK", "Input clock"}, {185, 2, "DEV_DPHY_RX0_IO_RX_CL_L_M", "Input clock"}, {185, 2, "DEV_DPHY_RX0_IO_RX_CL_L_M", "Output clock"}, {185, 3, "DEV_DPHY_RX0_IO_RX_CL_L_P", "Input clock"}, {185, 3, "DEV_DPHY_RX0_IO_RX_CL_L_P", "Output clock"}, {185, 4, "DEV_DPHY_RX0_JTAG_TCK", "Input clock"}, {185, 5, "DEV_DPHY_RX0_MAIN_CLK_CLK", "Input clock"}, {185, 7, "DEV_DPHY_RX0_PPI_RX_BYTE_CLK", "Output clock"}, {186, 0, "DEV_DSS0_DPI_0_IN_CLK", "Input clock"}, {186, 2, "DEV_DSS0_DPI_1_IN_CLK", "Input muxed clock"}, {186, 3, "DEV_DSS0_DPI_1_IN_CLK_PARENT_HSDIV0_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DPI_1_IN_CLK"}, {186, 4, "DEV_DSS0_DPI_1_IN_CLK_PARENT_BOARD_0_VOUT0_EXTPCLKIN_OUT", "Parent input clock option to DEV_DSS0_DPI_1_IN_CLK"}, {186, 5, "DEV_DSS0_DPI_1_OUT_CLK", "Output clock"}, {186, 6, "DEV_DSS0_DSS_FUNC_CLK", "Input clock"}, {51, 0, "DEV_ECAP0_VBUS_CLK", "Input clock"}, {52, 0, "DEV_ECAP1_VBUS_CLK", "Input clock"}, {53, 0, "DEV_ECAP2_VBUS_CLK", "Input clock"}, {54, 0, "DEV_ELM0_VBUSP_CLK", "Input clock"}, {86, 0, "DEV_EPWM0_VBUSP_CLK", "Input clock"}, {87, 0, "DEV_EPWM1_VBUSP_CLK", "Input clock"}, {88, 0, "DEV_EPWM2_VBUSP_CLK", "Input clock"}, {59, 0, "DEV_EQEP0_VBUS_CLK", "Input clock"}, {60, 0, "DEV_EQEP1_VBUS_CLK", "Input clock"}, {62, 0, "DEV_EQEP2_VBUS_CLK", "Input clock"}, {63, 0, "DEV_ESM0_CLK", "Input clock"}, {74, 0, "DEV_FSS0_FSAS_0_GCLK", "Input clock"}, {75, 0, "DEV_FSS0_OSPI_0_OSPI_DQS_CLK", "Input clock"}, {75, 1, "DEV_FSS0_OSPI_0_OSPI_HCLK_CLK", "Input clock"}, {75, 2, "DEV_FSS0_OSPI_0_OSPI_ICLK_CLK", "Input muxed clock"}, {75, 3, "DEV_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI0_DQS_OUT", "Parent input clock option to DEV_FSS0_OSPI_0_OSPI_ICLK_CLK"}, {75, 4, "DEV_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI0_LBCLKO_OUT", "Parent input clock option to DEV_FSS0_OSPI_0_OSPI_ICLK_CLK"}, {75, 5, "DEV_FSS0_OSPI_0_OSPI_OCLK_CLK", "Output clock"}, {75, 6, "DEV_FSS0_OSPI_0_OSPI_PCLK_CLK", "Input clock"}, {75, 7, "DEV_FSS0_OSPI_0_OSPI_RCLK_CLK", "Input muxed clock"}, {75, 8, "DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_FSS0_OSPI_0_OSPI_RCLK_CLK"}, {75, 9, "DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT5_CLK", "Parent input clock option to DEV_FSS0_OSPI_0_OSPI_RCLK_CLK"}, {76, 0, "DEV_GICSS0_VCLK_CLK", "Input clock"}, {77, 0, "DEV_GPIO0_MMR_CLK", "Input clock"}, {78, 0, "DEV_GPIO1_MMR_CLK", "Input clock"}, {80, 0, "DEV_GPMC0_FUNC_CLK", "Input muxed clock"}, {80, 1, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_GPMC0_FUNC_CLK"}, {80, 2, "DEV_GPMC0_FUNC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK", "Parent input clock option to DEV_GPMC0_FUNC_CLK"}, {80, 3, "DEV_GPMC0_PI_GPMC_RET_CLK", "Input clock"}, {80, 4, "DEV_GPMC0_PO_GPMC_DEV_CLK", "Output clock"}, {80, 5, "DEV_GPMC0_VBUSM_CLK", "Input clock"}, {187, 0, "DEV_GPU0_GPU_CLK", "Input clock"}, {174, 0, "DEV_GPU_RS_BW_LIMITER2_CLK_CLK", "Input clock"}, {175, 0, "DEV_GPU_WS_BW_LIMITER3_CLK_CLK", "Input clock"}, {102, 0, "DEV_I2C0_CLK", "Input clock"}, {102, 1, "DEV_I2C0_PISCL", "Input clock"}, {102, 2, "DEV_I2C0_PISYS_CLK", "Input clock"}, {102, 3, "DEV_I2C0_PORSCL", "Output clock"}, {103, 0, "DEV_I2C1_CLK", "Input clock"}, {103, 1, "DEV_I2C1_PISCL", "Input clock"}, {103, 2, "DEV_I2C1_PISYS_CLK", "Input clock"}, {103, 3, "DEV_I2C1_PORSCL", "Output clock"}, {104, 0, "DEV_I2C2_CLK", "Input clock"}, {104, 1, "DEV_I2C2_PISCL", "Input clock"}, {104, 2, "DEV_I2C2_PISYS_CLK", "Input clock"}, {104, 3, "DEV_I2C2_PORSCL", "Output clock"}, {105, 0, "DEV_I2C3_CLK", "Input clock"}, {105, 1, "DEV_I2C3_PISCL", "Input clock"}, {105, 2, "DEV_I2C3_PISYS_CLK", "Input clock"}, {105, 3, "DEV_I2C3_PORSCL", "Output clock"}, {81, 0, "DEV_ICSSM0_CORE_CLK", "Input muxed clock"}, {81, 1, "DEV_ICSSM0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_ICSSM0_CORE_CLK"}, {81, 2, "DEV_ICSSM0_CORE_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT9_CLK", "Parent input clock option to DEV_ICSSM0_CORE_CLK"}, {81, 3, "DEV_ICSSM0_IEP_CLK", "Input muxed clock"}, {81, 4, "DEV_ICSSM0_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK", "Parent input clock option to DEV_ICSSM0_IEP_CLK"}, {81, 5, "DEV_ICSSM0_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_ICSSM0_IEP_CLK"}, {81, 6, "DEV_ICSSM0_IEP_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_ICSSM0_IEP_CLK"}, {81, 8, "DEV_ICSSM0_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ICSSM0_IEP_CLK"}, {81, 9, "DEV_ICSSM0_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ICSSM0_IEP_CLK"}, {81, 10, "DEV_ICSSM0_IEP_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_ICSSM0_IEP_CLK"}, {81, 11, "DEV_ICSSM0_IEP_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_ICSSM0_IEP_CLK"}, {81, 13, "DEV_ICSSM0_UCLK_CLK", "Input clock"}, {81, 14, "DEV_ICSSM0_VCLK_CLK", "Input clock"}, {83, 1, "DEV_LED0_VBUS_CLK", "Input clock"}, {3, 0, "DEV_MAIN_GPIOMUX_INTROUTER0_INTR_CLK", "Input clock"}, {98, 1, "DEV_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"}, {98, 2, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, {98, 3, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, {98, 4, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, {98, 5, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, {98, 6, "DEV_MCAN0_MCANSS_HCLK_CLK", "Input clock"}, {190, 0, "DEV_MCASP0_AUX_CLK", "Input muxed clock"}, {190, 1, "DEV_MCASP0_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, {190, 2, "DEV_MCASP0_AUX_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, {190, 3, "DEV_MCASP0_MCASP_ACLKR_PIN", "Input clock"}, {190, 4, "DEV_MCASP0_MCASP_ACLKR_POUT", "Output clock"}, {190, 5, "DEV_MCASP0_MCASP_ACLKX_PIN", "Input clock"}, {190, 6, "DEV_MCASP0_MCASP_ACLKX_POUT", "Output clock"}, {190, 7, "DEV_MCASP0_MCASP_AFSR_POUT", "Output clock"}, {190, 8, "DEV_MCASP0_MCASP_AFSX_POUT", "Output clock"}, {190, 9, "DEV_MCASP0_MCASP_AHCLKR_PIN", "Input muxed clock"}, {190, 10, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {190, 11, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {190, 12, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {190, 13, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {190, 14, "DEV_MCASP0_MCASP_AHCLKR_POUT", "Output clock"}, {190, 15, "DEV_MCASP0_MCASP_AHCLKX_PIN", "Input muxed clock"}, {190, 16, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {190, 17, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {190, 18, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {190, 19, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {190, 20, "DEV_MCASP0_MCASP_AHCLKX_POUT", "Output clock"}, {190, 21, "DEV_MCASP0_VBUSP_CLK", "Input clock"}, {191, 0, "DEV_MCASP1_AUX_CLK", "Input muxed clock"}, {191, 1, "DEV_MCASP1_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, {191, 2, "DEV_MCASP1_AUX_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, {191, 3, "DEV_MCASP1_MCASP_ACLKR_PIN", "Input clock"}, {191, 4, "DEV_MCASP1_MCASP_ACLKR_POUT", "Output clock"}, {191, 5, "DEV_MCASP1_MCASP_ACLKX_PIN", "Input clock"}, {191, 6, "DEV_MCASP1_MCASP_ACLKX_POUT", "Output clock"}, {191, 7, "DEV_MCASP1_MCASP_AFSR_POUT", "Output clock"}, {191, 8, "DEV_MCASP1_MCASP_AFSX_POUT", "Output clock"}, {191, 9, "DEV_MCASP1_MCASP_AHCLKR_PIN", "Input muxed clock"}, {191, 10, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {191, 11, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {191, 12, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {191, 13, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {191, 14, "DEV_MCASP1_MCASP_AHCLKR_POUT", "Output clock"}, {191, 15, "DEV_MCASP1_MCASP_AHCLKX_PIN", "Input muxed clock"}, {191, 16, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {191, 17, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {191, 18, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {191, 19, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {191, 20, "DEV_MCASP1_MCASP_AHCLKX_POUT", "Output clock"}, {191, 21, "DEV_MCASP1_VBUSP_CLK", "Input clock"}, {192, 0, "DEV_MCASP2_AUX_CLK", "Input muxed clock"}, {192, 1, "DEV_MCASP2_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, {192, 2, "DEV_MCASP2_AUX_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, {192, 3, "DEV_MCASP2_MCASP_ACLKR_PIN", "Input clock"}, {192, 4, "DEV_MCASP2_MCASP_ACLKR_POUT", "Output clock"}, {192, 5, "DEV_MCASP2_MCASP_ACLKX_PIN", "Input clock"}, {192, 6, "DEV_MCASP2_MCASP_ACLKX_POUT", "Output clock"}, {192, 7, "DEV_MCASP2_MCASP_AFSR_POUT", "Output clock"}, {192, 8, "DEV_MCASP2_MCASP_AFSX_POUT", "Output clock"}, {192, 9, "DEV_MCASP2_MCASP_AHCLKR_PIN", "Input muxed clock"}, {192, 10, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {192, 11, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {192, 12, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {192, 13, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {192, 14, "DEV_MCASP2_MCASP_AHCLKR_POUT", "Output clock"}, {192, 15, "DEV_MCASP2_MCASP_AHCLKX_PIN", "Input muxed clock"}, {192, 16, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {192, 17, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {192, 18, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {192, 19, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {192, 20, "DEV_MCASP2_MCASP_AHCLKX_POUT", "Output clock"}, {192, 21, "DEV_MCASP2_VBUSP_CLK", "Input clock"}, {116, 0, "DEV_MCRC64_0_CLK", "Input clock"}, {141, 0, "DEV_MCSPI0_CLKSPIREF_CLK", "Input clock"}, {141, 1, "DEV_MCSPI0_IO_CLKSPIO_CLK", "Output clock"}, {141, 2, "DEV_MCSPI0_VBUSP_CLK", "Input clock"}, {142, 0, "DEV_MCSPI1_CLKSPIREF_CLK", "Input clock"}, {142, 1, "DEV_MCSPI1_IO_CLKSPIO_CLK", "Output clock"}, {142, 2, "DEV_MCSPI1_VBUSP_CLK", "Input clock"}, {143, 0, "DEV_MCSPI2_CLKSPIREF_CLK", "Input clock"}, {143, 1, "DEV_MCSPI2_IO_CLKSPIO_CLK", "Output clock"}, {143, 2, "DEV_MCSPI2_VBUSP_CLK", "Input clock"}, {23, 0, "DEV_MCU_DCC0_DCC_CLKSRC0_CLK", "Input clock"}, {23, 1, "DEV_MCU_DCC0_DCC_CLKSRC1_CLK", "Input clock"}, {23, 2, "DEV_MCU_DCC0_DCC_CLKSRC2_CLK", "Input clock"}, {23, 3, "DEV_MCU_DCC0_DCC_CLKSRC3_CLK", "Input clock"}, {23, 4, "DEV_MCU_DCC0_DCC_CLKSRC4_CLK", "Input clock"}, {23, 5, "DEV_MCU_DCC0_DCC_CLKSRC5_CLK", "Input clock"}, {23, 6, "DEV_MCU_DCC0_DCC_CLKSRC6_CLK", "Input clock"}, {23, 7, "DEV_MCU_DCC0_DCC_CLKSRC7_CLK", "Input clock"}, {23, 8, "DEV_MCU_DCC0_DCC_INPUT00_CLK", "Input clock"}, {23, 9, "DEV_MCU_DCC0_DCC_INPUT01_CLK", "Input clock"}, {23, 10, "DEV_MCU_DCC0_DCC_INPUT02_CLK", "Input clock"}, {23, 11, "DEV_MCU_DCC0_DCC_INPUT10_CLK", "Input clock"}, {23, 12, "DEV_MCU_DCC0_VBUS_CLK", "Input clock"}, {79, 0, "DEV_MCU_GPIO0_MMR_CLK", "Input muxed clock"}, {79, 1, "DEV_MCU_GPIO0_MMR_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_MCU_GPIO0_MMR_CLK"}, {79, 2, "DEV_MCU_GPIO0_MMR_CLK_PARENT_GLUELOGIC_LFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_GPIO0_MMR_CLK"}, {79, 3, "DEV_MCU_GPIO0_MMR_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_MCU_GPIO0_MMR_CLK"}, {79, 4, "DEV_MCU_GPIO0_MMR_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_GPIO0_MMR_CLK"}, {106, 0, "DEV_MCU_I2C0_CLK", "Input clock"}, {106, 1, "DEV_MCU_I2C0_PISCL", "Input clock"}, {106, 2, "DEV_MCU_I2C0_PISYS_CLK", "Input clock"}, {106, 3, "DEV_MCU_I2C0_PORSCL", "Output clock"}, {8, 0, "DEV_MCU_M4FSS0_CBASS_0_CLK", "Input clock"}, {9, 0, "DEV_MCU_M4FSS0_CORE0_DAP_CLK", "Input clock"}, {9, 1, "DEV_MCU_M4FSS0_CORE0_VBUS_CLK", "Input muxed clock"}, {9, 2, "DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_M4FSS0_CORE0_VBUS_CLK"}, {9, 3, "DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_M4FSS0_CORE0_VBUS_CLK"}, {188, 1, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"}, {188, 2, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, {188, 3, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, {188, 4, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, {188, 5, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT_DUP0", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, {188, 6, "DEV_MCU_MCAN0_MCANSS_HCLK_CLK", "Input clock"}, {189, 1, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"}, {189, 2, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, {189, 3, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, {189, 4, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, {189, 5, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT_DUP0", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, {189, 6, "DEV_MCU_MCAN1_MCANSS_HCLK_CLK", "Input clock"}, {100, 0, "DEV_MCU_MCRC64_0_CLK", "Input clock"}, {147, 0, "DEV_MCU_MCSPI0_CLKSPIREF_CLK", "Input clock"}, {147, 1, "DEV_MCU_MCSPI0_IO_CLKSPIO_CLK", "Output clock"}, {147, 2, "DEV_MCU_MCSPI0_VBUSP_CLK", "Input clock"}, {148, 0, "DEV_MCU_MCSPI1_CLKSPIREF_CLK", "Input clock"}, {148, 1, "DEV_MCU_MCSPI1_IO_CLKSPIO_CLK", "Output clock"}, {148, 2, "DEV_MCU_MCSPI1_VBUSP_CLK", "Input clock"}, {180, 3, "DEV_MCU_MCU_16FF0_PLL_CTRL_MCU_CLK24_CLK", "Input clock"}, {131, 0, "DEV_MCU_RTI0_RTI_CLK", "Input muxed clock"}, {131, 1, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, {131, 2, "DEV_MCU_RTI0_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, {131, 3, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, {131, 4, "DEV_MCU_RTI0_RTI_CLK_PARENT_MCU_WWDTCLK_SEL_DIV_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, {131, 5, "DEV_MCU_RTI0_VBUSP_CLK", "Input clock"}, {35, 0, "DEV_MCU_TIMER0_TIMER_HCLK_CLK", "Input clock"}, {35, 1, "DEV_MCU_TIMER0_TIMER_PWM", "Output clock"}, {35, 2, "DEV_MCU_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"}, {35, 3, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 4, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 5, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 6, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 7, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 8, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 9, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 10, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_MCU_TIMERCLKN_SEL_OUT0_DIV_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {48, 0, "DEV_MCU_TIMER1_TIMER_HCLK_CLK", "Input clock"}, {48, 1, "DEV_MCU_TIMER1_TIMER_PWM", "Output clock"}, {48, 2, "DEV_MCU_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"}, {48, 3, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, {48, 4, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, {48, 5, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, {48, 6, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, {48, 7, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, {48, 8, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, {48, 9, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, {48, 10, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMERCLKN_SEL_OUT1_DIV_CLKOUT", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, {49, 0, "DEV_MCU_TIMER2_TIMER_HCLK_CLK", "Input clock"}, {49, 1, "DEV_MCU_TIMER2_TIMER_PWM", "Output clock"}, {49, 2, "DEV_MCU_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"}, {49, 3, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {49, 4, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {49, 5, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {49, 6, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {49, 7, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {49, 8, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {49, 9, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {49, 10, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_MCU_TIMERCLKN_SEL_OUT2_DIV_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {50, 0, "DEV_MCU_TIMER3_TIMER_HCLK_CLK", "Input clock"}, {50, 1, "DEV_MCU_TIMER3_TIMER_PWM", "Output clock"}, {50, 2, "DEV_MCU_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"}, {50, 3, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, {50, 4, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, {50, 5, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, {50, 6, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, {50, 7, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, {50, 8, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, {50, 9, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, {50, 10, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMERCLKN_SEL_OUT3_DIV_CLKOUT", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, {149, 0, "DEV_MCU_UART0_FCLK_CLK", "Input clock"}, {149, 3, "DEV_MCU_UART0_VBUSP_CLK", "Input clock"}, {57, 0, "DEV_MMCSD0_EMMCSDSS_IO_CLK_I", "Input muxed clock"}, {57, 1, "DEV_MMCSD0_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC0_CLKLB_OUT", "Parent input clock option to DEV_MMCSD0_EMMCSDSS_IO_CLK_I"}, {57, 2, "DEV_MMCSD0_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC0_CLK_OUT", "Parent input clock option to DEV_MMCSD0_EMMCSDSS_IO_CLK_I"}, {57, 3, "DEV_MMCSD0_EMMCSDSS_IO_CLK_O", "Output clock"}, {57, 5, "DEV_MMCSD0_EMMCSDSS_VBUS_CLK", "Input clock"}, {57, 6, "DEV_MMCSD0_EMMCSDSS_XIN_CLK", "Input muxed clock"}, {57, 7, "DEV_MMCSD0_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSDSS_XIN_CLK"}, {57, 8, "DEV_MMCSD0_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSDSS_XIN_CLK"}, {58, 0, "DEV_MMCSD1_EMMCSDSS_IO_CLK_I", "Input muxed clock"}, {58, 1, "DEV_MMCSD1_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC1_CLKLB_OUT", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_IO_CLK_I"}, {58, 2, "DEV_MMCSD1_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC1_CLK_OUT", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_IO_CLK_I"}, {58, 3, "DEV_MMCSD1_EMMCSDSS_IO_CLK_O", "Output clock"}, {58, 5, "DEV_MMCSD1_EMMCSDSS_VBUS_CLK", "Input clock"}, {58, 6, "DEV_MMCSD1_EMMCSDSS_XIN_CLK", "Input muxed clock"}, {58, 7, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"}, {58, 8, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"}, {184, 0, "DEV_MMCSD2_EMMCSDSS_IO_CLK_I", "Input muxed clock"}, {184, 1, "DEV_MMCSD2_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC2_CLKLB_OUT", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_IO_CLK_I"}, {184, 2, "DEV_MMCSD2_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC2_CLK_OUT", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_IO_CLK_I"}, {184, 3, "DEV_MMCSD2_EMMCSDSS_IO_CLK_O", "Output clock"}, {184, 5, "DEV_MMCSD2_EMMCSDSS_VBUS_CLK", "Input clock"}, {184, 6, "DEV_MMCSD2_EMMCSDSS_XIN_CLK", "Input muxed clock"}, {184, 7, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"}, {184, 8, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"}, {163, 7, "DEV_PBIST0_CLK8_CLK", "Input clock"}, {163, 9, "DEV_PBIST0_TCLK_CLK", "Input clock"}, {164, 7, "DEV_PBIST1_CLK8_CLK", "Input clock"}, {164, 9, "DEV_PBIST1_TCLK_CLK", "Input clock"}, {168, 0, "DEV_PSC0_FW_0_CLK", "Input clock"}, {169, 0, "DEV_PSC0_PSC_0_CLK", "Input clock"}, {169, 1, "DEV_PSC0_PSC_0_SLOW_CLK", "Input clock"}, {121, 0, "DEV_R5FSS0_CORE0_CPU_CLK", "Input muxed clock"}, {121, 1, "DEV_R5FSS0_CORE0_CPU_CLK_PARENT_HSDIV1_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_R5FSS0_CORE0_CPU_CLK"}, {121, 2, "DEV_R5FSS0_CORE0_CPU_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_R5FSS0_CORE0_CPU_CLK"}, {121, 3, "DEV_R5FSS0_CORE0_INTERFACE_CLK", "Input clock"}, {125, 0, "DEV_RTI0_RTI_CLK", "Input muxed clock"}, {125, 1, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {125, 2, "DEV_RTI0_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {125, 3, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {125, 4, "DEV_RTI0_RTI_CLK_PARENT_MAIN_WWDTCLKN_SEL_OUT0_DIV_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {125, 5, "DEV_RTI0_VBUSP_CLK", "Input clock"}, {126, 0, "DEV_RTI1_RTI_CLK", "Input muxed clock"}, {126, 1, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {126, 2, "DEV_RTI1_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {126, 3, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {126, 4, "DEV_RTI1_RTI_CLK_PARENT_MAIN_WWDTCLKN_SEL_OUT1_DIV_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {126, 5, "DEV_RTI1_VBUSP_CLK", "Input clock"}, {130, 0, "DEV_RTI15_RTI_CLK", "Input muxed clock"}, {130, 1, "DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI15_RTI_CLK"}, {130, 2, "DEV_RTI15_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_RTI15_RTI_CLK"}, {130, 3, "DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI15_RTI_CLK"}, {130, 4, "DEV_RTI15_RTI_CLK_PARENT_MAIN_WWDTCLKN_SEL_OUT4_DIV_CLKOUT", "Parent input clock option to DEV_RTI15_RTI_CLK"}, {130, 5, "DEV_RTI15_VBUSP_CLK", "Input clock"}, {127, 0, "DEV_RTI2_RTI_CLK", "Input muxed clock"}, {127, 1, "DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI2_RTI_CLK"}, {127, 2, "DEV_RTI2_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_RTI2_RTI_CLK"}, {127, 3, "DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI2_RTI_CLK"}, {127, 4, "DEV_RTI2_RTI_CLK_PARENT_MAIN_WWDTCLKN_SEL_OUT2_DIV_CLKOUT", "Parent input clock option to DEV_RTI2_RTI_CLK"}, {127, 5, "DEV_RTI2_VBUSP_CLK", "Input clock"}, {128, 0, "DEV_RTI3_RTI_CLK", "Input muxed clock"}, {128, 1, "DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI3_RTI_CLK"}, {128, 2, "DEV_RTI3_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_RTI3_RTI_CLK"}, {128, 3, "DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI3_RTI_CLK"}, {128, 4, "DEV_RTI3_RTI_CLK_PARENT_MAIN_WWDTCLKN_SEL_OUT3_DIV_CLKOUT", "Parent input clock option to DEV_RTI3_RTI_CLK"}, {128, 5, "DEV_RTI3_VBUSP_CLK", "Input clock"}, {66, 0, "DEV_SA3_SS0_DMSS_ECCAGGR_0_X1_CLK", "Input clock"}, {67, 0, "DEV_SA3_SS0_INTAGGR_0_X1_CLK", "Input clock"}, {68, 0, "DEV_SA3_SS0_PKTDMA_0_X1_CLK", "Input clock"}, {69, 0, "DEV_SA3_SS0_RINGACC_0_X1_CLK", "Input clock"}, {70, 0, "DEV_SA3_SS0_SA_UL_0_PKA_IN_CLK", "Input clock"}, {70, 1, "DEV_SA3_SS0_SA_UL_0_X1_CLK", "Input clock"}, {70, 2, "DEV_SA3_SS0_SA_UL_0_X2_CLK", "Input clock"}, {150, 0, "DEV_SPINLOCK0_VCLK_CLK", "Input clock"}, {15, 0, "DEV_STM0_ATB_CLK", "Input clock"}, {15, 1, "DEV_STM0_CORE_CLK", "Input clock"}, {15, 2, "DEV_STM0_VBUSP_CLK", "Input clock"}, {36, 0, "DEV_TIMER0_TIMER_HCLK_CLK", "Input clock"}, {36, 1, "DEV_TIMER0_TIMER_PWM", "Output clock"}, {36, 2, "DEV_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"}, {36, 3, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 4, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 5, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 6, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 7, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 8, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 10, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 11, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 12, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 13, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 14, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {37, 0, "DEV_TIMER1_TIMER_HCLK_CLK", "Input clock"}, {37, 1, "DEV_TIMER1_TIMER_PWM", "Output clock"}, {37, 2, "DEV_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"}, {37, 3, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {37, 4, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {37, 5, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {37, 6, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {37, 7, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {37, 8, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {37, 10, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {37, 11, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {37, 12, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {37, 13, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {37, 14, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {38, 0, "DEV_TIMER2_TIMER_HCLK_CLK", "Input clock"}, {38, 1, "DEV_TIMER2_TIMER_PWM", "Output clock"}, {38, 2, "DEV_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"}, {38, 3, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 4, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 5, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 6, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 7, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 8, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 10, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 11, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 12, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 13, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 14, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {39, 0, "DEV_TIMER3_TIMER_HCLK_CLK", "Input clock"}, {39, 1, "DEV_TIMER3_TIMER_PWM", "Output clock"}, {39, 2, "DEV_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"}, {39, 3, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {39, 4, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {39, 5, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {39, 6, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {39, 7, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {39, 8, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {39, 10, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {39, 11, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {39, 12, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {39, 13, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {39, 14, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {40, 0, "DEV_TIMER4_TIMER_HCLK_CLK", "Input clock"}, {40, 1, "DEV_TIMER4_TIMER_PWM", "Output clock"}, {40, 2, "DEV_TIMER4_TIMER_TCLK_CLK", "Input muxed clock"}, {40, 3, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 4, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 5, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 6, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 7, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 8, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 10, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 11, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 12, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 13, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 14, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {41, 0, "DEV_TIMER5_TIMER_HCLK_CLK", "Input clock"}, {41, 1, "DEV_TIMER5_TIMER_PWM", "Output clock"}, {41, 2, "DEV_TIMER5_TIMER_TCLK_CLK", "Input muxed clock"}, {41, 3, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {41, 4, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {41, 5, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {41, 6, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {41, 7, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {41, 8, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {41, 10, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {41, 11, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {41, 12, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {41, 13, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {41, 14, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {42, 0, "DEV_TIMER6_TIMER_HCLK_CLK", "Input clock"}, {42, 1, "DEV_TIMER6_TIMER_PWM", "Output clock"}, {42, 2, "DEV_TIMER6_TIMER_TCLK_CLK", "Input muxed clock"}, {42, 3, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 4, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 5, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 6, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 7, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 8, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 10, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 11, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 12, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 13, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 14, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {43, 0, "DEV_TIMER7_TIMER_HCLK_CLK", "Input clock"}, {43, 1, "DEV_TIMER7_TIMER_PWM", "Output clock"}, {43, 2, "DEV_TIMER7_TIMER_TCLK_CLK", "Input muxed clock"}, {43, 3, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {43, 4, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {43, 5, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {43, 6, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {43, 7, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {43, 8, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {43, 10, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {43, 11, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {43, 12, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {43, 13, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {43, 14, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {6, 0, "DEV_TIMESYNC_EVENT_ROUTER0_INTR_CLK", "Input clock"}, {146, 0, "DEV_UART0_FCLK_CLK", "Input muxed clock"}, {146, 1, "DEV_UART0_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT0", "Parent input clock option to DEV_UART0_FCLK_CLK"}, {146, 2, "DEV_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART0_FCLK_CLK"}, {146, 5, "DEV_UART0_VBUSP_CLK", "Input clock"}, {152, 0, "DEV_UART1_FCLK_CLK", "Input muxed clock"}, {152, 1, "DEV_UART1_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT1", "Parent input clock option to DEV_UART1_FCLK_CLK"}, {152, 2, "DEV_UART1_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART1_FCLK_CLK"}, {152, 5, "DEV_UART1_VBUSP_CLK", "Input clock"}, {153, 0, "DEV_UART2_FCLK_CLK", "Input muxed clock"}, {153, 1, "DEV_UART2_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT2", "Parent input clock option to DEV_UART2_FCLK_CLK"}, {153, 2, "DEV_UART2_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART2_FCLK_CLK"}, {153, 5, "DEV_UART2_VBUSP_CLK", "Input clock"}, {154, 0, "DEV_UART3_FCLK_CLK", "Input muxed clock"}, {154, 1, "DEV_UART3_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT3", "Parent input clock option to DEV_UART3_FCLK_CLK"}, {154, 2, "DEV_UART3_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART3_FCLK_CLK"}, {154, 5, "DEV_UART3_VBUSP_CLK", "Input clock"}, {155, 0, "DEV_UART4_FCLK_CLK", "Input muxed clock"}, {155, 1, "DEV_UART4_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT4", "Parent input clock option to DEV_UART4_FCLK_CLK"}, {155, 2, "DEV_UART4_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART4_FCLK_CLK"}, {155, 5, "DEV_UART4_VBUSP_CLK", "Input clock"}, {156, 0, "DEV_UART5_FCLK_CLK", "Input muxed clock"}, {156, 1, "DEV_UART5_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT5", "Parent input clock option to DEV_UART5_FCLK_CLK"}, {156, 2, "DEV_UART5_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART5_FCLK_CLK"}, {156, 5, "DEV_UART5_VBUSP_CLK", "Input clock"}, {158, 0, "DEV_UART6_FCLK_CLK", "Input muxed clock"}, {158, 1, "DEV_UART6_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT6", "Parent input clock option to DEV_UART6_FCLK_CLK"}, {158, 2, "DEV_UART6_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART6_FCLK_CLK"}, {158, 5, "DEV_UART6_VBUSP_CLK", "Input clock"}, {161, 0, "DEV_USB0_BUS_CLK", "Input clock"}, {161, 1, "DEV_USB0_CFG_CLK", "Input clock"}, {161, 2, "DEV_USB0_USB2_APB_PCLK_CLK", "Input clock"}, {161, 3, "DEV_USB0_USB2_REFCLOCK_CLK", "Input muxed clock"}, {161, 4, "DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK"}, {161, 5, "DEV_USB0_USB2_REFCLOCK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK"}, {161, 10, "DEV_USB0_USB2_TAP_TCK", "Input clock"}, {162, 0, "DEV_USB1_BUS_CLK", "Input clock"}, {162, 1, "DEV_USB1_CFG_CLK", "Input clock"}, {162, 2, "DEV_USB1_USB2_APB_PCLK_CLK", "Input clock"}, {162, 3, "DEV_USB1_USB2_REFCLOCK_CLK", "Input muxed clock"}, {162, 4, "DEV_USB1_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_USB1_USB2_REFCLOCK_CLK"}, {162, 5, "DEV_USB1_USB2_REFCLOCK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_USB1_USB2_REFCLOCK_CLK"}, {162, 10, "DEV_USB1_USB2_TAP_TCK", "Input clock"}, {176, 0, "DEV_WKUP_DEEPSLEEP_SOURCES0_CLK_12M_RC_CLK", "Input clock"}, {64, 0, "DEV_WKUP_ESM0_CLK", "Input clock"}, {61, 0, "DEV_WKUP_GTC0_GTC_CLK", "Input muxed clock"}, {61, 1, "DEV_WKUP_GTC0_GTC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK", "Parent input clock option to DEV_WKUP_GTC0_GTC_CLK"}, {61, 2, "DEV_WKUP_GTC0_GTC_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_WKUP_GTC0_GTC_CLK"}, {61, 3, "DEV_WKUP_GTC0_GTC_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_WKUP_GTC0_GTC_CLK"}, {61, 5, "DEV_WKUP_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_WKUP_GTC0_GTC_CLK"}, {61, 6, "DEV_WKUP_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_WKUP_GTC0_GTC_CLK"}, {61, 7, "DEV_WKUP_GTC0_GTC_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_WKUP_GTC0_GTC_CLK"}, {61, 8, "DEV_WKUP_GTC0_GTC_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_WKUP_GTC0_GTC_CLK"}, {61, 9, "DEV_WKUP_GTC0_VBUSP_CLK", "Input muxed clock"}, {61, 10, "DEV_WKUP_GTC0_VBUSP_CLK_PARENT_HSDIV1_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_GTC0_VBUSP_CLK"}, {61, 11, "DEV_WKUP_GTC0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_GTC0_VBUSP_CLK"}, {107, 0, "DEV_WKUP_I2C0_CLK", "Input muxed clock"}, {107, 1, "DEV_WKUP_I2C0_CLK_PARENT_HSDIV1_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_I2C0_CLK"}, {107, 2, "DEV_WKUP_I2C0_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_I2C0_CLK"}, {107, 3, "DEV_WKUP_I2C0_PISCL", "Input clock"}, {107, 4, "DEV_WKUP_I2C0_PISYS_CLK", "Input clock"}, {107, 5, "DEV_WKUP_I2C0_PORSCL", "Output clock"}, {5, 0, "DEV_WKUP_MCU_GPIOMUX_INTROUTER0_INTR_CLK", "Input clock"}, {165, 7, "DEV_WKUP_PBIST0_CLK8_CLK", "Input clock"}, {140, 0, "DEV_WKUP_PSC0_CLK", "Input clock"}, {140, 1, "DEV_WKUP_PSC0_SLOW_CLK", "Input clock"}, {117, 0, "DEV_WKUP_RTCSS0_ANA_OSC32K_CLK", "Input muxed clock"}, {117, 1, "DEV_WKUP_RTCSS0_ANA_OSC32K_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_WKUP_RTCSS0_ANA_OSC32K_CLK"}, {117, 2, "DEV_WKUP_RTCSS0_ANA_OSC32K_CLK_PARENT_RTC_CLK_SEL_DIV_CLKOUT", "Parent input clock option to DEV_WKUP_RTCSS0_ANA_OSC32K_CLK"}, {117, 6, "DEV_WKUP_RTCSS0_VCLK_CLK", "Input muxed clock"}, {117, 7, "DEV_WKUP_RTCSS0_VCLK_CLK_PARENT_HSDIV1_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_RTCSS0_VCLK_CLK"}, {117, 8, "DEV_WKUP_RTCSS0_VCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_RTCSS0_VCLK_CLK"}, {132, 0, "DEV_WKUP_RTI0_RTI_CLK", "Input muxed clock"}, {132, 1, "DEV_WKUP_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_WKUP_RTI0_RTI_CLK"}, {132, 2, "DEV_WKUP_RTI0_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_WKUP_RTI0_RTI_CLK"}, {132, 3, "DEV_WKUP_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_WKUP_RTI0_RTI_CLK"}, {132, 4, "DEV_WKUP_RTI0_RTI_CLK_PARENT_WKUP_WWDTCLK_SEL_DIV_CLKOUT", "Parent input clock option to DEV_WKUP_RTI0_RTI_CLK"}, {132, 5, "DEV_WKUP_RTI0_VBUSP_CLK", "Input muxed clock"}, {132, 6, "DEV_WKUP_RTI0_VBUSP_CLK_PARENT_HSDIV1_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_RTI0_VBUSP_CLK"}, {132, 7, "DEV_WKUP_RTI0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_RTI0_VBUSP_CLK"}, {110, 0, "DEV_WKUP_TIMER0_TIMER_HCLK_CLK", "Input muxed clock"}, {110, 1, "DEV_WKUP_TIMER0_TIMER_HCLK_CLK_PARENT_HSDIV1_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_HCLK_CLK"}, {110, 2, "DEV_WKUP_TIMER0_TIMER_HCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_HCLK_CLK"}, {110, 4, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"}, {110, 5, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK"}, {110, 6, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_WKUP_CLKSEL_OUT04", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK"}, {110, 7, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK"}, {110, 8, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK"}, {110, 9, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK"}, {110, 10, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK"}, {110, 11, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK"}, {110, 12, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_WKUP_TIMERCLKN_SEL_OUT0_DIV_CLKOUT", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK"}, {111, 0, "DEV_WKUP_TIMER1_TIMER_HCLK_CLK", "Input muxed clock"}, {111, 1, "DEV_WKUP_TIMER1_TIMER_HCLK_CLK_PARENT_HSDIV1_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_TIMER1_TIMER_HCLK_CLK"}, {111, 2, "DEV_WKUP_TIMER1_TIMER_HCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_TIMER1_TIMER_HCLK_CLK"}, {111, 4, "DEV_WKUP_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"}, {111, 5, "DEV_WKUP_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_WKUP_TIMER1_TIMER_TCLK_CLK"}, {111, 6, "DEV_WKUP_TIMER1_TIMER_TCLK_CLK_PARENT_WKUP_CLKSEL_OUT04", "Parent input clock option to DEV_WKUP_TIMER1_TIMER_TCLK_CLK"}, {111, 7, "DEV_WKUP_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_WKUP_TIMER1_TIMER_TCLK_CLK"}, {111, 8, "DEV_WKUP_TIMER1_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_WKUP_TIMER1_TIMER_TCLK_CLK"}, {111, 9, "DEV_WKUP_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_WKUP_TIMER1_TIMER_TCLK_CLK"}, {111, 10, "DEV_WKUP_TIMER1_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_WKUP_TIMER1_TIMER_TCLK_CLK"}, {111, 11, "DEV_WKUP_TIMER1_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_WKUP_TIMER1_TIMER_TCLK_CLK"}, {111, 12, "DEV_WKUP_TIMER1_TIMER_TCLK_CLK_PARENT_WKUP_TIMERCLKN_SEL_OUT1_DIV_CLKOUT", "Parent input clock option to DEV_WKUP_TIMER1_TIMER_TCLK_CLK"}, {114, 0, "DEV_WKUP_UART0_FCLK_CLK", "Input clock"}, {114, 3, "DEV_WKUP_UART0_VBUSP_CLK", "Input muxed clock"}, {114, 4, "DEV_WKUP_UART0_VBUSP_CLK_PARENT_HSDIV1_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_UART0_VBUSP_CLK"}, {114, 5, "DEV_WKUP_UART0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_UART0_VBUSP_CLK"}, {95, 0, "DEV_WKUP_VTM0_FIX_REF2_CLK", "Input clock"}, {95, 1, "DEV_WKUP_VTM0_FIX_REF_CLK", "Input clock"}, {95, 2, "DEV_WKUP_VTM0_VBUSP_CLK", "Input muxed clock"}, {95, 3, "DEV_WKUP_VTM0_VBUSP_CLK_PARENT_HSDIV1_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_VTM0_VBUSP_CLK"}, {95, 4, "DEV_WKUP_VTM0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_VTM0_VBUSP_CLK"}, }; k3conf_0.3/soc/am62x/am62x_devices_info.h0000664000175000017500000000346414504336513015122 0ustar /* * AM62X Devices Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM62X_DEVICES_INFO_H #define __AM62X_DEVICES_INFO_H #define AM62X_MAX_DEVICES 154 extern struct ti_sci_devices_info am62x_devices_info[]; #endif /* __AM62X_DEVICES_INFO_H */ k3conf_0.3/soc/am62x/am62x_devices_info.c0000664000175000017500000001447714375734376015142 0ustar /* * AM62X Devices Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_devices_info am62x_devices_info[] = { {1, "AM62X_DEV_CMP_EVENT_INTROUTER0"}, {2, "AM62X_DEV_DBGSUSPENDROUTER0"}, {3, "AM62X_DEV_MAIN_GPIOMUX_INTROUTER0"}, {5, "AM62X_DEV_WKUP_MCU_GPIOMUX_INTROUTER0"}, {6, "AM62X_DEV_TIMESYNC_EVENT_ROUTER0"}, {7, "AM62X_DEV_MCU_M4FSS0"}, {8, "AM62X_DEV_MCU_M4FSS0_CBASS_0"}, {9, "AM62X_DEV_MCU_M4FSS0_CORE0"}, {13, "AM62X_DEV_CPSW0"}, {14, "AM62X_DEV_CPT2_AGGR0"}, {15, "AM62X_DEV_STM0"}, {16, "AM62X_DEV_DCC0"}, {17, "AM62X_DEV_DCC1"}, {18, "AM62X_DEV_DCC2"}, {19, "AM62X_DEV_DCC3"}, {20, "AM62X_DEV_DCC4"}, {21, "AM62X_DEV_DCC5"}, {22, "AM62X_DEV_SMS0"}, {23, "AM62X_DEV_MCU_DCC0"}, {24, "AM62X_DEV_DEBUGSS_WRAP0"}, {25, "AM62X_DEV_DMASS0"}, {26, "AM62X_DEV_DMASS0_BCDMA_0"}, {27, "AM62X_DEV_DMASS0_CBASS_0"}, {28, "AM62X_DEV_DMASS0_INTAGGR_0"}, {29, "AM62X_DEV_DMASS0_IPCSS_0"}, {30, "AM62X_DEV_DMASS0_PKTDMA_0"}, {33, "AM62X_DEV_DMASS0_RINGACC_0"}, {35, "AM62X_DEV_MCU_TIMER0"}, {36, "AM62X_DEV_TIMER0"}, {37, "AM62X_DEV_TIMER1"}, {38, "AM62X_DEV_TIMER2"}, {39, "AM62X_DEV_TIMER3"}, {40, "AM62X_DEV_TIMER4"}, {41, "AM62X_DEV_TIMER5"}, {42, "AM62X_DEV_TIMER6"}, {43, "AM62X_DEV_TIMER7"}, {48, "AM62X_DEV_MCU_TIMER1"}, {49, "AM62X_DEV_MCU_TIMER2"}, {50, "AM62X_DEV_MCU_TIMER3"}, {51, "AM62X_DEV_ECAP0"}, {52, "AM62X_DEV_ECAP1"}, {53, "AM62X_DEV_ECAP2"}, {54, "AM62X_DEV_ELM0"}, {55, "AM62X_DEV_EMIF_DATA_ISO_VD"}, {57, "AM62X_DEV_MMCSD0"}, {58, "AM62X_DEV_MMCSD1"}, {59, "AM62X_DEV_EQEP0"}, {60, "AM62X_DEV_EQEP1"}, {61, "AM62X_DEV_WKUP_GTC0"}, {62, "AM62X_DEV_EQEP2"}, {63, "AM62X_DEV_ESM0"}, {64, "AM62X_DEV_WKUP_ESM0"}, {65, "AM62X_DEV_SA3_SS0"}, {66, "AM62X_DEV_SA3_SS0_DMSS_ECCAGGR_0"}, {67, "AM62X_DEV_SA3_SS0_INTAGGR_0"}, {68, "AM62X_DEV_SA3_SS0_PKTDMA_0"}, {69, "AM62X_DEV_SA3_SS0_RINGACC_0"}, {70, "AM62X_DEV_SA3_SS0_SA_UL_0"}, {73, "AM62X_DEV_FSS0"}, {74, "AM62X_DEV_FSS0_FSAS_0"}, {75, "AM62X_DEV_FSS0_OSPI_0"}, {76, "AM62X_DEV_GICSS0"}, {77, "AM62X_DEV_GPIO0"}, {78, "AM62X_DEV_GPIO1"}, {79, "AM62X_DEV_MCU_GPIO0"}, {80, "AM62X_DEV_GPMC0"}, {81, "AM62X_DEV_ICSSM0"}, {83, "AM62X_DEV_LED0"}, {85, "AM62X_DEV_DDPA0"}, {86, "AM62X_DEV_EPWM0"}, {87, "AM62X_DEV_EPWM1"}, {88, "AM62X_DEV_EPWM2"}, {95, "AM62X_DEV_WKUP_VTM0"}, {96, "AM62X_DEV_MAILBOX0"}, {97, "AM62X_DEV_MAIN2MCU_VD"}, {98, "AM62X_DEV_MCAN0"}, {100, "AM62X_DEV_MCU_MCRC64_0"}, {101, "AM62X_DEV_MCU2MAIN_VD"}, {102, "AM62X_DEV_I2C0"}, {103, "AM62X_DEV_I2C1"}, {104, "AM62X_DEV_I2C2"}, {105, "AM62X_DEV_I2C3"}, {106, "AM62X_DEV_MCU_I2C0"}, {107, "AM62X_DEV_WKUP_I2C0"}, {110, "AM62X_DEV_WKUP_TIMER0"}, {111, "AM62X_DEV_WKUP_TIMER1"}, {114, "AM62X_DEV_WKUP_UART0"}, {116, "AM62X_DEV_MCRC64_0"}, {117, "AM62X_DEV_WKUP_RTCSS0"}, {118, "AM62X_DEV_R5FSS0_SS0"}, {119, "AM62X_DEV_R5FSS0"}, {121, "AM62X_DEV_R5FSS0_CORE0"}, {125, "AM62X_DEV_RTI0"}, {126, "AM62X_DEV_RTI1"}, {127, "AM62X_DEV_RTI2"}, {128, "AM62X_DEV_RTI3"}, {130, "AM62X_DEV_RTI15"}, {131, "AM62X_DEV_MCU_RTI0"}, {132, "AM62X_DEV_WKUP_RTI0"}, {134, "AM62X_DEV_COMPUTE_CLUSTER0"}, {135, "AM62X_DEV_A53SS0_CORE_0"}, {136, "AM62X_DEV_A53SS0_CORE_1"}, {137, "AM62X_DEV_A53SS0_CORE_2"}, {138, "AM62X_DEV_A53SS0_CORE_3"}, {139, "AM62X_DEV_PSC0"}, {140, "AM62X_DEV_WKUP_PSC0"}, {141, "AM62X_DEV_MCSPI0"}, {142, "AM62X_DEV_MCSPI1"}, {143, "AM62X_DEV_MCSPI2"}, {146, "AM62X_DEV_UART0"}, {147, "AM62X_DEV_MCU_MCSPI0"}, {148, "AM62X_DEV_MCU_MCSPI1"}, {149, "AM62X_DEV_MCU_UART0"}, {150, "AM62X_DEV_SPINLOCK0"}, {152, "AM62X_DEV_UART1"}, {153, "AM62X_DEV_UART2"}, {154, "AM62X_DEV_UART3"}, {155, "AM62X_DEV_UART4"}, {156, "AM62X_DEV_UART5"}, {157, "AM62X_DEV_BOARD0"}, {158, "AM62X_DEV_UART6"}, {161, "AM62X_DEV_USB0"}, {162, "AM62X_DEV_USB1"}, {163, "AM62X_DEV_PBIST0"}, {164, "AM62X_DEV_PBIST1"}, {165, "AM62X_DEV_WKUP_PBIST0"}, {166, "AM62X_DEV_A53SS0"}, {167, "AM62X_DEV_COMPUTE_CLUSTER0_PBIST_0"}, {168, "AM62X_DEV_PSC0_FW_0"}, {169, "AM62X_DEV_PSC0_PSC_0"}, {170, "AM62X_DEV_DDR16SS0"}, {171, "AM62X_DEV_DEBUGSS0"}, {172, "AM62X_DEV_A53_RS_BW_LIMITER0"}, {173, "AM62X_DEV_A53_WS_BW_LIMITER1"}, {174, "AM62X_DEV_GPU_RS_BW_LIMITER2"}, {175, "AM62X_DEV_GPU_WS_BW_LIMITER3"}, {176, "AM62X_DEV_WKUP_DEEPSLEEP_SOURCES0"}, {177, "AM62X_DEV_EMIF_CFG_ISO_VD"}, {178, "AM62X_DEV_MAIN_USB0_ISO_VD"}, {179, "AM62X_DEV_MAIN_USB1_ISO_VD"}, {180, "AM62X_DEV_MCU_MCU_16FF0"}, {181, "AM62X_DEV_CPT2_AGGR1"}, {182, "AM62X_DEV_CSI_RX_IF0"}, {183, "AM62X_DEV_DCC6"}, {184, "AM62X_DEV_MMCSD2"}, {185, "AM62X_DEV_DPHY_RX0"}, {186, "AM62X_DEV_DSS0"}, {187, "AM62X_DEV_GPU0"}, {188, "AM62X_DEV_MCU_MCAN0"}, {189, "AM62X_DEV_MCU_MCAN1"}, {190, "AM62X_DEV_MCASP0"}, {191, "AM62X_DEV_MCASP1"}, {192, "AM62X_DEV_MCASP2"}, {193, "AM62X_DEV_CLK_32K_RC_SEL_DEV_VD"}, }; k3conf_0.3/soc/am62x/am62x_ddr_info.c0000664000175000017500000000367514504336530014247 0ustar /* * AM62X DDR performance information * * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #define MAX_PERF_NUM_DDR_INSTANCES 1 static uintptr_t am62_ddr_base_address[MAX_PERF_NUM_DDR_INSTANCES] = { 0x0F300100, }; struct ddr_perf_soc_info am62x_ddr_perf_info = { .num_perf_insts = MAX_PERF_NUM_DDR_INSTANCES, .burst_size = 32, .perf_inst_base = am62_ddr_base_address, }; k3conf_0.3/soc/am62x/am62x_processors_info.h0000664000175000017500000000350614504336513015677 0ustar /* * AM62X Processor Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM62X_PROCESSOR_INFO_H #define __AM62X_PROCESSOR_INFO_H #define AM62X_MAX_PROCESSORS_IDS 6 extern struct ti_sci_processors_info am62x_processors_info[]; #endif /* __AM62X_PROCESSOR_INFO_H */ k3conf_0.3/soc/am62x/am62x_clocks_info.h0000664000175000017500000000345514504336513014756 0ustar /* * AM62X Clocks Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM62X_CLOCKS_INFO_H #define __AM62X_CLOCKS_INFO_H #define AM62X_MAX_CLOCKS 858 extern struct ti_sci_clocks_info am62x_clocks_info[]; #endif /* __AM62X_CLOCKS_INFO_H */ k3conf_0.3/soc/am62x/am62x_rm_info.h0000664000175000017500000000342114504336513014107 0ustar /* * AM62X RM Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM62X_RM_INFO_H #define __AM62X_RM_INFO_H #define AM62X_MAX_RES 87 extern struct ti_sci_rm_info am62x_rm_info[]; #endif /* __AM62X_RM_INFO_H */ k3conf_0.3/soc/am62x/am62x_processors_info.c0000664000175000017500000000365714375734376015720 0ustar /* * AM62X Processor Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_processors_info am62x_processors_info[] = { {135, 0, 0x20, "A53SS0_CORE_0"}, {136, 0, 0x21, "A53SS0_CORE_1"}, {137, 0, 0x22, "A53SS0_CORE_2"}, {138, 0, 0x23, "A53SS0_CORE_3"}, {9 , 1, 0x18, "MCU_M4FSS0_CORE0"}, {121, 1, 0x01, "R5FSS0_CORE0"}, }; k3conf_0.3/soc/am62x/am62x_host_info.h0000664000175000017500000000441514504336513014452 0ustar /* * AM62X Host Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM62X_HOST_INFO_H #define __AM62X_HOST_INFO_H #define AM62X_HOST_ID_TIFS 0 #define AM62X_HOST_ID_DM 254 #define AM62X_HOST_ID_MAIN_0_R5_0 35 #define AM62X_HOST_ID_MAIN_0_R5_1 36 #define AM62X_HOST_ID_MAIN_0_R5_2 37 #define AM62X_HOST_ID_MAIN_0_R5_3 38 #define AM62X_HOST_ID_A53_0 10 #define AM62X_HOST_ID_A53_1 11 #define AM62X_HOST_ID_A53_2 12 #define AM62X_HOST_ID_A53_3 13 #define AM62X_HOST_ID_M4_0 30 #define AM62X_HOST_ID_GPU 31 #define AM62X_HOST_ID_ICSSG_0 50 #define AM62X_HOST_ID_DM2TIFS 250 #define AM62X_HOST_ID_TIFS2DM 251 #define AM62X_MAX_HOST_IDS 15 extern struct ti_sci_host_info am62x_host_info[]; #endif /* __AM62X_HOST_INFO_H */ k3conf_0.3/soc/am62x/am62x_ddr_info.h0000664000175000017500000000343314504336530014244 0ustar /* * AM62X DDR performance information * * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM62X_DDRBW_INFO_H #define __AM62X_DDRBW_INFO_H extern struct ddr_perf_soc_info am62x_ddr_perf_info; #endif /* __AM62X_DDRBW_INFO_H */ k3conf_0.3/soc/am62x/am62x_host_info.c0000664000175000017500000000527414375734376014470 0ustar /* * AM62X Hosts Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_host_info am62x_host_info[] = { {0, "TIFS", "Secure", "Device Management and Security Control"}, {254, "DM", "Non Secure", "Device Management"}, {35, "MAIN_0_R5_0", "Secure", "Cortex R5_0 context 0 on Main island(BOOT)"}, {36, "MAIN_0_R5_1", "Non Secure", "Cortex R5_0 context 1 on Main island"}, {37, "MAIN_0_R5_2", "Secure", "Cortex R5_0 context 2 on Main island"}, {38, "MAIN_0_R5_3", "Non Secure", "Cortex R5_0 context 3 on Main island"}, {10, "A53_0", "Secure", "Cortex a53 context 0 on Main islana - ATF"}, {11, "A53_1", "Non Secure", "Cortex A53 context 1 on Main island - EL2/Hyp"}, {12, "A53_2", "Non Secure", "Cortex A53 context 2 on Main island - VM/OS1"}, {13, "A53_3", "Non Secure", "Cortex A53 context 3 on Main island - VM2/OS2"}, {30, "M4_0", "Non Secure", "M4"}, {31, "GPU", "Non Secure", "GPU context 0 on Main island"}, {50, "ICSSG_0", "Non Secure", "ICSSG context 0 on Main island"}, {250, "DM2TIFS", "Secure", "DM to TIFS communication"}, {251, "TIFS2DM", "Non Secure", "TIFS to DM communication"}, }; k3conf_0.3/soc/am62x/am62x_rm_info.c0000664000175000017500000001436714375734376014134 0ustar /* * AM62X RM Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_rm_info am62x_rm_info[] = { {0x0040, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x00C0, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x0140, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x0180, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x0682, "RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER"}, {0x0683, "RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG"}, {0x068D, "RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN"}, {0x068E, "RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN"}, {0x068F, "RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN"}, {0x06A0, "RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN"}, {0x06A1, "RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN"}, {0x06A2, "RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN"}, {0x070A, "RESASG_SUBTYPE_IA_VINT"}, {0x070D, "RESASG_SUBTYPE_GLOBAL_EVENT_SEVT"}, {0x070F, "RESASG_SUBTYPE_IA_TIMERMGR_EVT_OES"}, {0x0710, "RESASG_SUBTYPE_IA_PKTDMA_TX_CHAN_ERROR_OES"}, {0x0711, "RESASG_SUBTYPE_IA_PKTDMA_TX_FLOW_COMPLETION_OES"}, {0x0712, "RESASG_SUBTYPE_IA_PKTDMA_RX_CHAN_ERROR_OES"}, {0x0713, "RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_COMPLETION_OES"}, {0x0714, "RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_STARVATION_OES"}, {0x0715, "RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_FIREWALL_OES"}, {0x0716, "RESASG_SUBTYPE_IA_BCDMA_CHAN_ERROR_OES"}, {0x0717, "RESASG_SUBTYPE_IA_BCDMA_CHAN_DATA_COMPLETION_OES"}, {0x0718, "RESASG_SUBTYPE_IA_BCDMA_CHAN_RING_COMPLETION_OES"}, {0x0719, "RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_ERROR_OES"}, {0x071A, "RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_DATA_COMPLETION_OES"}, {0x071B, "RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_RING_COMPLETION_OES"}, {0x071C, "RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_ERROR_OES"}, {0x071D, "RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_DATA_COMPLETION_OES"}, {0x071E, "RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_RING_COMPLETION_OES"}, {0x0783, "RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG"}, {0x0790, "RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN"}, {0x0791, "RESASG_SUBTYPE_PKTDMA_RING_CPSW_TX_CHAN"}, {0x0792, "RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_0_CHAN"}, {0x0793, "RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_1_CHAN"}, {0x0796, "RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN"}, {0x0797, "RESASG_SUBTYPE_PKTDMA_RING_CPSW_RX_CHAN"}, {0x0798, "RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_0_CHAN"}, {0x0799, "RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_1_CHAN"}, {0x079A, "RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_2_CHAN"}, {0x079B, "RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_3_CHAN"}, {0x07A3, "RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN"}, {0x07A4, "RESASG_SUBTYPE_PKTDMA_CPSW_TX_CHAN"}, {0x07A5, "RESASG_SUBTYPE_PKTDMA_SAUL_TX_0_CHAN"}, {0x07A6, "RESASG_SUBTYPE_PKTDMA_SAUL_TX_1_CHAN"}, {0x07A9, "RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN"}, {0x07AA, "RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN"}, {0x07AB, "RESASG_SUBTYPE_PKTDMA_CPSW_RX_CHAN"}, {0x07AC, "RESASG_SUBTYPE_PKTDMA_FLOW_CPSW_RX_CHAN"}, {0x07AD, "RESASG_SUBTYPE_PKTDMA_SAUL_RX_0_CHAN"}, {0x07AE, "RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_0_CHAN"}, {0x07AF, "RESASG_SUBTYPE_PKTDMA_SAUL_RX_1_CHAN"}, {0x07B0, "RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_1_CHAN"}, {0x07B1, "RESASG_SUBTYPE_PKTDMA_SAUL_RX_2_CHAN"}, {0x07B2, "RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_2_CHAN"}, {0x07B3, "RESASG_SUBTYPE_PKTDMA_SAUL_RX_3_CHAN"}, {0x07B4, "RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_3_CHAN"}, {0x0840, "RESASG_SUBTYPE_RA_ERROR_OES"}, {0x084A, "RESASG_SUBTYPE_RA_VIRTID"}, {0x10CA, "RESASG_SUBTYPE_IA_VINT"}, {0x10CD, "RESASG_SUBTYPE_GLOBAL_EVENT_SEVT"}, {0x10CF, "RESASG_SUBTYPE_IA_TIMERMGR_EVT_OES"}, {0x10D0, "RESASG_SUBTYPE_IA_PKTDMA_TX_CHAN_ERROR_OES"}, {0x10D1, "RESASG_SUBTYPE_IA_PKTDMA_TX_FLOW_COMPLETION_OES"}, {0x10D2, "RESASG_SUBTYPE_IA_PKTDMA_RX_CHAN_ERROR_OES"}, {0x10D3, "RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_COMPLETION_OES"}, {0x10D4, "RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_STARVATION_OES"}, {0x10D5, "RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_FIREWALL_OES"}, {0x1103, "RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG"}, {0x1112, "RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_0_CHAN"}, {0x1113, "RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_1_CHAN"}, {0x1118, "RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_0_CHAN"}, {0x1119, "RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_1_CHAN"}, {0x111A, "RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_2_CHAN"}, {0x111B, "RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_3_CHAN"}, {0x1125, "RESASG_SUBTYPE_PKTDMA_SAUL_TX_0_CHAN"}, {0x1126, "RESASG_SUBTYPE_PKTDMA_SAUL_TX_1_CHAN"}, {0x112D, "RESASG_SUBTYPE_PKTDMA_SAUL_RX_0_CHAN"}, {0x112E, "RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_0_CHAN"}, {0x112F, "RESASG_SUBTYPE_PKTDMA_SAUL_RX_1_CHAN"}, {0x1130, "RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_1_CHAN"}, {0x1131, "RESASG_SUBTYPE_PKTDMA_SAUL_RX_2_CHAN"}, {0x1132, "RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_2_CHAN"}, {0x1133, "RESASG_SUBTYPE_PKTDMA_SAUL_RX_3_CHAN"}, {0x1134, "RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_3_CHAN"}, {0x1140, "RESASG_SUBTYPE_RA_ERROR_OES"}, {0x114A, "RESASG_SUBTYPE_RA_VIRTID"}, }; k3conf_0.3/soc/j721e/0000775000175000017500000000000014504336530011162 5ustar k3conf_0.3/soc/j721e/j721e_sec_proxy_info.h0000664000175000017500000000365114375734376015316 0ustar /* * J721E Sec Proxy Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __J721E_SEC_PROXY_INFO_H #define __J721E_SEC_PROXY_INFO_H #define J721E_MAIN_SEC_PROXY_THREADS 132 #define J721E_MCU_SEC_PROXY_THREADS 39 extern struct ti_sci_sec_proxy_info j721e_main_sp_info[]; extern struct ti_sci_sec_proxy_info j721e_mcu_sp_info[]; #endif /* __J721E_SEC_PROXY_INFO_H */ k3conf_0.3/soc/j721e/j721e_host_info.h0000664000175000017500000000536214375734376014261 0ustar /* * J721E Host Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __J721E_HOST_INFO_H #define __J721E_HOST_INFO_H #define J721E_HOST_ID_DMSC 0 #define J721E_HOST_ID_MCU_0_R5_0 3 #define J721E_HOST_ID_MCU_0_R5_1 4 #define J721E_HOST_ID_MCU_0_R5_2 5 #define J721E_HOST_ID_MCU_0_R5_3 6 #define J721E_HOST_ID_A72_0 10 #define J721E_HOST_ID_A72_1 11 #define J721E_HOST_ID_A72_2 12 #define J721E_HOST_ID_A72_3 13 #define J721E_HOST_ID_A72_4 14 #define J721E_HOST_ID_C7X_0 20 #define J721E_HOST_ID_C7X_1 21 #define J721E_HOST_ID_C6X_0_0 25 #define J721E_HOST_ID_C6X_0_1 26 #define J721E_HOST_ID_C6X_1_0 27 #define J721E_HOST_ID_C6X_1_1 28 #define J721E_HOST_ID_GPU_0 30 #define J721E_HOST_ID_MAIN_0_R5_0 35 #define J721E_HOST_ID_MAIN_0_R5_1 36 #define J721E_HOST_ID_MAIN_0_R5_2 37 #define J721E_HOST_ID_MAIN_0_R5_3 38 #define J721E_HOST_ID_MAIN_1_R5_0 40 #define J721E_HOST_ID_MAIN_1_R5_1 41 #define J721E_HOST_ID_MAIN_1_R5_2 42 #define J721E_HOST_ID_MAIN_1_R5_3 43 #define J721E_HOST_ID_ICSSG_0 50 #define J721E_HOST_ID_DM2DMSC 250 #define J721E_HOST_ID_DMSC2DM 251 #define J721E_HOST_ID_DM 254 #define J721E_MAX_HOST_IDS 29 extern struct ti_sci_host_info j721e_host_info[]; #endif /* __J721E_HOST_INFO_H */ k3conf_0.3/soc/j721e/j721e_ddr_info.h0000664000175000017500000000343314504336530014032 0ustar /* * J721E DDR performance information * * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __J721E_DDRBW_INFO_H #define __J721E_DDRBW_INFO_H extern struct ddr_perf_soc_info j721e_ddr_perf_info; #endif /* __J721E_DDRBW_INFO_H */ k3conf_0.3/soc/j721e/j721e_rm_info.c0000664000175000017500000001030714375734376013710 0ustar /* * J721E RM Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_rm_info j721e_rm_info[] = { {0x1E40, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x1E80, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x1EC0, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x2000, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x2080, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x20C0, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x2180, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x21C0, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x2200, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x2240, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x33CA, "RESASG_SUBTYPE_IA_VINT"}, {0x33CD, "RESASG_SUBTYPE_GLOBAL_EVENT_SEVT"}, {0x340A, "RESASG_SUBTYPE_IA_VINT"}, {0x340D, "RESASG_SUBTYPE_GLOBAL_EVENT_SEVT"}, {0x344A, "RESASG_SUBTYPE_IA_VINT"}, {0x344D, "RESASG_SUBTYPE_GLOBAL_EVENT_SEVT"}, {0x3480, "RESASG_SUBTYPE_PROXY_PROXIES"}, {0x34C0, "RESASG_SUBTYPE_RA_ERROR_OES"}, {0x34C1, "RESASG_SUBTYPE_RA_GP"}, {0x34C2, "RESASG_SUBTYPE_RA_UDMAP_RX"}, {0x34C3, "RESASG_SUBTYPE_RA_UDMAP_TX"}, {0x34C4, "RESASG_SUBTYPE_RA_UDMAP_TX_EXT"}, {0x34C5, "RESASG_SUBTYPE_RA_UDMAP_RX_H"}, {0x34C6, "RESASG_SUBTYPE_RA_UDMAP_RX_UH"}, {0x34C7, "RESASG_SUBTYPE_RA_UDMAP_TX_H"}, {0x34C8, "RESASG_SUBTYPE_RA_UDMAP_TX_UH"}, {0x34CA, "RESASG_SUBTYPE_RA_VIRTID"}, {0x34CB, "RESASG_SUBTYPE_RA_MONITORS"}, {0x3500, "RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON"}, {0x3501, "RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES"}, {0x3502, "RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER"}, {0x3503, "RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG"}, {0x350A, "RESASG_SUBTYPE_UDMAP_RX_CHAN"}, {0x350B, "RESASG_SUBTYPE_UDMAP_RX_HCHAN"}, {0x350C, "RESASG_SUBTYPE_UDMAP_RX_UHCHAN"}, {0x350D, "RESASG_SUBTYPE_UDMAP_TX_CHAN"}, {0x350E, "RESASG_SUBTYPE_UDMAP_TX_ECHAN"}, {0x350F, "RESASG_SUBTYPE_UDMAP_TX_HCHAN"}, {0x3510, "RESASG_SUBTYPE_UDMAP_TX_UHCHAN"}, {0x3540, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x3A4A, "RESASG_SUBTYPE_IA_VINT"}, {0x3A4D, "RESASG_SUBTYPE_GLOBAL_EVENT_SEVT"}, {0x3A80, "RESASG_SUBTYPE_PROXY_PROXIES"}, {0x3AC0, "RESASG_SUBTYPE_RA_ERROR_OES"}, {0x3AC1, "RESASG_SUBTYPE_RA_GP"}, {0x3AC2, "RESASG_SUBTYPE_RA_UDMAP_RX"}, {0x3AC3, "RESASG_SUBTYPE_RA_UDMAP_TX"}, {0x3AC5, "RESASG_SUBTYPE_RA_UDMAP_RX_H"}, {0x3AC7, "RESASG_SUBTYPE_RA_UDMAP_TX_H"}, {0x3ACA, "RESASG_SUBTYPE_RA_VIRTID"}, {0x3ACB, "RESASG_SUBTYPE_RA_MONITORS"}, {0x3B00, "RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON"}, {0x3B01, "RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES"}, {0x3B02, "RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER"}, {0x3B03, "RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG"}, {0x3B0A, "RESASG_SUBTYPE_UDMAP_RX_CHAN"}, {0x3B0B, "RESASG_SUBTYPE_UDMAP_RX_HCHAN"}, {0x3B0D, "RESASG_SUBTYPE_UDMAP_TX_CHAN"}, {0x3B0F, "RESASG_SUBTYPE_UDMAP_TX_HCHAN"}, {0x3B40, "RESASG_SUBTYPE_IR_OUTPUT"}, }; k3conf_0.3/soc/j721e/j721e_devices_info.h0000664000175000017500000000346414375734376014727 0ustar /* * J721E Devices Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __J721E_DEVICES_INFO_H #define __J721E_DEVICES_INFO_H #define J721E_MAX_DEVICES 334 extern struct ti_sci_devices_info j721e_devices_info[]; #endif /* __J721E_DEVICES_INFO_H */ k3conf_0.3/soc/j721e/j721e_ddr_info.c0000664000175000017500000000367714504336530014037 0ustar /* * J721E DDR performance information * * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #define MAX_PERF_NUM_DDR_INSTANCES 1 static uintptr_t j721e_ddr_base_address[MAX_PERF_NUM_DDR_INSTANCES] = { 0x02980100, }; struct ddr_perf_soc_info j721e_ddr_perf_info = { .num_perf_insts = MAX_PERF_NUM_DDR_INSTANCES, .burst_size = 64, .perf_inst_base = j721e_ddr_base_address, }; k3conf_0.3/soc/j721e/j721e_rm_info.h0000664000175000017500000000342114504336513013675 0ustar /* * J721E RM Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __J721E_RM_INFO_H #define __J721E_RM_INFO_H #define J721E_MAX_RES 60 extern struct ti_sci_rm_info j721e_rm_info[]; #endif /* __J721E_RM_INFO_H */ k3conf_0.3/soc/j721e/j721e_processors_info.c0000664000175000017500000000411514375734376015474 0ustar /* * J721E Processor Info * * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_processors_info j721e_processors_info[] = { {202, 2, 0x20, "A72SS0_CORE0"}, {203, 0, 0x21, "A72SS0_CORE1"}, {142, 6, 0x03, "C66SS0_CORE0"}, {143, 6, 0x04, "C66SS1_CORE0"}, {15, 0, 0x30, "C71SS0"}, {250, 0, 0x01, "MCU_R5FSS0_CORE0"}, {251, 0, 0x02, "MCU_R5FSS0_CORE1"}, {245, 0, 0x06, "R5FSS0_CORE0"}, {246, 0, 0x07, "R5FSS0_CORE1"}, {247, 0, 0x08, "R5FSS1_CORE0"}, {248, 0, 0x09, "R5FSS1_CORE1"}, }; k3conf_0.3/soc/j721e/j721e_clocks_info.h0000664000175000017500000000345614375734376014564 0ustar /* * J721E Clocks Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __J721E_CLOCKS_INFO_H #define __J721E_CLOCKS_INFO_H #define J721E_MAX_CLOCKS 3267 extern struct ti_sci_clocks_info j721e_clocks_info[]; #endif /* __J721E_CLOCKS_INFO_H */ k3conf_0.3/soc/j721e/j721e_host_info.c0000664000175000017500000000713214375734376014251 0ustar /* * J721E Hosts Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_host_info j721e_host_info[] = { {0, "DMSC", "Secure", "Security Controller"}, {3, "MCU_0_R5_0", "Non Secure", "Cortex R5 context 0 on MCU island"}, {4, "MCU_0_R5_1", "Secure", "Cortex R5 context 1 on MCU island(Boot)"}, {5, "MCU_0_R5_2", "Non Secure", "Cortex R5 context 2 on MCU island"}, {6, "MCU_0_R5_3", "Secure", "Cortex R5 context 3 on MCU island"}, {10, "A72_0", "Secure", "Cortex A72 context 0 on Main island"}, {11, "A72_1", "Secure", "Cortex A72 context 1 on Main island"}, {12, "A72_2", "Non Secure", "Cortex A72 context 2 on Main island"}, {13, "A72_3", "Non Secure", "Cortex A72 context 3 on Main island"}, {14, "A72_4", "Non Secure", "Cortex A72 context 4 on Main island"}, {20, "C7X_0", "Secure", "C7x Context 0 on Main island"}, {21, "C7X_1", "Non Secure", "C7x context 1 on Main island"}, {25, "C6X_0_0", "Secure", "C6x_0 Context 0 on Main island"}, {26, "C6X_0_1", "Non Secure", "C6x_0 context 1 on Main island"}, {27, "C6X_1_0", "Secure", "C6x_1 Context 0 on Main island"}, {28, "C6X_1_1", "Non Secure", "C6x_1 context 1 on Main island"}, {30, "GPU_0", "Non Secure", "RGX context 0 on Main island"}, {35, "MAIN_0_R5_0", "Non Secure", "Cortex R5_0 context 0 on Main island"}, {36, "MAIN_0_R5_1", "Secure", "Cortex R5_0 context 1 on Main island"}, {37, "MAIN_0_R5_2", "Non Secure", "Cortex R5_0 context 2 on Main island"}, {38, "MAIN_0_R5_3", "Secure", "Cortex R5_0 context 3 on Main island"}, {40, "MAIN_1_R5_0", "Non Secure", "Cortex R5_1 context 0 on Main island"}, {41, "MAIN_1_R5_1", "Secure", "Cortex R5_1 context 1 on Main island"}, {42, "MAIN_1_R5_2", "Non Secure", "Cortex R5_1 context 2 on Main island"}, {43, "MAIN_1_R5_3", "Secure", "Cortex R5_1 context 3 on Main island"}, {50, "ICSSG_0", "Non Secure", "ICSSG context 0 on Main island"}, {250, "DM2DMSC", "Secure", "DM to DMSC communication"}, {251, "DMSC2DM", "Non Secure", "DMSC to DM communication"}, {254, "DM", "Non Secure", "Device Management"}, }; k3conf_0.3/soc/j721e/j721e_devices_info.c0000664000175000017500000003002014375734376014706 0ustar /* * J721E Devices Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_devices_info j721e_devices_info[] = { {0, "J721E_DEV_MCU_ADC12_16FFC0"}, {1, "J721E_DEV_MCU_ADC12_16FFC1"}, {2, "J721E_DEV_ATL0"}, {3, "J721E_DEV_COMPUTE_CLUSTER0"}, {4, "J721E_DEV_A72SS0"}, {5, "J721E_DEV_COMPUTE_CLUSTER0_CFG_WRAP"}, {6, "J721E_DEV_COMPUTE_CLUSTER0_CLEC"}, {7, "J721E_DEV_COMPUTE_CLUSTER0_CORE_CORE"}, {8, "J721E_DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW"}, {9, "J721E_DEV_COMPUTE_CLUSTER0_DEBUG_WRAP"}, {10, "J721E_DEV_COMPUTE_CLUSTER0_DIVH2_DIVH0"}, {11, "J721E_DEV_COMPUTE_CLUSTER0_DIVP_TFT0"}, {12, "J721E_DEV_COMPUTE_CLUSTER0_DMSC_WRAP"}, {13, "J721E_DEV_COMPUTE_CLUSTER0_EN_MSMC_DOMAIN"}, {14, "J721E_DEV_COMPUTE_CLUSTER0_GIC500SS"}, {15, "J721E_DEV_C71SS0"}, {16, "J721E_DEV_C71SS0_MMA"}, {17, "J721E_DEV_COMPUTE_CLUSTER0_PBIST_WRAP"}, {18, "J721E_DEV_MCU_CPSW0"}, {19, "J721E_DEV_CPSW0"}, {20, "J721E_DEV_CPT2_AGGR0"}, {21, "J721E_DEV_CPT2_AGGR1"}, {22, "J721E_DEV_WKUP_DMSC0"}, {23, "J721E_DEV_CPT2_AGGR2"}, {24, "J721E_DEV_MCU_CPT2_AGGR0"}, {25, "J721E_DEV_CSI_PSILSS0"}, {26, "J721E_DEV_CSI_RX_IF0"}, {27, "J721E_DEV_CSI_RX_IF1"}, {28, "J721E_DEV_CSI_TX_IF0"}, {29, "J721E_DEV_STM0"}, {30, "J721E_DEV_DCC0"}, {31, "J721E_DEV_DCC1"}, {32, "J721E_DEV_DCC2"}, {33, "J721E_DEV_DCC3"}, {34, "J721E_DEV_DCC4"}, {35, "J721E_DEV_MCU_TIMER0"}, {36, "J721E_DEV_DCC5"}, {37, "J721E_DEV_DCC6"}, {38, "J721E_DEV_DCC7"}, {39, "J721E_DEV_DCC8"}, {40, "J721E_DEV_DCC9"}, {41, "J721E_DEV_DCC10"}, {42, "J721E_DEV_DCC11"}, {43, "J721E_DEV_DCC12"}, {44, "J721E_DEV_MCU_DCC0"}, {45, "J721E_DEV_MCU_DCC1"}, {46, "J721E_DEV_MCU_DCC2"}, {47, "J721E_DEV_DDR0"}, {48, "J721E_DEV_DMPAC0"}, {49, "J721E_DEV_TIMER0"}, {50, "J721E_DEV_TIMER1"}, {51, "J721E_DEV_TIMER2"}, {52, "J721E_DEV_TIMER3"}, {53, "J721E_DEV_TIMER4"}, {54, "J721E_DEV_TIMER5"}, {55, "J721E_DEV_TIMER6"}, {57, "J721E_DEV_TIMER7"}, {58, "J721E_DEV_TIMER8"}, {59, "J721E_DEV_TIMER9"}, {60, "J721E_DEV_TIMER10"}, {61, "J721E_DEV_GTC0"}, {62, "J721E_DEV_TIMER11"}, {63, "J721E_DEV_TIMER12"}, {64, "J721E_DEV_TIMER13"}, {65, "J721E_DEV_TIMER14"}, {66, "J721E_DEV_TIMER15"}, {67, "J721E_DEV_TIMER16"}, {68, "J721E_DEV_TIMER17"}, {69, "J721E_DEV_TIMER18"}, {70, "J721E_DEV_TIMER19"}, {71, "J721E_DEV_MCU_TIMER1"}, {72, "J721E_DEV_MCU_TIMER2"}, {73, "J721E_DEV_MCU_TIMER3"}, {74, "J721E_DEV_MCU_TIMER4"}, {75, "J721E_DEV_MCU_TIMER5"}, {76, "J721E_DEV_MCU_TIMER6"}, {77, "J721E_DEV_MCU_TIMER7"}, {78, "J721E_DEV_MCU_TIMER8"}, {79, "J721E_DEV_MCU_TIMER9"}, {80, "J721E_DEV_ECAP0"}, {81, "J721E_DEV_ECAP1"}, {82, "J721E_DEV_ECAP2"}, {83, "J721E_DEV_EHRPWM0"}, {84, "J721E_DEV_EHRPWM1"}, {85, "J721E_DEV_EHRPWM2"}, {86, "J721E_DEV_EHRPWM3"}, {87, "J721E_DEV_EHRPWM4"}, {88, "J721E_DEV_EHRPWM5"}, {89, "J721E_DEV_ELM0"}, {90, "J721E_DEV_EMIF_DATA_0_VD"}, {91, "J721E_DEV_MMCSD0"}, {92, "J721E_DEV_MMCSD1"}, {93, "J721E_DEV_MMCSD2"}, {94, "J721E_DEV_EQEP0"}, {95, "J721E_DEV_EQEP1"}, {96, "J721E_DEV_EQEP2"}, {97, "J721E_DEV_ESM0"}, {98, "J721E_DEV_MCU_ESM0"}, {99, "J721E_DEV_WKUP_ESM0"}, {100, "J721E_DEV_MCU_FSS0"}, {101, "J721E_DEV_MCU_FSS0_FSAS_0"}, {102, "J721E_DEV_MCU_FSS0_HYPERBUS1P0_0"}, {103, "J721E_DEV_MCU_FSS0_OSPI_0"}, {104, "J721E_DEV_MCU_FSS0_OSPI_1"}, {105, "J721E_DEV_GPIO0"}, {106, "J721E_DEV_GPIO1"}, {107, "J721E_DEV_GPIO2"}, {108, "J721E_DEV_GPIO3"}, {109, "J721E_DEV_GPIO4"}, {110, "J721E_DEV_GPIO5"}, {111, "J721E_DEV_GPIO6"}, {112, "J721E_DEV_GPIO7"}, {113, "J721E_DEV_WKUP_GPIO0"}, {114, "J721E_DEV_WKUP_GPIO1"}, {115, "J721E_DEV_GPMC0"}, {116, "J721E_DEV_I3C0"}, {117, "J721E_DEV_MCU_I3C0"}, {118, "J721E_DEV_MCU_I3C1"}, {119, "J721E_DEV_PRU_ICSSG0"}, {120, "J721E_DEV_PRU_ICSSG1"}, {121, "J721E_DEV_C66SS0_INTROUTER0"}, {122, "J721E_DEV_C66SS1_INTROUTER0"}, {123, "J721E_DEV_CMPEVENT_INTRTR0"}, {124, "J721E_DEV_GPU0"}, {125, "J721E_DEV_GPU0_GPU_0"}, {126, "J721E_DEV_GPU0_GPUCORE_0"}, {127, "J721E_DEV_LED0"}, {128, "J721E_DEV_MAIN2MCU_LVL_INTRTR0"}, {130, "J721E_DEV_MAIN2MCU_PLS_INTRTR0"}, {131, "J721E_DEV_GPIOMUX_INTRTR0"}, {132, "J721E_DEV_WKUP_PORZ_SYNC0"}, {133, "J721E_DEV_PSC0"}, {134, "J721E_DEV_R5FSS0_INTROUTER0"}, {135, "J721E_DEV_R5FSS1_INTROUTER0"}, {136, "J721E_DEV_TIMESYNC_INTRTR0"}, {137, "J721E_DEV_WKUP_GPIOMUX_INTRTR0"}, {138, "J721E_DEV_WKUP_PSC0"}, {139, "J721E_DEV_AASRC0"}, {140, "J721E_DEV_C66SS0"}, {141, "J721E_DEV_C66SS1"}, {142, "J721E_DEV_C66SS0_CORE0"}, {143, "J721E_DEV_C66SS1_CORE0"}, {144, "J721E_DEV_DECODER0"}, {145, "J721E_DEV_WKUP_DDPA0"}, {146, "J721E_DEV_UART0"}, {147, "J721E_DEV_DPHY_RX0"}, {148, "J721E_DEV_DPHY_RX1"}, {149, "J721E_DEV_MCU_UART0"}, {150, "J721E_DEV_DSS_DSI0"}, {151, "J721E_DEV_DSS_EDP0"}, {152, "J721E_DEV_DSS0"}, {153, "J721E_DEV_ENCODER0"}, {154, "J721E_DEV_WKUP_VTM0"}, {155, "J721E_DEV_MAIN2WKUPMCU_VD"}, {156, "J721E_DEV_MCAN0"}, {157, "J721E_DEV_BOARD0"}, {158, "J721E_DEV_MCAN1"}, {160, "J721E_DEV_MCAN2"}, {161, "J721E_DEV_MCAN3"}, {162, "J721E_DEV_MCAN4"}, {163, "J721E_DEV_MCAN5"}, {164, "J721E_DEV_MCAN6"}, {165, "J721E_DEV_MCAN7"}, {166, "J721E_DEV_MCAN8"}, {167, "J721E_DEV_MCAN9"}, {168, "J721E_DEV_MCAN10"}, {169, "J721E_DEV_MCAN11"}, {170, "J721E_DEV_MCAN12"}, {171, "J721E_DEV_MCAN13"}, {172, "J721E_DEV_MCU_MCAN0"}, {173, "J721E_DEV_MCU_MCAN1"}, {174, "J721E_DEV_MCASP0"}, {175, "J721E_DEV_MCASP1"}, {176, "J721E_DEV_MCASP2"}, {177, "J721E_DEV_MCASP3"}, {178, "J721E_DEV_MCASP4"}, {179, "J721E_DEV_MCASP5"}, {180, "J721E_DEV_MCASP6"}, {181, "J721E_DEV_MCASP7"}, {182, "J721E_DEV_MCASP8"}, {183, "J721E_DEV_MCASP9"}, {184, "J721E_DEV_MCASP10"}, {185, "J721E_DEV_MCASP11"}, {186, "J721E_DEV_MLB0"}, {187, "J721E_DEV_I2C0"}, {188, "J721E_DEV_I2C1"}, {189, "J721E_DEV_I2C2"}, {190, "J721E_DEV_I2C3"}, {191, "J721E_DEV_I2C4"}, {192, "J721E_DEV_I2C5"}, {193, "J721E_DEV_I2C6"}, {194, "J721E_DEV_MCU_I2C0"}, {195, "J721E_DEV_MCU_I2C1"}, {197, "J721E_DEV_WKUP_I2C0"}, {199, "J721E_DEV_NAVSS0"}, {201, "J721E_DEV_NAVSS0_CPTS_0"}, {202, "J721E_DEV_A72SS0_CORE0"}, {203, "J721E_DEV_A72SS0_CORE1"}, {206, "J721E_DEV_NAVSS0_DTI_0"}, {207, "J721E_DEV_NAVSS0_MODSS_INTAGGR_0"}, {208, "J721E_DEV_NAVSS0_MODSS_INTAGGR_1"}, {209, "J721E_DEV_NAVSS0_UDMASS_INTAGGR_0"}, {210, "J721E_DEV_NAVSS0_PROXY_0"}, {211, "J721E_DEV_NAVSS0_RINGACC_0"}, {212, "J721E_DEV_NAVSS0_UDMAP_0"}, {213, "J721E_DEV_NAVSS0_INTR_ROUTER_0"}, {214, "J721E_DEV_NAVSS0_MAILBOX_0"}, {215, "J721E_DEV_NAVSS0_MAILBOX_1"}, {216, "J721E_DEV_NAVSS0_MAILBOX_2"}, {217, "J721E_DEV_NAVSS0_MAILBOX_3"}, {218, "J721E_DEV_NAVSS0_MAILBOX_4"}, {219, "J721E_DEV_NAVSS0_MAILBOX_5"}, {220, "J721E_DEV_NAVSS0_MAILBOX_6"}, {221, "J721E_DEV_NAVSS0_MAILBOX_7"}, {222, "J721E_DEV_NAVSS0_MAILBOX_8"}, {223, "J721E_DEV_NAVSS0_MAILBOX_9"}, {224, "J721E_DEV_NAVSS0_MAILBOX_10"}, {225, "J721E_DEV_NAVSS0_MAILBOX_11"}, {226, "J721E_DEV_NAVSS0_SPINLOCK_0"}, {227, "J721E_DEV_NAVSS0_MCRC_0"}, {228, "J721E_DEV_NAVSS0_TBU_0"}, {229, "J721E_DEV_NAVSS0_TCU_0"}, {230, "J721E_DEV_NAVSS0_TIMERMGR_0"}, {231, "J721E_DEV_NAVSS0_TIMERMGR_1"}, {232, "J721E_DEV_MCU_NAVSS0"}, {233, "J721E_DEV_MCU_NAVSS0_UDMASS_INTA_0"}, {234, "J721E_DEV_MCU_NAVSS0_PROXY0"}, {235, "J721E_DEV_MCU_NAVSS0_RINGACC0"}, {236, "J721E_DEV_MCU_NAVSS0_UDMAP_0"}, {237, "J721E_DEV_MCU_NAVSS0_INTR_0"}, {238, "J721E_DEV_MCU_NAVSS0_MCRC_0"}, {239, "J721E_DEV_PCIE0"}, {240, "J721E_DEV_PCIE1"}, {241, "J721E_DEV_PCIE2"}, {242, "J721E_DEV_PCIE3"}, {243, "J721E_DEV_R5FSS0"}, {244, "J721E_DEV_R5FSS1"}, {245, "J721E_DEV_R5FSS0_CORE0"}, {246, "J721E_DEV_R5FSS0_CORE1"}, {247, "J721E_DEV_R5FSS1_CORE0"}, {248, "J721E_DEV_R5FSS1_CORE1"}, {249, "J721E_DEV_MCU_R5FSS0"}, {250, "J721E_DEV_MCU_R5FSS0_CORE0"}, {251, "J721E_DEV_MCU_R5FSS0_CORE1"}, {252, "J721E_DEV_RTI0"}, {253, "J721E_DEV_RTI1"}, {254, "J721E_DEV_RTI24"}, {255, "J721E_DEV_RTI25"}, {256, "J721E_DEV_RTI16"}, {257, "J721E_DEV_RTI15"}, {258, "J721E_DEV_RTI28"}, {259, "J721E_DEV_RTI29"}, {260, "J721E_DEV_RTI30"}, {261, "J721E_DEV_RTI31"}, {262, "J721E_DEV_MCU_RTI0"}, {263, "J721E_DEV_MCU_RTI1"}, {264, "J721E_DEV_SA2_UL0"}, {265, "J721E_DEV_MCU_SA2_UL0"}, {266, "J721E_DEV_MCSPI0"}, {267, "J721E_DEV_MCSPI1"}, {268, "J721E_DEV_MCSPI2"}, {269, "J721E_DEV_MCSPI3"}, {270, "J721E_DEV_MCSPI4"}, {271, "J721E_DEV_MCSPI5"}, {272, "J721E_DEV_MCSPI6"}, {273, "J721E_DEV_MCSPI7"}, {274, "J721E_DEV_MCU_MCSPI0"}, {275, "J721E_DEV_MCU_MCSPI1"}, {276, "J721E_DEV_MCU_MCSPI2"}, {277, "J721E_DEV_UFS0"}, {278, "J721E_DEV_UART1"}, {279, "J721E_DEV_UART2"}, {280, "J721E_DEV_UART3"}, {281, "J721E_DEV_UART4"}, {282, "J721E_DEV_UART5"}, {283, "J721E_DEV_UART6"}, {284, "J721E_DEV_UART7"}, {285, "J721E_DEV_UART8"}, {286, "J721E_DEV_UART9"}, {287, "J721E_DEV_WKUP_UART0"}, {288, "J721E_DEV_USB0"}, {289, "J721E_DEV_USB1"}, {290, "J721E_DEV_VPAC0"}, {291, "J721E_DEV_VPFE0"}, {292, "J721E_DEV_SERDES_16G0"}, {293, "J721E_DEV_SERDES_16G1"}, {294, "J721E_DEV_SERDES_16G2"}, {295, "J721E_DEV_SERDES_16G3"}, {296, "J721E_DEV_DPHY_TX0"}, {297, "J721E_DEV_SERDES_10G0"}, {298, "J721E_DEV_WKUPMCU2MAIN_VD"}, {299, "J721E_DEV_NAVSS0_MODSS"}, {300, "J721E_DEV_NAVSS0_UDMASS"}, {301, "J721E_DEV_NAVSS0_VIRTSS"}, {302, "J721E_DEV_MCU_NAVSS0_MODSS"}, {303, "J721E_DEV_MCU_NAVSS0_UDMASS"}, {304, "J721E_DEV_DEBUGSS_WRAP0"}, {305, "J721E_DEV_DMPAC0_SDE_0"}, {306, "J721E_DEV_GPU0_DFT_PBIST_0"}, {307, "J721E_DEV_C66SS0_PBIST0"}, {308, "J721E_DEV_C66SS1_PBIST0"}, {309, "J721E_DEV_PBIST0"}, {310, "J721E_DEV_PBIST1"}, {311, "J721E_DEV_PBIST2"}, {312, "J721E_DEV_PBIST3"}, {313, "J721E_DEV_PBIST4"}, {314, "J721E_DEV_PBIST5"}, {315, "J721E_DEV_PBIST6"}, {316, "J721E_DEV_PBIST7"}, {317, "J721E_DEV_PBIST9"}, {318, "J721E_DEV_PBIST10"}, {319, "J721E_DEV_MCU_PBIST0"}, {320, "J721E_DEV_MCU_PBIST1"}, {321, "J721E_DEV_C71X_0_PBIST_VD"}, {322, "J721E_DEV_MCU_TIMER1_CLKSEL_VD"}, {323, "J721E_DEV_MCU_TIMER3_CLKSEL_VD"}, {324, "J721E_DEV_MCU_TIMER5_CLKSEL_VD"}, {325, "J721E_DEV_MCU_TIMER7_CLKSEL_VD"}, {326, "J721E_DEV_MCU_TIMER9_CLKSEL_VD"}, {327, "J721E_DEV_TIMER1_CLKSEL_VD"}, {328, "J721E_DEV_TIMER3_CLKSEL_VD"}, {329, "J721E_DEV_TIMER5_CLKSEL_VD"}, {330, "J721E_DEV_TIMER7_CLKSEL_VD"}, {331, "J721E_DEV_TIMER9_CLKSEL_VD"}, {332, "J721E_DEV_TIMER11_CLKSEL_VD"}, {333, "J721E_DEV_TIMER13_CLKSEL_VD"}, {334, "J721E_DEV_TIMER15_CLKSEL_VD"}, {335, "J721E_DEV_TIMER17_CLKSEL_VD"}, {336, "J721E_DEV_TIMER19_CLKSEL_VD"}, {337, "J721E_DEV_ASCPCIE_BUFFER0"}, {338, "J721E_DEV_ASCPCIE_BUFFER1"}, {339, "J721E_DEV_NAVSS0_PVU_0"}, {340, "J721E_DEV_NAVSS0_PVU_1"}, {341, "J721E_DEV_NAVSS0_PVU_2"}, }; k3conf_0.3/soc/j721e/j721e_sec_proxy_info.c0000664000175000017500000002313114375734376015304 0ustar /* * J721E Sec Proxy Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_sec_proxy_info j721e_main_sp_info[] = { {138, "read", 22, "DM", "nonsec_high_priority_rx"}, {137, "read", 67, "DM", "nonsec_low_priority_rx"}, {136, "read", 22, "DM", "nonsec_notify_resp_rx"}, {135, "write", 2, "DM", "nonsec_A72_2_notify_tx"}, {134, "write", 22, "DM", "nonsec_A72_2_response_tx"}, {133, "write", 2, "DM", "nonsec_A72_3_notify_tx"}, {132, "write", 7, "DM", "nonsec_A72_3_response_tx"}, {131, "write", 2, "DM", "nonsec_A72_4_notify_tx"}, {130, "write", 7, "DM", "nonsec_A72_4_response_tx"}, {129, "write", 2, "DM", "nonsec_C7X_1_notify_tx"}, {128, "write", 7, "DM", "nonsec_C7X_1_response_tx"}, {127, "write", 2, "DM", "nonsec_C6X_0_1_notify_tx"}, {126, "write", 7, "DM", "nonsec_C6X_0_1_response_tx"}, {125, "write", 2, "DM", "nonsec_C6X_1_1_notify_tx"}, {124, "write", 7, "DM", "nonsec_C6X_1_1_response_tx"}, {123, "write", 2, "DM", "nonsec_GPU_0_notify_tx"}, {122, "write", 7, "DM", "nonsec_GPU_0_response_tx"}, {121, "write", 2, "DM", "nonsec_MAIN_0_R5_0_notify_tx"}, {120, "write", 7, "DM", "nonsec_MAIN_0_R5_0_response_tx"}, {119, "write", 1, "DM", "nonsec_MAIN_0_R5_2_notify_tx"}, {118, "write", 2, "DM", "nonsec_MAIN_0_R5_2_response_tx"}, {117, "write", 2, "DM", "nonsec_MAIN_1_R5_0_notify_tx"}, {116, "write", 7, "DM", "nonsec_MAIN_1_R5_0_response_tx"}, {115, "write", 1, "DM", "nonsec_MAIN_1_R5_2_notify_tx"}, {114, "write", 2, "DM", "nonsec_MAIN_1_R5_2_response_tx"}, {113, "write", 2, "DM", "nonsec_ICSSG_0_notify_tx"}, {112, "write", 7, "DM", "nonsec_ICSSG_0_response_tx"}, {0, "read", 2, "A72_0", "notify"}, {1, "read", 30, "A72_0", "response"}, {2, "write", 10, "A72_0", "high_priority"}, {3, "write", 20, "A72_0", "low_priority"}, {4, "write", 2, "A72_0", "notify_resp"}, {5, "read", 2, "A72_1", "notify"}, {6, "read", 30, "A72_1", "response"}, {7, "write", 10, "A72_1", "high_priority"}, {8, "write", 20, "A72_1", "low_priority"}, {9, "write", 2, "A72_1", "notify_resp"}, {10, "read", 2, "A72_2", "notify"}, {11, "read", 22, "A72_2", "response"}, {12, "write", 2, "A72_2", "high_priority"}, {13, "write", 20, "A72_2", "low_priority"}, {14, "write", 2, "A72_2", "notify_resp"}, {15, "read", 2, "A72_3", "notify"}, {16, "read", 7, "A72_3", "response"}, {17, "write", 2, "A72_3", "high_priority"}, {18, "write", 5, "A72_3", "low_priority"}, {19, "write", 2, "A72_3", "notify_resp"}, {20, "read", 2, "A72_4", "notify"}, {21, "read", 7, "A72_4", "response"}, {22, "write", 2, "A72_4", "high_priority"}, {23, "write", 5, "A72_4", "low_priority"}, {24, "write", 2, "A72_4", "notify_resp"}, {25, "read", 2, "C7X_0", "notify"}, {26, "read", 7, "C7X_0", "response"}, {27, "write", 2, "C7X_0", "high_priority"}, {28, "write", 5, "C7X_0", "low_priority"}, {29, "write", 2, "C7X_0", "notify_resp"}, {30, "read", 2, "C7X_1", "notify"}, {31, "read", 7, "C7X_1", "response"}, {32, "write", 2, "C7X_1", "high_priority"}, {33, "write", 5, "C7X_1", "low_priority"}, {34, "write", 2, "C7X_1", "notify_resp"}, {35, "read", 2, "C6X_0_0", "notify"}, {36, "read", 7, "C6X_0_0", "response"}, {37, "write", 2, "C6X_0_0", "high_priority"}, {38, "write", 5, "C6X_0_0", "low_priority"}, {39, "write", 2, "C6X_0_0", "notify_resp"}, {40, "read", 2, "C6X_0_1", "notify"}, {41, "read", 7, "C6X_0_1", "response"}, {42, "write", 2, "C6X_0_1", "high_priority"}, {43, "write", 5, "C6X_0_1", "low_priority"}, {44, "write", 2, "C6X_0_1", "notify_resp"}, {45, "read", 2, "C6X_1_0", "notify"}, {46, "read", 7, "C6X_1_0", "response"}, {47, "write", 2, "C6X_1_0", "high_priority"}, {48, "write", 5, "C6X_1_0", "low_priority"}, {49, "write", 2, "C6X_1_0", "notify_resp"}, {50, "read", 2, "C6X_1_1", "notify"}, {51, "read", 7, "C6X_1_1", "response"}, {52, "write", 2, "C6X_1_1", "high_priority"}, {53, "write", 5, "C6X_1_1", "low_priority"}, {54, "write", 2, "C6X_1_1", "notify_resp"}, {55, "read", 2, "GPU_0", "notify"}, {56, "read", 7, "GPU_0", "response"}, {57, "write", 2, "GPU_0", "high_priority"}, {58, "write", 5, "GPU_0", "low_priority"}, {59, "write", 2, "GPU_0", "notify_resp"}, {60, "read", 2, "MAIN_0_R5_0", "notify"}, {61, "read", 7, "MAIN_0_R5_0", "response"}, {62, "write", 2, "MAIN_0_R5_0", "high_priority"}, {63, "write", 5, "MAIN_0_R5_0", "low_priority"}, {64, "write", 2, "MAIN_0_R5_0", "notify_resp"}, {65, "read", 2, "MAIN_0_R5_1", "notify"}, {66, "read", 7, "MAIN_0_R5_1", "response"}, {67, "write", 2, "MAIN_0_R5_1", "high_priority"}, {68, "write", 5, "MAIN_0_R5_1", "low_priority"}, {69, "write", 2, "MAIN_0_R5_1", "notify_resp"}, {70, "read", 1, "MAIN_0_R5_2", "notify"}, {71, "read", 2, "MAIN_0_R5_2", "response"}, {72, "write", 1, "MAIN_0_R5_2", "high_priority"}, {73, "write", 1, "MAIN_0_R5_2", "low_priority"}, {74, "write", 1, "MAIN_0_R5_2", "notify_resp"}, {75, "read", 1, "MAIN_0_R5_3", "notify"}, {76, "read", 2, "MAIN_0_R5_3", "response"}, {77, "write", 1, "MAIN_0_R5_3", "high_priority"}, {78, "write", 1, "MAIN_0_R5_3", "low_priority"}, {79, "write", 1, "MAIN_0_R5_3", "notify_resp"}, {80, "read", 2, "MAIN_1_R5_0", "notify"}, {81, "read", 7, "MAIN_1_R5_0", "response"}, {82, "write", 2, "MAIN_1_R5_0", "high_priority"}, {83, "write", 5, "MAIN_1_R5_0", "low_priority"}, {84, "write", 2, "MAIN_1_R5_0", "notify_resp"}, {85, "read", 2, "MAIN_1_R5_1", "notify"}, {86, "read", 7, "MAIN_1_R5_1", "response"}, {87, "write", 2, "MAIN_1_R5_1", "high_priority"}, {88, "write", 5, "MAIN_1_R5_1", "low_priority"}, {89, "write", 2, "MAIN_1_R5_1", "notify_resp"}, {90, "read", 1, "MAIN_1_R5_2", "notify"}, {91, "read", 2, "MAIN_1_R5_2", "response"}, {92, "write", 1, "MAIN_1_R5_2", "high_priority"}, {93, "write", 1, "MAIN_1_R5_2", "low_priority"}, {94, "write", 1, "MAIN_1_R5_2", "notify_resp"}, {95, "read", 1, "MAIN_1_R5_3", "notify"}, {96, "read", 2, "MAIN_1_R5_3", "response"}, {97, "write", 1, "MAIN_1_R5_3", "high_priority"}, {98, "write", 1, "MAIN_1_R5_3", "low_priority"}, {99, "write", 1, "MAIN_1_R5_3", "notify_resp"}, {100, "read", 2, "ICSSG_0", "notify"}, {101, "read", 7, "ICSSG_0", "response"}, {102, "write", 2, "ICSSG_0", "high_priority"}, {103, "write", 5, "ICSSG_0", "low_priority"}, {104, "write", 2, "ICSSG_0", "notify_resp"}, }; struct ti_sci_sec_proxy_info j721e_mcu_sp_info[] = { {80, "read", 15, "DM", "nonsec_high_priority_rx"}, {79, "read", 15, "DM", "nonsec_low_priority_rx"}, {78, "read", 5, "DM", "nonsec_notify_resp_rx"}, {77, "write", 2, "DM", "nonsec_MCU_0_R5_0_notify_tx"}, {76, "write", 20, "DM", "nonsec_MCU_0_R5_0_response_tx"}, {75, "write", 1, "DM", "nonsec_MCU_0_R5_2_notify_tx"}, {74, "write", 2, "DM", "nonsec_MCU_0_R5_2_response_tx"}, {73, "write", 2, "DM", "nonsec_DMSC2DM_notify_tx"}, {72, "write", 4, "DM", "nonsec_DMSC2DM_response_tx"}, {0, "read", 2, "MCU_0_R5_0", "notify"}, {1, "read", 20, "MCU_0_R5_0", "response"}, {2, "write", 10, "MCU_0_R5_0", "high_priority"}, {3, "write", 10, "MCU_0_R5_0", "low_priority"}, {4, "write", 2, "MCU_0_R5_0", "notify_resp"}, {5, "read", 2, "MCU_0_R5_1", "notify"}, {6, "read", 20, "MCU_0_R5_1", "response"}, {7, "write", 10, "MCU_0_R5_1", "high_priority"}, {8, "write", 10, "MCU_0_R5_1", "low_priority"}, {9, "write", 2, "MCU_0_R5_1", "notify_resp"}, {10, "read", 1, "MCU_0_R5_2", "notify"}, {11, "read", 2, "MCU_0_R5_2", "response"}, {12, "write", 1, "MCU_0_R5_2", "high_priority"}, {13, "write", 1, "MCU_0_R5_2", "low_priority"}, {14, "write", 1, "MCU_0_R5_2", "notify_resp"}, {15, "read", 1, "MCU_0_R5_3", "notify"}, {16, "read", 2, "MCU_0_R5_3", "response"}, {17, "write", 1, "MCU_0_R5_3", "high_priority"}, {18, "write", 1, "MCU_0_R5_3", "low_priority"}, {19, "write", 1, "MCU_0_R5_3", "notify_resp"}, {20, "read", 2, "DM2DMSC", "notify"}, {21, "read", 4, "DM2DMSC", "response"}, {22, "write", 2, "DM2DMSC", "high_priority"}, {23, "write", 2, "DM2DMSC", "low_priority"}, {24, "write", 2, "DM2DMSC", "notify_resp"}, {25, "read", 2, "DMSC2DM", "notify"}, {26, "read", 4, "DMSC2DM", "response"}, {27, "write", 4, "DMSC2DM", "high_priority"}, {28, "write", 4, "DMSC2DM", "low_priority"}, {29, "write", 2, "DMSC2DM", "notify_resp"}, }; k3conf_0.3/soc/j721e/j721e_processors_info.h0000664000175000017500000000350714504336513015466 0ustar /* * J721E Processor Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __J721E_PROCESSOR_INFO_H #define __J721E_PROCESSOR_INFO_H #define J721E_MAX_PROCESSORS_IDS 11 extern struct ti_sci_processors_info j721e_processors_info[]; #endif /* __J721E_PROCESSOR_INFO_H */ k3conf_0.3/soc/j721e/j721e_clocks_info.c0000664000175000017500000116326414375734376014564 0ustar /* * J721E Clocks Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_clocks_info j721e_clocks_info[] = { {4, 0, "DEV_A72SS0_PLL_CTRL_CLK", "Input clock"}, {4, 1, "DEV_A72SS0_MSMC_CLK", "Input clock"}, {4, 2, "DEV_A72SS0_ARM_CLK_CLK", "Input clock"}, {202, 2, "DEV_A72SS0_CORE0_ARM_CLK_CLK", "Input clock"}, {203, 0, "DEV_A72SS0_CORE1_ARM_CLK_CLK", "Input clock"}, {139, 0, "DEV_AASRC0_SYS_CLK", "Input clock"}, {139, 1, "DEV_AASRC0_VBUSP_CLK", "Input clock"}, {139, 2, "DEV_AASRC0_RX0_SYNC", "Input muxed clock"}, {139, 3, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP0_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 4, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP1_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 5, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP2_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 6, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP3_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 7, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP4_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 8, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP5_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 9, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP6_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 10, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP7_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 11, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP8_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 12, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP9_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 13, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP10_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 14, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP11_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 15, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 16, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 17, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 18, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 19, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 20, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 21, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 22, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 23, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 24, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 25, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 26, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 27, "DEV_AASRC0_RX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 28, "DEV_AASRC0_RX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 29, "DEV_AASRC0_RX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 30, "DEV_AASRC0_RX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 31, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 32, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 33, "DEV_AASRC0_RX0_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 34, "DEV_AASRC0_RX0_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 35, "DEV_AASRC0_RX0_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 36, "DEV_AASRC0_RX0_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 37, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 38, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"}, {139, 39, "DEV_AASRC0_RX1_SYNC", "Input muxed clock"}, {139, 40, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP0_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 41, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP1_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 42, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP2_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 43, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP3_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 44, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP4_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 45, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP5_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 46, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP6_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 47, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP7_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 48, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP8_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 49, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP9_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 50, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP10_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 51, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP11_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 52, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 53, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 54, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 55, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 56, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 57, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 58, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 59, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 60, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 61, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 62, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 63, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 64, "DEV_AASRC0_RX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 65, "DEV_AASRC0_RX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 66, "DEV_AASRC0_RX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 67, "DEV_AASRC0_RX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 68, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 69, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 70, "DEV_AASRC0_RX1_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 71, "DEV_AASRC0_RX1_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 72, "DEV_AASRC0_RX1_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 73, "DEV_AASRC0_RX1_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 74, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 75, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"}, {139, 76, "DEV_AASRC0_RX2_SYNC", "Input muxed clock"}, {139, 77, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP0_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 78, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP1_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 79, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP2_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 80, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP3_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 81, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP4_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 82, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP5_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 83, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP6_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 84, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP7_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 85, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP8_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 86, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP9_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 87, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP10_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 88, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP11_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 89, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 90, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 91, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 92, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 93, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 94, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 95, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 96, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 97, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 98, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 99, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 100, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 101, "DEV_AASRC0_RX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 102, "DEV_AASRC0_RX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 103, "DEV_AASRC0_RX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 104, "DEV_AASRC0_RX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 105, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 106, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 107, "DEV_AASRC0_RX2_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 108, "DEV_AASRC0_RX2_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 109, "DEV_AASRC0_RX2_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 110, "DEV_AASRC0_RX2_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 111, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 112, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"}, {139, 113, "DEV_AASRC0_RX3_SYNC", "Input muxed clock"}, {139, 114, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP0_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 115, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP1_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 116, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP2_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 117, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP3_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 118, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP4_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 119, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP5_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 120, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP6_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 121, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP7_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 122, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP8_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 123, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP9_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 124, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP10_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 125, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP11_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 126, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 127, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 128, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 129, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 130, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 131, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 132, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 133, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 134, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 135, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 136, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 137, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 138, "DEV_AASRC0_RX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 139, "DEV_AASRC0_RX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 140, "DEV_AASRC0_RX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 141, "DEV_AASRC0_RX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 142, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 143, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 144, "DEV_AASRC0_RX3_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 145, "DEV_AASRC0_RX3_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 146, "DEV_AASRC0_RX3_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 147, "DEV_AASRC0_RX3_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 148, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 149, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"}, {139, 150, "DEV_AASRC0_TX0_SYNC", "Input muxed clock"}, {139, 151, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 152, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 153, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 154, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 155, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 156, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 157, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 158, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 159, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 160, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 161, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 162, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 163, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 164, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 165, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 166, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 167, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 168, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 169, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 170, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 171, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 172, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 173, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 174, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 175, "DEV_AASRC0_TX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 176, "DEV_AASRC0_TX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 177, "DEV_AASRC0_TX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 178, "DEV_AASRC0_TX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 179, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 180, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 181, "DEV_AASRC0_TX0_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 182, "DEV_AASRC0_TX0_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 183, "DEV_AASRC0_TX0_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 184, "DEV_AASRC0_TX0_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 185, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 186, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"}, {139, 187, "DEV_AASRC0_TX1_SYNC", "Input muxed clock"}, {139, 188, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 189, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 190, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 191, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 192, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 193, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 194, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 195, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 196, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 197, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 198, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 199, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 200, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 201, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 202, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 203, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 204, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 205, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 206, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 207, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 208, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 209, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 210, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 211, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 212, "DEV_AASRC0_TX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 213, "DEV_AASRC0_TX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 214, "DEV_AASRC0_TX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 215, "DEV_AASRC0_TX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 216, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 217, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 218, "DEV_AASRC0_TX1_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 219, "DEV_AASRC0_TX1_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 220, "DEV_AASRC0_TX1_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 221, "DEV_AASRC0_TX1_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 222, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 223, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"}, {139, 224, "DEV_AASRC0_TX2_SYNC", "Input muxed clock"}, {139, 225, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 226, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 227, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 228, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 229, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 230, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 231, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 232, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 233, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 234, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 235, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 236, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 237, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 238, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 239, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 240, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 241, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 242, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 243, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 244, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 245, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 246, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 247, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 248, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 249, "DEV_AASRC0_TX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 250, "DEV_AASRC0_TX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 251, "DEV_AASRC0_TX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 252, "DEV_AASRC0_TX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 253, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 254, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 255, "DEV_AASRC0_TX2_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 256, "DEV_AASRC0_TX2_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 257, "DEV_AASRC0_TX2_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 258, "DEV_AASRC0_TX2_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 259, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 260, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"}, {139, 261, "DEV_AASRC0_TX3_SYNC", "Input muxed clock"}, {139, 262, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 263, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 264, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 265, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 266, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 267, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 268, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 269, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 270, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 271, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 272, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 273, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 274, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 275, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 276, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 277, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 278, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 279, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 280, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 281, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 282, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 283, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 284, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 285, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 286, "DEV_AASRC0_TX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 287, "DEV_AASRC0_TX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 288, "DEV_AASRC0_TX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 289, "DEV_AASRC0_TX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 290, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 291, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 292, "DEV_AASRC0_TX3_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 293, "DEV_AASRC0_TX3_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 294, "DEV_AASRC0_TX3_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 295, "DEV_AASRC0_TX3_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 296, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {139, 297, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"}, {337, 0, "DEV_ASCPCIE_BUFFER0_CLKIN0", "Input muxed clock"}, {337, 1, "DEV_ASCPCIE_BUFFER0_CLKIN0_PARENT_WIZ16B4M4CS_MAIN_0_REF_DER_OUT_CLK", "Parent input clock option to DEV_ASCPCIE_BUFFER0_CLKIN0"}, {337, 2, "DEV_ASCPCIE_BUFFER0_CLKIN0_PARENT_WIZ16B4M4CS_MAIN_1_REF_DER_OUT_CLK", "Parent input clock option to DEV_ASCPCIE_BUFFER0_CLKIN0"}, {337, 3, "DEV_ASCPCIE_BUFFER0_CLKIN0_PARENT_WIZ16B4M4CS_MAIN_0_REF1_OUT_CLK", "Parent input clock option to DEV_ASCPCIE_BUFFER0_CLKIN0"}, {337, 4, "DEV_ASCPCIE_BUFFER0_CLKIN0_PARENT_WIZ16B4M4CS_MAIN_1_REF1_OUT_CLK", "Parent input clock option to DEV_ASCPCIE_BUFFER0_CLKIN0"}, {337, 5, "DEV_ASCPCIE_BUFFER0_CLKIN1", "Input muxed clock"}, {337, 6, "DEV_ASCPCIE_BUFFER0_CLKIN1_PARENT_WIZ16B4M4CS_MAIN_0_REF_DER_OUT_CLK", "Parent input clock option to DEV_ASCPCIE_BUFFER0_CLKIN1"}, {337, 7, "DEV_ASCPCIE_BUFFER0_CLKIN1_PARENT_WIZ16B4M4CS_MAIN_1_REF_DER_OUT_CLK", "Parent input clock option to DEV_ASCPCIE_BUFFER0_CLKIN1"}, {337, 8, "DEV_ASCPCIE_BUFFER0_CLKIN1_PARENT_WIZ16B4M4CS_MAIN_0_REF1_OUT_CLK", "Parent input clock option to DEV_ASCPCIE_BUFFER0_CLKIN1"}, {337, 9, "DEV_ASCPCIE_BUFFER0_CLKIN1_PARENT_WIZ16B4M4CS_MAIN_1_REF1_OUT_CLK", "Parent input clock option to DEV_ASCPCIE_BUFFER0_CLKIN1"}, {337, 10, "DEV_ASCPCIE_BUFFER0_CLKOUT0_N", "Output clock"}, {337, 11, "DEV_ASCPCIE_BUFFER0_CLKOUT0_P", "Output clock"}, {337, 12, "DEV_ASCPCIE_BUFFER0_CLKOUT1_N", "Output clock"}, {337, 13, "DEV_ASCPCIE_BUFFER0_CLKOUT1_P", "Output clock"}, {338, 0, "DEV_ASCPCIE_BUFFER1_CLKIN0", "Input muxed clock"}, {338, 1, "DEV_ASCPCIE_BUFFER1_CLKIN0_PARENT_WIZ16B4M4CS_MAIN_2_REF_DER_OUT_CLK", "Parent input clock option to DEV_ASCPCIE_BUFFER1_CLKIN0"}, {338, 2, "DEV_ASCPCIE_BUFFER1_CLKIN0_PARENT_WIZ16B4M4CS_MAIN_3_REF_DER_OUT_CLK", "Parent input clock option to DEV_ASCPCIE_BUFFER1_CLKIN0"}, {338, 3, "DEV_ASCPCIE_BUFFER1_CLKIN0_PARENT_WIZ16B4M4CS_MAIN_2_REF1_OUT_CLK", "Parent input clock option to DEV_ASCPCIE_BUFFER1_CLKIN0"}, {338, 4, "DEV_ASCPCIE_BUFFER1_CLKIN0_PARENT_WIZ16B4M4CS_MAIN_3_REF1_OUT_CLK", "Parent input clock option to DEV_ASCPCIE_BUFFER1_CLKIN0"}, {338, 5, "DEV_ASCPCIE_BUFFER1_CLKIN1", "Input muxed clock"}, {338, 6, "DEV_ASCPCIE_BUFFER1_CLKIN1_PARENT_WIZ16B4M4CS_MAIN_2_REF_DER_OUT_CLK", "Parent input clock option to DEV_ASCPCIE_BUFFER1_CLKIN1"}, {338, 7, "DEV_ASCPCIE_BUFFER1_CLKIN1_PARENT_WIZ16B4M4CS_MAIN_3_REF_DER_OUT_CLK", "Parent input clock option to DEV_ASCPCIE_BUFFER1_CLKIN1"}, {338, 8, "DEV_ASCPCIE_BUFFER1_CLKIN1_PARENT_WIZ16B4M4CS_MAIN_2_REF1_OUT_CLK", "Parent input clock option to DEV_ASCPCIE_BUFFER1_CLKIN1"}, {338, 9, "DEV_ASCPCIE_BUFFER1_CLKIN1_PARENT_WIZ16B4M4CS_MAIN_3_REF1_OUT_CLK", "Parent input clock option to DEV_ASCPCIE_BUFFER1_CLKIN1"}, {338, 10, "DEV_ASCPCIE_BUFFER1_CLKOUT0_N", "Output clock"}, {338, 11, "DEV_ASCPCIE_BUFFER1_CLKOUT0_P", "Output clock"}, {338, 12, "DEV_ASCPCIE_BUFFER1_CLKOUT1_N", "Output clock"}, {338, 13, "DEV_ASCPCIE_BUFFER1_CLKOUT1_P", "Output clock"}, {2, 0, "DEV_ATL0_VBUS_CLK", "Input clock"}, {2, 1, "DEV_ATL0_ATL_CLK", "Input muxed clock"}, {2, 2, "DEV_ATL0_ATL_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT1_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"}, {2, 3, "DEV_ATL0_ATL_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"}, {2, 4, "DEV_ATL0_ATL_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT1_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"}, {2, 5, "DEV_ATL0_ATL_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"}, {2, 6, "DEV_ATL0_ATL_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_CLK"}, {2, 7, "DEV_ATL0_ATL_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_CLK"}, {2, 8, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_1", "Output clock"}, {2, 9, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT", "Output clock"}, {2, 10, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_3", "Output clock"}, {2, 11, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_2", "Output clock"}, {157, 0, "DEV_BOARD0_SPI0_CLK_IN", "Input clock"}, {157, 2, "DEV_BOARD0_SPI1_CLK_IN", "Input clock"}, {157, 4, "DEV_BOARD0_SPI2_CLK_IN", "Input clock"}, {157, 6, "DEV_BOARD0_SPI3_CLK_IN", "Input clock"}, {157, 8, "DEV_BOARD0_SPI5_CLK_IN", "Input clock"}, {157, 10, "DEV_BOARD0_SPI6_CLK_IN", "Input clock"}, {157, 12, "DEV_BOARD0_SPI7_CLK_IN", "Input clock"}, {157, 14, "DEV_BOARD0_MCU_SPI0_CLK_IN", "Input clock"}, {157, 16, "DEV_BOARD0_MCU_SPI1_CLK_IN", "Input clock"}, {157, 18, "DEV_BOARD0_MCU_OSPI0_CLK_IN", "Input clock"}, {157, 19, "DEV_BOARD0_MCU_OSPI0_LBCLKO_IN", "Input clock"}, {157, 20, "DEV_BOARD0_MCU_OSPI0_DQS_OUT", "Output clock"}, {157, 21, "DEV_BOARD0_MCU_OSPI1_CLK_IN", "Input clock"}, {157, 22, "DEV_BOARD0_MCU_OSPI1_LBCLKO_IN", "Input clock"}, {157, 23, "DEV_BOARD0_MCU_OSPI1_DQS_OUT", "Output clock"}, {157, 25, "DEV_BOARD0_I2C0_SCL_OUT", "Output clock"}, {157, 27, "DEV_BOARD0_I2C1_SCL_OUT", "Output clock"}, {157, 29, "DEV_BOARD0_I2C2_SCL_OUT", "Output clock"}, {157, 31, "DEV_BOARD0_I2C3_SCL_OUT", "Output clock"}, {157, 33, "DEV_BOARD0_I2C4_SCL_OUT", "Output clock"}, {157, 35, "DEV_BOARD0_I2C5_SCL_OUT", "Output clock"}, {157, 37, "DEV_BOARD0_I2C6_SCL_OUT", "Output clock"}, {157, 38, "DEV_BOARD0_MCU_I2C0_SCL_IN", "Input clock"}, {157, 39, "DEV_BOARD0_MCU_I2C0_SCL_OUT", "Output clock"}, {157, 41, "DEV_BOARD0_MCU_I2C1_SCL_OUT", "Output clock"}, {157, 42, "DEV_BOARD0_WKUP_I2C0_SCL_IN", "Input clock"}, {157, 43, "DEV_BOARD0_WKUP_I2C0_SCL_OUT", "Output clock"}, {157, 44, "DEV_BOARD0_I3C0_SCL_IN", "Input clock"}, {157, 45, "DEV_BOARD0_I3C0_SCL_OUT", "Output clock"}, {157, 46, "DEV_BOARD0_MCU_I3C0_SCL_IN", "Input clock"}, {157, 47, "DEV_BOARD0_MCU_I3C0_SCL_OUT", "Output clock"}, {157, 48, "DEV_BOARD0_MCU_I3C1_SCL_IN", "Input clock"}, {157, 49, "DEV_BOARD0_MCU_I3C1_SCL_OUT", "Output clock"}, {157, 50, "DEV_BOARD0_MCU_HYPERBUS0_CK_IN", "Input clock"}, {157, 51, "DEV_BOARD0_MCU_HYPERBUS0_CKN_IN", "Input clock"}, {157, 52, "DEV_BOARD0_DSI_TXCLKP_IN", "Input clock"}, {157, 53, "DEV_BOARD0_DSI_TXCLKN_IN", "Input clock"}, {157, 54, "DEV_BOARD0_PRG0_MDIO0_MDC_IN", "Input clock"}, {157, 55, "DEV_BOARD0_PRG0_RGMII1_TXC_IN", "Input clock"}, {157, 56, "DEV_BOARD0_PRG0_RGMII1_TXC_OUT", "Output clock"}, {157, 57, "DEV_BOARD0_PRG0_RGMII1_RXC_OUT", "Output clock"}, {157, 58, "DEV_BOARD0_PRG0_RGMII2_TXC_IN", "Input clock"}, {157, 59, "DEV_BOARD0_PRG0_RGMII2_TXC_OUT", "Output clock"}, {157, 60, "DEV_BOARD0_PRG0_RGMII2_RXC_OUT", "Output clock"}, {157, 61, "DEV_BOARD0_PRG1_MDIO0_MDC_IN", "Input clock"}, {157, 62, "DEV_BOARD0_PRG1_RGMII1_TXC_IN", "Input clock"}, {157, 63, "DEV_BOARD0_PRG1_RGMII1_TXC_OUT", "Output clock"}, {157, 64, "DEV_BOARD0_PRG1_RGMII1_RXC_OUT", "Output clock"}, {157, 65, "DEV_BOARD0_PRG1_RGMII2_TXC_IN", "Input clock"}, {157, 66, "DEV_BOARD0_PRG1_RGMII2_TXC_OUT", "Output clock"}, {157, 67, "DEV_BOARD0_PRG1_RGMII2_RXC_OUT", "Output clock"}, {157, 68, "DEV_BOARD0_MDIO0_MDC_IN", "Input clock"}, {157, 70, "DEV_BOARD0_RGMII3_RXC_OUT", "Output clock"}, {157, 72, "DEV_BOARD0_RGMII4_RXC_OUT", "Output clock"}, {157, 74, "DEV_BOARD0_RGMII5_RXC_OUT", "Output clock"}, {157, 76, "DEV_BOARD0_RGMII6_RXC_OUT", "Output clock"}, {157, 78, "DEV_BOARD0_RGMII7_RXC_OUT", "Output clock"}, {157, 80, "DEV_BOARD0_RGMII8_RXC_OUT", "Output clock"}, {157, 81, "DEV_BOARD0_RMII_REF_CLK_OUT", "Output clock"}, {157, 82, "DEV_BOARD0_CPTS0_RFT_CLK_OUT", "Output clock"}, {157, 83, "DEV_BOARD0_MCU_MDIO0_MDC_IN", "Input clock"}, {157, 84, "DEV_BOARD0_MCU_RGMII1_TXC_IN", "Input clock"}, {157, 85, "DEV_BOARD0_MCU_RGMII1_TXC_OUT", "Output clock"}, {157, 86, "DEV_BOARD0_MCU_RGMII1_RXC_OUT", "Output clock"}, {157, 87, "DEV_BOARD0_MCU_RMII1_REF_CLK_OUT", "Output clock"}, {157, 88, "DEV_BOARD0_MCU_CPTS0_RFT_CLK_OUT", "Output clock"}, {157, 89, "DEV_BOARD0_UFS0_REF_CLK_IN", "Input clock"}, {157, 91, "DEV_BOARD0_DDR0_CK0_IN", "Input clock"}, {157, 92, "DEV_BOARD0_DDR0_CK0_N_IN", "Input clock"}, {157, 99, "DEV_BOARD0_MMC0_CLK_IN", "Input clock"}, {157, 100, "DEV_BOARD0_MMC1_CLK_IN", "Input clock"}, {157, 101, "DEV_BOARD0_MMC2_CLK_IN", "Input clock"}, {157, 102, "DEV_BOARD0_GPMC0_CLK_IN", "Input clock"}, {157, 103, "DEV_BOARD0_GPMC0_CLK_OUT", "Output clock"}, {157, 104, "DEV_BOARD0_GPMC0_FCLK_MUX_IN", "Input clock"}, {157, 105, "DEV_BOARD0_MLB0_MLBCLK_OUT", "Output clock"}, {157, 106, "DEV_BOARD0_MLB0_MLBCP_OUT", "Output clock"}, {157, 108, "DEV_BOARD0_VPFE0_PCLK_OUT", "Output clock"}, {157, 109, "DEV_BOARD0_VOUT1_PCLK_IN", "Input clock"}, {157, 110, "DEV_BOARD0_VOUT1_EXTPCLKIN_OUT", "Output clock"}, {157, 111, "DEV_BOARD0_VOUT2_PCLK_IN", "Input clock"}, {157, 112, "DEV_BOARD0_VOUT2_EXTPCLKIN_OUT", "Output clock"}, {157, 113, "DEV_BOARD0_OBSCLK0_IN", "Input clock"}, {157, 114, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 115, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 116, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 117, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 118, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 119, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_5_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 120, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_6_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 126, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 127, "DEV_BOARD0_OBSCLK0_IN_PARENT_OBSCLK1_MUX_OUT0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 128, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 129, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 130, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 131, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 132, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 133, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 137, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_23_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 138, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_24_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 139, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 140, "DEV_BOARD0_OBSCLK0_IN_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 141, "DEV_BOARD0_OBSCLK0_IN_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 142, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 143, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 144, "DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 145, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 146, "DEV_BOARD0_OBSCLK1_IN", "Input muxed clock"}, {157, 147, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_7_HSDIVOUT0_CLK4", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 148, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_8_HSDIVOUT0_CLK8", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 149, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV3_16FFT_MAIN_13_HSDIVOUT0_CLK4", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 152, "DEV_BOARD0_MCU_OBSCLK0_IN", "Input muxed clock"}, {157, 153, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"}, {157, 154, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"}, {157, 169, "DEV_BOARD0_SYSCLKOUT0_IN", "Input clock"}, {157, 170, "DEV_BOARD0_MCU_SYSCLKOUT0_IN", "Input clock"}, {157, 171, "DEV_BOARD0_TRC_CLK_IN", "Input clock"}, {157, 172, "DEV_BOARD0_CLKOUT_IN", "Input muxed clock"}, {157, 173, "DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK5", "Parent input clock option to DEV_BOARD0_CLKOUT_IN"}, {157, 174, "DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK10", "Parent input clock option to DEV_BOARD0_CLKOUT_IN"}, {157, 175, "DEV_BOARD0_MCU_CLKOUT0_IN", "Input muxed clock"}, {157, 176, "DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK5", "Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN"}, {157, 177, "DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK10", "Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN"}, {157, 178, "DEV_BOARD0_LED_CLK_OUT", "Output clock"}, {157, 179, "DEV_BOARD0_EXT_REFCLK1_OUT", "Output clock"}, {157, 180, "DEV_BOARD0_MCU_EXT_REFCLK0_OUT", "Output clock"}, {157, 181, "DEV_BOARD0_HFOSC1_CLK_OUT", "Output clock"}, {157, 182, "DEV_BOARD0_TCK_OUT", "Output clock"}, {157, 183, "DEV_BOARD0_PCIE_REFCLK0P_IN", "Input clock"}, {157, 184, "DEV_BOARD0_PCIE_REFCLK0N_IN", "Input clock"}, {157, 185, "DEV_BOARD0_PCIE_REFCLK0P_OUT", "Output clock"}, {157, 186, "DEV_BOARD0_PCIE_REFCLK0N_OUT", "Output clock"}, {157, 187, "DEV_BOARD0_PCIE_REFCLK0P_OUT_IN", "Input clock"}, {157, 188, "DEV_BOARD0_PCIE_REFCLK0N_OUT_IN", "Input clock"}, {157, 189, "DEV_BOARD0_PCIE_REFCLK1P_IN", "Input clock"}, {157, 190, "DEV_BOARD0_PCIE_REFCLK1N_IN", "Input clock"}, {157, 191, "DEV_BOARD0_PCIE_REFCLK1P_OUT", "Output clock"}, {157, 192, "DEV_BOARD0_PCIE_REFCLK1N_OUT", "Output clock"}, {157, 193, "DEV_BOARD0_PCIE_REFCLK1P_OUT_IN", "Input clock"}, {157, 194, "DEV_BOARD0_PCIE_REFCLK1N_OUT_IN", "Input clock"}, {157, 195, "DEV_BOARD0_PCIE_REFCLK2P_IN", "Input clock"}, {157, 196, "DEV_BOARD0_PCIE_REFCLK2N_IN", "Input clock"}, {157, 197, "DEV_BOARD0_PCIE_REFCLK2P_OUT", "Output clock"}, {157, 198, "DEV_BOARD0_PCIE_REFCLK2N_OUT", "Output clock"}, {157, 201, "DEV_BOARD0_PCIE_REFCLK3P_OUT", "Output clock"}, {157, 202, "DEV_BOARD0_PCIE_REFCLK3N_OUT", "Output clock"}, {157, 203, "DEV_BOARD0_PCIE_REFCLK3P_IN", "Input clock"}, {157, 204, "DEV_BOARD0_PCIE_REFCLK3N_IN", "Input clock"}, {157, 217, "DEV_BOARD0_MCASP0_ACLKR_IN", "Input clock"}, {157, 218, "DEV_BOARD0_MCASP0_ACLKR_OUT", "Output clock"}, {157, 219, "DEV_BOARD0_MCASP0_AFSR_OUT", "Output clock"}, {157, 220, "DEV_BOARD0_MCASP0_ACLKX_IN", "Input clock"}, {157, 221, "DEV_BOARD0_MCASP0_ACLKX_OUT", "Output clock"}, {157, 222, "DEV_BOARD0_MCASP0_AFSX_OUT", "Output clock"}, {157, 223, "DEV_BOARD0_MCASP1_ACLKR_IN", "Input clock"}, {157, 224, "DEV_BOARD0_MCASP1_ACLKR_OUT", "Output clock"}, {157, 225, "DEV_BOARD0_MCASP1_AFSR_OUT", "Output clock"}, {157, 226, "DEV_BOARD0_MCASP1_ACLKX_IN", "Input clock"}, {157, 227, "DEV_BOARD0_MCASP1_ACLKX_OUT", "Output clock"}, {157, 228, "DEV_BOARD0_MCASP1_AFSX_OUT", "Output clock"}, {157, 229, "DEV_BOARD0_MCASP2_ACLKR_IN", "Input clock"}, {157, 230, "DEV_BOARD0_MCASP2_ACLKR_OUT", "Output clock"}, {157, 231, "DEV_BOARD0_MCASP2_AFSR_OUT", "Output clock"}, {157, 232, "DEV_BOARD0_MCASP2_ACLKX_IN", "Input clock"}, {157, 233, "DEV_BOARD0_MCASP2_ACLKX_OUT", "Output clock"}, {157, 234, "DEV_BOARD0_MCASP2_AFSX_OUT", "Output clock"}, {157, 235, "DEV_BOARD0_MCASP3_ACLKR_IN", "Input clock"}, {157, 236, "DEV_BOARD0_MCASP3_ACLKR_OUT", "Output clock"}, {157, 237, "DEV_BOARD0_MCASP3_AFSR_OUT", "Output clock"}, {157, 238, "DEV_BOARD0_MCASP3_ACLKX_IN", "Input clock"}, {157, 239, "DEV_BOARD0_MCASP3_ACLKX_OUT", "Output clock"}, {157, 240, "DEV_BOARD0_MCASP3_AFSX_OUT", "Output clock"}, {157, 241, "DEV_BOARD0_MCASP4_ACLKR_IN", "Input clock"}, {157, 242, "DEV_BOARD0_MCASP4_ACLKR_OUT", "Output clock"}, {157, 243, "DEV_BOARD0_MCASP4_AFSR_OUT", "Output clock"}, {157, 244, "DEV_BOARD0_MCASP4_ACLKX_IN", "Input clock"}, {157, 245, "DEV_BOARD0_MCASP4_ACLKX_OUT", "Output clock"}, {157, 246, "DEV_BOARD0_MCASP4_AFSX_OUT", "Output clock"}, {157, 247, "DEV_BOARD0_MCASP5_ACLKR_IN", "Input clock"}, {157, 248, "DEV_BOARD0_MCASP5_ACLKR_OUT", "Output clock"}, {157, 249, "DEV_BOARD0_MCASP5_AFSR_OUT", "Output clock"}, {157, 250, "DEV_BOARD0_MCASP5_ACLKX_IN", "Input clock"}, {157, 251, "DEV_BOARD0_MCASP5_ACLKX_OUT", "Output clock"}, {157, 252, "DEV_BOARD0_MCASP5_AFSX_OUT", "Output clock"}, {157, 253, "DEV_BOARD0_MCASP6_ACLKR_IN", "Input clock"}, {157, 254, "DEV_BOARD0_MCASP6_ACLKR_OUT", "Output clock"}, {157, 255, "DEV_BOARD0_MCASP6_AFSR_OUT", "Output clock"}, {157, 256, "DEV_BOARD0_MCASP6_ACLKX_IN", "Input clock"}, {157, 257, "DEV_BOARD0_MCASP6_ACLKX_OUT", "Output clock"}, {157, 258, "DEV_BOARD0_MCASP6_AFSX_OUT", "Output clock"}, {157, 259, "DEV_BOARD0_MCASP7_ACLKR_IN", "Input clock"}, {157, 260, "DEV_BOARD0_MCASP7_ACLKR_OUT", "Output clock"}, {157, 261, "DEV_BOARD0_MCASP7_AFSR_OUT", "Output clock"}, {157, 262, "DEV_BOARD0_MCASP7_ACLKX_IN", "Input clock"}, {157, 263, "DEV_BOARD0_MCASP7_ACLKX_OUT", "Output clock"}, {157, 264, "DEV_BOARD0_MCASP7_AFSX_OUT", "Output clock"}, {157, 265, "DEV_BOARD0_MCASP8_ACLKR_IN", "Input clock"}, {157, 267, "DEV_BOARD0_MCASP8_ACLKR_OUT", "Output clock"}, {157, 268, "DEV_BOARD0_MCASP8_AFSR_OUT", "Output clock"}, {157, 269, "DEV_BOARD0_MCASP8_ACLKX_IN", "Input clock"}, {157, 270, "DEV_BOARD0_MCASP8_ACLKX_OUT", "Output clock"}, {157, 271, "DEV_BOARD0_MCASP8_AFSX_OUT", "Output clock"}, {157, 272, "DEV_BOARD0_MCASP9_ACLKR_IN", "Input clock"}, {157, 273, "DEV_BOARD0_MCASP9_ACLKR_OUT", "Output clock"}, {157, 274, "DEV_BOARD0_MCASP9_AFSR_OUT", "Output clock"}, {157, 275, "DEV_BOARD0_MCASP9_ACLKX_IN", "Input clock"}, {157, 276, "DEV_BOARD0_MCASP9_ACLKX_OUT", "Output clock"}, {157, 278, "DEV_BOARD0_MCASP9_AFSX_OUT", "Output clock"}, {157, 279, "DEV_BOARD0_MCASP10_ACLKR_IN", "Input clock"}, {157, 280, "DEV_BOARD0_MCASP10_ACLKR_OUT", "Output clock"}, {157, 281, "DEV_BOARD0_MCASP10_AFSR_OUT", "Output clock"}, {157, 282, "DEV_BOARD0_MCASP10_ACLKX_IN", "Input clock"}, {157, 283, "DEV_BOARD0_MCASP10_ACLKX_OUT", "Output clock"}, {157, 284, "DEV_BOARD0_MCASP10_AFSX_OUT", "Output clock"}, {157, 285, "DEV_BOARD0_MCASP11_ACLKR_IN", "Input clock"}, {157, 286, "DEV_BOARD0_MCASP11_ACLKR_OUT", "Output clock"}, {157, 287, "DEV_BOARD0_MCASP11_AFSR_OUT", "Output clock"}, {157, 288, "DEV_BOARD0_MCASP11_ACLKX_IN", "Input clock"}, {157, 289, "DEV_BOARD0_MCASP11_ACLKX_OUT", "Output clock"}, {157, 290, "DEV_BOARD0_MCASP11_AFSX_OUT", "Output clock"}, {157, 300, "DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT", "Output clock"}, {157, 301, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN", "Input muxed clock"}, {157, 302, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 303, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 304, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 305, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 306, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 307, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 308, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 309, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 310, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 311, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 312, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 313, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 314, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 315, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 316, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 317, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 318, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 319, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 320, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 321, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 322, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 323, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 324, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 325, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 326, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 327, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 328, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 329, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 330, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 331, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 334, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 335, "DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT", "Output clock"}, {157, 336, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN", "Input muxed clock"}, {157, 337, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 338, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 339, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 340, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 341, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 342, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 343, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 344, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 345, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 346, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 347, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 348, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 349, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 350, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 351, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 352, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 353, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 354, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 355, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 356, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 357, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 358, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 359, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 360, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 361, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 362, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 363, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 364, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 365, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 366, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 369, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 370, "DEV_BOARD0_AUDIO_EXT_REFCLK2_OUT", "Output clock"}, {157, 371, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN", "Input muxed clock"}, {157, 372, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, {157, 373, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, {157, 374, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, {157, 375, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, {157, 376, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, {157, 377, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, {157, 378, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, {157, 379, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, {157, 380, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, {157, 381, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, {157, 382, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, {157, 383, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, {157, 384, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, {157, 385, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, {157, 386, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, {157, 387, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, {157, 388, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, {157, 389, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, {157, 390, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, {157, 391, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, {157, 392, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, {157, 393, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, {157, 394, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, {157, 395, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, {157, 396, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, {157, 397, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, {157, 398, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, {157, 399, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, {157, 400, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, {157, 401, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, {157, 404, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"}, {157, 405, "DEV_BOARD0_AUDIO_EXT_REFCLK3_OUT", "Output clock"}, {157, 406, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN", "Input muxed clock"}, {157, 407, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, {157, 408, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, {157, 409, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, {157, 410, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, {157, 411, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, {157, 412, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, {157, 413, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, {157, 414, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, {157, 415, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, {157, 416, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, {157, 417, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, {157, 418, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, {157, 419, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, {157, 420, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, {157, 421, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, {157, 422, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, {157, 423, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, {157, 424, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, {157, 425, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, {157, 426, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, {157, 427, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, {157, 428, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, {157, 429, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, {157, 430, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, {157, 431, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, {157, 432, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, {157, 433, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, {157, 434, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, {157, 435, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, {157, 436, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, {157, 439, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK3_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"}, {142, 0, "DEV_C66SS0_CORE0_GEM_TRC_CLK", "Input clock"}, {142, 1, "DEV_C66SS0_CORE0_GEM_CLK2_OUT_CLK", "Output clock"}, {142, 4, "DEV_C66SS0_CORE0_GEM_PBIST_ROM_CLK", "Output clock"}, {142, 6, "DEV_C66SS0_CORE0_GEM_CLKIN_CLK", "Input clock"}, {121, 0, "DEV_C66SS0_INTROUTER0_INTR_CLK", "Input clock"}, {143, 0, "DEV_C66SS1_CORE0_GEM_TRC_CLK", "Input clock"}, {143, 1, "DEV_C66SS1_CORE0_GEM_CLK2_OUT_CLK", "Output clock"}, {143, 4, "DEV_C66SS1_CORE0_GEM_PBIST_ROM_CLK", "Output clock"}, {143, 6, "DEV_C66SS1_CORE0_GEM_CLKIN_CLK", "Input clock"}, {122, 0, "DEV_C66SS1_INTROUTER0_INTR_CLK", "Input clock"}, {15, 0, "DEV_C71SS0_C7X_CLK", "Input clock"}, {15, 1, "DEV_C71SS0_PLL_CTRL_CLK", "Input clock"}, {16, 0, "DEV_C71SS0_MMA_PLL_CTRL_CLK", "Input clock"}, {16, 1, "DEV_C71SS0_MMA_MMA_CLK", "Input clock"}, {123, 0, "DEV_CMPEVENT_INTRTR0_INTR_CLK", "Input clock"}, {5, 0, "DEV_COMPUTE_CLUSTER0_CFG_WRAP_CLK4_CLK", "Input clock"}, {6, 0, "DEV_COMPUTE_CLUSTER0_CLEC_CLK4_CLK", "Input clock"}, {6, 1, "DEV_COMPUTE_CLUSTER0_CLEC_CLK1_CLK", "Input clock"}, {7, 0, "DEV_COMPUTE_CLUSTER0_CORE_CORE_PSIL_LEAF_CLK", "Input clock"}, {7, 1, "DEV_COMPUTE_CLUSTER0_CORE_CORE_CLK1_CLK", "Input clock"}, {8, 0, "DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW_PLL_CTRL_CLK", "Input clock"}, {8, 1, "DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW_DDRSS_DDR_PLL_CLK", "Input clock"}, {9, 0, "DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_CLK1_CLK_CLK", "Input clock"}, {9, 1, "DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_CLK2_CLK_CLK", "Input clock"}, {12, 0, "DEV_COMPUTE_CLUSTER0_DMSC_WRAP_CLK4_CLK_CLK", "Input clock"}, {13, 0, "DEV_COMPUTE_CLUSTER0_EN_MSMC_DOMAIN_MSMC_CLK1_CLK", "Input clock"}, {14, 0, "DEV_COMPUTE_CLUSTER0_GIC500SS_VCLK_CLK", "Input clock"}, {17, 0, "DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVP_CLK1_CLK_CLK", "Input clock"}, {17, 1, "DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVH_CLK4_CLK_CLK", "Input clock"}, {17, 2, "DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVH_CLK2_CLK_CLK", "Input clock"}, {19, 0, "DEV_CPSW0_GMII3_MT_CLK", "Input clock"}, {19, 1, "DEV_CPSW0_SERDES6_TXFCLK", "Input clock"}, {19, 2, "DEV_CPSW0_SERDES8_TXMCLK", "Input clock"}, {19, 3, "DEV_CPSW0_GMII2_MR_CLK", "Input clock"}, {19, 4, "DEV_CPSW0_SERDES2_TXFCLK", "Input clock"}, {19, 5, "DEV_CPSW0_SERDES4_RXCLK", "Input clock"}, {19, 6, "DEV_CPSW0_SERDES7_TXMCLK", "Input clock"}, {19, 7, "DEV_CPSW0_SERDES7_RXCLK", "Input clock"}, {19, 8, "DEV_CPSW0_SERDES6_REFCLK", "Input clock"}, {19, 9, "DEV_CPSW0_SERDES5_TXFCLK", "Input clock"}, {19, 10, "DEV_CPSW0_SERDES5_RXCLK", "Input clock"}, {19, 11, "DEV_CPSW0_GMII4_MT_CLK", "Input clock"}, {19, 12, "DEV_CPSW0_SERDES3_TXFCLK", "Input clock"}, {19, 13, "DEV_CPSW0_SERDES2_REFCLK", "Input clock"}, {19, 14, "DEV_CPSW0_SERDES4_RXFCLK", "Input clock"}, {19, 15, "DEV_CPSW0_SERDES6_RXFCLK", "Input clock"}, {19, 16, "DEV_CPSW0_CPTS_RFT_CLK", "Input muxed clock"}, {19, 17, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {19, 18, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {19, 19, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {19, 20, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {19, 21, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {19, 22, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {19, 23, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {19, 24, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {19, 25, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {19, 26, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {19, 27, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {19, 28, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {19, 29, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {19, 30, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {19, 31, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {19, 32, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {19, 33, "DEV_CPSW0_SERDES5_RXFCLK", "Input clock"}, {19, 34, "DEV_CPSW0_SERDES5_TXMCLK", "Input clock"}, {19, 35, "DEV_CPSW0_GMII5_MT_CLK", "Input clock"}, {19, 36, "DEV_CPSW0_SERDES2_RXCLK", "Input clock"}, {19, 37, "DEV_CPSW0_SERDES8_RXFCLK", "Input clock"}, {19, 38, "DEV_CPSW0_SERDES1_RXFCLK", "Input clock"}, {19, 39, "DEV_CPSW0_SERDES8_RXCLK", "Input clock"}, {19, 40, "DEV_CPSW0_GMII_RFT_CLK", "Input clock"}, {19, 41, "DEV_CPSW0_SERDES3_REFCLK", "Input clock"}, {19, 42, "DEV_CPSW0_RGMII_MHZ_250_CLK", "Input clock"}, {19, 43, "DEV_CPSW0_SERDES7_REFCLK", "Input clock"}, {19, 44, "DEV_CPSW0_GMII6_MT_CLK", "Input clock"}, {19, 45, "DEV_CPSW0_SERDES6_TXMCLK", "Input clock"}, {19, 46, "DEV_CPSW0_RMII_MHZ_50_CLK", "Input clock"}, {19, 47, "DEV_CPSW0_GMII4_MR_CLK", "Input clock"}, {19, 48, "DEV_CPSW0_SERDES2_TXMCLK", "Input clock"}, {19, 49, "DEV_CPSW0_RGMII_MHZ_50_CLK", "Input clock"}, {19, 50, "DEV_CPSW0_SERDES4_TXMCLK", "Input clock"}, {19, 51, "DEV_CPSW0_SERDES3_RXFCLK", "Input clock"}, {19, 52, "DEV_CPSW0_GMII8_MT_CLK", "Input clock"}, {19, 53, "DEV_CPSW0_SERDES7_TXFCLK", "Input clock"}, {19, 54, "DEV_CPSW0_GMII7_MT_CLK", "Input clock"}, {19, 55, "DEV_CPSW0_GMII7_MR_CLK", "Input clock"}, {19, 56, "DEV_CPSW0_SERDES6_RXCLK", "Input clock"}, {19, 57, "DEV_CPSW0_SERDES3_RXCLK", "Input clock"}, {19, 58, "DEV_CPSW0_SERDES4_REFCLK", "Input clock"}, {19, 59, "DEV_CPSW0_SERDES1_RXCLK", "Input clock"}, {19, 60, "DEV_CPSW0_SERDES1_TXFCLK", "Input clock"}, {19, 61, "DEV_CPSW0_GMII6_MR_CLK", "Input clock"}, {19, 62, "DEV_CPSW0_SERDES1_REFCLK", "Input clock"}, {19, 63, "DEV_CPSW0_RGMII_MHZ_5_CLK", "Input clock"}, {19, 64, "DEV_CPSW0_SERDES5_REFCLK", "Input clock"}, {19, 65, "DEV_CPSW0_GMII2_MT_CLK", "Input clock"}, {19, 66, "DEV_CPSW0_SERDES8_TXFCLK", "Input clock"}, {19, 67, "DEV_CPSW0_GMII8_MR_CLK", "Input clock"}, {19, 68, "DEV_CPSW0_GMII1_MR_CLK", "Input clock"}, {19, 69, "DEV_CPSW0_SERDES8_REFCLK", "Input clock"}, {19, 70, "DEV_CPSW0_SERDES3_TXMCLK", "Input clock"}, {19, 71, "DEV_CPSW0_GMII3_MR_CLK", "Input clock"}, {19, 72, "DEV_CPSW0_SERDES1_TXMCLK", "Input clock"}, {19, 73, "DEV_CPSW0_SERDES7_RXFCLK", "Input clock"}, {19, 74, "DEV_CPSW0_GMII5_MR_CLK", "Input clock"}, {19, 75, "DEV_CPSW0_GMII1_MT_CLK", "Input clock"}, {19, 76, "DEV_CPSW0_SERDES2_RXFCLK", "Input clock"}, {19, 77, "DEV_CPSW0_SERDES4_TXFCLK", "Input clock"}, {19, 78, "DEV_CPSW0_SERDES3_TXCLK", "Output clock"}, {19, 79, "DEV_CPSW0_CPTS_GENF0", "Output clock"}, {19, 80, "DEV_CPSW0_SERDES5_TXCLK", "Output clock"}, {19, 81, "DEV_CPSW0_SERDES6_TXCLK", "Output clock"}, {19, 82, "DEV_CPSW0_SERDES8_TXCLK", "Output clock"}, {19, 83, "DEV_CPSW0_SERDES1_TXCLK", "Output clock"}, {19, 84, "DEV_CPSW0_SERDES4_TXCLK", "Output clock"}, {19, 85, "DEV_CPSW0_SERDES2_TXCLK", "Output clock"}, {19, 86, "DEV_CPSW0_SERDES7_TXCLK", "Output clock"}, {19, 87, "DEV_CPSW0_MDIO_MDCLK_O", "Output clock"}, {19, 89, "DEV_CPSW0_CPPI_CLK_CLK", "Input clock"}, {20, 0, "DEV_CPT2_AGGR0_VCLK_CLK", "Input clock"}, {21, 0, "DEV_CPT2_AGGR1_VCLK_CLK", "Input clock"}, {23, 0, "DEV_CPT2_AGGR2_VCLK_CLK", "Input clock"}, {25, 0, "DEV_CSI_PSILSS0_MAIN_CLK", "Input clock"}, {26, 0, "DEV_CSI_RX_IF0_VBUS_CLK_CLK", "Input clock"}, {26, 1, "DEV_CSI_RX_IF0_PPI_RX_BYTE_CLK", "Input clock"}, {26, 2, "DEV_CSI_RX_IF0_MAIN_CLK_CLK", "Input clock"}, {26, 3, "DEV_CSI_RX_IF0_VP_CLK_CLK", "Input clock"}, {27, 0, "DEV_CSI_RX_IF1_VBUS_CLK_CLK", "Input clock"}, {27, 1, "DEV_CSI_RX_IF1_PPI_RX_BYTE_CLK", "Input clock"}, {27, 2, "DEV_CSI_RX_IF1_MAIN_CLK_CLK", "Input clock"}, {27, 3, "DEV_CSI_RX_IF1_VP_CLK_CLK", "Input clock"}, {28, 0, "DEV_CSI_TX_IF0_ESC_CLK_CLK", "Input clock"}, {28, 1, "DEV_CSI_TX_IF0_DPHY_TXBYTECLKHS_CL_CLK", "Input clock"}, {28, 2, "DEV_CSI_TX_IF0_VBUS_CLK_CLK", "Input clock"}, {28, 3, "DEV_CSI_TX_IF0_MAIN_CLK_CLK", "Input clock"}, {30, 0, "DEV_DCC0_DCC_INPUT10_CLK", "Input clock"}, {30, 1, "DEV_DCC0_DCC_INPUT01_CLK", "Input clock"}, {30, 2, "DEV_DCC0_DCC_CLKSRC2_CLK", "Input clock"}, {30, 3, "DEV_DCC0_DCC_CLKSRC7_CLK", "Input clock"}, {30, 4, "DEV_DCC0_DCC_CLKSRC0_CLK", "Input clock"}, {30, 5, "DEV_DCC0_VBUS_CLK", "Input clock"}, {30, 6, "DEV_DCC0_DCC_CLKSRC4_CLK", "Input clock"}, {30, 7, "DEV_DCC0_DCC_CLKSRC1_CLK", "Input clock"}, {30, 8, "DEV_DCC0_DCC_CLKSRC3_CLK", "Input clock"}, {30, 9, "DEV_DCC0_DCC_INPUT00_CLK", "Input clock"}, {30, 10, "DEV_DCC0_DCC_CLKSRC5_CLK", "Input clock"}, {30, 11, "DEV_DCC0_DCC_CLKSRC6_CLK", "Input clock"}, {30, 12, "DEV_DCC0_DCC_INPUT02_CLK", "Input clock"}, {31, 0, "DEV_DCC1_DCC_INPUT10_CLK", "Input clock"}, {31, 1, "DEV_DCC1_DCC_INPUT01_CLK", "Input clock"}, {31, 2, "DEV_DCC1_DCC_CLKSRC2_CLK", "Input clock"}, {31, 3, "DEV_DCC1_DCC_CLKSRC7_CLK", "Input clock"}, {31, 4, "DEV_DCC1_DCC_CLKSRC0_CLK", "Input clock"}, {31, 5, "DEV_DCC1_VBUS_CLK", "Input clock"}, {31, 6, "DEV_DCC1_DCC_CLKSRC4_CLK", "Input clock"}, {31, 7, "DEV_DCC1_DCC_CLKSRC1_CLK", "Input clock"}, {31, 8, "DEV_DCC1_DCC_CLKSRC3_CLK", "Input clock"}, {31, 9, "DEV_DCC1_DCC_INPUT00_CLK", "Input clock"}, {31, 10, "DEV_DCC1_DCC_CLKSRC5_CLK", "Input clock"}, {31, 11, "DEV_DCC1_DCC_CLKSRC6_CLK", "Input clock"}, {31, 12, "DEV_DCC1_DCC_INPUT02_CLK", "Input clock"}, {41, 0, "DEV_DCC10_DCC_INPUT10_CLK", "Input clock"}, {41, 1, "DEV_DCC10_DCC_INPUT01_CLK", "Input clock"}, {41, 2, "DEV_DCC10_DCC_CLKSRC2_CLK", "Input clock"}, {41, 3, "DEV_DCC10_DCC_CLKSRC7_CLK", "Input clock"}, {41, 4, "DEV_DCC10_DCC_CLKSRC0_CLK", "Input clock"}, {41, 5, "DEV_DCC10_VBUS_CLK", "Input clock"}, {41, 6, "DEV_DCC10_DCC_CLKSRC4_CLK", "Input clock"}, {41, 7, "DEV_DCC10_DCC_CLKSRC1_CLK", "Input clock"}, {41, 8, "DEV_DCC10_DCC_CLKSRC3_CLK", "Input clock"}, {41, 9, "DEV_DCC10_DCC_INPUT00_CLK", "Input clock"}, {41, 10, "DEV_DCC10_DCC_CLKSRC5_CLK", "Input clock"}, {41, 11, "DEV_DCC10_DCC_CLKSRC6_CLK", "Input clock"}, {41, 12, "DEV_DCC10_DCC_INPUT02_CLK", "Input clock"}, {42, 0, "DEV_DCC11_DCC_INPUT10_CLK", "Input clock"}, {42, 1, "DEV_DCC11_DCC_INPUT01_CLK", "Input clock"}, {42, 2, "DEV_DCC11_DCC_CLKSRC2_CLK", "Input clock"}, {42, 3, "DEV_DCC11_DCC_CLKSRC7_CLK", "Input clock"}, {42, 4, "DEV_DCC11_DCC_CLKSRC0_CLK", "Input clock"}, {42, 5, "DEV_DCC11_VBUS_CLK", "Input clock"}, {42, 6, "DEV_DCC11_DCC_CLKSRC4_CLK", "Input clock"}, {42, 7, "DEV_DCC11_DCC_CLKSRC1_CLK", "Input clock"}, {42, 8, "DEV_DCC11_DCC_CLKSRC3_CLK", "Input clock"}, {42, 9, "DEV_DCC11_DCC_INPUT00_CLK", "Input clock"}, {42, 10, "DEV_DCC11_DCC_CLKSRC5_CLK", "Input clock"}, {42, 11, "DEV_DCC11_DCC_CLKSRC6_CLK", "Input clock"}, {42, 12, "DEV_DCC11_DCC_INPUT02_CLK", "Input clock"}, {43, 0, "DEV_DCC12_DCC_INPUT10_CLK", "Input clock"}, {43, 1, "DEV_DCC12_DCC_INPUT01_CLK", "Input clock"}, {43, 2, "DEV_DCC12_DCC_CLKSRC2_CLK", "Input clock"}, {43, 3, "DEV_DCC12_DCC_CLKSRC7_CLK", "Input clock"}, {43, 4, "DEV_DCC12_DCC_CLKSRC0_CLK", "Input clock"}, {43, 5, "DEV_DCC12_VBUS_CLK", "Input clock"}, {43, 6, "DEV_DCC12_DCC_CLKSRC4_CLK", "Input clock"}, {43, 7, "DEV_DCC12_DCC_CLKSRC1_CLK", "Input clock"}, {43, 8, "DEV_DCC12_DCC_CLKSRC3_CLK", "Input clock"}, {43, 9, "DEV_DCC12_DCC_INPUT00_CLK", "Input clock"}, {43, 10, "DEV_DCC12_DCC_CLKSRC5_CLK", "Input clock"}, {43, 11, "DEV_DCC12_DCC_CLKSRC6_CLK", "Input clock"}, {43, 12, "DEV_DCC12_DCC_INPUT02_CLK", "Input clock"}, {32, 0, "DEV_DCC2_DCC_INPUT10_CLK", "Input clock"}, {32, 1, "DEV_DCC2_DCC_INPUT01_CLK", "Input clock"}, {32, 2, "DEV_DCC2_DCC_CLKSRC2_CLK", "Input clock"}, {32, 3, "DEV_DCC2_DCC_CLKSRC7_CLK", "Input clock"}, {32, 4, "DEV_DCC2_DCC_CLKSRC0_CLK", "Input clock"}, {32, 5, "DEV_DCC2_VBUS_CLK", "Input clock"}, {32, 6, "DEV_DCC2_DCC_CLKSRC4_CLK", "Input clock"}, {32, 7, "DEV_DCC2_DCC_CLKSRC1_CLK", "Input clock"}, {32, 8, "DEV_DCC2_DCC_CLKSRC3_CLK", "Input clock"}, {32, 9, "DEV_DCC2_DCC_INPUT00_CLK", "Input clock"}, {32, 10, "DEV_DCC2_DCC_CLKSRC5_CLK", "Input clock"}, {32, 11, "DEV_DCC2_DCC_CLKSRC6_CLK", "Input clock"}, {32, 12, "DEV_DCC2_DCC_INPUT02_CLK", "Input clock"}, {33, 0, "DEV_DCC3_DCC_INPUT10_CLK", "Input clock"}, {33, 1, "DEV_DCC3_DCC_INPUT01_CLK", "Input clock"}, {33, 2, "DEV_DCC3_DCC_CLKSRC2_CLK", "Input clock"}, {33, 3, "DEV_DCC3_DCC_CLKSRC7_CLK", "Input clock"}, {33, 4, "DEV_DCC3_DCC_CLKSRC0_CLK", "Input clock"}, {33, 5, "DEV_DCC3_VBUS_CLK", "Input clock"}, {33, 6, "DEV_DCC3_DCC_CLKSRC4_CLK", "Input clock"}, {33, 7, "DEV_DCC3_DCC_CLKSRC1_CLK", "Input clock"}, {33, 8, "DEV_DCC3_DCC_CLKSRC3_CLK", "Input clock"}, {33, 9, "DEV_DCC3_DCC_INPUT00_CLK", "Input clock"}, {33, 10, "DEV_DCC3_DCC_CLKSRC5_CLK", "Input clock"}, {33, 11, "DEV_DCC3_DCC_CLKSRC6_CLK", "Input clock"}, {33, 12, "DEV_DCC3_DCC_INPUT02_CLK", "Input clock"}, {34, 0, "DEV_DCC4_DCC_INPUT10_CLK", "Input clock"}, {34, 1, "DEV_DCC4_DCC_INPUT01_CLK", "Input clock"}, {34, 2, "DEV_DCC4_DCC_CLKSRC2_CLK", "Input clock"}, {34, 3, "DEV_DCC4_DCC_CLKSRC7_CLK", "Input clock"}, {34, 4, "DEV_DCC4_DCC_CLKSRC0_CLK", "Input clock"}, {34, 5, "DEV_DCC4_VBUS_CLK", "Input clock"}, {34, 6, "DEV_DCC4_DCC_CLKSRC4_CLK", "Input clock"}, {34, 7, "DEV_DCC4_DCC_CLKSRC1_CLK", "Input clock"}, {34, 8, "DEV_DCC4_DCC_CLKSRC3_CLK", "Input clock"}, {34, 9, "DEV_DCC4_DCC_INPUT00_CLK", "Input clock"}, {34, 10, "DEV_DCC4_DCC_CLKSRC5_CLK", "Input clock"}, {34, 11, "DEV_DCC4_DCC_CLKSRC6_CLK", "Input clock"}, {34, 12, "DEV_DCC4_DCC_INPUT02_CLK", "Input clock"}, {36, 0, "DEV_DCC5_DCC_INPUT10_CLK", "Input clock"}, {36, 1, "DEV_DCC5_DCC_INPUT01_CLK", "Input clock"}, {36, 2, "DEV_DCC5_DCC_CLKSRC2_CLK", "Input clock"}, {36, 3, "DEV_DCC5_DCC_CLKSRC7_CLK", "Input clock"}, {36, 4, "DEV_DCC5_DCC_CLKSRC0_CLK", "Input clock"}, {36, 5, "DEV_DCC5_VBUS_CLK", "Input clock"}, {36, 6, "DEV_DCC5_DCC_CLKSRC4_CLK", "Input clock"}, {36, 7, "DEV_DCC5_DCC_CLKSRC1_CLK", "Input clock"}, {36, 8, "DEV_DCC5_DCC_CLKSRC3_CLK", "Input clock"}, {36, 9, "DEV_DCC5_DCC_INPUT00_CLK", "Input clock"}, {36, 10, "DEV_DCC5_DCC_CLKSRC5_CLK", "Input clock"}, {36, 11, "DEV_DCC5_DCC_CLKSRC6_CLK", "Input clock"}, {36, 12, "DEV_DCC5_DCC_INPUT02_CLK", "Input clock"}, {37, 0, "DEV_DCC6_DCC_INPUT10_CLK", "Input clock"}, {37, 1, "DEV_DCC6_DCC_INPUT01_CLK", "Input clock"}, {37, 2, "DEV_DCC6_DCC_CLKSRC2_CLK", "Input clock"}, {37, 3, "DEV_DCC6_DCC_CLKSRC7_CLK", "Input clock"}, {37, 4, "DEV_DCC6_DCC_CLKSRC0_CLK", "Input clock"}, {37, 5, "DEV_DCC6_VBUS_CLK", "Input clock"}, {37, 6, "DEV_DCC6_DCC_CLKSRC4_CLK", "Input clock"}, {37, 7, "DEV_DCC6_DCC_CLKSRC1_CLK", "Input clock"}, {37, 8, "DEV_DCC6_DCC_CLKSRC3_CLK", "Input clock"}, {37, 9, "DEV_DCC6_DCC_INPUT00_CLK", "Input clock"}, {37, 10, "DEV_DCC6_DCC_CLKSRC5_CLK", "Input clock"}, {37, 11, "DEV_DCC6_DCC_CLKSRC6_CLK", "Input clock"}, {37, 12, "DEV_DCC6_DCC_INPUT02_CLK", "Input clock"}, {38, 0, "DEV_DCC7_DCC_INPUT10_CLK", "Input clock"}, {38, 1, "DEV_DCC7_DCC_INPUT01_CLK", "Input clock"}, {38, 2, "DEV_DCC7_DCC_CLKSRC2_CLK", "Input clock"}, {38, 3, "DEV_DCC7_DCC_CLKSRC7_CLK", "Input clock"}, {38, 4, "DEV_DCC7_DCC_CLKSRC0_CLK", "Input clock"}, {38, 5, "DEV_DCC7_VBUS_CLK", "Input clock"}, {38, 6, "DEV_DCC7_DCC_CLKSRC4_CLK", "Input clock"}, {38, 7, "DEV_DCC7_DCC_CLKSRC1_CLK", "Input clock"}, {38, 8, "DEV_DCC7_DCC_CLKSRC3_CLK", "Input clock"}, {38, 9, "DEV_DCC7_DCC_INPUT00_CLK", "Input clock"}, {38, 10, "DEV_DCC7_DCC_CLKSRC5_CLK", "Input clock"}, {38, 11, "DEV_DCC7_DCC_CLKSRC6_CLK", "Input clock"}, {38, 12, "DEV_DCC7_DCC_INPUT02_CLK", "Input clock"}, {39, 0, "DEV_DCC8_DCC_INPUT10_CLK", "Input clock"}, {39, 1, "DEV_DCC8_DCC_INPUT01_CLK", "Input clock"}, {39, 2, "DEV_DCC8_DCC_CLKSRC2_CLK", "Input clock"}, {39, 3, "DEV_DCC8_DCC_CLKSRC7_CLK", "Input clock"}, {39, 4, "DEV_DCC8_DCC_CLKSRC0_CLK", "Input clock"}, {39, 5, "DEV_DCC8_VBUS_CLK", "Input clock"}, {39, 6, "DEV_DCC8_DCC_CLKSRC4_CLK", "Input clock"}, {39, 7, "DEV_DCC8_DCC_CLKSRC1_CLK", "Input clock"}, {39, 8, "DEV_DCC8_DCC_CLKSRC3_CLK", "Input clock"}, {39, 9, "DEV_DCC8_DCC_INPUT00_CLK", "Input clock"}, {39, 10, "DEV_DCC8_DCC_CLKSRC5_CLK", "Input clock"}, {39, 11, "DEV_DCC8_DCC_CLKSRC6_CLK", "Input clock"}, {39, 12, "DEV_DCC8_DCC_INPUT02_CLK", "Input clock"}, {40, 0, "DEV_DCC9_DCC_INPUT10_CLK", "Input clock"}, {40, 1, "DEV_DCC9_DCC_INPUT01_CLK", "Input clock"}, {40, 2, "DEV_DCC9_DCC_CLKSRC2_CLK", "Input clock"}, {40, 3, "DEV_DCC9_DCC_CLKSRC7_CLK", "Input clock"}, {40, 4, "DEV_DCC9_DCC_CLKSRC0_CLK", "Input clock"}, {40, 5, "DEV_DCC9_VBUS_CLK", "Input clock"}, {40, 6, "DEV_DCC9_DCC_CLKSRC4_CLK", "Input clock"}, {40, 7, "DEV_DCC9_DCC_CLKSRC1_CLK", "Input clock"}, {40, 8, "DEV_DCC9_DCC_CLKSRC3_CLK", "Input clock"}, {40, 9, "DEV_DCC9_DCC_INPUT00_CLK", "Input clock"}, {40, 10, "DEV_DCC9_DCC_CLKSRC5_CLK", "Input clock"}, {40, 11, "DEV_DCC9_DCC_CLKSRC6_CLK", "Input clock"}, {40, 12, "DEV_DCC9_DCC_INPUT02_CLK", "Input clock"}, {47, 0, "DEV_DDR0_DDRSS_VBUS_CLK", "Input clock"}, {47, 1, "DEV_DDR0_PLL_CTRL_CLK", "Input clock"}, {47, 2, "DEV_DDR0_DDRSS_DDR_PLL_CLK", "Input clock"}, {47, 3, "DEV_DDR0_DDRSS_CFG_CLK", "Input clock"}, {47, 4, "DEV_DDR0_DDRSS_IO_CK_N", "Output clock"}, {47, 5, "DEV_DDR0_DDRSS_IO_CK", "Output clock"}, {304, 5, "DEV_DEBUGSS_WRAP0_TREXPT_CLK", "Input clock"}, {304, 9, "DEV_DEBUGSS_WRAP0_CORE_CLK", "Input clock"}, {304, 25, "DEV_DEBUGSS_WRAP0_JTAG_TCK", "Input clock"}, {304, 32, "DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK", "Output clock"}, {304, 35, "DEV_DEBUGSS_WRAP0_ATB_CLK", "Input clock"}, {144, 0, "DEV_DECODER0_SYS_CLK", "Input clock"}, {48, 0, "DEV_DMPAC0_CLK", "Input clock"}, {48, 1, "DEV_DMPAC0_PLL_DCO_CLK", "Input clock"}, {305, 0, "DEV_DMPAC0_SDE_0_CLK", "Input clock"}, {147, 0, "DEV_DPHY_RX0_MAIN_CLK_CLK", "Input clock"}, {147, 1, "DEV_DPHY_RX0_PPI_RX_BYTE_CLK", "Output clock"}, {148, 0, "DEV_DPHY_RX1_MAIN_CLK_CLK", "Input clock"}, {148, 1, "DEV_DPHY_RX1_PPI_RX_BYTE_CLK", "Output clock"}, {296, 0, "DEV_DPHY_TX0_CLK", "Input clock"}, {296, 1, "DEV_DPHY_TX0_PSM_CLK", "Input clock"}, {296, 2, "DEV_DPHY_TX0_IP1_PPI_M_TXCLKESC_CLK", "Input clock"}, {296, 3, "DEV_DPHY_TX0_DPHY_REF_CLK", "Input muxed clock"}, {296, 4, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"}, {296, 5, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"}, {296, 6, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"}, {296, 7, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"}, {296, 8, "DEV_DPHY_TX0_IP1_PPI_TXBYTECLKHS_CL_CLK", "Output clock"}, {296, 9, "DEV_DPHY_TX0_IP1_PPI_M_RXCLKESC_CLK", "Output clock"}, {296, 10, "DEV_DPHY_TX0_CK_P", "Output clock"}, {296, 11, "DEV_DPHY_TX0_CK_M", "Output clock"}, {296, 12, "DEV_DPHY_TX0_IP2_PPI_TXBYTECLKHS_CL_CLK", "Output clock"}, {152, 0, "DEV_DSS0_DSS_FUNC_CLK", "Input clock"}, {152, 1, "DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK", "Input muxed clock"}, {152, 2, "DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK"}, {152, 3, "DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_DPI_1_PCLK_SEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK"}, {152, 4, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK", "Input muxed clock"}, {152, 5, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"}, {152, 6, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"}, {152, 7, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI1_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"}, {152, 8, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"}, {152, 9, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK", "Input muxed clock"}, {152, 10, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK"}, {152, 11, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK"}, {152, 12, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK"}, {152, 13, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK", "Input muxed clock"}, {152, 14, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT1_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"}, {152, 15, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"}, {152, 16, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT1_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"}, {152, 17, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"}, {152, 18, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI1_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"}, {152, 23, "DEV_DSS0_DSS_INST0_DPI_0_OUT_CLK", "Output clock"}, {152, 24, "DEV_DSS0_DSS_INST0_DPI_0_OUT_2X_CLK", "Output clock"}, {152, 25, "DEV_DSS0_DSS_INST0_DPI_1_OUT_CLK", "Output clock"}, {152, 27, "DEV_DSS0_DSS_INST0_DPI_2_OUT_CLK", "Output clock"}, {152, 29, "DEV_DSS0_DSS_INST0_DPI_3_OUT_CLK", "Output clock"}, {152, 31, "DEV_DSS0_DPI0_EXT_CLKSEL", "Input muxed clock"}, {152, 32, "DEV_DSS0_DPI0_EXT_CLKSEL_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DPI0_EXT_CLKSEL"}, {152, 33, "DEV_DSS0_DPI0_EXT_CLKSEL_PARENT_BOARD_0_VOUT1_EXTPCLKIN_OUT", "Parent input clock option to DEV_DSS0_DPI0_EXT_CLKSEL"}, {152, 34, "DEV_DSS0_DPI1_EXT_CLKSEL", "Input muxed clock"}, {152, 35, "DEV_DSS0_DPI1_EXT_CLKSEL_PARENT_HSDIV1_16FFT_MAIN_23_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DPI1_EXT_CLKSEL"}, {152, 36, "DEV_DSS0_DPI1_EXT_CLKSEL_PARENT_BOARD_0_VOUT2_EXTPCLKIN_OUT", "Parent input clock option to DEV_DSS0_DPI1_EXT_CLKSEL"}, {150, 0, "DEV_DSS_DSI0_DPHY_0_RX_ESC_CLK", "Input clock"}, {150, 1, "DEV_DSS_DSI0_DPI_0_CLK", "Input clock"}, {150, 2, "DEV_DSS_DSI0_PLL_CTRL_CLK", "Input clock"}, {150, 3, "DEV_DSS_DSI0_PPI_0_TXBYTECLKHS_CL_CLK", "Input clock"}, {150, 4, "DEV_DSS_DSI0_DPHY_0_TX_ESC_CLK", "Input clock"}, {150, 5, "DEV_DSS_DSI0_SYS_CLK", "Input clock"}, {151, 0, "DEV_DSS_EDP0_PHY_LN1_TXFCLK", "Input clock"}, {151, 1, "DEV_DSS_EDP0_DPI_2_CLK", "Input clock"}, {151, 2, "DEV_DSS_EDP0_PHY_LN2_TXFCLK", "Input clock"}, {151, 3, "DEV_DSS_EDP0_PHY_LN0_RXCLK", "Input clock"}, {151, 4, "DEV_DSS_EDP0_PHY_LN2_TXMCLK", "Input clock"}, {151, 5, "DEV_DSS_EDP0_PHY_LN0_RXFCLK", "Input clock"}, {151, 6, "DEV_DSS_EDP0_PHY_LN0_REFCLK", "Input clock"}, {151, 7, "DEV_DSS_EDP0_PHY_LN1_RXCLK", "Input clock"}, {151, 8, "DEV_DSS_EDP0_PHY_LN2_RXFCLK", "Input clock"}, {151, 9, "DEV_DSS_EDP0_DPI_4_CLK", "Input clock"}, {151, 10, "DEV_DSS_EDP0_DPI_2_2X_CLK", "Input clock"}, {151, 11, "DEV_DSS_EDP0_PHY_LN0_TXFCLK", "Input clock"}, {151, 12, "DEV_DSS_EDP0_PHY_LN2_RXCLK", "Input clock"}, {151, 13, "DEV_DSS_EDP0_PHY_LN2_REFCLK", "Input clock"}, {151, 14, "DEV_DSS_EDP0_PHY_LN3_REFCLK", "Input clock"}, {151, 15, "DEV_DSS_EDP0_DPI_5_CLK", "Input clock"}, {151, 16, "DEV_DSS_EDP0_PHY_LN3_RXCLK", "Input clock"}, {151, 17, "DEV_DSS_EDP0_PHY_LN1_REFCLK", "Input clock"}, {151, 18, "DEV_DSS_EDP0_AIF_I2S_CLK", "Input clock"}, {151, 19, "DEV_DSS_EDP0_PHY_LN3_TXFCLK", "Input clock"}, {151, 20, "DEV_DSS_EDP0_DPI_3_CLK", "Input clock"}, {151, 21, "DEV_DSS_EDP0_PHY_LN1_RXFCLK", "Input clock"}, {151, 22, "DEV_DSS_EDP0_PHY_LN1_TXMCLK", "Input clock"}, {151, 23, "DEV_DSS_EDP0_PLL_CTRL_CLK", "Input clock"}, {151, 24, "DEV_DSS_EDP0_PHY_LN3_TXMCLK", "Input clock"}, {151, 25, "DEV_DSS_EDP0_PHY_LN3_RXFCLK", "Input clock"}, {151, 26, "DEV_DSS_EDP0_PHY_LN0_TXMCLK", "Input clock"}, {151, 27, "DEV_DSS_EDP0_PHY_LN2_TXCLK", "Output clock"}, {151, 28, "DEV_DSS_EDP0_PHY_LN3_TXCLK", "Output clock"}, {151, 29, "DEV_DSS_EDP0_PHY_LN0_TXCLK", "Output clock"}, {151, 30, "DEV_DSS_EDP0_PHY_LN1_TXCLK", "Output clock"}, {151, 36, "DEV_DSS_EDP0_DPTX_MOD_CLK", "Input clock"}, {80, 0, "DEV_ECAP0_VBUS_CLK", "Input clock"}, {81, 0, "DEV_ECAP1_VBUS_CLK", "Input clock"}, {82, 0, "DEV_ECAP2_VBUS_CLK", "Input clock"}, {83, 0, "DEV_EHRPWM0_VBUSP_CLK", "Input clock"}, {84, 0, "DEV_EHRPWM1_VBUSP_CLK", "Input clock"}, {85, 0, "DEV_EHRPWM2_VBUSP_CLK", "Input clock"}, {86, 0, "DEV_EHRPWM3_VBUSP_CLK", "Input clock"}, {87, 0, "DEV_EHRPWM4_VBUSP_CLK", "Input clock"}, {88, 0, "DEV_EHRPWM5_VBUSP_CLK", "Input clock"}, {89, 0, "DEV_ELM0_VBUSP_CLK", "Input clock"}, {153, 0, "DEV_ENCODER0_SYS_CLK", "Input clock"}, {94, 0, "DEV_EQEP0_VBUS_CLK", "Input clock"}, {95, 0, "DEV_EQEP1_VBUS_CLK", "Input clock"}, {96, 0, "DEV_EQEP2_VBUS_CLK", "Input clock"}, {97, 0, "DEV_ESM0_CLK", "Input clock"}, {105, 0, "DEV_GPIO0_MMR_CLK", "Input clock"}, {106, 0, "DEV_GPIO1_MMR_CLK", "Input clock"}, {107, 0, "DEV_GPIO2_MMR_CLK", "Input clock"}, {108, 0, "DEV_GPIO3_MMR_CLK", "Input clock"}, {109, 0, "DEV_GPIO4_MMR_CLK", "Input clock"}, {110, 0, "DEV_GPIO5_MMR_CLK", "Input clock"}, {111, 0, "DEV_GPIO6_MMR_CLK", "Input clock"}, {112, 0, "DEV_GPIO7_MMR_CLK", "Input clock"}, {131, 0, "DEV_GPIOMUX_INTRTR0_INTR_CLK", "Input clock"}, {115, 0, "DEV_GPMC0_PI_GPMC_RET_CLK", "Input clock"}, {115, 1, "DEV_GPMC0_VBUSP_CLK", "Input clock"}, {115, 2, "DEV_GPMC0_FUNC_CLK", "Input muxed clock"}, {115, 3, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_GPMC0_FUNC_CLK"}, {115, 4, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK6", "Parent input clock option to DEV_GPMC0_FUNC_CLK"}, {115, 5, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK4", "Parent input clock option to DEV_GPMC0_FUNC_CLK"}, {115, 6, "DEV_GPMC0_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_GPMC0_FUNC_CLK"}, {115, 7, "DEV_GPMC0_PO_GPMC_DEV_CLK", "Output clock"}, {125, 0, "DEV_GPU0_GPU_0_GPU_PLL_CLK", "Input clock"}, {61, 0, "DEV_GTC0_VBUSP_CLK", "Input clock"}, {61, 1, "DEV_GTC0_GTC_CLK", "Input muxed clock"}, {61, 2, "DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 3, "DEV_GTC0_GTC_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 4, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 5, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 6, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 7, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 8, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 9, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 10, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 11, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 12, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 13, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 14, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 15, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 16, "DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 17, "DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {187, 0, "DEV_I2C0_PISYS_CLK", "Input clock"}, {187, 1, "DEV_I2C0_PISCL", "Input clock"}, {187, 2, "DEV_I2C0_CLK", "Input clock"}, {187, 3, "DEV_I2C0_PORSCL", "Output clock"}, {188, 0, "DEV_I2C1_PISYS_CLK", "Input clock"}, {188, 1, "DEV_I2C1_PISCL", "Input clock"}, {188, 2, "DEV_I2C1_CLK", "Input clock"}, {188, 3, "DEV_I2C1_PORSCL", "Output clock"}, {189, 0, "DEV_I2C2_PISYS_CLK", "Input clock"}, {189, 1, "DEV_I2C2_PISCL", "Input clock"}, {189, 2, "DEV_I2C2_CLK", "Input clock"}, {189, 3, "DEV_I2C2_PORSCL", "Output clock"}, {190, 0, "DEV_I2C3_PISYS_CLK", "Input clock"}, {190, 1, "DEV_I2C3_PISCL", "Input clock"}, {190, 2, "DEV_I2C3_CLK", "Input clock"}, {190, 3, "DEV_I2C3_PORSCL", "Output clock"}, {191, 0, "DEV_I2C4_PISYS_CLK", "Input clock"}, {191, 1, "DEV_I2C4_PISCL", "Input clock"}, {191, 2, "DEV_I2C4_CLK", "Input clock"}, {191, 3, "DEV_I2C4_PORSCL", "Output clock"}, {192, 0, "DEV_I2C5_PISYS_CLK", "Input clock"}, {192, 1, "DEV_I2C5_PISCL", "Input clock"}, {192, 2, "DEV_I2C5_CLK", "Input clock"}, {192, 3, "DEV_I2C5_PORSCL", "Output clock"}, {193, 0, "DEV_I2C6_PISYS_CLK", "Input clock"}, {193, 1, "DEV_I2C6_PISCL", "Input clock"}, {193, 2, "DEV_I2C6_CLK", "Input clock"}, {193, 3, "DEV_I2C6_PORSCL", "Output clock"}, {116, 0, "DEV_I3C0_I3C_PCLK_CLK", "Input clock"}, {116, 1, "DEV_I3C0_I3C_SCL_DI", "Input clock"}, {116, 2, "DEV_I3C0_I3C_SCLK_CLK", "Input clock"}, {116, 3, "DEV_I3C0_I3C_SCL_DO", "Output clock"}, {127, 0, "DEV_LED0_LED_CLK", "Input clock"}, {127, 1, "DEV_LED0_VBUS_CLK", "Input clock"}, {128, 0, "DEV_MAIN2MCU_LVL_INTRTR0_INTR_CLK", "Input clock"}, {130, 0, "DEV_MAIN2MCU_PLS_INTRTR0_INTR_CLK", "Input clock"}, {156, 0, "DEV_MCAN0_MCANSS_HCLK_CLK", "Input clock"}, {156, 1, "DEV_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"}, {156, 2, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, {156, 3, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, {156, 4, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, {156, 5, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, {158, 0, "DEV_MCAN1_MCANSS_HCLK_CLK", "Input clock"}, {158, 1, "DEV_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"}, {158, 2, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, {158, 3, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, {158, 4, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, {158, 5, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, {168, 0, "DEV_MCAN10_MCANSS_HCLK_CLK", "Input clock"}, {168, 1, "DEV_MCAN10_MCANSS_CCLK_CLK", "Input muxed clock"}, {168, 2, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"}, {168, 3, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"}, {168, 4, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"}, {168, 5, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"}, {169, 0, "DEV_MCAN11_MCANSS_HCLK_CLK", "Input clock"}, {169, 1, "DEV_MCAN11_MCANSS_CCLK_CLK", "Input muxed clock"}, {169, 2, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"}, {169, 3, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"}, {169, 4, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"}, {169, 5, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"}, {170, 0, "DEV_MCAN12_MCANSS_HCLK_CLK", "Input clock"}, {170, 1, "DEV_MCAN12_MCANSS_CCLK_CLK", "Input muxed clock"}, {170, 2, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"}, {170, 3, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"}, {170, 4, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"}, {170, 5, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"}, {171, 0, "DEV_MCAN13_MCANSS_HCLK_CLK", "Input clock"}, {171, 1, "DEV_MCAN13_MCANSS_CCLK_CLK", "Input muxed clock"}, {171, 2, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"}, {171, 3, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"}, {171, 4, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"}, {171, 5, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"}, {160, 0, "DEV_MCAN2_MCANSS_HCLK_CLK", "Input clock"}, {160, 1, "DEV_MCAN2_MCANSS_CCLK_CLK", "Input muxed clock"}, {160, 2, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"}, {160, 3, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"}, {160, 4, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"}, {160, 5, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"}, {161, 0, "DEV_MCAN3_MCANSS_HCLK_CLK", "Input clock"}, {161, 1, "DEV_MCAN3_MCANSS_CCLK_CLK", "Input muxed clock"}, {161, 2, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"}, {161, 3, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"}, {161, 4, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"}, {161, 5, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"}, {162, 0, "DEV_MCAN4_MCANSS_HCLK_CLK", "Input clock"}, {162, 1, "DEV_MCAN4_MCANSS_CCLK_CLK", "Input muxed clock"}, {162, 2, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"}, {162, 3, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"}, {162, 4, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"}, {162, 5, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"}, {163, 0, "DEV_MCAN5_MCANSS_HCLK_CLK", "Input clock"}, {163, 1, "DEV_MCAN5_MCANSS_CCLK_CLK", "Input muxed clock"}, {163, 2, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"}, {163, 3, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"}, {163, 4, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"}, {163, 5, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"}, {164, 0, "DEV_MCAN6_MCANSS_HCLK_CLK", "Input clock"}, {164, 1, "DEV_MCAN6_MCANSS_CCLK_CLK", "Input muxed clock"}, {164, 2, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"}, {164, 3, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"}, {164, 4, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"}, {164, 5, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"}, {165, 0, "DEV_MCAN7_MCANSS_HCLK_CLK", "Input clock"}, {165, 1, "DEV_MCAN7_MCANSS_CCLK_CLK", "Input muxed clock"}, {165, 2, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"}, {165, 3, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"}, {165, 4, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"}, {165, 5, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"}, {166, 0, "DEV_MCAN8_MCANSS_HCLK_CLK", "Input clock"}, {166, 1, "DEV_MCAN8_MCANSS_CCLK_CLK", "Input muxed clock"}, {166, 2, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"}, {166, 3, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"}, {166, 4, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"}, {166, 5, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"}, {167, 0, "DEV_MCAN9_MCANSS_HCLK_CLK", "Input clock"}, {167, 1, "DEV_MCAN9_MCANSS_CCLK_CLK", "Input muxed clock"}, {167, 2, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"}, {167, 3, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"}, {167, 4, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"}, {167, 5, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"}, {174, 0, "DEV_MCASP0_VBUSP_CLK", "Input clock"}, {174, 1, "DEV_MCASP0_AUX_CLK", "Input muxed clock"}, {174, 2, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, {174, 3, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, {174, 4, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, {174, 6, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, {174, 7, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, {174, 8, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, {174, 9, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, {174, 10, "DEV_MCASP0_MCASP_ACLKX_POUT", "Output clock"}, {174, 11, "DEV_MCASP0_MCASP_ACLKX_PIN", "Input clock"}, {174, 12, "DEV_MCASP0_MCASP_ACLKR_POUT", "Output clock"}, {174, 13, "DEV_MCASP0_MCASP_ACLKR_PIN", "Input clock"}, {174, 14, "DEV_MCASP0_MCASP_AHCLKX_POUT", "Output clock"}, {174, 15, "DEV_MCASP0_MCASP_AHCLKX_PIN", "Input muxed clock"}, {174, 16, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {174, 17, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {174, 18, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {174, 19, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {174, 20, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {174, 21, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {174, 22, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {174, 23, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {174, 24, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {174, 25, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {174, 26, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {174, 27, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {174, 28, "DEV_MCASP0_MCASP_AHCLKR_POUT", "Output clock"}, {174, 29, "DEV_MCASP0_MCASP_AHCLKR_PIN", "Input muxed clock"}, {174, 30, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {174, 31, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {174, 32, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {174, 33, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {174, 34, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {174, 35, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {174, 36, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {174, 37, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {174, 38, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {174, 39, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {174, 40, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {174, 41, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {175, 0, "DEV_MCASP1_VBUSP_CLK", "Input clock"}, {175, 1, "DEV_MCASP1_AUX_CLK", "Input muxed clock"}, {175, 2, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, {175, 3, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, {175, 4, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, {175, 6, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, {175, 7, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, {175, 8, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, {175, 9, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, {175, 10, "DEV_MCASP1_MCASP_ACLKX_POUT", "Output clock"}, {175, 11, "DEV_MCASP1_MCASP_ACLKX_PIN", "Input clock"}, {175, 12, "DEV_MCASP1_MCASP_ACLKR_POUT", "Output clock"}, {175, 13, "DEV_MCASP1_MCASP_ACLKR_PIN", "Input clock"}, {175, 14, "DEV_MCASP1_MCASP_AHCLKX_POUT", "Output clock"}, {175, 15, "DEV_MCASP1_MCASP_AHCLKX_PIN", "Input muxed clock"}, {175, 16, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {175, 17, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {175, 18, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {175, 19, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {175, 20, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {175, 21, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {175, 22, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {175, 23, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {175, 24, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {175, 25, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {175, 26, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {175, 27, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {175, 28, "DEV_MCASP1_MCASP_AHCLKR_POUT", "Output clock"}, {175, 29, "DEV_MCASP1_MCASP_AHCLKR_PIN", "Input muxed clock"}, {175, 30, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {175, 31, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {175, 32, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {175, 33, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {175, 34, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {175, 35, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {175, 36, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {175, 37, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {175, 38, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {175, 39, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {175, 40, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {175, 41, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {184, 0, "DEV_MCASP10_VBUSP_CLK", "Input clock"}, {184, 1, "DEV_MCASP10_AUX_CLK", "Input muxed clock"}, {184, 2, "DEV_MCASP10_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP10_AUX_CLK"}, {184, 3, "DEV_MCASP10_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP10_AUX_CLK"}, {184, 4, "DEV_MCASP10_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP10_AUX_CLK"}, {184, 6, "DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP10_AUX_CLK"}, {184, 7, "DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP10_AUX_CLK"}, {184, 8, "DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP10_AUX_CLK"}, {184, 9, "DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP10_AUX_CLK"}, {184, 10, "DEV_MCASP10_MCASP_ACLKX_POUT", "Output clock"}, {184, 11, "DEV_MCASP10_MCASP_ACLKX_PIN", "Input clock"}, {184, 12, "DEV_MCASP10_MCASP_ACLKR_POUT", "Output clock"}, {184, 13, "DEV_MCASP10_MCASP_ACLKR_PIN", "Input clock"}, {184, 14, "DEV_MCASP10_MCASP_AHCLKX_POUT", "Output clock"}, {184, 15, "DEV_MCASP10_MCASP_AHCLKX_PIN", "Input muxed clock"}, {184, 16, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"}, {184, 17, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"}, {184, 18, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"}, {184, 19, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"}, {184, 20, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"}, {184, 21, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"}, {184, 22, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"}, {184, 23, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"}, {184, 24, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"}, {184, 25, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"}, {184, 26, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"}, {184, 27, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"}, {184, 28, "DEV_MCASP10_MCASP_AHCLKR_POUT", "Output clock"}, {184, 29, "DEV_MCASP10_MCASP_AHCLKR_PIN", "Input muxed clock"}, {184, 30, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"}, {184, 31, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"}, {184, 32, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"}, {184, 33, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"}, {184, 34, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"}, {184, 35, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"}, {184, 36, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"}, {184, 37, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"}, {184, 38, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"}, {184, 39, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"}, {184, 40, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"}, {184, 41, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"}, {185, 0, "DEV_MCASP11_VBUSP_CLK", "Input clock"}, {185, 1, "DEV_MCASP11_AUX_CLK", "Input muxed clock"}, {185, 2, "DEV_MCASP11_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP11_AUX_CLK"}, {185, 3, "DEV_MCASP11_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP11_AUX_CLK"}, {185, 4, "DEV_MCASP11_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP11_AUX_CLK"}, {185, 6, "DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP11_AUX_CLK"}, {185, 7, "DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP11_AUX_CLK"}, {185, 8, "DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP11_AUX_CLK"}, {185, 9, "DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP11_AUX_CLK"}, {185, 10, "DEV_MCASP11_MCASP_ACLKX_POUT", "Output clock"}, {185, 11, "DEV_MCASP11_MCASP_ACLKX_PIN", "Input clock"}, {185, 12, "DEV_MCASP11_MCASP_ACLKR_POUT", "Output clock"}, {185, 13, "DEV_MCASP11_MCASP_ACLKR_PIN", "Input clock"}, {185, 14, "DEV_MCASP11_MCASP_AHCLKX_POUT", "Output clock"}, {185, 15, "DEV_MCASP11_MCASP_AHCLKX_PIN", "Input muxed clock"}, {185, 16, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"}, {185, 17, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"}, {185, 18, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"}, {185, 19, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"}, {185, 20, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"}, {185, 21, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"}, {185, 22, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"}, {185, 23, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"}, {185, 24, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"}, {185, 25, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"}, {185, 26, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"}, {185, 27, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"}, {185, 28, "DEV_MCASP11_MCASP_AHCLKR_POUT", "Output clock"}, {185, 29, "DEV_MCASP11_MCASP_AHCLKR_PIN", "Input muxed clock"}, {185, 30, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"}, {185, 31, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"}, {185, 32, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"}, {185, 33, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"}, {185, 34, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"}, {185, 35, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"}, {185, 36, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"}, {185, 37, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"}, {185, 38, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"}, {185, 39, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"}, {185, 40, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"}, {185, 41, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"}, {176, 0, "DEV_MCASP2_VBUSP_CLK", "Input clock"}, {176, 1, "DEV_MCASP2_AUX_CLK", "Input muxed clock"}, {176, 2, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, {176, 3, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, {176, 4, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, {176, 6, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, {176, 7, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, {176, 8, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, {176, 9, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, {176, 10, "DEV_MCASP2_MCASP_ACLKX_POUT", "Output clock"}, {176, 11, "DEV_MCASP2_MCASP_ACLKX_PIN", "Input clock"}, {176, 12, "DEV_MCASP2_MCASP_ACLKR_POUT", "Output clock"}, {176, 13, "DEV_MCASP2_MCASP_ACLKR_PIN", "Input clock"}, {176, 14, "DEV_MCASP2_MCASP_AHCLKX_POUT", "Output clock"}, {176, 15, "DEV_MCASP2_MCASP_AHCLKX_PIN", "Input muxed clock"}, {176, 16, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {176, 17, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {176, 18, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {176, 19, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {176, 20, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {176, 21, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {176, 22, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {176, 23, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {176, 24, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {176, 25, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {176, 26, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {176, 27, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {176, 28, "DEV_MCASP2_MCASP_AHCLKR_POUT", "Output clock"}, {176, 29, "DEV_MCASP2_MCASP_AHCLKR_PIN", "Input muxed clock"}, {176, 30, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {176, 31, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {176, 32, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {176, 33, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {176, 34, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {176, 35, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {176, 36, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {176, 37, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {176, 38, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {176, 39, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {176, 40, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {176, 41, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {177, 0, "DEV_MCASP3_VBUSP_CLK", "Input clock"}, {177, 1, "DEV_MCASP3_AUX_CLK", "Input muxed clock"}, {177, 2, "DEV_MCASP3_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP3_AUX_CLK"}, {177, 3, "DEV_MCASP3_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP3_AUX_CLK"}, {177, 4, "DEV_MCASP3_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP3_AUX_CLK"}, {177, 6, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP3_AUX_CLK"}, {177, 7, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP3_AUX_CLK"}, {177, 8, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP3_AUX_CLK"}, {177, 9, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP3_AUX_CLK"}, {177, 10, "DEV_MCASP3_MCASP_ACLKX_POUT", "Output clock"}, {177, 11, "DEV_MCASP3_MCASP_ACLKX_PIN", "Input clock"}, {177, 12, "DEV_MCASP3_MCASP_ACLKR_POUT", "Output clock"}, {177, 13, "DEV_MCASP3_MCASP_ACLKR_PIN", "Input clock"}, {177, 14, "DEV_MCASP3_MCASP_AHCLKX_POUT", "Output clock"}, {177, 15, "DEV_MCASP3_MCASP_AHCLKX_PIN", "Input muxed clock"}, {177, 16, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, {177, 17, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, {177, 18, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, {177, 19, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, {177, 20, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, {177, 21, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, {177, 22, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, {177, 23, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, {177, 24, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, {177, 25, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, {177, 26, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, {177, 27, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, {177, 28, "DEV_MCASP3_MCASP_AHCLKR_POUT", "Output clock"}, {177, 29, "DEV_MCASP3_MCASP_AHCLKR_PIN", "Input muxed clock"}, {177, 30, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, {177, 31, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, {177, 32, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, {177, 33, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, {177, 34, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, {177, 35, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, {177, 36, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, {177, 37, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, {177, 38, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, {177, 39, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, {177, 40, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, {177, 41, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, {178, 0, "DEV_MCASP4_VBUSP_CLK", "Input clock"}, {178, 1, "DEV_MCASP4_AUX_CLK", "Input muxed clock"}, {178, 2, "DEV_MCASP4_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP4_AUX_CLK"}, {178, 3, "DEV_MCASP4_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP4_AUX_CLK"}, {178, 4, "DEV_MCASP4_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP4_AUX_CLK"}, {178, 6, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP4_AUX_CLK"}, {178, 7, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP4_AUX_CLK"}, {178, 8, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP4_AUX_CLK"}, {178, 9, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP4_AUX_CLK"}, {178, 10, "DEV_MCASP4_MCASP_ACLKX_POUT", "Output clock"}, {178, 11, "DEV_MCASP4_MCASP_ACLKX_PIN", "Input clock"}, {178, 12, "DEV_MCASP4_MCASP_ACLKR_POUT", "Output clock"}, {178, 13, "DEV_MCASP4_MCASP_ACLKR_PIN", "Input clock"}, {178, 14, "DEV_MCASP4_MCASP_AHCLKX_POUT", "Output clock"}, {178, 15, "DEV_MCASP4_MCASP_AHCLKX_PIN", "Input muxed clock"}, {178, 16, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, {178, 17, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, {178, 18, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, {178, 19, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, {178, 20, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, {178, 21, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, {178, 22, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, {178, 23, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, {178, 24, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, {178, 25, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, {178, 26, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, {178, 27, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, {178, 28, "DEV_MCASP4_MCASP_AHCLKR_POUT", "Output clock"}, {178, 29, "DEV_MCASP4_MCASP_AHCLKR_PIN", "Input muxed clock"}, {178, 30, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, {178, 31, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, {178, 32, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, {178, 33, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, {178, 34, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, {178, 35, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, {178, 36, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, {178, 37, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, {178, 38, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, {178, 39, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, {178, 40, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, {178, 41, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, {179, 0, "DEV_MCASP5_VBUSP_CLK", "Input clock"}, {179, 1, "DEV_MCASP5_AUX_CLK", "Input muxed clock"}, {179, 2, "DEV_MCASP5_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP5_AUX_CLK"}, {179, 3, "DEV_MCASP5_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP5_AUX_CLK"}, {179, 4, "DEV_MCASP5_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP5_AUX_CLK"}, {179, 6, "DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP5_AUX_CLK"}, {179, 7, "DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP5_AUX_CLK"}, {179, 8, "DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP5_AUX_CLK"}, {179, 9, "DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP5_AUX_CLK"}, {179, 10, "DEV_MCASP5_MCASP_ACLKX_POUT", "Output clock"}, {179, 11, "DEV_MCASP5_MCASP_ACLKX_PIN", "Input clock"}, {179, 12, "DEV_MCASP5_MCASP_ACLKR_POUT", "Output clock"}, {179, 13, "DEV_MCASP5_MCASP_ACLKR_PIN", "Input clock"}, {179, 14, "DEV_MCASP5_MCASP_AHCLKX_POUT", "Output clock"}, {179, 15, "DEV_MCASP5_MCASP_AHCLKX_PIN", "Input muxed clock"}, {179, 16, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"}, {179, 17, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"}, {179, 18, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"}, {179, 19, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"}, {179, 20, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"}, {179, 21, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"}, {179, 22, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"}, {179, 23, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"}, {179, 24, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"}, {179, 25, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"}, {179, 26, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"}, {179, 27, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"}, {179, 28, "DEV_MCASP5_MCASP_AHCLKR_POUT", "Output clock"}, {179, 29, "DEV_MCASP5_MCASP_AHCLKR_PIN", "Input muxed clock"}, {179, 30, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"}, {179, 31, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"}, {179, 32, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"}, {179, 33, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"}, {179, 34, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"}, {179, 35, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"}, {179, 36, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"}, {179, 37, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"}, {179, 38, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"}, {179, 39, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"}, {179, 40, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"}, {179, 41, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"}, {180, 0, "DEV_MCASP6_VBUSP_CLK", "Input clock"}, {180, 1, "DEV_MCASP6_AUX_CLK", "Input muxed clock"}, {180, 2, "DEV_MCASP6_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP6_AUX_CLK"}, {180, 3, "DEV_MCASP6_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP6_AUX_CLK"}, {180, 4, "DEV_MCASP6_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP6_AUX_CLK"}, {180, 6, "DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP6_AUX_CLK"}, {180, 7, "DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP6_AUX_CLK"}, {180, 8, "DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP6_AUX_CLK"}, {180, 9, "DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP6_AUX_CLK"}, {180, 10, "DEV_MCASP6_MCASP_ACLKX_POUT", "Output clock"}, {180, 11, "DEV_MCASP6_MCASP_ACLKX_PIN", "Input clock"}, {180, 12, "DEV_MCASP6_MCASP_ACLKR_POUT", "Output clock"}, {180, 13, "DEV_MCASP6_MCASP_ACLKR_PIN", "Input clock"}, {180, 14, "DEV_MCASP6_MCASP_AHCLKX_POUT", "Output clock"}, {180, 15, "DEV_MCASP6_MCASP_AHCLKX_PIN", "Input muxed clock"}, {180, 16, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"}, {180, 17, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"}, {180, 18, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"}, {180, 19, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"}, {180, 20, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"}, {180, 21, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"}, {180, 22, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"}, {180, 23, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"}, {180, 24, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"}, {180, 25, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"}, {180, 26, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"}, {180, 27, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"}, {180, 28, "DEV_MCASP6_MCASP_AHCLKR_POUT", "Output clock"}, {180, 29, "DEV_MCASP6_MCASP_AHCLKR_PIN", "Input muxed clock"}, {180, 30, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"}, {180, 31, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"}, {180, 32, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"}, {180, 33, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"}, {180, 34, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"}, {180, 35, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"}, {180, 36, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"}, {180, 37, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"}, {180, 38, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"}, {180, 39, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"}, {180, 40, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"}, {180, 41, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"}, {181, 0, "DEV_MCASP7_VBUSP_CLK", "Input clock"}, {181, 1, "DEV_MCASP7_AUX_CLK", "Input muxed clock"}, {181, 2, "DEV_MCASP7_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP7_AUX_CLK"}, {181, 3, "DEV_MCASP7_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP7_AUX_CLK"}, {181, 4, "DEV_MCASP7_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP7_AUX_CLK"}, {181, 6, "DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP7_AUX_CLK"}, {181, 7, "DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP7_AUX_CLK"}, {181, 8, "DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP7_AUX_CLK"}, {181, 9, "DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP7_AUX_CLK"}, {181, 10, "DEV_MCASP7_MCASP_ACLKX_POUT", "Output clock"}, {181, 11, "DEV_MCASP7_MCASP_ACLKX_PIN", "Input clock"}, {181, 12, "DEV_MCASP7_MCASP_ACLKR_POUT", "Output clock"}, {181, 13, "DEV_MCASP7_MCASP_ACLKR_PIN", "Input clock"}, {181, 14, "DEV_MCASP7_MCASP_AHCLKX_POUT", "Output clock"}, {181, 15, "DEV_MCASP7_MCASP_AHCLKX_PIN", "Input muxed clock"}, {181, 16, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"}, {181, 17, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"}, {181, 18, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"}, {181, 19, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"}, {181, 20, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"}, {181, 21, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"}, {181, 22, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"}, {181, 23, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"}, {181, 24, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"}, {181, 25, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"}, {181, 26, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"}, {181, 27, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"}, {181, 28, "DEV_MCASP7_MCASP_AHCLKR_POUT", "Output clock"}, {181, 29, "DEV_MCASP7_MCASP_AHCLKR_PIN", "Input muxed clock"}, {181, 30, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"}, {181, 31, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"}, {181, 32, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"}, {181, 33, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"}, {181, 34, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"}, {181, 35, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"}, {181, 36, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"}, {181, 37, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"}, {181, 38, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"}, {181, 39, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"}, {181, 40, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"}, {181, 41, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"}, {182, 0, "DEV_MCASP8_VBUSP_CLK", "Input clock"}, {182, 1, "DEV_MCASP8_AUX_CLK", "Input muxed clock"}, {182, 2, "DEV_MCASP8_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP8_AUX_CLK"}, {182, 3, "DEV_MCASP8_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP8_AUX_CLK"}, {182, 4, "DEV_MCASP8_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP8_AUX_CLK"}, {182, 6, "DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP8_AUX_CLK"}, {182, 7, "DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP8_AUX_CLK"}, {182, 8, "DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP8_AUX_CLK"}, {182, 9, "DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP8_AUX_CLK"}, {182, 10, "DEV_MCASP8_MCASP_ACLKX_POUT", "Output clock"}, {182, 11, "DEV_MCASP8_MCASP_ACLKX_PIN", "Input clock"}, {182, 12, "DEV_MCASP8_MCASP_ACLKR_POUT", "Output clock"}, {182, 13, "DEV_MCASP8_MCASP_ACLKR_PIN", "Input clock"}, {182, 14, "DEV_MCASP8_MCASP_AHCLKX_POUT", "Output clock"}, {182, 15, "DEV_MCASP8_MCASP_AHCLKX_PIN", "Input muxed clock"}, {182, 16, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"}, {182, 17, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"}, {182, 18, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"}, {182, 19, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"}, {182, 20, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"}, {182, 21, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"}, {182, 22, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"}, {182, 23, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"}, {182, 24, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"}, {182, 25, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"}, {182, 26, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"}, {182, 27, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"}, {182, 28, "DEV_MCASP8_MCASP_AHCLKR_POUT", "Output clock"}, {182, 29, "DEV_MCASP8_MCASP_AHCLKR_PIN", "Input muxed clock"}, {182, 30, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"}, {182, 31, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"}, {182, 32, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"}, {182, 33, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"}, {182, 34, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"}, {182, 35, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"}, {182, 36, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"}, {182, 37, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"}, {182, 38, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"}, {182, 39, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"}, {182, 40, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"}, {182, 41, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"}, {183, 0, "DEV_MCASP9_VBUSP_CLK", "Input clock"}, {183, 1, "DEV_MCASP9_AUX_CLK", "Input muxed clock"}, {183, 2, "DEV_MCASP9_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP9_AUX_CLK"}, {183, 3, "DEV_MCASP9_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP9_AUX_CLK"}, {183, 4, "DEV_MCASP9_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP9_AUX_CLK"}, {183, 6, "DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP9_AUX_CLK"}, {183, 7, "DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP9_AUX_CLK"}, {183, 8, "DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP9_AUX_CLK"}, {183, 9, "DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP9_AUX_CLK"}, {183, 10, "DEV_MCASP9_MCASP_ACLKX_POUT", "Output clock"}, {183, 11, "DEV_MCASP9_MCASP_ACLKX_PIN", "Input clock"}, {183, 12, "DEV_MCASP9_MCASP_ACLKR_POUT", "Output clock"}, {183, 13, "DEV_MCASP9_MCASP_ACLKR_PIN", "Input clock"}, {183, 14, "DEV_MCASP9_MCASP_AHCLKX_POUT", "Output clock"}, {183, 15, "DEV_MCASP9_MCASP_AHCLKX_PIN", "Input muxed clock"}, {183, 16, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"}, {183, 17, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"}, {183, 18, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"}, {183, 19, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"}, {183, 20, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"}, {183, 21, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"}, {183, 22, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"}, {183, 23, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"}, {183, 24, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"}, {183, 25, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"}, {183, 26, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"}, {183, 27, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"}, {183, 28, "DEV_MCASP9_MCASP_AHCLKR_POUT", "Output clock"}, {183, 29, "DEV_MCASP9_MCASP_AHCLKR_PIN", "Input muxed clock"}, {183, 30, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"}, {183, 31, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"}, {183, 32, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"}, {183, 33, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"}, {183, 34, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"}, {183, 35, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"}, {183, 36, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"}, {183, 37, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"}, {183, 38, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"}, {183, 39, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"}, {183, 40, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"}, {183, 41, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"}, {266, 0, "DEV_MCSPI0_VBUSP_CLK", "Input clock"}, {266, 1, "DEV_MCSPI0_CLKSPIREF_CLK", "Input clock"}, {266, 2, "DEV_MCSPI0_IO_CLKSPIO_CLK", "Output clock"}, {267, 0, "DEV_MCSPI1_VBUSP_CLK", "Input clock"}, {267, 1, "DEV_MCSPI1_CLKSPIREF_CLK", "Input clock"}, {267, 2, "DEV_MCSPI1_IO_CLKSPIO_CLK", "Output clock"}, {268, 0, "DEV_MCSPI2_VBUSP_CLK", "Input clock"}, {268, 1, "DEV_MCSPI2_CLKSPIREF_CLK", "Input clock"}, {268, 2, "DEV_MCSPI2_IO_CLKSPIO_CLK", "Output clock"}, {269, 0, "DEV_MCSPI3_VBUSP_CLK", "Input clock"}, {269, 1, "DEV_MCSPI3_CLKSPIREF_CLK", "Input clock"}, {269, 2, "DEV_MCSPI3_IO_CLKSPII_CLK", "Input muxed clock"}, {269, 3, "DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI3_IO_CLKSPII_CLK"}, {269, 4, "DEV_MCSPI3_IO_CLKSPIO_CLK", "Output clock"}, {270, 0, "DEV_MCSPI4_VBUSP_CLK", "Input clock"}, {270, 1, "DEV_MCSPI4_CLKSPIREF_CLK", "Input clock"}, {270, 2, "DEV_MCSPI4_IO_CLKSPII_CLK", "Input clock"}, {270, 3, "DEV_MCSPI4_IO_CLKSPIO_CLK", "Output clock"}, {271, 0, "DEV_MCSPI5_VBUSP_CLK", "Input clock"}, {271, 1, "DEV_MCSPI5_CLKSPIREF_CLK", "Input clock"}, {271, 2, "DEV_MCSPI5_IO_CLKSPIO_CLK", "Output clock"}, {272, 0, "DEV_MCSPI6_VBUSP_CLK", "Input clock"}, {272, 1, "DEV_MCSPI6_CLKSPIREF_CLK", "Input clock"}, {272, 2, "DEV_MCSPI6_IO_CLKSPIO_CLK", "Output clock"}, {273, 0, "DEV_MCSPI7_VBUSP_CLK", "Input clock"}, {273, 1, "DEV_MCSPI7_CLKSPIREF_CLK", "Input clock"}, {273, 2, "DEV_MCSPI7_IO_CLKSPIO_CLK", "Output clock"}, {0, 0, "DEV_MCU_ADC12_16FFC0_SYS_CLK", "Input clock"}, {0, 1, "DEV_MCU_ADC12_16FFC0_ADC_CLK", "Input muxed clock"}, {0, 2, "DEV_MCU_ADC12_16FFC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_ADC12_16FFC0_ADC_CLK"}, {0, 3, "DEV_MCU_ADC12_16FFC0_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC12_16FFC0_ADC_CLK"}, {0, 4, "DEV_MCU_ADC12_16FFC0_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC12_16FFC0_ADC_CLK"}, {0, 5, "DEV_MCU_ADC12_16FFC0_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC12_16FFC0_ADC_CLK"}, {0, 6, "DEV_MCU_ADC12_16FFC0_VBUS_CLK", "Input clock"}, {1, 0, "DEV_MCU_ADC12_16FFC1_SYS_CLK", "Input clock"}, {1, 1, "DEV_MCU_ADC12_16FFC1_ADC_CLK", "Input muxed clock"}, {1, 2, "DEV_MCU_ADC12_16FFC1_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_ADC12_16FFC1_ADC_CLK"}, {1, 3, "DEV_MCU_ADC12_16FFC1_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC12_16FFC1_ADC_CLK"}, {1, 4, "DEV_MCU_ADC12_16FFC1_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC12_16FFC1_ADC_CLK"}, {1, 5, "DEV_MCU_ADC12_16FFC1_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC12_16FFC1_ADC_CLK"}, {1, 6, "DEV_MCU_ADC12_16FFC1_VBUS_CLK", "Input clock"}, {18, 0, "DEV_MCU_CPSW0_RGMII1_RXC_I", "Input clock"}, {18, 1, "DEV_MCU_CPSW0_RGMII_MHZ_250_CLK", "Input clock"}, {18, 2, "DEV_MCU_CPSW0_CPTS_RFT_CLK", "Input muxed clock"}, {18, 3, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {18, 4, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {18, 5, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {18, 6, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {18, 7, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {18, 8, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {18, 9, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {18, 10, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {18, 11, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {18, 12, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {18, 13, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {18, 14, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {18, 15, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {18, 16, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {18, 17, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {18, 18, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {18, 19, "DEV_MCU_CPSW0_GMII_RFT_CLK", "Input clock"}, {18, 20, "DEV_MCU_CPSW0_RMII_MHZ_50_CLK", "Input clock"}, {18, 21, "DEV_MCU_CPSW0_RGMII_MHZ_50_CLK", "Input clock"}, {18, 22, "DEV_MCU_CPSW0_CPPI_CLK_CLK", "Input clock"}, {18, 23, "DEV_MCU_CPSW0_RGMII_MHZ_5_CLK", "Input clock"}, {18, 24, "DEV_MCU_CPSW0_GMII1_MR_CLK", "Input clock"}, {18, 25, "DEV_MCU_CPSW0_GMII1_MT_CLK", "Input clock"}, {18, 26, "DEV_MCU_CPSW0_RGMII1_TXC_I", "Input clock"}, {18, 27, "DEV_MCU_CPSW0_RGMII1_TXC_O", "Output clock"}, {18, 28, "DEV_MCU_CPSW0_CPTS_GENF0", "Output clock"}, {18, 29, "DEV_MCU_CPSW0_MDIO_MDCLK_O", "Output clock"}, {24, 0, "DEV_MCU_CPT2_AGGR0_VCLK_CLK", "Input clock"}, {44, 0, "DEV_MCU_DCC0_DCC_INPUT10_CLK", "Input clock"}, {44, 1, "DEV_MCU_DCC0_DCC_INPUT01_CLK", "Input clock"}, {44, 2, "DEV_MCU_DCC0_DCC_CLKSRC2_CLK", "Input clock"}, {44, 3, "DEV_MCU_DCC0_DCC_CLKSRC7_CLK", "Input clock"}, {44, 4, "DEV_MCU_DCC0_DCC_CLKSRC0_CLK", "Input clock"}, {44, 5, "DEV_MCU_DCC0_VBUS_CLK", "Input clock"}, {44, 6, "DEV_MCU_DCC0_DCC_CLKSRC4_CLK", "Input clock"}, {44, 7, "DEV_MCU_DCC0_DCC_CLKSRC1_CLK", "Input clock"}, {44, 8, "DEV_MCU_DCC0_DCC_CLKSRC3_CLK", "Input clock"}, {44, 9, "DEV_MCU_DCC0_DCC_INPUT00_CLK", "Input clock"}, {44, 10, "DEV_MCU_DCC0_DCC_CLKSRC5_CLK", "Input clock"}, {44, 11, "DEV_MCU_DCC0_DCC_CLKSRC6_CLK", "Input clock"}, {44, 12, "DEV_MCU_DCC0_DCC_INPUT02_CLK", "Input clock"}, {45, 0, "DEV_MCU_DCC1_DCC_INPUT10_CLK", "Input clock"}, {45, 1, "DEV_MCU_DCC1_DCC_INPUT01_CLK", "Input clock"}, {45, 2, "DEV_MCU_DCC1_DCC_CLKSRC2_CLK", "Input clock"}, {45, 3, "DEV_MCU_DCC1_DCC_CLKSRC7_CLK", "Input clock"}, {45, 4, "DEV_MCU_DCC1_DCC_CLKSRC0_CLK", "Input clock"}, {45, 5, "DEV_MCU_DCC1_VBUS_CLK", "Input clock"}, {45, 6, "DEV_MCU_DCC1_DCC_CLKSRC4_CLK", "Input clock"}, {45, 7, "DEV_MCU_DCC1_DCC_CLKSRC1_CLK", "Input clock"}, {45, 8, "DEV_MCU_DCC1_DCC_CLKSRC3_CLK", "Input clock"}, {45, 9, "DEV_MCU_DCC1_DCC_INPUT00_CLK", "Input clock"}, {45, 10, "DEV_MCU_DCC1_DCC_CLKSRC5_CLK", "Input clock"}, {45, 11, "DEV_MCU_DCC1_DCC_CLKSRC6_CLK", "Input clock"}, {45, 12, "DEV_MCU_DCC1_DCC_INPUT02_CLK", "Input clock"}, {46, 0, "DEV_MCU_DCC2_DCC_INPUT10_CLK", "Input clock"}, {46, 1, "DEV_MCU_DCC2_DCC_INPUT01_CLK", "Input clock"}, {46, 2, "DEV_MCU_DCC2_DCC_CLKSRC7_CLK", "Input clock"}, {46, 3, "DEV_MCU_DCC2_DCC_CLKSRC0_CLK", "Input clock"}, {46, 4, "DEV_MCU_DCC2_VBUS_CLK", "Input clock"}, {46, 5, "DEV_MCU_DCC2_DCC_CLKSRC4_CLK", "Input clock"}, {46, 6, "DEV_MCU_DCC2_DCC_CLKSRC1_CLK", "Input clock"}, {46, 7, "DEV_MCU_DCC2_DCC_CLKSRC3_CLK", "Input clock"}, {46, 8, "DEV_MCU_DCC2_DCC_INPUT00_CLK", "Input clock"}, {46, 9, "DEV_MCU_DCC2_DCC_CLKSRC6_CLK", "Input clock"}, {46, 10, "DEV_MCU_DCC2_DCC_INPUT02_CLK", "Input clock"}, {98, 0, "DEV_MCU_ESM0_CLK", "Input clock"}, {101, 0, "DEV_MCU_FSS0_FSAS_0_GCLK", "Input clock"}, {102, 0, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_INV_CLK", "Input clock"}, {102, 1, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_INV_CLK", "Input clock"}, {102, 2, "DEV_MCU_FSS0_HYPERBUS1P0_0_CBA_CLK", "Input clock"}, {102, 3, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_CLK", "Input clock"}, {102, 4, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_CLK", "Input clock"}, {102, 5, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_N", "Output clock"}, {102, 6, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_P", "Output clock"}, {103, 0, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK", "Input muxed clock"}, {103, 1, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK"}, {103, 2, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK"}, {103, 3, "DEV_MCU_FSS0_OSPI_0_OSPI_HCLK_CLK", "Input clock"}, {103, 4, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK", "Input muxed clock"}, {103, 5, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI0_DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK"}, {103, 6, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_OSPI_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK"}, {103, 7, "DEV_MCU_FSS0_OSPI_0_OSPI_PCLK_CLK", "Input clock"}, {103, 8, "DEV_MCU_FSS0_OSPI_0_OSPI_DQS_CLK", "Input clock"}, {103, 9, "DEV_MCU_FSS0_OSPI_0_OSPI_OCLK_CLK", "Output clock"}, {104, 0, "DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK", "Input muxed clock"}, {104, 1, "DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK"}, {104, 2, "DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK"}, {104, 3, "DEV_MCU_FSS0_OSPI_1_OSPI_HCLK_CLK", "Input clock"}, {104, 4, "DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK", "Input muxed clock"}, {104, 5, "DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI1_DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK"}, {104, 6, "DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_1_OSPI_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK"}, {104, 7, "DEV_MCU_FSS0_OSPI_1_OSPI_PCLK_CLK", "Input clock"}, {104, 8, "DEV_MCU_FSS0_OSPI_1_OSPI_DQS_CLK", "Input clock"}, {104, 9, "DEV_MCU_FSS0_OSPI_1_OSPI_OCLK_CLK", "Output clock"}, {194, 0, "DEV_MCU_I2C0_PISYS_CLK", "Input clock"}, {194, 1, "DEV_MCU_I2C0_PISCL", "Input clock"}, {194, 2, "DEV_MCU_I2C0_CLK", "Input clock"}, {194, 3, "DEV_MCU_I2C0_PORSCL", "Output clock"}, {195, 0, "DEV_MCU_I2C1_PISYS_CLK", "Input clock"}, {195, 1, "DEV_MCU_I2C1_PISCL", "Input clock"}, {195, 2, "DEV_MCU_I2C1_CLK", "Input clock"}, {195, 3, "DEV_MCU_I2C1_PORSCL", "Output clock"}, {117, 0, "DEV_MCU_I3C0_I3C_PCLK_CLK", "Input clock"}, {117, 1, "DEV_MCU_I3C0_I3C_SCL_DI", "Input clock"}, {117, 2, "DEV_MCU_I3C0_I3C_SCLK_CLK", "Input clock"}, {117, 3, "DEV_MCU_I3C0_I3C_SCL_DO", "Output clock"}, {118, 0, "DEV_MCU_I3C1_I3C_PCLK_CLK", "Input clock"}, {118, 1, "DEV_MCU_I3C1_I3C_SCL_DI", "Input clock"}, {118, 2, "DEV_MCU_I3C1_I3C_SCLK_CLK", "Input clock"}, {118, 3, "DEV_MCU_I3C1_I3C_SCL_DO", "Output clock"}, {172, 0, "DEV_MCU_MCAN0_MCANSS_HCLK_CLK", "Input clock"}, {172, 1, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"}, {172, 2, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, {172, 3, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, {172, 4, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, {172, 5, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, {173, 0, "DEV_MCU_MCAN1_MCANSS_HCLK_CLK", "Input clock"}, {173, 1, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"}, {173, 2, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, {173, 3, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, {173, 4, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, {173, 5, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, {274, 0, "DEV_MCU_MCSPI0_VBUSP_CLK", "Input clock"}, {274, 1, "DEV_MCU_MCSPI0_CLKSPIREF_CLK", "Input clock"}, {274, 2, "DEV_MCU_MCSPI0_IO_CLKSPIO_CLK", "Output clock"}, {275, 0, "DEV_MCU_MCSPI1_VBUSP_CLK", "Input clock"}, {275, 1, "DEV_MCU_MCSPI1_CLKSPIREF_CLK", "Input clock"}, {275, 2, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK", "Input muxed clock"}, {275, 3, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK"}, {275, 4, "DEV_MCU_MCSPI1_IO_CLKSPIO_CLK", "Output clock"}, {276, 0, "DEV_MCU_MCSPI2_VBUSP_CLK", "Input clock"}, {276, 1, "DEV_MCU_MCSPI2_CLKSPIREF_CLK", "Input clock"}, {276, 2, "DEV_MCU_MCSPI2_IO_CLKSPII_CLK", "Input clock"}, {276, 3, "DEV_MCU_MCSPI2_IO_CLKSPIO_CLK", "Output clock"}, {237, 0, "DEV_MCU_NAVSS0_INTR_0_INTR_CLK", "Input clock"}, {238, 0, "DEV_MCU_NAVSS0_MCRC_0_CLK", "Input clock"}, {302, 0, "DEV_MCU_NAVSS0_MODSS_VD2CLK", "Input clock"}, {234, 0, "DEV_MCU_NAVSS0_PROXY0_CLK_CLK", "Input clock"}, {235, 0, "DEV_MCU_NAVSS0_RINGACC0_SYS_CLK", "Input clock"}, {236, 0, "DEV_MCU_NAVSS0_UDMAP_0_SYS_CLK", "Input clock"}, {303, 0, "DEV_MCU_NAVSS0_UDMASS_VD2CLK", "Input clock"}, {233, 0, "DEV_MCU_NAVSS0_UDMASS_INTA_0_SYS_CLK", "Input clock"}, {250, 0, "DEV_MCU_R5FSS0_CORE0_CPU_CLK", "Input muxed clock"}, {250, 1, "DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK"}, {250, 2, "DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3", "Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK"}, {250, 3, "DEV_MCU_R5FSS0_CORE0_INTERFACE_CLK", "Input clock"}, {250, 4, "DEV_MCU_R5FSS0_CORE0_INTERFACE_PHASE", "Input clock"}, {251, 0, "DEV_MCU_R5FSS0_CORE1_CPU_CLK", "Input muxed clock"}, {251, 1, "DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK"}, {251, 2, "DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3", "Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK"}, {251, 3, "DEV_MCU_R5FSS0_CORE1_INTERFACE_CLK", "Input clock"}, {251, 4, "DEV_MCU_R5FSS0_CORE1_INTERFACE_PHASE", "Input clock"}, {262, 0, "DEV_MCU_RTI0_VBUSP_CLK", "Input clock"}, {262, 1, "DEV_MCU_RTI0_RTI_CLK", "Input muxed clock"}, {262, 2, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, {262, 3, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, {262, 4, "DEV_MCU_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, {262, 5, "DEV_MCU_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, {263, 0, "DEV_MCU_RTI1_VBUSP_CLK", "Input clock"}, {263, 1, "DEV_MCU_RTI1_RTI_CLK", "Input muxed clock"}, {263, 2, "DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"}, {263, 3, "DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"}, {263, 4, "DEV_MCU_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"}, {263, 5, "DEV_MCU_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"}, {265, 0, "DEV_MCU_SA2_UL0_X2_CLK", "Input clock"}, {265, 1, "DEV_MCU_SA2_UL0_PKA_IN_CLK", "Input clock"}, {265, 2, "DEV_MCU_SA2_UL0_X1_CLK", "Input clock"}, {35, 0, "DEV_MCU_TIMER0_TIMER_HCLK_CLK", "Input clock"}, {35, 1, "DEV_MCU_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"}, {35, 2, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 3, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 4, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 5, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 6, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 7, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 8, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 9, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 10, "DEV_MCU_TIMER0_TIMER_PWM", "Output clock"}, {71, 0, "DEV_MCU_TIMER1_TIMER_HCLK_CLK", "Input clock"}, {71, 1, "DEV_MCU_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"}, {71, 2, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT1", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, {71, 3, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, {322, 0, "DEV_MCU_TIMER1_CLKSEL_VD_CLK", "Input muxed clock"}, {322, 1, "DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK"}, {322, 2, "DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK"}, {322, 3, "DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK"}, {322, 4, "DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK"}, {322, 5, "DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK"}, {322, 6, "DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK"}, {322, 7, "DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK"}, {322, 8, "DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK"}, {72, 0, "DEV_MCU_TIMER2_TIMER_HCLK_CLK", "Input clock"}, {72, 1, "DEV_MCU_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"}, {72, 2, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {72, 3, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {72, 4, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {72, 5, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {72, 6, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {72, 7, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {72, 8, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {72, 9, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {72, 10, "DEV_MCU_TIMER2_TIMER_PWM", "Output clock"}, {73, 0, "DEV_MCU_TIMER3_TIMER_HCLK_CLK", "Input clock"}, {73, 1, "DEV_MCU_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"}, {73, 2, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT3", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, {73, 3, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, {323, 0, "DEV_MCU_TIMER3_CLKSEL_VD_CLK", "Input muxed clock"}, {323, 1, "DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK"}, {323, 2, "DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK"}, {323, 3, "DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK"}, {323, 4, "DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK"}, {323, 5, "DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK"}, {323, 6, "DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK"}, {323, 7, "DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK"}, {323, 8, "DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK"}, {74, 0, "DEV_MCU_TIMER4_TIMER_HCLK_CLK", "Input clock"}, {74, 1, "DEV_MCU_TIMER4_TIMER_TCLK_CLK", "Input muxed clock"}, {74, 2, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, {74, 3, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, {74, 4, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, {74, 5, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, {74, 6, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, {74, 7, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, {74, 8, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, {74, 9, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, {74, 10, "DEV_MCU_TIMER4_TIMER_PWM", "Output clock"}, {75, 0, "DEV_MCU_TIMER5_TIMER_HCLK_CLK", "Input clock"}, {75, 1, "DEV_MCU_TIMER5_TIMER_TCLK_CLK", "Input muxed clock"}, {75, 2, "DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT5", "Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK"}, {75, 3, "DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_4_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK"}, {324, 0, "DEV_MCU_TIMER5_CLKSEL_VD_CLK", "Input muxed clock"}, {324, 1, "DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK"}, {324, 2, "DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK"}, {324, 3, "DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK"}, {324, 4, "DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK"}, {324, 5, "DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK"}, {324, 6, "DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK"}, {324, 7, "DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK"}, {324, 8, "DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK"}, {76, 0, "DEV_MCU_TIMER6_TIMER_HCLK_CLK", "Input clock"}, {76, 1, "DEV_MCU_TIMER6_TIMER_TCLK_CLK", "Input muxed clock"}, {76, 2, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, {76, 3, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, {76, 4, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, {76, 5, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, {76, 6, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, {76, 7, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, {76, 8, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, {76, 9, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, {76, 10, "DEV_MCU_TIMER6_TIMER_PWM", "Output clock"}, {77, 0, "DEV_MCU_TIMER7_TIMER_HCLK_CLK", "Input clock"}, {77, 1, "DEV_MCU_TIMER7_TIMER_TCLK_CLK", "Input muxed clock"}, {77, 2, "DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT7", "Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK"}, {77, 3, "DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_6_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK"}, {325, 0, "DEV_MCU_TIMER7_CLKSEL_VD_CLK", "Input muxed clock"}, {325, 1, "DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK"}, {325, 2, "DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK"}, {325, 3, "DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK"}, {325, 4, "DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK"}, {325, 5, "DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK"}, {325, 6, "DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK"}, {325, 7, "DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK"}, {325, 8, "DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK"}, {78, 0, "DEV_MCU_TIMER8_TIMER_HCLK_CLK", "Input clock"}, {78, 1, "DEV_MCU_TIMER8_TIMER_TCLK_CLK", "Input muxed clock"}, {78, 2, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, {78, 3, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, {78, 4, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, {78, 5, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, {78, 6, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, {78, 7, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, {78, 8, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, {78, 9, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, {78, 10, "DEV_MCU_TIMER8_TIMER_PWM", "Output clock"}, {79, 0, "DEV_MCU_TIMER9_TIMER_HCLK_CLK", "Input clock"}, {79, 1, "DEV_MCU_TIMER9_TIMER_TCLK_CLK", "Input muxed clock"}, {79, 2, "DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT9", "Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK"}, {79, 3, "DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_8_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK"}, {326, 0, "DEV_MCU_TIMER9_CLKSEL_VD_CLK", "Input muxed clock"}, {326, 1, "DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK"}, {326, 2, "DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK"}, {326, 3, "DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK"}, {326, 4, "DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK"}, {326, 5, "DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK"}, {326, 6, "DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK"}, {326, 7, "DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK"}, {326, 8, "DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK"}, {149, 0, "DEV_MCU_UART0_FCLK_CLK", "Input muxed clock"}, {149, 1, "DEV_MCU_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_UART0_FCLK_CLK"}, {149, 2, "DEV_MCU_UART0_FCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT5_CLK", "Parent input clock option to DEV_MCU_UART0_FCLK_CLK"}, {149, 3, "DEV_MCU_UART0_VBUSP_CLK", "Input clock"}, {186, 0, "DEV_MLB0_MLBSS_MLB_CLK", "Input clock"}, {186, 1, "DEV_MLB0_MLBSS_SCLK_CLK", "Input clock"}, {186, 2, "DEV_MLB0_MLBSS_HCLK_CLK", "Input clock"}, {186, 3, "DEV_MLB0_MLBSS_PCLK_CLK", "Input clock"}, {186, 4, "DEV_MLB0_MLBSS_AMLB_CLK", "Input clock"}, {91, 0, "DEV_MMCSD0_EMMCSS_VBUS_CLK", "Input clock"}, {91, 1, "DEV_MMCSD0_EMMCSS_XIN_CLK", "Input muxed clock"}, {91, 2, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"}, {91, 3, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"}, {91, 4, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"}, {91, 5, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"}, {91, 6, "DEV_MMCSD0_EMMCSS_IO_CLK", "Output clock"}, {92, 0, "DEV_MMCSD1_EMMCSDSS_XIN_CLK", "Input muxed clock"}, {92, 1, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"}, {92, 2, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"}, {92, 3, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"}, {92, 4, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"}, {92, 5, "DEV_MMCSD1_EMMCSDSS_VBUS_CLK", "Input clock"}, {92, 6, "DEV_MMCSD1_EMMCSDSS_IO_CLK_I", "Input clock"}, {92, 7, "DEV_MMCSD1_EMMCSDSS_IO_CLK_O", "Output clock"}, {93, 0, "DEV_MMCSD2_EMMCSDSS_XIN_CLK", "Input muxed clock"}, {93, 1, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"}, {93, 2, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"}, {93, 3, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"}, {93, 4, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"}, {93, 5, "DEV_MMCSD2_EMMCSDSS_VBUS_CLK", "Input clock"}, {93, 6, "DEV_MMCSD2_EMMCSDSS_IO_CLK_I", "Input clock"}, {93, 7, "DEV_MMCSD2_EMMCSDSS_IO_CLK_O", "Output clock"}, {199, 0, "DEV_NAVSS0_CPTS0_GENF3", "Output clock"}, {199, 1, "DEV_NAVSS0_CPTS0_GENF2", "Output clock"}, {201, 0, "DEV_NAVSS0_CPTS_0_VBUSP_GCLK", "Input clock"}, {201, 1, "DEV_NAVSS0_CPTS_0_RCLK", "Input muxed clock"}, {201, 2, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {201, 3, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {201, 4, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {201, 5, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {201, 6, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {201, 7, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {201, 8, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {201, 9, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {201, 10, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {201, 11, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {201, 12, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {201, 13, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {201, 14, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {201, 15, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {201, 16, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {201, 17, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {201, 18, "DEV_NAVSS0_CPTS_0_TS_GENF0", "Output clock"}, {201, 19, "DEV_NAVSS0_CPTS_0_TS_GENF1", "Output clock"}, {206, 0, "DEV_NAVSS0_DTI_0_CLK_CLK", "Input clock"}, {206, 1, "DEV_NAVSS0_DTI_0_EXT0_DTI_CLK_CLK", "Input clock"}, {206, 2, "DEV_NAVSS0_DTI_0_EXT3_DTI_CLK_CLK", "Input clock"}, {206, 3, "DEV_NAVSS0_DTI_0_EXT1_DTI_CLK_CLK", "Input clock"}, {206, 4, "DEV_NAVSS0_DTI_0_EXT2_DTI_CLK_CLK", "Input clock"}, {213, 0, "DEV_NAVSS0_INTR_ROUTER_0_INTR_CLK", "Input clock"}, {214, 0, "DEV_NAVSS0_MAILBOX_0_VCLK_CLK", "Input clock"}, {215, 0, "DEV_NAVSS0_MAILBOX_1_VCLK_CLK", "Input clock"}, {224, 0, "DEV_NAVSS0_MAILBOX_10_VCLK_CLK", "Input clock"}, {225, 0, "DEV_NAVSS0_MAILBOX_11_VCLK_CLK", "Input clock"}, {216, 0, "DEV_NAVSS0_MAILBOX_2_VCLK_CLK", "Input clock"}, {217, 0, "DEV_NAVSS0_MAILBOX_3_VCLK_CLK", "Input clock"}, {218, 0, "DEV_NAVSS0_MAILBOX_4_VCLK_CLK", "Input clock"}, {219, 0, "DEV_NAVSS0_MAILBOX_5_VCLK_CLK", "Input clock"}, {220, 0, "DEV_NAVSS0_MAILBOX_6_VCLK_CLK", "Input clock"}, {221, 0, "DEV_NAVSS0_MAILBOX_7_VCLK_CLK", "Input clock"}, {222, 0, "DEV_NAVSS0_MAILBOX_8_VCLK_CLK", "Input clock"}, {223, 0, "DEV_NAVSS0_MAILBOX_9_VCLK_CLK", "Input clock"}, {227, 0, "DEV_NAVSS0_MCRC_0_CLK", "Input clock"}, {299, 0, "DEV_NAVSS0_MODSS_VD2CLK", "Input clock"}, {207, 0, "DEV_NAVSS0_MODSS_INTAGGR_0_SYS_CLK", "Input clock"}, {208, 0, "DEV_NAVSS0_MODSS_INTAGGR_1_SYS_CLK", "Input clock"}, {210, 0, "DEV_NAVSS0_PROXY_0_CLK_CLK", "Input clock"}, {339, 0, "DEV_NAVSS0_PVU_0_CLK_CLK", "Input clock"}, {340, 0, "DEV_NAVSS0_PVU_1_CLK_CLK", "Input clock"}, {341, 0, "DEV_NAVSS0_PVU_2_CLK_CLK", "Input clock"}, {211, 0, "DEV_NAVSS0_RINGACC_0_SYS_CLK", "Input clock"}, {226, 0, "DEV_NAVSS0_SPINLOCK_0_CLK", "Input clock"}, {228, 0, "DEV_NAVSS0_TBU_0_CLK_CLK", "Input clock"}, {229, 0, "DEV_NAVSS0_TCU_0_CLK_CLK", "Input clock"}, {230, 0, "DEV_NAVSS0_TIMERMGR_0_VCLK_CLK", "Input clock"}, {230, 1, "DEV_NAVSS0_TIMERMGR_0_EON_TICK_EVT", "Input clock"}, {231, 0, "DEV_NAVSS0_TIMERMGR_1_VCLK_CLK", "Input clock"}, {231, 1, "DEV_NAVSS0_TIMERMGR_1_EON_TICK_EVT", "Input clock"}, {212, 0, "DEV_NAVSS0_UDMAP_0_SYS_CLK", "Input clock"}, {300, 0, "DEV_NAVSS0_UDMASS_VD2CLK", "Input clock"}, {209, 0, "DEV_NAVSS0_UDMASS_INTAGGR_0_SYS_CLK", "Input clock"}, {301, 0, "DEV_NAVSS0_VIRTSS_VD2CLK", "Input clock"}, {239, 0, "DEV_PCIE0_PCIE_LANE1_TXMCLK", "Input clock"}, {239, 1, "DEV_PCIE0_PCIE_CBA_CLK", "Input clock"}, {239, 2, "DEV_PCIE0_PCIE_LANE1_RXCLK", "Input clock"}, {239, 3, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK", "Input muxed clock"}, {239, 4, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {239, 5, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {239, 6, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {239, 7, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {239, 8, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {239, 9, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {239, 10, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {239, 11, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {239, 12, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {239, 13, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {239, 14, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {239, 15, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {239, 16, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {239, 17, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {239, 18, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {239, 19, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {239, 20, "DEV_PCIE0_PCIE_LANE1_TXFCLK", "Input clock"}, {239, 21, "DEV_PCIE0_PCIE_LANE1_REFCLK", "Input clock"}, {239, 22, "DEV_PCIE0_PCIE_LANE0_REFCLK", "Input clock"}, {239, 23, "DEV_PCIE0_PCIE_LANE0_TXMCLK", "Input clock"}, {239, 24, "DEV_PCIE0_PCIE_LANE0_TXFCLK", "Input clock"}, {239, 25, "DEV_PCIE0_PCIE_PM_CLK", "Input clock"}, {239, 26, "DEV_PCIE0_PCIE_LANE0_RXFCLK", "Input clock"}, {239, 27, "DEV_PCIE0_PCIE_LANE1_RXFCLK", "Input clock"}, {239, 28, "DEV_PCIE0_PCIE_LANE0_RXCLK", "Input clock"}, {239, 29, "DEV_PCIE0_PCIE_LANE1_TXCLK", "Output clock"}, {239, 30, "DEV_PCIE0_PCIE_LANE0_TXCLK", "Output clock"}, {240, 0, "DEV_PCIE1_PCIE_LANE1_TXMCLK", "Input clock"}, {240, 1, "DEV_PCIE1_PCIE_CBA_CLK", "Input clock"}, {240, 2, "DEV_PCIE1_PCIE_LANE1_RXCLK", "Input clock"}, {240, 3, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK", "Input muxed clock"}, {240, 4, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {240, 5, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {240, 6, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {240, 7, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {240, 8, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {240, 9, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {240, 10, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {240, 11, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {240, 12, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {240, 13, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {240, 14, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {240, 15, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {240, 16, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {240, 17, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {240, 18, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {240, 19, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {240, 20, "DEV_PCIE1_PCIE_LANE1_TXFCLK", "Input clock"}, {240, 21, "DEV_PCIE1_PCIE_LANE1_REFCLK", "Input clock"}, {240, 22, "DEV_PCIE1_PCIE_LANE0_REFCLK", "Input clock"}, {240, 23, "DEV_PCIE1_PCIE_LANE0_TXMCLK", "Input clock"}, {240, 24, "DEV_PCIE1_PCIE_LANE0_TXFCLK", "Input clock"}, {240, 25, "DEV_PCIE1_PCIE_PM_CLK", "Input clock"}, {240, 26, "DEV_PCIE1_PCIE_LANE0_RXFCLK", "Input clock"}, {240, 27, "DEV_PCIE1_PCIE_LANE1_RXFCLK", "Input clock"}, {240, 28, "DEV_PCIE1_PCIE_LANE0_RXCLK", "Input clock"}, {240, 29, "DEV_PCIE1_PCIE_LANE1_TXCLK", "Output clock"}, {240, 30, "DEV_PCIE1_PCIE_LANE0_TXCLK", "Output clock"}, {241, 0, "DEV_PCIE2_PCIE_LANE1_TXMCLK", "Input clock"}, {241, 1, "DEV_PCIE2_PCIE_CBA_CLK", "Input clock"}, {241, 2, "DEV_PCIE2_PCIE_LANE1_RXCLK", "Input clock"}, {241, 3, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK", "Input muxed clock"}, {241, 4, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, {241, 5, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, {241, 6, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, {241, 7, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, {241, 8, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, {241, 9, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, {241, 10, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, {241, 11, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, {241, 12, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, {241, 13, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, {241, 14, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, {241, 15, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, {241, 16, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, {241, 17, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, {241, 18, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, {241, 19, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, {241, 20, "DEV_PCIE2_PCIE_LANE1_TXFCLK", "Input clock"}, {241, 21, "DEV_PCIE2_PCIE_LANE1_REFCLK", "Input clock"}, {241, 22, "DEV_PCIE2_PCIE_LANE0_REFCLK", "Input clock"}, {241, 23, "DEV_PCIE2_PCIE_LANE0_TXMCLK", "Input clock"}, {241, 24, "DEV_PCIE2_PCIE_LANE0_TXFCLK", "Input clock"}, {241, 25, "DEV_PCIE2_PCIE_PM_CLK", "Input clock"}, {241, 26, "DEV_PCIE2_PCIE_LANE0_RXFCLK", "Input clock"}, {241, 27, "DEV_PCIE2_PCIE_LANE1_RXFCLK", "Input clock"}, {241, 28, "DEV_PCIE2_PCIE_LANE0_RXCLK", "Input clock"}, {241, 29, "DEV_PCIE2_PCIE_LANE1_TXCLK", "Output clock"}, {241, 30, "DEV_PCIE2_PCIE_LANE0_TXCLK", "Output clock"}, {242, 0, "DEV_PCIE3_PCIE_LANE1_TXMCLK", "Input clock"}, {242, 1, "DEV_PCIE3_PCIE_CBA_CLK", "Input clock"}, {242, 2, "DEV_PCIE3_PCIE_LANE1_RXCLK", "Input clock"}, {242, 3, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK", "Input muxed clock"}, {242, 4, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, {242, 5, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, {242, 6, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, {242, 7, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, {242, 8, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, {242, 9, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, {242, 10, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, {242, 11, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, {242, 12, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, {242, 13, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, {242, 14, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, {242, 15, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, {242, 16, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, {242, 17, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, {242, 18, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, {242, 19, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, {242, 20, "DEV_PCIE3_PCIE_LANE1_TXFCLK", "Input clock"}, {242, 21, "DEV_PCIE3_PCIE_LANE1_REFCLK", "Input clock"}, {242, 22, "DEV_PCIE3_PCIE_LANE0_REFCLK", "Input clock"}, {242, 23, "DEV_PCIE3_PCIE_LANE0_TXMCLK", "Input clock"}, {242, 24, "DEV_PCIE3_PCIE_LANE0_TXFCLK", "Input clock"}, {242, 25, "DEV_PCIE3_PCIE_PM_CLK", "Input clock"}, {242, 26, "DEV_PCIE3_PCIE_LANE0_RXFCLK", "Input clock"}, {242, 27, "DEV_PCIE3_PCIE_LANE1_RXFCLK", "Input clock"}, {242, 28, "DEV_PCIE3_PCIE_LANE0_RXCLK", "Input clock"}, {242, 29, "DEV_PCIE3_PCIE_LANE1_TXCLK", "Output clock"}, {242, 30, "DEV_PCIE3_PCIE_LANE0_TXCLK", "Output clock"}, {119, 0, "DEV_PRU_ICSSG0_PR1_RGMII0_RXC_I", "Input clock"}, {119, 1, "DEV_PRU_ICSSG0_VCLK_CLK", "Input clock"}, {119, 2, "DEV_PRU_ICSSG0_PR1_RGMII1_TXC_I", "Input clock"}, {119, 3, "DEV_PRU_ICSSG0_IEP_CLK", "Input muxed clock"}, {119, 4, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, {119, 5, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, {119, 6, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, {119, 7, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, {119, 8, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, {119, 9, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, {119, 10, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, {119, 11, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, {119, 12, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, {119, 13, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, {119, 14, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, {119, 15, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, {119, 16, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, {119, 17, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, {119, 18, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, {119, 19, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"}, {119, 20, "DEV_PRU_ICSSG0_RGMII_MHZ_5_CLK", "Input clock"}, {119, 21, "DEV_PRU_ICSSG0_PR1_RGMII1_RXC_I", "Input clock"}, {119, 22, "DEV_PRU_ICSSG0_UCLK_CLK", "Input clock"}, {119, 23, "DEV_PRU_ICSSG0_PR1_RGMII0_TXC_I", "Input clock"}, {119, 24, "DEV_PRU_ICSSG0_CORE_CLK", "Input muxed clock"}, {119, 25, "DEV_PRU_ICSSG0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_PRU_ICSSG0_CORE_CLK"}, {119, 26, "DEV_PRU_ICSSG0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG0_CORE_CLK"}, {119, 27, "DEV_PRU_ICSSG0_RGMII_MHZ_250_CLK", "Input clock"}, {119, 28, "DEV_PRU_ICSSG0_RGMII_MHZ_50_CLK", "Input clock"}, {119, 29, "DEV_PRU_ICSSG0_PR1_RGMII1_TXC_O", "Output clock"}, {119, 30, "DEV_PRU_ICSSG0_PR1_MDIO_MDCLK_O", "Output clock"}, {119, 31, "DEV_PRU_ICSSG0_PR1_RGMII0_TXC_O", "Output clock"}, {120, 0, "DEV_PRU_ICSSG1_SERDES0_RXCLK", "Input muxed clock"}, {120, 1, "DEV_PRU_ICSSG1_SERDES0_RXCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_RXCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXCLK"}, {120, 2, "DEV_PRU_ICSSG1_SERDES0_RXCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_RXCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXCLK"}, {120, 3, "DEV_PRU_ICSSG1_PR1_RGMII0_RXC_I", "Input clock"}, {120, 4, "DEV_PRU_ICSSG1_VCLK_CLK", "Input clock"}, {120, 5, "DEV_PRU_ICSSG1_PR1_RGMII1_TXC_I", "Input clock"}, {120, 6, "DEV_PRU_ICSSG1_SERDES0_RXFCLK", "Input muxed clock"}, {120, 7, "DEV_PRU_ICSSG1_SERDES0_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_RXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXFCLK"}, {120, 8, "DEV_PRU_ICSSG1_SERDES0_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_RXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXFCLK"}, {120, 9, "DEV_PRU_ICSSG1_IEP_CLK", "Input muxed clock"}, {120, 10, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, {120, 11, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, {120, 12, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, {120, 13, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, {120, 14, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, {120, 15, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, {120, 16, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, {120, 17, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, {120, 18, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, {120, 19, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, {120, 20, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, {120, 21, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, {120, 22, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, {120, 23, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, {120, 24, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, {120, 25, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"}, {120, 26, "DEV_PRU_ICSSG1_RGMII_MHZ_5_CLK", "Input clock"}, {120, 27, "DEV_PRU_ICSSG1_SERDES0_TXMCLK", "Input muxed clock"}, {120, 28, "DEV_PRU_ICSSG1_SERDES0_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXMCLK"}, {120, 29, "DEV_PRU_ICSSG1_SERDES0_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXMCLK"}, {120, 30, "DEV_PRU_ICSSG1_SERDES0_REFCLK", "Input muxed clock"}, {120, 31, "DEV_PRU_ICSSG1_SERDES0_REFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_REFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_REFCLK"}, {120, 32, "DEV_PRU_ICSSG1_SERDES0_REFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_REFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_REFCLK"}, {120, 33, "DEV_PRU_ICSSG1_SERDES1_RXFCLK", "Input muxed clock"}, {120, 34, "DEV_PRU_ICSSG1_SERDES1_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_RXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXFCLK"}, {120, 35, "DEV_PRU_ICSSG1_SERDES1_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_RXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXFCLK"}, {120, 36, "DEV_PRU_ICSSG1_PR1_RGMII1_RXC_I", "Input clock"}, {120, 37, "DEV_PRU_ICSSG1_SERDES1_RXCLK", "Input muxed clock"}, {120, 38, "DEV_PRU_ICSSG1_SERDES1_RXCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_RXCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXCLK"}, {120, 39, "DEV_PRU_ICSSG1_SERDES1_RXCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_RXCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXCLK"}, {120, 40, "DEV_PRU_ICSSG1_SERDES1_TXFCLK", "Input muxed clock"}, {120, 41, "DEV_PRU_ICSSG1_SERDES1_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_TXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXFCLK"}, {120, 42, "DEV_PRU_ICSSG1_SERDES1_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_TXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXFCLK"}, {120, 43, "DEV_PRU_ICSSG1_SERDES1_TXMCLK", "Input muxed clock"}, {120, 44, "DEV_PRU_ICSSG1_SERDES1_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXMCLK"}, {120, 45, "DEV_PRU_ICSSG1_SERDES1_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXMCLK"}, {120, 46, "DEV_PRU_ICSSG1_SERDES0_TXFCLK", "Input muxed clock"}, {120, 47, "DEV_PRU_ICSSG1_SERDES0_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_TXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXFCLK"}, {120, 48, "DEV_PRU_ICSSG1_SERDES0_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_TXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXFCLK"}, {120, 49, "DEV_PRU_ICSSG1_UCLK_CLK", "Input clock"}, {120, 50, "DEV_PRU_ICSSG1_PR1_RGMII0_TXC_I", "Input clock"}, {120, 51, "DEV_PRU_ICSSG1_SERDES1_REFCLK", "Input muxed clock"}, {120, 52, "DEV_PRU_ICSSG1_SERDES1_REFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_REFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_REFCLK"}, {120, 53, "DEV_PRU_ICSSG1_SERDES1_REFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_REFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_REFCLK"}, {120, 54, "DEV_PRU_ICSSG1_CORE_CLK", "Input muxed clock"}, {120, 55, "DEV_PRU_ICSSG1_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_PRU_ICSSG1_CORE_CLK"}, {120, 56, "DEV_PRU_ICSSG1_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG1_CORE_CLK"}, {120, 57, "DEV_PRU_ICSSG1_RGMII_MHZ_250_CLK", "Input clock"}, {120, 58, "DEV_PRU_ICSSG1_RGMII_MHZ_50_CLK", "Input clock"}, {120, 59, "DEV_PRU_ICSSG1_PR1_RGMII1_TXC_O", "Output clock"}, {120, 60, "DEV_PRU_ICSSG1_PR1_MDIO_MDCLK_O", "Output clock"}, {120, 61, "DEV_PRU_ICSSG1_PR1_RGMII0_TXC_O", "Output clock"}, {120, 62, "DEV_PRU_ICSSG1_SERDES0_TXCLK", "Output clock"}, {120, 63, "DEV_PRU_ICSSG1_SERDES1_TXCLK", "Output clock"}, {133, 0, "DEV_PSC0_SLOW_CLK", "Input clock"}, {133, 1, "DEV_PSC0_CLK", "Input clock"}, {245, 0, "DEV_R5FSS0_CORE0_CPU_CLK", "Input clock"}, {245, 1, "DEV_R5FSS0_CORE0_INTERFACE_CLK", "Input clock"}, {245, 2, "DEV_R5FSS0_CORE0_INTERFACE_PHASE", "Input clock"}, {246, 0, "DEV_R5FSS0_CORE1_CPU_CLK", "Input clock"}, {246, 1, "DEV_R5FSS0_CORE1_INTERFACE_CLK", "Input clock"}, {246, 2, "DEV_R5FSS0_CORE1_INTERFACE_PHASE", "Input clock"}, {134, 0, "DEV_R5FSS0_INTROUTER0_INTR_CLK", "Input clock"}, {247, 0, "DEV_R5FSS1_CORE0_CPU_CLK", "Input clock"}, {247, 1, "DEV_R5FSS1_CORE0_INTERFACE_CLK", "Input clock"}, {247, 2, "DEV_R5FSS1_CORE0_INTERFACE_PHASE", "Input clock"}, {248, 0, "DEV_R5FSS1_CORE1_CPU_CLK", "Input clock"}, {248, 1, "DEV_R5FSS1_CORE1_INTERFACE_CLK", "Input clock"}, {248, 2, "DEV_R5FSS1_CORE1_INTERFACE_PHASE", "Input clock"}, {135, 0, "DEV_R5FSS1_INTROUTER0_INTR_CLK", "Input clock"}, {252, 0, "DEV_RTI0_VBUSP_CLK", "Input clock"}, {252, 1, "DEV_RTI0_RTI_CLK", "Input muxed clock"}, {252, 2, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {252, 3, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {252, 4, "DEV_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {252, 5, "DEV_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {252, 6, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {252, 7, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {252, 8, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {252, 9, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {253, 0, "DEV_RTI1_VBUSP_CLK", "Input clock"}, {253, 1, "DEV_RTI1_RTI_CLK", "Input muxed clock"}, {253, 2, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {253, 3, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {253, 4, "DEV_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {253, 5, "DEV_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {253, 6, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {253, 7, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {253, 8, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {253, 9, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {257, 0, "DEV_RTI15_VBUSP_CLK", "Input clock"}, {257, 1, "DEV_RTI15_RTI_CLK", "Input muxed clock"}, {257, 2, "DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI15_RTI_CLK"}, {257, 3, "DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI15_RTI_CLK"}, {257, 4, "DEV_RTI15_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI15_RTI_CLK"}, {257, 5, "DEV_RTI15_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI15_RTI_CLK"}, {257, 6, "DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI15_RTI_CLK"}, {257, 7, "DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI15_RTI_CLK"}, {257, 8, "DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI15_RTI_CLK"}, {257, 9, "DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI15_RTI_CLK"}, {256, 0, "DEV_RTI16_VBUSP_CLK", "Input clock"}, {256, 1, "DEV_RTI16_RTI_CLK", "Input muxed clock"}, {256, 2, "DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI16_RTI_CLK"}, {256, 3, "DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI16_RTI_CLK"}, {256, 4, "DEV_RTI16_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI16_RTI_CLK"}, {256, 5, "DEV_RTI16_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI16_RTI_CLK"}, {256, 6, "DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI16_RTI_CLK"}, {256, 7, "DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI16_RTI_CLK"}, {256, 8, "DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI16_RTI_CLK"}, {256, 9, "DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI16_RTI_CLK"}, {254, 0, "DEV_RTI24_VBUSP_CLK", "Input clock"}, {254, 1, "DEV_RTI24_RTI_CLK", "Input muxed clock"}, {254, 2, "DEV_RTI24_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI24_RTI_CLK"}, {254, 3, "DEV_RTI24_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI24_RTI_CLK"}, {254, 4, "DEV_RTI24_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI24_RTI_CLK"}, {254, 5, "DEV_RTI24_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI24_RTI_CLK"}, {254, 6, "DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI24_RTI_CLK"}, {254, 7, "DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI24_RTI_CLK"}, {254, 8, "DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI24_RTI_CLK"}, {254, 9, "DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI24_RTI_CLK"}, {255, 0, "DEV_RTI25_VBUSP_CLK", "Input clock"}, {255, 1, "DEV_RTI25_RTI_CLK", "Input muxed clock"}, {255, 2, "DEV_RTI25_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI25_RTI_CLK"}, {255, 3, "DEV_RTI25_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI25_RTI_CLK"}, {255, 4, "DEV_RTI25_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI25_RTI_CLK"}, {255, 5, "DEV_RTI25_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI25_RTI_CLK"}, {255, 6, "DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI25_RTI_CLK"}, {255, 7, "DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI25_RTI_CLK"}, {255, 8, "DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI25_RTI_CLK"}, {255, 9, "DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI25_RTI_CLK"}, {258, 0, "DEV_RTI28_VBUSP_CLK", "Input clock"}, {258, 1, "DEV_RTI28_RTI_CLK", "Input muxed clock"}, {258, 2, "DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI28_RTI_CLK"}, {258, 3, "DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI28_RTI_CLK"}, {258, 4, "DEV_RTI28_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI28_RTI_CLK"}, {258, 5, "DEV_RTI28_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI28_RTI_CLK"}, {258, 6, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI28_RTI_CLK"}, {258, 7, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI28_RTI_CLK"}, {258, 8, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI28_RTI_CLK"}, {258, 9, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI28_RTI_CLK"}, {259, 0, "DEV_RTI29_VBUSP_CLK", "Input clock"}, {259, 1, "DEV_RTI29_RTI_CLK", "Input muxed clock"}, {259, 2, "DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI29_RTI_CLK"}, {259, 3, "DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI29_RTI_CLK"}, {259, 4, "DEV_RTI29_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI29_RTI_CLK"}, {259, 5, "DEV_RTI29_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI29_RTI_CLK"}, {259, 6, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI29_RTI_CLK"}, {259, 7, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI29_RTI_CLK"}, {259, 8, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI29_RTI_CLK"}, {259, 9, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI29_RTI_CLK"}, {260, 0, "DEV_RTI30_VBUSP_CLK", "Input clock"}, {260, 1, "DEV_RTI30_RTI_CLK", "Input muxed clock"}, {260, 2, "DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI30_RTI_CLK"}, {260, 3, "DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI30_RTI_CLK"}, {260, 4, "DEV_RTI30_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI30_RTI_CLK"}, {260, 5, "DEV_RTI30_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI30_RTI_CLK"}, {260, 6, "DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI30_RTI_CLK"}, {260, 7, "DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI30_RTI_CLK"}, {260, 8, "DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI30_RTI_CLK"}, {260, 9, "DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI30_RTI_CLK"}, {261, 0, "DEV_RTI31_VBUSP_CLK", "Input clock"}, {261, 1, "DEV_RTI31_RTI_CLK", "Input muxed clock"}, {261, 2, "DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI31_RTI_CLK"}, {261, 3, "DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI31_RTI_CLK"}, {261, 4, "DEV_RTI31_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI31_RTI_CLK"}, {261, 5, "DEV_RTI31_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI31_RTI_CLK"}, {261, 6, "DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI31_RTI_CLK"}, {261, 7, "DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI31_RTI_CLK"}, {261, 8, "DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI31_RTI_CLK"}, {261, 9, "DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI31_RTI_CLK"}, {264, 0, "DEV_SA2_UL0_X2_CLK", "Input clock"}, {264, 1, "DEV_SA2_UL0_PKA_IN_CLK", "Input clock"}, {264, 2, "DEV_SA2_UL0_X1_CLK", "Input clock"}, {297, 0, "DEV_SERDES_10G0_IP1_LN3_TXCLK", "Input clock"}, {297, 1, "DEV_SERDES_10G0_CLK", "Input clock"}, {297, 2, "DEV_SERDES_10G0_IP3_LN2_TXCLK", "Input clock"}, {297, 3, "DEV_SERDES_10G0_IP1_LN2_TXCLK", "Input clock"}, {297, 4, "DEV_SERDES_10G0_IP1_LN0_TXCLK", "Input clock"}, {297, 5, "DEV_SERDES_10G0_IP3_LN1_TXCLK", "Input clock"}, {297, 6, "DEV_SERDES_10G0_IP3_LN3_TXCLK", "Input clock"}, {297, 7, "DEV_SERDES_10G0_IP3_LN0_TXCLK", "Input clock"}, {297, 8, "DEV_SERDES_10G0_IP1_LN1_TXCLK", "Input clock"}, {297, 9, "DEV_SERDES_10G0_CORE_REF_CLK", "Input muxed clock"}, {297, 10, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"}, {297, 11, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"}, {297, 12, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"}, {297, 13, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"}, {297, 14, "DEV_SERDES_10G0_IP1_LN1_REFCLK", "Output clock"}, {297, 15, "DEV_SERDES_10G0_IP1_LN2_RXCLK", "Output clock"}, {297, 16, "DEV_SERDES_10G0_IP3_LN1_TXFCLK", "Output clock"}, {297, 17, "DEV_SERDES_10G0_IP1_LN0_RXFCLK", "Output clock"}, {297, 18, "DEV_SERDES_10G0_IP1_LN3_RXCLK", "Output clock"}, {297, 19, "DEV_SERDES_10G0_IP3_LN3_RXCLK", "Output clock"}, {297, 20, "DEV_SERDES_10G0_IP3_LN1_TXMCLK", "Output clock"}, {297, 21, "DEV_SERDES_10G0_IP3_LN3_RXFCLK", "Output clock"}, {297, 22, "DEV_SERDES_10G0_IP3_LN3_REFCLK", "Output clock"}, {297, 23, "DEV_SERDES_10G0_IP3_LN2_RXCLK", "Output clock"}, {297, 24, "DEV_SERDES_10G0_IP1_LN0_TXFCLK", "Output clock"}, {297, 25, "DEV_SERDES_10G0_IP3_LN3_TXMCLK", "Output clock"}, {297, 26, "DEV_SERDES_10G0_IP3_LN1_RXFCLK", "Output clock"}, {297, 27, "DEV_SERDES_10G0_IP3_LN0_RXFCLK", "Output clock"}, {297, 28, "DEV_SERDES_10G0_IP1_LN1_TXMCLK", "Output clock"}, {297, 29, "DEV_SERDES_10G0_IP1_LN1_RXFCLK", "Output clock"}, {297, 30, "DEV_SERDES_10G0_IP3_LN3_TXFCLK", "Output clock"}, {297, 31, "DEV_SERDES_10G0_IP1_LN3_TXFCLK", "Output clock"}, {297, 32, "DEV_SERDES_10G0_IP1_LN3_TXMCLK", "Output clock"}, {297, 33, "DEV_SERDES_10G0_IP3_LN1_REFCLK", "Output clock"}, {297, 34, "DEV_SERDES_10G0_IP3_LN0_REFCLK", "Output clock"}, {297, 35, "DEV_SERDES_10G0_IP1_LN3_REFCLK", "Output clock"}, {297, 36, "DEV_SERDES_10G0_IP3_LN0_RXCLK", "Output clock"}, {297, 37, "DEV_SERDES_10G0_IP3_LN2_REFCLK", "Output clock"}, {297, 38, "DEV_SERDES_10G0_IP1_LN0_RXCLK", "Output clock"}, {297, 39, "DEV_SERDES_10G0_IP1_LN0_REFCLK", "Output clock"}, {297, 40, "DEV_SERDES_10G0_IP1_LN2_RXFCLK", "Output clock"}, {297, 41, "DEV_SERDES_10G0_IP1_LN1_TXFCLK", "Output clock"}, {297, 42, "DEV_SERDES_10G0_IP3_LN0_TXFCLK", "Output clock"}, {297, 43, "DEV_SERDES_10G0_REF_OUT_CLK", "Output clock"}, {297, 44, "DEV_SERDES_10G0_IP3_LN1_RXCLK", "Output clock"}, {297, 45, "DEV_SERDES_10G0_IP1_LN2_TXFCLK", "Output clock"}, {297, 46, "DEV_SERDES_10G0_IP1_LN0_TXMCLK", "Output clock"}, {297, 47, "DEV_SERDES_10G0_IP3_LN2_RXFCLK", "Output clock"}, {297, 48, "DEV_SERDES_10G0_IP1_LN2_TXMCLK", "Output clock"}, {297, 49, "DEV_SERDES_10G0_IP3_LN2_TXMCLK", "Output clock"}, {297, 50, "DEV_SERDES_10G0_IP1_LN2_REFCLK", "Output clock"}, {297, 51, "DEV_SERDES_10G0_IP3_LN2_TXFCLK", "Output clock"}, {297, 52, "DEV_SERDES_10G0_IP3_LN0_TXMCLK", "Output clock"}, {297, 53, "DEV_SERDES_10G0_IP1_LN3_RXFCLK", "Output clock"}, {297, 54, "DEV_SERDES_10G0_IP1_LN1_RXCLK", "Output clock"}, {292, 0, "DEV_SERDES_16G0_CORE_REF1_CLK", "Input muxed clock"}, {292, 1, "DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G0_CORE_REF1_CLK"}, {292, 2, "DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G0_CORE_REF1_CLK"}, {292, 3, "DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G0_CORE_REF1_CLK"}, {292, 4, "DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G0_CORE_REF1_CLK"}, {292, 5, "DEV_SERDES_16G0_CLK", "Input clock"}, {292, 6, "DEV_SERDES_16G0_IP1_LN0_TXCLK", "Input clock"}, {292, 7, "DEV_SERDES_16G0_IP2_LN1_TXCLK", "Input clock"}, {292, 8, "DEV_SERDES_16G0_IP3_LN1_TXCLK", "Input clock"}, {292, 9, "DEV_SERDES_16G0_IP2_LN0_TXCLK", "Input clock"}, {292, 10, "DEV_SERDES_16G0_IP1_LN1_TXCLK", "Input clock"}, {292, 11, "DEV_SERDES_16G0_CORE_REF_CLK", "Input muxed clock"}, {292, 12, "DEV_SERDES_16G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G0_CORE_REF_CLK"}, {292, 13, "DEV_SERDES_16G0_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G0_CORE_REF_CLK"}, {292, 14, "DEV_SERDES_16G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G0_CORE_REF_CLK"}, {292, 15, "DEV_SERDES_16G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G0_CORE_REF_CLK"}, {292, 16, "DEV_SERDES_16G0_IP2_LN0_TXFCLK", "Output clock"}, {292, 17, "DEV_SERDES_16G0_IP1_LN1_REFCLK", "Output clock"}, {292, 18, "DEV_SERDES_16G0_IP3_LN1_TXMCLK", "Output clock"}, {292, 19, "DEV_SERDES_16G0_IP3_LN1_TXFCLK", "Output clock"}, {292, 20, "DEV_SERDES_16G0_IP1_LN0_RXFCLK", "Output clock"}, {292, 21, "DEV_SERDES_16G0_IP2_LN1_REFCLK", "Output clock"}, {292, 22, "DEV_SERDES_16G0_IP2_LN1_TXFCLK", "Output clock"}, {292, 23, "DEV_SERDES_16G0_REF_DER_OUT_CLK", "Output clock"}, {292, 24, "DEV_SERDES_16G0_IP1_LN0_TXFCLK", "Output clock"}, {292, 25, "DEV_SERDES_16G0_IP3_LN1_RXFCLK", "Output clock"}, {292, 26, "DEV_SERDES_16G0_IP1_LN1_TXMCLK", "Output clock"}, {292, 27, "DEV_SERDES_16G0_IP1_LN1_RXFCLK", "Output clock"}, {292, 28, "DEV_SERDES_16G0_IP3_LN1_RXCLK", "Output clock"}, {292, 29, "DEV_SERDES_16G0_IP3_LN1_REFCLK", "Output clock"}, {292, 30, "DEV_SERDES_16G0_IP2_LN1_RXCLK", "Output clock"}, {292, 31, "DEV_SERDES_16G0_IP2_LN0_RXFCLK", "Output clock"}, {292, 32, "DEV_SERDES_16G0_IP1_LN0_RXCLK", "Output clock"}, {292, 33, "DEV_SERDES_16G0_REF_OUT_CLK", "Output clock"}, {292, 34, "DEV_SERDES_16G0_REF1_OUT_CLK", "Output clock"}, {292, 35, "DEV_SERDES_16G0_IP1_LN0_REFCLK", "Output clock"}, {292, 36, "DEV_SERDES_16G0_IP1_LN0_TXMCLK", "Output clock"}, {292, 37, "DEV_SERDES_16G0_IP2_LN1_RXFCLK", "Output clock"}, {292, 38, "DEV_SERDES_16G0_IP2_LN1_TXMCLK", "Output clock"}, {292, 39, "DEV_SERDES_16G0_IP2_LN0_REFCLK", "Output clock"}, {292, 40, "DEV_SERDES_16G0_IP2_LN0_TXMCLK", "Output clock"}, {292, 41, "DEV_SERDES_16G0_IP1_LN1_TXFCLK", "Output clock"}, {292, 42, "DEV_SERDES_16G0_IP2_LN0_RXCLK", "Output clock"}, {292, 43, "DEV_SERDES_16G0_IP1_LN1_RXCLK", "Output clock"}, {292, 49, "DEV_SERDES_16G0_CMN_REFCLK1_M", "Input clock"}, {292, 57, "DEV_SERDES_16G0_CMN_REFCLK1_P", "Input clock"}, {293, 0, "DEV_SERDES_16G1_CORE_REF1_CLK", "Input muxed clock"}, {293, 1, "DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G1_CORE_REF1_CLK"}, {293, 2, "DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G1_CORE_REF1_CLK"}, {293, 3, "DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G1_CORE_REF1_CLK"}, {293, 4, "DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G1_CORE_REF1_CLK"}, {293, 5, "DEV_SERDES_16G1_CLK", "Input clock"}, {293, 6, "DEV_SERDES_16G1_IP1_LN0_TXCLK", "Input clock"}, {293, 7, "DEV_SERDES_16G1_IP2_LN1_TXCLK", "Input clock"}, {293, 8, "DEV_SERDES_16G1_IP4_LN1_TXCLK", "Input clock"}, {293, 9, "DEV_SERDES_16G1_IP4_LN0_TXCLK", "Input clock"}, {293, 10, "DEV_SERDES_16G1_IP3_LN1_TXCLK", "Input clock"}, {293, 11, "DEV_SERDES_16G1_IP2_LN0_TXCLK", "Input clock"}, {293, 12, "DEV_SERDES_16G1_IP1_LN1_TXCLK", "Input clock"}, {293, 13, "DEV_SERDES_16G1_CORE_REF_CLK", "Input muxed clock"}, {293, 14, "DEV_SERDES_16G1_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G1_CORE_REF_CLK"}, {293, 15, "DEV_SERDES_16G1_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G1_CORE_REF_CLK"}, {293, 16, "DEV_SERDES_16G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G1_CORE_REF_CLK"}, {293, 17, "DEV_SERDES_16G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G1_CORE_REF_CLK"}, {293, 18, "DEV_SERDES_16G1_IP2_LN0_TXFCLK", "Output clock"}, {293, 19, "DEV_SERDES_16G1_IP1_LN1_REFCLK", "Output clock"}, {293, 20, "DEV_SERDES_16G1_IP4_LN1_RXFCLK", "Output clock"}, {293, 21, "DEV_SERDES_16G1_IP3_LN1_TXMCLK", "Output clock"}, {293, 22, "DEV_SERDES_16G1_IP3_LN1_TXFCLK", "Output clock"}, {293, 23, "DEV_SERDES_16G1_IP1_LN0_RXFCLK", "Output clock"}, {293, 24, "DEV_SERDES_16G1_IP2_LN1_REFCLK", "Output clock"}, {293, 25, "DEV_SERDES_16G1_IP2_LN1_TXFCLK", "Output clock"}, {293, 26, "DEV_SERDES_16G1_REF_DER_OUT_CLK", "Output clock"}, {293, 27, "DEV_SERDES_16G1_IP1_LN0_TXFCLK", "Output clock"}, {293, 28, "DEV_SERDES_16G1_IP3_LN1_RXFCLK", "Output clock"}, {293, 29, "DEV_SERDES_16G1_IP1_LN1_TXMCLK", "Output clock"}, {293, 30, "DEV_SERDES_16G1_IP1_LN1_RXFCLK", "Output clock"}, {293, 31, "DEV_SERDES_16G1_IP4_LN1_REFCLK", "Output clock"}, {293, 32, "DEV_SERDES_16G1_IP3_LN1_RXCLK", "Output clock"}, {293, 33, "DEV_SERDES_16G1_IP4_LN1_TXMCLK", "Output clock"}, {293, 34, "DEV_SERDES_16G1_IP3_LN1_REFCLK", "Output clock"}, {293, 35, "DEV_SERDES_16G1_IP4_LN0_REFCLK", "Output clock"}, {293, 36, "DEV_SERDES_16G1_IP2_LN1_RXCLK", "Output clock"}, {293, 37, "DEV_SERDES_16G1_IP2_LN0_RXFCLK", "Output clock"}, {293, 38, "DEV_SERDES_16G1_IP1_LN0_RXCLK", "Output clock"}, {293, 39, "DEV_SERDES_16G1_REF_OUT_CLK", "Output clock"}, {293, 40, "DEV_SERDES_16G1_REF1_OUT_CLK", "Output clock"}, {293, 41, "DEV_SERDES_16G1_IP4_LN1_RXCLK", "Output clock"}, {293, 42, "DEV_SERDES_16G1_IP1_LN0_REFCLK", "Output clock"}, {293, 43, "DEV_SERDES_16G1_IP1_LN0_TXMCLK", "Output clock"}, {293, 44, "DEV_SERDES_16G1_IP4_LN0_TXFCLK", "Output clock"}, {293, 45, "DEV_SERDES_16G1_IP4_LN0_RXCLK", "Output clock"}, {293, 46, "DEV_SERDES_16G1_IP2_LN1_RXFCLK", "Output clock"}, {293, 47, "DEV_SERDES_16G1_IP2_LN1_TXMCLK", "Output clock"}, {293, 48, "DEV_SERDES_16G1_IP4_LN0_RXFCLK", "Output clock"}, {293, 49, "DEV_SERDES_16G1_IP2_LN0_REFCLK", "Output clock"}, {293, 50, "DEV_SERDES_16G1_IP2_LN0_TXMCLK", "Output clock"}, {293, 51, "DEV_SERDES_16G1_IP1_LN1_TXFCLK", "Output clock"}, {293, 52, "DEV_SERDES_16G1_IP2_LN0_RXCLK", "Output clock"}, {293, 53, "DEV_SERDES_16G1_IP4_LN0_TXMCLK", "Output clock"}, {293, 54, "DEV_SERDES_16G1_IP1_LN1_RXCLK", "Output clock"}, {293, 55, "DEV_SERDES_16G1_IP4_LN1_TXFCLK", "Output clock"}, {293, 60, "DEV_SERDES_16G1_CMN_REFCLK1_M", "Input clock"}, {293, 67, "DEV_SERDES_16G1_CMN_REFCLK1_P", "Input clock"}, {294, 0, "DEV_SERDES_16G2_CORE_REF1_CLK", "Input muxed clock"}, {294, 1, "DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G2_CORE_REF1_CLK"}, {294, 2, "DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G2_CORE_REF1_CLK"}, {294, 3, "DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G2_CORE_REF1_CLK"}, {294, 4, "DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G2_CORE_REF1_CLK"}, {294, 5, "DEV_SERDES_16G2_CLK", "Input clock"}, {294, 6, "DEV_SERDES_16G2_IP2_LN1_TXCLK", "Input clock"}, {294, 7, "DEV_SERDES_16G2_IP4_LN1_TXCLK", "Input clock"}, {294, 8, "DEV_SERDES_16G2_IP4_LN0_TXCLK", "Input clock"}, {294, 9, "DEV_SERDES_16G2_IP3_LN1_TXCLK", "Input clock"}, {294, 10, "DEV_SERDES_16G2_IP2_LN0_TXCLK", "Input clock"}, {294, 11, "DEV_SERDES_16G2_CORE_REF_CLK", "Input muxed clock"}, {294, 12, "DEV_SERDES_16G2_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G2_CORE_REF_CLK"}, {294, 13, "DEV_SERDES_16G2_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G2_CORE_REF_CLK"}, {294, 14, "DEV_SERDES_16G2_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G2_CORE_REF_CLK"}, {294, 15, "DEV_SERDES_16G2_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G2_CORE_REF_CLK"}, {294, 16, "DEV_SERDES_16G2_IP2_LN0_TXFCLK", "Output clock"}, {294, 17, "DEV_SERDES_16G2_IP4_LN1_RXFCLK", "Output clock"}, {294, 18, "DEV_SERDES_16G2_IP3_LN1_TXMCLK", "Output clock"}, {294, 19, "DEV_SERDES_16G2_IP3_LN1_TXFCLK", "Output clock"}, {294, 20, "DEV_SERDES_16G2_IP2_LN1_REFCLK", "Output clock"}, {294, 21, "DEV_SERDES_16G2_IP2_LN1_TXFCLK", "Output clock"}, {294, 22, "DEV_SERDES_16G2_REF_DER_OUT_CLK", "Output clock"}, {294, 23, "DEV_SERDES_16G2_IP3_LN1_RXFCLK", "Output clock"}, {294, 24, "DEV_SERDES_16G2_IP4_LN1_REFCLK", "Output clock"}, {294, 25, "DEV_SERDES_16G2_IP3_LN1_RXCLK", "Output clock"}, {294, 26, "DEV_SERDES_16G2_IP4_LN1_TXMCLK", "Output clock"}, {294, 27, "DEV_SERDES_16G2_IP3_LN1_REFCLK", "Output clock"}, {294, 28, "DEV_SERDES_16G2_IP4_LN0_REFCLK", "Output clock"}, {294, 29, "DEV_SERDES_16G2_IP2_LN1_RXCLK", "Output clock"}, {294, 30, "DEV_SERDES_16G2_IP2_LN0_RXFCLK", "Output clock"}, {294, 31, "DEV_SERDES_16G2_REF_OUT_CLK", "Output clock"}, {294, 32, "DEV_SERDES_16G2_REF1_OUT_CLK", "Output clock"}, {294, 33, "DEV_SERDES_16G2_IP4_LN1_RXCLK", "Output clock"}, {294, 34, "DEV_SERDES_16G2_IP4_LN0_TXFCLK", "Output clock"}, {294, 35, "DEV_SERDES_16G2_IP4_LN0_RXCLK", "Output clock"}, {294, 36, "DEV_SERDES_16G2_IP2_LN1_RXFCLK", "Output clock"}, {294, 37, "DEV_SERDES_16G2_IP2_LN1_TXMCLK", "Output clock"}, {294, 38, "DEV_SERDES_16G2_IP4_LN0_RXFCLK", "Output clock"}, {294, 39, "DEV_SERDES_16G2_IP2_LN0_REFCLK", "Output clock"}, {294, 40, "DEV_SERDES_16G2_IP2_LN0_TXMCLK", "Output clock"}, {294, 41, "DEV_SERDES_16G2_IP2_LN0_RXCLK", "Output clock"}, {294, 42, "DEV_SERDES_16G2_IP4_LN0_TXMCLK", "Output clock"}, {294, 43, "DEV_SERDES_16G2_IP4_LN1_TXFCLK", "Output clock"}, {294, 51, "DEV_SERDES_16G2_CMN_REFCLK1_M", "Input clock"}, {294, 61, "DEV_SERDES_16G2_CMN_REFCLK1_P", "Input clock"}, {295, 0, "DEV_SERDES_16G3_CORE_REF1_CLK", "Input muxed clock"}, {295, 1, "DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G3_CORE_REF1_CLK"}, {295, 2, "DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G3_CORE_REF1_CLK"}, {295, 3, "DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G3_CORE_REF1_CLK"}, {295, 4, "DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G3_CORE_REF1_CLK"}, {295, 5, "DEV_SERDES_16G3_CLK", "Input clock"}, {295, 6, "DEV_SERDES_16G3_IP2_LN1_TXCLK", "Input clock"}, {295, 7, "DEV_SERDES_16G3_IP3_LN1_TXCLK", "Input clock"}, {295, 8, "DEV_SERDES_16G3_IP2_LN0_TXCLK", "Input clock"}, {295, 9, "DEV_SERDES_16G3_CORE_REF_CLK", "Input muxed clock"}, {295, 10, "DEV_SERDES_16G3_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G3_CORE_REF_CLK"}, {295, 11, "DEV_SERDES_16G3_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G3_CORE_REF_CLK"}, {295, 12, "DEV_SERDES_16G3_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G3_CORE_REF_CLK"}, {295, 13, "DEV_SERDES_16G3_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G3_CORE_REF_CLK"}, {295, 14, "DEV_SERDES_16G3_IP2_LN0_TXFCLK", "Output clock"}, {295, 15, "DEV_SERDES_16G3_IP3_LN1_TXMCLK", "Output clock"}, {295, 16, "DEV_SERDES_16G3_IP3_LN1_TXFCLK", "Output clock"}, {295, 17, "DEV_SERDES_16G3_IP2_LN1_REFCLK", "Output clock"}, {295, 18, "DEV_SERDES_16G3_IP2_LN1_TXFCLK", "Output clock"}, {295, 19, "DEV_SERDES_16G3_REF_DER_OUT_CLK", "Output clock"}, {295, 20, "DEV_SERDES_16G3_IP3_LN1_RXFCLK", "Output clock"}, {295, 21, "DEV_SERDES_16G3_IP3_LN1_RXCLK", "Output clock"}, {295, 22, "DEV_SERDES_16G3_IP3_LN1_REFCLK", "Output clock"}, {295, 23, "DEV_SERDES_16G3_IP2_LN1_RXCLK", "Output clock"}, {295, 24, "DEV_SERDES_16G3_IP2_LN0_RXFCLK", "Output clock"}, {295, 25, "DEV_SERDES_16G3_REF_OUT_CLK", "Output clock"}, {295, 26, "DEV_SERDES_16G3_REF1_OUT_CLK", "Output clock"}, {295, 27, "DEV_SERDES_16G3_IP2_LN1_RXFCLK", "Output clock"}, {295, 28, "DEV_SERDES_16G3_IP2_LN1_TXMCLK", "Output clock"}, {295, 29, "DEV_SERDES_16G3_IP2_LN0_REFCLK", "Output clock"}, {295, 30, "DEV_SERDES_16G3_IP2_LN0_TXMCLK", "Output clock"}, {295, 31, "DEV_SERDES_16G3_IP2_LN0_RXCLK", "Output clock"}, {295, 40, "DEV_SERDES_16G3_CMN_REFCLK1_M", "Input clock"}, {295, 51, "DEV_SERDES_16G3_CMN_REFCLK1_P", "Input clock"}, {29, 0, "DEV_STM0_VBUSP_CLK", "Input clock"}, {29, 1, "DEV_STM0_CORE_CLK", "Input clock"}, {29, 2, "DEV_STM0_ATB_CLK", "Input clock"}, {49, 0, "DEV_TIMER0_TIMER_HCLK_CLK", "Input clock"}, {49, 1, "DEV_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"}, {49, 2, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {49, 3, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {49, 4, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {49, 5, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {49, 6, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {49, 7, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {49, 8, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {49, 9, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {49, 10, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {49, 11, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {49, 12, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {49, 13, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {49, 14, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {49, 15, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {49, 16, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {49, 17, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {49, 18, "DEV_TIMER0_TIMER_PWM", "Output clock"}, {50, 0, "DEV_TIMER1_TIMER_HCLK_CLK", "Input clock"}, {50, 1, "DEV_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"}, {50, 2, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT1", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {50, 3, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {60, 0, "DEV_TIMER10_TIMER_HCLK_CLK", "Input clock"}, {60, 1, "DEV_TIMER10_TIMER_TCLK_CLK", "Input muxed clock"}, {60, 2, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {60, 3, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {60, 4, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {60, 5, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {60, 6, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {60, 7, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {60, 8, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {60, 9, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {60, 10, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {60, 11, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {60, 12, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {60, 13, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {60, 14, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {60, 15, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {60, 16, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {60, 17, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {60, 18, "DEV_TIMER10_TIMER_PWM", "Output clock"}, {62, 0, "DEV_TIMER11_TIMER_HCLK_CLK", "Input clock"}, {62, 1, "DEV_TIMER11_TIMER_TCLK_CLK", "Input muxed clock"}, {62, 2, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT11", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, {62, 3, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_10_TIMER_PWM", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, {332, 0, "DEV_TIMER11_CLKSEL_VD_CLK", "Input muxed clock"}, {332, 1, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"}, {332, 2, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"}, {332, 3, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"}, {332, 4, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"}, {332, 5, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"}, {332, 6, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"}, {332, 7, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"}, {332, 8, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"}, {332, 9, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"}, {332, 10, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"}, {332, 11, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"}, {332, 12, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"}, {332, 13, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"}, {332, 14, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"}, {332, 15, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"}, {332, 16, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"}, {63, 0, "DEV_TIMER12_TIMER_HCLK_CLK", "Input clock"}, {63, 1, "DEV_TIMER12_TIMER_TCLK_CLK", "Input muxed clock"}, {63, 2, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {63, 3, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {63, 4, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {63, 5, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {63, 6, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {63, 7, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {63, 8, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {63, 9, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {63, 10, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {63, 11, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {63, 12, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {63, 13, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {63, 14, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {63, 15, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {63, 16, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {63, 17, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {63, 18, "DEV_TIMER12_TIMER_PWM", "Output clock"}, {64, 0, "DEV_TIMER13_TIMER_HCLK_CLK", "Input clock"}, {64, 1, "DEV_TIMER13_TIMER_TCLK_CLK", "Input muxed clock"}, {64, 2, "DEV_TIMER13_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT13", "Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK"}, {64, 3, "DEV_TIMER13_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_12_TIMER_PWM", "Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK"}, {333, 0, "DEV_TIMER13_CLKSEL_VD_CLK", "Input muxed clock"}, {333, 1, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"}, {333, 2, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"}, {333, 3, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"}, {333, 4, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"}, {333, 5, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"}, {333, 6, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"}, {333, 7, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"}, {333, 8, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"}, {333, 9, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"}, {333, 10, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"}, {333, 11, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"}, {333, 12, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"}, {333, 13, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"}, {333, 14, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"}, {333, 15, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"}, {333, 16, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"}, {65, 0, "DEV_TIMER14_TIMER_HCLK_CLK", "Input clock"}, {65, 1, "DEV_TIMER14_TIMER_TCLK_CLK", "Input muxed clock"}, {65, 2, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {65, 3, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {65, 4, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {65, 5, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {65, 6, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {65, 7, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {65, 8, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {65, 9, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {65, 10, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {65, 11, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {65, 12, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {65, 13, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {65, 14, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {65, 15, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {65, 16, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {65, 17, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {65, 18, "DEV_TIMER14_TIMER_PWM", "Output clock"}, {66, 0, "DEV_TIMER15_TIMER_HCLK_CLK", "Input clock"}, {66, 1, "DEV_TIMER15_TIMER_TCLK_CLK", "Input muxed clock"}, {66, 2, "DEV_TIMER15_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT15", "Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK"}, {66, 3, "DEV_TIMER15_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_14_TIMER_PWM", "Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK"}, {334, 0, "DEV_TIMER15_CLKSEL_VD_CLK", "Input muxed clock"}, {334, 1, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"}, {334, 2, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"}, {334, 3, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"}, {334, 4, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"}, {334, 5, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"}, {334, 6, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"}, {334, 7, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"}, {334, 8, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"}, {334, 9, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"}, {334, 10, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"}, {334, 11, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"}, {334, 12, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"}, {334, 13, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"}, {334, 14, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"}, {334, 15, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"}, {334, 16, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"}, {67, 0, "DEV_TIMER16_TIMER_HCLK_CLK", "Input clock"}, {67, 1, "DEV_TIMER16_TIMER_TCLK_CLK", "Input muxed clock"}, {67, 2, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {67, 3, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {67, 4, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {67, 5, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {67, 6, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {67, 7, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {67, 8, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {67, 9, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {67, 10, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {67, 11, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {67, 12, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {67, 13, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {67, 14, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {67, 15, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {67, 16, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {67, 17, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {67, 18, "DEV_TIMER16_TIMER_PWM", "Output clock"}, {68, 0, "DEV_TIMER17_TIMER_HCLK_CLK", "Input clock"}, {68, 1, "DEV_TIMER17_TIMER_TCLK_CLK", "Input muxed clock"}, {68, 2, "DEV_TIMER17_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT17", "Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK"}, {68, 3, "DEV_TIMER17_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_16_TIMER_PWM", "Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK"}, {335, 0, "DEV_TIMER17_CLKSEL_VD_CLK", "Input muxed clock"}, {335, 1, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"}, {335, 2, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"}, {335, 3, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"}, {335, 4, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"}, {335, 5, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"}, {335, 6, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"}, {335, 7, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"}, {335, 8, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"}, {335, 9, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"}, {335, 10, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"}, {335, 11, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"}, {335, 12, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"}, {335, 13, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"}, {335, 14, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"}, {335, 15, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"}, {335, 16, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"}, {69, 0, "DEV_TIMER18_TIMER_HCLK_CLK", "Input clock"}, {69, 1, "DEV_TIMER18_TIMER_TCLK_CLK", "Input muxed clock"}, {69, 2, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {69, 3, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {69, 4, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {69, 5, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {69, 6, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {69, 7, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {69, 8, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {69, 9, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {69, 10, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {69, 11, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {69, 12, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {69, 13, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {69, 14, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {69, 15, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {69, 16, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {69, 17, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {69, 18, "DEV_TIMER18_TIMER_PWM", "Output clock"}, {70, 0, "DEV_TIMER19_TIMER_HCLK_CLK", "Input clock"}, {70, 1, "DEV_TIMER19_TIMER_TCLK_CLK", "Input muxed clock"}, {70, 2, "DEV_TIMER19_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT19", "Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK"}, {70, 3, "DEV_TIMER19_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_18_TIMER_PWM", "Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK"}, {336, 0, "DEV_TIMER19_CLKSEL_VD_CLK", "Input muxed clock"}, {336, 1, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"}, {336, 2, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"}, {336, 3, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"}, {336, 4, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"}, {336, 5, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"}, {336, 6, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"}, {336, 7, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"}, {336, 8, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"}, {336, 9, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"}, {336, 10, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"}, {336, 11, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"}, {336, 12, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"}, {336, 13, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"}, {336, 14, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"}, {336, 15, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"}, {336, 16, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"}, {327, 0, "DEV_TIMER1_CLKSEL_VD_CLK", "Input muxed clock"}, {327, 1, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"}, {327, 2, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"}, {327, 3, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"}, {327, 4, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"}, {327, 5, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"}, {327, 6, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"}, {327, 7, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"}, {327, 8, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"}, {327, 9, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"}, {327, 10, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"}, {327, 11, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"}, {327, 12, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"}, {327, 13, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"}, {327, 14, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"}, {327, 15, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"}, {327, 16, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"}, {51, 0, "DEV_TIMER2_TIMER_HCLK_CLK", "Input clock"}, {51, 1, "DEV_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"}, {51, 2, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {51, 3, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {51, 4, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {51, 5, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {51, 6, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {51, 7, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {51, 8, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {51, 9, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {51, 10, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {51, 11, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {51, 12, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {51, 13, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {51, 14, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {51, 15, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {51, 16, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {51, 17, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {51, 18, "DEV_TIMER2_TIMER_PWM", "Output clock"}, {52, 0, "DEV_TIMER3_TIMER_HCLK_CLK", "Input clock"}, {52, 1, "DEV_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"}, {52, 2, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT3", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {52, 3, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {328, 0, "DEV_TIMER3_CLKSEL_VD_CLK", "Input muxed clock"}, {328, 1, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"}, {328, 2, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"}, {328, 3, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"}, {328, 4, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"}, {328, 5, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"}, {328, 6, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"}, {328, 7, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"}, {328, 8, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"}, {328, 9, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"}, {328, 10, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"}, {328, 11, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"}, {328, 12, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"}, {328, 13, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"}, {328, 14, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"}, {328, 15, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"}, {328, 16, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"}, {53, 0, "DEV_TIMER4_TIMER_HCLK_CLK", "Input clock"}, {53, 1, "DEV_TIMER4_TIMER_TCLK_CLK", "Input muxed clock"}, {53, 2, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {53, 3, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {53, 4, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {53, 5, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {53, 6, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {53, 7, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {53, 8, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {53, 9, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {53, 10, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {53, 11, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {53, 12, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {53, 13, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {53, 14, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {53, 15, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {53, 16, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {53, 17, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {53, 18, "DEV_TIMER4_TIMER_PWM", "Output clock"}, {54, 0, "DEV_TIMER5_TIMER_HCLK_CLK", "Input clock"}, {54, 1, "DEV_TIMER5_TIMER_TCLK_CLK", "Input muxed clock"}, {54, 2, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT5", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {54, 3, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {329, 0, "DEV_TIMER5_CLKSEL_VD_CLK", "Input muxed clock"}, {329, 1, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"}, {329, 2, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"}, {329, 3, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"}, {329, 4, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"}, {329, 5, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"}, {329, 6, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"}, {329, 7, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"}, {329, 8, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"}, {329, 9, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"}, {329, 10, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"}, {329, 11, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"}, {329, 12, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"}, {329, 13, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"}, {329, 14, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"}, {329, 15, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"}, {329, 16, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"}, {55, 0, "DEV_TIMER6_TIMER_HCLK_CLK", "Input clock"}, {55, 1, "DEV_TIMER6_TIMER_TCLK_CLK", "Input muxed clock"}, {55, 2, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {55, 3, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {55, 4, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {55, 5, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {55, 6, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {55, 7, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {55, 8, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {55, 9, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {55, 10, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {55, 11, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {55, 12, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {55, 13, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {55, 14, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {55, 15, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {55, 16, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {55, 17, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {55, 18, "DEV_TIMER6_TIMER_PWM", "Output clock"}, {57, 0, "DEV_TIMER7_TIMER_HCLK_CLK", "Input clock"}, {57, 1, "DEV_TIMER7_TIMER_TCLK_CLK", "Input muxed clock"}, {57, 2, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT7", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {57, 3, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {330, 0, "DEV_TIMER7_CLKSEL_VD_CLK", "Input muxed clock"}, {330, 1, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"}, {330, 2, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"}, {330, 3, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"}, {330, 4, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"}, {330, 5, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"}, {330, 6, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"}, {330, 7, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"}, {330, 8, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"}, {330, 9, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"}, {330, 10, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"}, {330, 11, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"}, {330, 12, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"}, {330, 13, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"}, {330, 14, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"}, {330, 15, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"}, {330, 16, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"}, {58, 0, "DEV_TIMER8_TIMER_HCLK_CLK", "Input clock"}, {58, 1, "DEV_TIMER8_TIMER_TCLK_CLK", "Input muxed clock"}, {58, 2, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {58, 3, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {58, 4, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {58, 5, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {58, 6, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {58, 7, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {58, 8, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {58, 9, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {58, 10, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {58, 11, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {58, 12, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {58, 13, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {58, 14, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {58, 15, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {58, 16, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {58, 17, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {58, 18, "DEV_TIMER8_TIMER_PWM", "Output clock"}, {59, 0, "DEV_TIMER9_TIMER_HCLK_CLK", "Input clock"}, {59, 1, "DEV_TIMER9_TIMER_TCLK_CLK", "Input muxed clock"}, {59, 2, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT9", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, {59, 3, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_8_TIMER_PWM", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, {331, 0, "DEV_TIMER9_CLKSEL_VD_CLK", "Input muxed clock"}, {331, 1, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"}, {331, 2, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"}, {331, 3, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"}, {331, 4, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"}, {331, 5, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"}, {331, 6, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"}, {331, 7, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"}, {331, 8, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"}, {331, 9, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"}, {331, 10, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"}, {331, 11, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"}, {331, 12, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"}, {331, 13, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"}, {331, 14, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"}, {331, 15, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"}, {331, 16, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"}, {136, 0, "DEV_TIMESYNC_INTRTR0_INTR_CLK", "Input clock"}, {146, 0, "DEV_UART0_FCLK_CLK", "Input clock"}, {146, 1, "DEV_UART0_VBUSP_CLK", "Input clock"}, {278, 0, "DEV_UART1_FCLK_CLK", "Input clock"}, {278, 1, "DEV_UART1_VBUSP_CLK", "Input clock"}, {279, 0, "DEV_UART2_FCLK_CLK", "Input clock"}, {279, 1, "DEV_UART2_VBUSP_CLK", "Input clock"}, {280, 0, "DEV_UART3_FCLK_CLK", "Input clock"}, {280, 1, "DEV_UART3_VBUSP_CLK", "Input clock"}, {281, 0, "DEV_UART4_FCLK_CLK", "Input clock"}, {281, 1, "DEV_UART4_VBUSP_CLK", "Input clock"}, {282, 0, "DEV_UART5_FCLK_CLK", "Input clock"}, {282, 1, "DEV_UART5_VBUSP_CLK", "Input clock"}, {283, 0, "DEV_UART6_FCLK_CLK", "Input clock"}, {283, 1, "DEV_UART6_VBUSP_CLK", "Input clock"}, {284, 0, "DEV_UART7_FCLK_CLK", "Input clock"}, {284, 1, "DEV_UART7_VBUSP_CLK", "Input clock"}, {285, 0, "DEV_UART8_FCLK_CLK", "Input clock"}, {285, 1, "DEV_UART8_VBUSP_CLK", "Input clock"}, {286, 0, "DEV_UART9_FCLK_CLK", "Input clock"}, {286, 1, "DEV_UART9_VBUSP_CLK", "Input clock"}, {277, 0, "DEV_UFS0_UFSHCI_HCLK_CLK", "Input clock"}, {277, 1, "DEV_UFS0_UFSHCI_MCLK_CLK", "Input muxed clock"}, {277, 2, "DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK"}, {277, 3, "DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK"}, {277, 4, "DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT6_CLK", "Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK"}, {277, 5, "DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK"}, {277, 6, "DEV_UFS0_UFSHCI_MPHY_REFCLK", "Output clock"}, {288, 0, "DEV_USB0_PIPE_REFCLK", "Input muxed clock"}, {288, 1, "DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_REFCLK", "Parent input clock option to DEV_USB0_PIPE_REFCLK"}, {288, 2, "DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_REFCLK", "Parent input clock option to DEV_USB0_PIPE_REFCLK"}, {288, 3, "DEV_USB0_CLK_LPM_CLK", "Input clock"}, {288, 4, "DEV_USB0_BUF_CLK", "Input clock"}, {288, 5, "DEV_USB0_USB2_APB_PCLK_CLK", "Input clock"}, {288, 6, "DEV_USB0_PIPE_RXCLK", "Input muxed clock"}, {288, 7, "DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_RXCLK", "Parent input clock option to DEV_USB0_PIPE_RXCLK"}, {288, 8, "DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_RXCLK", "Parent input clock option to DEV_USB0_PIPE_RXCLK"}, {288, 9, "DEV_USB0_PIPE_TXMCLK", "Input muxed clock"}, {288, 10, "DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_TXMCLK", "Parent input clock option to DEV_USB0_PIPE_TXMCLK"}, {288, 11, "DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_TXMCLK", "Parent input clock option to DEV_USB0_PIPE_TXMCLK"}, {288, 12, "DEV_USB0_PIPE_RXFCLK", "Input muxed clock"}, {288, 13, "DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_RXFCLK", "Parent input clock option to DEV_USB0_PIPE_RXFCLK"}, {288, 14, "DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_RXFCLK", "Parent input clock option to DEV_USB0_PIPE_RXFCLK"}, {288, 15, "DEV_USB0_USB2_REFCLOCK_CLK", "Input muxed clock"}, {288, 16, "DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK"}, {288, 17, "DEV_USB0_USB2_REFCLOCK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK"}, {288, 18, "DEV_USB0_PCLK_CLK", "Input clock"}, {288, 19, "DEV_USB0_ACLK_CLK", "Input clock"}, {288, 20, "DEV_USB0_PIPE_TXFCLK", "Input muxed clock"}, {288, 21, "DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_TXFCLK", "Parent input clock option to DEV_USB0_PIPE_TXFCLK"}, {288, 22, "DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_TXFCLK", "Parent input clock option to DEV_USB0_PIPE_TXFCLK"}, {288, 23, "DEV_USB0_PIPE_TXCLK", "Output clock"}, {289, 0, "DEV_USB1_PIPE_REFCLK", "Input muxed clock"}, {289, 1, "DEV_USB1_PIPE_REFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_REFCLK", "Parent input clock option to DEV_USB1_PIPE_REFCLK"}, {289, 2, "DEV_USB1_PIPE_REFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_REFCLK", "Parent input clock option to DEV_USB1_PIPE_REFCLK"}, {289, 3, "DEV_USB1_CLK_LPM_CLK", "Input clock"}, {289, 4, "DEV_USB1_BUF_CLK", "Input clock"}, {289, 5, "DEV_USB1_USB2_APB_PCLK_CLK", "Input clock"}, {289, 6, "DEV_USB1_PIPE_RXCLK", "Input muxed clock"}, {289, 7, "DEV_USB1_PIPE_RXCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_RXCLK", "Parent input clock option to DEV_USB1_PIPE_RXCLK"}, {289, 8, "DEV_USB1_PIPE_RXCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_RXCLK", "Parent input clock option to DEV_USB1_PIPE_RXCLK"}, {289, 9, "DEV_USB1_PIPE_TXMCLK", "Input muxed clock"}, {289, 10, "DEV_USB1_PIPE_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_TXMCLK", "Parent input clock option to DEV_USB1_PIPE_TXMCLK"}, {289, 11, "DEV_USB1_PIPE_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_TXMCLK", "Parent input clock option to DEV_USB1_PIPE_TXMCLK"}, {289, 12, "DEV_USB1_PIPE_RXFCLK", "Input muxed clock"}, {289, 13, "DEV_USB1_PIPE_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_RXFCLK", "Parent input clock option to DEV_USB1_PIPE_RXFCLK"}, {289, 14, "DEV_USB1_PIPE_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_RXFCLK", "Parent input clock option to DEV_USB1_PIPE_RXFCLK"}, {289, 15, "DEV_USB1_USB2_REFCLOCK_CLK", "Input muxed clock"}, {289, 16, "DEV_USB1_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_USB1_USB2_REFCLOCK_CLK"}, {289, 17, "DEV_USB1_USB2_REFCLOCK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_USB1_USB2_REFCLOCK_CLK"}, {289, 18, "DEV_USB1_PCLK_CLK", "Input clock"}, {289, 19, "DEV_USB1_ACLK_CLK", "Input clock"}, {289, 20, "DEV_USB1_PIPE_TXFCLK", "Input muxed clock"}, {289, 21, "DEV_USB1_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_TXFCLK", "Parent input clock option to DEV_USB1_PIPE_TXFCLK"}, {289, 22, "DEV_USB1_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_TXFCLK", "Parent input clock option to DEV_USB1_PIPE_TXFCLK"}, {289, 23, "DEV_USB1_PIPE_TXCLK", "Output clock"}, {290, 0, "DEV_VPAC0_CLK", "Input clock"}, {290, 1, "DEV_VPAC0_PLL_DCO_CLK", "Input clock"}, {291, 0, "DEV_VPFE0_CCD_PCLK_CLK", "Input clock"}, {291, 1, "DEV_VPFE0_VPFE_CLK", "Input clock"}, {145, 0, "DEV_WKUP_DDPA0_DDPA_CLK", "Input clock"}, {99, 0, "DEV_WKUP_ESM0_CLK", "Input clock"}, {113, 0, "DEV_WKUP_GPIO0_MMR_CLK", "Input clock"}, {114, 0, "DEV_WKUP_GPIO1_MMR_CLK", "Input clock"}, {137, 0, "DEV_WKUP_GPIOMUX_INTRTR0_INTR_CLK", "Input clock"}, {197, 0, "DEV_WKUP_I2C0_PISYS_CLK", "Input muxed clock"}, {197, 1, "DEV_WKUP_I2C0_PISYS_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_WKUP_I2C0_PISYS_CLK"}, {197, 2, "DEV_WKUP_I2C0_PISYS_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_WKUP_I2C0_PISYS_CLK"}, {197, 3, "DEV_WKUP_I2C0_PISCL", "Input clock"}, {197, 4, "DEV_WKUP_I2C0_CLK", "Input clock"}, {197, 5, "DEV_WKUP_I2C0_PORSCL", "Output clock"}, {132, 0, "DEV_WKUP_PORZ_SYNC0_CLK_12M_RC_CLK", "Input clock"}, {138, 0, "DEV_WKUP_PSC0_SLOW_CLK", "Input clock"}, {138, 1, "DEV_WKUP_PSC0_CLK", "Input clock"}, {287, 0, "DEV_WKUP_UART0_FCLK_CLK", "Input muxed clock"}, {287, 1, "DEV_WKUP_UART0_FCLK_CLK_PARENT_WKUPUSART_CLK_SEL_OUT0", "Parent input clock option to DEV_WKUP_UART0_FCLK_CLK"}, {287, 2, "DEV_WKUP_UART0_FCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_WKUP_UART0_FCLK_CLK"}, {287, 3, "DEV_WKUP_UART0_VBUSP_CLK", "Input clock"}, {154, 0, "DEV_WKUP_VTM0_FIX_REF2_CLK", "Input clock"}, {154, 1, "DEV_WKUP_VTM0_VBUSP_CLK", "Input clock"}, {154, 2, "DEV_WKUP_VTM0_FIX_REF_CLK", "Input clock"}, }; k3conf_0.3/soc/am65x/0000775000175000017500000000000014504336513011273 5ustar k3conf_0.3/soc/am65x/am65x_devices_info.c0000664000175000017500000002312514375734376015136 0ustar /* * AM65X Devices Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_devices_info am65x_devices_info[] = { {0, "AM6_DEV_MCU_ADC0"}, {1, "AM6_DEV_MCU_ADC1"}, {2, "AM6_DEV_CAL0"}, {3, "AM6_DEV_CMPEVENT_INTRTR0"}, {5, "AM6_DEV_MCU_CPSW0"}, {6, "AM6_DEV_CPT2_AGGR0"}, {7, "AM6_DEV_MCU_CPT2_AGGR0"}, {8, "AM6_DEV_STM0"}, {9, "AM6_DEV_DCC0"}, {10, "AM6_DEV_DCC1"}, {11, "AM6_DEV_DCC2"}, {12, "AM6_DEV_DCC3"}, {13, "AM6_DEV_DCC4"}, {14, "AM6_DEV_DCC5"}, {15, "AM6_DEV_DCC6"}, {16, "AM6_DEV_DCC7"}, {17, "AM6_DEV_MCU_DCC0"}, {18, "AM6_DEV_MCU_DCC1"}, {19, "AM6_DEV_MCU_DCC2"}, {20, "AM6_DEV_DDRSS0"}, {21, "AM6_DEV_DEBUGSS_WRAP0"}, {22, "AM6_DEV_WKUP_DMSC0"}, {23, "AM6_DEV_TIMER0"}, {24, "AM6_DEV_TIMER1"}, {25, "AM6_DEV_TIMER10"}, {26, "AM6_DEV_TIMER11"}, {27, "AM6_DEV_TIMER2"}, {28, "AM6_DEV_TIMER3"}, {29, "AM6_DEV_TIMER4"}, {30, "AM6_DEV_TIMER5"}, {31, "AM6_DEV_TIMER6"}, {32, "AM6_DEV_TIMER7"}, {33, "AM6_DEV_TIMER8"}, {34, "AM6_DEV_TIMER9"}, {35, "AM6_DEV_MCU_TIMER0"}, {36, "AM6_DEV_MCU_TIMER1"}, {37, "AM6_DEV_MCU_TIMER2"}, {38, "AM6_DEV_MCU_TIMER3"}, {39, "AM6_DEV_ECAP0"}, {40, "AM6_DEV_EHRPWM0"}, {41, "AM6_DEV_EHRPWM1"}, {42, "AM6_DEV_EHRPWM2"}, {43, "AM6_DEV_EHRPWM3"}, {44, "AM6_DEV_EHRPWM4"}, {45, "AM6_DEV_EHRPWM5"}, {46, "AM6_DEV_ELM0"}, {47, "AM6_DEV_MMCSD0"}, {48, "AM6_DEV_MMCSD1"}, {49, "AM6_DEV_EQEP0"}, {50, "AM6_DEV_EQEP1"}, {51, "AM6_DEV_EQEP2"}, {52, "AM6_DEV_ESM0"}, {53, "AM6_DEV_MCU_ESM0"}, {54, "AM6_DEV_WKUP_ESM0"}, {56, "AM6_DEV_GIC0"}, {57, "AM6_DEV_GPIO0"}, {58, "AM6_DEV_GPIO1"}, {59, "AM6_DEV_WKUP_GPIO0"}, {60, "AM6_DEV_GPMC0"}, {61, "AM6_DEV_GTC0"}, {62, "AM6_DEV_PRU_ICSSG0"}, {63, "AM6_DEV_PRU_ICSSG1"}, {64, "AM6_DEV_PRU_ICSSG2"}, {65, "AM6_DEV_GPU0"}, {66, "AM6_DEV_CCDEBUGSS0"}, {67, "AM6_DEV_DSS0"}, {68, "AM6_DEV_DEBUGSS0"}, {69, "AM6_DEV_EFUSE0"}, {70, "AM6_DEV_PSC0"}, {71, "AM6_DEV_MCU_DEBUGSS0"}, {72, "AM6_DEV_MCU_EFUSE0"}, {73, "AM6_DEV_PBIST0"}, {74, "AM6_DEV_PBIST1"}, {75, "AM6_DEV_MCU_PBIST0"}, {76, "AM6_DEV_PLLCTRL0"}, {77, "AM6_DEV_WKUP_PLLCTRL0"}, {78, "AM6_DEV_MCU_ROM0"}, {79, "AM6_DEV_WKUP_PSC0"}, {80, "AM6_DEV_WKUP_VTM0"}, {81, "AM6_DEV_DEBUGSUSPENDRTR0"}, {82, "AM6_DEV_CBASS0"}, {83, "AM6_DEV_CBASS_DEBUG0"}, {84, "AM6_DEV_CBASS_FW0"}, {85, "AM6_DEV_CBASS_INFRA0"}, {86, "AM6_DEV_ECC_AGGR0"}, {87, "AM6_DEV_ECC_AGGR1"}, {88, "AM6_DEV_ECC_AGGR2"}, {89, "AM6_DEV_MCU_CBASS0"}, {90, "AM6_DEV_MCU_CBASS_DEBUG0"}, {91, "AM6_DEV_MCU_CBASS_FW0"}, {92, "AM6_DEV_MCU_ECC_AGGR0"}, {93, "AM6_DEV_MCU_ECC_AGGR1"}, {94, "AM6_DEV_WKUP_CBASS0"}, {95, "AM6_DEV_WKUP_ECC_AGGR0"}, {96, "AM6_DEV_WKUP_CBASS_FW0"}, {97, "AM6_DEV_MAIN2MCU_LVL_INTRTR0"}, {98, "AM6_DEV_MAIN2MCU_PLS_INTRTR0"}, {99, "AM6_DEV_CTRL_MMR0"}, {100, "AM6_DEV_GPIOMUX_INTRTR0"}, {101, "AM6_DEV_PLL_MMR0"}, {102, "AM6_DEV_MCU_MCAN0"}, {103, "AM6_DEV_MCU_MCAN1"}, {104, "AM6_DEV_MCASP0"}, {105, "AM6_DEV_MCASP1"}, {106, "AM6_DEV_MCASP2"}, {107, "AM6_DEV_MCU_CTRL_MMR0"}, {108, "AM6_DEV_MCU_PLL_MMR0"}, {109, "AM6_DEV_MCU_SEC_MMR0"}, {110, "AM6_DEV_I2C0"}, {111, "AM6_DEV_I2C1"}, {112, "AM6_DEV_I2C2"}, {113, "AM6_DEV_I2C3"}, {114, "AM6_DEV_MCU_I2C0"}, {115, "AM6_DEV_WKUP_I2C0"}, {116, "AM6_DEV_MCU_MSRAM0"}, {117, "AM6_DEV_DFTSS0"}, {118, "AM6_DEV_NAVSS0"}, {119, "AM6_DEV_MCU_NAVSS0"}, {120, "AM6_DEV_PCIE0"}, {121, "AM6_DEV_PCIE1"}, {122, "AM6_DEV_PDMA_DEBUG0"}, {123, "AM6_DEV_PDMA0"}, {124, "AM6_DEV_PDMA1"}, {125, "AM6_DEV_MCU_PDMA0"}, {126, "AM6_DEV_MCU_PDMA1"}, {127, "AM6_DEV_MCU_PSRAM0"}, {128, "AM6_DEV_PSRAMECC0"}, {129, "AM6_DEV_MCU_ARMSS0"}, {130, "AM6_DEV_RTI0"}, {131, "AM6_DEV_RTI1"}, {132, "AM6_DEV_RTI2"}, {133, "AM6_DEV_RTI3"}, {134, "AM6_DEV_MCU_RTI0"}, {135, "AM6_DEV_MCU_RTI1"}, {136, "AM6_DEV_SA2_UL0"}, {137, "AM6_DEV_MCSPI0"}, {138, "AM6_DEV_MCSPI1"}, {139, "AM6_DEV_MCSPI2"}, {140, "AM6_DEV_MCSPI3"}, {141, "AM6_DEV_MCSPI4"}, {142, "AM6_DEV_MCU_MCSPI0"}, {143, "AM6_DEV_MCU_MCSPI1"}, {144, "AM6_DEV_MCU_MCSPI2"}, {145, "AM6_DEV_TIMESYNC_INTRTR0"}, {146, "AM6_DEV_UART0"}, {147, "AM6_DEV_UART1"}, {148, "AM6_DEV_UART2"}, {149, "AM6_DEV_MCU_UART0"}, {150, "AM6_DEV_WKUP_UART0"}, {151, "AM6_DEV_USB3SS0"}, {152, "AM6_DEV_USB3SS1"}, {153, "AM6_DEV_SERDES0"}, {154, "AM6_DEV_SERDES1"}, {155, "AM6_DEV_WKUP_CTRL_MMR0"}, {156, "AM6_DEV_WKUP_GPIOMUX_INTRTR0"}, {157, "AM6_DEV_BOARD0"}, {159, "AM6_DEV_MCU_ARMSS0_CPU0"}, {161, "AM6_DEV_WKUP_DMSC0_CORTEX_M3_0"}, {163, "AM6_DEV_NAVSS0_CPTS0"}, {164, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER0"}, {165, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER1"}, {166, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER2"}, {167, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER3"}, {168, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER4"}, {169, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER5"}, {170, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER6"}, {171, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER7"}, {172, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER8"}, {173, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER9"}, {174, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER10"}, {175, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER11"}, {176, "AM6_DEV_NAVSS0_MCRC0"}, {177, "AM6_DEV_NAVSS0_PVU0"}, {178, "AM6_DEV_NAVSS0_PVU1"}, {179, "AM6_DEV_NAVSS0_UDMASS_INTA0"}, {180, "AM6_DEV_NAVSS0_MODSS_INTA0"}, {181, "AM6_DEV_NAVSS0_MODSS_INTA1"}, {182, "AM6_DEV_NAVSS0_INTR_ROUTER_0"}, {183, "AM6_DEV_NAVSS0_TIMER_MGR0"}, {184, "AM6_DEV_NAVSS0_TIMER_MGR1"}, {185, "AM6_DEV_NAVSS0_PROXY0"}, {187, "AM6_DEV_NAVSS0_RINGACC0"}, {188, "AM6_DEV_NAVSS0_UDMAP0"}, {189, "AM6_DEV_MCU_NAVSS0_INTR_AGGR_0"}, {190, "AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0"}, {191, "AM6_DEV_MCU_NAVSS0_PROXY0"}, {193, "AM6_DEV_MCU_NAVSS0_MCRC0"}, {194, "AM6_DEV_MCU_NAVSS0_UDMAP0"}, {195, "AM6_DEV_MCU_NAVSS0_RINGACC0"}, {196, "AM6_DEV_COMPUTE_CLUSTER_MSMC0"}, {197, "AM6_DEV_COMPUTE_CLUSTER_PBIST0"}, {198, "AM6_DEV_COMPUTE_CLUSTER_CPAC0"}, {199, "AM6_DEV_COMPUTE_CLUSTER_CPAC_PBIST0"}, {200, "AM6_DEV_COMPUTE_CLUSTER_CPAC1"}, {201, "AM6_DEV_COMPUTE_CLUSTER_CPAC_PBIST1"}, {202, "AM6_DEV_COMPUTE_CLUSTER_A53_0"}, {203, "AM6_DEV_COMPUTE_CLUSTER_A53_1"}, {204, "AM6_DEV_COMPUTE_CLUSTER_A53_2"}, {205, "AM6_DEV_COMPUTE_CLUSTER_A53_3"}, {206, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4"}, {207, "AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3"}, {208, "AM6_DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0"}, {209, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3"}, {210, "AM6_DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1"}, {211, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5"}, {212, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6"}, {213, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0"}, {214, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2"}, {215, "AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2"}, {216, "AM6_DEV_OLDI_TX_CORE_MAIN_0"}, {217, "AM6_DEV_K3_ARM_ATB_FUNNEL_3_32_MCU_0"}, {218, "AM6_DEV_ICEMELTER_WKUP_0"}, {219, "AM6_DEV_K3_LED_MAIN_0"}, {220, "AM6_DEV_VDC_DATA_VBUSM_32B_REF_WKUP2MCU"}, {221, "AM6_DEV_VDC_DATA_VBUSM_32B_REF_MCU2WKUP"}, {222, "AM6_DEV_VDC_DATA_VBUSM_64B_REF_MAIN2MCU"}, {223, "AM6_DEV_VDC_DATA_VBUSM_64B_REF_MCU2MAIN"}, {224, "AM6_DEV_VDC_DMSC_DBG_VBUSP_32B_REF_DBG2DMSC"}, {225, "AM6_DEV_VDC_INFRA_VBUSP_32B_REF_WKUP2MAIN_INFRA"}, {226, "AM6_DEV_VDC_INFRA_VBUSP_32B_REF_MCU2MAIN_INFRA"}, {227, "AM6_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWWKUP2MCU"}, {228, "AM6_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWMCU2MAIN"}, {229, "AM6_DEV_VDC_MCU_DBG_VBUSP_32B_REF_DBGMAIN2MCU"}, {230, "AM6_DEV_VDC_NAV_PSIL_128B_REF_MAIN2MCU"}, {231, "AM6_DEV_GS80PRG_SOC_WRAP_WKUP_0"}, {232, "AM6_DEV_GS80PRG_MCU_WRAP_WKUP_0"}, {233, "AM6_DEV_MX_WAKEUP_RESET_SYNC_WKUP_0"}, {234, "AM6_DEV_MX_EFUSE_MAIN_CHAIN_MAIN_0"}, {235, "AM6_DEV_MX_EFUSE_MCU_CHAIN_MCU_0"}, {236, "AM6_DEV_DUMMY_IP_LPSC_WKUP2MCU_VD"}, {237, "AM6_DEV_DUMMY_IP_LPSC_WKUP2MAIN_INFRA_VD"}, {238, "AM6_DEV_DUMMY_IP_LPSC_DEBUG2DMSC_VD"}, {239, "AM6_DEV_DUMMY_IP_LPSC_DMSC_VD"}, {240, "AM6_DEV_DUMMY_IP_LPSC_MCU2MAIN_INFRA_VD"}, {241, "AM6_DEV_DUMMY_IP_LPSC_MCU2MAIN_VD"}, {242, "AM6_DEV_DUMMY_IP_LPSC_MCU2WKUP_VD"}, {243, "AM6_DEV_DUMMY_IP_LPSC_MAIN2MCU_VD"}, {244, "AM6_DEV_DUMMY_IP_LPSC_EMIF_DATA_VD"}, {245, "AM6_DEV_MCU_ARMSS0_CPU1"}, {246, "AM6_DEV_MCU_FSS0_FSAS_0"}, {247, "AM6_DEV_MCU_FSS0_HYPERBUS0"}, {248, "AM6_DEV_MCU_FSS0_OSPI_0"}, {249, "AM6_DEV_MCU_FSS0_OSPI_1"}, }; k3conf_0.3/soc/am65x/am65x_host_info.c0000664000175000017500000000557214375734376014477 0ustar /* * AM65X Hosts Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_host_info am65x_host_info[] = { {0, "DMSC", "Secure", "Device Management and Security Control"}, {3, "R5_0", "Non Secure", "Cortex R5 Context 0 on MCU island"}, {4, "R5_1", "Secure", "Cortex R5 Context 1 on MCU island(Boot)"}, {5, "R5_2", "Non Secure", "Cortex R5 Context 2 on MCU island"}, {6, "R5_3", "Secure", "Cortex R5 Context 3 on MCU island"}, {10, "A53_0", "Secure", "Cortex A53 context 0 on Main island"}, {11, "A53_1", "Secure", "Cortex A53 context 1 on Main island"}, {12, "A53_2", "Non Secure", "Cortex A53 context 2 on Main island"}, {13, "A53_3", "Non Secure", "Cortex A53 context 3 on Main island"}, {14, "A53_4", "Non Secure", "Cortex A53 context 4 on Main island"}, {15, "A53_5", "Non Secure", "Cortex A53 context 5 on Main island"}, {16, "A53_6", "Non Secure", "Cortex A53 context 6 on Main island"}, {17, "A53_7", "Non Secure", "Cortex A53 context 7 on Main island"}, {30, "GPU_0", "Non Secure", "SGX544 Context 0 on Main island"}, {31, "GPU_1", "Non Secure", "SGX544 Context 1 on Main island"}, {50, "ICSSG_0", "Non Secure", "ICSS Context 0 on Main island"}, {51, "ICSSG_1", "Non Secure", "ICSS Context 1 on Main island"}, {52, "ICSSG_2", "Non Secure", "ICSS Context 2 on Main island"}, }; k3conf_0.3/soc/am65x/am65x_sec_proxy_info.c0000664000175000017500000001235214375734376015527 0ustar /* * AM65X Sec Proxy Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_sec_proxy_info am65x_main_sp_info[] = { {0, "read", 2, "A53_0", "notify"}, {1, "read", 30, "A53_0", "response"}, {2, "write", 10, "A53_0", "high_priority"}, {3, "write", 20, "A53_0", "low_priority"}, {4, "write", 2, "A53_0", "notify_resp"}, {5, "read", 2, "A53_1", "notify"}, {6, "read", 30, "A53_1", "response"}, {7, "write", 10, "A53_1", "high_priority"}, {8, "write", 20, "A53_1", "low_priority"}, {9, "write", 2, "A53_1", "notify_resp"}, {10, "read", 2, "A53_2", "notify"}, {11, "read", 22, "A53_2", "response"}, {12, "write", 2, "A53_2", "high_priority"}, {13, "write", 20, "A53_2", "low_priority"}, {14, "write", 2, "A53_2", "notify_resp"}, {15, "read", 2, "A53_3", "notify"}, {16, "read", 7, "A53_3", "response"}, {17, "write", 2, "A53_3", "high_priority"}, {18, "write", 5, "A53_3", "low_priority"}, {19, "write", 2, "A53_3", "notify_resp"}, {20, "read", 2, "A53_4", "notify"}, {21, "read", 5, "A53_4", "response"}, {22, "write", 2, "A53_4", "high_priority"}, {23, "write", 5, "A53_4", "low_priority"}, {24, "write", 2, "A53_4", "notify_resp"}, {25, "read", 2, "A53_5", "notify"}, {26, "read", 5, "A53_5", "response"}, {27, "write", 2, "A53_5", "high_priority"}, {28, "write", 5, "A53_5", "low_priority"}, {29, "write", 2, "A53_5", "notify_resp"}, {30, "read", 2, "A53_6", "notify"}, {31, "read", 5, "A53_6", "response"}, {32, "write", 2, "A53_6", "high_priority"}, {33, "write", 5, "A53_6", "low_priority"}, {34, "write", 2, "A53_6", "notify_resp"}, {35, "read", 2, "A53_7", "notify"}, {36, "read", 5, "A53_7", "response"}, {37, "write", 2, "A53_7", "high_priority"}, {38, "write", 5, "A53_7", "low_priority"}, {39, "write", 2, "A53_7", "notify_resp"}, {40, "read", 2, "ICSSG_0", "notify"}, {41, "read", 7, "ICSSG_0", "response"}, {42, "write", 2, "ICSSG_0", "high_priority"}, {43, "write", 5, "ICSSG_0", "low_priority"}, {44, "write", 2, "ICSSG_0", "notify_resp"}, {45, "read", 2, "ICSSG_1", "notify"}, {46, "read", 4, "ICSSG_1", "response"}, {47, "write", 2, "ICSSG_1", "high_priority"}, {48, "write", 2, "ICSSG_1", "low_priority"}, {49, "write", 2, "ICSSG_1", "notify_resp"}, {50, "read", 2, "ICSSG_2", "notify"}, {51, "read", 4, "ICSSG_2", "response"}, {52, "write", 2, "ICSSG_2", "high_priority"}, {53, "write", 2, "ICSSG_2", "low_priority"}, {54, "write", 2, "ICSSG_2", "notify_resp"}, {55, "read", 2, "GPU_0", "notify"}, {56, "read", 7, "GPU_0", "response"}, {57, "write", 2, "GPU_0", "high_priority"}, {58, "write", 5, "GPU_0", "low_priority"}, {59, "write", 2, "GPU_0", "notify_resp"}, {60, "read", 2, "GPU_1", "notify"}, {61, "read", 5, "GPU_1", "response"}, {62, "write", 2, "GPU_1", "high_priority"}, {63, "write", 3, "GPU_1", "low_priority"}, {64, "write", 2, "GPU_1", "notify_resp"}, }; struct ti_sci_sec_proxy_info am65x_mcu_sp_info[] = { {0, "read", 2, "R5_0", "notify"}, {1, "read", 20, "R5_0", "response"}, {2, "write", 10, "R5_0", "high_priority"}, {3, "write", 10, "R5_0", "low_priority"}, {4, "write", 2, "R5_0", "notify_resp"}, {5, "read", 2, "R5_1", "notify"}, {6, "read", 20, "R5_1", "response"}, {7, "write", 10, "R5_1", "high_priority"}, {8, "write", 10, "R5_1", "low_priority"}, {9, "write", 2, "R5_1", "notify_resp"}, {10, "read", 1, "R5_2", "notify"}, {11, "read", 2, "R5_2", "response"}, {12, "write", 1, "R5_2", "high_priority"}, {13, "write", 1, "R5_2", "low_priority"}, {14, "write", 1, "R5_2", "notify_resp"}, {15, "read", 1, "R5_3", "notify"}, {16, "read", 2, "R5_3", "response"}, {17, "write", 1, "R5_3", "high_priority"}, {18, "write", 1, "R5_3", "low_priority"}, {19, "write", 1, "R5_3", "notify_resp"}, }; k3conf_0.3/soc/am65x/am65x_processors_info.h0000664000175000017500000000350614504336513015705 0ustar /* * AM65X Processor Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM65X_PROCESSOR_INFO_H #define __AM65X_PROCESSOR_INFO_H #define AM65X_MAX_PROCESSORS_IDS 6 extern struct ti_sci_processors_info am65x_processors_info[]; #endif /* __AM65X_PROCESSOR_INFO_H */ k3conf_0.3/soc/am65x/am65x_clocks_info.h0000664000175000017500000000345614504336513014765 0ustar /* * AM65X Clocks Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM65X_CLOCKS_INFO_H #define __AM65X_CLOCKS_INFO_H #define AM65X_MAX_CLOCKS 1145 extern struct ti_sci_clocks_info am65x_clocks_info[]; #endif /* __AM65X_CLOCKS_INFO_H */ k3conf_0.3/soc/am65x/am65x_clocks_info.c0000664000175000017500000033075014375734376014777 0ustar /* * AM65X Clocks Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_clocks_info am65x_clocks_info[] = { {157, 0, "DEV_BOARD0_BUS_SCL3_IN", "Input clock"}, {157, 1, "DEV_BOARD0_BUS_SCL2_IN", "Input clock"}, {157, 2, "DEV_BOARD0_BUS_SCL1_IN", "Input clock"}, {157, 3, "DEV_BOARD0_BUS_SCL0_IN", "Input clock"}, {157, 4, "DEV_BOARD0_BUS_PRG2_RGMII2_TCLK_IN", "Input clock"}, {157, 5, "DEV_BOARD0_BUS_MCU_OSPI1CLK_IN", "Input clock"}, {157, 6, "DEV_BOARD0_BUS_PRG1_RGMII1_TCLK_IN", "Input clock"}, {157, 7, "DEV_BOARD0_BUS_REFCLK1P_IN", "Input muxed clock"}, {157, 8, "DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN"}, {157, 9, "DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN"}, {157, 10, "DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN"}, {157, 11, "DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN"}, {157, 12, "DEV_BOARD0_BUS_MCU_OSPI1LBCLKO_IN", "Input clock"}, {157, 13, "DEV_BOARD0_BUS_MCU_OBSCLK_IN", "Input clock"}, {157, 14, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, {157, 15, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, {157, 16, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, {157, 17, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_CLKOUT_CLK_DUP0", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, {157, 18, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, {157, 19, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, {157, 20, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, {157, 21, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, {157, 22, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, {157, 23, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, {157, 24, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, {157, 25, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, {157, 26, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, {157, 27, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, {157, 28, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK_DUP0", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, {157, 29, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"}, {157, 30, "DEV_BOARD0_BUS_PRG2_RGMII1_TCLK_IN", "Input clock"}, {157, 31, "DEV_BOARD0_BUS_REFCLK1M_IN", "Input muxed clock"}, {157, 32, "DEV_BOARD0_BUS_REFCLK1M_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1M_IN"}, {157, 33, "DEV_BOARD0_BUS_REFCLK1M_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1M_IN"}, {157, 34, "DEV_BOARD0_BUS_REFCLK1M_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1M_IN"}, {157, 35, "DEV_BOARD0_BUS_REFCLK1M_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1M_IN"}, {157, 36, "DEV_BOARD0_BUS_OBSCLK_IN", "Input clock"}, {157, 37, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, {157, 38, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, {157, 39, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, {157, 40, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, {157, 41, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, {157, 42, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, {157, 43, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_WRAP_MAIN_4_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, {157, 44, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLM_WRAP_MAIN_6_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, {157, 45, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, {157, 46, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, {157, 47, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, {157, 48, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLM_WRAP_MAIN_7_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, {157, 49, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, {157, 50, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, {157, 51, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, {157, 52, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"}, {157, 53, "DEV_BOARD0_BUS_PRG0_RGMII1_TCLK_IN", "Input clock"}, {157, 54, "DEV_BOARD0_BUS_MCU_OSPI0CLK_IN", "Input clock"}, {157, 55, "DEV_BOARD0_BUS_DSS0PCLK_IN", "Input clock"}, {157, 56, "DEV_BOARD0_BUS_PRG0_RGMII2_TCLK_IN", "Input clock"}, {157, 57, "DEV_BOARD0_BUS_WKUP_SCL0_IN", "Input clock"}, {157, 58, "DEV_BOARD0_BUS_REFCLK0P_IN", "Input muxed clock"}, {157, 59, "DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN"}, {157, 60, "DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN"}, {157, 61, "DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN"}, {157, 62, "DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN"}, {157, 63, "DEV_BOARD0_BUS_REFCLK0M_IN", "Input muxed clock"}, {157, 64, "DEV_BOARD0_BUS_REFCLK0M_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0M_IN"}, {157, 65, "DEV_BOARD0_BUS_REFCLK0M_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0M_IN"}, {157, 66, "DEV_BOARD0_BUS_REFCLK0M_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0M_IN"}, {157, 67, "DEV_BOARD0_BUS_REFCLK0M_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0M_IN"}, {157, 68, "DEV_BOARD0_BUS_MCU_OSPI0LBCLKO_IN", "Input clock"}, {157, 69, "DEV_BOARD0_BUS_MCU_CLKOUT_IN", "Input muxed clock"}, {157, 70, "DEV_BOARD0_BUS_MCU_CLKOUT_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_BOARD0_BUS_MCU_CLKOUT_IN"}, {157, 71, "DEV_BOARD0_BUS_MCU_CLKOUT_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK10", "Parent input clock option to DEV_BOARD0_BUS_MCU_CLKOUT_IN"}, {157, 72, "DEV_BOARD0_BUS_MCU_SCL0_IN", "Input clock"}, {157, 73, "DEV_BOARD0_BUS_SYSCLKOUT_IN", "Input clock"}, {157, 74, "DEV_BOARD0_BUS_MCU_SYSCLKOUT_IN", "Input clock"}, {157, 75, "DEV_BOARD0_BUS_PRG1_RGMII1_RCLK_OUT", "Output clock"}, {157, 76, "DEV_BOARD0_BUS_PRG1_RGMII2_RCLK_OUT", "Output clock"}, {157, 77, "DEV_BOARD0_BUS_GPMCCLK_OUT", "Output clock"}, {157, 78, "DEV_BOARD0_BUS_MCASP2AHCLKX_OUT", "Output clock"}, {157, 79, "DEV_BOARD0_BUS_MCASP2AHCLKR_OUT", "Output clock"}, {157, 80, "DEV_BOARD0_BUS_PRG2_RGMII2_RCLK_OUT", "Output clock"}, {157, 81, "DEV_BOARD0_BUS_CPTS_RFT_CLK_OUT", "Output clock"}, {157, 82, "DEV_BOARD0_BUS_MCASP0ACLKR_OUT", "Output clock"}, {157, 83, "DEV_BOARD0_BUS_MCASP0ACLKX_OUT", "Output clock"}, {157, 84, "DEV_BOARD0_BUS_EXT_REFCLK1_OUT", "Output clock"}, {157, 85, "DEV_BOARD0_BUS_PRG0_RGMII2_RCLK_OUT", "Output clock"}, {157, 86, "DEV_BOARD0_BUS_MCU_OSPI0DQS_OUT", "Output clock"}, {157, 87, "DEV_BOARD0_BUS_USB0REFCLKP_OUT", "Output clock"}, {157, 88, "DEV_BOARD0_BUS_DSS0EXTPCLKIN_OUT", "Output clock"}, {157, 89, "DEV_BOARD0_BUS_SPI1CLK_OUT", "Output clock"}, {157, 90, "DEV_BOARD0_BUS_MCASP2ACLKR_OUT", "Output clock"}, {157, 91, "DEV_BOARD0_BUS_MCASP1ACLKX_OUT", "Output clock"}, {157, 92, "DEV_BOARD0_BUS_MCASP1ACLKR_OUT", "Output clock"}, {157, 93, "DEV_BOARD0_BUS_MCASP2ACLKX_OUT", "Output clock"}, {157, 94, "DEV_BOARD0_BUS_MCU_RMII1_REFCLK_OUT", "Output clock"}, {157, 95, "DEV_BOARD0_BUS_MCU_CPTS_RFT_CLK_OUT", "Output clock"}, {157, 96, "DEV_BOARD0_BUS_MCU_RGMII1_TCLK_OUT", "Output clock"}, {157, 97, "DEV_BOARD0_BUS_MCU_SPI0CLK_OUT", "Output clock"}, {157, 98, "DEV_BOARD0_BUS_MCU_SPI1CLK_OUT", "Output clock"}, {157, 99, "DEV_BOARD0_BUS_PRG0_RGMII1_RCLK_OUT", "Output clock"}, {157, 100, "DEV_BOARD0_BUS_SPI2CLK_OUT", "Output clock"}, {157, 101, "DEV_BOARD0_BUS_WKUP_TCK_OUT", "Output clock"}, {157, 102, "DEV_BOARD0_BUS_SPI3CLK_OUT", "Output clock"}, {157, 103, "DEV_BOARD0_BUS_USB0REFCLKM_OUT", "Output clock"}, {157, 104, "DEV_BOARD0_BUS_MCU_RGMII1_RCLK_OUT", "Output clock"}, {157, 105, "DEV_BOARD0_BUS_MCASP0AHCLKR_OUT", "Output clock"}, {157, 106, "DEV_BOARD0_BUS_MCU_EXT_REFCLK0_OUT", "Output clock"}, {157, 107, "DEV_BOARD0_BUS_MCASP0AHCLKX_OUT", "Output clock"}, {157, 108, "DEV_BOARD0_BUS_CCDC0_PCLK_OUT", "Output clock"}, {157, 109, "DEV_BOARD0_HFOSC1_CLK_OUT", "Output clock"}, {157, 110, "DEV_BOARD0_BUS_MCU_OSPI1DQS_OUT", "Output clock"}, {157, 111, "DEV_BOARD0_BUS_MCASP1AHCLKX_OUT", "Output clock"}, {157, 112, "DEV_BOARD0_BUS_PCIE1REFCLKM_OUT", "Output clock"}, {157, 113, "DEV_BOARD0_BUS_MCASP1AHCLKR_OUT", "Output clock"}, {157, 114, "DEV_BOARD0_BUS_PCIE1REFCLKP_OUT", "Output clock"}, {157, 115, "DEV_BOARD0_BUS_PRG2_RGMII1_RCLK_OUT", "Output clock"}, {157, 116, "DEV_BOARD0_BUS_SPI0CLK_OUT", "Output clock"}, {157, 117, "DEV_BOARD0_BUS_MCU_HYPERBUS_CLK_IN", "Input clock"}, {157, 118, "DEV_BOARD0_BUS_MCU_HYPERBUS_NCLK_IN", "Input clock"}, {2, 0, "DEV_CAL0_BUS_CLK", "Input clock"}, {2, 1, "DEV_CAL0_BUS_CP_C_CLK", "Input clock"}, {82, 0, "DEV_CBASS0_BUS_MAIN_SYSCLK0_2_CLK", "Input clock"}, {82, 1, "DEV_CBASS0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"}, {83, 0, "DEV_CBASS_DEBUG0_BUS_MAIN_SYSCLK0_2_CLK", "Input clock"}, {83, 1, "DEV_CBASS_DEBUG0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"}, {84, 0, "DEV_CBASS_FW0_BUS_MAIN_SYSCLK0_2_CLK", "Input clock"}, {84, 1, "DEV_CBASS_FW0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"}, {85, 0, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK", "Input muxed clock"}, {85, 1, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"}, {85, 2, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"}, {85, 3, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"}, {85, 4, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"}, {85, 5, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"}, {85, 6, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"}, {85, 7, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"}, {85, 8, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"}, {85, 9, "DEV_CBASS_INFRA0_BUS_MAIN_SYSCLK0_2_CLK", "Input clock"}, {85, 10, "DEV_CBASS_INFRA0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"}, {66, 0, "DEV_CCDEBUGSS0_BUS_ATB1_CLK", "Input clock"}, {66, 1, "DEV_CCDEBUGSS0_BUS_ATB0_CLK", "Input clock"}, {66, 2, "DEV_CCDEBUGSS0_BUS_SYS_CLK", "Input clock"}, {66, 3, "DEV_CCDEBUGSS0_BUS_DBG_CLK", "Input clock"}, {66, 4, "DEV_CCDEBUGSS0_BUS_CFG_CLK", "Input clock"}, {3, 0, "DEV_CMPEVENT_INTRTR0_BUS_INTR_CLK", "Input clock"}, {202, 0, "DEV_COMPUTE_CLUSTER_A53_0_BUS_ARM0_CLK", "Input clock"}, {203, 0, "DEV_COMPUTE_CLUSTER_A53_1_BUS_ARM0_CLK", "Input clock"}, {204, 0, "DEV_COMPUTE_CLUSTER_A53_2_BUS_ARM1_CLK", "Input clock"}, {205, 0, "DEV_COMPUTE_CLUSTER_A53_3_BUS_ARM1_CLK", "Input clock"}, {198, 0, "DEV_COMPUTE_CLUSTER_CPAC0_BUS_ARM0_CLK", "Input clock"}, {200, 0, "DEV_COMPUTE_CLUSTER_CPAC1_BUS_ARM1_CLK", "Input clock"}, {196, 0, "DEV_COMPUTE_CLUSTER_MSMC0_BUS_TB_SOC_VBUSP_DMSC_CLK", "Input clock"}, {196, 1, "DEV_COMPUTE_CLUSTER_MSMC0_BUS_TB_SOC_VBUSP_DBG_CLK", "Input clock"}, {196, 2, "DEV_COMPUTE_CLUSTER_MSMC0_BUS_MSMC_CLK", "Input clock"}, {196, 3, "DEV_COMPUTE_CLUSTER_MSMC0_BUS_TB_SOC_VBUSP_CFG_CLK", "Input clock"}, {196, 4, "DEV_COMPUTE_CLUSTER_MSMC0_BUS_TB_SOC_GIC_CLK", "Input clock"}, {6, 0, "DEV_CPT2_AGGR0_BUS_VCLK_CLK", "Input clock"}, {213, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0_BUS_VBUS_CLK", "Input clock"}, {213, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0_BUS_PROBE_CLK", "Input clock"}, {214, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2_BUS_VBUS_CLK", "Input clock"}, {214, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2_BUS_PROBE_CLK", "Input clock"}, {211, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5_BUS_VBUS_CLK", "Input clock"}, {211, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5_BUS_PROBE_CLK", "Input clock"}, {212, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6_BUS_VBUS_CLK", "Input clock"}, {212, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6_BUS_PROBE_CLK", "Input clock"}, {209, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3_BUS_VBUS_CLK", "Input clock"}, {209, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3_BUS_PROBE_CLK", "Input clock"}, {206, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4_BUS_VBUS_CLK", "Input clock"}, {206, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4_BUS_PROBE_CLK", "Input clock"}, {208, 0, "DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0_BUS_VBUS_CLK", "Input clock"}, {208, 1, "DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0_BUS_PROBE_CLK", "Input clock"}, {215, 0, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2_BUS_VBUS_CLK", "Input clock"}, {215, 1, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2_BUS_PROBE_CLK", "Input clock"}, {207, 0, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3_BUS_VBUS_CLK", "Input clock"}, {207, 1, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3_BUS_PROBE_CLK", "Input clock"}, {210, 0, "DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1_BUS_VBUS_CLK", "Input clock"}, {210, 1, "DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1_BUS_PROBE_CLK", "Input clock"}, {99, 0, "DEV_CTRL_MMR0_BUS_VBUSP_CLK", "Input clock"}, {9, 0, "DEV_DCC0_BUS_DCC_INPUT00_CLK", "Input clock"}, {9, 1, "DEV_DCC0_BUS_DCC_CLKSRC4_CLK", "Input clock"}, {9, 2, "DEV_DCC0_BUS_DCC_CLKSRC3_CLK", "Input clock"}, {9, 3, "DEV_DCC0_BUS_VBUS_CLK", "Input clock"}, {9, 4, "DEV_DCC0_BUS_DCC_CLKSRC1_CLK", "Input clock"}, {9, 5, "DEV_DCC0_BUS_DCC_INPUT01_CLK", "Input clock"}, {9, 6, "DEV_DCC0_BUS_DCC_CLKSRC5_CLK", "Input clock"}, {9, 7, "DEV_DCC0_BUS_DCC_INPUT02_CLK", "Input clock"}, {9, 8, "DEV_DCC0_BUS_DCC_CLKSRC0_CLK", "Input clock"}, {9, 9, "DEV_DCC0_BUS_DCC_CLKSRC6_CLK", "Input clock"}, {9, 10, "DEV_DCC0_BUS_DCC_INPUT10_CLK", "Input clock"}, {9, 11, "DEV_DCC0_BUS_DCC_CLKSRC2_CLK", "Input clock"}, {10, 0, "DEV_DCC1_BUS_DCC_INPUT00_CLK", "Input clock"}, {10, 1, "DEV_DCC1_BUS_DCC_CLKSRC7_CLK", "Input clock"}, {10, 2, "DEV_DCC1_BUS_DCC_CLKSRC4_CLK", "Input clock"}, {10, 3, "DEV_DCC1_BUS_DCC_CLKSRC3_CLK", "Input clock"}, {10, 4, "DEV_DCC1_BUS_VBUS_CLK", "Input clock"}, {10, 5, "DEV_DCC1_BUS_DCC_CLKSRC1_CLK", "Input clock"}, {10, 6, "DEV_DCC1_BUS_DCC_INPUT01_CLK", "Input clock"}, {10, 7, "DEV_DCC1_BUS_DCC_CLKSRC5_CLK", "Input clock"}, {10, 8, "DEV_DCC1_BUS_DCC_INPUT02_CLK", "Input clock"}, {10, 9, "DEV_DCC1_BUS_DCC_CLKSRC0_CLK", "Input clock"}, {10, 10, "DEV_DCC1_BUS_DCC_CLKSRC6_CLK", "Input clock"}, {10, 11, "DEV_DCC1_BUS_DCC_INPUT10_CLK", "Input clock"}, {10, 12, "DEV_DCC1_BUS_DCC_CLKSRC2_CLK", "Input clock"}, {11, 0, "DEV_DCC2_BUS_DCC_INPUT00_CLK", "Input clock"}, {11, 1, "DEV_DCC2_BUS_DCC_CLKSRC7_CLK", "Input clock"}, {11, 2, "DEV_DCC2_BUS_DCC_CLKSRC4_CLK", "Input clock"}, {11, 3, "DEV_DCC2_BUS_DCC_CLKSRC3_CLK", "Input clock"}, {11, 4, "DEV_DCC2_BUS_VBUS_CLK", "Input clock"}, {11, 5, "DEV_DCC2_BUS_DCC_CLKSRC1_CLK", "Input clock"}, {11, 6, "DEV_DCC2_BUS_DCC_INPUT01_CLK", "Input clock"}, {11, 7, "DEV_DCC2_BUS_DCC_CLKSRC5_CLK", "Input clock"}, {11, 8, "DEV_DCC2_BUS_DCC_INPUT02_CLK", "Input clock"}, {11, 9, "DEV_DCC2_BUS_DCC_CLKSRC0_CLK", "Input clock"}, {11, 10, "DEV_DCC2_BUS_DCC_CLKSRC6_CLK", "Input clock"}, {11, 11, "DEV_DCC2_BUS_DCC_INPUT10_CLK", "Input clock"}, {11, 12, "DEV_DCC2_BUS_DCC_CLKSRC2_CLK", "Input clock"}, {12, 0, "DEV_DCC3_BUS_DCC_INPUT00_CLK", "Input clock"}, {12, 1, "DEV_DCC3_BUS_DCC_CLKSRC7_CLK", "Input clock"}, {12, 2, "DEV_DCC3_BUS_DCC_CLKSRC4_CLK", "Input clock"}, {12, 3, "DEV_DCC3_BUS_DCC_CLKSRC3_CLK", "Input clock"}, {12, 4, "DEV_DCC3_BUS_VBUS_CLK", "Input clock"}, {12, 5, "DEV_DCC3_BUS_DCC_CLKSRC1_CLK", "Input clock"}, {12, 6, "DEV_DCC3_BUS_DCC_INPUT01_CLK", "Input clock"}, {12, 7, "DEV_DCC3_BUS_DCC_CLKSRC5_CLK", "Input clock"}, {12, 8, "DEV_DCC3_BUS_DCC_INPUT02_CLK", "Input clock"}, {12, 9, "DEV_DCC3_BUS_DCC_CLKSRC0_CLK", "Input clock"}, {12, 10, "DEV_DCC3_BUS_DCC_INPUT10_CLK", "Input clock"}, {12, 11, "DEV_DCC3_BUS_DCC_CLKSRC2_CLK", "Input clock"}, {13, 0, "DEV_DCC4_BUS_DCC_INPUT00_CLK", "Input clock"}, {13, 1, "DEV_DCC4_BUS_DCC_CLKSRC7_CLK", "Input clock"}, {13, 2, "DEV_DCC4_BUS_DCC_CLKSRC4_CLK", "Input clock"}, {13, 3, "DEV_DCC4_BUS_DCC_CLKSRC3_CLK", "Input clock"}, {13, 4, "DEV_DCC4_BUS_VBUS_CLK", "Input clock"}, {13, 5, "DEV_DCC4_BUS_DCC_INPUT01_CLK", "Input clock"}, {13, 6, "DEV_DCC4_BUS_DCC_CLKSRC5_CLK", "Input clock"}, {13, 7, "DEV_DCC4_BUS_DCC_INPUT02_CLK", "Input clock"}, {13, 8, "DEV_DCC4_BUS_DCC_CLKSRC0_CLK", "Input clock"}, {13, 9, "DEV_DCC4_BUS_DCC_CLKSRC6_CLK", "Input clock"}, {13, 10, "DEV_DCC4_BUS_DCC_INPUT10_CLK", "Input clock"}, {13, 11, "DEV_DCC4_BUS_DCC_CLKSRC2_CLK", "Input clock"}, {14, 0, "DEV_DCC5_BUS_DCC_INPUT00_CLK", "Input clock"}, {14, 1, "DEV_DCC5_BUS_DCC_CLKSRC7_CLK", "Input clock"}, {14, 2, "DEV_DCC5_BUS_DCC_CLKSRC4_CLK", "Input clock"}, {14, 3, "DEV_DCC5_BUS_DCC_CLKSRC3_CLK", "Input clock"}, {14, 4, "DEV_DCC5_BUS_VBUS_CLK", "Input clock"}, {14, 5, "DEV_DCC5_BUS_DCC_CLKSRC1_CLK", "Input clock"}, {14, 6, "DEV_DCC5_BUS_DCC_INPUT01_CLK", "Input clock"}, {14, 7, "DEV_DCC5_BUS_DCC_CLKSRC5_CLK", "Input clock"}, {14, 8, "DEV_DCC5_BUS_DCC_INPUT02_CLK", "Input clock"}, {14, 9, "DEV_DCC5_BUS_DCC_CLKSRC0_CLK", "Input clock"}, {14, 10, "DEV_DCC5_BUS_DCC_CLKSRC6_CLK", "Input clock"}, {14, 11, "DEV_DCC5_BUS_DCC_INPUT10_CLK", "Input clock"}, {14, 12, "DEV_DCC5_BUS_DCC_CLKSRC2_CLK", "Input clock"}, {15, 0, "DEV_DCC6_BUS_DCC_INPUT00_CLK", "Input clock"}, {15, 1, "DEV_DCC6_BUS_DCC_CLKSRC7_CLK", "Input clock"}, {15, 2, "DEV_DCC6_BUS_DCC_CLKSRC4_CLK", "Input clock"}, {15, 3, "DEV_DCC6_BUS_DCC_CLKSRC3_CLK", "Input clock"}, {15, 4, "DEV_DCC6_BUS_VBUS_CLK", "Input clock"}, {15, 5, "DEV_DCC6_BUS_DCC_CLKSRC1_CLK", "Input clock"}, {15, 6, "DEV_DCC6_BUS_DCC_INPUT01_CLK", "Input clock"}, {15, 7, "DEV_DCC6_BUS_DCC_CLKSRC5_CLK", "Input clock"}, {15, 8, "DEV_DCC6_BUS_DCC_INPUT02_CLK", "Input clock"}, {15, 9, "DEV_DCC6_BUS_DCC_CLKSRC0_CLK", "Input clock"}, {15, 10, "DEV_DCC6_BUS_DCC_CLKSRC6_CLK", "Input clock"}, {15, 11, "DEV_DCC6_BUS_DCC_INPUT10_CLK", "Input clock"}, {15, 12, "DEV_DCC6_BUS_DCC_CLKSRC2_CLK", "Input clock"}, {16, 0, "DEV_DCC7_BUS_DCC_INPUT00_CLK", "Input clock"}, {16, 1, "DEV_DCC7_BUS_DCC_CLKSRC7_CLK", "Input clock"}, {16, 2, "DEV_DCC7_BUS_DCC_CLKSRC4_CLK", "Input clock"}, {16, 3, "DEV_DCC7_BUS_DCC_CLKSRC3_CLK", "Input clock"}, {16, 4, "DEV_DCC7_BUS_VBUS_CLK", "Input clock"}, {16, 5, "DEV_DCC7_BUS_DCC_CLKSRC1_CLK", "Input clock"}, {16, 6, "DEV_DCC7_BUS_DCC_INPUT01_CLK", "Input clock"}, {16, 7, "DEV_DCC7_BUS_DCC_CLKSRC5_CLK", "Input clock"}, {16, 8, "DEV_DCC7_BUS_DCC_INPUT02_CLK", "Input clock"}, {16, 9, "DEV_DCC7_BUS_DCC_CLKSRC0_CLK", "Input clock"}, {16, 10, "DEV_DCC7_BUS_DCC_CLKSRC6_CLK", "Input clock"}, {16, 11, "DEV_DCC7_BUS_DCC_INPUT10_CLK", "Input clock"}, {16, 12, "DEV_DCC7_BUS_DCC_CLKSRC2_CLK", "Input clock"}, {20, 0, "DEV_DDRSS0_BUS_DDRSS_VBUS_CLK", "Input clock"}, {20, 1, "DEV_DDRSS0_BUS_DDRSS_BYP_4X_CLK", "Input clock"}, {20, 2, "DEV_DDRSS0_BUS_DDRSS_CTL_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"}, {20, 3, "DEV_DDRSS0_BUS_DDRSS_TCLK", "Input clock"}, {20, 4, "DEV_DDRSS0_BUS_DDRSS_PHY_CTL_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"}, {20, 5, "DEV_DDRSS0_BUS_DDRSS_PHY_CTL_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"}, {20, 6, "DEV_DDRSS0_BUS_DDRSS_CFG_CLK", "Input clock"}, {20, 7, "DEV_DDRSS0_BUS_DDRSS_CTL_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"}, {20, 8, "DEV_DDRSS0_BUS_DDRSS_BYP_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"}, {20, 9, "DEV_DDRSS0_BUS_DDRSS_BYP_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"}, {68, 0, "DEV_DEBUGSS0_BUS_ATB1_CLK", "Input clock"}, {68, 1, "DEV_DEBUGSS0_BUS_ATB5_CLK", "Input clock"}, {68, 2, "DEV_DEBUGSS0_BUS_ATB0_CLK", "Input clock"}, {68, 3, "DEV_DEBUGSS0_BUS_SYS_CLK", "Input clock"}, {68, 4, "DEV_DEBUGSS0_BUS_ATB4_CLK", "Input clock"}, {68, 5, "DEV_DEBUGSS0_BUS_CFG_CLK", "Input clock"}, {68, 6, "DEV_DEBUGSS0_BUS_ATB2_CLK", "Input clock"}, {68, 7, "DEV_DEBUGSS0_BUS_DBG_CLK", "Input clock"}, {68, 8, "DEV_DEBUGSS0_BUS_ATB3_CLK", "Input clock"}, {21, 0, "DEV_DEBUGSS_WRAP0_BUS_JTAG_TCK", "Input clock"}, {21, 1, "DEV_DEBUGSS_WRAP0_BUS_ATB_CLK", "Input clock"}, {21, 2, "DEV_DEBUGSS_WRAP0_BUS_TREXPT_CLK", "Input clock"}, {21, 3, "DEV_DEBUGSS_WRAP0_BUS_CORE_CLK", "Input clock"}, {81, 0, "DEV_DEBUGSUSPENDRTR0_BUS_INTR_CLK", "Input clock"}, {117, 0, "DEV_DFTSS0_BUS_VBUSP_CLK_CLK", "Input clock"}, {67, 0, "DEV_DSS0_BUS_DPI_0_IN_CLK_BUS_IN1_CLOCKDIVIDER_DSS_BUS_OUT0", "Input clock"}, {67, 1, "DEV_DSS0_BUS_DSS_FUNC_CLK", "Input clock"}, {67, 2, "DEV_DSS0_BUS_DPI_1_IN_CLK", "Input muxed clock"}, {67, 3, "DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_CLOCKDIVIDER_DSS_BUS_OUT07", "Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK"}, {67, 4, "DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_BOARD_0_BUS_DSS0EXTPCLKIN_OUT", "Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK"}, {67, 5, "DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_CLOCKDIVIDER_DSS_BUS_OUT1", "Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK"}, {67, 6, "DEV_DSS0_BUS_DPI_0_IN_CLK_BUS_IN0_CLOCKDIVIDER_DSS_BUS_OUT0", "Input clock"}, {67, 7, "DEV_DSS0_BUS_DPI_1_OUT_CLK", "Output clock"}, {39, 0, "DEV_ECAP0_BUS_VBUS_CLK", "Input clock"}, {86, 0, "DEV_ECC_AGGR0_BUS_AGGR_CLK", "Input clock"}, {87, 0, "DEV_ECC_AGGR1_BUS_AGGR_CLK", "Input clock"}, {88, 0, "DEV_ECC_AGGR2_BUS_AGGR_CLK", "Input clock"}, {69, 0, "DEV_EFUSE0_BUS_VBUSP_PLL_CLK_CLK", "Input clock"}, {69, 1, "DEV_EFUSE0_BUS_EFC1_CTL_FCLK", "Output clock"}, {69, 2, "DEV_EFUSE0_BUS_EFC0_CTL_FCLK", "Output clock"}, {40, 0, "DEV_EHRPWM0_BUS_VBUSP_CLK", "Input clock"}, {41, 0, "DEV_EHRPWM1_BUS_VBUSP_CLK", "Input clock"}, {42, 0, "DEV_EHRPWM2_BUS_VBUSP_CLK", "Input clock"}, {43, 0, "DEV_EHRPWM3_BUS_VBUSP_CLK", "Input clock"}, {44, 0, "DEV_EHRPWM4_BUS_VBUSP_CLK", "Input clock"}, {45, 0, "DEV_EHRPWM5_BUS_VBUSP_CLK", "Input clock"}, {46, 0, "DEV_ELM0_BUS_VBUSP_CLK", "Input clock"}, {49, 0, "DEV_EQEP0_BUS_VBUS_CLK", "Input clock"}, {50, 0, "DEV_EQEP1_BUS_VBUS_CLK", "Input clock"}, {51, 0, "DEV_EQEP2_BUS_VBUS_CLK", "Input clock"}, {52, 0, "DEV_ESM0_BUS_CLK", "Input clock"}, {56, 0, "DEV_GIC0_BUS_VCLK_CLK", "Input clock"}, {57, 0, "DEV_GPIO0_BUS_MMR_CLK", "Input clock"}, {58, 0, "DEV_GPIO1_BUS_MMR_CLK", "Input clock"}, {100, 0, "DEV_GPIOMUX_INTRTR0_BUS_INTR_CLK", "Input clock"}, {60, 0, "DEV_GPMC0_BUS_FUNC_CLK", "Input muxed clock"}, {60, 1, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"}, {60, 2, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK3", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"}, {60, 3, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK2", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"}, {60, 4, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_BUS_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"}, {60, 5, "DEV_GPMC0_BUS_PI_GPMC_RET_CLK", "Input clock"}, {60, 6, "DEV_GPMC0_BUS_VBUSP_CLK", "Input clock"}, {60, 7, "DEV_GPMC0_BUS_PO_GPMC_DEV_CLK", "Output clock"}, {65, 0, "DEV_GPU0_BUS_MEM_CLK", "Input clock"}, {65, 1, "DEV_GPU0_BUS_HYD_CORE_CLK", "Input clock"}, {65, 2, "DEV_GPU0_BUS_SGX_CORE_CLK", "Input clock"}, {65, 3, "DEV_GPU0_BUS_SYS_CLK", "Input clock"}, {232, 0, "DEV_GS80PRG_MCU_WRAP_WKUP_0_BUS_OSC_CLK", "Input clock"}, {232, 1, "DEV_GS80PRG_MCU_WRAP_WKUP_0_BUS_CLK", "Input clock"}, {231, 0, "DEV_GS80PRG_SOC_WRAP_WKUP_0_BUS_OSC_CLK", "Input clock"}, {231, 1, "DEV_GS80PRG_SOC_WRAP_WKUP_0_BUS_CLK", "Input clock"}, {61, 0, "DEV_GTC0_BUS_VBUSP_CLK", "Input muxed clock"}, {61, 1, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"}, {61, 2, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"}, {61, 3, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"}, {61, 4, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"}, {61, 5, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"}, {61, 6, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"}, {61, 7, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"}, {61, 8, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"}, {110, 0, "DEV_I2C0_BUS_CLK", "Input clock"}, {110, 1, "DEV_I2C0_BUS_PISYS_CLK", "Input clock"}, {110, 2, "DEV_I2C0_BUS_PISCL", "Output clock"}, {111, 0, "DEV_I2C1_BUS_CLK", "Input clock"}, {111, 1, "DEV_I2C1_BUS_PISYS_CLK", "Input clock"}, {111, 2, "DEV_I2C1_BUS_PISCL", "Output clock"}, {112, 0, "DEV_I2C2_BUS_CLK", "Input clock"}, {112, 1, "DEV_I2C2_BUS_PISYS_CLK", "Input clock"}, {112, 2, "DEV_I2C2_BUS_PISCL", "Output clock"}, {113, 0, "DEV_I2C3_BUS_CLK", "Input clock"}, {113, 1, "DEV_I2C3_BUS_PISYS_CLK", "Input clock"}, {113, 2, "DEV_I2C3_BUS_PISCL", "Output clock"}, {217, 0, "DEV_K3_ARM_ATB_FUNNEL_3_32_MCU_0_BUS_DBG_CLK", "Input clock"}, {97, 0, "DEV_MAIN2MCU_LVL_INTRTR0_BUS_INTR_CLK", "Input clock"}, {98, 0, "DEV_MAIN2MCU_PLS_INTRTR0_BUS_INTR_CLK", "Input clock"}, {104, 0, "DEV_MCASP0_BUS_AUX_CLK", "Input muxed clock"}, {104, 1, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"}, {104, 2, "DEV_MCASP0_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"}, {104, 3, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"}, {104, 4, "DEV_MCASP0_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"}, {104, 5, "DEV_MCASP0_BUS_AUX_CLK_PARENT_CLOCKDIVIDER_MCASP_ARM1_PLL_DIV_BUS_OUT0", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"}, {104, 6, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"}, {104, 7, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"}, {104, 8, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"}, {104, 9, "DEV_MCASP0_BUS_VBUSP_CLK", "Input clock"}, {104, 10, "DEV_MCASP0_BUS_MCASP_AHCLKX_PIN", "Input clock"}, {104, 11, "DEV_MCASP0_BUS_MCASP_AHCLKR_PIN", "Input clock"}, {105, 0, "DEV_MCASP1_BUS_AUX_CLK", "Input muxed clock"}, {105, 1, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"}, {105, 2, "DEV_MCASP1_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"}, {105, 3, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"}, {105, 4, "DEV_MCASP1_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"}, {105, 5, "DEV_MCASP1_BUS_AUX_CLK_PARENT_CLOCKDIVIDER_MCASP_ARM1_PLL_DIV_BUS_OUT1", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"}, {105, 6, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"}, {105, 7, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"}, {105, 8, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"}, {105, 9, "DEV_MCASP1_BUS_VBUSP_CLK", "Input clock"}, {105, 10, "DEV_MCASP1_BUS_MCASP_AHCLKX_PIN", "Input clock"}, {105, 11, "DEV_MCASP1_BUS_MCASP_AHCLKR_PIN", "Input clock"}, {106, 0, "DEV_MCASP2_BUS_AUX_CLK", "Input muxed clock"}, {106, 1, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"}, {106, 2, "DEV_MCASP2_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"}, {106, 3, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"}, {106, 4, "DEV_MCASP2_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"}, {106, 5, "DEV_MCASP2_BUS_AUX_CLK_PARENT_CLOCKDIVIDER_MCASP_ARM1_PLL_DIV_BUS_OUT2", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"}, {106, 6, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"}, {106, 7, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"}, {106, 8, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"}, {106, 9, "DEV_MCASP2_BUS_VBUSP_CLK", "Input clock"}, {106, 10, "DEV_MCASP2_BUS_MCASP_AHCLKX_PIN", "Input clock"}, {106, 11, "DEV_MCASP2_BUS_MCASP_AHCLKR_PIN", "Input clock"}, {137, 0, "DEV_MCSPI0_BUS_IO_CLKSPII_CLK", "Input clock"}, {137, 1, "DEV_MCSPI0_BUS_CLKSPIREF_CLK", "Input clock"}, {137, 2, "DEV_MCSPI0_BUS_VBUSP_CLK", "Input clock"}, {137, 3, "DEV_MCSPI0_BUS_IO_CLKSPIO_CLK", "Output clock"}, {138, 0, "DEV_MCSPI1_BUS_IO_CLKSPII_CLK", "Input clock"}, {138, 1, "DEV_MCSPI1_BUS_CLKSPIREF_CLK", "Input clock"}, {138, 2, "DEV_MCSPI1_BUS_VBUSP_CLK", "Input clock"}, {138, 3, "DEV_MCSPI1_BUS_IO_CLKSPIO_CLK", "Output clock"}, {139, 0, "DEV_MCSPI2_BUS_IO_CLKSPII_CLK", "Input clock"}, {139, 1, "DEV_MCSPI2_BUS_CLKSPIREF_CLK", "Input clock"}, {139, 2, "DEV_MCSPI2_BUS_VBUSP_CLK", "Input clock"}, {139, 3, "DEV_MCSPI2_BUS_IO_CLKSPIO_CLK", "Output clock"}, {140, 0, "DEV_MCSPI3_BUS_IO_CLKSPII_CLK", "Input clock"}, {140, 1, "DEV_MCSPI3_BUS_CLKSPIREF_CLK", "Input clock"}, {140, 2, "DEV_MCSPI3_BUS_VBUSP_CLK", "Input clock"}, {140, 3, "DEV_MCSPI3_BUS_IO_CLKSPIO_CLK", "Output clock"}, {141, 0, "DEV_MCSPI4_BUS_CLKSPIREF_CLK", "Input clock"}, {141, 1, "DEV_MCSPI4_BUS_VBUSP_CLK", "Input clock"}, {0, 0, "DEV_MCU_ADC0_BUS_VBUS_CLK", "Input clock"}, {0, 1, "DEV_MCU_ADC0_BUS_SYS_CLK", "Input clock"}, {0, 2, "DEV_MCU_ADC0_BUS_ADC_CLK", "Input muxed clock"}, {0, 3, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"}, {0, 4, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"}, {0, 5, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"}, {0, 6, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"}, {1, 0, "DEV_MCU_ADC1_BUS_VBUS_CLK", "Input clock"}, {1, 1, "DEV_MCU_ADC1_BUS_SYS_CLK", "Input clock"}, {1, 2, "DEV_MCU_ADC1_BUS_ADC_CLK", "Input muxed clock"}, {1, 3, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"}, {1, 4, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"}, {1, 5, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"}, {1, 6, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"}, {129, 0, "DEV_MCU_ARMSS0_BUS_INTERFACE_CLK", "Input clock"}, {159, 0, "DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_CLK", "Input clock"}, {159, 1, "DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE", "Input muxed clock"}, {159, 2, "DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE"}, {159, 3, "DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK", "Input muxed clock"}, {159, 4, "DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK"}, {159, 5, "DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK"}, {245, 0, "DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_CLK", "Input clock"}, {245, 1, "DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE", "Input muxed clock"}, {245, 2, "DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE"}, {245, 3, "DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK", "Input muxed clock"}, {245, 4, "DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK"}, {245, 5, "DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK"}, {89, 0, "DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_8_CLK", "Input clock"}, {89, 1, "DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_4_CLK", "Input clock"}, {89, 2, "DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_2_CLK", "Input clock"}, {90, 0, "DEV_MCU_CBASS_DEBUG0_BUS_MCU_SYSCLK0_2_CLK", "Input clock"}, {91, 0, "DEV_MCU_CBASS_FW0_BUS_MCU_SYSCLK0_4_CLK", "Input clock"}, {91, 1, "DEV_MCU_CBASS_FW0_BUS_MCU_SYSCLK0_2_CLK", "Input clock"}, {5, 0, "DEV_MCU_CPSW0_BUS_GMII1_MR_CLK", "Input clock"}, {5, 1, "DEV_MCU_CPSW0_BUS_RGMII_MHZ_250_CLK", "Input clock"}, {5, 2, "DEV_MCU_CPSW0_BUS_CPTS_RFT_CLK", "Input clock"}, {5, 3, "DEV_MCU_CPSW0_BUS_GMII1_MT_CLK", "Input clock"}, {5, 4, "DEV_MCU_CPSW0_BUS_RGMII_MHZ_5_CLK", "Input clock"}, {5, 5, "DEV_MCU_CPSW0_BUS_RGMII_MHZ_50_CLK", "Input clock"}, {5, 6, "DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK", "Input muxed clock"}, {5, 7, "DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK"}, {5, 8, "DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK_PARENT_BOARD_0_BUS_MCU_RMII1_REFCLK_OUT", "Parent input clock option to DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK"}, {5, 9, "DEV_MCU_CPSW0_BUS_GMII_RFT_CLK", "Input clock"}, {5, 10, "DEV_MCU_CPSW0_BUS_CPPI_CLK_CLK", "Input clock"}, {5, 11, "DEV_MCU_CPSW0_BUS_CPTS_GENF0_0", "Output clock"}, {7, 0, "DEV_MCU_CPT2_AGGR0_BUS_VCLK_CLK", "Input clock"}, {107, 0, "DEV_MCU_CTRL_MMR0_BUS_VBUSP_CLK", "Input clock"}, {17, 0, "DEV_MCU_DCC0_BUS_DCC_INPUT00_CLK", "Input clock"}, {17, 1, "DEV_MCU_DCC0_BUS_DCC_CLKSRC7_CLK", "Input clock"}, {17, 2, "DEV_MCU_DCC0_BUS_DCC_CLKSRC4_CLK", "Input clock"}, {17, 3, "DEV_MCU_DCC0_BUS_DCC_CLKSRC3_CLK", "Input clock"}, {17, 4, "DEV_MCU_DCC0_BUS_VBUS_CLK", "Input clock"}, {17, 5, "DEV_MCU_DCC0_BUS_DCC_CLKSRC1_CLK", "Input clock"}, {17, 6, "DEV_MCU_DCC0_BUS_DCC_INPUT01_CLK", "Input clock"}, {17, 7, "DEV_MCU_DCC0_BUS_DCC_CLKSRC5_CLK", "Input clock"}, {17, 8, "DEV_MCU_DCC0_BUS_DCC_INPUT02_CLK", "Input clock"}, {17, 9, "DEV_MCU_DCC0_BUS_DCC_CLKSRC0_CLK", "Input clock"}, {17, 10, "DEV_MCU_DCC0_BUS_DCC_CLKSRC6_CLK", "Input clock"}, {17, 11, "DEV_MCU_DCC0_BUS_DCC_INPUT10_CLK", "Input clock"}, {17, 12, "DEV_MCU_DCC0_BUS_DCC_CLKSRC2_CLK", "Input clock"}, {18, 0, "DEV_MCU_DCC1_BUS_DCC_INPUT00_CLK", "Input clock"}, {18, 1, "DEV_MCU_DCC1_BUS_DCC_CLKSRC7_CLK", "Input clock"}, {18, 2, "DEV_MCU_DCC1_BUS_DCC_CLKSRC4_CLK", "Input clock"}, {18, 3, "DEV_MCU_DCC1_BUS_DCC_CLKSRC3_CLK", "Input clock"}, {18, 4, "DEV_MCU_DCC1_BUS_VBUS_CLK", "Input clock"}, {18, 5, "DEV_MCU_DCC1_BUS_DCC_CLKSRC1_CLK", "Input clock"}, {18, 6, "DEV_MCU_DCC1_BUS_DCC_INPUT01_CLK", "Input clock"}, {18, 7, "DEV_MCU_DCC1_BUS_DCC_CLKSRC5_CLK", "Input clock"}, {18, 8, "DEV_MCU_DCC1_BUS_DCC_INPUT02_CLK", "Input clock"}, {18, 9, "DEV_MCU_DCC1_BUS_DCC_CLKSRC0_CLK", "Input clock"}, {18, 10, "DEV_MCU_DCC1_BUS_DCC_CLKSRC6_CLK", "Input clock"}, {18, 11, "DEV_MCU_DCC1_BUS_DCC_INPUT10_CLK", "Input clock"}, {18, 12, "DEV_MCU_DCC1_BUS_DCC_CLKSRC2_CLK", "Input clock"}, {19, 0, "DEV_MCU_DCC2_BUS_DCC_INPUT00_CLK", "Input clock"}, {19, 1, "DEV_MCU_DCC2_BUS_DCC_CLKSRC7_CLK", "Input clock"}, {19, 2, "DEV_MCU_DCC2_BUS_DCC_CLKSRC4_CLK", "Input clock"}, {19, 3, "DEV_MCU_DCC2_BUS_DCC_CLKSRC3_CLK", "Input clock"}, {19, 4, "DEV_MCU_DCC2_BUS_VBUS_CLK", "Input clock"}, {19, 5, "DEV_MCU_DCC2_BUS_DCC_CLKSRC1_CLK", "Input clock"}, {19, 6, "DEV_MCU_DCC2_BUS_DCC_INPUT01_CLK", "Input clock"}, {19, 7, "DEV_MCU_DCC2_BUS_DCC_CLKSRC5_CLK", "Input clock"}, {19, 8, "DEV_MCU_DCC2_BUS_DCC_INPUT02_CLK", "Input clock"}, {19, 9, "DEV_MCU_DCC2_BUS_DCC_CLKSRC0_CLK", "Input clock"}, {19, 10, "DEV_MCU_DCC2_BUS_DCC_CLKSRC6_CLK", "Input clock"}, {19, 11, "DEV_MCU_DCC2_BUS_DCC_INPUT10_CLK", "Input clock"}, {19, 12, "DEV_MCU_DCC2_BUS_DCC_CLKSRC2_CLK", "Input clock"}, {71, 0, "DEV_MCU_DEBUGSS0_BUS_ATB1_CLK", "Input clock"}, {71, 1, "DEV_MCU_DEBUGSS0_BUS_ATB0_CLK", "Input clock"}, {71, 2, "DEV_MCU_DEBUGSS0_BUS_SYS_CLK", "Input clock"}, {71, 3, "DEV_MCU_DEBUGSS0_BUS_CFG_CLK", "Input clock"}, {71, 4, "DEV_MCU_DEBUGSS0_BUS_ATB2_CLK", "Input clock"}, {71, 5, "DEV_MCU_DEBUGSS0_BUS_DBG_CLK", "Input clock"}, {71, 6, "DEV_MCU_DEBUGSS0_BUS_ATB3_CLK", "Input clock"}, {92, 0, "DEV_MCU_ECC_AGGR0_BUS_AGGR_CLK", "Input clock"}, {93, 0, "DEV_MCU_ECC_AGGR1_BUS_AGGR_CLK", "Input clock"}, {72, 0, "DEV_MCU_EFUSE0_BUS_VBUSP_CLK_CLK", "Input clock"}, {72, 1, "DEV_MCU_EFUSE0_BUS_EFC3_CTL_FCLK", "Output clock"}, {72, 2, "DEV_MCU_EFUSE0_BUS_EFC0_CTL_FCLK", "Output clock"}, {72, 3, "DEV_MCU_EFUSE0_BUS_EFC1_CTL_FCLK", "Output clock"}, {72, 4, "DEV_MCU_EFUSE0_BUS_EFC2_CTL_FCLK", "Output clock"}, {53, 0, "DEV_MCU_ESM0_BUS_CLK", "Input clock"}, {247, 0, "DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX1_INV_CLK", "Input clock"}, {247, 1, "DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX1_CLK", "Input clock"}, {247, 2, "DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX2_CLK", "Input clock"}, {247, 3, "DEV_MCU_FSS0_HYPERBUS0_BUS_CBA_CLK", "Input clock"}, {247, 4, "DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX2_INV_CLK", "Input clock"}, {247, 5, "DEV_MCU_FSS0_HYPERBUS0_HPB_OUT_CLK_N", "Output clock"}, {247, 6, "DEV_MCU_FSS0_HYPERBUS0_HPB_OUT_CLK_P", "Output clock"}, {248, 0, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_RCLK_CLK", "Input muxed clock"}, {248, 1, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_RCLK_CLK"}, {248, 2, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_RCLK_CLK"}, {248, 3, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_ICLK_CLK", "Input muxed clock"}, {248, 4, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_ICLK_CLK_PARENT_BOARD_0_BUS_MCU_OSPI0DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_ICLK_CLK"}, {248, 5, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_BUS_OSPI0_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_ICLK_CLK"}, {248, 6, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_PCLK_CLK", "Input clock"}, {248, 7, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_DQS_CLK", "Input clock"}, {248, 8, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_HCLK_CLK", "Input clock"}, {248, 9, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_OCLK_CLK", "Output clock"}, {249, 0, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_PCLK_CLK", "Input clock"}, {249, 1, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_ICLK_CLK", "Input muxed clock"}, {249, 2, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_ICLK_CLK_PARENT_BOARD_0_BUS_MCU_OSPI1DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_ICLK_CLK"}, {249, 3, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_1_BUS_OSPI1_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_ICLK_CLK"}, {249, 4, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_HCLK_CLK", "Input clock"}, {249, 5, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_DQS_CLK", "Input clock"}, {249, 6, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_RCLK_CLK", "Input muxed clock"}, {249, 7, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_RCLK_CLK"}, {249, 8, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_RCLK_CLK"}, {249, 9, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_OCLK_CLK", "Output clock"}, {114, 0, "DEV_MCU_I2C0_BUS_CLK", "Input clock"}, {114, 1, "DEV_MCU_I2C0_BUS_PISYS_CLK", "Input clock"}, {114, 2, "DEV_MCU_I2C0_BUS_PISCL", "Output clock"}, {102, 0, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK", "Input muxed clock"}, {102, 1, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"}, {102, 2, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK2", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"}, {102, 3, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK2", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"}, {102, 4, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"}, {102, 5, "DEV_MCU_MCAN0_BUS_MCANSS_HCLK_CLK", "Input clock"}, {103, 0, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK", "Input muxed clock"}, {103, 1, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"}, {103, 2, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK2", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"}, {103, 3, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK2", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"}, {103, 4, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"}, {103, 5, "DEV_MCU_MCAN1_BUS_MCANSS_HCLK_CLK", "Input clock"}, {142, 0, "DEV_MCU_MCSPI0_BUS_IO_CLKSPII_CLK", "Input clock"}, {142, 1, "DEV_MCU_MCSPI0_BUS_CLKSPIREF_CLK", "Input clock"}, {142, 2, "DEV_MCU_MCSPI0_BUS_VBUSP_CLK", "Input clock"}, {142, 3, "DEV_MCU_MCSPI0_BUS_IO_CLKSPIO_CLK", "Output clock"}, {143, 0, "DEV_MCU_MCSPI1_BUS_IO_CLKSPII_CLK", "Input clock"}, {143, 1, "DEV_MCU_MCSPI1_BUS_CLKSPIREF_CLK", "Input clock"}, {143, 2, "DEV_MCU_MCSPI1_BUS_VBUSP_CLK", "Input clock"}, {143, 3, "DEV_MCU_MCSPI1_BUS_IO_CLKSPIO_CLK", "Output clock"}, {144, 0, "DEV_MCU_MCSPI2_BUS_CLKSPIREF_CLK", "Input clock"}, {144, 1, "DEV_MCU_MCSPI2_BUS_VBUSP_CLK", "Input clock"}, {116, 0, "DEV_MCU_MSRAM0_BUS_CCLK_CLK", "Input clock"}, {116, 1, "DEV_MCU_MSRAM0_BUS_VCLK_CLK", "Input clock"}, {119, 0, "DEV_MCU_NAVSS0_BUS_UDMASS_VD2CLK", "Input clock"}, {119, 1, "DEV_MCU_NAVSS0_BUS_CPSW0CLK", "Input clock"}, {119, 2, "DEV_MCU_NAVSS0_BUS_MODSS_VD2CLK", "Input clock"}, {119, 3, "DEV_MCU_NAVSS0_BUS_PDMA_MCU1CLK", "Input clock"}, {75, 0, "DEV_MCU_PBIST0_BUS_CLK1_CLK", "Input clock"}, {75, 1, "DEV_MCU_PBIST0_BUS_CLK4_CLK", "Input clock"}, {75, 2, "DEV_MCU_PBIST0_BUS_CLK2_CLK", "Input clock"}, {125, 0, "DEV_MCU_PDMA0_BUS_VCLK", "Input clock"}, {126, 0, "DEV_MCU_PDMA1_BUS_VCLK", "Input clock"}, {108, 0, "DEV_MCU_PLL_MMR0_BUS_VBUSP_CLK", "Input clock"}, {127, 0, "DEV_MCU_PSRAM0_BUS_CLK_CLK", "Input clock"}, {78, 0, "DEV_MCU_ROM0_BUS_CLK_CLK", "Input clock"}, {134, 0, "DEV_MCU_RTI0_BUS_RTI_CLK", "Input muxed clock"}, {134, 1, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"}, {134, 2, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"}, {134, 3, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"}, {134, 4, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"}, {134, 5, "DEV_MCU_RTI0_BUS_VBUSP_CLK", "Input clock"}, {135, 0, "DEV_MCU_RTI1_BUS_RTI_CLK", "Input muxed clock"}, {135, 1, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"}, {135, 2, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"}, {135, 3, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"}, {135, 4, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"}, {135, 5, "DEV_MCU_RTI1_BUS_VBUSP_CLK", "Input clock"}, {109, 0, "DEV_MCU_SEC_MMR0_BUS_VBUSP_CLK", "Input clock"}, {35, 0, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, {35, 1, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"}, {35, 2, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"}, {35, 3, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"}, {35, 4, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"}, {35, 5, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"}, {35, 6, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"}, {35, 7, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_BUS_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"}, {35, 8, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"}, {35, 9, "DEV_MCU_TIMER0_BUS_TIMER_HCLK_CLK", "Input clock"}, {36, 0, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, {36, 1, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"}, {36, 2, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"}, {36, 3, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"}, {36, 4, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"}, {36, 5, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"}, {36, 6, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"}, {36, 7, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_BUS_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"}, {36, 8, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"}, {36, 9, "DEV_MCU_TIMER1_BUS_TIMER_HCLK_CLK", "Input clock"}, {37, 0, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, {37, 1, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"}, {37, 2, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"}, {37, 3, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"}, {37, 4, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"}, {37, 5, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"}, {37, 6, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"}, {37, 7, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_BUS_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"}, {37, 8, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"}, {37, 9, "DEV_MCU_TIMER2_BUS_TIMER_HCLK_CLK", "Input clock"}, {38, 0, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, {38, 1, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"}, {38, 2, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"}, {38, 3, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"}, {38, 4, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"}, {38, 5, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"}, {38, 6, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"}, {38, 7, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_BUS_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"}, {38, 8, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"}, {38, 9, "DEV_MCU_TIMER3_BUS_TIMER_HCLK_CLK", "Input clock"}, {149, 0, "DEV_MCU_UART0_BUS_FCLK_CLK", "Input muxed clock"}, {149, 1, "DEV_MCU_UART0_BUS_FCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_MCU_UART0_BUS_FCLK_CLK"}, {149, 2, "DEV_MCU_UART0_BUS_FCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_MCU_UART0_BUS_FCLK_CLK"}, {149, 3, "DEV_MCU_UART0_BUS_VBUSP_CLK", "Input clock"}, {47, 0, "DEV_MMCSD0_BUS_EMMCSDSS_VBUS_CLK", "Input clock"}, {47, 1, "DEV_MMCSD0_BUS_EMMCSDSS_XIN_CLK", "Input clock"}, {48, 0, "DEV_MMCSD1_BUS_EMMCSDSS_VBUS_CLK", "Input clock"}, {48, 1, "DEV_MMCSD1_BUS_EMMCSDSS_XIN_CLK", "Input clock"}, {234, 0, "DEV_MX_EFUSE_MAIN_CHAIN_MAIN_0_BUS_UNDEFINEDCHAIN1_FCLK", "Input clock"}, {234, 1, "DEV_MX_EFUSE_MAIN_CHAIN_MAIN_0_BUS_UNDEFINEDCHAIN0_FCLK", "Input clock"}, {235, 0, "DEV_MX_EFUSE_MCU_CHAIN_MCU_0_BUS_UNDEFINEDCHAIN1_FCLK", "Input clock"}, {235, 1, "DEV_MX_EFUSE_MCU_CHAIN_MCU_0_BUS_UNDEFINEDCHAIN0_FCLK", "Input clock"}, {235, 2, "DEV_MX_EFUSE_MCU_CHAIN_MCU_0_BUS_UNDEFINEDCHAIN2_FCLK", "Input clock"}, {118, 0, "DEV_NAVSS0_BUS_UDMASS_VD2CLK", "Input clock"}, {118, 1, "DEV_NAVSS0_BUS_ICSS_G2CLK", "Input clock"}, {118, 2, "DEV_NAVSS0_BUS_ICSS_G0CLK", "Input clock"}, {118, 3, "DEV_NAVSS0_BUS_RCLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Input clock"}, {118, 4, "DEV_NAVSS0_BUS_MSMC0CLK", "Input clock"}, {118, 5, "DEV_NAVSS0_BUS_RCLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Input clock"}, {118, 6, "DEV_NAVSS0_BUS_RCLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Input clock"}, {118, 7, "DEV_NAVSS0_BUS_MODSS_VD2CLK", "Input clock"}, {118, 8, "DEV_NAVSS0_BUS_RCLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Input clock"}, {118, 9, "DEV_NAVSS0_BUS_PDMA_MAIN1CLK", "Input clock"}, {118, 10, "DEV_NAVSS0_BUS_NBSS_VCLK", "Input clock"}, {118, 11, "DEV_NAVSS0_BUS_RCLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Input clock"}, {118, 12, "DEV_NAVSS0_BUS_NBSS_VD2CLK", "Input clock"}, {118, 13, "DEV_NAVSS0_BUS_ICSS_G1CLK", "Input clock"}, {118, 14, "DEV_NAVSS0_BUS_RCLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1_OUT", "Input clock"}, {118, 15, "DEV_NAVSS0_BUS_CPTS0_GENF4_0", "Output clock"}, {118, 16, "DEV_NAVSS0_BUS_CPTS0_GENF5_0", "Output clock"}, {118, 17, "DEV_NAVSS0_BUS_CPTS0_GENF2_0", "Output clock"}, {118, 18, "DEV_NAVSS0_BUS_CPTS0_GENF3_0", "Output clock"}, {216, 0, "DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_PLL_CLK", "Input clock"}, {216, 1, "DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_0_FWD_P_CLK_BUS_IN1_CLOCKDIVIDER_DSS_BUS_OUT0", "Input clock"}, {216, 2, "DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_0_FWD_P_CLK_BUS_IN0_CLOCKDIVIDER_DSS_BUS_OUT0", "Input clock"}, {73, 0, "DEV_PBIST0_BUS_CLK1_CLK", "Input clock"}, {73, 1, "DEV_PBIST0_BUS_CLK4_CLK", "Input clock"}, {73, 2, "DEV_PBIST0_BUS_CLK2_CLK", "Input clock"}, {74, 0, "DEV_PBIST1_BUS_CLK1_CLK", "Input clock"}, {74, 1, "DEV_PBIST1_BUS_CLK4_CLK", "Input clock"}, {74, 2, "DEV_PBIST1_BUS_CLK2_CLK", "Input clock"}, {120, 0, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1_OUT", "Input clock"}, {120, 1, "DEV_PCIE0_BUS_PCIE_CBA_CLK", "Input clock"}, {120, 2, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Input clock"}, {120, 3, "DEV_PCIE0_BUS_PCIE_TXI0_CLK", "Input clock"}, {120, 4, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Input clock"}, {120, 5, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Input clock"}, {120, 6, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Input clock"}, {120, 7, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Input clock"}, {120, 8, "DEV_PCIE0_BUS_PCIE_TXR1_CLK", "Output clock"}, {120, 9, "DEV_PCIE0_BUS_PCIE_TXR0_CLK", "Output clock"}, {121, 0, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1_OUT", "Input clock"}, {121, 1, "DEV_PCIE1_BUS_PCIE_CBA_CLK", "Input clock"}, {121, 2, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Input clock"}, {121, 3, "DEV_PCIE1_BUS_PCIE_TXI0_CLK", "Input clock"}, {121, 4, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Input clock"}, {121, 5, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Input clock"}, {121, 6, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Input clock"}, {121, 7, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Input clock"}, {121, 8, "DEV_PCIE1_BUS_PCIE_TXR0_CLK", "Output clock"}, {123, 0, "DEV_PDMA0_BUS_VCLK", "Input clock"}, {124, 0, "DEV_PDMA1_BUS_VCLK", "Input clock"}, {122, 0, "DEV_PDMA_DEBUG0_BUS_VCLK", "Input clock"}, {76, 0, "DEV_PLLCTRL0_BUS_VBUS_SLV_REFCLK_CLK", "Input clock"}, {76, 1, "DEV_PLLCTRL0_BUS_PLL_CLKOUT_CLK", "Input clock"}, {76, 2, "DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK", "Input muxed clock"}, {76, 3, "DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK"}, {76, 4, "DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK"}, {101, 0, "DEV_PLL_MMR0_BUS_VBUSP_CLK", "Input clock"}, {62, 0, "DEV_PRU_ICSSG0_BUS_RGMII_MHZ_5_CLK", "Input clock"}, {62, 1, "DEV_PRU_ICSSG0_BUS_WIZ1_TX_SLV_CLK", "Input clock"}, {62, 2, "DEV_PRU_ICSSG0_BUS_WIZ0_RX_SLV_CLK", "Input clock"}, {62, 3, "DEV_PRU_ICSSG0_BUS_VCLK_CLK", "Input clock"}, {62, 4, "DEV_PRU_ICSSG0_BUS_UCLK_CLK", "Input clock"}, {62, 5, "DEV_PRU_ICSSG0_BUS_WIZ0_TX_SLV_CLK", "Input clock"}, {62, 6, "DEV_PRU_ICSSG0_BUS_WIZ1_RX_SLV_CLK", "Input clock"}, {62, 7, "DEV_PRU_ICSSG0_BUS_PR1_RGMII1_RXC_I", "Input clock"}, {62, 8, "DEV_PRU_ICSSG0_BUS_RGMII_MHZ_250_CLK", "Input clock"}, {62, 9, "DEV_PRU_ICSSG0_BUS_RGMII_MHZ_50_CLK", "Input clock"}, {62, 10, "DEV_PRU_ICSSG0_BUS_IEP_CLK", "Input muxed clock"}, {62, 11, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"}, {62, 12, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"}, {62, 13, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"}, {62, 14, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"}, {62, 15, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"}, {62, 16, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"}, {62, 17, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"}, {62, 18, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"}, {62, 19, "DEV_PRU_ICSSG0_BUS_CORE_CLK", "Input muxed clock"}, {62, 20, "DEV_PRU_ICSSG0_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_CORE_CLK"}, {62, 21, "DEV_PRU_ICSSG0_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_CORE_CLK"}, {62, 22, "DEV_PRU_ICSSG0_BUS_PR1_RGMII0_RXC_I", "Input clock"}, {62, 23, "DEV_PRU_ICSSG0_BUS_PR1_RGMII1_TXC_I", "Output clock"}, {62, 24, "DEV_PRU_ICSSG0_BUS_PR1_RGMII0_TXC_I", "Output clock"}, {63, 0, "DEV_PRU_ICSSG1_BUS_RGMII_MHZ_5_CLK", "Input clock"}, {63, 1, "DEV_PRU_ICSSG1_BUS_WIZ1_TX_SLV_CLK", "Input clock"}, {63, 2, "DEV_PRU_ICSSG1_BUS_WIZ0_RX_SLV_CLK", "Input clock"}, {63, 3, "DEV_PRU_ICSSG1_BUS_VCLK_CLK", "Input clock"}, {63, 4, "DEV_PRU_ICSSG1_BUS_UCLK_CLK", "Input clock"}, {63, 5, "DEV_PRU_ICSSG1_BUS_WIZ0_TX_SLV_CLK", "Input clock"}, {63, 6, "DEV_PRU_ICSSG1_BUS_WIZ1_RX_SLV_CLK", "Input clock"}, {63, 7, "DEV_PRU_ICSSG1_BUS_PR1_RGMII1_RXC_I", "Input clock"}, {63, 8, "DEV_PRU_ICSSG1_BUS_RGMII_MHZ_250_CLK", "Input clock"}, {63, 9, "DEV_PRU_ICSSG1_BUS_RGMII_MHZ_50_CLK", "Input clock"}, {63, 10, "DEV_PRU_ICSSG1_BUS_IEP_CLK", "Input muxed clock"}, {63, 11, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"}, {63, 12, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"}, {63, 13, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"}, {63, 14, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"}, {63, 15, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"}, {63, 16, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"}, {63, 17, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"}, {63, 18, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"}, {63, 19, "DEV_PRU_ICSSG1_BUS_CORE_CLK", "Input muxed clock"}, {63, 20, "DEV_PRU_ICSSG1_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_CORE_CLK"}, {63, 21, "DEV_PRU_ICSSG1_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_CORE_CLK"}, {63, 22, "DEV_PRU_ICSSG1_BUS_PR1_RGMII0_RXC_I", "Input clock"}, {63, 23, "DEV_PRU_ICSSG1_BUS_PR1_RGMII1_TXC_I", "Output clock"}, {63, 24, "DEV_PRU_ICSSG1_BUS_PR1_RGMII0_TXC_I", "Output clock"}, {64, 0, "DEV_PRU_ICSSG2_BUS_RGMII_MHZ_5_CLK", "Input clock"}, {64, 1, "DEV_PRU_ICSSG2_BUS_WIZ1_TX_SLV_CLK", "Input clock"}, {64, 2, "DEV_PRU_ICSSG2_BUS_WIZ0_RX_SLV_CLK", "Input clock"}, {64, 3, "DEV_PRU_ICSSG2_BUS_VCLK_CLK", "Input clock"}, {64, 4, "DEV_PRU_ICSSG2_BUS_UCLK_CLK", "Input clock"}, {64, 5, "DEV_PRU_ICSSG2_BUS_WIZ0_TX_SLV_CLK", "Input clock"}, {64, 6, "DEV_PRU_ICSSG2_BUS_WIZ1_RX_SLV_CLK", "Input clock"}, {64, 7, "DEV_PRU_ICSSG2_BUS_PR1_RGMII1_RXC_I", "Input clock"}, {64, 8, "DEV_PRU_ICSSG2_BUS_RGMII_MHZ_250_CLK", "Input clock"}, {64, 9, "DEV_PRU_ICSSG2_BUS_RGMII_MHZ_50_CLK", "Input clock"}, {64, 10, "DEV_PRU_ICSSG2_BUS_IEP_CLK", "Input muxed clock"}, {64, 11, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"}, {64, 12, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"}, {64, 13, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"}, {64, 14, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"}, {64, 15, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"}, {64, 16, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"}, {64, 17, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"}, {64, 18, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"}, {64, 19, "DEV_PRU_ICSSG2_BUS_CORE_CLK", "Input muxed clock"}, {64, 20, "DEV_PRU_ICSSG2_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_CORE_CLK"}, {64, 21, "DEV_PRU_ICSSG2_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_CORE_CLK"}, {64, 22, "DEV_PRU_ICSSG2_BUS_PR1_RGMII0_RXC_I", "Input clock"}, {64, 23, "DEV_PRU_ICSSG2_BUS_PR1_RGMII1_TXC_I", "Output clock"}, {64, 24, "DEV_PRU_ICSSG2_BUS_PR1_RGMII0_TXC_I", "Output clock"}, {64, 25, "DEV_PRU_ICSSG2_BUS_WIZ1_TX_MST_CLK", "Output clock"}, {64, 26, "DEV_PRU_ICSSG2_BUS_WIZ0_TX_MST_CLK", "Output clock"}, {70, 0, "DEV_PSC0_BUS_CLK", "Input clock"}, {70, 1, "DEV_PSC0_BUS_SLOW_CLK", "Input clock"}, {128, 0, "DEV_PSRAMECC0_BUS_CLK_CLK", "Input clock"}, {130, 0, "DEV_RTI0_BUS_RTI_CLK", "Input muxed clock"}, {130, 1, "DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"}, {130, 2, "DEV_RTI0_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"}, {130, 3, "DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"}, {130, 4, "DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"}, {130, 5, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"}, {130, 6, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"}, {130, 7, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"}, {130, 8, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"}, {130, 9, "DEV_RTI0_BUS_VBUSP_CLK", "Input clock"}, {131, 0, "DEV_RTI1_BUS_RTI_CLK", "Input muxed clock"}, {131, 1, "DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"}, {131, 2, "DEV_RTI1_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"}, {131, 3, "DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"}, {131, 4, "DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"}, {131, 5, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"}, {131, 6, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"}, {131, 7, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"}, {131, 8, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"}, {131, 9, "DEV_RTI1_BUS_VBUSP_CLK", "Input clock"}, {132, 0, "DEV_RTI2_BUS_RTI_CLK", "Input muxed clock"}, {132, 1, "DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"}, {132, 2, "DEV_RTI2_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"}, {132, 3, "DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"}, {132, 4, "DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"}, {132, 5, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"}, {132, 6, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"}, {132, 7, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"}, {132, 8, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"}, {132, 9, "DEV_RTI2_BUS_VBUSP_CLK", "Input clock"}, {133, 0, "DEV_RTI3_BUS_RTI_CLK", "Input muxed clock"}, {133, 1, "DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"}, {133, 2, "DEV_RTI3_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"}, {133, 3, "DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"}, {133, 4, "DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"}, {133, 5, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"}, {133, 6, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"}, {133, 7, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"}, {133, 8, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"}, {133, 9, "DEV_RTI3_BUS_VBUSP_CLK", "Input clock"}, {136, 0, "DEV_SA2_UL0_BUS_PKA_IN_CLK", "Input clock"}, {136, 1, "DEV_SA2_UL0_BUS_X1_CLK", "Input clock"}, {136, 2, "DEV_SA2_UL0_BUS_X2_CLK", "Input clock"}, {153, 0, "DEV_SERDES0_BUS_IP3_LN0_TXRCLK", "Input clock"}, {153, 1, "DEV_SERDES0_BUS_REFCLKPP", "Input clock"}, {153, 2, "DEV_SERDES0_BUS_CLK", "Input clock"}, {153, 3, "DEV_SERDES0_BUS_IP2_LN0_TXRCLK", "Input clock"}, {153, 4, "DEV_SERDES0_BUS_LI_REFCLK", "Input muxed clock"}, {153, 5, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"}, {153, 6, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"}, {153, 7, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"}, {153, 8, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"}, {153, 9, "DEV_SERDES0_BUS_REFCLKPN", "Input clock"}, {153, 10, "DEV_SERDES0_BUS_LN0_TXCLK", "Output clock"}, {153, 11, "DEV_SERDES0_BUS_LN0_RXCLK", "Output clock"}, {154, 0, "DEV_SERDES1_BUS_IP3_LN0_TXRCLK", "Input clock"}, {154, 1, "DEV_SERDES1_BUS_REFCLKPP", "Input clock"}, {154, 2, "DEV_SERDES1_BUS_CLK", "Input clock"}, {154, 3, "DEV_SERDES1_BUS_IP1_LN0_TXRCLK", "Input clock"}, {154, 4, "DEV_SERDES1_BUS_IP2_LN0_TXRCLK", "Input clock"}, {154, 5, "DEV_SERDES1_BUS_RI_REFCLK", "Input muxed clock"}, {154, 6, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"}, {154, 7, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"}, {154, 8, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"}, {154, 9, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"}, {154, 10, "DEV_SERDES1_BUS_REFCLKPN", "Input clock"}, {154, 11, "DEV_SERDES1_BUS_LN0_TXCLK", "Output clock"}, {154, 12, "DEV_SERDES1_BUS_LN0_RXCLK", "Output clock"}, {8, 0, "DEV_STM0_BUS_CORE_CLK", "Input clock"}, {8, 1, "DEV_STM0_BUS_ATB_CLK", "Input clock"}, {8, 2, "DEV_STM0_BUS_VBUSP_CLK", "Input clock"}, {23, 0, "DEV_TIMER0_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, {23, 1, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, {23, 2, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, {23, 3, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, {23, 4, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, {23, 5, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, {23, 6, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, {23, 7, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, {23, 8, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, {23, 9, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, {23, 10, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, {23, 11, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, {23, 12, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, {23, 13, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, {23, 14, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, {23, 15, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, {23, 16, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"}, {23, 17, "DEV_TIMER0_BUS_TIMER_HCLK_CLK", "Input clock"}, {24, 0, "DEV_TIMER1_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, {24, 1, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, {24, 2, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, {24, 3, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, {24, 4, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, {24, 5, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, {24, 6, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, {24, 7, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, {24, 8, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, {24, 9, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, {24, 10, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, {24, 11, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, {24, 12, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, {24, 13, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, {24, 14, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, {24, 15, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, {24, 16, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"}, {24, 17, "DEV_TIMER1_BUS_TIMER_HCLK_CLK", "Input clock"}, {25, 0, "DEV_TIMER10_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, {25, 1, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, {25, 2, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, {25, 3, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, {25, 4, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, {25, 5, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, {25, 6, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, {25, 7, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, {25, 8, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, {25, 9, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, {25, 10, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, {25, 11, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, {25, 12, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, {25, 13, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, {25, 14, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, {25, 15, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, {25, 16, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"}, {25, 17, "DEV_TIMER10_BUS_TIMER_HCLK_CLK", "Input clock"}, {26, 0, "DEV_TIMER11_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, {26, 1, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, {26, 2, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, {26, 3, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, {26, 4, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, {26, 5, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, {26, 6, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, {26, 7, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, {26, 8, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, {26, 9, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, {26, 10, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, {26, 11, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, {26, 12, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, {26, 13, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, {26, 14, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, {26, 15, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, {26, 16, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"}, {26, 17, "DEV_TIMER11_BUS_TIMER_HCLK_CLK", "Input clock"}, {27, 0, "DEV_TIMER2_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, {27, 1, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, {27, 2, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, {27, 3, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, {27, 4, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, {27, 5, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, {27, 6, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, {27, 7, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, {27, 8, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, {27, 9, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, {27, 10, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, {27, 11, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, {27, 12, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, {27, 13, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, {27, 14, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, {27, 15, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, {27, 16, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"}, {27, 17, "DEV_TIMER2_BUS_TIMER_HCLK_CLK", "Input clock"}, {28, 0, "DEV_TIMER3_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, {28, 1, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, {28, 2, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, {28, 3, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, {28, 4, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, {28, 5, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, {28, 6, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, {28, 7, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, {28, 8, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, {28, 9, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, {28, 10, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, {28, 11, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, {28, 12, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, {28, 13, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, {28, 14, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, {28, 15, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, {28, 16, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"}, {28, 17, "DEV_TIMER3_BUS_TIMER_HCLK_CLK", "Input clock"}, {29, 0, "DEV_TIMER4_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, {29, 1, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, {29, 2, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, {29, 3, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, {29, 4, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, {29, 5, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, {29, 6, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, {29, 7, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, {29, 8, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, {29, 9, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, {29, 10, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, {29, 11, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, {29, 12, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, {29, 13, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, {29, 14, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, {29, 15, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, {29, 16, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"}, {29, 17, "DEV_TIMER4_BUS_TIMER_HCLK_CLK", "Input clock"}, {30, 0, "DEV_TIMER5_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, {30, 1, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, {30, 2, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, {30, 3, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, {30, 4, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, {30, 5, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, {30, 6, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, {30, 7, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, {30, 8, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, {30, 9, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, {30, 10, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, {30, 11, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, {30, 12, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, {30, 13, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, {30, 14, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, {30, 15, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, {30, 16, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"}, {30, 17, "DEV_TIMER5_BUS_TIMER_HCLK_CLK", "Input clock"}, {31, 0, "DEV_TIMER6_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, {31, 1, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, {31, 2, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, {31, 3, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, {31, 4, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, {31, 5, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, {31, 6, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, {31, 7, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, {31, 8, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, {31, 9, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, {31, 10, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, {31, 11, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, {31, 12, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, {31, 13, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, {31, 14, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, {31, 15, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, {31, 16, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"}, {31, 17, "DEV_TIMER6_BUS_TIMER_HCLK_CLK", "Input clock"}, {32, 0, "DEV_TIMER7_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, {32, 1, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, {32, 2, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, {32, 3, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, {32, 4, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, {32, 5, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, {32, 6, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, {32, 7, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, {32, 8, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, {32, 9, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, {32, 10, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, {32, 11, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, {32, 12, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, {32, 13, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, {32, 14, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, {32, 15, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, {32, 16, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"}, {32, 17, "DEV_TIMER7_BUS_TIMER_HCLK_CLK", "Input clock"}, {33, 0, "DEV_TIMER8_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, {33, 1, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, {33, 2, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, {33, 3, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, {33, 4, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, {33, 5, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, {33, 6, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, {33, 7, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, {33, 8, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, {33, 9, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, {33, 10, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, {33, 11, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, {33, 12, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, {33, 13, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, {33, 14, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, {33, 15, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, {33, 16, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"}, {33, 17, "DEV_TIMER8_BUS_TIMER_HCLK_CLK", "Input clock"}, {34, 0, "DEV_TIMER9_BUS_TIMER_TCLK_CLK", "Input muxed clock"}, {34, 1, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, {34, 2, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, {34, 3, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, {34, 4, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, {34, 5, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, {34, 6, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, {34, 7, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, {34, 8, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, {34, 9, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, {34, 10, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, {34, 11, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, {34, 12, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, {34, 13, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, {34, 14, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, {34, 15, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, {34, 16, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"}, {34, 17, "DEV_TIMER9_BUS_TIMER_HCLK_CLK", "Input clock"}, {145, 0, "DEV_TIMESYNC_INTRTR0_BUS_INTR_CLK", "Input clock"}, {146, 0, "DEV_UART0_BUS_FCLK_CLK", "Input clock"}, {146, 1, "DEV_UART0_BUS_VBUSP_CLK", "Input clock"}, {147, 0, "DEV_UART1_BUS_FCLK_CLK", "Input clock"}, {147, 1, "DEV_UART1_BUS_VBUSP_CLK", "Input clock"}, {148, 0, "DEV_UART2_BUS_FCLK_CLK", "Input clock"}, {148, 1, "DEV_UART2_BUS_VBUSP_CLK", "Input clock"}, {151, 0, "DEV_USB3SS0_BUS_SUSP_CLK", "Input clock"}, {151, 1, "DEV_USB3SS0_BUS_PHY2_REFCLK960M_CLK", "Input clock"}, {151, 2, "DEV_USB3SS0_BUS_REF_CLK", "Input muxed clock"}, {151, 3, "DEV_USB3SS0_BUS_REF_CLK_PARENT_CLOCKMUX_HFOSC_SEL_BUS_OUT0", "Parent input clock option to DEV_USB3SS0_BUS_REF_CLK"}, {151, 4, "DEV_USB3SS0_BUS_REF_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK48", "Parent input clock option to DEV_USB3SS0_BUS_REF_CLK"}, {151, 5, "DEV_USB3SS0_BUS_HSIC_CLK_CLK", "Input clock"}, {151, 6, "DEV_USB3SS0_BUS_BUS_CLK", "Input clock"}, {151, 7, "DEV_USB3SS0_BUS_PIPE3_TXB_CLK", "Input muxed clock"}, {151, 8, "DEV_USB3SS0_BUS_PIPE3_TXB_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_USB3SS0_BUS_PIPE3_TXB_CLK"}, {151, 9, "DEV_USB3SS0_BUS_PIPE3_TXB_CLK_PARENT_CLOCKMUX_USB0_PIPE3_CLK_SEL_DIV_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_USB3SS0_BUS_PIPE3_TXB_CLK"}, {151, 10, "DEV_USB3SS0_BUS_UTMI_CLK_CLK", "Input clock"}, {152, 0, "DEV_USB3SS1_BUS_SUSP_CLK", "Input clock"}, {152, 1, "DEV_USB3SS1_BUS_PHY2_REFCLK960M_CLK", "Input clock"}, {152, 2, "DEV_USB3SS1_BUS_REF_CLK", "Input muxed clock"}, {152, 3, "DEV_USB3SS1_BUS_REF_CLK_PARENT_CLOCKMUX_HFOSC_SEL_BUS_OUT0", "Parent input clock option to DEV_USB3SS1_BUS_REF_CLK"}, {152, 4, "DEV_USB3SS1_BUS_REF_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK48", "Parent input clock option to DEV_USB3SS1_BUS_REF_CLK"}, {152, 5, "DEV_USB3SS1_BUS_HSIC_CLK_CLK", "Input clock"}, {152, 6, "DEV_USB3SS1_BUS_BUS_CLK", "Input clock"}, {152, 7, "DEV_USB3SS1_BUS_PIPE3_TXB_CLK", "Input clock"}, {152, 8, "DEV_USB3SS1_BUS_UTMI_CLK_CLK", "Input clock"}, {94, 0, "DEV_WKUP_CBASS0_BUS_WKUP_MCU_PLL_OUT_2_CLK", "Input clock"}, {94, 1, "DEV_WKUP_CBASS0_BUS_WKUP_MCU_PLL_OUT_4_CLK", "Input clock"}, {96, 0, "DEV_WKUP_CBASS_FW0_BUS_WKUP_MCU_PLL_OUT_2_CLK", "Input clock"}, {155, 0, "DEV_WKUP_CTRL_MMR0_BUS_VBUSP_CLK", "Input clock"}, {22, 0, "DEV_WKUP_DMSC0_BUS_FUNC_32K_RT_CLK", "Input clock"}, {22, 1, "DEV_WKUP_DMSC0_BUS_FUNC_MOSC_CLK", "Input clock"}, {22, 2, "DEV_WKUP_DMSC0_BUS_VBUS_CLK", "Input clock"}, {22, 3, "DEV_WKUP_DMSC0_BUS_FUNC_32K_RC_CLK", "Input clock"}, {22, 4, "DEV_WKUP_DMSC0_BUS_SEC_EFC_FCLK", "Input clock"}, {22, 5, "DEV_WKUP_DMSC0_BUS_DAP_CLK", "Input clock"}, {22, 6, "DEV_WKUP_DMSC0_BUS_EXT_CLK", "Input clock"}, {95, 0, "DEV_WKUP_ECC_AGGR0_BUS_AGGR_CLK", "Input clock"}, {54, 0, "DEV_WKUP_ESM0_BUS_CLK", "Input clock"}, {59, 0, "DEV_WKUP_GPIO0_BUS_MMR_CLK", "Input muxed clock"}, {59, 1, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"}, {59, 2, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK4_DUP0", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"}, {59, 3, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"}, {59, 4, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"}, {156, 0, "DEV_WKUP_GPIOMUX_INTRTR0_BUS_INTR_CLK", "Input clock"}, {115, 0, "DEV_WKUP_I2C0_BUS_CLK", "Input clock"}, {115, 1, "DEV_WKUP_I2C0_BUS_PISYS_CLK", "Input muxed clock"}, {115, 2, "DEV_WKUP_I2C0_BUS_PISYS_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_WKUP_I2C0_BUS_PISYS_CLK"}, {115, 3, "DEV_WKUP_I2C0_BUS_PISYS_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_WKUP_I2C0_BUS_PISYS_CLK"}, {115, 4, "DEV_WKUP_I2C0_BUS_PISCL", "Output clock"}, {77, 0, "DEV_WKUP_PLLCTRL0_BUS_VBUS_SLV_REFCLK_CLK", "Input clock"}, {77, 1, "DEV_WKUP_PLLCTRL0_BUS_PLL_CLKOUT_CLK", "Input clock"}, {77, 2, "DEV_WKUP_PLLCTRL0_BUS_PLL_REFCLK_CLK", "Input clock"}, {79, 0, "DEV_WKUP_PSC0_BUS_CLK", "Input clock"}, {79, 1, "DEV_WKUP_PSC0_BUS_SLOW_CLK", "Input clock"}, {150, 0, "DEV_WKUP_UART0_BUS_FCLK_CLK", "Input muxed clock"}, {150, 1, "DEV_WKUP_UART0_BUS_FCLK_CLK_PARENT_CLOCKMUX_WKUPUSART_CLK_SEL_BUS_OUT0", "Parent input clock option to DEV_WKUP_UART0_BUS_FCLK_CLK"}, {150, 2, "DEV_WKUP_UART0_BUS_FCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_WKUP_UART0_BUS_FCLK_CLK"}, {150, 3, "DEV_WKUP_UART0_BUS_VBUSP_CLK", "Input clock"}, {80, 0, "DEV_WKUP_VTM0_BUS_FIX_REF_CLK", "Input clock"}, {80, 1, "DEV_WKUP_VTM0_BUS_VBUSP_CLK", "Input clock"}, }; k3conf_0.3/soc/am65x/am65x_processors_info.c0000664000175000017500000000363114375734376015716 0ustar /* * AM65X Processor Info * * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_processors_info am65x_processors_info[] = { {202, 0, 0x20, "A53_CL0_C0"}, {203, 0, 0x21, "A53_CL0_C1"}, {204, 0, 0x22, "A53_CL1_C0"}, {205, 0, 0x23, "A53_CL1_C1"}, {159, 0, 0x01, "R5_CL0_C0"}, {245, 0, 0x02, "R5_CL0_C1"}, }; k3conf_0.3/soc/am65x/am65x_devices_info.h0000664000175000017500000000346414504336513015130 0ustar /* * AM65X Devices Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM65X_DEVICES_INFO_H #define __AM65X_DEVICES_INFO_H #define AM65X_MAX_DEVICES 243 extern struct ti_sci_devices_info am65x_devices_info[]; #endif /* __AM65X_DEVICES_INFO_H */ k3conf_0.3/soc/am65x/am65x_rm_info.c0000664000175000017500000000757114375734376014141 0ustar /* * AM65X RM Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_rm_info am65x_rm_info[] = { {0x00C0, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x1840, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x1880, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x1900, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x2440, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x2700, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x2CCA, "RESASG_SUBTYPE_IA_VINT"}, {0x2CCD, "RESASG_SUBTYPE_GLOBAL_EVENT_SEVT"}, {0x2D0A, "RESASG_SUBTYPE_IA_VINT"}, {0x2D0D, "RESASG_SUBTYPE_GLOBAL_EVENT_SEVT"}, {0x2D4A, "RESASG_SUBTYPE_IA_VINT"}, {0x2D4D, "RESASG_SUBTYPE_GLOBAL_EVENT_SEVT"}, {0x2D80, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x2E40, "RESASG_SUBTYPE_PROXY_PROXIES"}, {0x2EC0, "RESASG_SUBTYPE_RA_ERROR_OES"}, {0x2EC1, "RESASG_SUBTYPE_RA_GP"}, {0x2EC2, "RESASG_SUBTYPE_RA_UDMAP_RX"}, {0x2EC3, "RESASG_SUBTYPE_RA_UDMAP_TX"}, {0x2EC4, "RESASG_SUBTYPE_RA_UDMAP_TX_EXT"}, {0x2EC5, "RESASG_SUBTYPE_RA_UDMAP_RX_H"}, {0x2EC7, "RESASG_SUBTYPE_RA_UDMAP_TX_H"}, {0x2ECA, "RESASG_SUBTYPE_RA_VIRTID"}, {0x2ECB, "RESASG_SUBTYPE_RA_MONITORS"}, {0x2F00, "RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON"}, {0x2F01, "RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES"}, {0x2F02, "RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER"}, {0x2F03, "RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG"}, {0x2F0A, "RESASG_SUBTYPE_UDMAP_RX_CHAN"}, {0x2F0B, "RESASG_SUBTYPE_UDMAP_RX_HCHAN"}, {0x2F0D, "RESASG_SUBTYPE_UDMAP_TX_CHAN"}, {0x2F0E, "RESASG_SUBTYPE_UDMAP_TX_ECHAN"}, {0x2F0F, "RESASG_SUBTYPE_UDMAP_TX_HCHAN"}, {0x2F4A, "RESASG_SUBTYPE_IA_VINT"}, {0x2F4D, "RESASG_SUBTYPE_GLOBAL_EVENT_SEVT"}, {0x2F80, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x2FC0, "RESASG_SUBTYPE_PROXY_PROXIES"}, {0x3080, "RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON"}, {0x3081, "RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES"}, {0x3082, "RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER"}, {0x3083, "RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG"}, {0x308A, "RESASG_SUBTYPE_UDMAP_RX_CHAN"}, {0x308B, "RESASG_SUBTYPE_UDMAP_RX_HCHAN"}, {0x308D, "RESASG_SUBTYPE_UDMAP_TX_CHAN"}, {0x308F, "RESASG_SUBTYPE_UDMAP_TX_HCHAN"}, {0x30C0, "RESASG_SUBTYPE_RA_ERROR_OES"}, {0x30C1, "RESASG_SUBTYPE_RA_GP"}, {0x30C2, "RESASG_SUBTYPE_RA_UDMAP_RX"}, {0x30C3, "RESASG_SUBTYPE_RA_UDMAP_TX"}, {0x30C5, "RESASG_SUBTYPE_RA_UDMAP_RX_H"}, {0x30C7, "RESASG_SUBTYPE_RA_UDMAP_TX_H"}, {0x30CA, "RESASG_SUBTYPE_RA_VIRTID"}, {0x30CB, "RESASG_SUBTYPE_RA_MONITORS"}, }; k3conf_0.3/soc/am65x/am65x_rm_info.h0000664000175000017500000000342114504336513014115 0ustar /* * AM65X RM Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM65X_RM_INFO_H #define __AM65X_RM_INFO_H #define AM65X_MAX_RES 52 extern struct ti_sci_rm_info am65x_rm_info[]; #endif /* __AM65X_RM_INFO_H */ k3conf_0.3/soc/am65x/am65x_host_info.h0000664000175000017500000000451514504336513014461 0ustar /* * AM65X Host Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM65X_HOST_INFO_H #define __AM65X_HOST_INFO_H #define AM65X_HOST_ID_DMSC 0 #define AM65X_HOST_ID_R5_0 3 #define AM65X_HOST_ID_R5_1 4 #define AM65X_HOST_ID_R5_2 5 #define AM65X_HOST_ID_R5_3 6 #define AM65X_HOST_ID_A53_0 10 #define AM65X_HOST_ID_A53_1 11 #define AM65X_HOST_ID_A53_2 12 #define AM65X_HOST_ID_A53_3 13 #define AM65X_HOST_ID_A53_4 14 #define AM65X_HOST_ID_A53_5 15 #define AM65X_HOST_ID_A53_6 16 #define AM65X_HOST_ID_A53_7 17 #define AM65X_HOST_ID_GPU_0 30 #define AM65X_HOST_ID_GPU_1 31 #define AM65X_HOST_ID_ICSSG_0 50 #define AM65X_HOST_ID_ICSSG_1 51 #define AM65X_HOST_ID_ICSSG_2 52 #define AM65X_MAX_HOST_IDS 18 extern struct ti_sci_host_info am65x_host_info[]; #endif /* __AM65X_HOST_INFO_H */ k3conf_0.3/soc/am65x/am65x_sec_proxy_info.h0000664000175000017500000000365014504336513015516 0ustar /* * AM65X Sec Proxy Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM65X_SEC_PROXY_INFO_H #define __AM65X_SEC_PROXY_INFO_H #define AM65X_MAIN_SEC_PROXY_THREADS 65 #define AM65X_MCU_SEC_PROXY_THREADS 20 extern struct ti_sci_sec_proxy_info am65x_main_sp_info[]; extern struct ti_sci_sec_proxy_info am65x_mcu_sp_info[]; #endif /* __AM65X_SEC_PROXY_INFO_H */ k3conf_0.3/soc/am62px/0000775000175000017500000000000014522734227011454 5ustar k3conf_0.3/soc/am62px/am62px_processors_info.h0000664000175000017500000000351414522734227016242 0ustar /* * AM62PX Processor Info * * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM62PX_PROCESSOR_INFO_H #define __AM62PX_PROCESSOR_INFO_H #define AM62PX_MAX_PROCESSORS_IDS 7 extern struct ti_sci_processors_info am62px_processors_info[]; #endif /* __AM62PX_PROCESSOR_INFO_H */ k3conf_0.3/soc/am62px/am62px_host_info.c0000664000175000017500000000515614522734227015014 0ustar /* * AM62PX Hosts Info * * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_host_info am62px_host_info[] = { {0, "TIFS", "Secure", "TI Foundational Security"}, {10, "A53_0", "Secure", "Cortex A53 context 0 on MAIN domain"}, {11, "A53_1", "Secure", "Cortex A53 context 1 on MAIN domain"}, {12, "A53_2", "Non Secure", "Cortex A53 context 2 on MAIN domain"}, {13, "A53_3", "Non Secure", "Cortex A53 context 3 on MAIN domain"}, {14, "A53_4", "Non Secure", "Cortex A53 context 4 on MAIN domain"}, {30, "MCU_0_R5_0", "Non Secure", "MCU R5"}, {31, "GPU_0", "Non Secure", "GPU context 0 on MAIN domain"}, {32, "GPU_1", "Non Secure", "GPU context 1 on MAIN domain"}, {35, "WKUP_0_R5_0", "Secure", "Cortex R5_0 context 0 on WKUP domain (BOOT)"}, {36, "WKUP_0_R5_1", "Non Secure", "Cortex R5_0 context 1 on WKUP domain"}, {250, "DM2TIFS", "Secure", "DM to TIFS communication"}, {251, "TIFS2DM", "Non Secure", "TIFS to DM communication"}, {253, "HSM", "Secure", "HSM Controller"}, {254, "DM", "Non Secure", "Device Management"}, }; k3conf_0.3/soc/am62px/am62px_processors_info.c0000664000175000017500000000371714522734227016242 0ustar /* * AM62PX Processor Info * * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_processors_info am62px_processors_info[] = { {121, 0, 0x01, "WKUP_R5FSS0_CORE0"}, {9, 0, 0x03, "MCU_R5FSS0_CORE0"}, {135, 0, 0x20, "A53SS0_CORE_0"}, {136, 0, 0x21, "A53SS0_CORE_1"}, {137, 0, 0x22, "A53SS0_CORE_2"}, {138, 0, 0x23, "A53SS0_CORE_3"}, {225, 0, 0x80, "HSM0"}, }; k3conf_0.3/soc/am62px/am62px_sec_proxy_info.h0000664000175000017500000000365714522734227016063 0ustar /* * AM62PX Sec Proxy Info * * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM62PX_SEC_PROXY_INFO_H #define __AM62PX_SEC_PROXY_INFO_H #define AM62PX_MAIN_SEC_PROXY_THREADS 33 #define AM62PX_MCU_SEC_PROXY_THREADS 4 extern struct ti_sci_sec_proxy_info am62px_main_sp_info[]; extern struct ti_sci_sec_proxy_info am62px_mcu_sp_info[]; #endif /* __AM62PX_SEC_PROXY_INFO_H */ k3conf_0.3/soc/am62px/am62px_sec_proxy_info.c0000664000175000017500000000670614522734227016054 0ustar /* * AM62PX Sec Proxy Info * * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_sec_proxy_info am62px_main_sp_info[] = { {70, "read", 34, "DM", "nonsec_low_priority_rx"}, {69, "write", 11, "DM", "nonsec_WKUP_0_R5_1_response_tx"}, {68, "write", 1, "DM", "nonsec_GPU_0_response_tx"}, {67, "write", 1, "DM", "nonsec_GPU_1_response_tx"}, {66, "write", 6, "DM", "nonsec_A53_2_response_tx"}, {65, "write", 6, "DM", "nonsec_A53_3_response_tx"}, {64, "write", 6, "DM", "nonsec_A53_4_response_tx"}, {63, "write", 6, "DM", "nonsec_MCU_0_R5_0_response_tx"}, {62, "write", 4, "DM", "nonsec_TIFS2DM_response_tx"}, {0, "read", 11, "WKUP_0_R5_0", "response"}, {1, "write", 10, "WKUP_0_R5_0", "low_priority"}, {2, "read", 11, "WKUP_0_R5_1", "response"}, {3, "write", 10, "WKUP_0_R5_1", "low_priority"}, {4, "read", 1, "GPU_0", "response"}, {5, "write", 1, "GPU_0", "low_priority"}, {6, "read", 1, "GPU_1", "response"}, {7, "write", 1, "GPU_1", "low_priority"}, {8, "read", 11, "A53_0", "response"}, {9, "write", 10, "A53_0", "low_priority"}, {10, "read", 11, "A53_1", "response"}, {11, "write", 10, "A53_1", "low_priority"}, {12, "read", 6, "A53_2", "response"}, {13, "write", 5, "A53_2", "low_priority"}, {14, "read", 6, "A53_3", "response"}, {15, "write", 5, "A53_3", "low_priority"}, {16, "read", 6, "A53_4", "response"}, {17, "write", 5, "A53_4", "low_priority"}, {18, "read", 6, "MCU_0_R5_0", "response"}, {19, "write", 5, "MCU_0_R5_0", "low_priority"}, {20, "read", 4, "DM2TIFS", "response"}, {21, "write", 2, "DM2TIFS", "low_priority"}, {22, "read", 4, "TIFS2DM", "response"}, {23, "write", 2, "TIFS2DM", "low_priority"}, }; struct ti_sci_sec_proxy_info am62px_mcu_sp_info[] = { {15, "read", 8, "TIFS_HSM", "sec_low_priority_rx"}, {14, "write", 8, "TIFS_HSM", "sec_HSM_response_tx"}, {0, "read", 8, "HSM", "response"}, {1, "write", 8, "HSM", "low_priority"}, }; k3conf_0.3/soc/am62px/am62px_rm_info.h0000664000175000017500000000342714522734227014461 0ustar /* * AM62PX RM Info * * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM62PX_RM_INFO_H #define __AM62PX_RM_INFO_H #define AM62PX_MAX_RES 65 extern struct ti_sci_rm_info am62px_rm_info[]; #endif /* __AM62PX_RM_INFO_H */ k3conf_0.3/soc/am62px/am62px_clocks_info.c0000664000175000017500000022677114511032107015307 0ustar /* * AM62PX Clocks Info * * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_clocks_info am62px_clocks_info[] = { {166, 2, "DEV_A53SS0_A53_DIVH_CLK4_OBSCLK_OUT_CLK", "Output clock"}, {166, 3, "DEV_A53SS0_COREPAC_ARM_CLK_CLK", "Input clock"}, {166, 5, "DEV_A53SS0_PLL_CTRL_CLK", "Input clock"}, {135, 0, "DEV_A53SS0_CORE_0_A53_CORE0_ARM_CLK_CLK", "Input clock"}, {136, 0, "DEV_A53SS0_CORE_1_A53_CORE1_ARM_CLK_CLK", "Input clock"}, {137, 0, "DEV_A53SS0_CORE_2_A53_CORE2_ARM_CLK_CLK", "Input clock"}, {138, 0, "DEV_A53SS0_CORE_3_A53_CORE3_ARM_CLK_CLK", "Input clock"}, {172, 0, "DEV_A53_RS_BW_LIMITER0_CLK_CLK", "Input clock"}, {173, 0, "DEV_A53_WS_BW_LIMITER1_CLK_CLK", "Input clock"}, {157, 0, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN", "Input muxed clock"}, {157, 1, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 2, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 3, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 6, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 7, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 8, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 15, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 16, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 17, "DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT", "Output clock"}, {157, 18, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN", "Input muxed clock"}, {157, 19, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 20, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 21, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 24, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 25, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 26, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 33, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 34, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 35, "DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT", "Output clock"}, {157, 36, "DEV_BOARD0_CLKOUT0_IN", "Input muxed clock"}, {157, 37, "DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK5", "Parent input clock option to DEV_BOARD0_CLKOUT0_IN"}, {157, 38, "DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK10", "Parent input clock option to DEV_BOARD0_CLKOUT0_IN"}, {157, 39, "DEV_BOARD0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Output clock"}, {157, 40, "DEV_BOARD0_DDR0_CK0_IN", "Input clock"}, {157, 49, "DEV_BOARD0_EXT_REFCLK1_OUT", "Output clock"}, {157, 50, "DEV_BOARD0_GPMC0_CLKLB_IN", "Input clock"}, {157, 51, "DEV_BOARD0_GPMC0_CLKLB_OUT", "Output clock"}, {157, 52, "DEV_BOARD0_GPMC0_CLK_IN", "Input clock"}, {157, 53, "DEV_BOARD0_GPMC0_FCLK_MUX_IN", "Input clock"}, {157, 54, "DEV_BOARD0_I2C0_SCL_IN", "Input clock"}, {157, 55, "DEV_BOARD0_I2C0_SCL_OUT", "Output clock"}, {157, 56, "DEV_BOARD0_I2C1_SCL_IN", "Input clock"}, {157, 57, "DEV_BOARD0_I2C1_SCL_OUT", "Output clock"}, {157, 58, "DEV_BOARD0_I2C2_SCL_IN", "Input clock"}, {157, 59, "DEV_BOARD0_I2C2_SCL_OUT", "Output clock"}, {157, 60, "DEV_BOARD0_I2C3_SCL_IN", "Input clock"}, {157, 61, "DEV_BOARD0_I2C3_SCL_OUT", "Output clock"}, {157, 63, "DEV_BOARD0_MCASP0_ACLKR_IN", "Input clock"}, {157, 64, "DEV_BOARD0_MCASP0_ACLKR_OUT", "Output clock"}, {157, 65, "DEV_BOARD0_MCASP0_ACLKX_IN", "Input clock"}, {157, 66, "DEV_BOARD0_MCASP0_ACLKX_OUT", "Output clock"}, {157, 67, "DEV_BOARD0_MCASP0_AFSR_IN", "Input clock"}, {157, 68, "DEV_BOARD0_MCASP0_AFSX_IN", "Input clock"}, {157, 69, "DEV_BOARD0_MCASP1_ACLKR_IN", "Input clock"}, {157, 70, "DEV_BOARD0_MCASP1_ACLKR_OUT", "Output clock"}, {157, 71, "DEV_BOARD0_MCASP1_ACLKX_IN", "Input clock"}, {157, 72, "DEV_BOARD0_MCASP1_ACLKX_OUT", "Output clock"}, {157, 73, "DEV_BOARD0_MCASP1_AFSR_IN", "Input clock"}, {157, 74, "DEV_BOARD0_MCASP1_AFSX_IN", "Input clock"}, {157, 75, "DEV_BOARD0_MCASP2_ACLKR_IN", "Input clock"}, {157, 76, "DEV_BOARD0_MCASP2_ACLKR_OUT", "Output clock"}, {157, 77, "DEV_BOARD0_MCASP2_ACLKX_IN", "Input clock"}, {157, 78, "DEV_BOARD0_MCASP2_ACLKX_OUT", "Output clock"}, {157, 79, "DEV_BOARD0_MCASP2_AFSR_IN", "Input clock"}, {157, 80, "DEV_BOARD0_MCASP2_AFSX_IN", "Input clock"}, {157, 81, "DEV_BOARD0_MCU_EXT_REFCLK0_OUT", "Output clock"}, {157, 83, "DEV_BOARD0_MCU_I2C0_SCL_OUT", "Output clock"}, {157, 84, "DEV_BOARD0_MCU_OBSCLK0_IN", "Input muxed clock"}, {157, 85, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"}, {157, 86, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"}, {157, 87, "DEV_BOARD0_MCU_SPI0_CLK_IN", "Input clock"}, {157, 88, "DEV_BOARD0_MCU_SPI0_CLK_OUT", "Output clock"}, {157, 89, "DEV_BOARD0_MCU_SPI1_CLK_IN", "Input clock"}, {157, 90, "DEV_BOARD0_MCU_SPI1_CLK_OUT", "Output clock"}, {157, 91, "DEV_BOARD0_MCU_SYSCLKOUT0_IN", "Input clock"}, {157, 92, "DEV_BOARD0_MCU_TIMER_IO0_IN", "Input clock"}, {157, 93, "DEV_BOARD0_MCU_TIMER_IO1_IN", "Input clock"}, {157, 94, "DEV_BOARD0_MCU_TIMER_IO2_IN", "Input clock"}, {157, 95, "DEV_BOARD0_MCU_TIMER_IO3_IN", "Input clock"}, {157, 96, "DEV_BOARD0_MDIO0_MDC_IN", "Input clock"}, {157, 101, "DEV_BOARD0_MMC1_CLKLB_IN", "Input clock"}, {157, 102, "DEV_BOARD0_MMC1_CLKLB_OUT", "Output clock"}, {157, 103, "DEV_BOARD0_MMC1_CLK_IN", "Input clock"}, {157, 104, "DEV_BOARD0_MMC1_CLK_OUT", "Output clock"}, {157, 105, "DEV_BOARD0_MMC2_CLKLB_IN", "Input clock"}, {157, 106, "DEV_BOARD0_MMC2_CLKLB_OUT", "Output clock"}, {157, 107, "DEV_BOARD0_MMC2_CLK_IN", "Input clock"}, {157, 108, "DEV_BOARD0_MMC2_CLK_OUT", "Output clock"}, {157, 109, "DEV_BOARD0_OBSCLK0_IN", "Input muxed clock"}, {157, 110, "DEV_BOARD0_OBSCLK0_IN_PARENT_MAIN_OBSCLK_DIV_OUT0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 111, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 142, "DEV_BOARD0_OBSCLK1_IN", "Input clock"}, {157, 143, "DEV_BOARD0_OSPI0_CLK_IN", "Input clock"}, {157, 144, "DEV_BOARD0_OSPI0_DQS_OUT", "Output clock"}, {157, 145, "DEV_BOARD0_OSPI0_LBCLKO_IN", "Input clock"}, {157, 146, "DEV_BOARD0_OSPI0_LBCLKO_OUT", "Output clock"}, {157, 147, "DEV_BOARD0_RGMII1_RXC_OUT", "Output clock"}, {157, 150, "DEV_BOARD0_RGMII2_RXC_OUT", "Output clock"}, {157, 153, "DEV_BOARD0_RMII1_REF_CLK_OUT", "Output clock"}, {157, 154, "DEV_BOARD0_RMII2_REF_CLK_OUT", "Output clock"}, {157, 155, "DEV_BOARD0_SPI0_CLK_IN", "Input clock"}, {157, 156, "DEV_BOARD0_SPI0_CLK_OUT", "Output clock"}, {157, 157, "DEV_BOARD0_SPI1_CLK_IN", "Input clock"}, {157, 158, "DEV_BOARD0_SPI1_CLK_OUT", "Output clock"}, {157, 159, "DEV_BOARD0_SPI2_CLK_IN", "Input clock"}, {157, 160, "DEV_BOARD0_SPI2_CLK_OUT", "Output clock"}, {157, 161, "DEV_BOARD0_SYSCLKOUT0_IN", "Input clock"}, {157, 162, "DEV_BOARD0_TCK_OUT", "Output clock"}, {157, 163, "DEV_BOARD0_TIMER_IO0_IN", "Input clock"}, {157, 164, "DEV_BOARD0_TIMER_IO1_IN", "Input clock"}, {157, 165, "DEV_BOARD0_TIMER_IO2_IN", "Input clock"}, {157, 166, "DEV_BOARD0_TIMER_IO3_IN", "Input clock"}, {157, 167, "DEV_BOARD0_TIMER_IO4_IN", "Input clock"}, {157, 168, "DEV_BOARD0_TIMER_IO5_IN", "Input clock"}, {157, 169, "DEV_BOARD0_TIMER_IO6_IN", "Input clock"}, {157, 170, "DEV_BOARD0_TIMER_IO7_IN", "Input clock"}, {157, 171, "DEV_BOARD0_TRC_CLK_IN", "Input clock"}, {157, 172, "DEV_BOARD0_VOUT0_EXTPCLKIN_OUT", "Output clock"}, {157, 173, "DEV_BOARD0_VOUT0_PCLK_IN", "Input clock"}, {157, 174, "DEV_BOARD0_WKUP_CLKOUT0_IN", "Input muxed clock"}, {157, 175, "DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_WKUP_CLKOUT_SEL_OUT0", "Parent input clock option to DEV_BOARD0_WKUP_CLKOUT0_IN"}, {157, 176, "DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_WKUP_CLKOUT0_IN"}, {157, 178, "DEV_BOARD0_WKUP_I2C0_SCL_OUT", "Output clock"}, {157, 179, "DEV_BOARD0_MCASP0_AFSR_OUT", "Output clock"}, {157, 180, "DEV_BOARD0_MCASP0_AFSX_OUT", "Output clock"}, {157, 181, "DEV_BOARD0_MCASP1_AFSR_OUT", "Output clock"}, {157, 182, "DEV_BOARD0_MCASP1_AFSX_OUT", "Output clock"}, {157, 183, "DEV_BOARD0_MCASP2_AFSR_OUT", "Output clock"}, {157, 184, "DEV_BOARD0_MCASP2_AFSX_OUT", "Output clock"}, {157, 185, "DEV_BOARD0_CSI0_RXCLKN_OUT", "Output clock"}, {157, 186, "DEV_BOARD0_CSI0_RXCLKP_OUT", "Output clock"}, {193, 0, "DEV_CLK_32K_RC_SEL_DEV_VD_CLK", "Input muxed clock"}, {193, 1, "DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_CLK_32K_RC_SEL_DEV_VD_CLK"}, {193, 2, "DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT8", "Parent input clock option to DEV_CLK_32K_RC_SEL_DEV_VD_CLK"}, {193, 3, "DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3_DUP0", "Parent input clock option to DEV_CLK_32K_RC_SEL_DEV_VD_CLK"}, {193, 4, "DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_LFOSC0_CLKOUT", "Parent input clock option to DEV_CLK_32K_RC_SEL_DEV_VD_CLK"}, {204, 0, "DEV_CODEC0_VPU_ACLK_CLK", "Input clock"}, {204, 1, "DEV_CODEC0_VPU_BCLK_CLK", "Input clock"}, {204, 2, "DEV_CODEC0_VPU_CCLK_CLK", "Input clock"}, {204, 3, "DEV_CODEC0_VPU_PCLK_CLK", "Input clock"}, {221, 0, "DEV_CODEC_RS_BW_LIMITER2_CLK_CLK", "Input clock"}, {222, 0, "DEV_CODEC_WS_BW_LIMITER3_CLK_CLK", "Input clock"}, {13, 0, "DEV_CPSW0_CPPI_CLK_CLK", "Input clock"}, {13, 1, "DEV_CPSW0_CPTS_GENF0", "Output clock"}, {13, 2, "DEV_CPSW0_CPTS_GENF1", "Output clock"}, {13, 3, "DEV_CPSW0_CPTS_RFT_CLK", "Input muxed clock"}, {13, 4, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {13, 5, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {13, 6, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {13, 8, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {13, 9, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {13, 11, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {13, 13, "DEV_CPSW0_GMII1_MR_CLK", "Input clock"}, {13, 14, "DEV_CPSW0_GMII1_MT_CLK", "Input clock"}, {13, 15, "DEV_CPSW0_GMII2_MR_CLK", "Input clock"}, {13, 16, "DEV_CPSW0_GMII2_MT_CLK", "Input clock"}, {13, 17, "DEV_CPSW0_GMII_RFT_CLK", "Input clock"}, {13, 18, "DEV_CPSW0_MDIO_MDCLK_O", "Output clock"}, {13, 19, "DEV_CPSW0_RGMII_MHZ_250_CLK", "Input clock"}, {13, 20, "DEV_CPSW0_RGMII_MHZ_50_CLK", "Input clock"}, {13, 21, "DEV_CPSW0_RGMII_MHZ_5_CLK", "Input clock"}, {13, 22, "DEV_CPSW0_RMII1_MHZ_50_CLK", "Input clock"}, {13, 23, "DEV_CPSW0_RMII2_MHZ_50_CLK", "Input clock"}, {195, 0, "DEV_CPT2_AGGR0_VCLK_CLK", "Input clock"}, {194, 0, "DEV_CPT2_AGGR1_VCLK_CLK", "Input clock"}, {182, 0, "DEV_CSI_RX_IF0_MAIN_CLK_CLK", "Input clock"}, {182, 2, "DEV_CSI_RX_IF0_PPI_RX_BYTE_CLK", "Input clock"}, {182, 3, "DEV_CSI_RX_IF0_VBUS_CLK_CLK", "Input clock"}, {182, 4, "DEV_CSI_RX_IF0_VP_CLK_CLK", "Input clock"}, {2, 0, "DEV_DBGSUSPENDROUTER0_INTR_CLK", "Input clock"}, {16, 0, "DEV_DCC0_DCC_CLKSRC0_CLK", "Input clock"}, {16, 1, "DEV_DCC0_DCC_CLKSRC1_CLK", "Input clock"}, {16, 2, "DEV_DCC0_DCC_CLKSRC2_CLK", "Input clock"}, {16, 3, "DEV_DCC0_DCC_CLKSRC3_CLK", "Input clock"}, {16, 4, "DEV_DCC0_DCC_CLKSRC4_CLK", "Input clock"}, {16, 5, "DEV_DCC0_DCC_CLKSRC5_CLK", "Input clock"}, {16, 6, "DEV_DCC0_DCC_CLKSRC6_CLK", "Input clock"}, {16, 7, "DEV_DCC0_DCC_CLKSRC7_CLK", "Input clock"}, {16, 8, "DEV_DCC0_DCC_INPUT00_CLK", "Input clock"}, {16, 9, "DEV_DCC0_DCC_INPUT01_CLK", "Input clock"}, {16, 10, "DEV_DCC0_DCC_INPUT02_CLK", "Input clock"}, {16, 11, "DEV_DCC0_DCC_INPUT10_CLK", "Input clock"}, {16, 12, "DEV_DCC0_VBUS_CLK", "Input clock"}, {17, 0, "DEV_DCC1_DCC_CLKSRC0_CLK", "Input clock"}, {17, 1, "DEV_DCC1_DCC_CLKSRC1_CLK", "Input clock"}, {17, 2, "DEV_DCC1_DCC_CLKSRC2_CLK", "Input clock"}, {17, 3, "DEV_DCC1_DCC_CLKSRC3_CLK", "Input clock"}, {17, 4, "DEV_DCC1_DCC_CLKSRC4_CLK", "Input clock"}, {17, 5, "DEV_DCC1_DCC_CLKSRC5_CLK", "Input clock"}, {17, 6, "DEV_DCC1_DCC_CLKSRC6_CLK", "Input clock"}, {17, 7, "DEV_DCC1_DCC_CLKSRC7_CLK", "Input clock"}, {17, 8, "DEV_DCC1_DCC_INPUT00_CLK", "Input clock"}, {17, 9, "DEV_DCC1_DCC_INPUT01_CLK", "Input clock"}, {17, 10, "DEV_DCC1_DCC_INPUT02_CLK", "Input clock"}, {17, 11, "DEV_DCC1_DCC_INPUT10_CLK", "Input clock"}, {17, 12, "DEV_DCC1_VBUS_CLK", "Input clock"}, {18, 0, "DEV_DCC2_DCC_CLKSRC0_CLK", "Input clock"}, {18, 1, "DEV_DCC2_DCC_CLKSRC1_CLK", "Input clock"}, {18, 2, "DEV_DCC2_DCC_CLKSRC2_CLK", "Input clock"}, {18, 3, "DEV_DCC2_DCC_CLKSRC3_CLK", "Input clock"}, {18, 4, "DEV_DCC2_DCC_CLKSRC4_CLK", "Input clock"}, {18, 5, "DEV_DCC2_DCC_CLKSRC5_CLK", "Input clock"}, {18, 6, "DEV_DCC2_DCC_CLKSRC6_CLK", "Input clock"}, {18, 7, "DEV_DCC2_DCC_CLKSRC7_CLK", "Input clock"}, {18, 8, "DEV_DCC2_DCC_INPUT00_CLK", "Input clock"}, {18, 9, "DEV_DCC2_DCC_INPUT01_CLK", "Input clock"}, {18, 10, "DEV_DCC2_DCC_INPUT02_CLK", "Input clock"}, {18, 11, "DEV_DCC2_DCC_INPUT10_CLK", "Input clock"}, {18, 12, "DEV_DCC2_VBUS_CLK", "Input clock"}, {19, 0, "DEV_DCC3_DCC_CLKSRC0_CLK", "Input clock"}, {19, 1, "DEV_DCC3_DCC_CLKSRC1_CLK", "Input clock"}, {19, 3, "DEV_DCC3_DCC_CLKSRC3_CLK", "Input clock"}, {19, 4, "DEV_DCC3_DCC_CLKSRC4_CLK", "Input clock"}, {19, 5, "DEV_DCC3_DCC_CLKSRC5_CLK", "Input clock"}, {19, 6, "DEV_DCC3_DCC_CLKSRC6_CLK", "Input clock"}, {19, 7, "DEV_DCC3_DCC_CLKSRC7_CLK", "Input clock"}, {19, 8, "DEV_DCC3_DCC_INPUT00_CLK", "Input clock"}, {19, 9, "DEV_DCC3_DCC_INPUT01_CLK", "Input clock"}, {19, 10, "DEV_DCC3_DCC_INPUT02_CLK", "Input clock"}, {19, 11, "DEV_DCC3_DCC_INPUT10_CLK", "Input clock"}, {19, 12, "DEV_DCC3_VBUS_CLK", "Input clock"}, {20, 0, "DEV_DCC4_DCC_CLKSRC0_CLK", "Input clock"}, {20, 1, "DEV_DCC4_DCC_CLKSRC1_CLK", "Input clock"}, {20, 2, "DEV_DCC4_DCC_CLKSRC2_CLK", "Input clock"}, {20, 3, "DEV_DCC4_DCC_CLKSRC3_CLK", "Input clock"}, {20, 4, "DEV_DCC4_DCC_CLKSRC4_CLK", "Input clock"}, {20, 5, "DEV_DCC4_DCC_CLKSRC5_CLK", "Input clock"}, {20, 6, "DEV_DCC4_DCC_CLKSRC6_CLK", "Input clock"}, {20, 7, "DEV_DCC4_DCC_CLKSRC7_CLK", "Input clock"}, {20, 8, "DEV_DCC4_DCC_INPUT00_CLK", "Input clock"}, {20, 9, "DEV_DCC4_DCC_INPUT01_CLK", "Input clock"}, {20, 10, "DEV_DCC4_DCC_INPUT02_CLK", "Input clock"}, {20, 11, "DEV_DCC4_DCC_INPUT10_CLK", "Input clock"}, {20, 12, "DEV_DCC4_VBUS_CLK", "Input clock"}, {21, 0, "DEV_DCC5_DCC_CLKSRC0_CLK", "Input clock"}, {21, 2, "DEV_DCC5_DCC_CLKSRC2_CLK", "Input clock"}, {21, 3, "DEV_DCC5_DCC_CLKSRC3_CLK", "Input clock"}, {21, 4, "DEV_DCC5_DCC_CLKSRC4_CLK", "Input clock"}, {21, 5, "DEV_DCC5_DCC_CLKSRC5_CLK", "Input clock"}, {21, 6, "DEV_DCC5_DCC_CLKSRC6_CLK", "Input clock"}, {21, 7, "DEV_DCC5_DCC_CLKSRC7_CLK", "Input clock"}, {21, 8, "DEV_DCC5_DCC_INPUT00_CLK", "Input clock"}, {21, 9, "DEV_DCC5_DCC_INPUT01_CLK", "Input clock"}, {21, 10, "DEV_DCC5_DCC_INPUT02_CLK", "Input clock"}, {21, 11, "DEV_DCC5_DCC_INPUT10_CLK", "Input clock"}, {21, 12, "DEV_DCC5_VBUS_CLK", "Input clock"}, {183, 0, "DEV_DCC6_DCC_CLKSRC0_CLK", "Input clock"}, {183, 1, "DEV_DCC6_DCC_CLKSRC1_CLK", "Input clock"}, {183, 2, "DEV_DCC6_DCC_CLKSRC2_CLK", "Input clock"}, {183, 3, "DEV_DCC6_DCC_CLKSRC3_CLK", "Input clock"}, {183, 4, "DEV_DCC6_DCC_CLKSRC4_CLK", "Input clock"}, {183, 5, "DEV_DCC6_DCC_CLKSRC5_CLK", "Input clock"}, {183, 6, "DEV_DCC6_DCC_CLKSRC6_CLK", "Input clock"}, {183, 7, "DEV_DCC6_DCC_CLKSRC7_CLK", "Input clock"}, {183, 8, "DEV_DCC6_DCC_INPUT00_CLK", "Input clock"}, {183, 9, "DEV_DCC6_DCC_INPUT01_CLK", "Input clock"}, {183, 10, "DEV_DCC6_DCC_INPUT02_CLK", "Input clock"}, {183, 11, "DEV_DCC6_DCC_INPUT10_CLK", "Input clock"}, {183, 12, "DEV_DCC6_VBUS_CLK", "Input clock"}, {229, 0, "DEV_DCC7_DCC_CLKSRC0_CLK", "Input clock"}, {229, 1, "DEV_DCC7_DCC_CLKSRC1_CLK", "Input clock"}, {229, 2, "DEV_DCC7_DCC_CLKSRC2_CLK", "Input clock"}, {229, 5, "DEV_DCC7_DCC_CLKSRC5_CLK", "Input clock"}, {229, 6, "DEV_DCC7_DCC_CLKSRC6_CLK", "Input clock"}, {229, 7, "DEV_DCC7_DCC_CLKSRC7_CLK", "Input clock"}, {229, 8, "DEV_DCC7_DCC_INPUT00_CLK", "Input clock"}, {229, 9, "DEV_DCC7_DCC_INPUT01_CLK", "Input clock"}, {229, 10, "DEV_DCC7_DCC_INPUT02_CLK", "Input clock"}, {229, 11, "DEV_DCC7_DCC_INPUT10_CLK", "Input clock"}, {229, 12, "DEV_DCC7_VBUS_CLK", "Input clock"}, {230, 0, "DEV_DCC8_DCC_CLKSRC0_CLK", "Input clock"}, {230, 1, "DEV_DCC8_DCC_CLKSRC1_CLK", "Input clock"}, {230, 8, "DEV_DCC8_DCC_INPUT00_CLK", "Input clock"}, {230, 9, "DEV_DCC8_DCC_INPUT01_CLK", "Input clock"}, {230, 10, "DEV_DCC8_DCC_INPUT02_CLK", "Input clock"}, {230, 11, "DEV_DCC8_DCC_INPUT10_CLK", "Input clock"}, {230, 12, "DEV_DCC8_VBUS_CLK", "Input clock"}, {85, 0, "DEV_DDPA0_DDPA_CLK", "Input clock"}, {170, 0, "DEV_DDR32SS0_DDR_PLL_DIVH_CLK4_OBSCLK_OUT_CLK", "Output clock"}, {170, 1, "DEV_DDR32SS0_DDRSS_DDR_PLL_CLK", "Input clock"}, {170, 2, "DEV_DDR32SS0_DDRSS_TCK", "Input clock"}, {170, 3, "DEV_DDR32SS0_PLL_CTRL_CLK", "Input clock"}, {171, 0, "DEV_DEBUGSS0_CFG_CLK", "Input clock"}, {171, 1, "DEV_DEBUGSS0_DBG_CLK", "Input clock"}, {171, 2, "DEV_DEBUGSS0_SYS_CLK", "Input clock"}, {24, 0, "DEV_DEBUGSS_WRAP0_ATB_CLK", "Input clock"}, {24, 1, "DEV_DEBUGSS_WRAP0_CORE_CLK", "Input clock"}, {24, 2, "DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK", "Output clock"}, {24, 20, "DEV_DEBUGSS_WRAP0_JTAG_TCK", "Input clock"}, {24, 21, "DEV_DEBUGSS_WRAP0_P1500_WRCK", "Input clock"}, {24, 22, "DEV_DEBUGSS_WRAP0_TREXPT_CLK", "Input clock"}, {26, 0, "DEV_DMASS0_BCDMA_0_CLK", "Input clock"}, {27, 0, "DEV_DMASS0_CBASS_0_CLK", "Input clock"}, {28, 0, "DEV_DMASS0_INTAGGR_0_CLK", "Input clock"}, {29, 0, "DEV_DMASS0_IPCSS_0_CLK", "Input clock"}, {30, 0, "DEV_DMASS0_PKTDMA_0_CLK", "Input clock"}, {33, 0, "DEV_DMASS0_RINGACC_0_CLK", "Input clock"}, {199, 0, "DEV_DMASS1_BCDMA_0_CLK", "Input clock"}, {200, 0, "DEV_DMASS1_INTAGGR_0_CLK", "Input clock"}, {185, 2, "DEV_DPHY_RX0_IO_RX_CL_L_M", "Input clock"}, {185, 3, "DEV_DPHY_RX0_IO_RX_CL_L_P", "Input clock"}, {185, 4, "DEV_DPHY_RX0_JTAG_TCK", "Input clock"}, {185, 5, "DEV_DPHY_RX0_MAIN_CLK_CLK", "Input clock"}, {185, 6, "DEV_DPHY_RX0_PPI_RX_BYTE_CLK", "Output clock"}, {238, 0, "DEV_DPHY_TX0_CLK", "Input clock"}, {238, 1, "DEV_DPHY_TX0_DPHY_REF_CLK", "Input muxed clock"}, {238, 2, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"}, {238, 3, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT9_CLK", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"}, {238, 4, "DEV_DPHY_TX0_IP1_PPI_M_RXCLKESC_CLK", "Output clock"}, {238, 5, "DEV_DPHY_TX0_IP1_PPI_M_TXCLKESC_CLK", "Input clock"}, {238, 6, "DEV_DPHY_TX0_IP1_PPI_TXBYTECLKHS_CL_CLK", "Output clock"}, {238, 8, "DEV_DPHY_TX0_IP2_PPI_M_TXCLKESC_CLK", "Input clock"}, {238, 11, "DEV_DPHY_TX0_IP3_PPI_M_TXCLKESC_CLK", "Input clock"}, {238, 14, "DEV_DPHY_TX0_IP4_PPI_M_TXCLKESC_CLK", "Input clock"}, {238, 16, "DEV_DPHY_TX0_PSM_CLK", "Input clock"}, {238, 20, "DEV_DPHY_TX0_TAP_TCK", "Input clock"}, {186, 0, "DEV_DSS0_DPI_0_IN_CLK", "Input clock"}, {186, 2, "DEV_DSS0_DPI_1_IN_CLK", "Input muxed clock"}, {186, 3, "DEV_DSS0_DPI_1_IN_CLK_PARENT_HSDIV0_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DPI_1_IN_CLK"}, {186, 4, "DEV_DSS0_DPI_1_IN_CLK_PARENT_BOARD_0_VOUT0_EXTPCLKIN_OUT", "Parent input clock option to DEV_DSS0_DPI_1_IN_CLK"}, {186, 5, "DEV_DSS0_DPI_1_OUT_CLK", "Output clock"}, {186, 6, "DEV_DSS0_DSS_FUNC_CLK", "Input clock"}, {232, 0, "DEV_DSS1_DPI_0_IN_CLK", "Input muxed clock"}, {232, 1, "DEV_DSS1_DPI_0_IN_CLK_PARENT_MAIN_DSS1_DPI0__PLLSEL_OUT0", "Parent input clock option to DEV_DSS1_DPI_0_IN_CLK"}, {232, 2, "DEV_DSS1_DPI_0_IN_CLK_PARENT_BOARD_0_VOUT0_EXTPCLKIN_OUT", "Parent input clock option to DEV_DSS1_DPI_0_IN_CLK"}, {232, 3, "DEV_DSS1_DPI_0_OUT_CLK", "Output clock"}, {232, 4, "DEV_DSS1_DPI_1_IN_CLK", "Input muxed clock"}, {232, 5, "DEV_DSS1_DPI_1_IN_CLK_PARENT_MAIN_DSS1_DPI1__PLLSEL_OUT0", "Parent input clock option to DEV_DSS1_DPI_1_IN_CLK"}, {232, 6, "DEV_DSS1_DPI_1_IN_CLK_PARENT_BOARD_0_VOUT0_EXTPCLKIN_OUT", "Parent input clock option to DEV_DSS1_DPI_1_IN_CLK"}, {232, 7, "DEV_DSS1_DPI_1_OUT_CLK", "Output clock"}, {232, 8, "DEV_DSS1_DSS_FUNC_CLK", "Input clock"}, {241, 0, "DEV_DSS1_DPI0_PLLSEL_DEV_VD_CLK", "Input muxed clock"}, {241, 1, "DEV_DSS1_DPI0_PLLSEL_DEV_VD_CLK_PARENT_HSDIV0_16FFT_MAIN_18_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS1_DPI0_PLLSEL_DEV_VD_CLK"}, {241, 2, "DEV_DSS1_DPI0_PLLSEL_DEV_VD_CLK_PARENT_HSDIV0_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS1_DPI0_PLLSEL_DEV_VD_CLK"}, {240, 0, "DEV_DSS1_DPI1_PLLSEL_DEV_VD_CLK", "Input muxed clock"}, {240, 1, "DEV_DSS1_DPI1_PLLSEL_DEV_VD_CLK_PARENT_HSDIV0_16FFT_MAIN_18_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS1_DPI1_PLLSEL_DEV_VD_CLK"}, {240, 2, "DEV_DSS1_DPI1_PLLSEL_DEV_VD_CLK_PARENT_HSDIV0_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS1_DPI1_PLLSEL_DEV_VD_CLK"}, {231, 0, "DEV_DSS_DSI0_DPHY_0_RX_ESC_CLK", "Input clock"}, {231, 1, "DEV_DSS_DSI0_DPHY_0_TX_ESC_CLK", "Input clock"}, {231, 2, "DEV_DSS_DSI0_DPI_0_CLK", "Input clock"}, {231, 3, "DEV_DSS_DSI0_PLL_CTRL_CLK", "Input clock"}, {231, 4, "DEV_DSS_DSI0_PPI_0_TXBYTECLKHS_CL_CLK", "Input clock"}, {231, 5, "DEV_DSS_DSI0_SYS_CLK", "Input clock"}, {51, 0, "DEV_ECAP0_VBUS_CLK", "Input clock"}, {52, 0, "DEV_ECAP1_VBUS_CLK", "Input clock"}, {53, 0, "DEV_ECAP2_VBUS_CLK", "Input clock"}, {54, 0, "DEV_ELM0_VBUSP_CLK", "Input clock"}, {86, 0, "DEV_EPWM0_VBUSP_CLK", "Input clock"}, {87, 0, "DEV_EPWM1_VBUSP_CLK", "Input clock"}, {88, 0, "DEV_EPWM2_VBUSP_CLK", "Input clock"}, {59, 0, "DEV_EQEP0_VBUS_CLK", "Input clock"}, {60, 0, "DEV_EQEP1_VBUS_CLK", "Input clock"}, {62, 0, "DEV_EQEP2_VBUS_CLK", "Input clock"}, {63, 0, "DEV_ESM0_CLK", "Input clock"}, {74, 0, "DEV_FSS0_FSAS_0_GCLK", "Input clock"}, {75, 0, "DEV_FSS0_OSPI_0_OSPI_DQS_CLK", "Input clock"}, {75, 1, "DEV_FSS0_OSPI_0_OSPI_HCLK_CLK", "Input clock"}, {75, 2, "DEV_FSS0_OSPI_0_OSPI_ICLK_CLK", "Input muxed clock"}, {75, 3, "DEV_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI0_DQS_OUT", "Parent input clock option to DEV_FSS0_OSPI_0_OSPI_ICLK_CLK"}, {75, 4, "DEV_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI0_LBCLKO_OUT", "Parent input clock option to DEV_FSS0_OSPI_0_OSPI_ICLK_CLK"}, {75, 5, "DEV_FSS0_OSPI_0_OSPI_OCLK_CLK", "Output clock"}, {75, 6, "DEV_FSS0_OSPI_0_OSPI_PCLK_CLK", "Input clock"}, {75, 7, "DEV_FSS0_OSPI_0_OSPI_RCLK_CLK", "Input muxed clock"}, {75, 8, "DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_FSS0_OSPI_0_OSPI_RCLK_CLK"}, {75, 9, "DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT5_CLK", "Parent input clock option to DEV_FSS0_OSPI_0_OSPI_RCLK_CLK"}, {76, 0, "DEV_GICSS0_VCLK_CLK", "Input clock"}, {77, 0, "DEV_GPIO0_MMR_CLK", "Input clock"}, {78, 0, "DEV_GPIO1_MMR_CLK", "Input clock"}, {80, 0, "DEV_GPMC0_FUNC_CLK", "Input muxed clock"}, {80, 1, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_GPMC0_FUNC_CLK"}, {80, 2, "DEV_GPMC0_FUNC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK", "Parent input clock option to DEV_GPMC0_FUNC_CLK"}, {80, 3, "DEV_GPMC0_PI_GPMC_RET_CLK", "Input clock"}, {80, 4, "DEV_GPMC0_PO_GPMC_DEV_CLK", "Output clock"}, {80, 5, "DEV_GPMC0_VBUSM_CLK", "Input clock"}, {237, 2, "DEV_GPU0_GPU_DCC_CLK", "Output clock"}, {237, 3, "DEV_GPU0_GPU_PLL_CLK", "Input clock"}, {237, 4, "DEV_GPU0_PLL_CTRL_CLK", "Input clock"}, {174, 0, "DEV_GPU_RS_BW_LIMITER9_CLK_CLK", "Input clock"}, {175, 0, "DEV_GPU_WS_BW_LIMITER10_CLK_CLK", "Input clock"}, {225, 0, "DEV_HSM0_DAP_CLK", "Input clock"}, {102, 0, "DEV_I2C0_CLK", "Input clock"}, {102, 1, "DEV_I2C0_PISCL", "Input clock"}, {102, 2, "DEV_I2C0_PISYS_CLK", "Input clock"}, {102, 3, "DEV_I2C0_PORSCL", "Output clock"}, {103, 0, "DEV_I2C1_CLK", "Input clock"}, {103, 1, "DEV_I2C1_PISCL", "Input clock"}, {103, 2, "DEV_I2C1_PISYS_CLK", "Input clock"}, {103, 3, "DEV_I2C1_PORSCL", "Output clock"}, {104, 0, "DEV_I2C2_CLK", "Input clock"}, {104, 1, "DEV_I2C2_PISCL", "Input clock"}, {104, 2, "DEV_I2C2_PISYS_CLK", "Input clock"}, {104, 3, "DEV_I2C2_PORSCL", "Output clock"}, {105, 0, "DEV_I2C3_CLK", "Input clock"}, {105, 1, "DEV_I2C3_PISCL", "Input clock"}, {105, 2, "DEV_I2C3_PISYS_CLK", "Input clock"}, {105, 3, "DEV_I2C3_PORSCL", "Output clock"}, {83, 1, "DEV_LED0_VBUS_CLK", "Input clock"}, {3, 0, "DEV_MAIN_GPIOMUX_INTROUTER0_INTR_CLK", "Input clock"}, {98, 1, "DEV_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"}, {98, 2, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, {98, 3, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, {98, 4, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, {98, 5, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, {98, 6, "DEV_MCAN0_MCANSS_HCLK_CLK", "Input clock"}, {99, 1, "DEV_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"}, {99, 2, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, {99, 3, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, {99, 4, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, {99, 5, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, {99, 6, "DEV_MCAN1_MCANSS_HCLK_CLK", "Input clock"}, {190, 0, "DEV_MCASP0_AUX_CLK", "Input muxed clock"}, {190, 1, "DEV_MCASP0_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, {190, 2, "DEV_MCASP0_AUX_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, {190, 3, "DEV_MCASP0_MCASP_ACLKR_PIN", "Input clock"}, {190, 4, "DEV_MCASP0_MCASP_ACLKR_POUT", "Output clock"}, {190, 5, "DEV_MCASP0_MCASP_ACLKX_PIN", "Input clock"}, {190, 6, "DEV_MCASP0_MCASP_ACLKX_POUT", "Output clock"}, {190, 7, "DEV_MCASP0_MCASP_AFSR_POUT", "Output clock"}, {190, 8, "DEV_MCASP0_MCASP_AFSX_POUT", "Output clock"}, {190, 9, "DEV_MCASP0_MCASP_AHCLKR_PIN", "Input muxed clock"}, {190, 10, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {190, 11, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {190, 12, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {190, 13, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {190, 26, "DEV_MCASP0_MCASP_AHCLKR_POUT", "Output clock"}, {190, 27, "DEV_MCASP0_MCASP_AHCLKX_PIN", "Input muxed clock"}, {190, 28, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {190, 29, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {190, 30, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {190, 31, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {190, 44, "DEV_MCASP0_MCASP_AHCLKX_POUT", "Output clock"}, {190, 45, "DEV_MCASP0_VBUSP_CLK", "Input clock"}, {190, 46, "DEV_MCASP0_MCASP_AFSR_PIN", "Input clock"}, {190, 47, "DEV_MCASP0_MCASP_AFSX_PIN", "Input clock"}, {191, 0, "DEV_MCASP1_AUX_CLK", "Input muxed clock"}, {191, 1, "DEV_MCASP1_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, {191, 2, "DEV_MCASP1_AUX_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, {191, 3, "DEV_MCASP1_MCASP_ACLKR_PIN", "Input clock"}, {191, 4, "DEV_MCASP1_MCASP_ACLKR_POUT", "Output clock"}, {191, 5, "DEV_MCASP1_MCASP_ACLKX_PIN", "Input clock"}, {191, 6, "DEV_MCASP1_MCASP_ACLKX_POUT", "Output clock"}, {191, 7, "DEV_MCASP1_MCASP_AFSR_POUT", "Output clock"}, {191, 8, "DEV_MCASP1_MCASP_AFSX_POUT", "Output clock"}, {191, 9, "DEV_MCASP1_MCASP_AHCLKR_PIN", "Input muxed clock"}, {191, 10, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {191, 11, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {191, 12, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {191, 13, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {191, 26, "DEV_MCASP1_MCASP_AHCLKR_POUT", "Output clock"}, {191, 27, "DEV_MCASP1_MCASP_AHCLKX_PIN", "Input muxed clock"}, {191, 28, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {191, 29, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {191, 30, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {191, 31, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {191, 44, "DEV_MCASP1_MCASP_AHCLKX_POUT", "Output clock"}, {191, 45, "DEV_MCASP1_VBUSP_CLK", "Input clock"}, {191, 46, "DEV_MCASP1_MCASP_AFSR_PIN", "Input clock"}, {191, 47, "DEV_MCASP1_MCASP_AFSX_PIN", "Input clock"}, {192, 0, "DEV_MCASP2_AUX_CLK", "Input muxed clock"}, {192, 1, "DEV_MCASP2_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, {192, 2, "DEV_MCASP2_AUX_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, {192, 3, "DEV_MCASP2_MCASP_ACLKR_PIN", "Input clock"}, {192, 4, "DEV_MCASP2_MCASP_ACLKR_POUT", "Output clock"}, {192, 5, "DEV_MCASP2_MCASP_ACLKX_PIN", "Input clock"}, {192, 6, "DEV_MCASP2_MCASP_ACLKX_POUT", "Output clock"}, {192, 7, "DEV_MCASP2_MCASP_AFSR_POUT", "Output clock"}, {192, 8, "DEV_MCASP2_MCASP_AFSX_POUT", "Output clock"}, {192, 9, "DEV_MCASP2_MCASP_AHCLKR_PIN", "Input muxed clock"}, {192, 10, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {192, 11, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {192, 12, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {192, 13, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {192, 26, "DEV_MCASP2_MCASP_AHCLKR_POUT", "Output clock"}, {192, 27, "DEV_MCASP2_MCASP_AHCLKX_PIN", "Input muxed clock"}, {192, 28, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {192, 29, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {192, 30, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {192, 31, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {192, 44, "DEV_MCASP2_MCASP_AHCLKX_POUT", "Output clock"}, {192, 45, "DEV_MCASP2_VBUSP_CLK", "Input clock"}, {192, 46, "DEV_MCASP2_MCASP_AFSR_PIN", "Input clock"}, {192, 47, "DEV_MCASP2_MCASP_AFSX_PIN", "Input clock"}, {116, 0, "DEV_MCRC64_0_CLK", "Input clock"}, {141, 0, "DEV_MCSPI0_CLKSPIREF_CLK", "Input clock"}, {141, 1, "DEV_MCSPI0_IO_CLKSPII_CLK", "Input muxed clock"}, {141, 2, "DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI0_CLK_OUT", "Parent input clock option to DEV_MCSPI0_IO_CLKSPII_CLK"}, {141, 3, "DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MAIN_0_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI0_IO_CLKSPII_CLK"}, {141, 4, "DEV_MCSPI0_IO_CLKSPIO_CLK", "Output clock"}, {141, 5, "DEV_MCSPI0_VBUSP_CLK", "Input clock"}, {142, 0, "DEV_MCSPI1_CLKSPIREF_CLK", "Input clock"}, {142, 1, "DEV_MCSPI1_IO_CLKSPII_CLK", "Input muxed clock"}, {142, 2, "DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI1_CLK_OUT", "Parent input clock option to DEV_MCSPI1_IO_CLKSPII_CLK"}, {142, 3, "DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_1_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI1_IO_CLKSPII_CLK"}, {142, 4, "DEV_MCSPI1_IO_CLKSPIO_CLK", "Output clock"}, {142, 5, "DEV_MCSPI1_VBUSP_CLK", "Input clock"}, {143, 0, "DEV_MCSPI2_CLKSPIREF_CLK", "Input clock"}, {143, 1, "DEV_MCSPI2_IO_CLKSPII_CLK", "Input muxed clock"}, {143, 2, "DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI2_CLK_OUT", "Parent input clock option to DEV_MCSPI2_IO_CLKSPII_CLK"}, {143, 3, "DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_SPI_MAIN_2_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI2_IO_CLKSPII_CLK"}, {143, 4, "DEV_MCSPI2_IO_CLKSPIO_CLK", "Output clock"}, {143, 5, "DEV_MCSPI2_VBUSP_CLK", "Input clock"}, {196, 0, "DEV_MCU_CPT2_AGGR0_VCLK_CLK", "Input clock"}, {23, 0, "DEV_MCU_DCC0_DCC_CLKSRC0_CLK", "Input clock"}, {23, 1, "DEV_MCU_DCC0_DCC_CLKSRC1_CLK", "Input clock"}, {23, 2, "DEV_MCU_DCC0_DCC_CLKSRC2_CLK", "Input clock"}, {23, 3, "DEV_MCU_DCC0_DCC_CLKSRC3_CLK", "Input clock"}, {23, 4, "DEV_MCU_DCC0_DCC_CLKSRC4_CLK", "Input clock"}, {23, 5, "DEV_MCU_DCC0_DCC_CLKSRC5_CLK", "Input clock"}, {23, 6, "DEV_MCU_DCC0_DCC_CLKSRC6_CLK", "Input clock"}, {23, 7, "DEV_MCU_DCC0_DCC_CLKSRC7_CLK", "Input clock"}, {23, 8, "DEV_MCU_DCC0_DCC_INPUT00_CLK", "Input clock"}, {23, 9, "DEV_MCU_DCC0_DCC_INPUT01_CLK", "Input clock"}, {23, 10, "DEV_MCU_DCC0_DCC_INPUT02_CLK", "Input clock"}, {23, 11, "DEV_MCU_DCC0_DCC_INPUT10_CLK", "Input clock"}, {23, 12, "DEV_MCU_DCC0_VBUS_CLK", "Input clock"}, {197, 0, "DEV_MCU_DCC1_DCC_CLKSRC0_CLK", "Input clock"}, {197, 1, "DEV_MCU_DCC1_DCC_CLKSRC1_CLK", "Input clock"}, {197, 5, "DEV_MCU_DCC1_DCC_CLKSRC5_CLK", "Input clock"}, {197, 6, "DEV_MCU_DCC1_DCC_CLKSRC6_CLK", "Input clock"}, {197, 7, "DEV_MCU_DCC1_DCC_CLKSRC7_CLK", "Input clock"}, {197, 8, "DEV_MCU_DCC1_DCC_INPUT00_CLK", "Input clock"}, {197, 9, "DEV_MCU_DCC1_DCC_INPUT01_CLK", "Input clock"}, {197, 10, "DEV_MCU_DCC1_DCC_INPUT02_CLK", "Input clock"}, {197, 11, "DEV_MCU_DCC1_DCC_INPUT10_CLK", "Input clock"}, {197, 12, "DEV_MCU_DCC1_VBUS_CLK", "Input clock"}, {79, 0, "DEV_MCU_GPIO0_MMR_CLK", "Input muxed clock"}, {79, 1, "DEV_MCU_GPIO0_MMR_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_MCU_GPIO0_MMR_CLK"}, {79, 2, "DEV_MCU_GPIO0_MMR_CLK_PARENT_GLUELOGIC_LFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_GPIO0_MMR_CLK"}, {79, 3, "DEV_MCU_GPIO0_MMR_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_MCU_GPIO0_MMR_CLK"}, {79, 4, "DEV_MCU_GPIO0_MMR_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_GPIO0_MMR_CLK"}, {106, 0, "DEV_MCU_I2C0_CLK", "Input clock"}, {106, 1, "DEV_MCU_I2C0_PISCL", "Input clock"}, {106, 2, "DEV_MCU_I2C0_PISYS_CLK", "Input clock"}, {106, 3, "DEV_MCU_I2C0_PORSCL", "Output clock"}, {188, 1, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"}, {188, 2, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, {188, 3, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, {188, 4, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, {188, 5, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT_DUP0", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, {188, 6, "DEV_MCU_MCAN0_MCANSS_HCLK_CLK", "Input clock"}, {189, 1, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"}, {189, 2, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, {189, 3, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, {189, 4, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, {189, 5, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT_DUP0", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, {189, 6, "DEV_MCU_MCAN1_MCANSS_HCLK_CLK", "Input clock"}, {100, 0, "DEV_MCU_MCRC64_0_CLK", "Input clock"}, {147, 0, "DEV_MCU_MCSPI0_CLKSPIREF_CLK", "Input clock"}, {147, 1, "DEV_MCU_MCSPI0_IO_CLKSPII_CLK", "Input muxed clock"}, {147, 2, "DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI0_CLK_OUT", "Parent input clock option to DEV_MCU_MCSPI0_IO_CLKSPII_CLK"}, {147, 3, "DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MCU_0_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCU_MCSPI0_IO_CLKSPII_CLK"}, {147, 4, "DEV_MCU_MCSPI0_IO_CLKSPIO_CLK", "Output clock"}, {147, 5, "DEV_MCU_MCSPI0_VBUSP_CLK", "Input clock"}, {148, 0, "DEV_MCU_MCSPI1_CLKSPIREF_CLK", "Input clock"}, {148, 1, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK", "Input muxed clock"}, {148, 2, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI1_CLK_OUT", "Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK"}, {148, 3, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MCU_1_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK"}, {148, 4, "DEV_MCU_MCSPI1_IO_CLKSPIO_CLK", "Output clock"}, {148, 5, "DEV_MCU_MCSPI1_VBUSP_CLK", "Input clock"}, {180, 3, "DEV_MCU_MCU_16FF0_PLL_CTRL_MCU_CLK24_CLK", "Input clock"}, {227, 0, "DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK", "Input muxed clock"}, {227, 1, "DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK"}, {227, 2, "DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK"}, {227, 3, "DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK"}, {227, 4, "DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK_DUP0", "Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK"}, {227, 5, "DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK"}, {227, 6, "DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK"}, {227, 7, "DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT8", "Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK"}, {227, 8, "DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK"}, {227, 9, "DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK"}, {203, 7, "DEV_MCU_PBIST0_CLK8_CLK", "Input clock"}, {9, 0, "DEV_MCU_R5FSS0_CORE0_CPU0_CLK", "Input clock"}, {9, 1, "DEV_MCU_R5FSS0_CORE0_INTERFACE0_CLK", "Input clock"}, {131, 0, "DEV_MCU_RTI0_RTI_CLK", "Input muxed clock"}, {131, 1, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, {131, 2, "DEV_MCU_RTI0_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, {131, 3, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, {131, 4, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, {131, 5, "DEV_MCU_RTI0_VBUSP_CLK", "Input clock"}, {35, 0, "DEV_MCU_TIMER0_TIMER_HCLK_CLK", "Input clock"}, {35, 1, "DEV_MCU_TIMER0_TIMER_PWM", "Output clock"}, {35, 2, "DEV_MCU_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"}, {35, 3, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 4, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 5, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 6, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV1_16FFT_MCU_0_HSDIVOUT5_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 7, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 8, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 9, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 10, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {48, 0, "DEV_MCU_TIMER1_TIMER_HCLK_CLK", "Input clock"}, {48, 1, "DEV_MCU_TIMER1_TIMER_PWM", "Output clock"}, {48, 2, "DEV_MCU_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"}, {48, 3, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMERCLKN_SEL_OUT1", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, {48, 4, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, {49, 0, "DEV_MCU_TIMER2_TIMER_HCLK_CLK", "Input clock"}, {49, 1, "DEV_MCU_TIMER2_TIMER_PWM", "Output clock"}, {49, 2, "DEV_MCU_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"}, {49, 3, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {49, 4, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {49, 5, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {49, 6, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV1_16FFT_MCU_0_HSDIVOUT5_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {49, 7, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {49, 8, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {49, 9, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {49, 10, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {50, 0, "DEV_MCU_TIMER3_TIMER_HCLK_CLK", "Input clock"}, {50, 1, "DEV_MCU_TIMER3_TIMER_PWM", "Output clock"}, {50, 2, "DEV_MCU_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"}, {50, 3, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMERCLKN_SEL_OUT3", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, {50, 4, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, {149, 0, "DEV_MCU_UART0_FCLK_CLK", "Input clock"}, {149, 3, "DEV_MCU_UART0_VBUSP_CLK", "Input clock"}, {57, 1, "DEV_MMCSD0_EMMCSS_VBUS_CLK", "Input clock"}, {57, 2, "DEV_MMCSD0_EMMCSS_XIN_CLK", "Input muxed clock"}, {57, 3, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"}, {57, 4, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"}, {58, 0, "DEV_MMCSD1_EMMCSDSS_IO_CLK_I", "Input muxed clock"}, {58, 1, "DEV_MMCSD1_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC1_CLKLB_OUT", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_IO_CLK_I"}, {58, 2, "DEV_MMCSD1_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC1_CLK_OUT", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_IO_CLK_I"}, {58, 3, "DEV_MMCSD1_EMMCSDSS_IO_CLK_O", "Output clock"}, {58, 5, "DEV_MMCSD1_EMMCSDSS_VBUS_CLK", "Input clock"}, {58, 6, "DEV_MMCSD1_EMMCSDSS_XIN_CLK", "Input muxed clock"}, {58, 7, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"}, {58, 8, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"}, {184, 0, "DEV_MMCSD2_EMMCSDSS_IO_CLK_I", "Input muxed clock"}, {184, 1, "DEV_MMCSD2_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC2_CLKLB_OUT", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_IO_CLK_I"}, {184, 2, "DEV_MMCSD2_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC2_CLK_OUT", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_IO_CLK_I"}, {184, 3, "DEV_MMCSD2_EMMCSDSS_IO_CLK_O", "Output clock"}, {184, 5, "DEV_MMCSD2_EMMCSDSS_VBUS_CLK", "Input clock"}, {184, 6, "DEV_MMCSD2_EMMCSDSS_XIN_CLK", "Input muxed clock"}, {184, 7, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"}, {184, 8, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"}, {228, 0, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK", "Input muxed clock"}, {228, 1, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 2, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 3, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 4, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 5, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 6, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 7, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV0_16FFT_MAIN_16_HSDIVOUT0_CLK8", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 8, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV0_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 9, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 10, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 11, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_5_HSDIVOUT0_CLK2", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 12, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 13, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_SAM67_GPU_BXS464_WRAP_MAIN_0_GPU_DCC_CLK4", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 14, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV0_16FFT_MAIN_18_HSDIVOUT0_CLK2", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 15, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_SAM62A_A53_CLK", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 16, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_SAM67_DDR_WRAP_MAIN_0_DDR_PLL_DIVH_CLK4_OBSCLK_OUT_CLK", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 17, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 18, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT8", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 19, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 20, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 21, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {234, 0, "DEV_OLDI_TX_CORE0_OLDI_0_FWD_P_CLK", "Input clock"}, {234, 5, "DEV_OLDI_TX_CORE0_OLDI_PLL_CLK", "Input clock"}, {235, 0, "DEV_OLDI_TX_CORE1_OLDI_0_FWD_P_CLK", "Input muxed clock"}, {235, 1, "DEV_OLDI_TX_CORE1_OLDI_0_FWD_P_CLK_PARENT_HSDIV0_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_OLDI_TX_CORE1_OLDI_0_FWD_P_CLK"}, {235, 2, "DEV_OLDI_TX_CORE1_OLDI_0_FWD_P_CLK_PARENT_MAIN_DSS1_DPI0_PCLK_OUT0", "Parent input clock option to DEV_OLDI_TX_CORE1_OLDI_0_FWD_P_CLK"}, {235, 7, "DEV_OLDI_TX_CORE1_OLDI_PLL_CLK", "Input muxed clock"}, {235, 8, "DEV_OLDI_TX_CORE1_OLDI_PLL_CLK_PARENT_HSDIV0_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_OLDI_TX_CORE1_OLDI_PLL_CLK"}, {235, 9, "DEV_OLDI_TX_CORE1_OLDI_PLL_CLK_PARENT_HSDIV0_16FFT_MAIN_18_HSDIVOUT0_CLK", "Parent input clock option to DEV_OLDI_TX_CORE1_OLDI_PLL_CLK"}, {163, 7, "DEV_PBIST0_CLK8_CLK", "Input clock"}, {163, 9, "DEV_PBIST0_TCLK_CLK", "Input clock"}, {233, 7, "DEV_PBIST1_CLK8_CLK", "Input clock"}, {233, 9, "DEV_PBIST1_TCLK_CLK", "Input clock"}, {220, 2, "DEV_PBIST3_CLK8_CLK", "Input clock"}, {220, 4, "DEV_PBIST3_TCLK_CLK", "Input clock"}, {169, 0, "DEV_PSC0_CLK", "Input clock"}, {169, 1, "DEV_PSC0_SLOW_CLK", "Input clock"}, {168, 0, "DEV_PSC0_FW_0_CLK", "Input clock"}, {125, 0, "DEV_RTI0_RTI_CLK", "Input muxed clock"}, {125, 1, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {125, 2, "DEV_RTI0_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {125, 3, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {125, 4, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {125, 5, "DEV_RTI0_VBUSP_CLK", "Input clock"}, {126, 0, "DEV_RTI1_RTI_CLK", "Input muxed clock"}, {126, 1, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {126, 2, "DEV_RTI1_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {126, 3, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {126, 4, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {126, 5, "DEV_RTI1_VBUSP_CLK", "Input clock"}, {130, 0, "DEV_RTI15_RTI_CLK", "Input muxed clock"}, {130, 1, "DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI15_RTI_CLK"}, {130, 2, "DEV_RTI15_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_RTI15_RTI_CLK"}, {130, 3, "DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI15_RTI_CLK"}, {130, 4, "DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_RTI15_RTI_CLK"}, {130, 5, "DEV_RTI15_VBUSP_CLK", "Input clock"}, {127, 0, "DEV_RTI2_RTI_CLK", "Input muxed clock"}, {127, 1, "DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI2_RTI_CLK"}, {127, 2, "DEV_RTI2_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_RTI2_RTI_CLK"}, {127, 3, "DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI2_RTI_CLK"}, {127, 4, "DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_RTI2_RTI_CLK"}, {127, 5, "DEV_RTI2_VBUSP_CLK", "Input clock"}, {128, 0, "DEV_RTI3_RTI_CLK", "Input muxed clock"}, {128, 1, "DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI3_RTI_CLK"}, {128, 2, "DEV_RTI3_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_RTI3_RTI_CLK"}, {128, 3, "DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI3_RTI_CLK"}, {128, 4, "DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_RTI3_RTI_CLK"}, {128, 5, "DEV_RTI3_VBUSP_CLK", "Input clock"}, {150, 0, "DEV_SPINLOCK0_VCLK_CLK", "Input clock"}, {15, 0, "DEV_STM0_ATB_CLK", "Input clock"}, {15, 1, "DEV_STM0_CORE_CLK", "Input clock"}, {15, 2, "DEV_STM0_VBUSP_CLK", "Input clock"}, {36, 0, "DEV_TIMER0_TIMER_HCLK_CLK", "Input clock"}, {36, 1, "DEV_TIMER0_TIMER_PWM", "Output clock"}, {36, 2, "DEV_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"}, {36, 3, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 4, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 5, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 6, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 7, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 8, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 10, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 11, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 12, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 13, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 14, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {37, 0, "DEV_TIMER1_TIMER_HCLK_CLK", "Input clock"}, {37, 1, "DEV_TIMER1_TIMER_PWM", "Output clock"}, {37, 2, "DEV_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"}, {37, 3, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT1", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {37, 4, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {38, 0, "DEV_TIMER2_TIMER_HCLK_CLK", "Input clock"}, {38, 1, "DEV_TIMER2_TIMER_PWM", "Output clock"}, {38, 2, "DEV_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"}, {38, 3, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 4, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 5, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 6, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 7, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 8, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 10, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 11, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 12, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 13, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 14, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {39, 0, "DEV_TIMER3_TIMER_HCLK_CLK", "Input clock"}, {39, 1, "DEV_TIMER3_TIMER_PWM", "Output clock"}, {39, 2, "DEV_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"}, {39, 3, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT3", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {39, 4, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {40, 0, "DEV_TIMER4_TIMER_HCLK_CLK", "Input clock"}, {40, 1, "DEV_TIMER4_TIMER_PWM", "Output clock"}, {40, 2, "DEV_TIMER4_TIMER_TCLK_CLK", "Input muxed clock"}, {40, 3, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 4, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 5, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 6, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 7, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 8, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 10, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 11, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 12, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 13, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 14, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {41, 0, "DEV_TIMER5_TIMER_HCLK_CLK", "Input clock"}, {41, 1, "DEV_TIMER5_TIMER_PWM", "Output clock"}, {41, 2, "DEV_TIMER5_TIMER_TCLK_CLK", "Input muxed clock"}, {41, 3, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT5", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {41, 4, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {42, 0, "DEV_TIMER6_TIMER_HCLK_CLK", "Input clock"}, {42, 1, "DEV_TIMER6_TIMER_PWM", "Output clock"}, {42, 2, "DEV_TIMER6_TIMER_TCLK_CLK", "Input muxed clock"}, {42, 3, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 4, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 5, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 6, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 7, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 8, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 10, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 11, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 12, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 13, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 14, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {43, 0, "DEV_TIMER7_TIMER_HCLK_CLK", "Input clock"}, {43, 1, "DEV_TIMER7_TIMER_PWM", "Output clock"}, {43, 2, "DEV_TIMER7_TIMER_TCLK_CLK", "Input muxed clock"}, {43, 3, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT7", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {43, 4, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {6, 0, "DEV_TIMESYNC_EVENT_INTROUTER0_INTR_CLK", "Input clock"}, {146, 0, "DEV_UART0_FCLK_CLK", "Input muxed clock"}, {146, 1, "DEV_UART0_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT0", "Parent input clock option to DEV_UART0_FCLK_CLK"}, {146, 2, "DEV_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART0_FCLK_CLK"}, {146, 5, "DEV_UART0_VBUSP_CLK", "Input clock"}, {152, 0, "DEV_UART1_FCLK_CLK", "Input muxed clock"}, {152, 1, "DEV_UART1_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT1", "Parent input clock option to DEV_UART1_FCLK_CLK"}, {152, 2, "DEV_UART1_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART1_FCLK_CLK"}, {152, 5, "DEV_UART1_VBUSP_CLK", "Input clock"}, {153, 0, "DEV_UART2_FCLK_CLK", "Input muxed clock"}, {153, 1, "DEV_UART2_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT2", "Parent input clock option to DEV_UART2_FCLK_CLK"}, {153, 2, "DEV_UART2_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART2_FCLK_CLK"}, {153, 5, "DEV_UART2_VBUSP_CLK", "Input clock"}, {154, 0, "DEV_UART3_FCLK_CLK", "Input muxed clock"}, {154, 1, "DEV_UART3_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT3", "Parent input clock option to DEV_UART3_FCLK_CLK"}, {154, 2, "DEV_UART3_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART3_FCLK_CLK"}, {154, 5, "DEV_UART3_VBUSP_CLK", "Input clock"}, {155, 0, "DEV_UART4_FCLK_CLK", "Input muxed clock"}, {155, 1, "DEV_UART4_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT4", "Parent input clock option to DEV_UART4_FCLK_CLK"}, {155, 2, "DEV_UART4_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART4_FCLK_CLK"}, {155, 5, "DEV_UART4_VBUSP_CLK", "Input clock"}, {156, 0, "DEV_UART5_FCLK_CLK", "Input muxed clock"}, {156, 1, "DEV_UART5_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT5", "Parent input clock option to DEV_UART5_FCLK_CLK"}, {156, 2, "DEV_UART5_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART5_FCLK_CLK"}, {156, 5, "DEV_UART5_VBUSP_CLK", "Input clock"}, {158, 0, "DEV_UART6_FCLK_CLK", "Input muxed clock"}, {158, 1, "DEV_UART6_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT6", "Parent input clock option to DEV_UART6_FCLK_CLK"}, {158, 2, "DEV_UART6_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART6_FCLK_CLK"}, {158, 5, "DEV_UART6_VBUSP_CLK", "Input clock"}, {161, 0, "DEV_USB0_BUS_CLK", "Input clock"}, {161, 1, "DEV_USB0_CFG_CLK", "Input clock"}, {161, 2, "DEV_USB0_USB2_APB_PCLK_CLK", "Input clock"}, {161, 3, "DEV_USB0_USB2_REFCLOCK_CLK", "Input muxed clock"}, {161, 4, "DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK"}, {161, 5, "DEV_USB0_USB2_REFCLOCK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK"}, {161, 10, "DEV_USB0_USB2_TAP_TCK", "Input clock"}, {162, 0, "DEV_USB1_BUS_CLK", "Input clock"}, {162, 1, "DEV_USB1_CFG_CLK", "Input clock"}, {162, 2, "DEV_USB1_USB2_APB_PCLK_CLK", "Input clock"}, {162, 3, "DEV_USB1_USB2_REFCLOCK_CLK", "Input muxed clock"}, {162, 4, "DEV_USB1_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_USB1_USB2_REFCLOCK_CLK"}, {162, 5, "DEV_USB1_USB2_REFCLOCK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_USB1_USB2_REFCLOCK_CLK"}, {162, 10, "DEV_USB1_USB2_TAP_TCK", "Input clock"}, {226, 0, "DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK", "Input muxed clock"}, {226, 1, "DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_LFOSC0_CLKOUT", "Parent input clock option to DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK"}, {226, 2, "DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK"}, {226, 3, "DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK"}, {226, 4, "DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT9_CLK", "Parent input clock option to DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK"}, {226, 5, "DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK"}, {226, 6, "DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK"}, {226, 7, "DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK"}, {176, 0, "DEV_WKUP_DEEPSLEEP_SOURCES0_CLK_12M_RC_CLK", "Input clock"}, {64, 0, "DEV_WKUP_ESM0_CLK", "Input clock"}, {61, 0, "DEV_WKUP_GTC0_GTC_CLK", "Input muxed clock"}, {61, 1, "DEV_WKUP_GTC0_GTC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK", "Parent input clock option to DEV_WKUP_GTC0_GTC_CLK"}, {61, 2, "DEV_WKUP_GTC0_GTC_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_WKUP_GTC0_GTC_CLK"}, {61, 3, "DEV_WKUP_GTC0_GTC_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_WKUP_GTC0_GTC_CLK"}, {61, 5, "DEV_WKUP_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_WKUP_GTC0_GTC_CLK"}, {61, 6, "DEV_WKUP_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_WKUP_GTC0_GTC_CLK"}, {61, 7, "DEV_WKUP_GTC0_GTC_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_WKUP_GTC0_GTC_CLK"}, {61, 8, "DEV_WKUP_GTC0_GTC_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_WKUP_GTC0_GTC_CLK"}, {61, 9, "DEV_WKUP_GTC0_VBUSP_CLK", "Input muxed clock"}, {61, 10, "DEV_WKUP_GTC0_VBUSP_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_GTC0_VBUSP_CLK"}, {61, 11, "DEV_WKUP_GTC0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_GTC0_VBUSP_CLK"}, {107, 0, "DEV_WKUP_I2C0_CLK", "Input muxed clock"}, {107, 1, "DEV_WKUP_I2C0_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_I2C0_CLK"}, {107, 2, "DEV_WKUP_I2C0_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_I2C0_CLK"}, {107, 3, "DEV_WKUP_I2C0_PISCL", "Input clock"}, {107, 4, "DEV_WKUP_I2C0_PISYS_CLK", "Input clock"}, {107, 5, "DEV_WKUP_I2C0_PORSCL", "Output clock"}, {5, 0, "DEV_WKUP_MCU_GPIOMUX_INTROUTER0_INTR_CLK", "Input clock"}, {165, 7, "DEV_WKUP_PBIST0_CLK8_CLK", "Input clock"}, {140, 0, "DEV_WKUP_PSC0_CLK", "Input clock"}, {140, 1, "DEV_WKUP_PSC0_SLOW_CLK", "Input clock"}, {121, 0, "DEV_WKUP_R5FSS0_CORE0_CPU_CLK", "Input muxed clock"}, {121, 1, "DEV_WKUP_R5FSS0_CORE0_CPU_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_WKUP_R5FSS0_CORE0_CPU_CLK"}, {121, 2, "DEV_WKUP_R5FSS0_CORE0_CPU_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_R5FSS0_CORE0_CPU_CLK"}, {121, 5, "DEV_WKUP_R5FSS0_CORE0_INTERFACE_CLK", "Input clock"}, {117, 0, "DEV_WKUP_RTCSS0_ANA_OSC32K_CLK", "Input muxed clock"}, {117, 1, "DEV_WKUP_RTCSS0_ANA_OSC32K_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_WKUP_RTCSS0_ANA_OSC32K_CLK"}, {117, 2, "DEV_WKUP_RTCSS0_ANA_OSC32K_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_WKUP_RTCSS0_ANA_OSC32K_CLK"}, {117, 4, "DEV_WKUP_RTCSS0_JTAG_WRCK", "Input clock"}, {117, 6, "DEV_WKUP_RTCSS0_VCLK_CLK", "Input muxed clock"}, {117, 7, "DEV_WKUP_RTCSS0_VCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_RTCSS0_VCLK_CLK"}, {117, 8, "DEV_WKUP_RTCSS0_VCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_RTCSS0_VCLK_CLK"}, {132, 0, "DEV_WKUP_RTI0_RTI_CLK", "Input muxed clock"}, {132, 1, "DEV_WKUP_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_WKUP_RTI0_RTI_CLK"}, {132, 2, "DEV_WKUP_RTI0_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_WKUP_RTI0_RTI_CLK"}, {132, 3, "DEV_WKUP_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_WKUP_RTI0_RTI_CLK"}, {132, 4, "DEV_WKUP_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_WKUP_RTI0_RTI_CLK"}, {132, 5, "DEV_WKUP_RTI0_VBUSP_CLK", "Input muxed clock"}, {132, 6, "DEV_WKUP_RTI0_VBUSP_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_RTI0_VBUSP_CLK"}, {132, 7, "DEV_WKUP_RTI0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_RTI0_VBUSP_CLK"}, {110, 0, "DEV_WKUP_TIMER0_TIMER_HCLK_CLK", "Input muxed clock"}, {110, 1, "DEV_WKUP_TIMER0_TIMER_HCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_HCLK_CLK"}, {110, 2, "DEV_WKUP_TIMER0_TIMER_HCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_HCLK_CLK"}, {110, 3, "DEV_WKUP_TIMER0_TIMER_PWM", "Output clock"}, {110, 4, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"}, {110, 5, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK"}, {110, 6, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_WKUP_CLKSEL_OUT04", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK"}, {110, 7, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK"}, {110, 8, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV1_16FFT_MCU_0_HSDIVOUT5_CLK", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK"}, {110, 9, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK"}, {110, 10, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK"}, {110, 11, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK"}, {110, 12, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK"}, {111, 0, "DEV_WKUP_TIMER1_TIMER_HCLK_CLK", "Input muxed clock"}, {111, 1, "DEV_WKUP_TIMER1_TIMER_HCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_TIMER1_TIMER_HCLK_CLK"}, {111, 2, "DEV_WKUP_TIMER1_TIMER_HCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_TIMER1_TIMER_HCLK_CLK"}, {111, 4, "DEV_WKUP_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"}, {111, 5, "DEV_WKUP_TIMER1_TIMER_TCLK_CLK_PARENT_WKUP_TIMERCLKN_SEL_OUT1", "Parent input clock option to DEV_WKUP_TIMER1_TIMER_TCLK_CLK"}, {111, 6, "DEV_WKUP_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_WKUP_0_TIMER_PWM", "Parent input clock option to DEV_WKUP_TIMER1_TIMER_TCLK_CLK"}, {114, 0, "DEV_WKUP_UART0_FCLK_CLK", "Input clock"}, {114, 3, "DEV_WKUP_UART0_VBUSP_CLK", "Input muxed clock"}, {114, 4, "DEV_WKUP_UART0_VBUSP_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_UART0_VBUSP_CLK"}, {114, 5, "DEV_WKUP_UART0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_UART0_VBUSP_CLK"}, {95, 0, "DEV_WKUP_VTM0_FIX_REF2_CLK", "Input clock"}, {95, 1, "DEV_WKUP_VTM0_FIX_REF_CLK", "Input clock"}, {95, 2, "DEV_WKUP_VTM0_VBUSP_CLK", "Input muxed clock"}, {95, 3, "DEV_WKUP_VTM0_VBUSP_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_VTM0_VBUSP_CLK"}, {95, 4, "DEV_WKUP_VTM0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_VTM0_VBUSP_CLK"}, }; k3conf_0.3/soc/am62px/am62px_devices_info.h0000664000175000017500000000347214511032107015447 0ustar /* * AM62PX Devices Info * * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM62PX_DEVICES_INFO_H #define __AM62PX_DEVICES_INFO_H #define AM62PX_MAX_DEVICES 172 extern struct ti_sci_devices_info am62px_devices_info[]; #endif /* __AM62PX_DEVICES_INFO_H */ k3conf_0.3/soc/am62px/am62px_devices_info.c0000664000175000017500000001613114511032107015436 0ustar /* * AM62PX Devices Info * * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_devices_info am62px_devices_info[] = { {2, "AM62PX_DEV_DBGSUSPENDROUTER0"}, {3, "AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0"}, {5, "AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0"}, {6, "AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0"}, {7, "AM62PX_DEV_MCU_R5FSS0"}, {9, "AM62PX_DEV_MCU_R5FSS0_CORE0"}, {13, "AM62PX_DEV_CPSW0"}, {15, "AM62PX_DEV_STM0"}, {16, "AM62PX_DEV_DCC0"}, {17, "AM62PX_DEV_DCC1"}, {18, "AM62PX_DEV_DCC2"}, {19, "AM62PX_DEV_DCC3"}, {20, "AM62PX_DEV_DCC4"}, {21, "AM62PX_DEV_DCC5"}, {22, "AM62PX_DEV_SMS0"}, {23, "AM62PX_DEV_MCU_DCC0"}, {24, "AM62PX_DEV_DEBUGSS_WRAP0"}, {25, "AM62PX_DEV_DMASS0"}, {26, "AM62PX_DEV_DMASS0_BCDMA_0"}, {27, "AM62PX_DEV_DMASS0_CBASS_0"}, {28, "AM62PX_DEV_DMASS0_INTAGGR_0"}, {29, "AM62PX_DEV_DMASS0_IPCSS_0"}, {30, "AM62PX_DEV_DMASS0_PKTDMA_0"}, {33, "AM62PX_DEV_DMASS0_RINGACC_0"}, {35, "AM62PX_DEV_MCU_TIMER0"}, {36, "AM62PX_DEV_TIMER0"}, {37, "AM62PX_DEV_TIMER1"}, {38, "AM62PX_DEV_TIMER2"}, {39, "AM62PX_DEV_TIMER3"}, {40, "AM62PX_DEV_TIMER4"}, {41, "AM62PX_DEV_TIMER5"}, {42, "AM62PX_DEV_TIMER6"}, {43, "AM62PX_DEV_TIMER7"}, {48, "AM62PX_DEV_MCU_TIMER1"}, {49, "AM62PX_DEV_MCU_TIMER2"}, {50, "AM62PX_DEV_MCU_TIMER3"}, {51, "AM62PX_DEV_ECAP0"}, {52, "AM62PX_DEV_ECAP1"}, {53, "AM62PX_DEV_ECAP2"}, {54, "AM62PX_DEV_ELM0"}, {55, "AM62PX_DEV_MAIN_EMIF_DATA_ISO_VD"}, {57, "AM62PX_DEV_MMCSD0"}, {58, "AM62PX_DEV_MMCSD1"}, {59, "AM62PX_DEV_EQEP0"}, {60, "AM62PX_DEV_EQEP1"}, {61, "AM62PX_DEV_WKUP_GTC0"}, {62, "AM62PX_DEV_EQEP2"}, {63, "AM62PX_DEV_ESM0"}, {64, "AM62PX_DEV_WKUP_ESM0"}, {73, "AM62PX_DEV_FSS0"}, {74, "AM62PX_DEV_FSS0_FSAS_0"}, {75, "AM62PX_DEV_FSS0_OSPI_0"}, {76, "AM62PX_DEV_GICSS0"}, {77, "AM62PX_DEV_GPIO0"}, {78, "AM62PX_DEV_GPIO1"}, {79, "AM62PX_DEV_MCU_GPIO0"}, {80, "AM62PX_DEV_GPMC0"}, {83, "AM62PX_DEV_LED0"}, {85, "AM62PX_DEV_DDPA0"}, {86, "AM62PX_DEV_EPWM0"}, {87, "AM62PX_DEV_EPWM1"}, {88, "AM62PX_DEV_EPWM2"}, {95, "AM62PX_DEV_WKUP_VTM0"}, {96, "AM62PX_DEV_MAILBOX0"}, {97, "AM62PX_DEV_MAIN2MCU_VD"}, {98, "AM62PX_DEV_MCAN0"}, {99, "AM62PX_DEV_MCAN1"}, {100, "AM62PX_DEV_MCU_MCRC64_0"}, {102, "AM62PX_DEV_I2C0"}, {103, "AM62PX_DEV_I2C1"}, {104, "AM62PX_DEV_I2C2"}, {105, "AM62PX_DEV_I2C3"}, {106, "AM62PX_DEV_MCU_I2C0"}, {107, "AM62PX_DEV_WKUP_I2C0"}, {110, "AM62PX_DEV_WKUP_TIMER0"}, {111, "AM62PX_DEV_WKUP_TIMER1"}, {114, "AM62PX_DEV_WKUP_UART0"}, {116, "AM62PX_DEV_MCRC64_0"}, {117, "AM62PX_DEV_WKUP_RTCSS0"}, {118, "AM62PX_DEV_WKUP_R5FSS0_SS0"}, {119, "AM62PX_DEV_WKUP_R5FSS0"}, {121, "AM62PX_DEV_WKUP_R5FSS0_CORE0"}, {125, "AM62PX_DEV_RTI0"}, {126, "AM62PX_DEV_RTI1"}, {127, "AM62PX_DEV_RTI2"}, {128, "AM62PX_DEV_RTI3"}, {130, "AM62PX_DEV_RTI15"}, {131, "AM62PX_DEV_MCU_RTI0"}, {132, "AM62PX_DEV_WKUP_RTI0"}, {134, "AM62PX_DEV_COMPUTE_CLUSTER0"}, {135, "AM62PX_DEV_A53SS0_CORE_0"}, {136, "AM62PX_DEV_A53SS0_CORE_1"}, {137, "AM62PX_DEV_A53SS0_CORE_2"}, {138, "AM62PX_DEV_A53SS0_CORE_3"}, {139, "AM62PX_DEV_PSCSS0"}, {140, "AM62PX_DEV_WKUP_PSC0"}, {141, "AM62PX_DEV_MCSPI0"}, {142, "AM62PX_DEV_MCSPI1"}, {143, "AM62PX_DEV_MCSPI2"}, {146, "AM62PX_DEV_UART0"}, {147, "AM62PX_DEV_MCU_MCSPI0"}, {148, "AM62PX_DEV_MCU_MCSPI1"}, {149, "AM62PX_DEV_MCU_UART0"}, {150, "AM62PX_DEV_SPINLOCK0"}, {152, "AM62PX_DEV_UART1"}, {153, "AM62PX_DEV_UART2"}, {154, "AM62PX_DEV_UART3"}, {155, "AM62PX_DEV_UART4"}, {156, "AM62PX_DEV_UART5"}, {157, "AM62PX_DEV_BOARD0"}, {158, "AM62PX_DEV_UART6"}, {161, "AM62PX_DEV_USB0"}, {162, "AM62PX_DEV_USB1"}, {163, "AM62PX_DEV_PBIST0"}, {165, "AM62PX_DEV_WKUP_PBIST0"}, {166, "AM62PX_DEV_A53SS0"}, {167, "AM62PX_DEV_COMPUTE_CLUSTER0_PBIST_0"}, {168, "AM62PX_DEV_PSC0_FW_0"}, {169, "AM62PX_DEV_PSC0"}, {170, "AM62PX_DEV_DDR32SS0"}, {171, "AM62PX_DEV_DEBUGSS0"}, {172, "AM62PX_DEV_A53_RS_BW_LIMITER0"}, {173, "AM62PX_DEV_A53_WS_BW_LIMITER1"}, {174, "AM62PX_DEV_GPU_RS_BW_LIMITER9"}, {175, "AM62PX_DEV_GPU_WS_BW_LIMITER10"}, {176, "AM62PX_DEV_WKUP_DEEPSLEEP_SOURCES0"}, {177, "AM62PX_DEV_MAIN_EMIF_CFG_ISO_VD"}, {178, "AM62PX_DEV_MAIN_USB0_ISO_VD"}, {179, "AM62PX_DEV_MAIN_USB2_ISO_VD"}, {180, "AM62PX_DEV_MCU_MCU_16FF0"}, {182, "AM62PX_DEV_CSI_RX_IF0"}, {183, "AM62PX_DEV_DCC6"}, {184, "AM62PX_DEV_MMCSD2"}, {185, "AM62PX_DEV_DPHY_RX0"}, {186, "AM62PX_DEV_DSS0"}, {188, "AM62PX_DEV_MCU_MCAN0"}, {189, "AM62PX_DEV_MCU_MCAN1"}, {190, "AM62PX_DEV_MCASP0"}, {191, "AM62PX_DEV_MCASP1"}, {192, "AM62PX_DEV_MCASP2"}, {193, "AM62PX_DEV_CLK_32K_RC_SEL_DEV_VD"}, {194, "AM62PX_DEV_CPT2_AGGR1"}, {195, "AM62PX_DEV_CPT2_AGGR0"}, {196, "AM62PX_DEV_MCU_CPT2_AGGR0"}, {197, "AM62PX_DEV_MCU_DCC1"}, {198, "AM62PX_DEV_DMASS1"}, {199, "AM62PX_DEV_DMASS1_BCDMA_0"}, {200, "AM62PX_DEV_DMASS1_INTAGGR_0"}, {202, "AM62PX_DEV_WKUP_PBIST1"}, {203, "AM62PX_DEV_MCU_PBIST0"}, {204, "AM62PX_DEV_CODEC0"}, {220, "AM62PX_DEV_PBIST3"}, {221, "AM62PX_DEV_CODEC_RS_BW_LIMITER2"}, {222, "AM62PX_DEV_CODEC_WS_BW_LIMITER3"}, {225, "AM62PX_DEV_HSM0"}, {226, "AM62PX_DEV_WKUP_CLKOUT_SEL_DEV_VD"}, {227, "AM62PX_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD"}, {228, "AM62PX_DEV_OBSCLK0_MUX_SEL_DEV_VD"}, {229, "AM62PX_DEV_DCC7"}, {230, "AM62PX_DEV_DCC8"}, {231, "AM62PX_DEV_DSS_DSI0"}, {232, "AM62PX_DEV_DSS1"}, {233, "AM62PX_DEV_PBIST1"}, {234, "AM62PX_DEV_OLDI_TX_CORE0"}, {235, "AM62PX_DEV_OLDI_TX_CORE1"}, {237, "AM62PX_DEV_GPU0"}, {238, "AM62PX_DEV_DPHY_TX0"}, {240, "AM62PX_DEV_DSS1_DPI1_PLLSEL_DEV_VD"}, {241, "AM62PX_DEV_DSS1_DPI0_PLLSEL_DEV_VD"}, {242, "AM62PX_DEV_GPU0_CORE_VD"}, {243, "AM62PX_DEV_OLDI0_VD"}, {244, "AM62PX_DEV_OLDI1_VD"}, }; k3conf_0.3/soc/am62px/am62px_host_info.h0000664000175000017500000000443314522734227015016 0ustar /* * AM62PX Host Info * * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM62PX_HOST_INFO_H #define __AM62PX_HOST_INFO_H #define AM62PX_HOST_ID_TIFS 0 #define AM62PX_HOST_ID_A53_0 10 #define AM62PX_HOST_ID_A53_1 11 #define AM62PX_HOST_ID_A53_2 12 #define AM62PX_HOST_ID_A53_3 13 #define AM62PX_HOST_ID_A53_4 14 #define AM62PX_HOST_ID_MCU_0_R5_0 30 #define AM62PX_HOST_ID_GPU_0 31 #define AM62PX_HOST_ID_GPU_1 32 #define AM62PX_HOST_ID_WKUP_0_R5_0 35 #define AM62PX_HOST_ID_WKUP_0_R5_1 36 #define AM62PX_HOST_ID_DM2TIFS 250 #define AM62PX_HOST_ID_TIFS2DM 251 #define AM62PX_HOST_ID_HSM 253 #define AM62PX_HOST_ID_DM 254 #define AM62PX_MAX_HOST_IDS 15 extern struct ti_sci_host_info am62px_host_info[]; #endif /* __AM62PX_HOST_INFO_H */ k3conf_0.3/soc/am62px/am62px_rm_info.c0000664000175000017500000001216414522734227014452 0ustar /* * AM62PX RM Info * * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_rm_info am62px_rm_info[] = { {0x00C0, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x0140, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x0180, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x0682, "RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER"}, {0x0683, "RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG"}, {0x068D, "RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN"}, {0x068E, "RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN"}, {0x068F, "RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN"}, {0x06A0, "RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN"}, {0x06A1, "RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN"}, {0x06A2, "RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN"}, {0x070A, "RESASG_SUBTYPE_IA_VINT"}, {0x070D, "RESASG_SUBTYPE_GLOBAL_EVENT_SEVT"}, {0x070F, "RESASG_SUBTYPE_IA_PKTDMA_TX_CHAN_ERROR_OES"}, {0x0710, "RESASG_SUBTYPE_IA_PKTDMA_TX_FLOW_COMPLETION_OES"}, {0x0711, "RESASG_SUBTYPE_IA_PKTDMA_RX_CHAN_ERROR_OES"}, {0x0712, "RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_COMPLETION_OES"}, {0x0713, "RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_STARVATION_OES"}, {0x0714, "RESASG_SUBTYPE_IA_BCDMA_CHAN_ERROR_OES"}, {0x0715, "RESASG_SUBTYPE_IA_BCDMA_CHAN_DATA_COMPLETION_OES"}, {0x0716, "RESASG_SUBTYPE_IA_BCDMA_CHAN_RING_COMPLETION_OES"}, {0x0717, "RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_ERROR_OES"}, {0x0718, "RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_DATA_COMPLETION_OES"}, {0x0719, "RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_RING_COMPLETION_OES"}, {0x071A, "RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_ERROR_OES"}, {0x071B, "RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_DATA_COMPLETION_OES"}, {0x071C, "RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_RING_COMPLETION_OES"}, {0x0783, "RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG"}, {0x0790, "RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN"}, {0x0791, "RESASG_SUBTYPE_PKTDMA_RING_CPSW_TX_CHAN"}, {0x0792, "RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_0_CHAN"}, {0x0793, "RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_1_CHAN"}, {0x0796, "RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN"}, {0x0797, "RESASG_SUBTYPE_PKTDMA_RING_CPSW_RX_CHAN"}, {0x0798, "RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_0_CHAN"}, {0x0799, "RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_1_CHAN"}, {0x079A, "RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_2_CHAN"}, {0x079B, "RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_3_CHAN"}, {0x07A3, "RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN"}, {0x07A4, "RESASG_SUBTYPE_PKTDMA_CPSW_TX_CHAN"}, {0x07A5, "RESASG_SUBTYPE_PKTDMA_SAUL_TX_0_CHAN"}, {0x07A6, "RESASG_SUBTYPE_PKTDMA_SAUL_TX_1_CHAN"}, {0x07A9, "RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN"}, {0x07AA, "RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN"}, {0x07AB, "RESASG_SUBTYPE_PKTDMA_CPSW_RX_CHAN"}, {0x07AC, "RESASG_SUBTYPE_PKTDMA_FLOW_CPSW_RX_CHAN"}, {0x07AD, "RESASG_SUBTYPE_PKTDMA_SAUL_RX_0_CHAN"}, {0x07AE, "RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_0_CHAN"}, {0x07AF, "RESASG_SUBTYPE_PKTDMA_SAUL_RX_1_CHAN"}, {0x07B0, "RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_1_CHAN"}, {0x07B1, "RESASG_SUBTYPE_PKTDMA_SAUL_RX_2_CHAN"}, {0x07B2, "RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_2_CHAN"}, {0x07B3, "RESASG_SUBTYPE_PKTDMA_SAUL_RX_3_CHAN"}, {0x07B4, "RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_3_CHAN"}, {0x0840, "RESASG_SUBTYPE_RA_ERROR_OES"}, {0x084A, "RESASG_SUBTYPE_RA_VIRTID"}, {0x31C2, "RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER"}, {0x31C3, "RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG"}, {0x31CE, "RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN"}, {0x31E1, "RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN"}, {0x320A, "RESASG_SUBTYPE_IA_VINT"}, {0x320D, "RESASG_SUBTYPE_GLOBAL_EVENT_SEVT"}, {0x321A, "RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_ERROR_OES"}, {0x321B, "RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_DATA_COMPLETION_OES"}, {0x321C, "RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_RING_COMPLETION_OES"}, }; k3conf_0.3/soc/am62px/am62px_clocks_info.h0000664000175000017500000000346314511032107015303 0ustar /* * AM62PX Clocks Info * * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM62PX_CLOCKS_INFO_H #define __AM62PX_CLOCKS_INFO_H #define AM62PX_MAX_CLOCKS 903 extern struct ti_sci_clocks_info am62px_clocks_info[]; #endif /* __AM62PX_CLOCKS_INFO_H */ k3conf_0.3/soc/j721s2/0000775000175000017500000000000014456530612011265 5ustar k3conf_0.3/soc/j721s2/j721s2_clocks_info.h0000664000175000017500000000346414375734376014763 0ustar /* * J721S2 Clocks Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __J721S2_CLOCKS_INFO_H #define __J721S2_CLOCKS_INFO_H #define J721S2_MAX_CLOCKS 2017 extern struct ti_sci_clocks_info j721s2_clocks_info[]; #endif /* __J721S2_CLOCKS_INFO_H */ k3conf_0.3/soc/j721s2/j721s2_devices_info.h0000664000175000017500000000347214375734376015126 0ustar /* * J721S2 Devices Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __J721S2_DEVICES_INFO_H #define __J721S2_DEVICES_INFO_H #define J721S2_MAX_DEVICES 327 extern struct ti_sci_devices_info j721s2_devices_info[]; #endif /* __J721S2_DEVICES_INFO_H */ k3conf_0.3/soc/j721s2/j721s2_clocks_info.c0000664000175000017500000053610414375734376014760 0ustar /* * J721S2 Clocks Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_clocks_info j721s2_clocks_info[] = { {4, 0, "DEV_A72SS0_ARM_CLK_CLK", "Input clock"}, {4, 1, "DEV_A72SS0_MSMC_CLK", "Input clock"}, {4, 2, "DEV_A72SS0_PLL_CTRL_CLK", "Input clock"}, {4, 6, "DEV_A72SS0_A72_DIVH_CLK8_OBSCLK_OUT_CLK", "Output clock"}, {202, 0, "DEV_A72SS0_CORE0_ARM_CLK_CLK", "Input clock"}, {203, 0, "DEV_A72SS0_CORE1_ARM_CLK_CLK", "Input clock"}, {134, 0, "DEV_AGGR_ATB0_DBG_CLK", "Input clock"}, {2, 0, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT", "Output clock"}, {2, 1, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_1", "Output clock"}, {2, 2, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_2", "Output clock"}, {2, 3, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_3", "Output clock"}, {2, 4, "DEV_ATL0_ATL_CLK", "Input muxed clock"}, {2, 5, "DEV_ATL0_ATL_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT1_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"}, {2, 6, "DEV_ATL0_ATL_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"}, {2, 9, "DEV_ATL0_ATL_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"}, {2, 10, "DEV_ATL0_ATL_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_CLK"}, {2, 11, "DEV_ATL0_ATL_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_CLK"}, {2, 13, "DEV_ATL0_VBUS_CLK", "Input clock"}, {2, 14, "DEV_ATL0_ATL_IO_PORT_AWS", "Input muxed clock"}, {2, 15, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"}, {2, 16, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"}, {2, 17, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"}, {2, 18, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"}, {2, 19, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"}, {2, 27, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"}, {2, 28, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"}, {2, 29, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"}, {2, 30, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"}, {2, 31, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"}, {2, 39, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"}, {2, 40, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"}, {2, 47, "DEV_ATL0_ATL_IO_PORT_AWS_1", "Input muxed clock"}, {2, 48, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"}, {2, 49, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"}, {2, 50, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"}, {2, 51, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"}, {2, 52, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"}, {2, 60, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"}, {2, 61, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"}, {2, 62, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"}, {2, 63, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"}, {2, 64, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"}, {2, 72, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"}, {2, 73, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"}, {2, 80, "DEV_ATL0_ATL_IO_PORT_AWS_2", "Input muxed clock"}, {2, 81, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"}, {2, 82, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"}, {2, 83, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"}, {2, 84, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"}, {2, 85, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"}, {2, 93, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"}, {2, 94, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"}, {2, 95, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"}, {2, 96, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"}, {2, 97, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"}, {2, 105, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"}, {2, 106, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"}, {2, 113, "DEV_ATL0_ATL_IO_PORT_AWS_3", "Input muxed clock"}, {2, 114, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"}, {2, 115, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"}, {2, 116, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"}, {2, 117, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"}, {2, 118, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"}, {2, 126, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"}, {2, 127, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"}, {2, 128, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"}, {2, 129, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"}, {2, 130, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"}, {2, 138, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"}, {2, 139, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"}, {2, 146, "DEV_ATL0_ATL_IO_PORT_BWS", "Input muxed clock"}, {2, 147, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"}, {2, 148, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"}, {2, 149, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"}, {2, 150, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"}, {2, 151, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"}, {2, 159, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"}, {2, 160, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"}, {2, 161, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"}, {2, 162, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"}, {2, 163, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"}, {2, 171, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"}, {2, 172, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"}, {2, 179, "DEV_ATL0_ATL_IO_PORT_BWS_1", "Input muxed clock"}, {2, 180, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"}, {2, 181, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"}, {2, 182, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"}, {2, 183, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"}, {2, 184, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"}, {2, 192, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"}, {2, 193, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"}, {2, 194, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"}, {2, 195, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"}, {2, 196, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"}, {2, 204, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"}, {2, 205, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"}, {2, 212, "DEV_ATL0_ATL_IO_PORT_BWS_2", "Input muxed clock"}, {2, 213, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"}, {2, 214, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"}, {2, 215, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"}, {2, 216, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"}, {2, 217, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"}, {2, 225, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"}, {2, 226, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"}, {2, 227, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"}, {2, 228, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"}, {2, 229, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"}, {2, 237, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"}, {2, 238, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"}, {2, 245, "DEV_ATL0_ATL_IO_PORT_BWS_3", "Input muxed clock"}, {2, 246, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"}, {2, 247, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"}, {2, 248, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"}, {2, 249, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"}, {2, 250, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"}, {2, 258, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"}, {2, 259, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"}, {2, 260, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"}, {2, 261, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"}, {2, 262, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"}, {2, 270, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"}, {2, 271, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"}, {157, 1, "DEV_BOARD0_DSI0_TXCLKN_IN", "Input clock"}, {157, 2, "DEV_BOARD0_I2C4_SCL_OUT", "Output clock"}, {157, 4, "DEV_BOARD0_CSI0_TXCLKN_IN", "Input clock"}, {157, 5, "DEV_BOARD0_CSI0_RXCLKP_OUT", "Output clock"}, {157, 6, "DEV_BOARD0_HYP0_TXPMCLK_IN", "Input clock"}, {157, 7, "DEV_BOARD0_MCAN1_RX_OUT", "Output clock"}, {157, 8, "DEV_BOARD0_MCAN17_RX_OUT", "Output clock"}, {157, 9, "DEV_BOARD0_MMC1_CLK_IN", "Input clock"}, {157, 10, "DEV_BOARD0_MCU_OBSCLK0_IN", "Input muxed clock"}, {157, 11, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"}, {157, 12, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"}, {157, 43, "DEV_BOARD0_I2C0_SCL_IN", "Input clock"}, {157, 44, "DEV_BOARD0_SPI7_CLK_OUT", "Output clock"}, {157, 45, "DEV_BOARD0_MCU_CPTS0_RFT_CLK_OUT", "Output clock"}, {157, 46, "DEV_BOARD0_MCASP3_ACLKR_IN", "Input clock"}, {157, 47, "DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT", "Output clock"}, {157, 48, "DEV_BOARD0_MCU_OSPI0_DQS_OUT", "Output clock"}, {157, 49, "DEV_BOARD0_HYP0_TXFLCLK_OUT", "Output clock"}, {157, 50, "DEV_BOARD0_MCU_OSPI0_LBCLKO_OUT", "Output clock"}, {157, 51, "DEV_BOARD0_MCASP3_ACLKX_IN", "Input clock"}, {157, 52, "DEV_BOARD0_HYP0_RXPMCLK_OUT", "Output clock"}, {157, 54, "DEV_BOARD0_MCASP1_ACLKX_IN", "Input clock"}, {157, 55, "DEV_BOARD0_MCU_SPI1_CLK_IN", "Input clock"}, {157, 56, "DEV_BOARD0_MCAN9_RX_OUT", "Output clock"}, {157, 57, "DEV_BOARD0_I2C6_SCL_OUT", "Output clock"}, {157, 58, "DEV_BOARD0_MCU_SPI0_CLK_OUT", "Output clock"}, {157, 59, "DEV_BOARD0_OBSCLK1_IN", "Input clock"}, {157, 60, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 61, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 62, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 63, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 64, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 65, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_5_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 66, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_6_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 67, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_26_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 72, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 73, "DEV_BOARD0_OBSCLK1_IN_PARENT_OBSCLK1_MUX_OUT0", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 74, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_14_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 76, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 77, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 79, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 85, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 86, "DEV_BOARD0_OBSCLK1_IN_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 87, "DEV_BOARD0_OBSCLK1_IN_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 88, "DEV_BOARD0_OBSCLK1_IN_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 89, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 90, "DEV_BOARD0_OBSCLK1_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 91, "DEV_BOARD0_OBSCLK1_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 92, "DEV_BOARD0_MCU_OSPI1_LBCLKO_OUT", "Output clock"}, {157, 93, "DEV_BOARD0_MCASP3_ACLKX_OUT", "Output clock"}, {157, 95, "DEV_BOARD0_MCASP2_AFSR_OUT", "Output clock"}, {157, 96, "DEV_BOARD0_TRC_CLK_IN", "Input clock"}, {157, 100, "DEV_BOARD0_CSI1_RXCLKN_OUT", "Output clock"}, {157, 102, "DEV_BOARD0_MCASP0_ACLKX_OUT", "Output clock"}, {157, 103, "DEV_BOARD0_MCU_OSPI0_CLK_IN", "Input clock"}, {157, 105, "DEV_BOARD0_GPMC0_FCLK_MUX_IN", "Input clock"}, {157, 106, "DEV_BOARD0_MCU_SPI0_CLK_IN", "Input clock"}, {157, 108, "DEV_BOARD0_MCU_RGMII1_RXC_OUT", "Output clock"}, {157, 109, "DEV_BOARD0_MCASP0_AFSR_OUT", "Output clock"}, {157, 110, "DEV_BOARD0_CSI1_RXCLKP_OUT", "Output clock"}, {157, 111, "DEV_BOARD0_MCU_SYSCLKOUT0_IN", "Input clock"}, {157, 112, "DEV_BOARD0_SPI5_CLK_OUT", "Output clock"}, {157, 113, "DEV_BOARD0_MCU_RMII1_REF_CLK_OUT", "Output clock"}, {157, 114, "DEV_BOARD0_SPI0_CLK_OUT", "Output clock"}, {157, 116, "DEV_BOARD0_SPI6_CLK_OUT", "Output clock"}, {157, 117, "DEV_BOARD0_I2C1_SCL_IN", "Input clock"}, {157, 118, "DEV_BOARD0_DSI1_TXCLKP_IN", "Input clock"}, {157, 119, "DEV_BOARD0_MCAN0_RX_OUT", "Output clock"}, {157, 120, "DEV_BOARD0_MCASP0_ACLKR_OUT", "Output clock"}, {157, 121, "DEV_BOARD0_RMII_REF_CLK_OUT", "Output clock"}, {157, 123, "DEV_BOARD0_MCAN14_RX_OUT", "Output clock"}, {157, 125, "DEV_BOARD0_MCU_I2C0_SCL_OUT", "Output clock"}, {157, 126, "DEV_BOARD0_SPI6_CLK_IN", "Input clock"}, {157, 128, "DEV_BOARD0_MCASP3_AFSX_OUT", "Output clock"}, {157, 129, "DEV_BOARD0_MCU_SPI1_CLK_OUT", "Output clock"}, {157, 130, "DEV_BOARD0_SERDES0_REFCLK_P_IN", "Input clock"}, {157, 131, "DEV_BOARD0_SERDES0_REFCLK_P_OUT", "Output clock"}, {157, 132, "DEV_BOARD0_MCASP1_ACLKR_IN", "Input clock"}, {157, 134, "DEV_BOARD0_MCASP1_AFSX_OUT", "Output clock"}, {157, 135, "DEV_BOARD0_SPI1_CLK_OUT", "Output clock"}, {157, 136, "DEV_BOARD0_I2C3_SCL_IN", "Input clock"}, {157, 137, "DEV_BOARD0_MCU_I2C0_SCL_IN", "Input clock"}, {157, 138, "DEV_BOARD0_HYP1_TXPMCLK_IN", "Input clock"}, {157, 139, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN", "Input muxed clock"}, {157, 140, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 141, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 142, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 143, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 144, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 152, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 153, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 154, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 155, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 156, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 164, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 165, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 166, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 167, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 168, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 173, "DEV_BOARD0_MCASP2_ACLKX_OUT", "Output clock"}, {157, 175, "DEV_BOARD0_MMC1_CLKLB_OUT", "Output clock"}, {157, 176, "DEV_BOARD0_WKUP_I2C0_SCL_OUT", "Output clock"}, {157, 177, "DEV_BOARD0_SYSCLKOUT0_IN", "Input clock"}, {157, 178, "DEV_BOARD0_I2C1_SCL_OUT", "Output clock"}, {157, 179, "DEV_BOARD0_MCU_OSPI0_LBCLKO_IN", "Input clock"}, {157, 180, "DEV_BOARD0_SPI3_CLK_IN", "Input clock"}, {157, 181, "DEV_BOARD0_MCAN13_RX_OUT", "Output clock"}, {157, 182, "DEV_BOARD0_WKUP_I2C0_SCL_IN", "Input clock"}, {157, 183, "DEV_BOARD0_DSI1_TXCLKN_IN", "Input clock"}, {157, 184, "DEV_BOARD0_CPTS0_RFT_CLK_OUT", "Output clock"}, {157, 185, "DEV_BOARD0_MCU_I2C1_SCL_OUT", "Output clock"}, {157, 186, "DEV_BOARD0_MCASP0_ACLKR_IN", "Input clock"}, {157, 187, "DEV_BOARD0_MCU_OSPI1_LBCLKO_IN", "Input clock"}, {157, 188, "DEV_BOARD0_MCASP0_AFSX_OUT", "Output clock"}, {157, 190, "DEV_BOARD0_MCU_I3C0_SDA_OUT", "Output clock"}, {157, 191, "DEV_BOARD0_MCASP0_ACLKX_IN", "Input clock"}, {157, 192, "DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT", "Output clock"}, {157, 193, "DEV_BOARD0_MCAN3_RX_OUT", "Output clock"}, {157, 194, "DEV_BOARD0_MMC1_CLKLB_IN", "Input clock"}, {157, 195, "DEV_BOARD0_MCASP2_ACLKR_OUT", "Output clock"}, {157, 198, "DEV_BOARD0_HFOSC1_CLK_OUT", "Output clock"}, {157, 199, "DEV_BOARD0_MCASP1_ACLKR_OUT", "Output clock"}, {157, 200, "DEV_BOARD0_MCAN4_RX_OUT", "Output clock"}, {157, 201, "DEV_BOARD0_MCASP4_ACLKX_OUT", "Output clock"}, {157, 202, "DEV_BOARD0_CSI1_TXCLKP_IN", "Input clock"}, {157, 203, "DEV_BOARD0_MCASP3_AFSR_OUT", "Output clock"}, {157, 204, "DEV_BOARD0_LED_CLK_OUT", "Output clock"}, {157, 206, "DEV_BOARD0_MCAN7_RX_OUT", "Output clock"}, {157, 207, "DEV_BOARD0_MCU_MDIO0_MDC_IN", "Input clock"}, {157, 209, "DEV_BOARD0_MCASP4_ACLKR_IN", "Input clock"}, {157, 210, "DEV_BOARD0_I2C2_SCL_IN", "Input clock"}, {157, 212, "DEV_BOARD0_SPI1_CLK_IN", "Input clock"}, {157, 213, "DEV_BOARD0_HYP1_RXPMCLK_OUT", "Output clock"}, {157, 214, "DEV_BOARD0_MCU_HYPERBUS0_CK_IN", "Input clock"}, {157, 215, "DEV_BOARD0_MCASP2_AFSX_OUT", "Output clock"}, {157, 216, "DEV_BOARD0_MCASP3_ACLKR_OUT", "Output clock"}, {157, 217, "DEV_BOARD0_MCAN15_RX_OUT", "Output clock"}, {157, 218, "DEV_BOARD0_SPI0_CLK_IN", "Input clock"}, {157, 219, "DEV_BOARD0_MCAN12_RX_OUT", "Output clock"}, {157, 220, "DEV_BOARD0_MCASP2_ACLKR_IN", "Input clock"}, {157, 221, "DEV_BOARD0_MCU_CLKOUT0_IN", "Input muxed clock"}, {157, 222, "DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK5", "Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN"}, {157, 223, "DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK10", "Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN"}, {157, 224, "DEV_BOARD0_MCU_OSPI1_DQS_OUT", "Output clock"}, {157, 226, "DEV_BOARD0_CSI0_RXCLKN_OUT", "Output clock"}, {157, 227, "DEV_BOARD0_TCK_OUT", "Output clock"}, {157, 228, "DEV_BOARD0_CSI1_TXCLKN_IN", "Input clock"}, {157, 229, "DEV_BOARD0_MCU_MCAN0_RX_OUT", "Output clock"}, {157, 230, "DEV_BOARD0_MCASP4_AFSR_OUT", "Output clock"}, {157, 231, "DEV_BOARD0_MCU_HYPERBUS0_CKN_IN", "Input clock"}, {157, 232, "DEV_BOARD0_MCASP4_ACLKR_OUT", "Output clock"}, {157, 233, "DEV_BOARD0_MCAN11_RX_OUT", "Output clock"}, {157, 234, "DEV_BOARD0_I2C5_SCL_IN", "Input clock"}, {157, 235, "DEV_BOARD0_MCU_I2C1_SCL_IN", "Input clock"}, {157, 236, "DEV_BOARD0_I2C0_SCL_OUT", "Output clock"}, {157, 237, "DEV_BOARD0_MCAN6_RX_OUT", "Output clock"}, {157, 238, "DEV_BOARD0_MCU_I3C0_SCL_IN", "Input clock"}, {157, 239, "DEV_BOARD0_MMC1_CLK_OUT", "Output clock"}, {157, 240, "DEV_BOARD0_VOUT0_EXTPCLKIN_OUT", "Output clock"}, {157, 241, "DEV_BOARD0_EXT_REFCLK1_OUT", "Output clock"}, {157, 242, "DEV_BOARD0_I2C5_SCL_OUT", "Output clock"}, {157, 243, "DEV_BOARD0_MCAN16_RX_OUT", "Output clock"}, {157, 244, "DEV_BOARD0_MCU_RGMII1_TXC_IN", "Input clock"}, {157, 245, "DEV_BOARD0_MCASP4_ACLKX_IN", "Input clock"}, {157, 246, "DEV_BOARD0_GPMC0_CLKOUT_IN", "Input clock"}, {157, 247, "DEV_BOARD0_GPMC0_CLK_OUT", "Output clock"}, {157, 248, "DEV_BOARD0_I2C6_SCL_IN", "Input clock"}, {157, 249, "DEV_BOARD0_I2C4_SCL_IN", "Input clock"}, {157, 250, "DEV_BOARD0_SERDES0_REFCLK_N_IN", "Input clock"}, {157, 251, "DEV_BOARD0_OBSCLK0_IN", "Input clock"}, {157, 252, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 253, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 254, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 255, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 256, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 257, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_5_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 258, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_6_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 259, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_26_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 264, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 265, "DEV_BOARD0_OBSCLK0_IN_PARENT_OBSCLK1_MUX_OUT0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 266, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_14_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 268, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 269, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 271, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 277, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 278, "DEV_BOARD0_OBSCLK0_IN_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 279, "DEV_BOARD0_OBSCLK0_IN_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 280, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 281, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 282, "DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 283, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 284, "DEV_BOARD0_MCAN2_RX_OUT", "Output clock"}, {157, 285, "DEV_BOARD0_MCASP2_ACLKX_IN", "Input clock"}, {157, 287, "DEV_BOARD0_MCU_EXT_REFCLK0_OUT", "Output clock"}, {157, 288, "DEV_BOARD0_MCASP1_ACLKX_OUT", "Output clock"}, {157, 289, "DEV_BOARD0_SPI2_CLK_OUT", "Output clock"}, {157, 290, "DEV_BOARD0_HYP0_RXFLCLK_IN", "Input clock"}, {157, 291, "DEV_BOARD0_SPI3_CLK_OUT", "Output clock"}, {157, 292, "DEV_BOARD0_MCASP1_AFSR_OUT", "Output clock"}, {157, 293, "DEV_BOARD0_I2C2_SCL_OUT", "Output clock"}, {157, 294, "DEV_BOARD0_MCAN10_RX_OUT", "Output clock"}, {157, 295, "DEV_BOARD0_MCAN5_RX_OUT", "Output clock"}, {157, 296, "DEV_BOARD0_MCU_I3C0_SCL_OUT", "Output clock"}, {157, 297, "DEV_BOARD0_MCU_MCAN1_RX_OUT", "Output clock"}, {157, 299, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN", "Input muxed clock"}, {157, 300, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 301, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 302, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 303, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 304, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 312, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 313, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 314, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 315, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 316, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 324, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 325, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 326, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 327, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 328, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 333, "DEV_BOARD0_HYP1_TXFLCLK_OUT", "Output clock"}, {157, 334, "DEV_BOARD0_SPI5_CLK_IN", "Input clock"}, {157, 335, "DEV_BOARD0_I2C3_SCL_OUT", "Output clock"}, {157, 336, "DEV_BOARD0_MCAN8_RX_OUT", "Output clock"}, {157, 338, "DEV_BOARD0_RGMII1_RXC_OUT", "Output clock"}, {157, 339, "DEV_BOARD0_SERDES0_REFCLK_N_OUT", "Output clock"}, {157, 340, "DEV_BOARD0_CSI0_TXCLKP_IN", "Input clock"}, {157, 341, "DEV_BOARD0_SPI7_CLK_IN", "Input clock"}, {157, 342, "DEV_BOARD0_RGMII1_TXC_IN", "Input clock"}, {157, 343, "DEV_BOARD0_HYP1_RXFLCLK_IN", "Input clock"}, {157, 344, "DEV_BOARD0_MDIO1_MDC_IN", "Input clock"}, {157, 345, "DEV_BOARD0_SPI2_CLK_IN", "Input clock"}, {157, 346, "DEV_BOARD0_DSI0_TXCLKP_IN", "Input clock"}, {157, 347, "DEV_BOARD0_MCASP4_AFSX_OUT", "Output clock"}, {157, 352, "DEV_BOARD0_VOUT0_PCLK_IN", "Input clock"}, {150, 0, "DEV_CMPEVENT_INTRTR0_INTR_CLK", "Input clock"}, {179, 0, "DEV_CODEC0_VPU_PCLK_CLK", "Input clock"}, {179, 1, "DEV_CODEC0_VPU_BCLK_CLK", "Input clock"}, {179, 2, "DEV_CODEC0_VPU_CCLK_CLK", "Input clock"}, {179, 3, "DEV_CODEC0_VPU_ACLK_CLK", "Input clock"}, {8, 0, "DEV_COMPUTE_CLUSTER0_C71SS0_0_C7X_CLK", "Input clock"}, {8, 1, "DEV_COMPUTE_CLUSTER0_C71SS0_0_PLL_CTRL_CLK", "Input clock"}, {8, 3, "DEV_COMPUTE_CLUSTER0_C71SS0_0_C7X_DIVH_CLK4_OBSCLK_OUT_CLK", "Output clock"}, {11, 0, "DEV_COMPUTE_CLUSTER0_C71SS1_0_C7X_CLK", "Input clock"}, {11, 1, "DEV_COMPUTE_CLUSTER0_C71SS1_0_PLL_CTRL_CLK", "Input clock"}, {14, 1, "DEV_COMPUTE_CLUSTER0_CLEC_CLK1_CLK", "Input clock"}, {15, 1, "DEV_COMPUTE_CLUSTER0_CORE_CORE_CLK1_CLK", "Input clock"}, {15, 2, "DEV_COMPUTE_CLUSTER0_CORE_CORE_PSIL_LEAF_CLK", "Input clock"}, {18, 0, "DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_0_CLK1_CLK_CLK", "Input clock"}, {18, 1, "DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_0_CLK2_CLK_CLK", "Input clock"}, {25, 0, "DEV_COMPUTE_CLUSTER0_EN_MSMC_DOMAIN_0_MSMC_CLK1_CLK", "Input clock"}, {26, 0, "DEV_COMPUTE_CLUSTER0_GIC500SS_VCLK_CLK", "Input clock"}, {27, 3, "DEV_COMPUTE_CLUSTER0_PBIST_WRAP_0_DIVP_CLK1_CLK_CLK", "Input clock"}, {27, 4, "DEV_COMPUTE_CLUSTER0_PBIST_WRAP_0_DIVH_CLK2_CLK_CLK", "Input clock"}, {28, 0, "DEV_CPSW1_MDIO_MDCLK_O", "Output clock"}, {28, 1, "DEV_CPSW1_CPTS_GENF0", "Output clock"}, {28, 3, "DEV_CPSW1_CPTS_RFT_CLK", "Input muxed clock"}, {28, 4, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"}, {28, 5, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"}, {28, 6, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"}, {28, 7, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"}, {28, 8, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"}, {28, 9, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"}, {28, 10, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"}, {28, 11, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"}, {28, 12, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN2_TXMCLK", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"}, {28, 13, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN3_TXMCLK", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"}, {28, 18, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"}, {28, 19, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"}, {28, 20, "DEV_CPSW1_GMII1_MR_CLK", "Input clock"}, {28, 21, "DEV_CPSW1_GMII_RFT_CLK", "Input clock"}, {28, 22, "DEV_CPSW1_RGMII1_RXC_I", "Input clock"}, {28, 26, "DEV_CPSW1_RMII_MHZ_50_CLK", "Input clock"}, {28, 27, "DEV_CPSW1_RGMII1_TXC_O", "Output clock"}, {28, 28, "DEV_CPSW1_CPPI_CLK_CLK", "Input clock"}, {28, 29, "DEV_CPSW1_RGMII_MHZ_5_CLK", "Input clock"}, {28, 30, "DEV_CPSW1_GMII1_MT_CLK", "Input clock"}, {28, 32, "DEV_CPSW1_RGMII_MHZ_50_CLK", "Input clock"}, {28, 33, "DEV_CPSW1_RGMII_MHZ_250_CLK", "Input clock"}, {36, 0, "DEV_CPT2_AGGR0_VCLK_CLK", "Input clock"}, {30, 0, "DEV_CPT2_AGGR1_VCLK_CLK", "Input clock"}, {32, 0, "DEV_CPT2_AGGR2_VCLK_CLK", "Input clock"}, {34, 0, "DEV_CPT2_AGGR3_VCLK_CLK", "Input clock"}, {33, 0, "DEV_CPT2_AGGR4_VCLK_CLK", "Input clock"}, {31, 0, "DEV_CPT2_AGGR5_VCLK_CLK", "Input clock"}, {136, 0, "DEV_CSI_PSILSS0_MAIN_CLK", "Input clock"}, {38, 0, "DEV_CSI_RX_IF0_PPI_D_RX_ULPS_ESC", "Input clock"}, {38, 1, "DEV_CSI_RX_IF0_VBUS_CLK_CLK", "Input clock"}, {38, 2, "DEV_CSI_RX_IF0_PPI_RX_BYTE_CLK", "Input clock"}, {38, 3, "DEV_CSI_RX_IF0_MAIN_CLK_CLK", "Input clock"}, {38, 4, "DEV_CSI_RX_IF0_VP_CLK_CLK", "Input clock"}, {39, 0, "DEV_CSI_RX_IF1_PPI_D_RX_ULPS_ESC", "Input clock"}, {39, 1, "DEV_CSI_RX_IF1_VBUS_CLK_CLK", "Input clock"}, {39, 2, "DEV_CSI_RX_IF1_PPI_RX_BYTE_CLK", "Input clock"}, {39, 3, "DEV_CSI_RX_IF1_MAIN_CLK_CLK", "Input clock"}, {39, 4, "DEV_CSI_RX_IF1_VP_CLK_CLK", "Input clock"}, {40, 1, "DEV_CSI_TX_IF_V2_0_VBUS_CLK_CLK", "Input clock"}, {40, 2, "DEV_CSI_TX_IF_V2_0_MAIN_CLK_CLK", "Input clock"}, {40, 3, "DEV_CSI_TX_IF_V2_0_DPHY_TXBYTECLKHS_CL_CLK", "Input clock"}, {40, 5, "DEV_CSI_TX_IF_V2_0_ESC_CLK_CLK", "Input clock"}, {41, 1, "DEV_CSI_TX_IF_V2_1_VBUS_CLK_CLK", "Input clock"}, {41, 2, "DEV_CSI_TX_IF_V2_1_MAIN_CLK_CLK", "Input clock"}, {41, 3, "DEV_CSI_TX_IF_V2_1_DPHY_TXBYTECLKHS_CL_CLK", "Input clock"}, {41, 5, "DEV_CSI_TX_IF_V2_1_ESC_CLK_CLK", "Input clock"}, {43, 0, "DEV_DCC0_DCC_CLKSRC0_CLK", "Input clock"}, {43, 1, "DEV_DCC0_DCC_CLKSRC1_CLK", "Input clock"}, {43, 2, "DEV_DCC0_DCC_CLKSRC2_CLK", "Input clock"}, {43, 3, "DEV_DCC0_DCC_CLKSRC3_CLK", "Input clock"}, {43, 4, "DEV_DCC0_DCC_CLKSRC4_CLK", "Input clock"}, {43, 5, "DEV_DCC0_DCC_CLKSRC5_CLK", "Input clock"}, {43, 6, "DEV_DCC0_DCC_CLKSRC6_CLK", "Input clock"}, {43, 7, "DEV_DCC0_DCC_CLKSRC7_CLK", "Input clock"}, {43, 8, "DEV_DCC0_DCC_INPUT00_CLK", "Input clock"}, {43, 9, "DEV_DCC0_DCC_INPUT01_CLK", "Input clock"}, {43, 10, "DEV_DCC0_DCC_INPUT02_CLK", "Input clock"}, {43, 11, "DEV_DCC0_DCC_INPUT10_CLK", "Input clock"}, {43, 12, "DEV_DCC0_VBUS_CLK", "Input clock"}, {44, 0, "DEV_DCC1_DCC_CLKSRC0_CLK", "Input clock"}, {44, 1, "DEV_DCC1_DCC_CLKSRC1_CLK", "Input clock"}, {44, 2, "DEV_DCC1_DCC_CLKSRC2_CLK", "Input clock"}, {44, 3, "DEV_DCC1_DCC_CLKSRC3_CLK", "Input clock"}, {44, 4, "DEV_DCC1_DCC_CLKSRC4_CLK", "Input clock"}, {44, 5, "DEV_DCC1_DCC_CLKSRC5_CLK", "Input clock"}, {44, 6, "DEV_DCC1_DCC_CLKSRC6_CLK", "Input clock"}, {44, 7, "DEV_DCC1_DCC_CLKSRC7_CLK", "Input clock"}, {44, 8, "DEV_DCC1_DCC_INPUT00_CLK", "Input clock"}, {44, 9, "DEV_DCC1_DCC_INPUT01_CLK", "Input clock"}, {44, 10, "DEV_DCC1_DCC_INPUT02_CLK", "Input clock"}, {44, 11, "DEV_DCC1_DCC_INPUT10_CLK", "Input clock"}, {44, 12, "DEV_DCC1_VBUS_CLK", "Input clock"}, {45, 0, "DEV_DCC2_DCC_CLKSRC0_CLK", "Input clock"}, {45, 1, "DEV_DCC2_DCC_CLKSRC1_CLK", "Input clock"}, {45, 3, "DEV_DCC2_DCC_CLKSRC3_CLK", "Input clock"}, {45, 4, "DEV_DCC2_DCC_CLKSRC4_CLK", "Input clock"}, {45, 5, "DEV_DCC2_DCC_CLKSRC5_CLK", "Input clock"}, {45, 6, "DEV_DCC2_DCC_CLKSRC6_CLK", "Input clock"}, {45, 7, "DEV_DCC2_DCC_CLKSRC7_CLK", "Input clock"}, {45, 8, "DEV_DCC2_DCC_INPUT00_CLK", "Input clock"}, {45, 9, "DEV_DCC2_DCC_INPUT01_CLK", "Input clock"}, {45, 10, "DEV_DCC2_DCC_INPUT02_CLK", "Input clock"}, {45, 11, "DEV_DCC2_DCC_INPUT10_CLK", "Input clock"}, {45, 12, "DEV_DCC2_VBUS_CLK", "Input clock"}, {46, 0, "DEV_DCC3_DCC_CLKSRC0_CLK", "Input clock"}, {46, 1, "DEV_DCC3_DCC_CLKSRC1_CLK", "Input clock"}, {46, 2, "DEV_DCC3_DCC_CLKSRC2_CLK", "Input clock"}, {46, 5, "DEV_DCC3_DCC_CLKSRC5_CLK", "Input clock"}, {46, 6, "DEV_DCC3_DCC_CLKSRC6_CLK", "Input clock"}, {46, 7, "DEV_DCC3_DCC_CLKSRC7_CLK", "Input clock"}, {46, 8, "DEV_DCC3_DCC_INPUT00_CLK", "Input clock"}, {46, 9, "DEV_DCC3_DCC_INPUT01_CLK", "Input clock"}, {46, 10, "DEV_DCC3_DCC_INPUT02_CLK", "Input clock"}, {46, 11, "DEV_DCC3_DCC_INPUT10_CLK", "Input clock"}, {46, 12, "DEV_DCC3_VBUS_CLK", "Input clock"}, {47, 0, "DEV_DCC4_DCC_CLKSRC0_CLK", "Input clock"}, {47, 2, "DEV_DCC4_DCC_CLKSRC2_CLK", "Input clock"}, {47, 3, "DEV_DCC4_DCC_CLKSRC3_CLK", "Input clock"}, {47, 4, "DEV_DCC4_DCC_CLKSRC4_CLK", "Input clock"}, {47, 5, "DEV_DCC4_DCC_CLKSRC5_CLK", "Input clock"}, {47, 7, "DEV_DCC4_DCC_CLKSRC7_CLK", "Input clock"}, {47, 8, "DEV_DCC4_DCC_INPUT00_CLK", "Input clock"}, {47, 9, "DEV_DCC4_DCC_INPUT01_CLK", "Input clock"}, {47, 10, "DEV_DCC4_DCC_INPUT02_CLK", "Input clock"}, {47, 11, "DEV_DCC4_DCC_INPUT10_CLK", "Input clock"}, {47, 12, "DEV_DCC4_VBUS_CLK", "Input clock"}, {48, 1, "DEV_DCC5_DCC_CLKSRC1_CLK", "Input clock"}, {48, 2, "DEV_DCC5_DCC_CLKSRC2_CLK", "Input clock"}, {48, 3, "DEV_DCC5_DCC_CLKSRC3_CLK", "Input clock"}, {48, 4, "DEV_DCC5_DCC_CLKSRC4_CLK", "Input clock"}, {48, 6, "DEV_DCC5_DCC_CLKSRC6_CLK", "Input clock"}, {48, 7, "DEV_DCC5_DCC_CLKSRC7_CLK", "Input clock"}, {48, 8, "DEV_DCC5_DCC_INPUT00_CLK", "Input clock"}, {48, 9, "DEV_DCC5_DCC_INPUT01_CLK", "Input clock"}, {48, 10, "DEV_DCC5_DCC_INPUT02_CLK", "Input clock"}, {48, 11, "DEV_DCC5_DCC_INPUT10_CLK", "Input clock"}, {48, 12, "DEV_DCC5_VBUS_CLK", "Input clock"}, {49, 0, "DEV_DCC6_DCC_CLKSRC0_CLK", "Input clock"}, {49, 1, "DEV_DCC6_DCC_CLKSRC1_CLK", "Input clock"}, {49, 2, "DEV_DCC6_DCC_CLKSRC2_CLK", "Input clock"}, {49, 3, "DEV_DCC6_DCC_CLKSRC3_CLK", "Input clock"}, {49, 4, "DEV_DCC6_DCC_CLKSRC4_CLK", "Input clock"}, {49, 5, "DEV_DCC6_DCC_CLKSRC5_CLK", "Input clock"}, {49, 6, "DEV_DCC6_DCC_CLKSRC6_CLK", "Input clock"}, {49, 7, "DEV_DCC6_DCC_CLKSRC7_CLK", "Input clock"}, {49, 8, "DEV_DCC6_DCC_INPUT00_CLK", "Input clock"}, {49, 9, "DEV_DCC6_DCC_INPUT01_CLK", "Input clock"}, {49, 10, "DEV_DCC6_DCC_INPUT02_CLK", "Input clock"}, {49, 11, "DEV_DCC6_DCC_INPUT10_CLK", "Input clock"}, {49, 12, "DEV_DCC6_VBUS_CLK", "Input clock"}, {50, 0, "DEV_DCC7_DCC_CLKSRC0_CLK", "Input clock"}, {50, 1, "DEV_DCC7_DCC_CLKSRC1_CLK", "Input clock"}, {50, 2, "DEV_DCC7_DCC_CLKSRC2_CLK", "Input clock"}, {50, 5, "DEV_DCC7_DCC_CLKSRC5_CLK", "Input clock"}, {50, 6, "DEV_DCC7_DCC_CLKSRC6_CLK", "Input clock"}, {50, 7, "DEV_DCC7_DCC_CLKSRC7_CLK", "Input clock"}, {50, 8, "DEV_DCC7_DCC_INPUT00_CLK", "Input clock"}, {50, 9, "DEV_DCC7_DCC_INPUT01_CLK", "Input clock"}, {50, 10, "DEV_DCC7_DCC_INPUT02_CLK", "Input clock"}, {50, 11, "DEV_DCC7_DCC_INPUT10_CLK", "Input clock"}, {50, 12, "DEV_DCC7_VBUS_CLK", "Input clock"}, {51, 0, "DEV_DCC8_DCC_CLKSRC0_CLK", "Input clock"}, {51, 1, "DEV_DCC8_DCC_CLKSRC1_CLK", "Input clock"}, {51, 2, "DEV_DCC8_DCC_CLKSRC2_CLK", "Input clock"}, {51, 3, "DEV_DCC8_DCC_CLKSRC3_CLK", "Input clock"}, {51, 4, "DEV_DCC8_DCC_CLKSRC4_CLK", "Input clock"}, {51, 6, "DEV_DCC8_DCC_CLKSRC6_CLK", "Input clock"}, {51, 7, "DEV_DCC8_DCC_CLKSRC7_CLK", "Input clock"}, {51, 8, "DEV_DCC8_DCC_INPUT00_CLK", "Input clock"}, {51, 9, "DEV_DCC8_DCC_INPUT01_CLK", "Input clock"}, {51, 10, "DEV_DCC8_DCC_INPUT02_CLK", "Input clock"}, {51, 11, "DEV_DCC8_DCC_INPUT10_CLK", "Input clock"}, {51, 12, "DEV_DCC8_VBUS_CLK", "Input clock"}, {52, 0, "DEV_DCC9_DCC_CLKSRC0_CLK", "Input clock"}, {52, 1, "DEV_DCC9_DCC_CLKSRC1_CLK", "Input clock"}, {52, 2, "DEV_DCC9_DCC_CLKSRC2_CLK", "Input clock"}, {52, 3, "DEV_DCC9_DCC_CLKSRC3_CLK", "Input clock"}, {52, 4, "DEV_DCC9_DCC_CLKSRC4_CLK", "Input clock"}, {52, 5, "DEV_DCC9_DCC_CLKSRC5_CLK", "Input clock"}, {52, 6, "DEV_DCC9_DCC_CLKSRC6_CLK", "Input clock"}, {52, 8, "DEV_DCC9_DCC_INPUT00_CLK", "Input clock"}, {52, 9, "DEV_DCC9_DCC_INPUT01_CLK", "Input clock"}, {52, 10, "DEV_DCC9_DCC_INPUT02_CLK", "Input clock"}, {52, 11, "DEV_DCC9_DCC_INPUT10_CLK", "Input clock"}, {52, 12, "DEV_DCC9_VBUS_CLK", "Input clock"}, {138, 0, "DEV_DDR0_DDRSS_DDR_PLL_CLK", "Input clock"}, {138, 1, "DEV_DDR0_DDRSS_VBUS_CLK", "Input clock"}, {138, 2, "DEV_DDR0_PLL_CTRL_CLK", "Input clock"}, {138, 7, "DEV_DDR0_DDRSS_CFG_CLK", "Input clock"}, {139, 0, "DEV_DDR1_DDRSS_DDR_PLL_CLK", "Input clock"}, {139, 1, "DEV_DDR1_DDRSS_VBUS_CLK", "Input clock"}, {139, 2, "DEV_DDR1_PLL_CTRL_CLK", "Input clock"}, {139, 7, "DEV_DDR1_DDRSS_CFG_CLK", "Input clock"}, {57, 1, "DEV_DEBUGSS_WRAP0_ATB_CLK", "Input clock"}, {57, 16, "DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK", "Output clock"}, {57, 17, "DEV_DEBUGSS_WRAP0_CORE_CLK", "Input clock"}, {57, 28, "DEV_DEBUGSS_WRAP0_TREXPT_CLK", "Input clock"}, {57, 41, "DEV_DEBUGSS_WRAP0_JTAG_TCK", "Input clock"}, {137, 0, "DEV_DEBUGSUSPENDRTR0_INTR_CLK", "Input clock"}, {58, 0, "DEV_DMPAC0_CLK", "Input clock"}, {62, 0, "DEV_DMPAC0_SDE_0_CLK", "Input clock"}, {374, 0, "DEV_DMPAC0_UTC_0_PSIL_LEAF_CLK", "Input clock"}, {140, 0, "DEV_DMPAC_VPAC_PSILSS0_MAIN_CLK", "Input clock"}, {152, 0, "DEV_DPHY_RX0_IO_RX_CL_L_M", "Input clock"}, {152, 1, "DEV_DPHY_RX0_PPI_RX_BYTE_CLK", "Output clock"}, {152, 2, "DEV_DPHY_RX0_MAIN_CLK_CLK", "Input clock"}, {152, 3, "DEV_DPHY_RX0_IO_RX_CL_L_P", "Input clock"}, {152, 4, "DEV_DPHY_RX0_JTAG_TCK", "Input clock"}, {152, 8, "DEV_DPHY_RX0_PPI_D_RX_ULPS_ESC", "Output clock"}, {153, 0, "DEV_DPHY_RX1_IO_RX_CL_L_M", "Input clock"}, {153, 1, "DEV_DPHY_RX1_PPI_RX_BYTE_CLK", "Output clock"}, {153, 2, "DEV_DPHY_RX1_MAIN_CLK_CLK", "Input clock"}, {153, 3, "DEV_DPHY_RX1_IO_RX_CL_L_P", "Input clock"}, {153, 4, "DEV_DPHY_RX1_JTAG_TCK", "Input clock"}, {153, 8, "DEV_DPHY_RX1_PPI_D_RX_ULPS_ESC", "Output clock"}, {363, 1, "DEV_DPHY_TX0_IP2_PPI_TXBYTECLKHS_CL_CLK", "Output clock"}, {363, 2, "DEV_DPHY_TX0_IP1_PPI_TXBYTECLKHS_CL_CLK", "Output clock"}, {363, 5, "DEV_DPHY_TX0_CLK", "Input clock"}, {363, 8, "DEV_DPHY_TX0_PSM_CLK", "Input clock"}, {363, 12, "DEV_DPHY_TX0_CK_M", "Output clock"}, {363, 14, "DEV_DPHY_TX0_DPHY_REF_CLK", "Input muxed clock"}, {363, 15, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"}, {363, 16, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"}, {363, 17, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"}, {363, 18, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"}, {363, 19, "DEV_DPHY_TX0_TAP_TCK", "Input clock"}, {363, 20, "DEV_DPHY_TX0_CK_P", "Output clock"}, {363, 22, "DEV_DPHY_TX0_IP1_PPI_M_TXCLKESC_CLK", "Input clock"}, {363, 23, "DEV_DPHY_TX0_IP1_PPI_M_RXCLKESC_CLK", "Output clock"}, {363, 24, "DEV_DPHY_TX0_IP2_PPI_M_TXCLKESC_CLK", "Input clock"}, {364, 1, "DEV_DPHY_TX1_IP2_PPI_TXBYTECLKHS_CL_CLK", "Output clock"}, {364, 2, "DEV_DPHY_TX1_IP1_PPI_TXBYTECLKHS_CL_CLK", "Output clock"}, {364, 5, "DEV_DPHY_TX1_CLK", "Input clock"}, {364, 8, "DEV_DPHY_TX1_PSM_CLK", "Input clock"}, {364, 12, "DEV_DPHY_TX1_CK_M", "Output clock"}, {364, 14, "DEV_DPHY_TX1_DPHY_REF_CLK", "Input muxed clock"}, {364, 15, "DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_DPHY_TX1_DPHY_REF_CLK"}, {364, 16, "DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_DPHY_TX1_DPHY_REF_CLK"}, {364, 17, "DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_DPHY_TX1_DPHY_REF_CLK"}, {364, 18, "DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_DPHY_TX1_DPHY_REF_CLK"}, {364, 19, "DEV_DPHY_TX1_TAP_TCK", "Input clock"}, {364, 20, "DEV_DPHY_TX1_CK_P", "Output clock"}, {364, 22, "DEV_DPHY_TX1_IP1_PPI_M_TXCLKESC_CLK", "Input clock"}, {364, 23, "DEV_DPHY_TX1_IP1_PPI_M_RXCLKESC_CLK", "Output clock"}, {158, 0, "DEV_DSS0_DSS_FUNC_CLK", "Input clock"}, {158, 1, "DEV_DSS0_DSS_INST0_DPI_0_IN_CLK", "Input clock"}, {158, 2, "DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK", "Input muxed clock"}, {158, 3, "DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK"}, {158, 4, "DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_DPI_1_PCLK_SEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK"}, {158, 5, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK", "Input muxed clock"}, {158, 6, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"}, {158, 7, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"}, {158, 8, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0_DUP0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"}, {158, 9, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"}, {158, 10, "DEV_DSS0_DSS_INST0_DPI_2_IN_CLK", "Input muxed clock"}, {158, 11, "DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_CLK"}, {158, 12, "DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_CLK"}, {158, 13, "DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_CLK"}, {158, 14, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK", "Input muxed clock"}, {158, 15, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK"}, {158, 16, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK"}, {158, 17, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK"}, {158, 18, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK", "Input muxed clock"}, {158, 19, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT1_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"}, {158, 20, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"}, {158, 21, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK_DUP0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"}, {158, 22, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"}, {158, 23, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0_DUP0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"}, {158, 24, "DEV_DSS0_DSS_INST0_PARA_1_OUT_CLK", "Output clock"}, {158, 25, "DEV_DSS0_DSS_INST0_PARA_3_OUT_CLK", "Output clock"}, {158, 26, "DEV_DSS0_DSS_INST0_DPI_0_OUT_CLK", "Output clock"}, {158, 27, "DEV_DSS0_DSS_INST0_DPI_1_OUT_CLK", "Output clock"}, {158, 28, "DEV_DSS0_DSS_INST0_DPI_2_OUT_CLK", "Output clock"}, {158, 29, "DEV_DSS0_DSS_INST0_DPI_3_OUT_CLK", "Output clock"}, {158, 30, "DEV_DSS0_DSS_INST0_DPI_0_OUT_2X_CLK", "Output clock"}, {154, 0, "DEV_DSS_DSI0_PLL_CTRL_CLK", "Input clock"}, {154, 1, "DEV_DSS_DSI0_SYS_CLK", "Input clock"}, {154, 2, "DEV_DSS_DSI0_DPHY_0_RX_ESC_CLK", "Input clock"}, {154, 3, "DEV_DSS_DSI0_DPHY_0_TX_ESC_CLK", "Input clock"}, {154, 4, "DEV_DSS_DSI0_DPI_0_CLK", "Input clock"}, {154, 5, "DEV_DSS_DSI0_PPI_0_TXBYTECLKHS_CL_CLK", "Input clock"}, {155, 0, "DEV_DSS_DSI1_PLL_CTRL_CLK", "Input clock"}, {155, 1, "DEV_DSS_DSI1_SYS_CLK", "Input clock"}, {155, 2, "DEV_DSS_DSI1_DPHY_0_RX_ESC_CLK", "Input clock"}, {155, 3, "DEV_DSS_DSI1_DPHY_0_TX_ESC_CLK", "Input clock"}, {155, 4, "DEV_DSS_DSI1_DPI_0_CLK", "Input clock"}, {155, 5, "DEV_DSS_DSI1_PPI_0_TXBYTECLKHS_CL_CLK", "Input clock"}, {156, 0, "DEV_DSS_EDP0_PHY_LN0_RXCLK", "Input clock"}, {156, 1, "DEV_DSS_EDP0_PHY_LN2_TXCLK", "Output clock"}, {156, 2, "DEV_DSS_EDP0_PHY_LN3_RXFCLK", "Input clock"}, {156, 3, "DEV_DSS_EDP0_PHY_LN2_TXMCLK", "Input clock"}, {156, 4, "DEV_DSS_EDP0_PHY_LN3_REFCLK", "Input clock"}, {156, 6, "DEV_DSS_EDP0_DPI_2_2X_CLK", "Input clock"}, {156, 7, "DEV_DSS_EDP0_PHY_LN0_TXCLK", "Output clock"}, {156, 8, "DEV_DSS_EDP0_PHY_LN2_TXFCLK", "Input clock"}, {156, 9, "DEV_DSS_EDP0_DPI_3_CLK", "Input clock"}, {156, 10, "DEV_DSS_EDP0_PHY_LN1_RXCLK", "Input clock"}, {156, 11, "DEV_DSS_EDP0_PHY_LN1_TXCLK", "Output clock"}, {156, 12, "DEV_DSS_EDP0_PHY_LN1_RXFCLK", "Input clock"}, {156, 13, "DEV_DSS_EDP0_DPI_5_CLK", "Input clock"}, {156, 14, "DEV_DSS_EDP0_PHY_LN2_RXCLK", "Input clock"}, {156, 16, "DEV_DSS_EDP0_PHY_LN1_TXMCLK", "Input clock"}, {156, 18, "DEV_DSS_EDP0_DPI_2_CLK", "Input clock"}, {156, 19, "DEV_DSS_EDP0_DPTX_MOD_CLK", "Input clock"}, {156, 20, "DEV_DSS_EDP0_PHY_LN1_REFCLK", "Input clock"}, {156, 21, "DEV_DSS_EDP0_PHY_LN1_TXFCLK", "Input clock"}, {156, 22, "DEV_DSS_EDP0_PHY_LN0_RXFCLK", "Input clock"}, {156, 24, "DEV_DSS_EDP0_PHY_LN3_TXMCLK", "Input clock"}, {156, 25, "DEV_DSS_EDP0_PLL_CTRL_CLK", "Input clock"}, {156, 26, "DEV_DSS_EDP0_PHY_LN0_TXFCLK", "Input clock"}, {156, 27, "DEV_DSS_EDP0_PHY_LN3_TXFCLK", "Input clock"}, {156, 28, "DEV_DSS_EDP0_PHY_LN3_TXCLK", "Output clock"}, {156, 29, "DEV_DSS_EDP0_PHY_LN2_REFCLK", "Input clock"}, {156, 30, "DEV_DSS_EDP0_DPI_4_CLK", "Input clock"}, {156, 31, "DEV_DSS_EDP0_PHY_LN0_TXMCLK", "Input clock"}, {156, 33, "DEV_DSS_EDP0_PHY_LN0_REFCLK", "Input clock"}, {156, 34, "DEV_DSS_EDP0_PHY_LN3_RXCLK", "Input clock"}, {156, 35, "DEV_DSS_EDP0_AIF_I2S_CLK", "Input clock"}, {156, 36, "DEV_DSS_EDP0_PHY_LN2_RXFCLK", "Input clock"}, {92, 0, "DEV_ECAP0_VBUS_CLK", "Input clock"}, {93, 0, "DEV_ECAP1_VBUS_CLK", "Input clock"}, {94, 0, "DEV_ECAP2_VBUS_CLK", "Input clock"}, {95, 0, "DEV_ELM0_VBUSP_CLK", "Input clock"}, {160, 0, "DEV_EPWM0_VBUSP_CLK", "Input clock"}, {161, 0, "DEV_EPWM1_VBUSP_CLK", "Input clock"}, {162, 0, "DEV_EPWM2_VBUSP_CLK", "Input clock"}, {163, 0, "DEV_EPWM3_VBUSP_CLK", "Input clock"}, {164, 0, "DEV_EPWM4_VBUSP_CLK", "Input clock"}, {165, 0, "DEV_EPWM5_VBUSP_CLK", "Input clock"}, {100, 0, "DEV_EQEP0_VBUS_CLK", "Input clock"}, {101, 0, "DEV_EQEP1_VBUS_CLK", "Input clock"}, {102, 0, "DEV_EQEP2_VBUS_CLK", "Input clock"}, {103, 0, "DEV_ESM0_CLK", "Input clock"}, {111, 0, "DEV_GPIO0_MMR_CLK", "Input clock"}, {112, 0, "DEV_GPIO2_MMR_CLK", "Input clock"}, {113, 0, "DEV_GPIO4_MMR_CLK", "Input clock"}, {114, 0, "DEV_GPIO6_MMR_CLK", "Input clock"}, {148, 0, "DEV_GPIOMUX_INTRTR0_INTR_CLK", "Input clock"}, {117, 0, "DEV_GPMC0_VBUSM_CLK", "Input clock"}, {117, 1, "DEV_GPMC0_PO_GPMC_DEV_CLK", "Output clock"}, {117, 2, "DEV_GPMC0_FUNC_CLK", "Input muxed clock"}, {117, 3, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_GPMC0_FUNC_CLK"}, {117, 4, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK6", "Parent input clock option to DEV_GPMC0_FUNC_CLK"}, {117, 5, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK4", "Parent input clock option to DEV_GPMC0_FUNC_CLK"}, {117, 6, "DEV_GPMC0_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_GPMC0_FUNC_CLK"}, {117, 7, "DEV_GPMC0_PI_GPMC_RET_CLK", "Input clock"}, {61, 0, "DEV_GTC0_VBUSP_CLK", "Input clock"}, {61, 1, "DEV_GTC0_GTC_CLK", "Input muxed clock"}, {61, 2, "DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 3, "DEV_GTC0_GTC_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 4, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 5, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 6, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 7, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 8, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 9, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 10, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN2_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 11, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN3_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 16, "DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 17, "DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {214, 0, "DEV_I2C0_PORSCL", "Output clock"}, {214, 1, "DEV_I2C0_PISYS_CLK", "Input clock"}, {214, 2, "DEV_I2C0_CLK", "Input clock"}, {214, 3, "DEV_I2C0_PISCL", "Input clock"}, {215, 0, "DEV_I2C1_PORSCL", "Output clock"}, {215, 1, "DEV_I2C1_PISYS_CLK", "Input clock"}, {215, 2, "DEV_I2C1_CLK", "Input clock"}, {215, 3, "DEV_I2C1_PISCL", "Input clock"}, {216, 0, "DEV_I2C2_PORSCL", "Output clock"}, {216, 1, "DEV_I2C2_PISYS_CLK", "Input clock"}, {216, 2, "DEV_I2C2_CLK", "Input clock"}, {216, 3, "DEV_I2C2_PISCL", "Input clock"}, {217, 0, "DEV_I2C3_PORSCL", "Output clock"}, {217, 1, "DEV_I2C3_PISYS_CLK", "Input clock"}, {217, 2, "DEV_I2C3_CLK", "Input clock"}, {217, 3, "DEV_I2C3_PISCL", "Input clock"}, {218, 0, "DEV_I2C4_PORSCL", "Output clock"}, {218, 1, "DEV_I2C4_PISYS_CLK", "Input clock"}, {218, 2, "DEV_I2C4_CLK", "Input clock"}, {218, 3, "DEV_I2C4_PISCL", "Input clock"}, {219, 0, "DEV_I2C5_PORSCL", "Output clock"}, {219, 1, "DEV_I2C5_PISYS_CLK", "Input clock"}, {219, 2, "DEV_I2C5_CLK", "Input clock"}, {219, 3, "DEV_I2C5_PISCL", "Input clock"}, {220, 0, "DEV_I2C6_PORSCL", "Output clock"}, {220, 1, "DEV_I2C6_PISYS_CLK", "Input clock"}, {220, 2, "DEV_I2C6_CLK", "Input clock"}, {220, 3, "DEV_I2C6_PISCL", "Input clock"}, {130, 0, "DEV_J7AEP_GPU_BXS464_WRAP0_GPU_SS_0_PLL_CTRL_CLK", "Input clock"}, {130, 1, "DEV_J7AEP_GPU_BXS464_WRAP0_GPU_SS_0_GPU_PLL_CLK", "Input clock"}, {131, 0, "DEV_J7AM_32_64_ATB_FUNNEL0_DBG_CLK", "Input clock"}, {132, 0, "DEV_J7AM_32_64_ATB_FUNNEL1_DBG_CLK", "Input clock"}, {133, 0, "DEV_J7AM_32_64_ATB_FUNNEL2_DBG_CLK", "Input clock"}, {135, 0, "DEV_J7AM_BOLT_PGD0_WKUP_OSC0_CLK", "Input clock"}, {141, 0, "DEV_J7AM_HWA_ATB_FUNNEL0_DBG_CLK", "Input clock"}, {142, 0, "DEV_J7AM_MAIN_16FF0_WKUP_OSC0_CLK", "Input clock"}, {144, 0, "DEV_J7AM_PULSAR_ATB_FUNNEL0_DBG_CLK", "Input clock"}, {120, 0, "DEV_LED0_VBUS_CLK", "Input clock"}, {120, 1, "DEV_LED0_LED_CLK", "Input clock"}, {121, 0, "DEV_MAIN2MCU_LVL_INTRTR0_INTR_CLK", "Input clock"}, {122, 0, "DEV_MAIN2MCU_PLS_INTRTR0_INTR_CLK", "Input clock"}, {182, 0, "DEV_MCAN0_MCANSS_HCLK_CLK", "Input clock"}, {182, 1, "DEV_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"}, {182, 2, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, {182, 3, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, {182, 4, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, {182, 5, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, {182, 6, "DEV_MCAN0_MCANSS_CAN_RXD", "Input clock"}, {183, 0, "DEV_MCAN1_MCANSS_HCLK_CLK", "Input clock"}, {183, 1, "DEV_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"}, {183, 2, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, {183, 3, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, {183, 4, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, {183, 5, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, {183, 6, "DEV_MCAN1_MCANSS_CAN_RXD", "Input clock"}, {192, 0, "DEV_MCAN10_MCANSS_HCLK_CLK", "Input clock"}, {192, 1, "DEV_MCAN10_MCANSS_CCLK_CLK", "Input muxed clock"}, {192, 2, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"}, {192, 3, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"}, {192, 4, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"}, {192, 5, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"}, {192, 6, "DEV_MCAN10_MCANSS_CAN_RXD", "Input clock"}, {193, 0, "DEV_MCAN11_MCANSS_HCLK_CLK", "Input clock"}, {193, 1, "DEV_MCAN11_MCANSS_CCLK_CLK", "Input muxed clock"}, {193, 2, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"}, {193, 3, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"}, {193, 4, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"}, {193, 5, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"}, {193, 6, "DEV_MCAN11_MCANSS_CAN_RXD", "Input clock"}, {194, 0, "DEV_MCAN12_MCANSS_HCLK_CLK", "Input clock"}, {194, 1, "DEV_MCAN12_MCANSS_CCLK_CLK", "Input muxed clock"}, {194, 2, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"}, {194, 3, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"}, {194, 4, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"}, {194, 5, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"}, {194, 6, "DEV_MCAN12_MCANSS_CAN_RXD", "Input clock"}, {195, 0, "DEV_MCAN13_MCANSS_HCLK_CLK", "Input clock"}, {195, 1, "DEV_MCAN13_MCANSS_CCLK_CLK", "Input muxed clock"}, {195, 2, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"}, {195, 3, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"}, {195, 4, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"}, {195, 5, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"}, {195, 6, "DEV_MCAN13_MCANSS_CAN_RXD", "Input clock"}, {197, 0, "DEV_MCAN14_MCANSS_HCLK_CLK", "Input clock"}, {197, 1, "DEV_MCAN14_MCANSS_CCLK_CLK", "Input muxed clock"}, {197, 2, "DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK"}, {197, 3, "DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK"}, {197, 4, "DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK"}, {197, 5, "DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK"}, {197, 6, "DEV_MCAN14_MCANSS_CAN_RXD", "Input clock"}, {199, 0, "DEV_MCAN15_MCANSS_HCLK_CLK", "Input clock"}, {199, 1, "DEV_MCAN15_MCANSS_CCLK_CLK", "Input muxed clock"}, {199, 2, "DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK"}, {199, 3, "DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK"}, {199, 4, "DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK"}, {199, 5, "DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK"}, {199, 6, "DEV_MCAN15_MCANSS_CAN_RXD", "Input clock"}, {201, 0, "DEV_MCAN16_MCANSS_HCLK_CLK", "Input clock"}, {201, 1, "DEV_MCAN16_MCANSS_CCLK_CLK", "Input muxed clock"}, {201, 2, "DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK"}, {201, 3, "DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK"}, {201, 4, "DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK"}, {201, 5, "DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK"}, {201, 6, "DEV_MCAN16_MCANSS_CAN_RXD", "Input clock"}, {206, 0, "DEV_MCAN17_MCANSS_HCLK_CLK", "Input clock"}, {206, 1, "DEV_MCAN17_MCANSS_CCLK_CLK", "Input muxed clock"}, {206, 2, "DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK"}, {206, 3, "DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK"}, {206, 4, "DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK"}, {206, 5, "DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK"}, {206, 6, "DEV_MCAN17_MCANSS_CAN_RXD", "Input clock"}, {184, 0, "DEV_MCAN2_MCANSS_HCLK_CLK", "Input clock"}, {184, 1, "DEV_MCAN2_MCANSS_CCLK_CLK", "Input muxed clock"}, {184, 2, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"}, {184, 3, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"}, {184, 4, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"}, {184, 5, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"}, {184, 6, "DEV_MCAN2_MCANSS_CAN_RXD", "Input clock"}, {185, 0, "DEV_MCAN3_MCANSS_HCLK_CLK", "Input clock"}, {185, 1, "DEV_MCAN3_MCANSS_CCLK_CLK", "Input muxed clock"}, {185, 2, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"}, {185, 3, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"}, {185, 4, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"}, {185, 5, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"}, {185, 6, "DEV_MCAN3_MCANSS_CAN_RXD", "Input clock"}, {186, 0, "DEV_MCAN4_MCANSS_HCLK_CLK", "Input clock"}, {186, 1, "DEV_MCAN4_MCANSS_CCLK_CLK", "Input muxed clock"}, {186, 2, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"}, {186, 3, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"}, {186, 4, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"}, {186, 5, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"}, {186, 6, "DEV_MCAN4_MCANSS_CAN_RXD", "Input clock"}, {187, 0, "DEV_MCAN5_MCANSS_HCLK_CLK", "Input clock"}, {187, 1, "DEV_MCAN5_MCANSS_CCLK_CLK", "Input muxed clock"}, {187, 2, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"}, {187, 3, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"}, {187, 4, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"}, {187, 5, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"}, {187, 6, "DEV_MCAN5_MCANSS_CAN_RXD", "Input clock"}, {188, 0, "DEV_MCAN6_MCANSS_HCLK_CLK", "Input clock"}, {188, 1, "DEV_MCAN6_MCANSS_CCLK_CLK", "Input muxed clock"}, {188, 2, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"}, {188, 3, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"}, {188, 4, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"}, {188, 5, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"}, {188, 6, "DEV_MCAN6_MCANSS_CAN_RXD", "Input clock"}, {189, 0, "DEV_MCAN7_MCANSS_HCLK_CLK", "Input clock"}, {189, 1, "DEV_MCAN7_MCANSS_CCLK_CLK", "Input muxed clock"}, {189, 2, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"}, {189, 3, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"}, {189, 4, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"}, {189, 5, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"}, {189, 6, "DEV_MCAN7_MCANSS_CAN_RXD", "Input clock"}, {190, 0, "DEV_MCAN8_MCANSS_HCLK_CLK", "Input clock"}, {190, 1, "DEV_MCAN8_MCANSS_CCLK_CLK", "Input muxed clock"}, {190, 2, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"}, {190, 3, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"}, {190, 4, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"}, {190, 5, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"}, {190, 6, "DEV_MCAN8_MCANSS_CAN_RXD", "Input clock"}, {191, 0, "DEV_MCAN9_MCANSS_HCLK_CLK", "Input clock"}, {191, 1, "DEV_MCAN9_MCANSS_CCLK_CLK", "Input muxed clock"}, {191, 2, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"}, {191, 3, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"}, {191, 4, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"}, {191, 5, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"}, {191, 6, "DEV_MCAN9_MCANSS_CAN_RXD", "Input clock"}, {209, 0, "DEV_MCASP0_AUX_CLK", "Input muxed clock"}, {209, 1, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, {209, 2, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, {209, 5, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, {209, 6, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, {209, 7, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, {209, 8, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, {209, 9, "DEV_MCASP0_MCASP_AFSX_POUT", "Output clock"}, {209, 10, "DEV_MCASP0_MCASP_AHCLKR_POUT", "Output clock"}, {209, 11, "DEV_MCASP0_MCASP_AHCLKR_PIN", "Input muxed clock"}, {209, 12, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {209, 13, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {209, 14, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {209, 15, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {209, 20, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {209, 21, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {209, 22, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {209, 23, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {209, 28, "DEV_MCASP0_MCASP_ACLKX_POUT", "Output clock"}, {209, 29, "DEV_MCASP0_MCASP_AFSR_POUT", "Output clock"}, {209, 30, "DEV_MCASP0_VBUSP_CLK", "Input clock"}, {209, 31, "DEV_MCASP0_MCASP_ACLKR_POUT", "Output clock"}, {209, 32, "DEV_MCASP0_MCASP_AHCLKX_POUT", "Output clock"}, {209, 33, "DEV_MCASP0_MCASP_ACLKX_PIN", "Input clock"}, {209, 34, "DEV_MCASP0_MCASP_AHCLKX_PIN", "Input muxed clock"}, {209, 35, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {209, 36, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {209, 37, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {209, 38, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {209, 43, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {209, 44, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {209, 45, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {209, 46, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {209, 51, "DEV_MCASP0_MCASP_ACLKR_PIN", "Input clock"}, {210, 0, "DEV_MCASP1_AUX_CLK", "Input muxed clock"}, {210, 1, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, {210, 2, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, {210, 5, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, {210, 6, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, {210, 7, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, {210, 8, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, {210, 9, "DEV_MCASP1_MCASP_AFSX_POUT", "Output clock"}, {210, 10, "DEV_MCASP1_MCASP_AHCLKR_POUT", "Output clock"}, {210, 11, "DEV_MCASP1_MCASP_AHCLKR_PIN", "Input muxed clock"}, {210, 12, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {210, 13, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {210, 14, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {210, 15, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {210, 20, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {210, 21, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {210, 22, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {210, 23, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {210, 28, "DEV_MCASP1_MCASP_ACLKX_POUT", "Output clock"}, {210, 29, "DEV_MCASP1_MCASP_AFSR_POUT", "Output clock"}, {210, 30, "DEV_MCASP1_VBUSP_CLK", "Input clock"}, {210, 31, "DEV_MCASP1_MCASP_ACLKR_POUT", "Output clock"}, {210, 32, "DEV_MCASP1_MCASP_AHCLKX_POUT", "Output clock"}, {210, 33, "DEV_MCASP1_MCASP_ACLKX_PIN", "Input clock"}, {210, 34, "DEV_MCASP1_MCASP_AHCLKX_PIN", "Input muxed clock"}, {210, 35, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {210, 36, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {210, 37, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {210, 38, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {210, 43, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {210, 44, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {210, 45, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {210, 46, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {210, 51, "DEV_MCASP1_MCASP_ACLKR_PIN", "Input clock"}, {211, 0, "DEV_MCASP2_AUX_CLK", "Input muxed clock"}, {211, 1, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, {211, 2, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, {211, 5, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, {211, 6, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, {211, 7, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, {211, 8, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, {211, 9, "DEV_MCASP2_MCASP_AFSX_POUT", "Output clock"}, {211, 10, "DEV_MCASP2_MCASP_AHCLKR_POUT", "Output clock"}, {211, 11, "DEV_MCASP2_MCASP_AHCLKR_PIN", "Input muxed clock"}, {211, 12, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {211, 13, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {211, 14, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {211, 15, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {211, 20, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {211, 21, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {211, 22, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {211, 23, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {211, 28, "DEV_MCASP2_MCASP_ACLKX_POUT", "Output clock"}, {211, 29, "DEV_MCASP2_MCASP_AFSR_POUT", "Output clock"}, {211, 30, "DEV_MCASP2_VBUSP_CLK", "Input clock"}, {211, 31, "DEV_MCASP2_MCASP_ACLKR_POUT", "Output clock"}, {211, 32, "DEV_MCASP2_MCASP_AHCLKX_POUT", "Output clock"}, {211, 33, "DEV_MCASP2_MCASP_ACLKX_PIN", "Input clock"}, {211, 34, "DEV_MCASP2_MCASP_AHCLKX_PIN", "Input muxed clock"}, {211, 35, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {211, 36, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {211, 37, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {211, 38, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {211, 43, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {211, 44, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {211, 45, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {211, 46, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {211, 51, "DEV_MCASP2_MCASP_ACLKR_PIN", "Input clock"}, {212, 0, "DEV_MCASP3_AUX_CLK", "Input muxed clock"}, {212, 1, "DEV_MCASP3_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP3_AUX_CLK"}, {212, 2, "DEV_MCASP3_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP3_AUX_CLK"}, {212, 5, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP3_AUX_CLK"}, {212, 6, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP3_AUX_CLK"}, {212, 7, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP3_AUX_CLK"}, {212, 8, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP3_AUX_CLK"}, {212, 9, "DEV_MCASP3_MCASP_AFSX_POUT", "Output clock"}, {212, 10, "DEV_MCASP3_MCASP_AHCLKR_POUT", "Output clock"}, {212, 11, "DEV_MCASP3_MCASP_AHCLKR_PIN", "Input muxed clock"}, {212, 12, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, {212, 13, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, {212, 14, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, {212, 15, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, {212, 20, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, {212, 21, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, {212, 22, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, {212, 23, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, {212, 28, "DEV_MCASP3_MCASP_ACLKX_POUT", "Output clock"}, {212, 29, "DEV_MCASP3_MCASP_AFSR_POUT", "Output clock"}, {212, 30, "DEV_MCASP3_VBUSP_CLK", "Input clock"}, {212, 31, "DEV_MCASP3_MCASP_ACLKR_POUT", "Output clock"}, {212, 32, "DEV_MCASP3_MCASP_AHCLKX_POUT", "Output clock"}, {212, 33, "DEV_MCASP3_MCASP_ACLKX_PIN", "Input clock"}, {212, 34, "DEV_MCASP3_MCASP_AHCLKX_PIN", "Input muxed clock"}, {212, 35, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, {212, 36, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, {212, 37, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, {212, 38, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, {212, 43, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, {212, 44, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, {212, 45, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, {212, 46, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, {212, 51, "DEV_MCASP3_MCASP_ACLKR_PIN", "Input clock"}, {213, 0, "DEV_MCASP4_AUX_CLK", "Input muxed clock"}, {213, 1, "DEV_MCASP4_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP4_AUX_CLK"}, {213, 2, "DEV_MCASP4_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP4_AUX_CLK"}, {213, 5, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP4_AUX_CLK"}, {213, 6, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP4_AUX_CLK"}, {213, 7, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP4_AUX_CLK"}, {213, 8, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP4_AUX_CLK"}, {213, 9, "DEV_MCASP4_MCASP_AFSX_POUT", "Output clock"}, {213, 10, "DEV_MCASP4_MCASP_AHCLKR_POUT", "Output clock"}, {213, 11, "DEV_MCASP4_MCASP_AHCLKR_PIN", "Input muxed clock"}, {213, 12, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, {213, 13, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, {213, 14, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, {213, 15, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, {213, 20, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, {213, 21, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, {213, 22, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, {213, 23, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, {213, 28, "DEV_MCASP4_MCASP_ACLKX_POUT", "Output clock"}, {213, 29, "DEV_MCASP4_MCASP_AFSR_POUT", "Output clock"}, {213, 30, "DEV_MCASP4_VBUSP_CLK", "Input clock"}, {213, 31, "DEV_MCASP4_MCASP_ACLKR_POUT", "Output clock"}, {213, 32, "DEV_MCASP4_MCASP_AHCLKX_POUT", "Output clock"}, {213, 33, "DEV_MCASP4_MCASP_ACLKX_PIN", "Input clock"}, {213, 34, "DEV_MCASP4_MCASP_AHCLKX_PIN", "Input muxed clock"}, {213, 35, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, {213, 36, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, {213, 37, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, {213, 38, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, {213, 43, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, {213, 44, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, {213, 45, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, {213, 46, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, {213, 51, "DEV_MCASP4_MCASP_ACLKR_PIN", "Input clock"}, {339, 0, "DEV_MCSPI0_IO_CLKSPIO_CLK", "Output clock"}, {339, 1, "DEV_MCSPI0_VBUSP_CLK", "Input clock"}, {339, 2, "DEV_MCSPI0_CLKSPIREF_CLK", "Input clock"}, {339, 3, "DEV_MCSPI0_IO_CLKSPII_CLK", "Input muxed clock"}, {339, 4, "DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI0_CLK_OUT", "Parent input clock option to DEV_MCSPI0_IO_CLKSPII_CLK"}, {339, 5, "DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MAIN_0_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI0_IO_CLKSPII_CLK"}, {340, 0, "DEV_MCSPI1_IO_CLKSPIO_CLK", "Output clock"}, {340, 1, "DEV_MCSPI1_VBUSP_CLK", "Input clock"}, {340, 2, "DEV_MCSPI1_CLKSPIREF_CLK", "Input clock"}, {340, 3, "DEV_MCSPI1_IO_CLKSPII_CLK", "Input muxed clock"}, {340, 4, "DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI1_CLK_OUT", "Parent input clock option to DEV_MCSPI1_IO_CLKSPII_CLK"}, {340, 5, "DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_1_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI1_IO_CLKSPII_CLK"}, {341, 0, "DEV_MCSPI2_IO_CLKSPIO_CLK", "Output clock"}, {341, 1, "DEV_MCSPI2_VBUSP_CLK", "Input clock"}, {341, 2, "DEV_MCSPI2_CLKSPIREF_CLK", "Input clock"}, {341, 3, "DEV_MCSPI2_IO_CLKSPII_CLK", "Input muxed clock"}, {341, 4, "DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI2_CLK_OUT", "Parent input clock option to DEV_MCSPI2_IO_CLKSPII_CLK"}, {341, 5, "DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_SPI_MAIN_2_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI2_IO_CLKSPII_CLK"}, {342, 0, "DEV_MCSPI3_IO_CLKSPIO_CLK", "Output clock"}, {342, 1, "DEV_MCSPI3_VBUSP_CLK", "Input clock"}, {342, 2, "DEV_MCSPI3_CLKSPIREF_CLK", "Input clock"}, {342, 3, "DEV_MCSPI3_IO_CLKSPII_CLK", "Input muxed clock"}, {342, 4, "DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI3_IO_CLKSPII_CLK"}, {342, 5, "DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI3_CLK_LPBK_MUX_OUT0", "Parent input clock option to DEV_MCSPI3_IO_CLKSPII_CLK"}, {343, 0, "DEV_MCSPI4_IO_CLKSPIO_CLK", "Output clock"}, {343, 1, "DEV_MCSPI4_VBUSP_CLK", "Input clock"}, {343, 2, "DEV_MCSPI4_CLKSPIREF_CLK", "Input clock"}, {343, 3, "DEV_MCSPI4_IO_CLKSPII_CLK", "Input clock"}, {344, 0, "DEV_MCSPI5_IO_CLKSPIO_CLK", "Output clock"}, {344, 1, "DEV_MCSPI5_VBUSP_CLK", "Input clock"}, {344, 2, "DEV_MCSPI5_CLKSPIREF_CLK", "Input clock"}, {344, 3, "DEV_MCSPI5_IO_CLKSPII_CLK", "Input muxed clock"}, {344, 4, "DEV_MCSPI5_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI5_CLK_OUT", "Parent input clock option to DEV_MCSPI5_IO_CLKSPII_CLK"}, {344, 5, "DEV_MCSPI5_IO_CLKSPII_CLK_PARENT_SPI_MAIN_5_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI5_IO_CLKSPII_CLK"}, {345, 0, "DEV_MCSPI6_IO_CLKSPIO_CLK", "Output clock"}, {345, 1, "DEV_MCSPI6_VBUSP_CLK", "Input clock"}, {345, 2, "DEV_MCSPI6_CLKSPIREF_CLK", "Input clock"}, {345, 3, "DEV_MCSPI6_IO_CLKSPII_CLK", "Input muxed clock"}, {345, 4, "DEV_MCSPI6_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI6_CLK_OUT", "Parent input clock option to DEV_MCSPI6_IO_CLKSPII_CLK"}, {345, 5, "DEV_MCSPI6_IO_CLKSPII_CLK_PARENT_SPI_MAIN_6_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI6_IO_CLKSPII_CLK"}, {346, 0, "DEV_MCSPI7_IO_CLKSPIO_CLK", "Output clock"}, {346, 1, "DEV_MCSPI7_VBUSP_CLK", "Input clock"}, {346, 2, "DEV_MCSPI7_CLKSPIREF_CLK", "Input clock"}, {346, 3, "DEV_MCSPI7_IO_CLKSPII_CLK", "Input muxed clock"}, {346, 4, "DEV_MCSPI7_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI7_CLK_OUT", "Parent input clock option to DEV_MCSPI7_IO_CLKSPII_CLK"}, {346, 5, "DEV_MCSPI7_IO_CLKSPII_CLK_PARENT_SPI_MAIN_7_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI7_IO_CLKSPII_CLK"}, {0, 0, "DEV_MCU_ADC12FC_16FFC0_ADC_CLK", "Input muxed clock"}, {0, 1, "DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_ADC12FC_16FFC0_ADC_CLK"}, {0, 2, "DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC12FC_16FFC0_ADC_CLK"}, {0, 3, "DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC12FC_16FFC0_ADC_CLK"}, {0, 4, "DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC12FC_16FFC0_ADC_CLK"}, {0, 5, "DEV_MCU_ADC12FC_16FFC0_VBUS_CLK", "Input clock"}, {0, 6, "DEV_MCU_ADC12FC_16FFC0_SYS_CLK", "Input clock"}, {1, 0, "DEV_MCU_ADC12FC_16FFC1_ADC_CLK", "Input muxed clock"}, {1, 1, "DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_ADC12FC_16FFC1_ADC_CLK"}, {1, 2, "DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC12FC_16FFC1_ADC_CLK"}, {1, 3, "DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC12FC_16FFC1_ADC_CLK"}, {1, 4, "DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC12FC_16FFC1_ADC_CLK"}, {1, 5, "DEV_MCU_ADC12FC_16FFC1_VBUS_CLK", "Input clock"}, {1, 6, "DEV_MCU_ADC12FC_16FFC1_SYS_CLK", "Input clock"}, {29, 0, "DEV_MCU_CPSW0_MDIO_MDCLK_O", "Output clock"}, {29, 1, "DEV_MCU_CPSW0_CPTS_GENF0", "Output clock"}, {29, 3, "DEV_MCU_CPSW0_CPTS_RFT_CLK", "Input muxed clock"}, {29, 4, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {29, 5, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {29, 6, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {29, 7, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {29, 8, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {29, 9, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {29, 10, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {29, 11, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {29, 12, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN2_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {29, 13, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN3_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {29, 18, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {29, 19, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {29, 20, "DEV_MCU_CPSW0_GMII1_MR_CLK", "Input clock"}, {29, 21, "DEV_MCU_CPSW0_GMII_RFT_CLK", "Input clock"}, {29, 22, "DEV_MCU_CPSW0_RGMII1_RXC_I", "Input clock"}, {29, 26, "DEV_MCU_CPSW0_RMII_MHZ_50_CLK", "Input clock"}, {29, 27, "DEV_MCU_CPSW0_RGMII1_TXC_O", "Output clock"}, {29, 28, "DEV_MCU_CPSW0_CPPI_CLK_CLK", "Input clock"}, {29, 29, "DEV_MCU_CPSW0_RGMII_MHZ_5_CLK", "Input clock"}, {29, 30, "DEV_MCU_CPSW0_GMII1_MT_CLK", "Input clock"}, {29, 32, "DEV_MCU_CPSW0_RGMII_MHZ_50_CLK", "Input clock"}, {29, 33, "DEV_MCU_CPSW0_RGMII_MHZ_250_CLK", "Input clock"}, {37, 0, "DEV_MCU_CPT2_AGGR0_VCLK_CLK", "Input clock"}, {53, 0, "DEV_MCU_DCC0_DCC_CLKSRC0_CLK", "Input clock"}, {53, 1, "DEV_MCU_DCC0_DCC_CLKSRC1_CLK", "Input clock"}, {53, 2, "DEV_MCU_DCC0_DCC_CLKSRC2_CLK", "Input clock"}, {53, 3, "DEV_MCU_DCC0_DCC_CLKSRC3_CLK", "Input clock"}, {53, 4, "DEV_MCU_DCC0_DCC_CLKSRC4_CLK", "Input clock"}, {53, 5, "DEV_MCU_DCC0_DCC_CLKSRC5_CLK", "Input clock"}, {53, 6, "DEV_MCU_DCC0_DCC_CLKSRC6_CLK", "Input clock"}, {53, 7, "DEV_MCU_DCC0_DCC_CLKSRC7_CLK", "Input clock"}, {53, 8, "DEV_MCU_DCC0_DCC_INPUT00_CLK", "Input clock"}, {53, 9, "DEV_MCU_DCC0_DCC_INPUT01_CLK", "Input clock"}, {53, 10, "DEV_MCU_DCC0_DCC_INPUT02_CLK", "Input clock"}, {53, 11, "DEV_MCU_DCC0_DCC_INPUT10_CLK", "Input clock"}, {53, 12, "DEV_MCU_DCC0_VBUS_CLK", "Input clock"}, {54, 0, "DEV_MCU_DCC1_DCC_CLKSRC0_CLK", "Input clock"}, {54, 1, "DEV_MCU_DCC1_DCC_CLKSRC1_CLK", "Input clock"}, {54, 2, "DEV_MCU_DCC1_DCC_CLKSRC2_CLK", "Input clock"}, {54, 3, "DEV_MCU_DCC1_DCC_CLKSRC3_CLK", "Input clock"}, {54, 4, "DEV_MCU_DCC1_DCC_CLKSRC4_CLK", "Input clock"}, {54, 5, "DEV_MCU_DCC1_DCC_CLKSRC5_CLK", "Input clock"}, {54, 6, "DEV_MCU_DCC1_DCC_CLKSRC6_CLK", "Input clock"}, {54, 7, "DEV_MCU_DCC1_DCC_CLKSRC7_CLK", "Input clock"}, {54, 8, "DEV_MCU_DCC1_DCC_INPUT00_CLK", "Input clock"}, {54, 9, "DEV_MCU_DCC1_DCC_INPUT01_CLK", "Input clock"}, {54, 10, "DEV_MCU_DCC1_DCC_INPUT02_CLK", "Input clock"}, {54, 11, "DEV_MCU_DCC1_DCC_INPUT10_CLK", "Input clock"}, {54, 12, "DEV_MCU_DCC1_VBUS_CLK", "Input clock"}, {55, 0, "DEV_MCU_DCC2_DCC_CLKSRC0_CLK", "Input clock"}, {55, 1, "DEV_MCU_DCC2_DCC_CLKSRC1_CLK", "Input clock"}, {55, 2, "DEV_MCU_DCC2_DCC_CLKSRC2_CLK", "Input clock"}, {55, 3, "DEV_MCU_DCC2_DCC_CLKSRC3_CLK", "Input clock"}, {55, 4, "DEV_MCU_DCC2_DCC_CLKSRC4_CLK", "Input clock"}, {55, 6, "DEV_MCU_DCC2_DCC_CLKSRC6_CLK", "Input clock"}, {55, 7, "DEV_MCU_DCC2_DCC_CLKSRC7_CLK", "Input clock"}, {55, 8, "DEV_MCU_DCC2_DCC_INPUT00_CLK", "Input clock"}, {55, 9, "DEV_MCU_DCC2_DCC_INPUT01_CLK", "Input clock"}, {55, 10, "DEV_MCU_DCC2_DCC_INPUT02_CLK", "Input clock"}, {55, 11, "DEV_MCU_DCC2_DCC_INPUT10_CLK", "Input clock"}, {55, 12, "DEV_MCU_DCC2_VBUS_CLK", "Input clock"}, {105, 0, "DEV_MCU_ESM0_CLK", "Input clock"}, {107, 0, "DEV_MCU_FSS0_FSAS_0_GCLK", "Input clock"}, {108, 1, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_INV_CLK", "Input clock"}, {108, 2, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_INV_CLK", "Input clock"}, {108, 3, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_CLK", "Input clock"}, {108, 6, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_CLK", "Input clock"}, {108, 7, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_N", "Output clock"}, {108, 8, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_P", "Output clock"}, {108, 11, "DEV_MCU_FSS0_HYPERBUS1P0_0_CBA_CLK", "Input clock"}, {109, 0, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK", "Input muxed clock"}, {109, 1, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI0_DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK"}, {109, 2, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_OSPI_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK"}, {109, 3, "DEV_MCU_FSS0_OSPI_0_OSPI_HCLK_CLK", "Input clock"}, {109, 4, "DEV_MCU_FSS0_OSPI_0_OSPI_OCLK_CLK", "Output clock"}, {109, 5, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK", "Input muxed clock"}, {109, 6, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK"}, {109, 7, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK"}, {109, 8, "DEV_MCU_FSS0_OSPI_0_OSPI_DQS_CLK", "Input clock"}, {109, 9, "DEV_MCU_FSS0_OSPI_0_OSPI_PCLK_CLK", "Input clock"}, {110, 0, "DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK", "Input muxed clock"}, {110, 1, "DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI1_DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK"}, {110, 2, "DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_1_OSPI_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK"}, {110, 3, "DEV_MCU_FSS0_OSPI_1_OSPI_HCLK_CLK", "Input clock"}, {110, 4, "DEV_MCU_FSS0_OSPI_1_OSPI_OCLK_CLK", "Output clock"}, {110, 5, "DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK", "Input muxed clock"}, {110, 6, "DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK"}, {110, 7, "DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK"}, {110, 8, "DEV_MCU_FSS0_OSPI_1_OSPI_DQS_CLK", "Input clock"}, {110, 9, "DEV_MCU_FSS0_OSPI_1_OSPI_PCLK_CLK", "Input clock"}, {221, 0, "DEV_MCU_I2C0_PORSCL", "Output clock"}, {221, 1, "DEV_MCU_I2C0_PISYS_CLK", "Input clock"}, {221, 2, "DEV_MCU_I2C0_CLK", "Input clock"}, {221, 3, "DEV_MCU_I2C0_PISCL", "Input clock"}, {222, 0, "DEV_MCU_I2C1_PORSCL", "Output clock"}, {222, 1, "DEV_MCU_I2C1_PISYS_CLK", "Input clock"}, {222, 2, "DEV_MCU_I2C1_CLK", "Input clock"}, {222, 3, "DEV_MCU_I2C1_PISCL", "Input clock"}, {118, 0, "DEV_MCU_I3C0_I3C_SCL_DI", "Input clock"}, {118, 1, "DEV_MCU_I3C0_I3C_SCL_DO", "Output clock"}, {118, 2, "DEV_MCU_I3C0_I3C_SCLK_CLK", "Input clock"}, {118, 3, "DEV_MCU_I3C0_I3C_PCLK_CLK", "Input clock"}, {118, 4, "DEV_MCU_I3C0_I3C_SDA_DI", "Input clock"}, {119, 2, "DEV_MCU_I3C1_I3C_SCLK_CLK", "Input clock"}, {119, 3, "DEV_MCU_I3C1_I3C_PCLK_CLK", "Input clock"}, {207, 0, "DEV_MCU_MCAN0_MCANSS_HCLK_CLK", "Input clock"}, {207, 1, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"}, {207, 2, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, {207, 3, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, {207, 4, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, {207, 5, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, {207, 6, "DEV_MCU_MCAN0_MCANSS_CAN_RXD", "Input clock"}, {208, 0, "DEV_MCU_MCAN1_MCANSS_HCLK_CLK", "Input clock"}, {208, 1, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"}, {208, 2, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, {208, 3, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, {208, 4, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, {208, 5, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, {208, 6, "DEV_MCU_MCAN1_MCANSS_CAN_RXD", "Input clock"}, {347, 0, "DEV_MCU_MCSPI0_IO_CLKSPIO_CLK", "Output clock"}, {347, 1, "DEV_MCU_MCSPI0_VBUSP_CLK", "Input clock"}, {347, 2, "DEV_MCU_MCSPI0_CLKSPIREF_CLK", "Input clock"}, {347, 3, "DEV_MCU_MCSPI0_IO_CLKSPII_CLK", "Input muxed clock"}, {347, 4, "DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI0_CLK_OUT", "Parent input clock option to DEV_MCU_MCSPI0_IO_CLKSPII_CLK"}, {347, 5, "DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MCU_0_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCU_MCSPI0_IO_CLKSPII_CLK"}, {348, 0, "DEV_MCU_MCSPI1_IO_CLKSPIO_CLK", "Output clock"}, {348, 1, "DEV_MCU_MCSPI1_VBUSP_CLK", "Input clock"}, {348, 2, "DEV_MCU_MCSPI1_CLKSPIREF_CLK", "Input clock"}, {348, 3, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK", "Input muxed clock"}, {348, 4, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK"}, {348, 5, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_MCU_SPI1_CLK_LPBK_MUX_OUT0", "Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK"}, {349, 0, "DEV_MCU_MCSPI2_IO_CLKSPIO_CLK", "Output clock"}, {349, 1, "DEV_MCU_MCSPI2_VBUSP_CLK", "Input clock"}, {349, 2, "DEV_MCU_MCSPI2_CLKSPIREF_CLK", "Input clock"}, {349, 3, "DEV_MCU_MCSPI2_IO_CLKSPII_CLK", "Input clock"}, {268, 0, "DEV_MCU_NAVSS0_INTR_ROUTER_0_INTR_CLK", "Input clock"}, {269, 0, "DEV_MCU_NAVSS0_MCRC_0_CLK", "Input clock"}, {270, 0, "DEV_MCU_NAVSS0_MODSS_VD2CLK", "Input clock"}, {271, 0, "DEV_MCU_NAVSS0_PROXY0_CLK_CLK", "Input clock"}, {272, 0, "DEV_MCU_NAVSS0_RINGACC0_SYS_CLK", "Input clock"}, {273, 0, "DEV_MCU_NAVSS0_UDMAP_0_SYS_CLK", "Input clock"}, {274, 0, "DEV_MCU_NAVSS0_UDMASS_VD2CLK", "Input clock"}, {275, 0, "DEV_MCU_NAVSS0_UDMASS_INTA_0_SYS_CLK", "Input clock"}, {176, 0, "DEV_MCU_PBIST0_CLK6_CLK", "Input clock"}, {176, 1, "DEV_MCU_PBIST0_CLK8_CLK", "Input clock"}, {176, 3, "DEV_MCU_PBIST0_CLK3_CLK", "Input clock"}, {176, 4, "DEV_MCU_PBIST0_CLK7_CLK", "Input clock"}, {176, 6, "DEV_MCU_PBIST0_CLK4_CLK", "Input clock"}, {176, 7, "DEV_MCU_PBIST0_CLK5_CLK", "Input clock"}, {176, 8, "DEV_MCU_PBIST0_CLK1_CLK", "Input clock"}, {176, 9, "DEV_MCU_PBIST0_CLK2_CLK", "Input clock"}, {177, 0, "DEV_MCU_PBIST1_CLK6_CLK", "Input clock"}, {177, 1, "DEV_MCU_PBIST1_CLK8_CLK", "Input clock"}, {177, 3, "DEV_MCU_PBIST1_CLK3_CLK", "Input clock"}, {177, 4, "DEV_MCU_PBIST1_CLK7_CLK", "Input clock"}, {177, 6, "DEV_MCU_PBIST1_CLK4_CLK", "Input clock"}, {177, 7, "DEV_MCU_PBIST1_CLK5_CLK", "Input clock"}, {177, 8, "DEV_MCU_PBIST1_CLK1_CLK", "Input clock"}, {177, 9, "DEV_MCU_PBIST1_CLK2_CLK", "Input clock"}, {178, 1, "DEV_MCU_PBIST2_CLK8_CLK", "Input clock"}, {284, 0, "DEV_MCU_R5FSS0_CORE0_CPU_CLK", "Input muxed clock"}, {284, 1, "DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK"}, {284, 2, "DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3", "Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK"}, {284, 3, "DEV_MCU_R5FSS0_CORE0_INTERFACE_CLK", "Input clock"}, {284, 4, "DEV_MCU_R5FSS0_CORE0_INTERFACE_PHASE", "Input clock"}, {285, 0, "DEV_MCU_R5FSS0_CORE1_CPU_CLK", "Input muxed clock"}, {285, 1, "DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK"}, {285, 2, "DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3", "Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK"}, {285, 3, "DEV_MCU_R5FSS0_CORE1_INTERFACE_CLK", "Input clock"}, {285, 4, "DEV_MCU_R5FSS0_CORE1_INTERFACE_PHASE", "Input clock"}, {295, 0, "DEV_MCU_RTI0_VBUSP_CLK", "Input clock"}, {295, 1, "DEV_MCU_RTI0_RTI_CLK", "Input muxed clock"}, {295, 2, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, {295, 3, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, {295, 4, "DEV_MCU_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, {295, 5, "DEV_MCU_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, {296, 0, "DEV_MCU_RTI1_VBUSP_CLK", "Input clock"}, {296, 1, "DEV_MCU_RTI1_RTI_CLK", "Input muxed clock"}, {296, 2, "DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"}, {296, 3, "DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"}, {296, 4, "DEV_MCU_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"}, {296, 5, "DEV_MCU_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"}, {35, 0, "DEV_MCU_TIMER0_TIMER_PWM", "Output clock"}, {35, 1, "DEV_MCU_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"}, {35, 2, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 3, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 4, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 5, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 6, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 7, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 8, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 9, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 10, "DEV_MCU_TIMER0_TIMER_HCLK_CLK", "Input clock"}, {83, 1, "DEV_MCU_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"}, {83, 2, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT1", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, {83, 3, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, {83, 10, "DEV_MCU_TIMER1_TIMER_HCLK_CLK", "Input clock"}, {84, 0, "DEV_MCU_TIMER2_TIMER_PWM", "Output clock"}, {84, 1, "DEV_MCU_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"}, {84, 2, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {84, 3, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {84, 4, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {84, 5, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {84, 6, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {84, 7, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {84, 8, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {84, 9, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {84, 10, "DEV_MCU_TIMER2_TIMER_HCLK_CLK", "Input clock"}, {85, 1, "DEV_MCU_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"}, {85, 2, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT3", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, {85, 3, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, {85, 10, "DEV_MCU_TIMER3_TIMER_HCLK_CLK", "Input clock"}, {86, 0, "DEV_MCU_TIMER4_TIMER_PWM", "Output clock"}, {86, 1, "DEV_MCU_TIMER4_TIMER_TCLK_CLK", "Input muxed clock"}, {86, 2, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, {86, 3, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, {86, 4, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, {86, 5, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, {86, 6, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, {86, 7, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, {86, 8, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, {86, 9, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, {86, 10, "DEV_MCU_TIMER4_TIMER_HCLK_CLK", "Input clock"}, {87, 1, "DEV_MCU_TIMER5_TIMER_TCLK_CLK", "Input muxed clock"}, {87, 2, "DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT5", "Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK"}, {87, 3, "DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_4_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK"}, {87, 10, "DEV_MCU_TIMER5_TIMER_HCLK_CLK", "Input clock"}, {88, 0, "DEV_MCU_TIMER6_TIMER_PWM", "Output clock"}, {88, 1, "DEV_MCU_TIMER6_TIMER_TCLK_CLK", "Input muxed clock"}, {88, 2, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, {88, 3, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, {88, 4, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, {88, 5, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, {88, 6, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, {88, 7, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, {88, 8, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, {88, 9, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, {88, 10, "DEV_MCU_TIMER6_TIMER_HCLK_CLK", "Input clock"}, {89, 1, "DEV_MCU_TIMER7_TIMER_TCLK_CLK", "Input muxed clock"}, {89, 2, "DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT7", "Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK"}, {89, 3, "DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_6_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK"}, {89, 10, "DEV_MCU_TIMER7_TIMER_HCLK_CLK", "Input clock"}, {90, 0, "DEV_MCU_TIMER8_TIMER_PWM", "Output clock"}, {90, 1, "DEV_MCU_TIMER8_TIMER_TCLK_CLK", "Input muxed clock"}, {90, 2, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, {90, 3, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, {90, 4, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, {90, 5, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, {90, 6, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, {90, 7, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, {90, 8, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, {90, 9, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, {90, 10, "DEV_MCU_TIMER8_TIMER_HCLK_CLK", "Input clock"}, {91, 1, "DEV_MCU_TIMER9_TIMER_TCLK_CLK", "Input muxed clock"}, {91, 2, "DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT9", "Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK"}, {91, 3, "DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_8_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK"}, {91, 10, "DEV_MCU_TIMER9_TIMER_HCLK_CLK", "Input clock"}, {149, 2, "DEV_MCU_UART0_VBUSP_CLK", "Input clock"}, {149, 3, "DEV_MCU_UART0_FCLK_CLK", "Input muxed clock"}, {149, 4, "DEV_MCU_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_UART0_FCLK_CLK"}, {149, 5, "DEV_MCU_UART0_FCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT5_CLK", "Parent input clock option to DEV_MCU_UART0_FCLK_CLK"}, {98, 1, "DEV_MMCSD0_EMMCSS_XIN_CLK", "Input muxed clock"}, {98, 2, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"}, {98, 3, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"}, {98, 4, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"}, {98, 5, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"}, {98, 7, "DEV_MMCSD0_EMMCSS_VBUS_CLK", "Input clock"}, {99, 1, "DEV_MMCSD1_EMMCSDSS_XIN_CLK", "Input muxed clock"}, {99, 2, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"}, {99, 3, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"}, {99, 4, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"}, {99, 5, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"}, {99, 6, "DEV_MMCSD1_EMMCSDSS_IO_CLK_O", "Output clock"}, {99, 7, "DEV_MMCSD1_EMMCSDSS_IO_CLK_I", "Input clock"}, {99, 8, "DEV_MMCSD1_EMMCSDSS_VBUS_CLK", "Input clock"}, {224, 0, "DEV_NAVSS0_CPTS0_GENF2", "Output clock"}, {224, 1, "DEV_NAVSS0_CPTS0_GENF3", "Output clock"}, {225, 0, "DEV_NAVSS0_BCDMA_0_CLK", "Input clock"}, {226, 0, "DEV_NAVSS0_CPTS_0_TS_GENF0", "Output clock"}, {226, 2, "DEV_NAVSS0_CPTS_0_TS_GENF1", "Output clock"}, {226, 4, "DEV_NAVSS0_CPTS_0_VBUSP_GCLK", "Input clock"}, {226, 5, "DEV_NAVSS0_CPTS_0_RCLK", "Input muxed clock"}, {226, 6, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {226, 7, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {226, 8, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {226, 9, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {226, 10, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {226, 11, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {226, 12, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {226, 13, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {226, 14, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN2_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {226, 15, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN3_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {226, 20, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {226, 21, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {227, 0, "DEV_NAVSS0_INTR_0_INTR_CLK", "Input clock"}, {228, 0, "DEV_NAVSS0_MAILBOX1_0_VCLK_CLK", "Input clock"}, {229, 0, "DEV_NAVSS0_MAILBOX1_1_VCLK_CLK", "Input clock"}, {238, 0, "DEV_NAVSS0_MAILBOX1_10_VCLK_CLK", "Input clock"}, {239, 0, "DEV_NAVSS0_MAILBOX1_11_VCLK_CLK", "Input clock"}, {230, 0, "DEV_NAVSS0_MAILBOX1_2_VCLK_CLK", "Input clock"}, {231, 0, "DEV_NAVSS0_MAILBOX1_3_VCLK_CLK", "Input clock"}, {232, 0, "DEV_NAVSS0_MAILBOX1_4_VCLK_CLK", "Input clock"}, {233, 0, "DEV_NAVSS0_MAILBOX1_5_VCLK_CLK", "Input clock"}, {234, 0, "DEV_NAVSS0_MAILBOX1_6_VCLK_CLK", "Input clock"}, {235, 0, "DEV_NAVSS0_MAILBOX1_7_VCLK_CLK", "Input clock"}, {236, 0, "DEV_NAVSS0_MAILBOX1_8_VCLK_CLK", "Input clock"}, {237, 0, "DEV_NAVSS0_MAILBOX1_9_VCLK_CLK", "Input clock"}, {240, 0, "DEV_NAVSS0_MAILBOX_0_VCLK_CLK", "Input clock"}, {241, 0, "DEV_NAVSS0_MAILBOX_1_VCLK_CLK", "Input clock"}, {250, 0, "DEV_NAVSS0_MAILBOX_10_VCLK_CLK", "Input clock"}, {251, 0, "DEV_NAVSS0_MAILBOX_11_VCLK_CLK", "Input clock"}, {242, 0, "DEV_NAVSS0_MAILBOX_2_VCLK_CLK", "Input clock"}, {243, 0, "DEV_NAVSS0_MAILBOX_3_VCLK_CLK", "Input clock"}, {244, 0, "DEV_NAVSS0_MAILBOX_4_VCLK_CLK", "Input clock"}, {245, 0, "DEV_NAVSS0_MAILBOX_5_VCLK_CLK", "Input clock"}, {246, 0, "DEV_NAVSS0_MAILBOX_6_VCLK_CLK", "Input clock"}, {247, 0, "DEV_NAVSS0_MAILBOX_7_VCLK_CLK", "Input clock"}, {248, 0, "DEV_NAVSS0_MAILBOX_8_VCLK_CLK", "Input clock"}, {249, 0, "DEV_NAVSS0_MAILBOX_9_VCLK_CLK", "Input clock"}, {252, 0, "DEV_NAVSS0_MCRC_0_CLK", "Input clock"}, {253, 0, "DEV_NAVSS0_MODSS_VD2CLK", "Input clock"}, {254, 0, "DEV_NAVSS0_MODSS_INTA_0_SYS_CLK", "Input clock"}, {255, 0, "DEV_NAVSS0_MODSS_INTA_1_SYS_CLK", "Input clock"}, {256, 0, "DEV_NAVSS0_PROXY_0_CLK_CLK", "Input clock"}, {257, 0, "DEV_NAVSS0_PVU_0_CLK_CLK", "Input clock"}, {258, 0, "DEV_NAVSS0_PVU_1_CLK_CLK", "Input clock"}, {259, 0, "DEV_NAVSS0_RINGACC_0_SYS_CLK", "Input clock"}, {260, 0, "DEV_NAVSS0_SPINLOCK_0_CLK", "Input clock"}, {261, 0, "DEV_NAVSS0_TIMERMGR_0_EON_TICK_EVT", "Input clock"}, {261, 1, "DEV_NAVSS0_TIMERMGR_0_VCLK_CLK", "Input clock"}, {262, 0, "DEV_NAVSS0_TIMERMGR_1_EON_TICK_EVT", "Input clock"}, {262, 1, "DEV_NAVSS0_TIMERMGR_1_VCLK_CLK", "Input clock"}, {263, 0, "DEV_NAVSS0_UDMAP_0_SYS_CLK", "Input clock"}, {264, 0, "DEV_NAVSS0_UDMASS_VD2CLK", "Input clock"}, {265, 0, "DEV_NAVSS0_UDMASS_INTA_0_SYS_CLK", "Input clock"}, {266, 0, "DEV_NAVSS0_VIRTSS_VD2CLK", "Input clock"}, {171, 1, "DEV_PBIST0_CLK8_CLK", "Input clock"}, {172, 1, "DEV_PBIST1_CLK8_CLK", "Input clock"}, {175, 1, "DEV_PBIST10_CLK8_CLK", "Input clock"}, {168, 4, "DEV_PBIST11_CLK7_CLK", "Input clock"}, {174, 1, "DEV_PBIST2_CLK8_CLK", "Input clock"}, {170, 1, "DEV_PBIST3_CLK8_CLK", "Input clock"}, {173, 1, "DEV_PBIST4_CLK8_CLK", "Input clock"}, {167, 1, "DEV_PBIST5_CLK8_CLK", "Input clock"}, {276, 0, "DEV_PCIE1_PCIE_LANE0_TXMCLK", "Input clock"}, {276, 1, "DEV_PCIE1_PCIE_LANE0_TXFCLK", "Input clock"}, {276, 2, "DEV_PCIE1_PCIE_LANE0_RXFCLK", "Input clock"}, {276, 3, "DEV_PCIE1_PCIE_LANE0_TXCLK", "Output clock"}, {276, 4, "DEV_PCIE1_PCIE_LANE3_RXFCLK", "Input clock"}, {276, 5, "DEV_PCIE1_PCIE_LANE3_RXCLK", "Input clock"}, {276, 6, "DEV_PCIE1_PCIE_LANE2_RXFCLK", "Input clock"}, {276, 7, "DEV_PCIE1_PCIE_LANE1_TXCLK", "Output clock"}, {276, 8, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK", "Input muxed clock"}, {276, 9, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {276, 10, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {276, 11, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {276, 12, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {276, 13, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {276, 14, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {276, 15, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {276, 16, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {276, 17, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN2_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {276, 18, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN3_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {276, 23, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {276, 24, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {276, 26, "DEV_PCIE1_PCIE_LANE3_TXMCLK", "Input clock"}, {276, 27, "DEV_PCIE1_PCIE_LANE2_RXCLK", "Input clock"}, {276, 28, "DEV_PCIE1_PCIE_LANE1_RXFCLK", "Input clock"}, {276, 29, "DEV_PCIE1_PCIE_LANE0_RXCLK", "Input clock"}, {276, 30, "DEV_PCIE1_PCIE_LANE2_REFCLK", "Input clock"}, {276, 31, "DEV_PCIE1_PCIE_LANE3_REFCLK", "Input clock"}, {276, 32, "DEV_PCIE1_PCIE_LANE2_TXMCLK", "Input clock"}, {276, 33, "DEV_PCIE1_PCIE_LANE1_REFCLK", "Input clock"}, {276, 34, "DEV_PCIE1_PCIE_LANE2_TXFCLK", "Input clock"}, {276, 35, "DEV_PCIE1_PCIE_PM_CLK", "Input clock"}, {276, 36, "DEV_PCIE1_PCIE_LANE1_TXFCLK", "Input clock"}, {276, 37, "DEV_PCIE1_PCIE_LANE1_TXMCLK", "Input clock"}, {276, 38, "DEV_PCIE1_PCIE_LANE0_REFCLK", "Input clock"}, {276, 39, "DEV_PCIE1_PCIE_LANE1_RXCLK", "Input clock"}, {276, 40, "DEV_PCIE1_PCIE_LANE3_TXFCLK", "Input clock"}, {276, 41, "DEV_PCIE1_PCIE_CBA_CLK", "Input clock"}, {276, 42, "DEV_PCIE1_PCIE_LANE2_TXCLK", "Output clock"}, {276, 43, "DEV_PCIE1_PCIE_LANE3_TXCLK", "Output clock"}, {143, 0, "DEV_PSC0_SLOW_CLK", "Input clock"}, {143, 1, "DEV_PSC0_CLK", "Input clock"}, {279, 0, "DEV_R5FSS0_CORE0_CPU_CLK", "Input clock"}, {279, 1, "DEV_R5FSS0_CORE0_INTERFACE_CLK", "Input clock"}, {280, 0, "DEV_R5FSS0_CORE1_CPU_CLK", "Input clock"}, {280, 1, "DEV_R5FSS0_CORE1_INTERFACE_CLK", "Input clock"}, {281, 0, "DEV_R5FSS1_CORE0_CPU_CLK", "Input clock"}, {281, 1, "DEV_R5FSS1_CORE0_INTERFACE_CLK", "Input clock"}, {282, 0, "DEV_R5FSS1_CORE1_CPU_CLK", "Input clock"}, {282, 1, "DEV_R5FSS1_CORE1_INTERFACE_CLK", "Input clock"}, {286, 0, "DEV_RTI0_VBUSP_CLK", "Input clock"}, {286, 1, "DEV_RTI0_RTI_CLK", "Input muxed clock"}, {286, 2, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {286, 3, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {286, 4, "DEV_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {286, 5, "DEV_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {286, 6, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {286, 7, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {286, 8, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {286, 9, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {287, 0, "DEV_RTI1_VBUSP_CLK", "Input clock"}, {287, 1, "DEV_RTI1_RTI_CLK", "Input muxed clock"}, {287, 2, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {287, 3, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {287, 4, "DEV_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {287, 5, "DEV_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {287, 6, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {287, 7, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {287, 8, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {287, 9, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {290, 0, "DEV_RTI15_VBUSP_CLK", "Input clock"}, {290, 1, "DEV_RTI15_RTI_CLK", "Input muxed clock"}, {290, 2, "DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI15_RTI_CLK"}, {290, 3, "DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI15_RTI_CLK"}, {290, 4, "DEV_RTI15_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI15_RTI_CLK"}, {290, 5, "DEV_RTI15_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI15_RTI_CLK"}, {290, 6, "DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI15_RTI_CLK"}, {290, 7, "DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI15_RTI_CLK"}, {290, 8, "DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI15_RTI_CLK"}, {290, 9, "DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI15_RTI_CLK"}, {288, 0, "DEV_RTI16_VBUSP_CLK", "Input clock"}, {288, 1, "DEV_RTI16_RTI_CLK", "Input muxed clock"}, {288, 2, "DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI16_RTI_CLK"}, {288, 3, "DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI16_RTI_CLK"}, {288, 4, "DEV_RTI16_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI16_RTI_CLK"}, {288, 5, "DEV_RTI16_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI16_RTI_CLK"}, {288, 6, "DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI16_RTI_CLK"}, {288, 7, "DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI16_RTI_CLK"}, {288, 8, "DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI16_RTI_CLK"}, {288, 9, "DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI16_RTI_CLK"}, {289, 0, "DEV_RTI17_VBUSP_CLK", "Input clock"}, {289, 1, "DEV_RTI17_RTI_CLK", "Input muxed clock"}, {289, 2, "DEV_RTI17_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI17_RTI_CLK"}, {289, 3, "DEV_RTI17_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI17_RTI_CLK"}, {289, 4, "DEV_RTI17_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI17_RTI_CLK"}, {289, 5, "DEV_RTI17_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI17_RTI_CLK"}, {289, 6, "DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI17_RTI_CLK"}, {289, 7, "DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI17_RTI_CLK"}, {289, 8, "DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI17_RTI_CLK"}, {289, 9, "DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI17_RTI_CLK"}, {291, 0, "DEV_RTI28_VBUSP_CLK", "Input clock"}, {291, 1, "DEV_RTI28_RTI_CLK", "Input muxed clock"}, {291, 2, "DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI28_RTI_CLK"}, {291, 3, "DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI28_RTI_CLK"}, {291, 4, "DEV_RTI28_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI28_RTI_CLK"}, {291, 5, "DEV_RTI28_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI28_RTI_CLK"}, {291, 6, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI28_RTI_CLK"}, {291, 7, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI28_RTI_CLK"}, {291, 8, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI28_RTI_CLK"}, {291, 9, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI28_RTI_CLK"}, {292, 0, "DEV_RTI29_VBUSP_CLK", "Input clock"}, {292, 1, "DEV_RTI29_RTI_CLK", "Input muxed clock"}, {292, 2, "DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI29_RTI_CLK"}, {292, 3, "DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI29_RTI_CLK"}, {292, 4, "DEV_RTI29_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI29_RTI_CLK"}, {292, 5, "DEV_RTI29_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI29_RTI_CLK"}, {292, 6, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI29_RTI_CLK"}, {292, 7, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI29_RTI_CLK"}, {292, 8, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI29_RTI_CLK"}, {292, 9, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI29_RTI_CLK"}, {293, 0, "DEV_RTI30_VBUSP_CLK", "Input clock"}, {293, 1, "DEV_RTI30_RTI_CLK", "Input muxed clock"}, {293, 2, "DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI30_RTI_CLK"}, {293, 3, "DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI30_RTI_CLK"}, {293, 4, "DEV_RTI30_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI30_RTI_CLK"}, {293, 5, "DEV_RTI30_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI30_RTI_CLK"}, {293, 6, "DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI30_RTI_CLK"}, {293, 7, "DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI30_RTI_CLK"}, {293, 8, "DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI30_RTI_CLK"}, {293, 9, "DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI30_RTI_CLK"}, {294, 0, "DEV_RTI31_VBUSP_CLK", "Input clock"}, {294, 1, "DEV_RTI31_RTI_CLK", "Input muxed clock"}, {294, 2, "DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI31_RTI_CLK"}, {294, 3, "DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI31_RTI_CLK"}, {294, 4, "DEV_RTI31_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI31_RTI_CLK"}, {294, 5, "DEV_RTI31_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI31_RTI_CLK"}, {294, 6, "DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI31_RTI_CLK"}, {294, 7, "DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI31_RTI_CLK"}, {294, 8, "DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI31_RTI_CLK"}, {294, 9, "DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI31_RTI_CLK"}, {145, 0, "DEV_SA2_CPSW_PSILSS0_MAIN_CLK", "Input clock"}, {145, 1, "DEV_SA2_CPSW_PSILSS0_MAIN_2_CLK", "Input clock"}, {297, 0, "DEV_SA2_UL0_PKA_IN_CLK", "Input clock"}, {297, 1, "DEV_SA2_UL0_X1_CLK", "Input clock"}, {297, 2, "DEV_SA2_UL0_X2_CLK", "Input clock"}, {365, 0, "DEV_SERDES_10G0_CLK", "Input clock"}, {365, 1, "DEV_SERDES_10G0_CMN_REFCLK_M", "Input clock"}, {365, 1, "DEV_SERDES_10G0_CMN_REFCLK_M", "Output clock"}, {365, 2, "DEV_SERDES_10G0_CMN_REFCLK_P", "Input clock"}, {365, 2, "DEV_SERDES_10G0_CMN_REFCLK_P", "Output clock"}, {365, 3, "DEV_SERDES_10G0_CORE_REF_CLK", "Input muxed clock"}, {365, 4, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"}, {365, 5, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"}, {365, 6, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"}, {365, 7, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"}, {365, 9, "DEV_SERDES_10G0_IP1_LN0_REFCLK", "Output clock"}, {365, 10, "DEV_SERDES_10G0_IP1_LN0_RXCLK", "Output clock"}, {365, 11, "DEV_SERDES_10G0_IP1_LN0_RXFCLK", "Output clock"}, {365, 12, "DEV_SERDES_10G0_IP1_LN0_TXCLK", "Input clock"}, {365, 13, "DEV_SERDES_10G0_IP1_LN0_TXFCLK", "Output clock"}, {365, 14, "DEV_SERDES_10G0_IP1_LN0_TXMCLK", "Output clock"}, {365, 15, "DEV_SERDES_10G0_IP1_LN1_REFCLK", "Output clock"}, {365, 16, "DEV_SERDES_10G0_IP1_LN1_RXCLK", "Output clock"}, {365, 17, "DEV_SERDES_10G0_IP1_LN1_RXFCLK", "Output clock"}, {365, 18, "DEV_SERDES_10G0_IP1_LN1_TXCLK", "Input clock"}, {365, 19, "DEV_SERDES_10G0_IP1_LN1_TXFCLK", "Output clock"}, {365, 20, "DEV_SERDES_10G0_IP1_LN1_TXMCLK", "Output clock"}, {365, 21, "DEV_SERDES_10G0_IP1_LN2_REFCLK", "Output clock"}, {365, 22, "DEV_SERDES_10G0_IP1_LN2_RXCLK", "Output clock"}, {365, 23, "DEV_SERDES_10G0_IP1_LN2_RXFCLK", "Output clock"}, {365, 24, "DEV_SERDES_10G0_IP1_LN2_TXCLK", "Input muxed clock"}, {365, 25, "DEV_SERDES_10G0_IP1_LN2_TXCLK_PARENT_K3_DSS_EDP_MAIN_0_PHY_LN2_TXCLK", "Parent input clock option to DEV_SERDES_10G0_IP1_LN2_TXCLK"}, {365, 26, "DEV_SERDES_10G0_IP1_LN2_TXCLK_PARENT_K3_DSS_EDP_MAIN_0_PHY_LN0_TXCLK", "Parent input clock option to DEV_SERDES_10G0_IP1_LN2_TXCLK"}, {365, 27, "DEV_SERDES_10G0_IP1_LN2_TXFCLK", "Output clock"}, {365, 28, "DEV_SERDES_10G0_IP1_LN2_TXMCLK", "Output clock"}, {365, 29, "DEV_SERDES_10G0_IP1_LN3_REFCLK", "Output clock"}, {365, 30, "DEV_SERDES_10G0_IP1_LN3_RXCLK", "Output clock"}, {365, 31, "DEV_SERDES_10G0_IP1_LN3_RXFCLK", "Output clock"}, {365, 32, "DEV_SERDES_10G0_IP1_LN3_TXCLK", "Input muxed clock"}, {365, 33, "DEV_SERDES_10G0_IP1_LN3_TXCLK_PARENT_K3_DSS_EDP_MAIN_0_PHY_LN3_TXCLK", "Parent input clock option to DEV_SERDES_10G0_IP1_LN3_TXCLK"}, {365, 34, "DEV_SERDES_10G0_IP1_LN3_TXCLK_PARENT_K3_DSS_EDP_MAIN_0_PHY_LN1_TXCLK", "Parent input clock option to DEV_SERDES_10G0_IP1_LN3_TXCLK"}, {365, 35, "DEV_SERDES_10G0_IP1_LN3_TXFCLK", "Output clock"}, {365, 36, "DEV_SERDES_10G0_IP1_LN3_TXMCLK", "Output clock"}, {365, 37, "DEV_SERDES_10G0_IP2_LN0_REFCLK", "Output clock"}, {365, 38, "DEV_SERDES_10G0_IP2_LN0_RXCLK", "Output clock"}, {365, 39, "DEV_SERDES_10G0_IP2_LN0_RXFCLK", "Output clock"}, {365, 40, "DEV_SERDES_10G0_IP2_LN0_TXCLK", "Input clock"}, {365, 41, "DEV_SERDES_10G0_IP2_LN0_TXFCLK", "Output clock"}, {365, 42, "DEV_SERDES_10G0_IP2_LN0_TXMCLK", "Output clock"}, {365, 43, "DEV_SERDES_10G0_IP2_LN1_REFCLK", "Output clock"}, {365, 44, "DEV_SERDES_10G0_IP2_LN1_RXCLK", "Output clock"}, {365, 45, "DEV_SERDES_10G0_IP2_LN1_RXFCLK", "Output clock"}, {365, 46, "DEV_SERDES_10G0_IP2_LN1_TXCLK", "Input clock"}, {365, 47, "DEV_SERDES_10G0_IP2_LN1_TXFCLK", "Output clock"}, {365, 48, "DEV_SERDES_10G0_IP2_LN1_TXMCLK", "Output clock"}, {365, 49, "DEV_SERDES_10G0_IP2_LN2_REFCLK", "Output clock"}, {365, 50, "DEV_SERDES_10G0_IP2_LN2_RXCLK", "Output clock"}, {365, 51, "DEV_SERDES_10G0_IP2_LN2_RXFCLK", "Output clock"}, {365, 52, "DEV_SERDES_10G0_IP2_LN2_TXCLK", "Input clock"}, {365, 53, "DEV_SERDES_10G0_IP2_LN2_TXFCLK", "Output clock"}, {365, 54, "DEV_SERDES_10G0_IP2_LN2_TXMCLK", "Output clock"}, {365, 55, "DEV_SERDES_10G0_IP2_LN3_REFCLK", "Output clock"}, {365, 56, "DEV_SERDES_10G0_IP2_LN3_RXCLK", "Output clock"}, {365, 57, "DEV_SERDES_10G0_IP2_LN3_RXFCLK", "Output clock"}, {365, 58, "DEV_SERDES_10G0_IP2_LN3_TXCLK", "Input clock"}, {365, 59, "DEV_SERDES_10G0_IP2_LN3_TXFCLK", "Output clock"}, {365, 60, "DEV_SERDES_10G0_IP2_LN3_TXMCLK", "Output clock"}, {365, 67, "DEV_SERDES_10G0_IP3_LN1_REFCLK", "Output clock"}, {365, 68, "DEV_SERDES_10G0_IP3_LN1_RXCLK", "Output clock"}, {365, 69, "DEV_SERDES_10G0_IP3_LN1_RXFCLK", "Output clock"}, {365, 70, "DEV_SERDES_10G0_IP3_LN1_TXCLK", "Input clock"}, {365, 71, "DEV_SERDES_10G0_IP3_LN1_TXFCLK", "Output clock"}, {365, 72, "DEV_SERDES_10G0_IP3_LN1_TXMCLK", "Output clock"}, {365, 79, "DEV_SERDES_10G0_IP3_LN3_REFCLK", "Output clock"}, {365, 80, "DEV_SERDES_10G0_IP3_LN3_RXCLK", "Output clock"}, {365, 81, "DEV_SERDES_10G0_IP3_LN3_RXFCLK", "Output clock"}, {365, 82, "DEV_SERDES_10G0_IP3_LN3_TXCLK", "Input clock"}, {365, 83, "DEV_SERDES_10G0_IP3_LN3_TXFCLK", "Output clock"}, {365, 84, "DEV_SERDES_10G0_IP3_LN3_TXMCLK", "Output clock"}, {365, 85, "DEV_SERDES_10G0_IP4_LN0_REFCLK", "Output clock"}, {365, 86, "DEV_SERDES_10G0_IP4_LN0_RXCLK", "Output clock"}, {365, 87, "DEV_SERDES_10G0_IP4_LN0_RXFCLK", "Output clock"}, {365, 88, "DEV_SERDES_10G0_IP4_LN0_TXCLK", "Input clock"}, {365, 89, "DEV_SERDES_10G0_IP4_LN0_TXFCLK", "Output clock"}, {365, 90, "DEV_SERDES_10G0_IP4_LN0_TXMCLK", "Output clock"}, {365, 91, "DEV_SERDES_10G0_IP4_LN1_REFCLK", "Output clock"}, {365, 92, "DEV_SERDES_10G0_IP4_LN1_RXCLK", "Output clock"}, {365, 93, "DEV_SERDES_10G0_IP4_LN1_RXFCLK", "Output clock"}, {365, 94, "DEV_SERDES_10G0_IP4_LN1_TXCLK", "Input clock"}, {365, 95, "DEV_SERDES_10G0_IP4_LN1_TXFCLK", "Output clock"}, {365, 96, "DEV_SERDES_10G0_IP4_LN1_TXMCLK", "Output clock"}, {365, 97, "DEV_SERDES_10G0_IP4_LN2_REFCLK", "Output clock"}, {365, 98, "DEV_SERDES_10G0_IP4_LN2_RXCLK", "Output clock"}, {365, 99, "DEV_SERDES_10G0_IP4_LN2_RXFCLK", "Output clock"}, {365, 100, "DEV_SERDES_10G0_IP4_LN2_TXCLK", "Input clock"}, {365, 101, "DEV_SERDES_10G0_IP4_LN2_TXFCLK", "Output clock"}, {365, 102, "DEV_SERDES_10G0_IP4_LN2_TXMCLK", "Output clock"}, {365, 103, "DEV_SERDES_10G0_IP4_LN3_REFCLK", "Output clock"}, {365, 104, "DEV_SERDES_10G0_IP4_LN3_RXCLK", "Output clock"}, {365, 105, "DEV_SERDES_10G0_IP4_LN3_RXFCLK", "Output clock"}, {365, 106, "DEV_SERDES_10G0_IP4_LN3_TXCLK", "Input clock"}, {365, 107, "DEV_SERDES_10G0_IP4_LN3_TXFCLK", "Output clock"}, {365, 108, "DEV_SERDES_10G0_IP4_LN3_TXMCLK", "Output clock"}, {365, 130, "DEV_SERDES_10G0_TAP_TCK", "Input clock"}, {42, 0, "DEV_STM0_CORE_CLK", "Input clock"}, {42, 1, "DEV_STM0_VBUSP_CLK", "Input clock"}, {42, 2, "DEV_STM0_ATB_CLK", "Input clock"}, {63, 0, "DEV_TIMER0_TIMER_PWM", "Output clock"}, {63, 1, "DEV_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"}, {63, 2, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {63, 3, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {63, 4, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {63, 5, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {63, 6, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {63, 7, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {63, 8, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {63, 9, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {63, 10, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {63, 11, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {63, 12, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {63, 13, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {63, 14, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {63, 15, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {63, 16, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {63, 18, "DEV_TIMER0_TIMER_HCLK_CLK", "Input clock"}, {64, 1, "DEV_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"}, {64, 2, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT1", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {64, 3, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {64, 18, "DEV_TIMER1_TIMER_HCLK_CLK", "Input clock"}, {73, 0, "DEV_TIMER10_TIMER_PWM", "Output clock"}, {73, 1, "DEV_TIMER10_TIMER_TCLK_CLK", "Input muxed clock"}, {73, 2, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {73, 3, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {73, 4, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {73, 5, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {73, 6, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {73, 7, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {73, 8, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {73, 9, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {73, 10, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {73, 11, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {73, 12, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {73, 13, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {73, 14, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {73, 15, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {73, 16, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {73, 18, "DEV_TIMER10_TIMER_HCLK_CLK", "Input clock"}, {74, 1, "DEV_TIMER11_TIMER_TCLK_CLK", "Input muxed clock"}, {74, 2, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT11", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, {74, 3, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_10_TIMER_PWM", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, {74, 18, "DEV_TIMER11_TIMER_HCLK_CLK", "Input clock"}, {75, 0, "DEV_TIMER12_TIMER_PWM", "Output clock"}, {75, 1, "DEV_TIMER12_TIMER_TCLK_CLK", "Input muxed clock"}, {75, 2, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {75, 3, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {75, 4, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {75, 5, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {75, 6, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {75, 7, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {75, 8, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {75, 9, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {75, 10, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {75, 11, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {75, 12, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {75, 13, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {75, 14, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {75, 15, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {75, 16, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {75, 18, "DEV_TIMER12_TIMER_HCLK_CLK", "Input clock"}, {76, 1, "DEV_TIMER13_TIMER_TCLK_CLK", "Input muxed clock"}, {76, 2, "DEV_TIMER13_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT13", "Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK"}, {76, 3, "DEV_TIMER13_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_12_TIMER_PWM", "Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK"}, {76, 18, "DEV_TIMER13_TIMER_HCLK_CLK", "Input clock"}, {77, 0, "DEV_TIMER14_TIMER_PWM", "Output clock"}, {77, 1, "DEV_TIMER14_TIMER_TCLK_CLK", "Input muxed clock"}, {77, 2, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {77, 3, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {77, 4, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {77, 5, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {77, 6, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {77, 7, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {77, 8, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {77, 9, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {77, 10, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {77, 11, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {77, 12, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {77, 13, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {77, 14, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {77, 15, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {77, 16, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {77, 18, "DEV_TIMER14_TIMER_HCLK_CLK", "Input clock"}, {78, 1, "DEV_TIMER15_TIMER_TCLK_CLK", "Input muxed clock"}, {78, 2, "DEV_TIMER15_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT15", "Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK"}, {78, 3, "DEV_TIMER15_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_14_TIMER_PWM", "Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK"}, {78, 18, "DEV_TIMER15_TIMER_HCLK_CLK", "Input clock"}, {79, 0, "DEV_TIMER16_TIMER_PWM", "Output clock"}, {79, 1, "DEV_TIMER16_TIMER_TCLK_CLK", "Input muxed clock"}, {79, 2, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT16", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {79, 3, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_MAIN_TIMER16_AFS_SEL_OUT0", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {79, 34, "DEV_TIMER16_TIMER_HCLK_CLK", "Input clock"}, {80, 1, "DEV_TIMER17_TIMER_TCLK_CLK", "Input muxed clock"}, {80, 2, "DEV_TIMER17_TIMER_TCLK_CLK_PARENT_MAIN_TIMER17_AFS_EN_OUT0", "Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK"}, {80, 3, "DEV_TIMER17_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_16_TIMER_PWM", "Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK"}, {80, 34, "DEV_TIMER17_TIMER_HCLK_CLK", "Input clock"}, {81, 0, "DEV_TIMER18_TIMER_PWM", "Output clock"}, {81, 1, "DEV_TIMER18_TIMER_TCLK_CLK", "Input muxed clock"}, {81, 2, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT18", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {81, 3, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_MAIN_TIMER18_AFS_SEL_OUT0", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {81, 34, "DEV_TIMER18_TIMER_HCLK_CLK", "Input clock"}, {82, 1, "DEV_TIMER19_TIMER_TCLK_CLK", "Input muxed clock"}, {82, 2, "DEV_TIMER19_TIMER_TCLK_CLK_PARENT_MAIN_TIMER19_AFS_EN_OUT0", "Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK"}, {82, 3, "DEV_TIMER19_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_18_TIMER_PWM", "Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK"}, {82, 34, "DEV_TIMER19_TIMER_HCLK_CLK", "Input clock"}, {65, 0, "DEV_TIMER2_TIMER_PWM", "Output clock"}, {65, 1, "DEV_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"}, {65, 2, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {65, 3, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {65, 4, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {65, 5, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {65, 6, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {65, 7, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {65, 8, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {65, 9, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {65, 10, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {65, 11, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {65, 12, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {65, 13, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {65, 14, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {65, 15, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {65, 16, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {65, 18, "DEV_TIMER2_TIMER_HCLK_CLK", "Input clock"}, {66, 1, "DEV_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"}, {66, 2, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT3", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {66, 3, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {66, 18, "DEV_TIMER3_TIMER_HCLK_CLK", "Input clock"}, {67, 0, "DEV_TIMER4_TIMER_PWM", "Output clock"}, {67, 1, "DEV_TIMER4_TIMER_TCLK_CLK", "Input muxed clock"}, {67, 2, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {67, 3, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {67, 4, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {67, 5, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {67, 6, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {67, 7, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {67, 8, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {67, 9, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {67, 10, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {67, 11, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {67, 12, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {67, 13, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {67, 14, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {67, 15, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {67, 16, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {67, 18, "DEV_TIMER4_TIMER_HCLK_CLK", "Input clock"}, {68, 1, "DEV_TIMER5_TIMER_TCLK_CLK", "Input muxed clock"}, {68, 2, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT5", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {68, 3, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {68, 18, "DEV_TIMER5_TIMER_HCLK_CLK", "Input clock"}, {69, 0, "DEV_TIMER6_TIMER_PWM", "Output clock"}, {69, 1, "DEV_TIMER6_TIMER_TCLK_CLK", "Input muxed clock"}, {69, 2, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {69, 3, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {69, 4, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {69, 5, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {69, 6, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {69, 7, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {69, 8, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {69, 9, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {69, 10, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {69, 11, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {69, 12, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {69, 13, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {69, 14, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {69, 15, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {69, 16, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {69, 18, "DEV_TIMER6_TIMER_HCLK_CLK", "Input clock"}, {70, 1, "DEV_TIMER7_TIMER_TCLK_CLK", "Input muxed clock"}, {70, 2, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT7", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {70, 3, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {70, 18, "DEV_TIMER7_TIMER_HCLK_CLK", "Input clock"}, {71, 0, "DEV_TIMER8_TIMER_PWM", "Output clock"}, {71, 1, "DEV_TIMER8_TIMER_TCLK_CLK", "Input muxed clock"}, {71, 2, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {71, 3, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {71, 4, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {71, 5, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {71, 6, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {71, 7, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {71, 8, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {71, 9, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {71, 10, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {71, 11, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {71, 12, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {71, 13, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {71, 14, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {71, 15, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {71, 16, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {71, 18, "DEV_TIMER8_TIMER_HCLK_CLK", "Input clock"}, {72, 1, "DEV_TIMER9_TIMER_TCLK_CLK", "Input muxed clock"}, {72, 2, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT9", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, {72, 3, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_8_TIMER_PWM", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, {72, 18, "DEV_TIMER9_TIMER_HCLK_CLK", "Input clock"}, {124, 0, "DEV_TIMESYNC_INTRTR0_INTR_CLK", "Input clock"}, {146, 2, "DEV_UART0_VBUSP_CLK", "Input clock"}, {146, 3, "DEV_UART0_FCLK_CLK", "Input clock"}, {350, 2, "DEV_UART1_VBUSP_CLK", "Input clock"}, {350, 3, "DEV_UART1_FCLK_CLK", "Input clock"}, {351, 2, "DEV_UART2_VBUSP_CLK", "Input clock"}, {351, 3, "DEV_UART2_FCLK_CLK", "Input clock"}, {352, 2, "DEV_UART3_VBUSP_CLK", "Input clock"}, {352, 3, "DEV_UART3_FCLK_CLK", "Input clock"}, {353, 2, "DEV_UART4_VBUSP_CLK", "Input clock"}, {353, 3, "DEV_UART4_FCLK_CLK", "Input clock"}, {354, 2, "DEV_UART5_VBUSP_CLK", "Input clock"}, {354, 3, "DEV_UART5_FCLK_CLK", "Input clock"}, {355, 2, "DEV_UART6_VBUSP_CLK", "Input clock"}, {355, 3, "DEV_UART6_FCLK_CLK", "Input clock"}, {356, 2, "DEV_UART7_VBUSP_CLK", "Input clock"}, {356, 3, "DEV_UART7_FCLK_CLK", "Input clock"}, {357, 2, "DEV_UART8_VBUSP_CLK", "Input clock"}, {357, 3, "DEV_UART8_FCLK_CLK", "Input clock"}, {358, 2, "DEV_UART9_VBUSP_CLK", "Input clock"}, {358, 3, "DEV_UART9_FCLK_CLK", "Input clock"}, {360, 1, "DEV_USB0_PIPE_RXFCLK", "Input muxed clock"}, {360, 2, "DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN3_RXFCLK", "Parent input clock option to DEV_USB0_PIPE_RXFCLK"}, {360, 3, "DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN1_RXFCLK", "Parent input clock option to DEV_USB0_PIPE_RXFCLK"}, {360, 4, "DEV_USB0_USB2_APB_PCLK_CLK", "Input clock"}, {360, 5, "DEV_USB0_PIPE_TXCLK", "Output clock"}, {360, 7, "DEV_USB0_PIPE_TXFCLK", "Input muxed clock"}, {360, 8, "DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN3_TXFCLK", "Parent input clock option to DEV_USB0_PIPE_TXFCLK"}, {360, 9, "DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN1_TXFCLK", "Parent input clock option to DEV_USB0_PIPE_TXFCLK"}, {360, 10, "DEV_USB0_PIPE_REFCLK", "Input muxed clock"}, {360, 11, "DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN3_REFCLK", "Parent input clock option to DEV_USB0_PIPE_REFCLK"}, {360, 12, "DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN1_REFCLK", "Parent input clock option to DEV_USB0_PIPE_REFCLK"}, {360, 13, "DEV_USB0_PCLK_CLK", "Input clock"}, {360, 15, "DEV_USB0_CLK_LPM_CLK", "Input clock"}, {360, 16, "DEV_USB0_USB2_REFCLOCK_CLK", "Input muxed clock"}, {360, 17, "DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK"}, {360, 18, "DEV_USB0_USB2_REFCLOCK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK"}, {360, 19, "DEV_USB0_PIPE_RXCLK", "Input muxed clock"}, {360, 20, "DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN3_RXCLK", "Parent input clock option to DEV_USB0_PIPE_RXCLK"}, {360, 21, "DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN1_RXCLK", "Parent input clock option to DEV_USB0_PIPE_RXCLK"}, {360, 22, "DEV_USB0_ACLK_CLK", "Input clock"}, {360, 23, "DEV_USB0_BUF_CLK", "Input clock"}, {360, 25, "DEV_USB0_USB2_TAP_TCK", "Input clock"}, {360, 26, "DEV_USB0_PIPE_TXMCLK", "Input muxed clock"}, {360, 27, "DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN3_TXMCLK", "Parent input clock option to DEV_USB0_PIPE_TXMCLK"}, {360, 28, "DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN1_TXMCLK", "Parent input clock option to DEV_USB0_PIPE_TXMCLK"}, {361, 0, "DEV_VPAC0_LDC0_CLK_CLK", "Input clock"}, {361, 1, "DEV_VPAC0_NF_CLK_CLK", "Input clock"}, {361, 2, "DEV_VPAC0_MAIN_CLK", "Input muxed clock"}, {361, 3, "DEV_VPAC0_MAIN_CLK_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT1_CLK", "Parent input clock option to DEV_VPAC0_MAIN_CLK"}, {361, 4, "DEV_VPAC0_MAIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_VPAC0_MAIN_CLK"}, {361, 5, "DEV_VPAC0_VISS0_CLK_CLK", "Input clock"}, {361, 6, "DEV_VPAC0_PSIL_LEAF_CLK", "Input clock"}, {361, 7, "DEV_VPAC0_MSC_CLK", "Input clock"}, {362, 0, "DEV_VUSR_DUAL0_V0_RXFL_CLK", "Output clock"}, {362, 1, "DEV_VUSR_DUAL0_VUSRX_LN0_TXFCLK", "Input clock"}, {362, 2, "DEV_VUSR_DUAL0_V0_CLK", "Input clock"}, {362, 3, "DEV_VUSR_DUAL0_V1_TXPM_CLK", "Output clock"}, {362, 4, "DEV_VUSR_DUAL0_VUSRX_LN1_TXMCLK", "Input clock"}, {362, 5, "DEV_VUSR_DUAL0_V1_TXFL_CLK", "Input clock"}, {362, 6, "DEV_VUSR_DUAL0_VUSRX_LN0_RXCLK", "Input clock"}, {362, 7, "DEV_VUSR_DUAL0_VUSRX_LN2_RXFCLK", "Input clock"}, {362, 8, "DEV_VUSR_DUAL0_VUSRX_LN2_REFCLK", "Input clock"}, {362, 9, "DEV_VUSR_DUAL0_VUSRX_LN3_RXCLK", "Input clock"}, {362, 10, "DEV_VUSR_DUAL0_VUSRX_LN1_RXFCLK", "Input clock"}, {362, 11, "DEV_VUSR_DUAL0_VUSRX_LN0_REFCLK", "Input clock"}, {362, 12, "DEV_VUSR_DUAL0_VUSRX_LN1_TXCLK", "Output clock"}, {362, 13, "DEV_VUSR_DUAL0_VUSRX_LN3_RXFCLK", "Input clock"}, {362, 14, "DEV_VUSR_DUAL0_VUSRX_LN3_TXCLK", "Output clock"}, {362, 15, "DEV_VUSR_DUAL0_VUSRX_LN3_TXMCLK", "Input clock"}, {362, 16, "DEV_VUSR_DUAL0_VUSRX_LN3_TXFCLK", "Input clock"}, {362, 17, "DEV_VUSR_DUAL0_VUSRX_LN0_TXCLK", "Output clock"}, {362, 18, "DEV_VUSR_DUAL0_V1_CLK", "Input clock"}, {362, 19, "DEV_VUSR_DUAL0_V0_TXFL_CLK", "Input clock"}, {362, 20, "DEV_VUSR_DUAL0_VUSRX_LN0_RXFCLK", "Input clock"}, {362, 21, "DEV_VUSR_DUAL0_VUSRX_LN2_RXCLK", "Input clock"}, {362, 22, "DEV_VUSR_DUAL0_V0_TXPM_CLK", "Output clock"}, {362, 23, "DEV_VUSR_DUAL0_V0_RXPM_CLK", "Input clock"}, {362, 24, "DEV_VUSR_DUAL0_VUSRX_LN1_REFCLK", "Input clock"}, {362, 25, "DEV_VUSR_DUAL0_V1_RXPM_CLK", "Input clock"}, {362, 26, "DEV_VUSR_DUAL0_V1_RXFL_CLK", "Output clock"}, {362, 27, "DEV_VUSR_DUAL0_VUSRX_LN2_TXCLK", "Output clock"}, {362, 28, "DEV_VUSR_DUAL0_VUSRX_LN2_TXFCLK", "Input clock"}, {362, 29, "DEV_VUSR_DUAL0_VUSRX_LN0_TXMCLK", "Input clock"}, {362, 30, "DEV_VUSR_DUAL0_VUSRX_LN2_TXMCLK", "Input clock"}, {362, 31, "DEV_VUSR_DUAL0_VUSRX_LN1_TXFCLK", "Input clock"}, {362, 32, "DEV_VUSR_DUAL0_VUSRX_LN3_REFCLK", "Input clock"}, {362, 33, "DEV_VUSR_DUAL0_VUSRX_LN1_RXCLK", "Input clock"}, {151, 0, "DEV_WKUP_DDPA0_DDPA_CLK", "Input clock"}, {104, 0, "DEV_WKUP_ESM0_CLK", "Input clock"}, {115, 0, "DEV_WKUP_GPIO0_MMR_CLK", "Input clock"}, {116, 0, "DEV_WKUP_GPIO1_MMR_CLK", "Input clock"}, {125, 0, "DEV_WKUP_GPIOMUX_INTRTR0_INTR_CLK", "Input clock"}, {304, 0, "DEV_WKUP_HSM0_DAP_CLK", "Input clock"}, {223, 0, "DEV_WKUP_I2C0_PORSCL", "Output clock"}, {223, 1, "DEV_WKUP_I2C0_PISYS_CLK", "Input muxed clock"}, {223, 2, "DEV_WKUP_I2C0_PISYS_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_WKUP_I2C0_PISYS_CLK"}, {223, 3, "DEV_WKUP_I2C0_PISYS_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_WKUP_I2C0_PISYS_CLK"}, {223, 4, "DEV_WKUP_I2C0_CLK", "Input clock"}, {223, 5, "DEV_WKUP_I2C0_PISCL", "Input clock"}, {147, 0, "DEV_WKUP_J7AM_WAKEUP_16FF0_PLL_CTRL_WKUP_CLK24_CLK", "Input clock"}, {147, 1, "DEV_WKUP_J7AM_WAKEUP_16FF0_WKUP_RCOSC_12P5M_CLK", "Output clock"}, {147, 2, "DEV_WKUP_J7AM_WAKEUP_16FF0_WKUP_RCOSC_32K_CLK", "Output clock"}, {123, 0, "DEV_WKUP_PORZ_SYNC0_CLK_12M_RC_CLK", "Input clock"}, {126, 0, "DEV_WKUP_PSC0_SLOW_CLK", "Input clock"}, {126, 1, "DEV_WKUP_PSC0_CLK", "Input clock"}, {359, 2, "DEV_WKUP_UART0_VBUSP_CLK", "Input clock"}, {359, 3, "DEV_WKUP_UART0_FCLK_CLK", "Input muxed clock"}, {359, 4, "DEV_WKUP_UART0_FCLK_CLK_PARENT_WKUP_USART_CLKSEL_OUT0", "Parent input clock option to DEV_WKUP_UART0_FCLK_CLK"}, {359, 5, "DEV_WKUP_UART0_FCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_WKUP_UART0_FCLK_CLK"}, {180, 0, "DEV_WKUP_VTM0_FIX_REF_CLK", "Input clock"}, {180, 1, "DEV_WKUP_VTM0_FIX_REF2_CLK", "Input clock"}, {180, 2, "DEV_WKUP_VTM0_VBUSP_CLK", "Input clock"}, }; k3conf_0.3/soc/j721s2/j721s2_host_info.h0000664000175000017500000000532214375734376014455 0ustar /* * J721S2 Host Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __J721S2_HOST_INFO_H #define __J721S2_HOST_INFO_H #define J721S2_HOST_ID_TIFS 0 #define J721S2_HOST_ID_MCU_0_R5_0 3 #define J721S2_HOST_ID_MCU_0_R5_1 4 #define J721S2_HOST_ID_MCU_0_R5_2 5 #define J721S2_HOST_ID_MCU_0_R5_3 6 #define J721S2_HOST_ID_A72_0 10 #define J721S2_HOST_ID_A72_1 11 #define J721S2_HOST_ID_A72_2 12 #define J721S2_HOST_ID_A72_3 13 #define J721S2_HOST_ID_A72_4 14 #define J721S2_HOST_ID_C7X_0_0 20 #define J721S2_HOST_ID_C7X_0_1 21 #define J721S2_HOST_ID_C7X_1_0 22 #define J721S2_HOST_ID_C7X_1_1 23 #define J721S2_HOST_ID_GPU_0 30 #define J721S2_HOST_ID_MAIN_0_R5_0 35 #define J721S2_HOST_ID_MAIN_0_R5_1 36 #define J721S2_HOST_ID_MAIN_0_R5_2 37 #define J721S2_HOST_ID_MAIN_0_R5_3 38 #define J721S2_HOST_ID_MAIN_1_R5_0 40 #define J721S2_HOST_ID_MAIN_1_R5_1 41 #define J721S2_HOST_ID_MAIN_1_R5_2 42 #define J721S2_HOST_ID_MAIN_1_R5_3 43 #define J721S2_HOST_ID_DM2TIFS 250 #define J721S2_HOST_ID_TIFS2DM 251 #define J721S2_HOST_ID_HSM 253 #define J721S2_HOST_ID_DM 254 #define J721S2_MAX_HOST_IDS 27 extern struct ti_sci_host_info j721s2_host_info[]; #endif /* __J721S2_HOST_INFO_H */ k3conf_0.3/soc/j721s2/j721s2_sec_proxy_info.h0000664000175000017500000000366114375734376015517 0ustar /* * J721S2 Sec Proxy Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __J721S2_SEC_PROXY_INFO_H #define __J721S2_SEC_PROXY_INFO_H #define J721S2_MAIN_SEC_PROXY_THREADS 113 #define J721S2_MCU_SEC_PROXY_THREADS 44 extern struct ti_sci_sec_proxy_info j721s2_main_sp_info[]; extern struct ti_sci_sec_proxy_info j721s2_mcu_sp_info[]; #endif /* __J721S2_SEC_PROXY_INFO_H */ k3conf_0.3/soc/j721s2/j721s2_rm_info.c0000664000175000017500000001134214375734376014110 0ustar /* * J721S2 RM Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_rm_info j721s2_rm_info[] = { {0x1E40, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x1E80, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x1F00, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x1F40, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x2500, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x2580, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x3842, "RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER"}, {0x3843, "RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG"}, {0x384E, "RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN"}, {0x384F, "RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN"}, {0x3861, "RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN"}, {0x3862, "RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN"}, {0x38C0, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x3F8A, "RESASG_SUBTYPE_IA_VINT"}, {0x3F8D, "RESASG_SUBTYPE_GLOBAL_EVENT_SEVT"}, {0x3FCA, "RESASG_SUBTYPE_IA_VINT"}, {0x3FCD, "RESASG_SUBTYPE_GLOBAL_EVENT_SEVT"}, {0x4000, "RESASG_SUBTYPE_PROXY_PROXIES"}, {0x40C0, "RESASG_SUBTYPE_RA_ERROR_OES"}, {0x40C1, "RESASG_SUBTYPE_RA_GP"}, {0x40C2, "RESASG_SUBTYPE_RA_UDMAP_RX"}, {0x40C3, "RESASG_SUBTYPE_RA_UDMAP_TX"}, {0x40C4, "RESASG_SUBTYPE_RA_UDMAP_TX_EXT"}, {0x40C5, "RESASG_SUBTYPE_RA_UDMAP_RX_H"}, {0x40C6, "RESASG_SUBTYPE_RA_UDMAP_RX_UH"}, {0x40C7, "RESASG_SUBTYPE_RA_UDMAP_TX_H"}, {0x40C8, "RESASG_SUBTYPE_RA_UDMAP_TX_UH"}, {0x40CA, "RESASG_SUBTYPE_RA_VIRTID"}, {0x40CB, "RESASG_SUBTYPE_RA_MONITORS"}, {0x41C0, "RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON"}, {0x41C1, "RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES"}, {0x41C2, "RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER"}, {0x41C3, "RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG"}, {0x41CA, "RESASG_SUBTYPE_UDMAP_RX_CHAN"}, {0x41CB, "RESASG_SUBTYPE_UDMAP_RX_HCHAN"}, {0x41CC, "RESASG_SUBTYPE_UDMAP_RX_UHCHAN"}, {0x41CD, "RESASG_SUBTYPE_UDMAP_TX_CHAN"}, {0x41CE, "RESASG_SUBTYPE_UDMAP_TX_ECHAN"}, {0x41CF, "RESASG_SUBTYPE_UDMAP_TX_HCHAN"}, {0x41D0, "RESASG_SUBTYPE_UDMAP_TX_UHCHAN"}, {0x424A, "RESASG_SUBTYPE_IA_VINT"}, {0x424D, "RESASG_SUBTYPE_GLOBAL_EVENT_SEVT"}, {0x424F, "RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_ERROR_OES"}, {0x4250, "RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_DATA_COMPLETION_OES"}, {0x4251, "RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_RING_COMPLETION_OES"}, {0x4252, "RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_ERROR_OES"}, {0x4253, "RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_DATA_COMPLETION_OES"}, {0x4254, "RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_RING_COMPLETION_OES"}, {0x4300, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x43C0, "RESASG_SUBTYPE_PROXY_PROXIES"}, {0x4400, "RESASG_SUBTYPE_RA_ERROR_OES"}, {0x4401, "RESASG_SUBTYPE_RA_GP"}, {0x4402, "RESASG_SUBTYPE_RA_UDMAP_RX"}, {0x4403, "RESASG_SUBTYPE_RA_UDMAP_TX"}, {0x4405, "RESASG_SUBTYPE_RA_UDMAP_RX_H"}, {0x4407, "RESASG_SUBTYPE_RA_UDMAP_TX_H"}, {0x440A, "RESASG_SUBTYPE_RA_VIRTID"}, {0x440B, "RESASG_SUBTYPE_RA_MONITORS"}, {0x4440, "RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON"}, {0x4441, "RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES"}, {0x4442, "RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER"}, {0x4443, "RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG"}, {0x444A, "RESASG_SUBTYPE_UDMAP_RX_CHAN"}, {0x444B, "RESASG_SUBTYPE_UDMAP_RX_HCHAN"}, {0x444D, "RESASG_SUBTYPE_UDMAP_TX_CHAN"}, {0x444F, "RESASG_SUBTYPE_UDMAP_TX_HCHAN"}, {0x44CA, "RESASG_SUBTYPE_IA_VINT"}, {0x44CD, "RESASG_SUBTYPE_GLOBAL_EVENT_SEVT"}, }; k3conf_0.3/soc/j721s2/j721s2_processors_info.c0000664000175000017500000000415214375734376015675 0ustar /* * J721S2 Processor Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_processors_info j721s2_processors_info[] = { {202, 0, 0x20, "A72SS0_CORE0"}, {203, 0, 0x21, "A72SS0_CORE1"}, {8, 0, 0x30, "COMPUTE_CLUSTER0_C71SS0_0"}, {11, 0, 0x31, "COMPUTE_CLUSTER0_C71SS1_0"}, {284, 0, 0x01, "MCU_R5FSS0_CORE0"}, {285, 0, 0x02, "MCU_R5FSS0_CORE1"}, {279, 0, 0x06, "R5FSS0_CORE0"}, {280, 0, 0x07, "R5FSS0_CORE1"}, {281, 0, 0x08, "R5FSS1_CORE0"}, {282, 0, 0x09, "R5FSS1_CORE1"}, {304, 0, 0x80, "WKUP_HSM0"}, }; k3conf_0.3/soc/j721s2/j721s2_processors_info.h0000664000175000017500000000351514375734376015704 0ustar /* * J721S2 Processor Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __J721S2_PROCESSOR_INFO_H #define __J721S2_PROCESSOR_INFO_H #define J721S2_MAX_PROCESSORS_IDS 11 extern struct ti_sci_processors_info j721s2_processors_info[]; #endif /* __J721S2_PROCESSOR_INFO_H */ k3conf_0.3/soc/j721s2/j721s2_host_info.c0000664000175000017500000000671514375734376014457 0ustar /* * J721S2 Hosts Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_host_info j721s2_host_info[] = { {0, "TIFS", "Secure", "Security Controller"}, {3, "MCU_0_R5_0", "Non Secure", "Cortex R5 context 0 on MCU island"}, {4, "MCU_0_R5_1", "Secure", "Cortex R5 context 1 on MCU island(Boot)"}, {5, "MCU_0_R5_2", "Non Secure", "Cortex R5 context 2 on MCU island"}, {6, "MCU_0_R5_3", "Secure", "Cortex R5 context 3 on MCU island"}, {10, "A72_0", "Secure", "Cortex A72 context 0 on Main island"}, {11, "A72_1", "Secure", "Cortex A72 context 1 on Main island"}, {12, "A72_2", "Non Secure", "Cortex A72 context 2 on Main island"}, {13, "A72_3", "Non Secure", "Cortex A72 context 3 on Main island"}, {14, "A72_4", "Non Secure", "Cortex A72 context 4 on Main island"}, {20, "C7X_0_0", "Secure", "C7x_0 Context 0 on Main island"}, {21, "C7X_0_1", "Non Secure", "C7x_0 context 1 on Main island"}, {22, "C7X_1_0", "Secure", "C7x_1 Context 0 on Main island"}, {23, "C7X_1_1", "Non Secure", "C7x_1 context 1 on Main island"}, {30, "GPU_0", "Non Secure", "BXS context 0 on Main island"}, {35, "MAIN_0_R5_0", "Non Secure", "Cortex R5_0 context 0 on Main island"}, {36, "MAIN_0_R5_1", "Secure", "Cortex R5_0 context 1 on Main island"}, {37, "MAIN_0_R5_2", "Non Secure", "Cortex R5_0 context 2 on Main island"}, {38, "MAIN_0_R5_3", "Secure", "Cortex R5_0 context 3 on Main island"}, {40, "MAIN_1_R5_0", "Non Secure", "Cortex R5_1 context 0 on Main island"}, {41, "MAIN_1_R5_1", "Secure", "Cortex R5_1 context 1 on Main island"}, {42, "MAIN_1_R5_2", "Non Secure", "Cortex R5_1 context 2 on Main island"}, {43, "MAIN_1_R5_3", "Secure", "Cortex R5_1 context 3 on Main island"}, {250, "DM2TIFS", "Secure", "DM to TIFS communication"}, {251, "TIFS2DM", "Non Secure", "TIFS to DM communication"}, {253, "HSM", "Secure", "HSM Controller"}, {254, "DM", "Non Secure", "Device Management"}, }; k3conf_0.3/soc/j721s2/j721s2_rm_info.h0000664000175000017500000000342714375734376014122 0ustar /* * J721S2 RM Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __J721S2_RM_INFO_H #define __J721S2_RM_INFO_H #define J721S2_MAX_RES 68 extern struct ti_sci_rm_info j721s2_rm_info[]; #endif /* __J721S2_RM_INFO_H */ k3conf_0.3/soc/j721s2/j721s2_sec_proxy_info.c0000664000175000017500000002171314375734376015510 0ustar /* * J721S2 Sec Proxy Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_sec_proxy_info j721s2_main_sp_info[] = { {350, "read", 18, "DM", "nonsec_high_priority_rx"}, {349, "read", 57, "DM", "nonsec_low_priority_rx"}, {348, "read", 18, "DM", "nonsec_notify_resp_rx"}, {347, "write", 2, "DM", "nonsec_A72_2_notify_tx"}, {346, "write", 22, "DM", "nonsec_A72_2_response_tx"}, {345, "write", 2, "DM", "nonsec_A72_3_notify_tx"}, {344, "write", 7, "DM", "nonsec_A72_3_response_tx"}, {343, "write", 2, "DM", "nonsec_A72_4_notify_tx"}, {342, "write", 7, "DM", "nonsec_A72_4_response_tx"}, {341, "write", 2, "DM", "nonsec_C7X_0_1_notify_tx"}, {340, "write", 7, "DM", "nonsec_C7X_0_1_response_tx"}, {339, "write", 2, "DM", "nonsec_C7X_1_1_notify_tx"}, {338, "write", 7, "DM", "nonsec_C7X_1_1_response_tx"}, {337, "write", 2, "DM", "nonsec_GPU_0_notify_tx"}, {336, "write", 7, "DM", "nonsec_GPU_0_response_tx"}, {335, "write", 2, "DM", "nonsec_MAIN_0_R5_0_notify_tx"}, {334, "write", 7, "DM", "nonsec_MAIN_0_R5_0_response_tx"}, {333, "write", 1, "DM", "nonsec_MAIN_0_R5_2_notify_tx"}, {332, "write", 2, "DM", "nonsec_MAIN_0_R5_2_response_tx"}, {331, "write", 2, "DM", "nonsec_MAIN_1_R5_0_notify_tx"}, {330, "write", 7, "DM", "nonsec_MAIN_1_R5_0_response_tx"}, {329, "write", 1, "DM", "nonsec_MAIN_1_R5_2_notify_tx"}, {328, "write", 2, "DM", "nonsec_MAIN_1_R5_2_response_tx"}, {0, "read", 2, "A72_0", "notify"}, {1, "read", 30, "A72_0", "response"}, {2, "write", 10, "A72_0", "high_priority"}, {3, "write", 20, "A72_0", "low_priority"}, {4, "write", 2, "A72_0", "notify_resp"}, {5, "read", 2, "A72_1", "notify"}, {6, "read", 30, "A72_1", "response"}, {7, "write", 10, "A72_1", "high_priority"}, {8, "write", 20, "A72_1", "low_priority"}, {9, "write", 2, "A72_1", "notify_resp"}, {10, "read", 2, "A72_2", "notify"}, {11, "read", 22, "A72_2", "response"}, {12, "write", 2, "A72_2", "high_priority"}, {13, "write", 20, "A72_2", "low_priority"}, {14, "write", 2, "A72_2", "notify_resp"}, {15, "read", 2, "A72_3", "notify"}, {16, "read", 7, "A72_3", "response"}, {17, "write", 2, "A72_3", "high_priority"}, {18, "write", 5, "A72_3", "low_priority"}, {19, "write", 2, "A72_3", "notify_resp"}, {20, "read", 2, "A72_4", "notify"}, {21, "read", 7, "A72_4", "response"}, {22, "write", 2, "A72_4", "high_priority"}, {23, "write", 5, "A72_4", "low_priority"}, {24, "write", 2, "A72_4", "notify_resp"}, {25, "read", 2, "C7X_0_0", "notify"}, {26, "read", 7, "C7X_0_0", "response"}, {27, "write", 2, "C7X_0_0", "high_priority"}, {28, "write", 5, "C7X_0_0", "low_priority"}, {29, "write", 2, "C7X_0_0", "notify_resp"}, {30, "read", 2, "C7X_0_1", "notify"}, {31, "read", 7, "C7X_0_1", "response"}, {32, "write", 2, "C7X_0_1", "high_priority"}, {33, "write", 5, "C7X_0_1", "low_priority"}, {34, "write", 2, "C7X_0_1", "notify_resp"}, {35, "read", 2, "C7X_1_0", "notify"}, {36, "read", 7, "C7X_1_0", "response"}, {37, "write", 2, "C7X_1_0", "high_priority"}, {38, "write", 5, "C7X_1_0", "low_priority"}, {39, "write", 2, "C7X_1_0", "notify_resp"}, {40, "read", 2, "C7X_1_1", "notify"}, {41, "read", 7, "C7X_1_1", "response"}, {42, "write", 2, "C7X_1_1", "high_priority"}, {43, "write", 5, "C7X_1_1", "low_priority"}, {44, "write", 2, "C7X_1_1", "notify_resp"}, {45, "read", 2, "GPU_0", "notify"}, {46, "read", 7, "GPU_0", "response"}, {47, "write", 2, "GPU_0", "high_priority"}, {48, "write", 5, "GPU_0", "low_priority"}, {49, "write", 2, "GPU_0", "notify_resp"}, {50, "read", 2, "MAIN_0_R5_0", "notify"}, {51, "read", 7, "MAIN_0_R5_0", "response"}, {52, "write", 2, "MAIN_0_R5_0", "high_priority"}, {53, "write", 5, "MAIN_0_R5_0", "low_priority"}, {54, "write", 2, "MAIN_0_R5_0", "notify_resp"}, {55, "read", 2, "MAIN_0_R5_1", "notify"}, {56, "read", 7, "MAIN_0_R5_1", "response"}, {57, "write", 2, "MAIN_0_R5_1", "high_priority"}, {58, "write", 5, "MAIN_0_R5_1", "low_priority"}, {59, "write", 2, "MAIN_0_R5_1", "notify_resp"}, {60, "read", 1, "MAIN_0_R5_2", "notify"}, {61, "read", 2, "MAIN_0_R5_2", "response"}, {62, "write", 1, "MAIN_0_R5_2", "high_priority"}, {63, "write", 1, "MAIN_0_R5_2", "low_priority"}, {64, "write", 1, "MAIN_0_R5_2", "notify_resp"}, {65, "read", 1, "MAIN_0_R5_3", "notify"}, {66, "read", 2, "MAIN_0_R5_3", "response"}, {67, "write", 1, "MAIN_0_R5_3", "high_priority"}, {68, "write", 1, "MAIN_0_R5_3", "low_priority"}, {69, "write", 1, "MAIN_0_R5_3", "notify_resp"}, {70, "read", 2, "MAIN_1_R5_0", "notify"}, {71, "read", 7, "MAIN_1_R5_0", "response"}, {72, "write", 2, "MAIN_1_R5_0", "high_priority"}, {73, "write", 5, "MAIN_1_R5_0", "low_priority"}, {74, "write", 2, "MAIN_1_R5_0", "notify_resp"}, {75, "read", 2, "MAIN_1_R5_1", "notify"}, {76, "read", 7, "MAIN_1_R5_1", "response"}, {77, "write", 2, "MAIN_1_R5_1", "high_priority"}, {78, "write", 5, "MAIN_1_R5_1", "low_priority"}, {79, "write", 2, "MAIN_1_R5_1", "notify_resp"}, {80, "read", 1, "MAIN_1_R5_2", "notify"}, {81, "read", 2, "MAIN_1_R5_2", "response"}, {82, "write", 1, "MAIN_1_R5_2", "high_priority"}, {83, "write", 1, "MAIN_1_R5_2", "low_priority"}, {84, "write", 1, "MAIN_1_R5_2", "notify_resp"}, {85, "read", 1, "MAIN_1_R5_3", "notify"}, {86, "read", 2, "MAIN_1_R5_3", "response"}, {87, "write", 1, "MAIN_1_R5_3", "high_priority"}, {88, "write", 1, "MAIN_1_R5_3", "low_priority"}, {89, "write", 1, "MAIN_1_R5_3", "notify_resp"}, }; struct ti_sci_sec_proxy_info j721s2_mcu_sp_info[] = { {78, "read", 13, "DM", "nonsec_high_priority_rx"}, {77, "read", 13, "DM", "nonsec_low_priority_rx"}, {76, "read", 5, "DM", "nonsec_notify_resp_rx"}, {75, "write", 2, "DM", "nonsec_MCU_0_R5_0_notify_tx"}, {74, "write", 20, "DM", "nonsec_MCU_0_R5_0_response_tx"}, {73, "write", 1, "DM", "nonsec_MCU_0_R5_2_notify_tx"}, {72, "write", 2, "DM", "nonsec_MCU_0_R5_2_response_tx"}, {71, "write", 2, "DM", "nonsec_TIFS2DM_notify_tx"}, {70, "write", 4, "DM", "nonsec_TIFS2DM_response_tx"}, {0, "read", 2, "MCU_0_R5_0", "notify"}, {1, "read", 20, "MCU_0_R5_0", "response"}, {2, "write", 10, "MCU_0_R5_0", "high_priority"}, {3, "write", 10, "MCU_0_R5_0", "low_priority"}, {4, "write", 2, "MCU_0_R5_0", "notify_resp"}, {5, "read", 2, "MCU_0_R5_1", "notify"}, {6, "read", 20, "MCU_0_R5_1", "response"}, {7, "write", 10, "MCU_0_R5_1", "high_priority"}, {8, "write", 10, "MCU_0_R5_1", "low_priority"}, {9, "write", 2, "MCU_0_R5_1", "notify_resp"}, {10, "read", 1, "MCU_0_R5_2", "notify"}, {11, "read", 2, "MCU_0_R5_2", "response"}, {12, "write", 1, "MCU_0_R5_2", "high_priority"}, {13, "write", 1, "MCU_0_R5_2", "low_priority"}, {14, "write", 1, "MCU_0_R5_2", "notify_resp"}, {15, "read", 1, "MCU_0_R5_3", "notify"}, {16, "read", 2, "MCU_0_R5_3", "response"}, {17, "write", 1, "MCU_0_R5_3", "high_priority"}, {18, "write", 1, "MCU_0_R5_3", "low_priority"}, {19, "write", 1, "MCU_0_R5_3", "notify_resp"}, {20, "read", 2, "DM2TIFS", "notify"}, {21, "read", 4, "DM2TIFS", "response"}, {22, "write", 2, "DM2TIFS", "high_priority"}, {23, "write", 2, "DM2TIFS", "low_priority"}, {24, "write", 2, "DM2TIFS", "notify_resp"}, {25, "read", 2, "TIFS2DM", "notify"}, {26, "read", 4, "TIFS2DM", "response"}, {27, "write", 2, "TIFS2DM", "high_priority"}, {28, "write", 2, "TIFS2DM", "low_priority"}, {29, "write", 2, "TIFS2DM", "notify_resp"}, {30, "read", 1, "HSM", "notify"}, {31, "read", 2, "HSM", "response"}, {32, "write", 1, "HSM", "high_priority"}, {33, "write", 1, "HSM", "low_priority"}, {34, "write", 1, "HSM", "notify_resp"}, }; k3conf_0.3/soc/j721s2/j721s2_devices_info.c0000664000175000017500000003111214375734376015111 0ustar /* * J721S2 Devices Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_devices_info j721s2_devices_info[] = { {0, "J721S2_DEV_MCU_ADC12FC_16FFC0"}, {1, "J721S2_DEV_MCU_ADC12FC_16FFC1"}, {2, "J721S2_DEV_ATL0"}, {3, "J721S2_DEV_C71X_0_PBIST_VD"}, {4, "J721S2_DEV_A72SS0"}, {5, "J721S2_DEV_C71X_1_PBIST_VD"}, {6, "J721S2_DEV_COMPUTE_CLUSTER0"}, {7, "J721S2_DEV_A72SS0_CORE0_PBIST_WRAP"}, {8, "J721S2_DEV_COMPUTE_CLUSTER0_C71SS0_0"}, {9, "J721S2_DEV_COMPUTE_CLUSTER0_C71SS0_MMA_0"}, {10, "J721S2_DEV_COMPUTE_CLUSTER0_C71SS0_PBIST_WRAP_0"}, {11, "J721S2_DEV_COMPUTE_CLUSTER0_C71SS1_0"}, {12, "J721S2_DEV_COMPUTE_CLUSTER0_C71SS1_PBIST_WRAP_0"}, {13, "J721S2_DEV_COMPUTE_CLUSTER0_CFG_WRAP_0"}, {14, "J721S2_DEV_COMPUTE_CLUSTER0_CLEC"}, {15, "J721S2_DEV_COMPUTE_CLUSTER0_CORE_CORE"}, {16, "J721S2_DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW_0"}, {17, "J721S2_DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF1_EW_0"}, {18, "J721S2_DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_0"}, {19, "J721S2_DEV_COMPUTE_CLUSTER0_DIVH2_DIVH0_0"}, {20, "J721S2_DEV_COMPUTE_CLUSTER0_DIVH2_DIVH0_1"}, {21, "J721S2_DEV_COMPUTE_CLUSTER0_DIVP_TFT0_0"}, {22, "J721S2_DEV_WKUP_SMS0"}, {23, "J721S2_DEV_COMPUTE_CLUSTER0_DIVP_TFT0_1"}, {24, "J721S2_DEV_COMPUTE_CLUSTER0_DMSC_WRAP_0"}, {25, "J721S2_DEV_COMPUTE_CLUSTER0_EN_MSMC_DOMAIN_0"}, {26, "J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS"}, {27, "J721S2_DEV_COMPUTE_CLUSTER0_PBIST_WRAP_0"}, {28, "J721S2_DEV_CPSW1"}, {29, "J721S2_DEV_MCU_CPSW0"}, {30, "J721S2_DEV_CPT2_AGGR1"}, {31, "J721S2_DEV_CPT2_AGGR5"}, {32, "J721S2_DEV_CPT2_AGGR2"}, {33, "J721S2_DEV_CPT2_AGGR4"}, {34, "J721S2_DEV_CPT2_AGGR3"}, {35, "J721S2_DEV_MCU_TIMER0"}, {36, "J721S2_DEV_CPT2_AGGR0"}, {37, "J721S2_DEV_MCU_CPT2_AGGR0"}, {38, "J721S2_DEV_CSI_RX_IF0"}, {39, "J721S2_DEV_CSI_RX_IF1"}, {40, "J721S2_DEV_CSI_TX_IF_V2_0"}, {41, "J721S2_DEV_CSI_TX_IF_V2_1"}, {42, "J721S2_DEV_STM0"}, {43, "J721S2_DEV_DCC0"}, {44, "J721S2_DEV_DCC1"}, {45, "J721S2_DEV_DCC2"}, {46, "J721S2_DEV_DCC3"}, {47, "J721S2_DEV_DCC4"}, {48, "J721S2_DEV_DCC5"}, {49, "J721S2_DEV_DCC6"}, {50, "J721S2_DEV_DCC7"}, {51, "J721S2_DEV_DCC8"}, {52, "J721S2_DEV_DCC9"}, {53, "J721S2_DEV_MCU_DCC0"}, {54, "J721S2_DEV_MCU_DCC1"}, {55, "J721S2_DEV_MCU_DCC2"}, {57, "J721S2_DEV_DEBUGSS_WRAP0"}, {58, "J721S2_DEV_DMPAC0"}, {59, "J721S2_DEV_DMPAC0_CTSET_0"}, {60, "J721S2_DEV_DMPAC0_INTD_0"}, {61, "J721S2_DEV_GTC0"}, {62, "J721S2_DEV_DMPAC0_SDE_0"}, {63, "J721S2_DEV_TIMER0"}, {64, "J721S2_DEV_TIMER1"}, {65, "J721S2_DEV_TIMER2"}, {66, "J721S2_DEV_TIMER3"}, {67, "J721S2_DEV_TIMER4"}, {68, "J721S2_DEV_TIMER5"}, {69, "J721S2_DEV_TIMER6"}, {70, "J721S2_DEV_TIMER7"}, {71, "J721S2_DEV_TIMER8"}, {72, "J721S2_DEV_TIMER9"}, {73, "J721S2_DEV_TIMER10"}, {74, "J721S2_DEV_TIMER11"}, {75, "J721S2_DEV_TIMER12"}, {76, "J721S2_DEV_TIMER13"}, {77, "J721S2_DEV_TIMER14"}, {78, "J721S2_DEV_TIMER15"}, {79, "J721S2_DEV_TIMER16"}, {80, "J721S2_DEV_TIMER17"}, {81, "J721S2_DEV_TIMER18"}, {82, "J721S2_DEV_TIMER19"}, {83, "J721S2_DEV_MCU_TIMER1"}, {84, "J721S2_DEV_MCU_TIMER2"}, {85, "J721S2_DEV_MCU_TIMER3"}, {86, "J721S2_DEV_MCU_TIMER4"}, {87, "J721S2_DEV_MCU_TIMER5"}, {88, "J721S2_DEV_MCU_TIMER6"}, {89, "J721S2_DEV_MCU_TIMER7"}, {90, "J721S2_DEV_MCU_TIMER8"}, {91, "J721S2_DEV_MCU_TIMER9"}, {92, "J721S2_DEV_ECAP0"}, {93, "J721S2_DEV_ECAP1"}, {94, "J721S2_DEV_ECAP2"}, {95, "J721S2_DEV_ELM0"}, {96, "J721S2_DEV_EMIF_DATA_0_VD"}, {97, "J721S2_DEV_EMIF_DATA_1_VD"}, {98, "J721S2_DEV_MMCSD0"}, {99, "J721S2_DEV_MMCSD1"}, {100, "J721S2_DEV_EQEP0"}, {101, "J721S2_DEV_EQEP1"}, {102, "J721S2_DEV_EQEP2"}, {103, "J721S2_DEV_ESM0"}, {104, "J721S2_DEV_WKUP_ESM0"}, {105, "J721S2_DEV_MCU_ESM0"}, {106, "J721S2_DEV_MCU_FSS0"}, {107, "J721S2_DEV_MCU_FSS0_FSAS_0"}, {108, "J721S2_DEV_MCU_FSS0_HYPERBUS1P0_0"}, {109, "J721S2_DEV_MCU_FSS0_OSPI_0"}, {110, "J721S2_DEV_MCU_FSS0_OSPI_1"}, {111, "J721S2_DEV_GPIO0"}, {112, "J721S2_DEV_GPIO2"}, {113, "J721S2_DEV_GPIO4"}, {114, "J721S2_DEV_GPIO6"}, {115, "J721S2_DEV_WKUP_GPIO0"}, {116, "J721S2_DEV_WKUP_GPIO1"}, {117, "J721S2_DEV_GPMC0"}, {118, "J721S2_DEV_MCU_I3C0"}, {119, "J721S2_DEV_MCU_I3C1"}, {120, "J721S2_DEV_LED0"}, {121, "J721S2_DEV_MAIN2MCU_LVL_INTRTR0"}, {122, "J721S2_DEV_MAIN2MCU_PLS_INTRTR0"}, {123, "J721S2_DEV_WKUP_PORZ_SYNC0"}, {124, "J721S2_DEV_TIMESYNC_INTRTR0"}, {125, "J721S2_DEV_WKUP_GPIOMUX_INTRTR0"}, {126, "J721S2_DEV_WKUP_PSC0"}, {127, "J721S2_DEV_J7AEP_GPU_BXS464_WRAP0"}, {128, "J721S2_DEV_J7AEP_GPU_BXS464_WRAP0_DFT_EMBED_PBIST_0"}, {130, "J721S2_DEV_J7AEP_GPU_BXS464_WRAP0_GPU_SS_0"}, {131, "J721S2_DEV_J7AM_32_64_ATB_FUNNEL0"}, {132, "J721S2_DEV_J7AM_32_64_ATB_FUNNEL1"}, {133, "J721S2_DEV_J7AM_32_64_ATB_FUNNEL2"}, {134, "J721S2_DEV_AGGR_ATB0"}, {135, "J721S2_DEV_J7AM_BOLT_PGD0"}, {136, "J721S2_DEV_CSI_PSILSS0"}, {137, "J721S2_DEV_DEBUGSUSPENDRTR0"}, {138, "J721S2_DEV_DDR0"}, {139, "J721S2_DEV_DDR1"}, {140, "J721S2_DEV_DMPAC_VPAC_PSILSS0"}, {141, "J721S2_DEV_J7AM_HWA_ATB_FUNNEL0"}, {142, "J721S2_DEV_J7AM_MAIN_16FF0"}, {143, "J721S2_DEV_PSC0"}, {144, "J721S2_DEV_J7AM_PULSAR_ATB_FUNNEL0"}, {145, "J721S2_DEV_SA2_CPSW_PSILSS0"}, {146, "J721S2_DEV_UART0"}, {147, "J721S2_DEV_WKUP_J7AM_WAKEUP_16FF0"}, {148, "J721S2_DEV_GPIOMUX_INTRTR0"}, {149, "J721S2_DEV_MCU_UART0"}, {150, "J721S2_DEV_CMPEVENT_INTRTR0"}, {151, "J721S2_DEV_WKUP_DDPA0"}, {152, "J721S2_DEV_DPHY_RX0"}, {153, "J721S2_DEV_DPHY_RX1"}, {154, "J721S2_DEV_DSS_DSI0"}, {155, "J721S2_DEV_DSS_DSI1"}, {156, "J721S2_DEV_DSS_EDP0"}, {157, "J721S2_DEV_BOARD0"}, {158, "J721S2_DEV_DSS0"}, {160, "J721S2_DEV_EPWM0"}, {161, "J721S2_DEV_EPWM1"}, {162, "J721S2_DEV_EPWM2"}, {163, "J721S2_DEV_EPWM3"}, {164, "J721S2_DEV_EPWM4"}, {165, "J721S2_DEV_EPWM5"}, {166, "J721S2_DEV_PBIST7"}, {167, "J721S2_DEV_PBIST5"}, {168, "J721S2_DEV_PBIST11"}, {169, "J721S2_DEV_PBIST8"}, {170, "J721S2_DEV_PBIST3"}, {171, "J721S2_DEV_PBIST0"}, {172, "J721S2_DEV_PBIST1"}, {173, "J721S2_DEV_PBIST4"}, {174, "J721S2_DEV_PBIST2"}, {175, "J721S2_DEV_PBIST10"}, {176, "J721S2_DEV_MCU_PBIST0"}, {177, "J721S2_DEV_MCU_PBIST1"}, {178, "J721S2_DEV_MCU_PBIST2"}, {179, "J721S2_DEV_CODEC0"}, {180, "J721S2_DEV_WKUP_VTM0"}, {181, "J721S2_DEV_MAIN2WKUPMCU_VD"}, {182, "J721S2_DEV_MCAN0"}, {183, "J721S2_DEV_MCAN1"}, {184, "J721S2_DEV_MCAN2"}, {185, "J721S2_DEV_MCAN3"}, {186, "J721S2_DEV_MCAN4"}, {187, "J721S2_DEV_MCAN5"}, {188, "J721S2_DEV_MCAN6"}, {189, "J721S2_DEV_MCAN7"}, {190, "J721S2_DEV_MCAN8"}, {191, "J721S2_DEV_MCAN9"}, {192, "J721S2_DEV_MCAN10"}, {193, "J721S2_DEV_MCAN11"}, {194, "J721S2_DEV_MCAN12"}, {195, "J721S2_DEV_MCAN13"}, {197, "J721S2_DEV_MCAN14"}, {199, "J721S2_DEV_MCAN15"}, {201, "J721S2_DEV_MCAN16"}, {202, "J721S2_DEV_A72SS0_CORE0"}, {203, "J721S2_DEV_A72SS0_CORE1"}, {206, "J721S2_DEV_MCAN17"}, {207, "J721S2_DEV_MCU_MCAN0"}, {208, "J721S2_DEV_MCU_MCAN1"}, {209, "J721S2_DEV_MCASP0"}, {210, "J721S2_DEV_MCASP1"}, {211, "J721S2_DEV_MCASP2"}, {212, "J721S2_DEV_MCASP3"}, {213, "J721S2_DEV_MCASP4"}, {214, "J721S2_DEV_I2C0"}, {215, "J721S2_DEV_I2C1"}, {216, "J721S2_DEV_I2C2"}, {217, "J721S2_DEV_I2C3"}, {218, "J721S2_DEV_I2C4"}, {219, "J721S2_DEV_I2C5"}, {220, "J721S2_DEV_I2C6"}, {221, "J721S2_DEV_MCU_I2C0"}, {222, "J721S2_DEV_MCU_I2C1"}, {223, "J721S2_DEV_WKUP_I2C0"}, {224, "J721S2_DEV_NAVSS0"}, {225, "J721S2_DEV_NAVSS0_BCDMA_0"}, {226, "J721S2_DEV_NAVSS0_CPTS_0"}, {227, "J721S2_DEV_NAVSS0_INTR_0"}, {228, "J721S2_DEV_NAVSS0_MAILBOX1_0"}, {229, "J721S2_DEV_NAVSS0_MAILBOX1_1"}, {230, "J721S2_DEV_NAVSS0_MAILBOX1_2"}, {231, "J721S2_DEV_NAVSS0_MAILBOX1_3"}, {232, "J721S2_DEV_NAVSS0_MAILBOX1_4"}, {233, "J721S2_DEV_NAVSS0_MAILBOX1_5"}, {234, "J721S2_DEV_NAVSS0_MAILBOX1_6"}, {235, "J721S2_DEV_NAVSS0_MAILBOX1_7"}, {236, "J721S2_DEV_NAVSS0_MAILBOX1_8"}, {237, "J721S2_DEV_NAVSS0_MAILBOX1_9"}, {238, "J721S2_DEV_NAVSS0_MAILBOX1_10"}, {239, "J721S2_DEV_NAVSS0_MAILBOX1_11"}, {240, "J721S2_DEV_NAVSS0_MAILBOX_0"}, {241, "J721S2_DEV_NAVSS0_MAILBOX_1"}, {242, "J721S2_DEV_NAVSS0_MAILBOX_2"}, {243, "J721S2_DEV_NAVSS0_MAILBOX_3"}, {244, "J721S2_DEV_NAVSS0_MAILBOX_4"}, {245, "J721S2_DEV_NAVSS0_MAILBOX_5"}, {246, "J721S2_DEV_NAVSS0_MAILBOX_6"}, {247, "J721S2_DEV_NAVSS0_MAILBOX_7"}, {248, "J721S2_DEV_NAVSS0_MAILBOX_8"}, {249, "J721S2_DEV_NAVSS0_MAILBOX_9"}, {250, "J721S2_DEV_NAVSS0_MAILBOX_10"}, {251, "J721S2_DEV_NAVSS0_MAILBOX_11"}, {252, "J721S2_DEV_NAVSS0_MCRC_0"}, {253, "J721S2_DEV_NAVSS0_MODSS"}, {254, "J721S2_DEV_NAVSS0_MODSS_INTA_0"}, {255, "J721S2_DEV_NAVSS0_MODSS_INTA_1"}, {256, "J721S2_DEV_NAVSS0_PROXY_0"}, {257, "J721S2_DEV_NAVSS0_PVU_0"}, {258, "J721S2_DEV_NAVSS0_PVU_1"}, {259, "J721S2_DEV_NAVSS0_RINGACC_0"}, {260, "J721S2_DEV_NAVSS0_SPINLOCK_0"}, {261, "J721S2_DEV_NAVSS0_TIMERMGR_0"}, {262, "J721S2_DEV_NAVSS0_TIMERMGR_1"}, {263, "J721S2_DEV_NAVSS0_UDMAP_0"}, {264, "J721S2_DEV_NAVSS0_UDMASS"}, {265, "J721S2_DEV_NAVSS0_UDMASS_INTA_0"}, {266, "J721S2_DEV_NAVSS0_VIRTSS"}, {267, "J721S2_DEV_MCU_NAVSS0"}, {268, "J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0"}, {269, "J721S2_DEV_MCU_NAVSS0_MCRC_0"}, {270, "J721S2_DEV_MCU_NAVSS0_MODSS"}, {271, "J721S2_DEV_MCU_NAVSS0_PROXY0"}, {272, "J721S2_DEV_MCU_NAVSS0_RINGACC0"}, {273, "J721S2_DEV_MCU_NAVSS0_UDMAP_0"}, {274, "J721S2_DEV_MCU_NAVSS0_UDMASS"}, {275, "J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0"}, {276, "J721S2_DEV_PCIE1"}, {277, "J721S2_DEV_R5FSS0"}, {278, "J721S2_DEV_R5FSS1"}, {279, "J721S2_DEV_R5FSS0_CORE0"}, {280, "J721S2_DEV_R5FSS0_CORE1"}, {281, "J721S2_DEV_R5FSS1_CORE0"}, {282, "J721S2_DEV_R5FSS1_CORE1"}, {283, "J721S2_DEV_MCU_R5FSS0"}, {284, "J721S2_DEV_MCU_R5FSS0_CORE0"}, {285, "J721S2_DEV_MCU_R5FSS0_CORE1"}, {286, "J721S2_DEV_RTI0"}, {287, "J721S2_DEV_RTI1"}, {288, "J721S2_DEV_RTI16"}, {289, "J721S2_DEV_RTI17"}, {290, "J721S2_DEV_RTI15"}, {291, "J721S2_DEV_RTI28"}, {292, "J721S2_DEV_RTI29"}, {293, "J721S2_DEV_RTI30"}, {294, "J721S2_DEV_RTI31"}, {295, "J721S2_DEV_MCU_RTI0"}, {296, "J721S2_DEV_MCU_RTI1"}, {297, "J721S2_DEV_SA2_UL0"}, {304, "J721S2_DEV_WKUP_HSM0"}, {339, "J721S2_DEV_MCSPI0"}, {340, "J721S2_DEV_MCSPI1"}, {341, "J721S2_DEV_MCSPI2"}, {342, "J721S2_DEV_MCSPI3"}, {343, "J721S2_DEV_MCSPI4"}, {344, "J721S2_DEV_MCSPI5"}, {345, "J721S2_DEV_MCSPI6"}, {346, "J721S2_DEV_MCSPI7"}, {347, "J721S2_DEV_MCU_MCSPI0"}, {348, "J721S2_DEV_MCU_MCSPI1"}, {349, "J721S2_DEV_MCU_MCSPI2"}, {350, "J721S2_DEV_UART1"}, {351, "J721S2_DEV_UART2"}, {352, "J721S2_DEV_UART3"}, {353, "J721S2_DEV_UART4"}, {354, "J721S2_DEV_UART5"}, {355, "J721S2_DEV_UART6"}, {356, "J721S2_DEV_UART7"}, {357, "J721S2_DEV_UART8"}, {358, "J721S2_DEV_UART9"}, {359, "J721S2_DEV_WKUP_UART0"}, {360, "J721S2_DEV_USB0"}, {361, "J721S2_DEV_VPAC0"}, {362, "J721S2_DEV_VUSR_DUAL0"}, {363, "J721S2_DEV_DPHY_TX0"}, {364, "J721S2_DEV_DPHY_TX1"}, {365, "J721S2_DEV_SERDES_10G0"}, {366, "J721S2_DEV_WKUPMCU2MAIN_VD"}, {367, "J721S2_DEV_FFI_MAIN_AC_CBASS_VD"}, {368, "J721S2_DEV_FFI_MAIN_AC_QM_CBASS_VD"}, {369, "J721S2_DEV_FFI_MAIN_HC_CBASS_VD"}, {370, "J721S2_DEV_FFI_MAIN_INFRA_CBASS_VD"}, {371, "J721S2_DEV_FFI_MAIN_IP_CBASS_VD"}, {372, "J721S2_DEV_FFI_MAIN_RC_CBASS_VD"}, {373, "J721S2_DEV_J7AEP_GPU_BXS464_WRAP0_GPUCORE_0"}, {374, "J721S2_DEV_DMPAC0_UTC_0"}, }; k3conf_0.3/soc/j7200/0000775000175000017500000000000014504336530011074 5ustar k3conf_0.3/soc/j7200/j7200_rm_info.h0000664000175000017500000000342114504336513013521 0ustar /* * J7200 RM Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __J7200_RM_INFO_H #define __J7200_RM_INFO_H #define J7200_MAX_RES 54 extern struct ti_sci_rm_info j7200_rm_info[]; #endif /* __J7200_RM_INFO_H */ k3conf_0.3/soc/j7200/j7200_clocks_info.c0000664000175000017500000045714014375734376014406 0ustar /* * J7200 Clocks Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_clocks_info j7200_clocks_info[] = { {4, 0, "DEV_A72SS0_CORE0_ARM_CLK_CLK", "Input clock"}, {4, 1, "DEV_A72SS0_CORE0_MSMC_CLK", "Input clock"}, {4, 2, "DEV_A72SS0_CORE0_PLL_CTRL_CLK", "Input clock"}, {202, 2, "DEV_A72SS0_CORE0_0_ARM_CLK_CLK", "Input clock"}, {203, 0, "DEV_A72SS0_CORE0_1_ARM_CLK_CLK", "Input clock"}, {2, 0, "DEV_ATL0_VBUS_CLK", "Input clock"}, {2, 1, "DEV_ATL0_ATL_CLK", "Input muxed clock"}, {2, 2, "DEV_ATL0_ATL_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT1_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"}, {2, 3, "DEV_ATL0_ATL_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"}, {2, 6, "DEV_ATL0_ATL_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"}, {2, 7, "DEV_ATL0_ATL_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_CLK"}, {2, 8, "DEV_ATL0_ATL_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_CLK"}, {2, 10, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_1", "Output clock"}, {2, 11, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_3", "Output clock"}, {2, 12, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_2", "Output clock"}, {2, 13, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT", "Output clock"}, {157, 1, "DEV_BOARD0_I2C1_SCL_OUT", "Output clock"}, {157, 2, "DEV_BOARD0_MCASP0_ACLKR_OUT", "Output clock"}, {157, 3, "DEV_BOARD0_SPI2_CLK_IN", "Input clock"}, {157, 4, "DEV_BOARD0_I2C3_SCL_OUT", "Output clock"}, {157, 5, "DEV_BOARD0_OBSCLK2_IN", "Input clock"}, {157, 6, "DEV_BOARD0_MCU_I3C0_SCL_IN", "Input clock"}, {157, 7, "DEV_BOARD0_MCU_HYPERBUS0_CKN_IN", "Input clock"}, {157, 8, "DEV_BOARD0_I2C4_SCL_OUT", "Output clock"}, {157, 9, "DEV_BOARD0_RGMII3_TXC_IN", "Input clock"}, {157, 11, "DEV_BOARD0_EXT_REFCLK1_OUT", "Output clock"}, {157, 12, "DEV_BOARD0_SPI1_CLK_IN", "Input clock"}, {157, 13, "DEV_BOARD0_GPMC0_CLKOUT_IN", "Input clock"}, {157, 14, "DEV_BOARD0_MCU_OBSCLK0_IN", "Input muxed clock"}, {157, 15, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"}, {157, 16, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"}, {157, 31, "DEV_BOARD0_MCU_I3C0_SCL_OUT", "Output clock"}, {157, 32, "DEV_BOARD0_SPI3_CLK_IN", "Input clock"}, {157, 33, "DEV_BOARD0_MCASP0_ACLKX_OUT", "Output clock"}, {157, 34, "DEV_BOARD0_MCASP1_ACLKR_IN", "Input clock"}, {157, 35, "DEV_BOARD0_CLKOUT_IN", "Input muxed clock"}, {157, 36, "DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK5", "Parent input clock option to DEV_BOARD0_CLKOUT_IN"}, {157, 37, "DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK10", "Parent input clock option to DEV_BOARD0_CLKOUT_IN"}, {157, 38, "DEV_BOARD0_OBSCLK1_IN", "Input clock"}, {157, 39, "DEV_BOARD0_MCU_RMII1_REF_CLK_OUT", "Output clock"}, {157, 40, "DEV_BOARD0_GPMC0_CLK_OUT", "Output clock"}, {157, 41, "DEV_BOARD0_I3C0_SCL_OUT", "Output clock"}, {157, 43, "DEV_BOARD0_TCK_OUT", "Output clock"}, {157, 44, "DEV_BOARD0_HFOSC1_CLK_OUT", "Output clock"}, {157, 45, "DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT", "Output clock"}, {157, 46, "DEV_BOARD0_I2C6_SCL_OUT", "Output clock"}, {157, 48, "DEV_BOARD0_I2C5_SCL_OUT", "Output clock"}, {157, 49, "DEV_BOARD0_MCU_OSPI0_DQS_OUT", "Output clock"}, {157, 52, "DEV_BOARD0_RGMII2_RXC_OUT", "Output clock"}, {157, 53, "DEV_BOARD0_MCASP2_ACLKX_IN", "Input clock"}, {157, 54, "DEV_BOARD0_I2C0_SCL_OUT", "Output clock"}, {157, 57, "DEV_BOARD0_MCU_HYPERBUS0_CK_IN", "Input clock"}, {157, 59, "DEV_BOARD0_MCASP1_ACLKX_OUT", "Output clock"}, {157, 61, "DEV_BOARD0_MCU_CPTS0_RFT_CLK_OUT", "Output clock"}, {157, 62, "DEV_BOARD0_MDIO0_MDC_IN", "Input clock"}, {157, 63, "DEV_BOARD0_RGMII1_TXC_IN", "Input clock"}, {157, 65, "DEV_BOARD0_MMC1_CLK_IN", "Input clock"}, {157, 66, "DEV_BOARD0_MCASP2_ACLKR_IN", "Input clock"}, {157, 68, "DEV_BOARD0_WKUP_I2C0_SCL_OUT", "Output clock"}, {157, 69, "DEV_BOARD0_MCU_CLKOUT0_IN", "Input muxed clock"}, {157, 70, "DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK5", "Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN"}, {157, 71, "DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK10", "Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN"}, {157, 73, "DEV_BOARD0_MCASP0_ACLKR_IN", "Input clock"}, {157, 74, "DEV_BOARD0_MCU_MDIO0_MDC_IN", "Input clock"}, {157, 77, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN", "Input muxed clock"}, {157, 78, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 79, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 80, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 90, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 91, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 92, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 102, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 103, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 104, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 105, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 106, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 110, "DEV_BOARD0_MCU_OSPI0_CLK_IN", "Input clock"}, {157, 114, "DEV_BOARD0_MCU_SYSCLKOUT0_IN", "Input clock"}, {157, 115, "DEV_BOARD0_RGMII1_RXC_OUT", "Output clock"}, {157, 116, "DEV_BOARD0_LED_CLK_OUT", "Output clock"}, {157, 118, "DEV_BOARD0_RGMII2_TXC_IN", "Input clock"}, {157, 119, "DEV_BOARD0_I3C0_SCL_IN", "Input clock"}, {157, 120, "DEV_BOARD0_MCU_I2C0_SCL_OUT", "Output clock"}, {157, 122, "DEV_BOARD0_SPI6_CLK_IN", "Input clock"}, {157, 123, "DEV_BOARD0_WKUP_I2C0_SCL_IN", "Input clock"}, {157, 124, "DEV_BOARD0_WKUP_LF_CLKIN_OUT", "Output clock"}, {157, 126, "DEV_BOARD0_MCU_SPI1_CLK_IN", "Input clock"}, {157, 127, "DEV_BOARD0_MCASP0_ACLKX_IN", "Input clock"}, {157, 128, "DEV_BOARD0_MCASP1_ACLKX_IN", "Input clock"}, {157, 130, "DEV_BOARD0_MCU_SPI0_CLK_IN", "Input clock"}, {157, 131, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN", "Input muxed clock"}, {157, 132, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 133, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 134, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 144, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 145, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 146, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 156, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 157, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 158, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 159, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 160, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 164, "DEV_BOARD0_MCU_RGMII1_TXC_IN", "Input clock"}, {157, 165, "DEV_BOARD0_CPTS0_RFT_CLK_OUT", "Output clock"}, {157, 166, "DEV_BOARD0_MCU_I2C1_SCL_OUT", "Output clock"}, {157, 168, "DEV_BOARD0_MCASP2_ACLKR_OUT", "Output clock"}, {157, 169, "DEV_BOARD0_MCU_I2C0_SCL_IN", "Input clock"}, {157, 170, "DEV_BOARD0_RMII_REF_CLK_OUT", "Output clock"}, {157, 171, "DEV_BOARD0_GPMC0_CLK_IN", "Input clock"}, {157, 172, "DEV_BOARD0_TRC_CLK_IN", "Input clock"}, {157, 174, "DEV_BOARD0_MCASP2_ACLKX_OUT", "Output clock"}, {157, 176, "DEV_BOARD0_RGMII4_RXC_OUT", "Output clock"}, {157, 177, "DEV_BOARD0_SYSCLKOUT0_IN", "Input clock"}, {157, 178, "DEV_BOARD0_MCASP1_ACLKR_OUT", "Output clock"}, {157, 179, "DEV_BOARD0_SPI5_CLK_IN", "Input clock"}, {157, 180, "DEV_BOARD0_MCU_RGMII1_RXC_OUT", "Output clock"}, {157, 181, "DEV_BOARD0_RGMII3_RXC_OUT", "Output clock"}, {157, 183, "DEV_BOARD0_SPI0_CLK_IN", "Input clock"}, {157, 184, "DEV_BOARD0_GPMC0_FCLK_MUX_IN", "Input clock"}, {157, 185, "DEV_BOARD0_I2C2_SCL_OUT", "Output clock"}, {157, 186, "DEV_BOARD0_MCU_EXT_REFCLK0_OUT", "Output clock"}, {157, 187, "DEV_BOARD0_MCU_OSPI0_LBCLKO_IN", "Input clock"}, {157, 189, "DEV_BOARD0_SPI7_CLK_IN", "Input clock"}, {157, 190, "DEV_BOARD0_RGMII4_TXC_IN", "Input clock"}, {157, 191, "DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT", "Output clock"}, {157, 192, "DEV_BOARD0_OBSCLK0_IN", "Input clock"}, {157, 193, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 194, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 195, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 196, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 197, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 205, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 206, "DEV_BOARD0_OBSCLK0_IN_PARENT_OBSCLK1_MUX_OUT0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 207, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 219, "DEV_BOARD0_OBSCLK0_IN_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 220, "DEV_BOARD0_OBSCLK0_IN_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 221, "DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 222, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 223, "DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 224, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {123, 0, "DEV_CMPEVENT_INTRTR0_INTR_CLK", "Input clock"}, {3, 0, "DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_PLL_CTRL_CLK", "Input clock"}, {3, 2, "DEV_COMPUTE_CLUSTER0_TB_SOC_VBUSP_DBG_CLK", "Input clock"}, {3, 3, "DEV_COMPUTE_CLUSTER0_TB_SOC_GIC_CLK", "Input clock"}, {3, 4, "DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_DDR_PLL_CLK", "Input clock"}, {3, 5, "DEV_COMPUTE_CLUSTER0_TB_SOC_VBUSP_CFG_CLK", "Input clock"}, {3, 6, "DEV_COMPUTE_CLUSTER0_TB_SOC_VBUSP_DMSC_CLK", "Input clock"}, {17, 4, "DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVH_CLK4_CLK_CLK", "Input clock"}, {19, 0, "DEV_CPSW0_MDIO_MDCLK_O", "Output clock"}, {19, 1, "DEV_CPSW0_GMII3_MT_CLK", "Input clock"}, {19, 2, "DEV_CPSW0_GMII2_MR_CLK", "Input clock"}, {19, 3, "DEV_CPSW0_SERDES4_RXCLK", "Input clock"}, {19, 4, "DEV_CPSW0_CPTS_GENF0", "Output clock"}, {19, 5, "DEV_CPSW0_PRE_RGMII4_TCLK", "Output clock"}, {19, 6, "DEV_CPSW0_RGMII3_RXC_I", "Input clock"}, {19, 7, "DEV_CPSW0_RGMII4_RXC_I", "Input clock"}, {19, 8, "DEV_CPSW0_PRE_RGMII3_TCLK", "Output clock"}, {19, 9, "DEV_CPSW0_RGMII1_RXC_I", "Input clock"}, {19, 10, "DEV_CPSW0_RGMII_MHZ_250_CLK", "Input clock"}, {19, 11, "DEV_CPSW0_GMII4_MT_CLK", "Input clock"}, {19, 13, "DEV_CPSW0_GMII3_MR_CLK", "Input clock"}, {19, 14, "DEV_CPSW0_SERDES4_RXFCLK", "Input clock"}, {19, 15, "DEV_CPSW0_CPTS_RFT_CLK", "Input muxed clock"}, {19, 16, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {19, 17, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {19, 18, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {19, 19, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {19, 20, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {19, 21, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {19, 22, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {19, 23, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {19, 24, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {19, 25, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {19, 30, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {19, 31, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {19, 32, "DEV_CPSW0_SERDES1_TXCLK", "Output clock"}, {19, 33, "DEV_CPSW0_CPPI_CLK_CLK", "Input clock"}, {19, 34, "DEV_CPSW0_SERDES2_RXCLK", "Input clock"}, {19, 35, "DEV_CPSW0_SERDES1_RXFCLK", "Input clock"}, {19, 36, "DEV_CPSW0_GMII_RFT_CLK", "Input clock"}, {19, 37, "DEV_CPSW0_SERDES1_TXMCLK", "Input clock"}, {19, 38, "DEV_CPSW0_SERDES1_REFCLK", "Input clock"}, {19, 39, "DEV_CPSW0_RMII_MHZ_50_CLK", "Input clock"}, {19, 40, "DEV_CPSW0_GMII4_MR_CLK", "Input clock"}, {19, 41, "DEV_CPSW0_RGMII_MHZ_50_CLK", "Input clock"}, {19, 42, "DEV_CPSW0_SERDES3_TXFCLK", "Input clock"}, {19, 43, "DEV_CPSW0_SERDES3_RXFCLK", "Input clock"}, {19, 45, "DEV_CPSW0_PRE_RGMII2_TCLK", "Output clock"}, {19, 46, "DEV_CPSW0_SERDES2_TXCLK", "Output clock"}, {19, 47, "DEV_CPSW0_SERDES1_RXCLK", "Input clock"}, {19, 48, "DEV_CPSW0_SERDES1_TXFCLK", "Input clock"}, {19, 49, "DEV_CPSW0_RGMII2_RXC_I", "Input clock"}, {19, 50, "DEV_CPSW0_SERDES2_TXFCLK", "Input clock"}, {19, 51, "DEV_CPSW0_PRE_RGMII1_TCLK", "Output clock"}, {19, 52, "DEV_CPSW0_RGMII_MHZ_5_CLK", "Input clock"}, {19, 53, "DEV_CPSW0_GMII2_MT_CLK", "Input clock"}, {19, 54, "DEV_CPSW0_SERDES4_TXMCLK", "Input clock"}, {19, 55, "DEV_CPSW0_SERDES3_TXCLK", "Output clock"}, {19, 56, "DEV_CPSW0_SERDES2_TXMCLK", "Input clock"}, {19, 57, "DEV_CPSW0_GMII1_MR_CLK", "Input clock"}, {19, 58, "DEV_CPSW0_SERDES4_REFCLK", "Input clock"}, {19, 59, "DEV_CPSW0_SERDES3_TXMCLK", "Input clock"}, {19, 60, "DEV_CPSW0_SERDES2_REFCLK", "Input clock"}, {19, 61, "DEV_CPSW0_SERDES3_REFCLK", "Input clock"}, {19, 62, "DEV_CPSW0_SERDES3_RXCLK", "Input clock"}, {19, 63, "DEV_CPSW0_GMII1_MT_CLK", "Input clock"}, {19, 64, "DEV_CPSW0_SERDES2_RXFCLK", "Input clock"}, {19, 66, "DEV_CPSW0_SERDES4_TXCLK", "Output clock"}, {19, 67, "DEV_CPSW0_SERDES4_TXFCLK", "Input clock"}, {26, 0, "DEV_CPSW_TX_RGMII0_IO__RGMII4_TXC__A", "Output clock"}, {26, 1, "DEV_CPSW_TX_RGMII0_IO__RGMII3_TXC__A", "Output clock"}, {26, 2, "DEV_CPSW_TX_RGMII0_IO__RGMII2_TXC__A", "Output clock"}, {26, 3, "DEV_CPSW_TX_RGMII0_IO__RGMII1_TXC__A", "Output clock"}, {26, 4, "DEV_CPSW_TX_RGMII0_PRE_RGMII2_TCLK", "Input clock"}, {26, 5, "DEV_CPSW_TX_RGMII0_PRE_RGMII4_TCLK", "Input clock"}, {26, 6, "DEV_CPSW_TX_RGMII0_PRE_RGMII3_TCLK", "Input clock"}, {26, 7, "DEV_CPSW_TX_RGMII0_PRE_RGMII1_TCLK", "Input clock"}, {20, 0, "DEV_CPT2_AGGR0_VCLK_CLK", "Input clock"}, {21, 0, "DEV_CPT2_AGGR1_VCLK_CLK", "Input clock"}, {23, 0, "DEV_CPT2_AGGR2_VCLK_CLK", "Input clock"}, {25, 0, "DEV_CPT2_AGGR3_VCLK_CLK", "Input clock"}, {30, 0, "DEV_DCC0_DCC_INPUT10_CLK", "Input clock"}, {30, 1, "DEV_DCC0_DCC_INPUT01_CLK", "Input clock"}, {30, 2, "DEV_DCC0_DCC_CLKSRC2_CLK", "Input clock"}, {30, 4, "DEV_DCC0_DCC_CLKSRC0_CLK", "Input clock"}, {30, 5, "DEV_DCC0_VBUS_CLK", "Input clock"}, {30, 6, "DEV_DCC0_DCC_CLKSRC4_CLK", "Input clock"}, {30, 7, "DEV_DCC0_DCC_CLKSRC1_CLK", "Input clock"}, {30, 8, "DEV_DCC0_DCC_CLKSRC3_CLK", "Input clock"}, {30, 9, "DEV_DCC0_DCC_INPUT00_CLK", "Input clock"}, {30, 10, "DEV_DCC0_DCC_CLKSRC5_CLK", "Input clock"}, {30, 11, "DEV_DCC0_DCC_CLKSRC6_CLK", "Input clock"}, {30, 12, "DEV_DCC0_DCC_INPUT02_CLK", "Input clock"}, {31, 0, "DEV_DCC1_DCC_INPUT10_CLK", "Input clock"}, {31, 1, "DEV_DCC1_DCC_INPUT01_CLK", "Input clock"}, {31, 2, "DEV_DCC1_DCC_CLKSRC2_CLK", "Input clock"}, {31, 4, "DEV_DCC1_DCC_CLKSRC0_CLK", "Input clock"}, {31, 5, "DEV_DCC1_VBUS_CLK", "Input clock"}, {31, 6, "DEV_DCC1_DCC_CLKSRC4_CLK", "Input clock"}, {31, 7, "DEV_DCC1_DCC_CLKSRC1_CLK", "Input clock"}, {31, 8, "DEV_DCC1_DCC_CLKSRC3_CLK", "Input clock"}, {31, 9, "DEV_DCC1_DCC_INPUT00_CLK", "Input clock"}, {31, 10, "DEV_DCC1_DCC_CLKSRC5_CLK", "Input clock"}, {31, 11, "DEV_DCC1_DCC_CLKSRC6_CLK", "Input clock"}, {31, 12, "DEV_DCC1_DCC_INPUT02_CLK", "Input clock"}, {32, 0, "DEV_DCC2_DCC_INPUT10_CLK", "Input clock"}, {32, 1, "DEV_DCC2_DCC_INPUT01_CLK", "Input clock"}, {32, 2, "DEV_DCC2_DCC_CLKSRC2_CLK", "Input clock"}, {32, 3, "DEV_DCC2_DCC_CLKSRC7_CLK", "Input clock"}, {32, 4, "DEV_DCC2_DCC_CLKSRC0_CLK", "Input clock"}, {32, 5, "DEV_DCC2_VBUS_CLK", "Input clock"}, {32, 6, "DEV_DCC2_DCC_CLKSRC4_CLK", "Input clock"}, {32, 8, "DEV_DCC2_DCC_CLKSRC3_CLK", "Input clock"}, {32, 9, "DEV_DCC2_DCC_INPUT00_CLK", "Input clock"}, {32, 10, "DEV_DCC2_DCC_CLKSRC5_CLK", "Input clock"}, {32, 11, "DEV_DCC2_DCC_CLKSRC6_CLK", "Input clock"}, {32, 12, "DEV_DCC2_DCC_INPUT02_CLK", "Input clock"}, {33, 0, "DEV_DCC3_DCC_INPUT10_CLK", "Input clock"}, {33, 1, "DEV_DCC3_DCC_INPUT01_CLK", "Input clock"}, {33, 2, "DEV_DCC3_DCC_CLKSRC2_CLK", "Input clock"}, {33, 3, "DEV_DCC3_DCC_CLKSRC7_CLK", "Input clock"}, {33, 4, "DEV_DCC3_DCC_CLKSRC0_CLK", "Input clock"}, {33, 5, "DEV_DCC3_VBUS_CLK", "Input clock"}, {33, 6, "DEV_DCC3_DCC_CLKSRC4_CLK", "Input clock"}, {33, 8, "DEV_DCC3_DCC_CLKSRC3_CLK", "Input clock"}, {33, 9, "DEV_DCC3_DCC_INPUT00_CLK", "Input clock"}, {33, 10, "DEV_DCC3_DCC_CLKSRC5_CLK", "Input clock"}, {33, 11, "DEV_DCC3_DCC_CLKSRC6_CLK", "Input clock"}, {33, 12, "DEV_DCC3_DCC_INPUT02_CLK", "Input clock"}, {34, 0, "DEV_DCC4_DCC_INPUT10_CLK", "Input clock"}, {34, 1, "DEV_DCC4_DCC_INPUT01_CLK", "Input clock"}, {34, 2, "DEV_DCC4_DCC_CLKSRC2_CLK", "Input clock"}, {34, 3, "DEV_DCC4_DCC_CLKSRC7_CLK", "Input clock"}, {34, 4, "DEV_DCC4_DCC_CLKSRC0_CLK", "Input clock"}, {34, 5, "DEV_DCC4_VBUS_CLK", "Input clock"}, {34, 6, "DEV_DCC4_DCC_CLKSRC4_CLK", "Input clock"}, {34, 7, "DEV_DCC4_DCC_CLKSRC1_CLK", "Input clock"}, {34, 8, "DEV_DCC4_DCC_CLKSRC3_CLK", "Input clock"}, {34, 9, "DEV_DCC4_DCC_INPUT00_CLK", "Input clock"}, {34, 10, "DEV_DCC4_DCC_CLKSRC5_CLK", "Input clock"}, {34, 11, "DEV_DCC4_DCC_CLKSRC6_CLK", "Input clock"}, {34, 12, "DEV_DCC4_DCC_INPUT02_CLK", "Input clock"}, {36, 0, "DEV_DCC5_DCC_INPUT10_CLK", "Input clock"}, {36, 1, "DEV_DCC5_DCC_INPUT01_CLK", "Input clock"}, {36, 4, "DEV_DCC5_DCC_CLKSRC0_CLK", "Input clock"}, {36, 5, "DEV_DCC5_VBUS_CLK", "Input clock"}, {36, 6, "DEV_DCC5_DCC_CLKSRC4_CLK", "Input clock"}, {36, 7, "DEV_DCC5_DCC_CLKSRC1_CLK", "Input clock"}, {36, 9, "DEV_DCC5_DCC_INPUT00_CLK", "Input clock"}, {36, 11, "DEV_DCC5_DCC_CLKSRC6_CLK", "Input clock"}, {36, 12, "DEV_DCC5_DCC_INPUT02_CLK", "Input clock"}, {37, 0, "DEV_DCC6_DCC_INPUT10_CLK", "Input clock"}, {37, 1, "DEV_DCC6_DCC_INPUT01_CLK", "Input clock"}, {37, 2, "DEV_DCC6_DCC_CLKSRC2_CLK", "Input clock"}, {37, 3, "DEV_DCC6_DCC_CLKSRC7_CLK", "Input clock"}, {37, 4, "DEV_DCC6_DCC_CLKSRC0_CLK", "Input clock"}, {37, 5, "DEV_DCC6_VBUS_CLK", "Input clock"}, {37, 6, "DEV_DCC6_DCC_CLKSRC4_CLK", "Input clock"}, {37, 7, "DEV_DCC6_DCC_CLKSRC1_CLK", "Input clock"}, {37, 8, "DEV_DCC6_DCC_CLKSRC3_CLK", "Input clock"}, {37, 9, "DEV_DCC6_DCC_INPUT00_CLK", "Input clock"}, {37, 10, "DEV_DCC6_DCC_CLKSRC5_CLK", "Input clock"}, {37, 11, "DEV_DCC6_DCC_CLKSRC6_CLK", "Input clock"}, {37, 12, "DEV_DCC6_DCC_INPUT02_CLK", "Input clock"}, {8, 0, "DEV_DDR0_PLL_CTRL_CLK", "Input clock"}, {8, 5, "DEV_DDR0_DDRSS_DDR_PLL_CLK", "Input clock"}, {304, 5, "DEV_DEBUGSS_WRAP0_TREXPT_CLK", "Input clock"}, {304, 9, "DEV_DEBUGSS_WRAP0_CORE_CLK", "Input clock"}, {304, 25, "DEV_DEBUGSS_WRAP0_JTAG_TCK", "Input clock"}, {304, 34, "DEV_DEBUGSS_WRAP0_ATB_CLK", "Input clock"}, {304, 49, "DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK", "Output clock"}, {80, 0, "DEV_ECAP0_VBUS_CLK", "Input clock"}, {81, 0, "DEV_ECAP1_VBUS_CLK", "Input clock"}, {82, 0, "DEV_ECAP2_VBUS_CLK", "Input clock"}, {83, 0, "DEV_EHRPWM0_VBUSP_CLK", "Input clock"}, {84, 0, "DEV_EHRPWM1_VBUSP_CLK", "Input clock"}, {85, 0, "DEV_EHRPWM2_VBUSP_CLK", "Input clock"}, {86, 0, "DEV_EHRPWM3_VBUSP_CLK", "Input clock"}, {87, 0, "DEV_EHRPWM4_VBUSP_CLK", "Input clock"}, {88, 0, "DEV_EHRPWM5_VBUSP_CLK", "Input clock"}, {89, 0, "DEV_ELM0_VBUSP_CLK", "Input clock"}, {94, 0, "DEV_EQEP0_VBUS_CLK", "Input clock"}, {95, 0, "DEV_EQEP1_VBUS_CLK", "Input clock"}, {96, 0, "DEV_EQEP2_VBUS_CLK", "Input clock"}, {97, 0, "DEV_ESM0_CLK", "Input clock"}, {105, 0, "DEV_GPIO0_MMR_CLK", "Input clock"}, {107, 0, "DEV_GPIO2_MMR_CLK", "Input clock"}, {109, 0, "DEV_GPIO4_MMR_CLK", "Input clock"}, {111, 0, "DEV_GPIO6_MMR_CLK", "Input clock"}, {131, 0, "DEV_GPIOMUX_INTRTR0_INTR_CLK", "Input clock"}, {115, 0, "DEV_GPMC0_FUNC_CLK", "Input muxed clock"}, {115, 1, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_GPMC0_FUNC_CLK"}, {115, 2, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK6", "Parent input clock option to DEV_GPMC0_FUNC_CLK"}, {115, 3, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK4", "Parent input clock option to DEV_GPMC0_FUNC_CLK"}, {115, 4, "DEV_GPMC0_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_GPMC0_FUNC_CLK"}, {115, 5, "DEV_GPMC0_VBUSP_CLK", "Input clock"}, {115, 6, "DEV_GPMC0_PO_GPMC_DEV_CLK", "Output clock"}, {115, 7, "DEV_GPMC0_PI_GPMC_RET_CLK", "Input clock"}, {61, 0, "DEV_GTC0_VBUSP_CLK", "Input clock"}, {61, 1, "DEV_GTC0_GTC_CLK", "Input muxed clock"}, {61, 2, "DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 3, "DEV_GTC0_GTC_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 4, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 5, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 6, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 7, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 8, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 9, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 10, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 11, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 16, "DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 17, "DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {187, 0, "DEV_I2C0_PISCL", "Input clock"}, {187, 1, "DEV_I2C0_PISYS_CLK", "Input clock"}, {187, 2, "DEV_I2C0_CLK", "Input clock"}, {187, 3, "DEV_I2C0_PORSCL", "Output clock"}, {188, 0, "DEV_I2C1_PISCL", "Input clock"}, {188, 1, "DEV_I2C1_PISYS_CLK", "Input clock"}, {188, 2, "DEV_I2C1_CLK", "Input clock"}, {188, 3, "DEV_I2C1_PORSCL", "Output clock"}, {189, 0, "DEV_I2C2_PISCL", "Input clock"}, {189, 1, "DEV_I2C2_PISYS_CLK", "Input clock"}, {189, 2, "DEV_I2C2_CLK", "Input clock"}, {189, 3, "DEV_I2C2_PORSCL", "Output clock"}, {190, 0, "DEV_I2C3_PISCL", "Input clock"}, {190, 1, "DEV_I2C3_PISYS_CLK", "Input clock"}, {190, 2, "DEV_I2C3_CLK", "Input clock"}, {190, 3, "DEV_I2C3_PORSCL", "Output clock"}, {191, 0, "DEV_I2C4_PISCL", "Input clock"}, {191, 1, "DEV_I2C4_PISYS_CLK", "Input clock"}, {191, 2, "DEV_I2C4_CLK", "Input clock"}, {191, 3, "DEV_I2C4_PORSCL", "Output clock"}, {192, 0, "DEV_I2C5_PISCL", "Input clock"}, {192, 1, "DEV_I2C5_PISYS_CLK", "Input clock"}, {192, 2, "DEV_I2C5_CLK", "Input clock"}, {192, 3, "DEV_I2C5_PORSCL", "Output clock"}, {193, 0, "DEV_I2C6_PISCL", "Input clock"}, {193, 1, "DEV_I2C6_PISYS_CLK", "Input clock"}, {193, 2, "DEV_I2C6_CLK", "Input clock"}, {193, 3, "DEV_I2C6_PORSCL", "Output clock"}, {116, 0, "DEV_I3C0_I3C_SCL_DI", "Input clock"}, {116, 1, "DEV_I3C0_I3C_SCL_DO", "Output clock"}, {116, 2, "DEV_I3C0_I3C_PCLK_CLK", "Input clock"}, {116, 4, "DEV_I3C0_I3C_SCLK_CLK", "Input clock"}, {127, 0, "DEV_LED0_LED_CLK", "Input clock"}, {127, 1, "DEV_LED0_VBUS_CLK", "Input clock"}, {156, 0, "DEV_MCAN0_MCANSS_HCLK_CLK", "Input clock"}, {156, 2, "DEV_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"}, {156, 3, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, {156, 4, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, {156, 5, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, {156, 6, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, {158, 0, "DEV_MCAN1_MCANSS_HCLK_CLK", "Input clock"}, {158, 2, "DEV_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"}, {158, 3, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, {158, 4, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, {158, 5, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, {158, 6, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, {168, 0, "DEV_MCAN10_MCANSS_HCLK_CLK", "Input clock"}, {168, 2, "DEV_MCAN10_MCANSS_CCLK_CLK", "Input muxed clock"}, {168, 3, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"}, {168, 4, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"}, {168, 5, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"}, {168, 6, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"}, {169, 0, "DEV_MCAN11_MCANSS_HCLK_CLK", "Input clock"}, {169, 2, "DEV_MCAN11_MCANSS_CCLK_CLK", "Input muxed clock"}, {169, 3, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"}, {169, 4, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"}, {169, 5, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"}, {169, 6, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"}, {170, 0, "DEV_MCAN12_MCANSS_HCLK_CLK", "Input clock"}, {170, 2, "DEV_MCAN12_MCANSS_CCLK_CLK", "Input muxed clock"}, {170, 3, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"}, {170, 4, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"}, {170, 5, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"}, {170, 6, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"}, {171, 0, "DEV_MCAN13_MCANSS_HCLK_CLK", "Input clock"}, {171, 2, "DEV_MCAN13_MCANSS_CCLK_CLK", "Input muxed clock"}, {171, 3, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"}, {171, 4, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"}, {171, 5, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"}, {171, 6, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"}, {150, 0, "DEV_MCAN14_MCANSS_HCLK_CLK", "Input clock"}, {150, 2, "DEV_MCAN14_MCANSS_CCLK_CLK", "Input muxed clock"}, {150, 3, "DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK"}, {150, 4, "DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK"}, {150, 5, "DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK"}, {150, 6, "DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK"}, {151, 0, "DEV_MCAN15_MCANSS_HCLK_CLK", "Input clock"}, {151, 2, "DEV_MCAN15_MCANSS_CCLK_CLK", "Input muxed clock"}, {151, 3, "DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK"}, {151, 4, "DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK"}, {151, 5, "DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK"}, {151, 6, "DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK"}, {152, 0, "DEV_MCAN16_MCANSS_HCLK_CLK", "Input clock"}, {152, 2, "DEV_MCAN16_MCANSS_CCLK_CLK", "Input muxed clock"}, {152, 3, "DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK"}, {152, 4, "DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK"}, {152, 5, "DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK"}, {152, 6, "DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK"}, {153, 0, "DEV_MCAN17_MCANSS_HCLK_CLK", "Input clock"}, {153, 2, "DEV_MCAN17_MCANSS_CCLK_CLK", "Input muxed clock"}, {153, 3, "DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK"}, {153, 4, "DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK"}, {153, 5, "DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK"}, {153, 6, "DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK"}, {160, 0, "DEV_MCAN2_MCANSS_HCLK_CLK", "Input clock"}, {160, 2, "DEV_MCAN2_MCANSS_CCLK_CLK", "Input muxed clock"}, {160, 3, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"}, {160, 4, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"}, {160, 5, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"}, {160, 6, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"}, {161, 0, "DEV_MCAN3_MCANSS_HCLK_CLK", "Input clock"}, {161, 2, "DEV_MCAN3_MCANSS_CCLK_CLK", "Input muxed clock"}, {161, 3, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"}, {161, 4, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"}, {161, 5, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"}, {161, 6, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"}, {162, 0, "DEV_MCAN4_MCANSS_HCLK_CLK", "Input clock"}, {162, 2, "DEV_MCAN4_MCANSS_CCLK_CLK", "Input muxed clock"}, {162, 3, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"}, {162, 4, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"}, {162, 5, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"}, {162, 6, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"}, {163, 0, "DEV_MCAN5_MCANSS_HCLK_CLK", "Input clock"}, {163, 2, "DEV_MCAN5_MCANSS_CCLK_CLK", "Input muxed clock"}, {163, 3, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"}, {163, 4, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"}, {163, 5, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"}, {163, 6, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"}, {164, 0, "DEV_MCAN6_MCANSS_HCLK_CLK", "Input clock"}, {164, 2, "DEV_MCAN6_MCANSS_CCLK_CLK", "Input muxed clock"}, {164, 3, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"}, {164, 4, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"}, {164, 5, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"}, {164, 6, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"}, {165, 0, "DEV_MCAN7_MCANSS_HCLK_CLK", "Input clock"}, {165, 2, "DEV_MCAN7_MCANSS_CCLK_CLK", "Input muxed clock"}, {165, 3, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"}, {165, 4, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"}, {165, 5, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"}, {165, 6, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"}, {166, 0, "DEV_MCAN8_MCANSS_HCLK_CLK", "Input clock"}, {166, 2, "DEV_MCAN8_MCANSS_CCLK_CLK", "Input muxed clock"}, {166, 3, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"}, {166, 4, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"}, {166, 5, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"}, {166, 6, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"}, {167, 0, "DEV_MCAN9_MCANSS_HCLK_CLK", "Input clock"}, {167, 2, "DEV_MCAN9_MCANSS_CCLK_CLK", "Input muxed clock"}, {167, 3, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"}, {167, 4, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"}, {167, 5, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"}, {167, 6, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"}, {174, 0, "DEV_MCASP0_MCASP_AHCLKX_POUT", "Output clock"}, {174, 2, "DEV_MCASP0_MCASP_AHCLKR_PIN", "Input muxed clock"}, {174, 3, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {174, 4, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {174, 5, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {174, 6, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {174, 11, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {174, 12, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {174, 13, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {174, 14, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {174, 19, "DEV_MCASP0_MCASP_ACLKR_PIN", "Input clock"}, {174, 21, "DEV_MCASP0_MCASP_AHCLKX_PIN", "Input muxed clock"}, {174, 22, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {174, 23, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {174, 24, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {174, 25, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {174, 30, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {174, 31, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {174, 32, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {174, 33, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {174, 38, "DEV_MCASP0_MCASP_AHCLKR_POUT", "Output clock"}, {174, 39, "DEV_MCASP0_MCASP_ACLKX_PIN", "Input clock"}, {174, 40, "DEV_MCASP0_AUX_CLK", "Input muxed clock"}, {174, 41, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, {174, 42, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, {174, 45, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, {174, 46, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, {174, 47, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, {174, 48, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, {174, 49, "DEV_MCASP0_VBUSP_CLK", "Input clock"}, {174, 50, "DEV_MCASP0_MCASP_ACLKR_POUT", "Output clock"}, {174, 51, "DEV_MCASP0_MCASP_ACLKX_POUT", "Output clock"}, {175, 0, "DEV_MCASP1_MCASP_AHCLKX_POUT", "Output clock"}, {175, 2, "DEV_MCASP1_MCASP_AHCLKR_PIN", "Input muxed clock"}, {175, 3, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {175, 4, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {175, 5, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {175, 6, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {175, 11, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {175, 12, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {175, 13, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {175, 14, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {175, 19, "DEV_MCASP1_MCASP_ACLKR_PIN", "Input clock"}, {175, 21, "DEV_MCASP1_MCASP_AHCLKX_PIN", "Input muxed clock"}, {175, 22, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {175, 23, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {175, 24, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {175, 25, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {175, 30, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {175, 31, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {175, 32, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {175, 33, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {175, 38, "DEV_MCASP1_MCASP_AHCLKR_POUT", "Output clock"}, {175, 39, "DEV_MCASP1_MCASP_ACLKX_PIN", "Input clock"}, {175, 40, "DEV_MCASP1_AUX_CLK", "Input muxed clock"}, {175, 41, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, {175, 42, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, {175, 45, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, {175, 46, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, {175, 47, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, {175, 48, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, {175, 49, "DEV_MCASP1_VBUSP_CLK", "Input clock"}, {175, 50, "DEV_MCASP1_MCASP_ACLKR_POUT", "Output clock"}, {175, 51, "DEV_MCASP1_MCASP_ACLKX_POUT", "Output clock"}, {176, 0, "DEV_MCASP2_MCASP_AHCLKX_POUT", "Output clock"}, {176, 2, "DEV_MCASP2_MCASP_AHCLKR_PIN", "Input muxed clock"}, {176, 3, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {176, 4, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {176, 5, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {176, 6, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {176, 11, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {176, 12, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {176, 13, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {176, 14, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {176, 19, "DEV_MCASP2_MCASP_ACLKR_PIN", "Input clock"}, {176, 21, "DEV_MCASP2_MCASP_AHCLKX_PIN", "Input muxed clock"}, {176, 22, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {176, 23, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {176, 24, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {176, 25, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {176, 30, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {176, 31, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {176, 32, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {176, 33, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {176, 38, "DEV_MCASP2_MCASP_AHCLKR_POUT", "Output clock"}, {176, 39, "DEV_MCASP2_MCASP_ACLKX_PIN", "Input clock"}, {176, 40, "DEV_MCASP2_AUX_CLK", "Input muxed clock"}, {176, 41, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, {176, 42, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, {176, 45, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, {176, 46, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, {176, 47, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, {176, 48, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, {176, 49, "DEV_MCASP2_VBUSP_CLK", "Input clock"}, {176, 50, "DEV_MCASP2_MCASP_ACLKR_POUT", "Output clock"}, {176, 51, "DEV_MCASP2_MCASP_ACLKX_POUT", "Output clock"}, {266, 3, "DEV_MCSPI0_VBUSP_CLK", "Input clock"}, {266, 4, "DEV_MCSPI0_CLKSPIREF_CLK", "Input clock"}, {266, 5, "DEV_MCSPI0_IO_CLKSPIO_CLK", "Output clock"}, {267, 3, "DEV_MCSPI1_VBUSP_CLK", "Input clock"}, {267, 4, "DEV_MCSPI1_CLKSPIREF_CLK", "Input clock"}, {267, 5, "DEV_MCSPI1_IO_CLKSPIO_CLK", "Output clock"}, {268, 3, "DEV_MCSPI2_VBUSP_CLK", "Input clock"}, {268, 4, "DEV_MCSPI2_CLKSPIREF_CLK", "Input clock"}, {268, 5, "DEV_MCSPI2_IO_CLKSPIO_CLK", "Output clock"}, {269, 0, "DEV_MCSPI3_IO_CLKSPII_CLK", "Input muxed clock"}, {269, 1, "DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI3_IO_CLKSPII_CLK"}, {269, 3, "DEV_MCSPI3_VBUSP_CLK", "Input clock"}, {269, 4, "DEV_MCSPI3_CLKSPIREF_CLK", "Input clock"}, {269, 5, "DEV_MCSPI3_IO_CLKSPIO_CLK", "Output clock"}, {270, 0, "DEV_MCSPI4_IO_CLKSPII_CLK", "Input clock"}, {270, 1, "DEV_MCSPI4_VBUSP_CLK", "Input clock"}, {270, 2, "DEV_MCSPI4_CLKSPIREF_CLK", "Input clock"}, {270, 3, "DEV_MCSPI4_IO_CLKSPIO_CLK", "Output clock"}, {271, 3, "DEV_MCSPI5_VBUSP_CLK", "Input clock"}, {271, 4, "DEV_MCSPI5_CLKSPIREF_CLK", "Input clock"}, {271, 5, "DEV_MCSPI5_IO_CLKSPIO_CLK", "Output clock"}, {272, 3, "DEV_MCSPI6_VBUSP_CLK", "Input clock"}, {272, 4, "DEV_MCSPI6_CLKSPIREF_CLK", "Input clock"}, {272, 5, "DEV_MCSPI6_IO_CLKSPIO_CLK", "Output clock"}, {273, 3, "DEV_MCSPI7_VBUSP_CLK", "Input clock"}, {273, 4, "DEV_MCSPI7_CLKSPIREF_CLK", "Input clock"}, {273, 5, "DEV_MCSPI7_IO_CLKSPIO_CLK", "Output clock"}, {0, 0, "DEV_MCU_ADC0_SYS_CLK", "Input clock"}, {0, 1, "DEV_MCU_ADC0_ADC_CLK", "Input muxed clock"}, {0, 2, "DEV_MCU_ADC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_ADC0_ADC_CLK"}, {0, 3, "DEV_MCU_ADC0_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC0_ADC_CLK"}, {0, 4, "DEV_MCU_ADC0_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC0_ADC_CLK"}, {0, 5, "DEV_MCU_ADC0_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC0_ADC_CLK"}, {0, 6, "DEV_MCU_ADC0_VBUS_CLK", "Input clock"}, {1, 0, "DEV_MCU_ADC1_SYS_CLK", "Input clock"}, {1, 1, "DEV_MCU_ADC1_ADC_CLK", "Input muxed clock"}, {1, 2, "DEV_MCU_ADC1_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_ADC1_ADC_CLK"}, {1, 3, "DEV_MCU_ADC1_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC1_ADC_CLK"}, {1, 4, "DEV_MCU_ADC1_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC1_ADC_CLK"}, {1, 5, "DEV_MCU_ADC1_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC1_ADC_CLK"}, {1, 6, "DEV_MCU_ADC1_VBUS_CLK", "Input clock"}, {18, 0, "DEV_MCU_CPSW0_MDIO_MDCLK_O", "Output clock"}, {18, 2, "DEV_MCU_CPSW0_CPTS_RFT_CLK", "Input muxed clock"}, {18, 3, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {18, 4, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {18, 5, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {18, 6, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {18, 7, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {18, 8, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {18, 9, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {18, 10, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {18, 11, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {18, 12, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {18, 17, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {18, 18, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {18, 20, "DEV_MCU_CPSW0_GMII1_MR_CLK", "Input clock"}, {18, 21, "DEV_MCU_CPSW0_CPPI_CLK_CLK", "Input clock"}, {18, 22, "DEV_MCU_CPSW0_CPTS_GENF0", "Output clock"}, {18, 24, "DEV_MCU_CPSW0_GMII_RFT_CLK", "Input clock"}, {18, 27, "DEV_MCU_CPSW0_GMII1_MT_CLK", "Input clock"}, {18, 28, "DEV_MCU_CPSW0_RGMII1_TXC_O", "Output clock"}, {18, 29, "DEV_MCU_CPSW0_RMII_MHZ_50_CLK", "Input clock"}, {18, 30, "DEV_MCU_CPSW0_RGMII_MHZ_5_CLK", "Input clock"}, {18, 31, "DEV_MCU_CPSW0_RGMII1_RXC_I", "Input clock"}, {18, 32, "DEV_MCU_CPSW0_RGMII_MHZ_250_CLK", "Input clock"}, {18, 33, "DEV_MCU_CPSW0_RGMII_MHZ_50_CLK", "Input clock"}, {24, 0, "DEV_MCU_CPT2_AGGR0_VCLK_CLK", "Input clock"}, {44, 0, "DEV_MCU_DCC0_DCC_INPUT10_CLK", "Input clock"}, {44, 1, "DEV_MCU_DCC0_DCC_INPUT01_CLK", "Input clock"}, {44, 2, "DEV_MCU_DCC0_DCC_CLKSRC2_CLK", "Input clock"}, {44, 3, "DEV_MCU_DCC0_DCC_CLKSRC7_CLK", "Input clock"}, {44, 4, "DEV_MCU_DCC0_DCC_CLKSRC0_CLK", "Input clock"}, {44, 5, "DEV_MCU_DCC0_VBUS_CLK", "Input clock"}, {44, 6, "DEV_MCU_DCC0_DCC_CLKSRC4_CLK", "Input clock"}, {44, 7, "DEV_MCU_DCC0_DCC_CLKSRC1_CLK", "Input clock"}, {44, 8, "DEV_MCU_DCC0_DCC_CLKSRC3_CLK", "Input clock"}, {44, 9, "DEV_MCU_DCC0_DCC_INPUT00_CLK", "Input clock"}, {44, 10, "DEV_MCU_DCC0_DCC_CLKSRC5_CLK", "Input clock"}, {44, 11, "DEV_MCU_DCC0_DCC_CLKSRC6_CLK", "Input clock"}, {44, 12, "DEV_MCU_DCC0_DCC_INPUT02_CLK", "Input clock"}, {45, 0, "DEV_MCU_DCC1_DCC_INPUT10_CLK", "Input clock"}, {45, 1, "DEV_MCU_DCC1_DCC_INPUT01_CLK", "Input clock"}, {45, 2, "DEV_MCU_DCC1_DCC_CLKSRC2_CLK", "Input clock"}, {45, 3, "DEV_MCU_DCC1_DCC_CLKSRC7_CLK", "Input clock"}, {45, 4, "DEV_MCU_DCC1_DCC_CLKSRC0_CLK", "Input clock"}, {45, 5, "DEV_MCU_DCC1_VBUS_CLK", "Input clock"}, {45, 6, "DEV_MCU_DCC1_DCC_CLKSRC4_CLK", "Input clock"}, {45, 7, "DEV_MCU_DCC1_DCC_CLKSRC1_CLK", "Input clock"}, {45, 8, "DEV_MCU_DCC1_DCC_CLKSRC3_CLK", "Input clock"}, {45, 9, "DEV_MCU_DCC1_DCC_INPUT00_CLK", "Input clock"}, {45, 10, "DEV_MCU_DCC1_DCC_CLKSRC5_CLK", "Input clock"}, {45, 11, "DEV_MCU_DCC1_DCC_CLKSRC6_CLK", "Input clock"}, {45, 12, "DEV_MCU_DCC1_DCC_INPUT02_CLK", "Input clock"}, {46, 0, "DEV_MCU_DCC2_DCC_INPUT10_CLK", "Input clock"}, {46, 1, "DEV_MCU_DCC2_DCC_INPUT01_CLK", "Input clock"}, {46, 3, "DEV_MCU_DCC2_DCC_CLKSRC7_CLK", "Input clock"}, {46, 4, "DEV_MCU_DCC2_DCC_CLKSRC0_CLK", "Input clock"}, {46, 5, "DEV_MCU_DCC2_VBUS_CLK", "Input clock"}, {46, 7, "DEV_MCU_DCC2_DCC_CLKSRC1_CLK", "Input clock"}, {46, 8, "DEV_MCU_DCC2_DCC_CLKSRC3_CLK", "Input clock"}, {46, 9, "DEV_MCU_DCC2_DCC_INPUT00_CLK", "Input clock"}, {46, 11, "DEV_MCU_DCC2_DCC_CLKSRC6_CLK", "Input clock"}, {46, 12, "DEV_MCU_DCC2_DCC_INPUT02_CLK", "Input clock"}, {98, 0, "DEV_MCU_ESM0_CLK", "Input clock"}, {101, 0, "DEV_MCU_FSS0_FSAS_0_GCLK", "Input clock"}, {102, 0, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_N", "Output clock"}, {102, 1, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_INV_CLK", "Input clock"}, {102, 2, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_INV_CLK", "Input clock"}, {102, 4, "DEV_MCU_FSS0_HYPERBUS1P0_0_CBA_CLK", "Input clock"}, {102, 5, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_CLK", "Input clock"}, {102, 7, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_CLK", "Input clock"}, {102, 10, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_P", "Output clock"}, {103, 0, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK", "Input muxed clock"}, {103, 1, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK"}, {103, 2, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK"}, {103, 3, "DEV_MCU_FSS0_OSPI_0_OSPI_HCLK_CLK", "Input clock"}, {103, 4, "DEV_MCU_FSS0_OSPI_0_OSPI_DQS_CLK", "Input clock"}, {103, 5, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK", "Input muxed clock"}, {103, 6, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI0_DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK"}, {103, 7, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_OSPI_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK"}, {103, 8, "DEV_MCU_FSS0_OSPI_0_OSPI_PCLK_CLK", "Input clock"}, {103, 9, "DEV_MCU_FSS0_OSPI_0_OSPI_OCLK_CLK", "Output clock"}, {104, 0, "DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK", "Input clock"}, {104, 1, "DEV_MCU_FSS0_OSPI_1_OSPI_HCLK_CLK", "Input clock"}, {104, 7, "DEV_MCU_FSS0_OSPI_1_OSPI_PCLK_CLK", "Input clock"}, {194, 0, "DEV_MCU_I2C0_PISCL", "Input clock"}, {194, 1, "DEV_MCU_I2C0_PISYS_CLK", "Input clock"}, {194, 2, "DEV_MCU_I2C0_CLK", "Input clock"}, {195, 0, "DEV_MCU_I2C1_PISCL", "Input clock"}, {195, 1, "DEV_MCU_I2C1_PISYS_CLK", "Input clock"}, {195, 2, "DEV_MCU_I2C1_CLK", "Input clock"}, {195, 3, "DEV_MCU_I2C1_PORSCL", "Output clock"}, {117, 0, "DEV_MCU_I3C0_I3C_SCL_DI", "Input clock"}, {117, 1, "DEV_MCU_I3C0_I3C_SCL_DO", "Output clock"}, {117, 2, "DEV_MCU_I3C0_I3C_PCLK_CLK", "Input clock"}, {117, 4, "DEV_MCU_I3C0_I3C_SCLK_CLK", "Input clock"}, {118, 2, "DEV_MCU_I3C1_I3C_PCLK_CLK", "Input clock"}, {118, 4, "DEV_MCU_I3C1_I3C_SCLK_CLK", "Input clock"}, {172, 0, "DEV_MCU_MCAN0_MCANSS_HCLK_CLK", "Input clock"}, {172, 2, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"}, {172, 3, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, {172, 4, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, {172, 5, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, {172, 6, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, {173, 0, "DEV_MCU_MCAN1_MCANSS_HCLK_CLK", "Input clock"}, {173, 2, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"}, {173, 3, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, {173, 4, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, {173, 5, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, {173, 6, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, {274, 3, "DEV_MCU_MCSPI0_VBUSP_CLK", "Input clock"}, {274, 4, "DEV_MCU_MCSPI0_CLKSPIREF_CLK", "Input clock"}, {274, 5, "DEV_MCU_MCSPI0_IO_CLKSPIO_CLK", "Output clock"}, {275, 0, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK", "Input muxed clock"}, {275, 1, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK"}, {275, 3, "DEV_MCU_MCSPI1_VBUSP_CLK", "Input clock"}, {275, 4, "DEV_MCU_MCSPI1_CLKSPIREF_CLK", "Input clock"}, {275, 5, "DEV_MCU_MCSPI1_IO_CLKSPIO_CLK", "Output clock"}, {276, 0, "DEV_MCU_MCSPI2_IO_CLKSPII_CLK", "Input clock"}, {276, 1, "DEV_MCU_MCSPI2_VBUSP_CLK", "Input clock"}, {276, 2, "DEV_MCU_MCSPI2_CLKSPIREF_CLK", "Input clock"}, {276, 3, "DEV_MCU_MCSPI2_IO_CLKSPIO_CLK", "Output clock"}, {237, 0, "DEV_MCU_NAVSS0_INTR_0_INTR_CLK", "Input clock"}, {238, 0, "DEV_MCU_NAVSS0_MCRC_0_CLK", "Input clock"}, {302, 0, "DEV_MCU_NAVSS0_MODSS_VD2CLK", "Input clock"}, {234, 0, "DEV_MCU_NAVSS0_PROXY0_CLK_CLK", "Input clock"}, {235, 0, "DEV_MCU_NAVSS0_RINGACC0_SYS_CLK", "Input clock"}, {236, 0, "DEV_MCU_NAVSS0_UDMAP_0_SYS_CLK", "Input clock"}, {303, 0, "DEV_MCU_NAVSS0_UDMASS_VD2CLK", "Input clock"}, {233, 0, "DEV_MCU_NAVSS0_UDMASS_INTA_0_SYS_CLK", "Input clock"}, {142, 1, "DEV_MCU_PBIST0_CLK7_CLK", "Input clock"}, {142, 2, "DEV_MCU_PBIST0_CLK3_CLK", "Input clock"}, {142, 3, "DEV_MCU_PBIST0_CLK5_CLK", "Input clock"}, {142, 4, "DEV_MCU_PBIST0_CLK1_CLK", "Input clock"}, {142, 5, "DEV_MCU_PBIST0_CLK8_CLK", "Input clock"}, {142, 6, "DEV_MCU_PBIST0_CLK6_CLK", "Input clock"}, {142, 8, "DEV_MCU_PBIST0_CLK4_CLK", "Input clock"}, {142, 9, "DEV_MCU_PBIST0_CLK2_CLK", "Input clock"}, {143, 1, "DEV_MCU_PBIST1_CLK7_CLK", "Input clock"}, {143, 2, "DEV_MCU_PBIST1_CLK3_CLK", "Input clock"}, {143, 3, "DEV_MCU_PBIST1_CLK5_CLK", "Input clock"}, {143, 4, "DEV_MCU_PBIST1_CLK1_CLK", "Input clock"}, {143, 5, "DEV_MCU_PBIST1_CLK8_CLK", "Input clock"}, {143, 6, "DEV_MCU_PBIST1_CLK6_CLK", "Input clock"}, {143, 8, "DEV_MCU_PBIST1_CLK4_CLK", "Input clock"}, {143, 9, "DEV_MCU_PBIST1_CLK2_CLK", "Input clock"}, {144, 1, "DEV_MCU_PBIST2_CLK7_CLK", "Input clock"}, {144, 2, "DEV_MCU_PBIST2_CLK3_CLK", "Input clock"}, {144, 3, "DEV_MCU_PBIST2_CLK5_CLK", "Input clock"}, {144, 4, "DEV_MCU_PBIST2_CLK1_CLK", "Input clock"}, {144, 5, "DEV_MCU_PBIST2_CLK8_CLK", "Input clock"}, {144, 6, "DEV_MCU_PBIST2_CLK6_CLK", "Input clock"}, {144, 8, "DEV_MCU_PBIST2_CLK4_CLK", "Input clock"}, {144, 9, "DEV_MCU_PBIST2_CLK2_CLK", "Input clock"}, {250, 0, "DEV_MCU_R5FSS0_CORE0_CPU_CLK", "Input muxed clock"}, {250, 1, "DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK"}, {250, 2, "DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3", "Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK"}, {250, 3, "DEV_MCU_R5FSS0_CORE0_INTERFACE_CLK", "Input clock"}, {250, 4, "DEV_MCU_R5FSS0_CORE0_INTERFACE_PHASE", "Input clock"}, {251, 0, "DEV_MCU_R5FSS0_CORE1_CPU_CLK", "Input muxed clock"}, {251, 1, "DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK"}, {251, 2, "DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3", "Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK"}, {251, 3, "DEV_MCU_R5FSS0_CORE1_INTERFACE_CLK", "Input clock"}, {251, 4, "DEV_MCU_R5FSS0_CORE1_INTERFACE_PHASE", "Input clock"}, {262, 0, "DEV_MCU_RTI0_VBUSP_CLK", "Input clock"}, {262, 1, "DEV_MCU_RTI0_RTI_CLK", "Input muxed clock"}, {262, 2, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, {262, 3, "DEV_MCU_RTI0_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, {262, 4, "DEV_MCU_RTI0_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, {262, 5, "DEV_MCU_RTI0_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, {263, 0, "DEV_MCU_RTI1_VBUSP_CLK", "Input clock"}, {263, 1, "DEV_MCU_RTI1_RTI_CLK", "Input muxed clock"}, {263, 2, "DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"}, {263, 3, "DEV_MCU_RTI1_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"}, {263, 4, "DEV_MCU_RTI1_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"}, {263, 5, "DEV_MCU_RTI1_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"}, {265, 0, "DEV_MCU_SA2_UL0_X2_CLK", "Input clock"}, {265, 1, "DEV_MCU_SA2_UL0_PKA_IN_CLK", "Input clock"}, {265, 2, "DEV_MCU_SA2_UL0_X1_CLK", "Input clock"}, {35, 0, "DEV_MCU_TIMER0_TIMER_HCLK_CLK", "Input clock"}, {35, 1, "DEV_MCU_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"}, {35, 2, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 3, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 4, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 5, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 6, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 7, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 8, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 9, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 11, "DEV_MCU_TIMER0_TIMER_PWM", "Output clock"}, {71, 0, "DEV_MCU_TIMER1_TIMER_HCLK_CLK", "Input clock"}, {71, 1, "DEV_MCU_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"}, {71, 2, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT1", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, {71, 3, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, {308, 0, "DEV_MCU_TIMER1_CLKSEL_VD_CLK", "Input muxed clock"}, {308, 1, "DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK"}, {308, 2, "DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK"}, {308, 3, "DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK"}, {308, 4, "DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK"}, {308, 5, "DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK"}, {308, 6, "DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK"}, {308, 7, "DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK"}, {308, 8, "DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK"}, {72, 0, "DEV_MCU_TIMER2_TIMER_HCLK_CLK", "Input clock"}, {72, 1, "DEV_MCU_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"}, {72, 2, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {72, 3, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {72, 4, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {72, 5, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {72, 6, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {72, 7, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {72, 8, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {72, 9, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {72, 11, "DEV_MCU_TIMER2_TIMER_PWM", "Output clock"}, {73, 0, "DEV_MCU_TIMER3_TIMER_HCLK_CLK", "Input clock"}, {73, 1, "DEV_MCU_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"}, {73, 2, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT3", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, {73, 3, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, {309, 0, "DEV_MCU_TIMER3_CLKSEL_VD_CLK", "Input muxed clock"}, {309, 1, "DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK"}, {309, 2, "DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK"}, {309, 3, "DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK"}, {309, 4, "DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK"}, {309, 5, "DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK"}, {309, 6, "DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK"}, {309, 7, "DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK"}, {309, 8, "DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK"}, {74, 0, "DEV_MCU_TIMER4_TIMER_HCLK_CLK", "Input clock"}, {74, 1, "DEV_MCU_TIMER4_TIMER_TCLK_CLK", "Input muxed clock"}, {74, 2, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, {74, 3, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, {74, 4, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, {74, 5, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, {74, 6, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, {74, 7, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, {74, 8, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, {74, 9, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, {74, 11, "DEV_MCU_TIMER4_TIMER_PWM", "Output clock"}, {75, 0, "DEV_MCU_TIMER5_TIMER_HCLK_CLK", "Input clock"}, {75, 1, "DEV_MCU_TIMER5_TIMER_TCLK_CLK", "Input muxed clock"}, {75, 2, "DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT5", "Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK"}, {75, 3, "DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_4_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK"}, {310, 0, "DEV_MCU_TIMER5_CLKSEL_VD_CLK", "Input muxed clock"}, {310, 1, "DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK"}, {310, 2, "DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK"}, {310, 3, "DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK"}, {310, 4, "DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK"}, {310, 5, "DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK"}, {310, 6, "DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK"}, {310, 7, "DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK"}, {310, 8, "DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK"}, {76, 0, "DEV_MCU_TIMER6_TIMER_HCLK_CLK", "Input clock"}, {76, 1, "DEV_MCU_TIMER6_TIMER_TCLK_CLK", "Input muxed clock"}, {76, 2, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, {76, 3, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, {76, 4, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, {76, 5, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, {76, 6, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, {76, 7, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, {76, 8, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, {76, 9, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, {76, 11, "DEV_MCU_TIMER6_TIMER_PWM", "Output clock"}, {77, 0, "DEV_MCU_TIMER7_TIMER_HCLK_CLK", "Input clock"}, {77, 1, "DEV_MCU_TIMER7_TIMER_TCLK_CLK", "Input muxed clock"}, {77, 2, "DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT7", "Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK"}, {77, 3, "DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_6_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK"}, {311, 0, "DEV_MCU_TIMER7_CLKSEL_VD_CLK", "Input muxed clock"}, {311, 1, "DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK"}, {311, 2, "DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK"}, {311, 3, "DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK"}, {311, 4, "DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK"}, {311, 5, "DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK"}, {311, 6, "DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK"}, {311, 7, "DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK"}, {311, 8, "DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK"}, {78, 0, "DEV_MCU_TIMER8_TIMER_HCLK_CLK", "Input clock"}, {78, 1, "DEV_MCU_TIMER8_TIMER_TCLK_CLK", "Input muxed clock"}, {78, 2, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, {78, 3, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, {78, 4, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, {78, 5, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, {78, 6, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, {78, 7, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, {78, 8, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, {78, 9, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, {78, 11, "DEV_MCU_TIMER8_TIMER_PWM", "Output clock"}, {79, 0, "DEV_MCU_TIMER9_TIMER_HCLK_CLK", "Input clock"}, {79, 1, "DEV_MCU_TIMER9_TIMER_TCLK_CLK", "Input muxed clock"}, {79, 2, "DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT9", "Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK"}, {79, 3, "DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_8_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK"}, {312, 0, "DEV_MCU_TIMER9_CLKSEL_VD_CLK", "Input muxed clock"}, {312, 1, "DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK"}, {312, 2, "DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK"}, {312, 3, "DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK"}, {312, 4, "DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK"}, {312, 5, "DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK"}, {312, 6, "DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK"}, {312, 7, "DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK"}, {312, 8, "DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK"}, {149, 2, "DEV_MCU_UART0_FCLK_CLK", "Input muxed clock"}, {149, 3, "DEV_MCU_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_UART0_FCLK_CLK"}, {149, 4, "DEV_MCU_UART0_FCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_1_HSDIVOUT5_CLK", "Parent input clock option to DEV_MCU_UART0_FCLK_CLK"}, {149, 5, "DEV_MCU_UART0_VBUSP_CLK", "Input clock"}, {91, 0, "DEV_MMCSD0_EMMCSS_VBUS_CLK", "Input clock"}, {91, 3, "DEV_MMCSD0_EMMCSS_XIN_CLK", "Input muxed clock"}, {91, 4, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"}, {91, 5, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"}, {91, 6, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"}, {91, 7, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK_DUP0", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"}, {92, 0, "DEV_MMCSD1_EMMCSDSS_IO_CLK_I", "Input clock"}, {92, 1, "DEV_MMCSD1_EMMCSDSS_VBUS_CLK", "Input clock"}, {92, 2, "DEV_MMCSD1_EMMCSDSS_XIN_CLK", "Input muxed clock"}, {92, 3, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"}, {92, 4, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"}, {92, 5, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"}, {92, 6, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK_DUP0", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"}, {92, 7, "DEV_MMCSD1_EMMCSDSS_IO_CLK_O", "Output clock"}, {199, 0, "DEV_NAVSS0_CPTS0_GENF2", "Output clock"}, {199, 1, "DEV_NAVSS0_CPTS0_GENF3", "Output clock"}, {199, 2, "DEV_NAVSS0_CPTS0_GENF4", "Output clock"}, {201, 0, "DEV_NAVSS0_CPTS_0_VBUSP_GCLK", "Input clock"}, {201, 1, "DEV_NAVSS0_CPTS_0_RCLK", "Input muxed clock"}, {201, 2, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {201, 3, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {201, 4, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {201, 5, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {201, 6, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {201, 7, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {201, 8, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {201, 9, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {201, 10, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {201, 11, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {201, 16, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {201, 17, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {201, 20, "DEV_NAVSS0_CPTS_0_TS_GENF0", "Output clock"}, {201, 21, "DEV_NAVSS0_CPTS_0_TS_GENF1", "Output clock"}, {206, 0, "DEV_NAVSS0_DTI_0_CLK_CLK", "Input clock"}, {213, 0, "DEV_NAVSS0_INTR_ROUTER_0_INTR_CLK", "Input clock"}, {214, 0, "DEV_NAVSS0_MAILBOX_0_VCLK_CLK", "Input clock"}, {215, 0, "DEV_NAVSS0_MAILBOX_1_VCLK_CLK", "Input clock"}, {224, 0, "DEV_NAVSS0_MAILBOX_10_VCLK_CLK", "Input clock"}, {225, 0, "DEV_NAVSS0_MAILBOX_11_VCLK_CLK", "Input clock"}, {216, 0, "DEV_NAVSS0_MAILBOX_2_VCLK_CLK", "Input clock"}, {217, 0, "DEV_NAVSS0_MAILBOX_3_VCLK_CLK", "Input clock"}, {218, 0, "DEV_NAVSS0_MAILBOX_4_VCLK_CLK", "Input clock"}, {219, 0, "DEV_NAVSS0_MAILBOX_5_VCLK_CLK", "Input clock"}, {220, 0, "DEV_NAVSS0_MAILBOX_6_VCLK_CLK", "Input clock"}, {221, 0, "DEV_NAVSS0_MAILBOX_7_VCLK_CLK", "Input clock"}, {222, 0, "DEV_NAVSS0_MAILBOX_8_VCLK_CLK", "Input clock"}, {223, 0, "DEV_NAVSS0_MAILBOX_9_VCLK_CLK", "Input clock"}, {227, 0, "DEV_NAVSS0_MCRC_0_CLK", "Input clock"}, {299, 0, "DEV_NAVSS0_MODSS_VD2CLK", "Input clock"}, {207, 0, "DEV_NAVSS0_MODSS_INTA_0_SYS_CLK", "Input clock"}, {208, 0, "DEV_NAVSS0_MODSS_INTA_1_SYS_CLK", "Input clock"}, {210, 0, "DEV_NAVSS0_PROXY_0_CLK_CLK", "Input clock"}, {211, 0, "DEV_NAVSS0_RINGACC_0_SYS_CLK", "Input clock"}, {226, 0, "DEV_NAVSS0_SPINLOCK_0_CLK", "Input clock"}, {228, 0, "DEV_NAVSS0_TBU_0_CLK_CLK", "Input clock"}, {230, 0, "DEV_NAVSS0_TIMERMGR_0_VCLK_CLK", "Input clock"}, {230, 1, "DEV_NAVSS0_TIMERMGR_0_EON_TICK_EVT", "Input clock"}, {231, 0, "DEV_NAVSS0_TIMERMGR_1_VCLK_CLK", "Input clock"}, {231, 1, "DEV_NAVSS0_TIMERMGR_1_EON_TICK_EVT", "Input clock"}, {212, 0, "DEV_NAVSS0_UDMAP_0_SYS_CLK", "Input clock"}, {300, 0, "DEV_NAVSS0_UDMASS_VD2CLK", "Input clock"}, {209, 0, "DEV_NAVSS0_UDMASS_INTA_0_SYS_CLK", "Input clock"}, {301, 0, "DEV_NAVSS0_VIRTSS_VD2CLK", "Input clock"}, {139, 1, "DEV_PBIST0_CLK7_CLK", "Input clock"}, {139, 2, "DEV_PBIST0_CLK3_CLK", "Input clock"}, {139, 3, "DEV_PBIST0_CLK5_CLK", "Input clock"}, {139, 4, "DEV_PBIST0_CLK1_CLK", "Input clock"}, {139, 5, "DEV_PBIST0_CLK8_CLK", "Input clock"}, {139, 6, "DEV_PBIST0_CLK6_CLK", "Input clock"}, {139, 8, "DEV_PBIST0_CLK4_CLK", "Input clock"}, {139, 9, "DEV_PBIST0_CLK2_CLK", "Input clock"}, {140, 1, "DEV_PBIST1_CLK7_CLK", "Input clock"}, {140, 2, "DEV_PBIST1_CLK3_CLK", "Input clock"}, {140, 3, "DEV_PBIST1_CLK5_CLK", "Input clock"}, {140, 4, "DEV_PBIST1_CLK1_CLK", "Input clock"}, {140, 5, "DEV_PBIST1_CLK8_CLK", "Input clock"}, {140, 6, "DEV_PBIST1_CLK6_CLK", "Input clock"}, {140, 8, "DEV_PBIST1_CLK4_CLK", "Input clock"}, {140, 9, "DEV_PBIST1_CLK2_CLK", "Input clock"}, {141, 1, "DEV_PBIST2_CLK7_CLK", "Input clock"}, {141, 2, "DEV_PBIST2_CLK3_CLK", "Input clock"}, {141, 3, "DEV_PBIST2_CLK5_CLK", "Input clock"}, {141, 4, "DEV_PBIST2_CLK1_CLK", "Input clock"}, {141, 5, "DEV_PBIST2_CLK8_CLK", "Input clock"}, {141, 6, "DEV_PBIST2_CLK6_CLK", "Input clock"}, {141, 8, "DEV_PBIST2_CLK4_CLK", "Input clock"}, {141, 9, "DEV_PBIST2_CLK2_CLK", "Input clock"}, {240, 0, "DEV_PCIE1_PCIE_LANE0_TXCLK", "Output clock"}, {240, 1, "DEV_PCIE1_PCIE_LANE1_TXMCLK", "Input clock"}, {240, 2, "DEV_PCIE1_PCIE_LANE0_TXMCLK", "Input clock"}, {240, 3, "DEV_PCIE1_PCIE_LANE0_TXFCLK", "Input clock"}, {240, 4, "DEV_PCIE1_PCIE_PM_CLK", "Input clock"}, {240, 5, "DEV_PCIE1_PCIE_LANE3_TXMCLK", "Input clock"}, {240, 6, "DEV_PCIE1_PCIE_CBA_CLK", "Input clock"}, {240, 7, "DEV_PCIE1_PCIE_LANE1_REFCLK", "Input clock"}, {240, 8, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK", "Input muxed clock"}, {240, 9, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {240, 10, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {240, 11, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {240, 12, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {240, 13, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {240, 14, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {240, 15, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {240, 16, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {240, 17, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {240, 18, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {240, 23, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {240, 24, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {240, 25, "DEV_PCIE1_PCIE_LANE1_RXFCLK", "Input clock"}, {240, 27, "DEV_PCIE1_PCIE_LANE2_RXCLK", "Input clock"}, {240, 28, "DEV_PCIE1_PCIE_LANE2_TXMCLK", "Input clock"}, {240, 29, "DEV_PCIE1_PCIE_LANE1_TXCLK", "Output clock"}, {240, 30, "DEV_PCIE1_PCIE_LANE3_TXFCLK", "Input clock"}, {240, 31, "DEV_PCIE1_PCIE_LANE2_TXFCLK", "Input clock"}, {240, 32, "DEV_PCIE1_PCIE_LANE1_RXCLK", "Input clock"}, {240, 33, "DEV_PCIE1_PCIE_LANE2_TXCLK", "Output clock"}, {240, 34, "DEV_PCIE1_PCIE_LANE1_TXFCLK", "Input clock"}, {240, 35, "DEV_PCIE1_PCIE_LANE0_REFCLK", "Input clock"}, {240, 36, "DEV_PCIE1_PCIE_LANE3_RXFCLK", "Input clock"}, {240, 37, "DEV_PCIE1_PCIE_LANE2_RXFCLK", "Input clock"}, {240, 38, "DEV_PCIE1_PCIE_LANE3_RXCLK", "Input clock"}, {240, 39, "DEV_PCIE1_PCIE_LANE3_REFCLK", "Input clock"}, {240, 40, "DEV_PCIE1_PCIE_LANE2_REFCLK", "Input clock"}, {240, 41, "DEV_PCIE1_PCIE_LANE0_RXFCLK", "Input clock"}, {240, 42, "DEV_PCIE1_PCIE_LANE3_TXCLK", "Output clock"}, {240, 43, "DEV_PCIE1_PCIE_LANE0_RXCLK", "Input clock"}, {133, 0, "DEV_PSC0_SLOW_CLK", "Input clock"}, {133, 1, "DEV_PSC0_CLK", "Input clock"}, {245, 0, "DEV_R5FSS0_CORE0_CPU_CLK", "Input clock"}, {245, 1, "DEV_R5FSS0_CORE0_INTERFACE_CLK", "Input clock"}, {245, 2, "DEV_R5FSS0_CORE0_INTERFACE_PHASE", "Input clock"}, {246, 0, "DEV_R5FSS0_CORE1_CPU_CLK", "Input clock"}, {246, 1, "DEV_R5FSS0_CORE1_INTERFACE_CLK", "Input clock"}, {246, 2, "DEV_R5FSS0_CORE1_INTERFACE_PHASE", "Input clock"}, {252, 0, "DEV_RTI0_VBUSP_CLK", "Input clock"}, {252, 1, "DEV_RTI0_RTI_CLK", "Input muxed clock"}, {252, 2, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {252, 3, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {252, 4, "DEV_RTI0_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {252, 5, "DEV_RTI0_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {252, 6, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {252, 7, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {252, 8, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {252, 9, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {253, 0, "DEV_RTI1_VBUSP_CLK", "Input clock"}, {253, 1, "DEV_RTI1_RTI_CLK", "Input muxed clock"}, {253, 2, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {253, 3, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {253, 4, "DEV_RTI1_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {253, 5, "DEV_RTI1_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {253, 6, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {253, 7, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {253, 8, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {253, 9, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {258, 0, "DEV_RTI28_VBUSP_CLK", "Input clock"}, {258, 1, "DEV_RTI28_RTI_CLK", "Input muxed clock"}, {258, 2, "DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI28_RTI_CLK"}, {258, 3, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_RTI28_RTI_CLK"}, {258, 4, "DEV_RTI28_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI28_RTI_CLK"}, {258, 5, "DEV_RTI28_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI28_RTI_CLK"}, {258, 6, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI28_RTI_CLK"}, {258, 7, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI28_RTI_CLK"}, {258, 8, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI28_RTI_CLK"}, {258, 9, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI28_RTI_CLK"}, {259, 0, "DEV_RTI29_VBUSP_CLK", "Input clock"}, {259, 1, "DEV_RTI29_RTI_CLK", "Input muxed clock"}, {259, 2, "DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI29_RTI_CLK"}, {259, 3, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_RTI29_RTI_CLK"}, {259, 4, "DEV_RTI29_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI29_RTI_CLK"}, {259, 5, "DEV_RTI29_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI29_RTI_CLK"}, {259, 6, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI29_RTI_CLK"}, {259, 7, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI29_RTI_CLK"}, {259, 8, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI29_RTI_CLK"}, {259, 9, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI29_RTI_CLK"}, {292, 1, "DEV_SERDES_10G1_IP3_LN1_TXFCLK", "Output clock"}, {292, 3, "DEV_SERDES_10G1_IP2_LN2_REFCLK", "Output clock"}, {292, 4, "DEV_SERDES_10G1_IP1_LN0_TXMCLK", "Output clock"}, {292, 6, "DEV_SERDES_10G1_IP3_LN3_RXCLK", "Output clock"}, {292, 9, "DEV_SERDES_10G1_IP2_LN2_RXCLK", "Output clock"}, {292, 10, "DEV_SERDES_10G1_IP1_LN0_TXFCLK", "Output clock"}, {292, 11, "DEV_SERDES_10G1_CLK", "Input clock"}, {292, 13, "DEV_SERDES_10G1_IP1_LN3_RXCLK", "Output clock"}, {292, 14, "DEV_SERDES_10G1_IP1_LN1_TXMCLK", "Output clock"}, {292, 15, "DEV_SERDES_10G1_IP2_LN0_TXFCLK", "Output clock"}, {292, 16, "DEV_SERDES_10G1_IP2_LN2_TXMCLK", "Output clock"}, {292, 19, "DEV_SERDES_10G1_IP3_LN1_TXCLK", "Input clock"}, {292, 21, "DEV_SERDES_10G1_IP2_LN3_RXFCLK", "Output clock"}, {292, 22, "DEV_SERDES_10G1_IP1_LN2_TXCLK", "Input clock"}, {292, 24, "DEV_SERDES_10G1_IP2_LN1_RXCLK", "Output clock"}, {292, 25, "DEV_SERDES_10G1_IP2_LN1_TXCLK", "Input clock"}, {292, 29, "DEV_SERDES_10G1_IP1_LN2_TXMCLK", "Output clock"}, {292, 32, "DEV_SERDES_10G1_IP2_LN1_TXMCLK", "Output clock"}, {292, 33, "DEV_SERDES_10G1_IP2_LN1_TXFCLK", "Output clock"}, {292, 34, "DEV_SERDES_10G1_IP1_LN1_TXFCLK", "Output clock"}, {292, 38, "DEV_SERDES_10G1_IP1_LN2_RXCLK", "Output clock"}, {292, 40, "DEV_SERDES_10G1_IP2_LN1_REFCLK", "Output clock"}, {292, 41, "DEV_SERDES_10G1_IP2_LN0_TXMCLK", "Output clock"}, {292, 42, "DEV_SERDES_10G1_IP2_LN3_RXCLK", "Output clock"}, {292, 43, "DEV_SERDES_10G1_IP2_LN2_TXCLK", "Input clock"}, {292, 44, "DEV_SERDES_10G1_IP2_LN2_RXFCLK", "Output clock"}, {292, 45, "DEV_SERDES_10G1_IP1_LN1_RXFCLK", "Output clock"}, {292, 49, "DEV_SERDES_10G1_IP1_LN0_RXCLK", "Output clock"}, {292, 52, "DEV_SERDES_10G1_IP1_LN1_RXCLK", "Output clock"}, {292, 55, "DEV_SERDES_10G1_IP1_LN0_RXFCLK", "Output clock"}, {292, 56, "DEV_SERDES_10G1_IP3_LN3_TXCLK", "Input clock"}, {292, 59, "DEV_SERDES_10G1_IP2_LN3_REFCLK", "Output clock"}, {292, 61, "DEV_SERDES_10G1_IP2_LN0_TXCLK", "Input clock"}, {292, 62, "DEV_SERDES_10G1_IP2_LN3_TXMCLK", "Output clock"}, {292, 63, "DEV_SERDES_10G1_IP1_LN1_REFCLK", "Output clock"}, {292, 65, "DEV_SERDES_10G1_IP1_LN3_TXCLK", "Input clock"}, {292, 66, "DEV_SERDES_10G1_IP3_LN1_TXMCLK", "Output clock"}, {292, 67, "DEV_SERDES_10G1_IP2_LN2_TXFCLK", "Output clock"}, {292, 73, "DEV_SERDES_10G1_IP3_LN1_RXCLK", "Output clock"}, {292, 74, "DEV_SERDES_10G1_IP3_LN1_REFCLK", "Output clock"}, {292, 75, "DEV_SERDES_10G1_IP1_LN3_REFCLK", "Output clock"}, {292, 77, "DEV_SERDES_10G1_IP1_LN0_REFCLK", "Output clock"}, {292, 80, "DEV_SERDES_10G1_IP1_LN2_REFCLK", "Output clock"}, {292, 81, "DEV_SERDES_10G1_IP2_LN0_REFCLK", "Output clock"}, {292, 82, "DEV_SERDES_10G1_IP2_LN0_RXCLK", "Output clock"}, {292, 85, "DEV_SERDES_10G1_CORE_REF_CLK", "Input muxed clock"}, {292, 86, "DEV_SERDES_10G1_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_10G1_CORE_REF_CLK"}, {292, 87, "DEV_SERDES_10G1_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_10G1_CORE_REF_CLK"}, {292, 88, "DEV_SERDES_10G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_10G1_CORE_REF_CLK"}, {292, 89, "DEV_SERDES_10G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_10G1_CORE_REF_CLK"}, {292, 92, "DEV_SERDES_10G1_IP1_LN3_TXMCLK", "Output clock"}, {292, 95, "DEV_SERDES_10G1_IP2_LN3_TXCLK", "Input clock"}, {292, 96, "DEV_SERDES_10G1_IP3_LN3_RXFCLK", "Output clock"}, {292, 98, "DEV_SERDES_10G1_IP3_LN3_REFCLK", "Output clock"}, {292, 100, "DEV_SERDES_10G1_IP2_LN1_RXFCLK", "Output clock"}, {292, 102, "DEV_SERDES_10G1_IP3_LN1_RXFCLK", "Output clock"}, {292, 104, "DEV_SERDES_10G1_IP1_LN1_TXCLK", "Input clock"}, {292, 107, "DEV_SERDES_10G1_IP3_LN3_TXFCLK", "Output clock"}, {292, 108, "DEV_SERDES_10G1_IP1_LN3_TXFCLK", "Output clock"}, {292, 109, "DEV_SERDES_10G1_IP2_LN3_TXFCLK", "Output clock"}, {292, 111, "DEV_SERDES_10G1_IP1_LN0_TXCLK", "Input clock"}, {292, 112, "DEV_SERDES_10G1_IP2_LN0_RXFCLK", "Output clock"}, {292, 113, "DEV_SERDES_10G1_IP1_LN2_RXFCLK", "Output clock"}, {292, 118, "DEV_SERDES_10G1_IP1_LN2_TXFCLK", "Output clock"}, {292, 124, "DEV_SERDES_10G1_IP1_LN3_RXFCLK", "Output clock"}, {292, 126, "DEV_SERDES_10G1_IP3_LN3_TXMCLK", "Output clock"}, {29, 0, "DEV_STM0_CORE_CLK", "Input clock"}, {29, 1, "DEV_STM0_VBUSP_CLK", "Input clock"}, {29, 2, "DEV_STM0_ATB_CLK", "Input clock"}, {49, 0, "DEV_TIMER0_TIMER_HCLK_CLK", "Input clock"}, {49, 1, "DEV_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"}, {49, 2, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {49, 3, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {49, 4, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {49, 5, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {49, 6, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {49, 7, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {49, 8, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {49, 9, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {49, 10, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {49, 11, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {49, 12, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {49, 13, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {49, 14, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {49, 15, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {49, 16, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {49, 17, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {49, 26, "DEV_TIMER0_TIMER_PWM", "Output clock"}, {50, 0, "DEV_TIMER1_TIMER_HCLK_CLK", "Input clock"}, {50, 1, "DEV_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"}, {50, 2, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT1", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {50, 3, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {60, 0, "DEV_TIMER10_TIMER_HCLK_CLK", "Input clock"}, {60, 1, "DEV_TIMER10_TIMER_TCLK_CLK", "Input muxed clock"}, {60, 2, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {60, 3, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {60, 4, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {60, 5, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {60, 6, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {60, 7, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {60, 8, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {60, 9, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {60, 10, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {60, 11, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {60, 12, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {60, 13, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {60, 14, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {60, 15, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {60, 16, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {60, 17, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {60, 26, "DEV_TIMER10_TIMER_PWM", "Output clock"}, {62, 0, "DEV_TIMER11_TIMER_HCLK_CLK", "Input clock"}, {62, 1, "DEV_TIMER11_TIMER_TCLK_CLK", "Input muxed clock"}, {62, 2, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT11", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, {62, 3, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_10_TIMER_PWM", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, {318, 0, "DEV_TIMER11_CLKSEL_VD_CLK", "Input muxed clock"}, {318, 1, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"}, {318, 2, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"}, {318, 3, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"}, {318, 4, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"}, {318, 5, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"}, {318, 6, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"}, {318, 7, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"}, {318, 8, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"}, {318, 9, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"}, {318, 10, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"}, {318, 11, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"}, {318, 12, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"}, {318, 13, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"}, {318, 14, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"}, {318, 15, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"}, {318, 16, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"}, {63, 0, "DEV_TIMER12_TIMER_HCLK_CLK", "Input clock"}, {63, 1, "DEV_TIMER12_TIMER_TCLK_CLK", "Input muxed clock"}, {63, 2, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {63, 3, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {63, 4, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {63, 5, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {63, 6, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {63, 7, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {63, 8, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {63, 9, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {63, 10, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {63, 11, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {63, 12, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {63, 13, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {63, 14, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {63, 15, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {63, 16, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {63, 17, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {63, 26, "DEV_TIMER12_TIMER_PWM", "Output clock"}, {64, 0, "DEV_TIMER13_TIMER_HCLK_CLK", "Input clock"}, {64, 1, "DEV_TIMER13_TIMER_TCLK_CLK", "Input muxed clock"}, {64, 2, "DEV_TIMER13_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT13", "Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK"}, {64, 3, "DEV_TIMER13_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_12_TIMER_PWM", "Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK"}, {319, 0, "DEV_TIMER13_CLKSEL_VD_CLK", "Input muxed clock"}, {319, 1, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"}, {319, 2, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"}, {319, 3, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"}, {319, 4, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"}, {319, 5, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"}, {319, 6, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"}, {319, 7, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"}, {319, 8, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"}, {319, 9, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"}, {319, 10, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"}, {319, 11, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"}, {319, 12, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"}, {319, 13, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"}, {319, 14, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"}, {319, 15, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"}, {319, 16, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"}, {65, 0, "DEV_TIMER14_TIMER_HCLK_CLK", "Input clock"}, {65, 1, "DEV_TIMER14_TIMER_TCLK_CLK", "Input muxed clock"}, {65, 2, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {65, 3, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {65, 4, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {65, 5, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {65, 6, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {65, 7, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {65, 8, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {65, 9, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {65, 10, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {65, 11, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {65, 12, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {65, 13, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {65, 14, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {65, 15, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {65, 16, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {65, 17, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {65, 26, "DEV_TIMER14_TIMER_PWM", "Output clock"}, {66, 0, "DEV_TIMER15_TIMER_HCLK_CLK", "Input clock"}, {66, 1, "DEV_TIMER15_TIMER_TCLK_CLK", "Input muxed clock"}, {66, 2, "DEV_TIMER15_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT15", "Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK"}, {66, 3, "DEV_TIMER15_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_14_TIMER_PWM", "Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK"}, {320, 0, "DEV_TIMER15_CLKSEL_VD_CLK", "Input muxed clock"}, {320, 1, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"}, {320, 2, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"}, {320, 3, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"}, {320, 4, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"}, {320, 5, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"}, {320, 6, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"}, {320, 7, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"}, {320, 8, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"}, {320, 9, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"}, {320, 10, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"}, {320, 11, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"}, {320, 12, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"}, {320, 13, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"}, {320, 14, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"}, {320, 15, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"}, {320, 16, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"}, {67, 0, "DEV_TIMER16_TIMER_HCLK_CLK", "Input clock"}, {67, 1, "DEV_TIMER16_TIMER_TCLK_CLK", "Input muxed clock"}, {67, 2, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {67, 3, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {67, 4, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {67, 5, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {67, 6, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {67, 7, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {67, 8, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {67, 9, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {67, 10, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {67, 11, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {67, 12, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {67, 13, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {67, 14, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {67, 15, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {67, 16, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {67, 17, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {67, 26, "DEV_TIMER16_TIMER_PWM", "Output clock"}, {68, 0, "DEV_TIMER17_TIMER_HCLK_CLK", "Input clock"}, {68, 1, "DEV_TIMER17_TIMER_TCLK_CLK", "Input muxed clock"}, {68, 2, "DEV_TIMER17_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT17", "Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK"}, {68, 3, "DEV_TIMER17_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_16_TIMER_PWM", "Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK"}, {321, 0, "DEV_TIMER17_CLKSEL_VD_CLK", "Input muxed clock"}, {321, 1, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"}, {321, 2, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"}, {321, 3, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"}, {321, 4, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"}, {321, 5, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"}, {321, 6, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"}, {321, 7, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"}, {321, 8, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"}, {321, 9, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"}, {321, 10, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"}, {321, 11, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"}, {321, 12, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"}, {321, 13, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"}, {321, 14, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"}, {321, 15, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"}, {321, 16, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"}, {69, 0, "DEV_TIMER18_TIMER_HCLK_CLK", "Input clock"}, {69, 1, "DEV_TIMER18_TIMER_TCLK_CLK", "Input muxed clock"}, {69, 2, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {69, 3, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {69, 4, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {69, 5, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {69, 6, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {69, 7, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {69, 8, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {69, 9, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {69, 10, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {69, 11, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {69, 12, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {69, 13, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {69, 14, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {69, 15, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {69, 16, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {69, 17, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {69, 26, "DEV_TIMER18_TIMER_PWM", "Output clock"}, {70, 0, "DEV_TIMER19_TIMER_HCLK_CLK", "Input clock"}, {70, 1, "DEV_TIMER19_TIMER_TCLK_CLK", "Input muxed clock"}, {70, 2, "DEV_TIMER19_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT19", "Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK"}, {70, 3, "DEV_TIMER19_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_18_TIMER_PWM", "Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK"}, {322, 0, "DEV_TIMER19_CLKSEL_VD_CLK", "Input muxed clock"}, {322, 1, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"}, {322, 2, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"}, {322, 3, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"}, {322, 4, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"}, {322, 5, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"}, {322, 6, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"}, {322, 7, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"}, {322, 8, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"}, {322, 9, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"}, {322, 10, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"}, {322, 11, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"}, {322, 12, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"}, {322, 13, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"}, {322, 14, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"}, {322, 15, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"}, {322, 16, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"}, {313, 0, "DEV_TIMER1_CLKSEL_VD_CLK", "Input muxed clock"}, {313, 1, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"}, {313, 2, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"}, {313, 3, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"}, {313, 4, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"}, {313, 5, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"}, {313, 6, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"}, {313, 7, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"}, {313, 8, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"}, {313, 9, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"}, {313, 10, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"}, {313, 11, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"}, {313, 12, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"}, {313, 13, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"}, {313, 14, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"}, {313, 15, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"}, {313, 16, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"}, {51, 0, "DEV_TIMER2_TIMER_HCLK_CLK", "Input clock"}, {51, 1, "DEV_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"}, {51, 2, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {51, 3, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {51, 4, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {51, 5, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {51, 6, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {51, 7, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {51, 8, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {51, 9, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {51, 10, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {51, 11, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {51, 12, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {51, 13, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {51, 14, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {51, 15, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {51, 16, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {51, 17, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {51, 26, "DEV_TIMER2_TIMER_PWM", "Output clock"}, {52, 0, "DEV_TIMER3_TIMER_HCLK_CLK", "Input clock"}, {52, 1, "DEV_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"}, {52, 2, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT3", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {52, 3, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {314, 0, "DEV_TIMER3_CLKSEL_VD_CLK", "Input muxed clock"}, {314, 1, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"}, {314, 2, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"}, {314, 3, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"}, {314, 4, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"}, {314, 5, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"}, {314, 6, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"}, {314, 7, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"}, {314, 8, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"}, {314, 9, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"}, {314, 10, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"}, {314, 11, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"}, {314, 12, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"}, {314, 13, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"}, {314, 14, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"}, {314, 15, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"}, {314, 16, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"}, {53, 0, "DEV_TIMER4_TIMER_HCLK_CLK", "Input clock"}, {53, 1, "DEV_TIMER4_TIMER_TCLK_CLK", "Input muxed clock"}, {53, 2, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {53, 3, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {53, 4, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {53, 5, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {53, 6, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {53, 7, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {53, 8, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {53, 9, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {53, 10, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {53, 11, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {53, 12, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {53, 13, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {53, 14, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {53, 15, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {53, 16, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {53, 17, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {53, 26, "DEV_TIMER4_TIMER_PWM", "Output clock"}, {54, 0, "DEV_TIMER5_TIMER_HCLK_CLK", "Input clock"}, {54, 1, "DEV_TIMER5_TIMER_TCLK_CLK", "Input muxed clock"}, {54, 2, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT5", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {54, 3, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {315, 0, "DEV_TIMER5_CLKSEL_VD_CLK", "Input muxed clock"}, {315, 1, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"}, {315, 2, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"}, {315, 3, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"}, {315, 4, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"}, {315, 5, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"}, {315, 6, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"}, {315, 7, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"}, {315, 8, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"}, {315, 9, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"}, {315, 10, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"}, {315, 11, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"}, {315, 12, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"}, {315, 13, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"}, {315, 14, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"}, {315, 15, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"}, {315, 16, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"}, {55, 0, "DEV_TIMER6_TIMER_HCLK_CLK", "Input clock"}, {55, 1, "DEV_TIMER6_TIMER_TCLK_CLK", "Input muxed clock"}, {55, 2, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {55, 3, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {55, 4, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {55, 5, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {55, 6, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {55, 7, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {55, 8, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {55, 9, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {55, 10, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {55, 11, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {55, 12, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {55, 13, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {55, 14, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {55, 15, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {55, 16, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {55, 17, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {55, 26, "DEV_TIMER6_TIMER_PWM", "Output clock"}, {57, 0, "DEV_TIMER7_TIMER_HCLK_CLK", "Input clock"}, {57, 1, "DEV_TIMER7_TIMER_TCLK_CLK", "Input muxed clock"}, {57, 2, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT7", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {57, 3, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {316, 0, "DEV_TIMER7_CLKSEL_VD_CLK", "Input muxed clock"}, {316, 1, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"}, {316, 2, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"}, {316, 3, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"}, {316, 4, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"}, {316, 5, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"}, {316, 6, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"}, {316, 7, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"}, {316, 8, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"}, {316, 9, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"}, {316, 10, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"}, {316, 11, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"}, {316, 12, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"}, {316, 13, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"}, {316, 14, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"}, {316, 15, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"}, {316, 16, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"}, {58, 0, "DEV_TIMER8_TIMER_HCLK_CLK", "Input clock"}, {58, 1, "DEV_TIMER8_TIMER_TCLK_CLK", "Input muxed clock"}, {58, 2, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {58, 3, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {58, 4, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {58, 5, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {58, 6, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {58, 7, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {58, 8, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {58, 9, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {58, 10, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {58, 11, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {58, 12, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {58, 13, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {58, 14, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {58, 15, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {58, 16, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {58, 17, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {58, 26, "DEV_TIMER8_TIMER_PWM", "Output clock"}, {59, 0, "DEV_TIMER9_TIMER_HCLK_CLK", "Input clock"}, {59, 1, "DEV_TIMER9_TIMER_TCLK_CLK", "Input muxed clock"}, {59, 2, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT9", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, {59, 3, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_8_TIMER_PWM", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, {317, 0, "DEV_TIMER9_CLKSEL_VD_CLK", "Input muxed clock"}, {317, 1, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"}, {317, 2, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"}, {317, 3, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"}, {317, 4, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"}, {317, 5, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"}, {317, 6, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"}, {317, 7, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"}, {317, 8, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"}, {317, 9, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"}, {317, 10, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"}, {317, 11, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"}, {317, 12, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"}, {317, 13, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"}, {317, 14, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"}, {317, 15, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"}, {317, 16, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"}, {146, 2, "DEV_UART0_FCLK_CLK", "Input clock"}, {146, 3, "DEV_UART0_VBUSP_CLK", "Input clock"}, {278, 2, "DEV_UART1_FCLK_CLK", "Input clock"}, {278, 3, "DEV_UART1_VBUSP_CLK", "Input clock"}, {279, 2, "DEV_UART2_FCLK_CLK", "Input clock"}, {279, 3, "DEV_UART2_VBUSP_CLK", "Input clock"}, {280, 2, "DEV_UART3_FCLK_CLK", "Input clock"}, {280, 3, "DEV_UART3_VBUSP_CLK", "Input clock"}, {281, 2, "DEV_UART4_FCLK_CLK", "Input clock"}, {281, 3, "DEV_UART4_VBUSP_CLK", "Input clock"}, {282, 2, "DEV_UART5_FCLK_CLK", "Input clock"}, {282, 3, "DEV_UART5_VBUSP_CLK", "Input clock"}, {283, 2, "DEV_UART6_FCLK_CLK", "Input clock"}, {283, 3, "DEV_UART6_VBUSP_CLK", "Input clock"}, {284, 2, "DEV_UART7_FCLK_CLK", "Input clock"}, {284, 3, "DEV_UART7_VBUSP_CLK", "Input clock"}, {285, 2, "DEV_UART8_FCLK_CLK", "Input clock"}, {285, 3, "DEV_UART8_VBUSP_CLK", "Input clock"}, {286, 2, "DEV_UART9_FCLK_CLK", "Input clock"}, {286, 3, "DEV_UART9_VBUSP_CLK", "Input clock"}, {288, 0, "DEV_USB0_PIPE_REFCLK", "Input muxed clock"}, {288, 1, "DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP3_LN1_REFCLK", "Parent input clock option to DEV_USB0_PIPE_REFCLK"}, {288, 2, "DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP3_LN3_REFCLK", "Parent input clock option to DEV_USB0_PIPE_REFCLK"}, {288, 3, "DEV_USB0_CLK_LPM_CLK", "Input clock"}, {288, 4, "DEV_USB0_BUF_CLK", "Input clock"}, {288, 5, "DEV_USB0_PIPE_TXFCLK", "Input clock"}, {288, 6, "DEV_USB0_USB2_APB_PCLK_CLK", "Input clock"}, {288, 7, "DEV_USB0_PIPE_RXCLK", "Input clock"}, {288, 8, "DEV_USB0_PIPE_TXMCLK", "Input clock"}, {288, 9, "DEV_USB0_PIPE_RXFCLK", "Input clock"}, {288, 11, "DEV_USB0_PIPE_TXCLK", "Output clock"}, {288, 12, "DEV_USB0_USB2_REFCLOCK_CLK", "Input muxed clock"}, {288, 13, "DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK"}, {288, 14, "DEV_USB0_USB2_REFCLOCK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK"}, {288, 15, "DEV_USB0_PCLK_CLK", "Input clock"}, {288, 17, "DEV_USB0_ACLK_CLK", "Input clock"}, {145, 0, "DEV_WKUP_DDPA0_DDPA_CLK", "Input clock"}, {99, 0, "DEV_WKUP_ESM0_CLK", "Input clock"}, {113, 0, "DEV_WKUP_GPIO0_MMR_CLK", "Input muxed clock"}, {113, 1, "DEV_WKUP_GPIO0_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_WKUP_GPIO0_MMR_CLK"}, {113, 2, "DEV_WKUP_GPIO0_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6_DUP0", "Parent input clock option to DEV_WKUP_GPIO0_MMR_CLK"}, {113, 3, "DEV_WKUP_GPIO0_MMR_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_WKUP_GPIO0_MMR_CLK"}, {113, 4, "DEV_WKUP_GPIO0_MMR_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_WKUP_GPIO0_MMR_CLK"}, {114, 0, "DEV_WKUP_GPIO1_MMR_CLK", "Input muxed clock"}, {114, 1, "DEV_WKUP_GPIO1_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_WKUP_GPIO1_MMR_CLK"}, {114, 2, "DEV_WKUP_GPIO1_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6_DUP0", "Parent input clock option to DEV_WKUP_GPIO1_MMR_CLK"}, {114, 3, "DEV_WKUP_GPIO1_MMR_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_WKUP_GPIO1_MMR_CLK"}, {114, 4, "DEV_WKUP_GPIO1_MMR_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_WKUP_GPIO1_MMR_CLK"}, {197, 0, "DEV_WKUP_I2C0_PISCL", "Input clock"}, {197, 1, "DEV_WKUP_I2C0_PISYS_CLK", "Input clock"}, {197, 2, "DEV_WKUP_I2C0_CLK", "Input clock"}, {197, 3, "DEV_WKUP_I2C0_PORSCL", "Output clock"}, {132, 0, "DEV_WKUP_PORZ_SYNC0_CLK_12M_RC_CLK", "Input clock"}, {138, 0, "DEV_WKUP_PSC0_SLOW_CLK", "Input clock"}, {138, 1, "DEV_WKUP_PSC0_CLK", "Input clock"}, {287, 2, "DEV_WKUP_UART0_FCLK_CLK", "Input muxed clock"}, {287, 3, "DEV_WKUP_UART0_FCLK_CLK_PARENT_WKUPUSART_CLK_SEL_OUT0", "Parent input clock option to DEV_WKUP_UART0_FCLK_CLK"}, {287, 4, "DEV_WKUP_UART0_FCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_WKUP_UART0_FCLK_CLK"}, {287, 5, "DEV_WKUP_UART0_VBUSP_CLK", "Input clock"}, {154, 0, "DEV_WKUP_VTM0_FIX_REF2_CLK", "Input clock"}, {154, 1, "DEV_WKUP_VTM0_VBUSP_CLK", "Input clock"}, {154, 2, "DEV_WKUP_VTM0_FIX_REF_CLK", "Input clock"}, {40, 0, "DEV_WKUP_WAKEUP0_PLL_CTRL_WKUP_CLK24_CLK", "Input clock"}, {40, 1, "DEV_WKUP_WAKEUP0_WKUP_RCOSC_32K_CLK", "Output clock"}, {40, 2, "DEV_WKUP_WAKEUP0_WKUP_RCOSC_12P5M_CLK", "Output clock"}, }; k3conf_0.3/soc/j7200/j7200_devices_info.h0000664000175000017500000000346414375734376014553 0ustar /* * J7200 Devices Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __J7200_DEVICES_INFO_H #define __J7200_DEVICES_INFO_H #define J7200_MAX_DEVICES 256 extern struct ti_sci_devices_info j7200_devices_info[]; #endif /* __J7200_DEVICES_INFO_H */ k3conf_0.3/soc/j7200/j7200_processors_info.c0000664000175000017500000000366314375734376015327 0ustar /* * J7200 Processor Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_processors_info j7200_processors_info[] = { {202, 2, 0x20, "A72SS0_CORE0_0"}, {203, 0, 0x21, "A72SS0_CORE0_1"}, {250, 0, 0x01, "MCU_R5FSS0_CORE0"}, {251, 0, 0x02, "MCU_R5FSS0_CORE1"}, {245, 0, 0x06, "R5FSS0_CORE0"}, {246, 0, 0x07, "R5FSS0_CORE1"}, }; k3conf_0.3/soc/j7200/j7200_clocks_info.h0000664000175000017500000000345614375734376014410 0ustar /* * J7200 Clocks Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __J7200_CLOCKS_INFO_H #define __J7200_CLOCKS_INFO_H #define J7200_MAX_CLOCKS 1641 extern struct ti_sci_clocks_info j7200_clocks_info[]; #endif /* __J7200_CLOCKS_INFO_H */ k3conf_0.3/soc/j7200/j7200_ddr_info.c0000664000175000017500000000367714504336530013663 0ustar /* * J7200 DDR performance information * * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #define MAX_PERF_NUM_DDR_INSTANCES 1 static uintptr_t j7200_ddr_base_address[MAX_PERF_NUM_DDR_INSTANCES] = { 0x02980100, }; struct ddr_perf_soc_info j7200_ddr_perf_info = { .num_perf_insts = MAX_PERF_NUM_DDR_INSTANCES, .burst_size = 64, .perf_inst_base = j7200_ddr_base_address, }; k3conf_0.3/soc/j7200/j7200_host_info.c0000664000175000017500000000547214375734376014102 0ustar /* * J7200 Hosts Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_host_info j7200_host_info[] = { {0, "DMSC", "Secure", "Security Controller"}, {3, "MCU_0_R5_0", "Non Secure", "Cortex R5 context 0 on MCU island"}, {4, "MCU_0_R5_1", "Secure", "Cortex R5 context 1 on MCU island(Boot)"}, {5, "MCU_0_R5_2", "Non Secure", "Cortex R5 context 2 on MCU island"}, {6, "MCU_0_R5_3", "Secure", "Cortex R5 context 3 on MCU island"}, {10, "A72_0", "Secure", "Cortex A72 context 0 on Main island"}, {11, "A72_1", "Secure", "Cortex A72 context 1 on Main island"}, {12, "A72_2", "Non Secure", "Cortex A72 context 2 on Main island"}, {13, "A72_3", "Non Secure", "Cortex A72 context 3 on Main island"}, {14, "A72_4", "Non Secure", "Cortex A72 context 4 on Main island"}, {35, "MAIN_0_R5_0", "Non Secure", "Cortex R5_0 context 0 on Main island"}, {36, "MAIN_0_R5_1", "Secure", "Cortex R5_0 context 1 on Main island"}, {37, "MAIN_0_R5_2", "Non Secure", "Cortex R5_0 context 2 on Main island"}, {38, "MAIN_0_R5_3", "Secure", "Cortex R5_0 context 3 on Main island"}, {250, "DM2DMSC", "Secure", "DM to DMSC communication"}, {251, "DMSC2DM", "Non Secure", "DMSC to DM communication"}, {254, "DM", "Non Secure", "Device Management"}, }; k3conf_0.3/soc/j7200/j7200_rm_info.c0000664000175000017500000000772214375734376013543 0ustar /* * J7200 RM Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_rm_info j7200_rm_info[] = { {0x1EC0, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x2000, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x2080, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x20C0, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x2200, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x2240, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x33CA, "RESASG_SUBTYPE_IA_VINT"}, {0x33CD, "RESASG_SUBTYPE_GLOBAL_EVENT_SEVT"}, {0x340A, "RESASG_SUBTYPE_IA_VINT"}, {0x340D, "RESASG_SUBTYPE_GLOBAL_EVENT_SEVT"}, {0x344A, "RESASG_SUBTYPE_IA_VINT"}, {0x344D, "RESASG_SUBTYPE_GLOBAL_EVENT_SEVT"}, {0x3480, "RESASG_SUBTYPE_PROXY_PROXIES"}, {0x34C0, "RESASG_SUBTYPE_RA_ERROR_OES"}, {0x34C1, "RESASG_SUBTYPE_RA_GP"}, {0x34C2, "RESASG_SUBTYPE_RA_UDMAP_RX"}, {0x34C3, "RESASG_SUBTYPE_RA_UDMAP_TX"}, {0x34C5, "RESASG_SUBTYPE_RA_UDMAP_RX_H"}, {0x34C6, "RESASG_SUBTYPE_RA_UDMAP_RX_UH"}, {0x34C7, "RESASG_SUBTYPE_RA_UDMAP_TX_H"}, {0x34C8, "RESASG_SUBTYPE_RA_UDMAP_TX_UH"}, {0x34CA, "RESASG_SUBTYPE_RA_VIRTID"}, {0x34CB, "RESASG_SUBTYPE_RA_MONITORS"}, {0x3500, "RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON"}, {0x3501, "RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES"}, {0x3502, "RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER"}, {0x3503, "RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG"}, {0x350A, "RESASG_SUBTYPE_UDMAP_RX_CHAN"}, {0x350B, "RESASG_SUBTYPE_UDMAP_RX_HCHAN"}, {0x350C, "RESASG_SUBTYPE_UDMAP_RX_UHCHAN"}, {0x350D, "RESASG_SUBTYPE_UDMAP_TX_CHAN"}, {0x350F, "RESASG_SUBTYPE_UDMAP_TX_HCHAN"}, {0x3510, "RESASG_SUBTYPE_UDMAP_TX_UHCHAN"}, {0x3540, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x3A4A, "RESASG_SUBTYPE_IA_VINT"}, {0x3A4D, "RESASG_SUBTYPE_GLOBAL_EVENT_SEVT"}, {0x3A80, "RESASG_SUBTYPE_PROXY_PROXIES"}, {0x3AC0, "RESASG_SUBTYPE_RA_ERROR_OES"}, {0x3AC1, "RESASG_SUBTYPE_RA_GP"}, {0x3AC2, "RESASG_SUBTYPE_RA_UDMAP_RX"}, {0x3AC3, "RESASG_SUBTYPE_RA_UDMAP_TX"}, {0x3AC5, "RESASG_SUBTYPE_RA_UDMAP_RX_H"}, {0x3AC7, "RESASG_SUBTYPE_RA_UDMAP_TX_H"}, {0x3ACA, "RESASG_SUBTYPE_RA_VIRTID"}, {0x3ACB, "RESASG_SUBTYPE_RA_MONITORS"}, {0x3B00, "RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON"}, {0x3B01, "RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES"}, {0x3B02, "RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER"}, {0x3B03, "RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG"}, {0x3B0A, "RESASG_SUBTYPE_UDMAP_RX_CHAN"}, {0x3B0B, "RESASG_SUBTYPE_UDMAP_RX_HCHAN"}, {0x3B0D, "RESASG_SUBTYPE_UDMAP_TX_CHAN"}, {0x3B0F, "RESASG_SUBTYPE_UDMAP_TX_HCHAN"}, {0x3B40, "RESASG_SUBTYPE_IR_OUTPUT"}, }; k3conf_0.3/soc/j7200/j7200_processors_info.h0000664000175000017500000000350614504336513015311 0ustar /* * J7200 Processor Info * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __J7200_PROCESSOR_INFO_H #define __J7200_PROCESSOR_INFO_H #define J7200_MAX_PROCESSORS_IDS 6 extern struct ti_sci_processors_info j7200_processors_info[]; #endif /* __J7200_PROCESSOR_INFO_H */ k3conf_0.3/soc/j7200/j7200_devices_info.c0000664000175000017500000002335114375734376014543 0ustar /* * J7200 Devices Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_devices_info j7200_devices_info[] = { {0, "J7200_DEV_MCU_ADC0"}, {1, "J7200_DEV_MCU_ADC1"}, {2, "J7200_DEV_ATL0"}, {3, "J7200_DEV_COMPUTE_CLUSTER0"}, {4, "J7200_DEV_A72SS0_CORE0"}, {5, "J7200_DEV_COMPUTE_CLUSTER0_CFG_WRAP"}, {6, "J7200_DEV_COMPUTE_CLUSTER0_CLEC"}, {7, "J7200_DEV_COMPUTE_CLUSTER0_CORE_CORE"}, {8, "J7200_DEV_DDR0"}, {9, "J7200_DEV_COMPUTE_CLUSTER0_DEBUG_WRAP"}, {10, "J7200_DEV_COMPUTE_CLUSTER0_DIVH2_DIVH0"}, {11, "J7200_DEV_COMPUTE_CLUSTER0_DIVP_TFT0"}, {12, "J7200_DEV_COMPUTE_CLUSTER0_DMSC_WRAP"}, {13, "J7200_DEV_COMPUTE_CLUSTER0_EN_MSMC_DOMAIN"}, {14, "J7200_DEV_COMPUTE_CLUSTER0_GIC500SS"}, {17, "J7200_DEV_COMPUTE_CLUSTER0_PBIST_WRAP"}, {18, "J7200_DEV_MCU_CPSW0"}, {19, "J7200_DEV_CPSW0"}, {20, "J7200_DEV_CPT2_AGGR0"}, {21, "J7200_DEV_CPT2_AGGR1"}, {22, "J7200_DEV_WKUP_DMSC0"}, {23, "J7200_DEV_CPT2_AGGR2"}, {24, "J7200_DEV_MCU_CPT2_AGGR0"}, {25, "J7200_DEV_CPT2_AGGR3"}, {26, "J7200_DEV_CPSW_TX_RGMII0"}, {29, "J7200_DEV_STM0"}, {30, "J7200_DEV_DCC0"}, {31, "J7200_DEV_DCC1"}, {32, "J7200_DEV_DCC2"}, {33, "J7200_DEV_DCC3"}, {34, "J7200_DEV_DCC4"}, {35, "J7200_DEV_MCU_TIMER0"}, {36, "J7200_DEV_DCC5"}, {37, "J7200_DEV_DCC6"}, {39, "J7200_DEV_MAIN0"}, {40, "J7200_DEV_WKUP_WAKEUP0"}, {44, "J7200_DEV_MCU_DCC0"}, {45, "J7200_DEV_MCU_DCC1"}, {46, "J7200_DEV_MCU_DCC2"}, {49, "J7200_DEV_TIMER0"}, {50, "J7200_DEV_TIMER1"}, {51, "J7200_DEV_TIMER2"}, {52, "J7200_DEV_TIMER3"}, {53, "J7200_DEV_TIMER4"}, {54, "J7200_DEV_TIMER5"}, {55, "J7200_DEV_TIMER6"}, {57, "J7200_DEV_TIMER7"}, {58, "J7200_DEV_TIMER8"}, {59, "J7200_DEV_TIMER9"}, {60, "J7200_DEV_TIMER10"}, {61, "J7200_DEV_GTC0"}, {62, "J7200_DEV_TIMER11"}, {63, "J7200_DEV_TIMER12"}, {64, "J7200_DEV_TIMER13"}, {65, "J7200_DEV_TIMER14"}, {66, "J7200_DEV_TIMER15"}, {67, "J7200_DEV_TIMER16"}, {68, "J7200_DEV_TIMER17"}, {69, "J7200_DEV_TIMER18"}, {70, "J7200_DEV_TIMER19"}, {71, "J7200_DEV_MCU_TIMER1"}, {72, "J7200_DEV_MCU_TIMER2"}, {73, "J7200_DEV_MCU_TIMER3"}, {74, "J7200_DEV_MCU_TIMER4"}, {75, "J7200_DEV_MCU_TIMER5"}, {76, "J7200_DEV_MCU_TIMER6"}, {77, "J7200_DEV_MCU_TIMER7"}, {78, "J7200_DEV_MCU_TIMER8"}, {79, "J7200_DEV_MCU_TIMER9"}, {80, "J7200_DEV_ECAP0"}, {81, "J7200_DEV_ECAP1"}, {82, "J7200_DEV_ECAP2"}, {83, "J7200_DEV_EHRPWM0"}, {84, "J7200_DEV_EHRPWM1"}, {85, "J7200_DEV_EHRPWM2"}, {86, "J7200_DEV_EHRPWM3"}, {87, "J7200_DEV_EHRPWM4"}, {88, "J7200_DEV_EHRPWM5"}, {89, "J7200_DEV_ELM0"}, {90, "J7200_DEV_EMIF_DATA_0_VD"}, {91, "J7200_DEV_MMCSD0"}, {92, "J7200_DEV_MMCSD1"}, {94, "J7200_DEV_EQEP0"}, {95, "J7200_DEV_EQEP1"}, {96, "J7200_DEV_EQEP2"}, {97, "J7200_DEV_ESM0"}, {98, "J7200_DEV_MCU_ESM0"}, {99, "J7200_DEV_WKUP_ESM0"}, {100, "J7200_DEV_MCU_FSS0"}, {101, "J7200_DEV_MCU_FSS0_FSAS_0"}, {102, "J7200_DEV_MCU_FSS0_HYPERBUS1P0_0"}, {103, "J7200_DEV_MCU_FSS0_OSPI_0"}, {104, "J7200_DEV_MCU_FSS0_OSPI_1"}, {105, "J7200_DEV_GPIO0"}, {107, "J7200_DEV_GPIO2"}, {109, "J7200_DEV_GPIO4"}, {111, "J7200_DEV_GPIO6"}, {113, "J7200_DEV_WKUP_GPIO0"}, {114, "J7200_DEV_WKUP_GPIO1"}, {115, "J7200_DEV_GPMC0"}, {116, "J7200_DEV_I3C0"}, {117, "J7200_DEV_MCU_I3C0"}, {118, "J7200_DEV_MCU_I3C1"}, {123, "J7200_DEV_CMPEVENT_INTRTR0"}, {127, "J7200_DEV_LED0"}, {128, "J7200_DEV_MAIN2MCU_LVL_INTRTR0"}, {130, "J7200_DEV_MAIN2MCU_PLS_INTRTR0"}, {131, "J7200_DEV_GPIOMUX_INTRTR0"}, {132, "J7200_DEV_WKUP_PORZ_SYNC0"}, {133, "J7200_DEV_PSC0"}, {136, "J7200_DEV_TIMESYNC_INTRTR0"}, {137, "J7200_DEV_WKUP_GPIOMUX_INTRTR0"}, {138, "J7200_DEV_WKUP_PSC0"}, {139, "J7200_DEV_PBIST0"}, {140, "J7200_DEV_PBIST1"}, {141, "J7200_DEV_PBIST2"}, {142, "J7200_DEV_MCU_PBIST0"}, {143, "J7200_DEV_MCU_PBIST1"}, {144, "J7200_DEV_MCU_PBIST2"}, {145, "J7200_DEV_WKUP_DDPA0"}, {146, "J7200_DEV_UART0"}, {149, "J7200_DEV_MCU_UART0"}, {150, "J7200_DEV_MCAN14"}, {151, "J7200_DEV_MCAN15"}, {152, "J7200_DEV_MCAN16"}, {153, "J7200_DEV_MCAN17"}, {154, "J7200_DEV_WKUP_VTM0"}, {155, "J7200_DEV_MAIN2WKUPMCU_VD"}, {156, "J7200_DEV_MCAN0"}, {157, "J7200_DEV_BOARD0"}, {158, "J7200_DEV_MCAN1"}, {160, "J7200_DEV_MCAN2"}, {161, "J7200_DEV_MCAN3"}, {162, "J7200_DEV_MCAN4"}, {163, "J7200_DEV_MCAN5"}, {164, "J7200_DEV_MCAN6"}, {165, "J7200_DEV_MCAN7"}, {166, "J7200_DEV_MCAN8"}, {167, "J7200_DEV_MCAN9"}, {168, "J7200_DEV_MCAN10"}, {169, "J7200_DEV_MCAN11"}, {170, "J7200_DEV_MCAN12"}, {171, "J7200_DEV_MCAN13"}, {172, "J7200_DEV_MCU_MCAN0"}, {173, "J7200_DEV_MCU_MCAN1"}, {174, "J7200_DEV_MCASP0"}, {175, "J7200_DEV_MCASP1"}, {176, "J7200_DEV_MCASP2"}, {187, "J7200_DEV_I2C0"}, {188, "J7200_DEV_I2C1"}, {189, "J7200_DEV_I2C2"}, {190, "J7200_DEV_I2C3"}, {191, "J7200_DEV_I2C4"}, {192, "J7200_DEV_I2C5"}, {193, "J7200_DEV_I2C6"}, {194, "J7200_DEV_MCU_I2C0"}, {195, "J7200_DEV_MCU_I2C1"}, {197, "J7200_DEV_WKUP_I2C0"}, {199, "J7200_DEV_NAVSS0"}, {201, "J7200_DEV_NAVSS0_CPTS_0"}, {202, "J7200_DEV_A72SS0_CORE0_0"}, {203, "J7200_DEV_A72SS0_CORE0_1"}, {206, "J7200_DEV_NAVSS0_DTI_0"}, {207, "J7200_DEV_NAVSS0_MODSS_INTA_0"}, {208, "J7200_DEV_NAVSS0_MODSS_INTA_1"}, {209, "J7200_DEV_NAVSS0_UDMASS_INTA_0"}, {210, "J7200_DEV_NAVSS0_PROXY_0"}, {211, "J7200_DEV_NAVSS0_RINGACC_0"}, {212, "J7200_DEV_NAVSS0_UDMAP_0"}, {213, "J7200_DEV_NAVSS0_INTR_ROUTER_0"}, {214, "J7200_DEV_NAVSS0_MAILBOX_0"}, {215, "J7200_DEV_NAVSS0_MAILBOX_1"}, {216, "J7200_DEV_NAVSS0_MAILBOX_2"}, {217, "J7200_DEV_NAVSS0_MAILBOX_3"}, {218, "J7200_DEV_NAVSS0_MAILBOX_4"}, {219, "J7200_DEV_NAVSS0_MAILBOX_5"}, {220, "J7200_DEV_NAVSS0_MAILBOX_6"}, {221, "J7200_DEV_NAVSS0_MAILBOX_7"}, {222, "J7200_DEV_NAVSS0_MAILBOX_8"}, {223, "J7200_DEV_NAVSS0_MAILBOX_9"}, {224, "J7200_DEV_NAVSS0_MAILBOX_10"}, {225, "J7200_DEV_NAVSS0_MAILBOX_11"}, {226, "J7200_DEV_NAVSS0_SPINLOCK_0"}, {227, "J7200_DEV_NAVSS0_MCRC_0"}, {228, "J7200_DEV_NAVSS0_TBU_0"}, {230, "J7200_DEV_NAVSS0_TIMERMGR_0"}, {231, "J7200_DEV_NAVSS0_TIMERMGR_1"}, {232, "J7200_DEV_MCU_NAVSS0"}, {233, "J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0"}, {234, "J7200_DEV_MCU_NAVSS0_PROXY0"}, {235, "J7200_DEV_MCU_NAVSS0_RINGACC0"}, {236, "J7200_DEV_MCU_NAVSS0_UDMAP_0"}, {237, "J7200_DEV_MCU_NAVSS0_INTR_0"}, {238, "J7200_DEV_MCU_NAVSS0_MCRC_0"}, {240, "J7200_DEV_PCIE1"}, {243, "J7200_DEV_R5FSS0"}, {245, "J7200_DEV_R5FSS0_CORE0"}, {246, "J7200_DEV_R5FSS0_CORE1"}, {249, "J7200_DEV_MCU_R5FSS0"}, {250, "J7200_DEV_MCU_R5FSS0_CORE0"}, {251, "J7200_DEV_MCU_R5FSS0_CORE1"}, {252, "J7200_DEV_RTI0"}, {253, "J7200_DEV_RTI1"}, {258, "J7200_DEV_RTI28"}, {259, "J7200_DEV_RTI29"}, {262, "J7200_DEV_MCU_RTI0"}, {263, "J7200_DEV_MCU_RTI1"}, {265, "J7200_DEV_MCU_SA2_UL0"}, {266, "J7200_DEV_MCSPI0"}, {267, "J7200_DEV_MCSPI1"}, {268, "J7200_DEV_MCSPI2"}, {269, "J7200_DEV_MCSPI3"}, {270, "J7200_DEV_MCSPI4"}, {271, "J7200_DEV_MCSPI5"}, {272, "J7200_DEV_MCSPI6"}, {273, "J7200_DEV_MCSPI7"}, {274, "J7200_DEV_MCU_MCSPI0"}, {275, "J7200_DEV_MCU_MCSPI1"}, {276, "J7200_DEV_MCU_MCSPI2"}, {278, "J7200_DEV_UART1"}, {279, "J7200_DEV_UART2"}, {280, "J7200_DEV_UART3"}, {281, "J7200_DEV_UART4"}, {282, "J7200_DEV_UART5"}, {283, "J7200_DEV_UART6"}, {284, "J7200_DEV_UART7"}, {285, "J7200_DEV_UART8"}, {286, "J7200_DEV_UART9"}, {287, "J7200_DEV_WKUP_UART0"}, {288, "J7200_DEV_USB0"}, {292, "J7200_DEV_SERDES_10G1"}, {298, "J7200_DEV_WKUPMCU2MAIN_VD"}, {299, "J7200_DEV_NAVSS0_MODSS"}, {300, "J7200_DEV_NAVSS0_UDMASS"}, {301, "J7200_DEV_NAVSS0_VIRTSS"}, {302, "J7200_DEV_MCU_NAVSS0_MODSS"}, {303, "J7200_DEV_MCU_NAVSS0_UDMASS"}, {304, "J7200_DEV_DEBUGSS_WRAP0"}, {305, "J7200_DEV_FFI_MAIN_INFRA_CBASS_VD"}, {306, "J7200_DEV_FFI_MAIN_IP_CBASS_VD"}, {307, "J7200_DEV_FFI_MAIN_RC_CBASS_VD"}, {308, "J7200_DEV_MCU_TIMER1_CLKSEL_VD"}, {309, "J7200_DEV_MCU_TIMER3_CLKSEL_VD"}, {310, "J7200_DEV_MCU_TIMER5_CLKSEL_VD"}, {311, "J7200_DEV_MCU_TIMER7_CLKSEL_VD"}, {312, "J7200_DEV_MCU_TIMER9_CLKSEL_VD"}, {313, "J7200_DEV_TIMER1_CLKSEL_VD"}, {314, "J7200_DEV_TIMER3_CLKSEL_VD"}, {315, "J7200_DEV_TIMER5_CLKSEL_VD"}, {316, "J7200_DEV_TIMER7_CLKSEL_VD"}, {317, "J7200_DEV_TIMER9_CLKSEL_VD"}, {318, "J7200_DEV_TIMER11_CLKSEL_VD"}, {319, "J7200_DEV_TIMER13_CLKSEL_VD"}, {320, "J7200_DEV_TIMER15_CLKSEL_VD"}, {321, "J7200_DEV_TIMER17_CLKSEL_VD"}, {322, "J7200_DEV_TIMER19_CLKSEL_VD"}, }; k3conf_0.3/soc/j7200/j7200_sec_proxy_info.c0000664000175000017500000001433614375734376015137 0ustar /* * J7200 Sec Proxy Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_sec_proxy_info j7200_main_sp_info[] = { {148, "read", 9, "DM", "nonsec_high_priority_rx"}, {147, "read", 36, "DM", "nonsec_low_priority_rx"}, {146, "read", 9, "DM", "nonsec_notify_resp_rx"}, {145, "write", 2, "DM", "nonsec_A72_2_notify_tx"}, {144, "write", 22, "DM", "nonsec_A72_2_response_tx"}, {143, "write", 2, "DM", "nonsec_A72_3_notify_tx"}, {142, "write", 7, "DM", "nonsec_A72_3_response_tx"}, {141, "write", 2, "DM", "nonsec_A72_4_notify_tx"}, {140, "write", 7, "DM", "nonsec_A72_4_response_tx"}, {139, "write", 2, "DM", "nonsec_MAIN_0_R5_0_notify_tx"}, {138, "write", 7, "DM", "nonsec_MAIN_0_R5_0_response_tx"}, {137, "write", 1, "DM", "nonsec_MAIN_0_R5_2_notify_tx"}, {136, "write", 2, "DM", "nonsec_MAIN_0_R5_2_response_tx"}, {0, "read", 2, "A72_0", "notify"}, {1, "read", 30, "A72_0", "response"}, {2, "write", 10, "A72_0", "high_priority"}, {3, "write", 20, "A72_0", "low_priority"}, {4, "write", 2, "A72_0", "notify_resp"}, {5, "read", 2, "A72_1", "notify"}, {6, "read", 30, "A72_1", "response"}, {7, "write", 10, "A72_1", "high_priority"}, {8, "write", 20, "A72_1", "low_priority"}, {9, "write", 2, "A72_1", "notify_resp"}, {10, "read", 2, "A72_2", "notify"}, {11, "read", 22, "A72_2", "response"}, {12, "write", 2, "A72_2", "high_priority"}, {13, "write", 20, "A72_2", "low_priority"}, {14, "write", 2, "A72_2", "notify_resp"}, {15, "read", 2, "A72_3", "notify"}, {16, "read", 7, "A72_3", "response"}, {17, "write", 2, "A72_3", "high_priority"}, {18, "write", 5, "A72_3", "low_priority"}, {19, "write", 2, "A72_3", "notify_resp"}, {20, "read", 2, "A72_4", "notify"}, {21, "read", 7, "A72_4", "response"}, {22, "write", 2, "A72_4", "high_priority"}, {23, "write", 5, "A72_4", "low_priority"}, {24, "write", 2, "A72_4", "notify_resp"}, {25, "read", 2, "MAIN_0_R5_0", "notify"}, {26, "read", 7, "MAIN_0_R5_0", "response"}, {27, "write", 2, "MAIN_0_R5_0", "high_priority"}, {28, "write", 5, "MAIN_0_R5_0", "low_priority"}, {29, "write", 2, "MAIN_0_R5_0", "notify_resp"}, {30, "read", 2, "MAIN_0_R5_1", "notify"}, {31, "read", 7, "MAIN_0_R5_1", "response"}, {32, "write", 2, "MAIN_0_R5_1", "high_priority"}, {33, "write", 5, "MAIN_0_R5_1", "low_priority"}, {34, "write", 2, "MAIN_0_R5_1", "notify_resp"}, {35, "read", 1, "MAIN_0_R5_2", "notify"}, {36, "read", 2, "MAIN_0_R5_2", "response"}, {37, "write", 1, "MAIN_0_R5_2", "high_priority"}, {38, "write", 1, "MAIN_0_R5_2", "low_priority"}, {39, "write", 1, "MAIN_0_R5_2", "notify_resp"}, {40, "read", 1, "MAIN_0_R5_3", "notify"}, {41, "read", 2, "MAIN_0_R5_3", "response"}, {42, "write", 1, "MAIN_0_R5_3", "high_priority"}, {43, "write", 1, "MAIN_0_R5_3", "low_priority"}, {44, "write", 1, "MAIN_0_R5_3", "notify_resp"}, }; struct ti_sci_sec_proxy_info j7200_mcu_sp_info[] = { {80, "read", 15, "DM", "nonsec_high_priority_rx"}, {79, "read", 15, "DM", "nonsec_low_priority_rx"}, {78, "read", 5, "DM", "nonsec_notify_resp_rx"}, {77, "write", 2, "DM", "nonsec_MCU_0_R5_0_notify_tx"}, {76, "write", 20, "DM", "nonsec_MCU_0_R5_0_response_tx"}, {75, "write", 1, "DM", "nonsec_MCU_0_R5_2_notify_tx"}, {74, "write", 2, "DM", "nonsec_MCU_0_R5_2_response_tx"}, {73, "write", 2, "DM", "nonsec_DMSC2DM_notify_tx"}, {72, "write", 4, "DM", "nonsec_DMSC2DM_response_tx"}, {0, "read", 2, "MCU_0_R5_0", "notify"}, {1, "read", 20, "MCU_0_R5_0", "response"}, {2, "write", 10, "MCU_0_R5_0", "high_priority"}, {3, "write", 10, "MCU_0_R5_0", "low_priority"}, {4, "write", 2, "MCU_0_R5_0", "notify_resp"}, {5, "read", 2, "MCU_0_R5_1", "notify"}, {6, "read", 20, "MCU_0_R5_1", "response"}, {7, "write", 10, "MCU_0_R5_1", "high_priority"}, {8, "write", 10, "MCU_0_R5_1", "low_priority"}, {9, "write", 2, "MCU_0_R5_1", "notify_resp"}, {10, "read", 1, "MCU_0_R5_2", "notify"}, {11, "read", 2, "MCU_0_R5_2", "response"}, {12, "write", 1, "MCU_0_R5_2", "high_priority"}, {13, "write", 1, "MCU_0_R5_2", "low_priority"}, {14, "write", 1, "MCU_0_R5_2", "notify_resp"}, {15, "read", 1, "MCU_0_R5_3", "notify"}, {16, "read", 2, "MCU_0_R5_3", "response"}, {17, "write", 1, "MCU_0_R5_3", "high_priority"}, {18, "write", 1, "MCU_0_R5_3", "low_priority"}, {19, "write", 1, "MCU_0_R5_3", "notify_resp"}, {20, "read", 2, "DM2DMSC", "notify"}, {21, "read", 4, "DM2DMSC", "response"}, {22, "write", 2, "DM2DMSC", "high_priority"}, {23, "write", 2, "DM2DMSC", "low_priority"}, {24, "write", 2, "DM2DMSC", "notify_resp"}, {25, "read", 2, "DMSC2DM", "notify"}, {26, "read", 4, "DMSC2DM", "response"}, {27, "write", 4, "DMSC2DM", "high_priority"}, {28, "write", 4, "DMSC2DM", "low_priority"}, {29, "write", 2, "DMSC2DM", "notify_resp"}, }; k3conf_0.3/soc/j7200/j7200_sec_proxy_info.h0000664000175000017500000000365014375734376015141 0ustar /* * J7200 Sec Proxy Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __J7200_SEC_PROXY_INFO_H #define __J7200_SEC_PROXY_INFO_H #define J7200_MAIN_SEC_PROXY_THREADS 58 #define J7200_MCU_SEC_PROXY_THREADS 39 extern struct ti_sci_sec_proxy_info j7200_main_sp_info[]; extern struct ti_sci_sec_proxy_info j7200_mcu_sp_info[]; #endif /* __J7200_SEC_PROXY_INFO_H */ k3conf_0.3/soc/j7200/j7200_ddr_info.h0000664000175000017500000000343314504336530013656 0ustar /* * J7200 DDR performance information * * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __J7200_DDRBW_INFO_H #define __J7200_DDRBW_INFO_H extern struct ddr_perf_soc_info j7200_ddr_perf_info; #endif /* __J7200_DDRBW_INFO_H */ k3conf_0.3/soc/j7200/j7200_host_info.h0000664000175000017500000000453414375734376014105 0ustar /* * J7200 Host Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __J7200_HOST_INFO_H #define __J7200_HOST_INFO_H #define J7200_HOST_ID_DMSC 0 #define J7200_HOST_ID_MCU_0_R5_0 3 #define J7200_HOST_ID_MCU_0_R5_1 4 #define J7200_HOST_ID_MCU_0_R5_2 5 #define J7200_HOST_ID_MCU_0_R5_3 6 #define J7200_HOST_ID_A72_0 10 #define J7200_HOST_ID_A72_1 11 #define J7200_HOST_ID_A72_2 12 #define J7200_HOST_ID_A72_3 13 #define J7200_HOST_ID_A72_4 14 #define J7200_HOST_ID_MAIN_0_R5_0 35 #define J7200_HOST_ID_MAIN_0_R5_1 36 #define J7200_HOST_ID_MAIN_0_R5_2 37 #define J7200_HOST_ID_MAIN_0_R5_3 38 #define J7200_HOST_ID_DM2DMSC 250 #define J7200_HOST_ID_DMSC2DM 251 #define J7200_HOST_ID_DM 254 #define J7200_MAX_HOST_IDS 17 extern struct ti_sci_host_info j7200_host_info[]; #endif /* __J7200_HOST_INFO_H */ k3conf_0.3/soc/j784s4/0000775000175000017500000000000014456530612011300 5ustar k3conf_0.3/soc/j784s4/j784s4_devices_info.h0000664000175000017500000000347214375734376015154 0ustar /* * J784S4 Devices Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __J784S4_DEVICES_INFO_H #define __J784S4_DEVICES_INFO_H #define J784S4_MAX_DEVICES 398 extern struct ti_sci_devices_info j784s4_devices_info[]; #endif /* __J784S4_DEVICES_INFO_H */ k3conf_0.3/soc/j784s4/j784s4_processors_info.h0000664000175000017500000000351514375734376015732 0ustar /* * J784S4 Processor Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __J784S4_PROCESSOR_INFO_H #define __J784S4_PROCESSOR_INFO_H #define J784S4_MAX_PROCESSORS_IDS 21 extern struct ti_sci_processors_info j784s4_processors_info[]; #endif /* __J784S4_PROCESSOR_INFO_H */ k3conf_0.3/soc/j784s4/j784s4_processors_info.c0000664000175000017500000000473514375734376015732 0ustar /* * J784S4 Processor Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_processors_info j784s4_processors_info[] = { {202, 0, 0x20, "A72SS0_CORE0"}, {203, 0, 0x21, "A72SS0_CORE1"}, {204, 0, 0x22, "A72SS0_CORE2"}, {205, 0, 0x23, "A72SS0_CORE3"}, {206, 0, 0x24, "A72SS1_CORE0"}, {207, 0, 0x25, "A72SS1_CORE1"}, {208, 0, 0x26, "A72SS1_CORE2"}, {209, 0, 0x27, "A72SS1_CORE3"}, {31, 0, 0x30, "COMPUTE_CLUSTER0_C71SS0_CORE0"}, {34, 0, 0x31, "COMPUTE_CLUSTER0_C71SS1_CORE0"}, {38, 0, 0x32, "COMPUTE_CLUSTER0_C71SS2_CORE0"}, {41, 0, 0x33, "COMPUTE_CLUSTER0_C71SS3_CORE0"}, {346, 0, 0x01, "MCU_R5FSS0_CORE0"}, {347, 0, 0x02, "MCU_R5FSS0_CORE1"}, {339, 0, 0x06, "R5FSS0_CORE0"}, {340, 0, 0x07, "R5FSS0_CORE1"}, {341, 0, 0x08, "R5FSS1_CORE0"}, {342, 0, 0x09, "R5FSS1_CORE1"}, {343, 0, 0x0A, "R5FSS2_CORE0"}, {344, 0, 0x0B, "R5FSS2_CORE1"}, {371, 0, 0x80, "WKUP_HSM0"}, }; k3conf_0.3/soc/j784s4/j784s4_sec_proxy_info.h0000664000175000017500000000366114375734376015545 0ustar /* * J784S4 Sec Proxy Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __J784S4_SEC_PROXY_INFO_H #define __J784S4_SEC_PROXY_INFO_H #define J784S4_MAIN_SEC_PROXY_THREADS 182 #define J784S4_MCU_SEC_PROXY_THREADS 44 extern struct ti_sci_sec_proxy_info j784s4_main_sp_info[]; extern struct ti_sci_sec_proxy_info j784s4_mcu_sp_info[]; #endif /* __J784S4_SEC_PROXY_INFO_H */ k3conf_0.3/soc/j784s4/j784s4_clocks_info.c0000664000175000017500000070363514375734376015013 0ustar /* * J784S4 Clocks Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_clocks_info j784s4_clocks_info[] = { {198, 0, "DEV_A72SS0_ARM0_CLK_CLK", "Input clock"}, {198, 2, "DEV_A72SS0_ARM0_DIVH_CLK8_OBSCLK_OUT_CLK", "Output clock"}, {198, 3, "DEV_A72SS0_ARM0_MSMC_CLK_CLK", "Input clock"}, {198, 4, "DEV_A72SS0_ARM0_PLL_CTRL_CLK_CLK", "Input clock"}, {202, 0, "DEV_A72SS0_CORE0_ARM0_CLK_CLK", "Input clock"}, {203, 0, "DEV_A72SS0_CORE1_ARM0_CLK_CLK", "Input clock"}, {204, 0, "DEV_A72SS0_CORE2_ARM0_CLK_CLK", "Input clock"}, {205, 0, "DEV_A72SS0_CORE3_ARM0_CLK_CLK", "Input clock"}, {200, 0, "DEV_A72SS1_ARM1_CLK_CLK", "Input clock"}, {200, 2, "DEV_A72SS1_ARM1_DIVH_CLK8_OBSCLK_OUT_CLK", "Output clock"}, {200, 6, "DEV_A72SS1_ARM1_PLL_CTRL_CLK_CLK", "Input clock"}, {206, 0, "DEV_A72SS1_CORE0_ARM1_CLK_CLK", "Input clock"}, {207, 0, "DEV_A72SS1_CORE1_ARM1_CLK_CLK", "Input clock"}, {208, 0, "DEV_A72SS1_CORE2_ARM1_CLK_CLK", "Input clock"}, {209, 0, "DEV_A72SS1_CORE3_ARM1_CLK_CLK", "Input clock"}, {186, 0, "DEV_AGGR_ATB0_DBG_CLK", "Input clock"}, {2, 0, "DEV_ATL0_ATL_CLK", "Input muxed clock"}, {2, 1, "DEV_ATL0_ATL_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT1_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"}, {2, 2, "DEV_ATL0_ATL_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"}, {2, 5, "DEV_ATL0_ATL_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"}, {2, 6, "DEV_ATL0_ATL_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_CLK"}, {2, 7, "DEV_ATL0_ATL_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_CLK"}, {2, 9, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT", "Output clock"}, {2, 10, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_1", "Output clock"}, {2, 11, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_2", "Output clock"}, {2, 12, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_3", "Output clock"}, {2, 13, "DEV_ATL0_ATL_IO_PORT_AWS", "Input muxed clock"}, {2, 14, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"}, {2, 15, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"}, {2, 16, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"}, {2, 17, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"}, {2, 18, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"}, {2, 26, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"}, {2, 27, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"}, {2, 28, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"}, {2, 29, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"}, {2, 30, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"}, {2, 38, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"}, {2, 39, "DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS"}, {2, 46, "DEV_ATL0_ATL_IO_PORT_AWS_1", "Input muxed clock"}, {2, 47, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"}, {2, 48, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"}, {2, 49, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"}, {2, 50, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"}, {2, 51, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"}, {2, 59, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"}, {2, 60, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"}, {2, 61, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"}, {2, 62, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"}, {2, 63, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"}, {2, 71, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"}, {2, 72, "DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1"}, {2, 85, "DEV_ATL0_ATL_IO_PORT_AWS_2", "Input muxed clock"}, {2, 86, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"}, {2, 87, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"}, {2, 88, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"}, {2, 89, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"}, {2, 90, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"}, {2, 98, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"}, {2, 99, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"}, {2, 100, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"}, {2, 101, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"}, {2, 102, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"}, {2, 110, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"}, {2, 111, "DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2"}, {2, 118, "DEV_ATL0_ATL_IO_PORT_AWS_3", "Input muxed clock"}, {2, 119, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"}, {2, 120, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"}, {2, 121, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"}, {2, 122, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"}, {2, 123, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"}, {2, 131, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"}, {2, 132, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"}, {2, 133, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"}, {2, 134, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"}, {2, 135, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"}, {2, 143, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"}, {2, 144, "DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3"}, {2, 157, "DEV_ATL0_ATL_IO_PORT_BWS", "Input muxed clock"}, {2, 158, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"}, {2, 159, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"}, {2, 160, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"}, {2, 161, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"}, {2, 162, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"}, {2, 170, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"}, {2, 171, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"}, {2, 172, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"}, {2, 173, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"}, {2, 174, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"}, {2, 182, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"}, {2, 183, "DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS"}, {2, 190, "DEV_ATL0_ATL_IO_PORT_BWS_1", "Input muxed clock"}, {2, 191, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"}, {2, 192, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"}, {2, 193, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"}, {2, 194, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"}, {2, 195, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"}, {2, 203, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"}, {2, 204, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"}, {2, 205, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"}, {2, 206, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"}, {2, 207, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"}, {2, 215, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"}, {2, 216, "DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1"}, {2, 229, "DEV_ATL0_ATL_IO_PORT_BWS_2", "Input muxed clock"}, {2, 230, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"}, {2, 231, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"}, {2, 232, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"}, {2, 233, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"}, {2, 234, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"}, {2, 242, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"}, {2, 243, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"}, {2, 244, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"}, {2, 245, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"}, {2, 246, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"}, {2, 254, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"}, {2, 255, "DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2"}, {2, 262, "DEV_ATL0_ATL_IO_PORT_BWS_3", "Input muxed clock"}, {2, 263, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"}, {2, 264, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"}, {2, 265, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"}, {2, 266, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"}, {2, 267, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"}, {2, 275, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"}, {2, 276, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"}, {2, 277, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"}, {2, 278, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"}, {2, 279, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"}, {2, 287, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"}, {2, 288, "DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3"}, {2, 301, "DEV_ATL0_VBUS_CLK", "Input clock"}, {157, 0, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN", "Input muxed clock"}, {157, 1, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 2, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 3, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 4, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 5, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 13, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 14, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 15, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 16, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 17, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 25, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 26, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 27, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 28, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 29, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 33, "DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT", "Output clock"}, {157, 34, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN", "Input muxed clock"}, {157, 35, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 36, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 37, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 38, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 39, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 47, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 48, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 49, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 50, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 51, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 59, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 60, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 61, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 62, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 63, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 67, "DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT", "Output clock"}, {157, 68, "DEV_BOARD0_CPTS0_RFT_CLK_OUT", "Output clock"}, {157, 69, "DEV_BOARD0_CSI0_RXCLKN_OUT", "Output clock"}, {157, 70, "DEV_BOARD0_CSI0_RXCLKP_OUT", "Output clock"}, {157, 71, "DEV_BOARD0_CSI0_TXCLKN_IN", "Input clock"}, {157, 72, "DEV_BOARD0_CSI0_TXCLKP_IN", "Input clock"}, {157, 73, "DEV_BOARD0_CSI1_RXCLKN_OUT", "Output clock"}, {157, 74, "DEV_BOARD0_CSI1_RXCLKP_OUT", "Output clock"}, {157, 75, "DEV_BOARD0_CSI1_TXCLKN_IN", "Input clock"}, {157, 76, "DEV_BOARD0_CSI1_TXCLKP_IN", "Input clock"}, {157, 77, "DEV_BOARD0_CSI2_RXCLKN_OUT", "Output clock"}, {157, 78, "DEV_BOARD0_CSI2_RXCLKP_OUT", "Output clock"}, {157, 95, "DEV_BOARD0_DSI0_TXCLKN_IN", "Input clock"}, {157, 96, "DEV_BOARD0_DSI0_TXCLKP_IN", "Input clock"}, {157, 97, "DEV_BOARD0_DSI1_TXCLKN_IN", "Input clock"}, {157, 98, "DEV_BOARD0_DSI1_TXCLKP_IN", "Input clock"}, {157, 99, "DEV_BOARD0_EXT_REFCLK1_OUT", "Output clock"}, {157, 100, "DEV_BOARD0_GPMC0_CLKOUT_IN", "Input clock"}, {157, 101, "DEV_BOARD0_GPMC0_CLK_OUT", "Output clock"}, {157, 102, "DEV_BOARD0_GPMC0_FCLK_MUX_IN", "Input clock"}, {157, 103, "DEV_BOARD0_HYP0_RXFLCLK_IN", "Input clock"}, {157, 104, "DEV_BOARD0_HYP0_RXPMCLK_OUT", "Output clock"}, {157, 105, "DEV_BOARD0_HYP0_TXFLCLK_OUT", "Output clock"}, {157, 106, "DEV_BOARD0_HYP0_TXPMCLK_IN", "Input clock"}, {157, 107, "DEV_BOARD0_HYP1_RXFLCLK_IN", "Input clock"}, {157, 108, "DEV_BOARD0_HYP1_RXPMCLK_OUT", "Output clock"}, {157, 109, "DEV_BOARD0_HYP1_TXFLCLK_OUT", "Output clock"}, {157, 110, "DEV_BOARD0_HYP1_TXPMCLK_IN", "Input clock"}, {157, 111, "DEV_BOARD0_I2C0_SCL_IN", "Input clock"}, {157, 112, "DEV_BOARD0_I2C0_SCL_OUT", "Output clock"}, {157, 113, "DEV_BOARD0_I2C1_SCL_IN", "Input clock"}, {157, 114, "DEV_BOARD0_I2C1_SCL_OUT", "Output clock"}, {157, 115, "DEV_BOARD0_I2C2_SCL_IN", "Input clock"}, {157, 116, "DEV_BOARD0_I2C2_SCL_OUT", "Output clock"}, {157, 117, "DEV_BOARD0_I2C3_SCL_IN", "Input clock"}, {157, 118, "DEV_BOARD0_I2C3_SCL_OUT", "Output clock"}, {157, 119, "DEV_BOARD0_I2C4_SCL_IN", "Input clock"}, {157, 120, "DEV_BOARD0_I2C4_SCL_OUT", "Output clock"}, {157, 121, "DEV_BOARD0_I2C5_SCL_IN", "Input clock"}, {157, 122, "DEV_BOARD0_I2C5_SCL_OUT", "Output clock"}, {157, 123, "DEV_BOARD0_I2C6_SCL_IN", "Input clock"}, {157, 124, "DEV_BOARD0_I2C6_SCL_OUT", "Output clock"}, {157, 125, "DEV_BOARD0_LED_CLK_OUT", "Output clock"}, {157, 126, "DEV_BOARD0_MCAN0_RX_OUT", "Output clock"}, {157, 127, "DEV_BOARD0_MCAN10_RX_OUT", "Output clock"}, {157, 128, "DEV_BOARD0_MCAN11_RX_OUT", "Output clock"}, {157, 129, "DEV_BOARD0_MCAN12_RX_OUT", "Output clock"}, {157, 130, "DEV_BOARD0_MCAN13_RX_OUT", "Output clock"}, {157, 131, "DEV_BOARD0_MCAN14_RX_OUT", "Output clock"}, {157, 132, "DEV_BOARD0_MCAN15_RX_OUT", "Output clock"}, {157, 133, "DEV_BOARD0_MCAN16_RX_OUT", "Output clock"}, {157, 134, "DEV_BOARD0_MCAN17_RX_OUT", "Output clock"}, {157, 135, "DEV_BOARD0_MCAN1_RX_OUT", "Output clock"}, {157, 136, "DEV_BOARD0_MCAN2_RX_OUT", "Output clock"}, {157, 137, "DEV_BOARD0_MCAN3_RX_OUT", "Output clock"}, {157, 138, "DEV_BOARD0_MCAN4_RX_OUT", "Output clock"}, {157, 139, "DEV_BOARD0_MCAN5_RX_OUT", "Output clock"}, {157, 140, "DEV_BOARD0_MCAN6_RX_OUT", "Output clock"}, {157, 141, "DEV_BOARD0_MCAN7_RX_OUT", "Output clock"}, {157, 142, "DEV_BOARD0_MCAN8_RX_OUT", "Output clock"}, {157, 143, "DEV_BOARD0_MCAN9_RX_OUT", "Output clock"}, {157, 144, "DEV_BOARD0_MCASP0_ACLKR_IN", "Input clock"}, {157, 145, "DEV_BOARD0_MCASP0_ACLKR_OUT", "Output clock"}, {157, 146, "DEV_BOARD0_MCASP0_ACLKX_IN", "Input clock"}, {157, 147, "DEV_BOARD0_MCASP0_ACLKX_OUT", "Output clock"}, {157, 148, "DEV_BOARD0_MCASP0_AFSR_OUT", "Output clock"}, {157, 149, "DEV_BOARD0_MCASP0_AFSX_OUT", "Output clock"}, {157, 150, "DEV_BOARD0_MCASP1_ACLKR_IN", "Input clock"}, {157, 151, "DEV_BOARD0_MCASP1_ACLKR_OUT", "Output clock"}, {157, 152, "DEV_BOARD0_MCASP1_ACLKX_IN", "Input clock"}, {157, 153, "DEV_BOARD0_MCASP1_ACLKX_OUT", "Output clock"}, {157, 154, "DEV_BOARD0_MCASP1_AFSR_OUT", "Output clock"}, {157, 155, "DEV_BOARD0_MCASP1_AFSX_OUT", "Output clock"}, {157, 156, "DEV_BOARD0_MCASP2_ACLKR_IN", "Input clock"}, {157, 157, "DEV_BOARD0_MCASP2_ACLKR_OUT", "Output clock"}, {157, 158, "DEV_BOARD0_MCASP2_ACLKX_IN", "Input clock"}, {157, 159, "DEV_BOARD0_MCASP2_ACLKX_OUT", "Output clock"}, {157, 160, "DEV_BOARD0_MCASP2_AFSR_OUT", "Output clock"}, {157, 161, "DEV_BOARD0_MCASP2_AFSX_OUT", "Output clock"}, {157, 162, "DEV_BOARD0_MCASP3_ACLKR_IN", "Input clock"}, {157, 163, "DEV_BOARD0_MCASP3_ACLKR_OUT", "Output clock"}, {157, 164, "DEV_BOARD0_MCASP3_ACLKX_IN", "Input clock"}, {157, 165, "DEV_BOARD0_MCASP3_ACLKX_OUT", "Output clock"}, {157, 166, "DEV_BOARD0_MCASP3_AFSR_OUT", "Output clock"}, {157, 167, "DEV_BOARD0_MCASP3_AFSX_OUT", "Output clock"}, {157, 168, "DEV_BOARD0_MCASP4_ACLKR_IN", "Input clock"}, {157, 169, "DEV_BOARD0_MCASP4_ACLKR_OUT", "Output clock"}, {157, 170, "DEV_BOARD0_MCASP4_ACLKX_IN", "Input clock"}, {157, 171, "DEV_BOARD0_MCASP4_ACLKX_OUT", "Output clock"}, {157, 172, "DEV_BOARD0_MCASP4_AFSR_OUT", "Output clock"}, {157, 173, "DEV_BOARD0_MCASP4_AFSX_OUT", "Output clock"}, {157, 174, "DEV_BOARD0_MCU_CLKOUT0_IN", "Input muxed clock"}, {157, 175, "DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK5", "Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN"}, {157, 176, "DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK10", "Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN"}, {157, 177, "DEV_BOARD0_MCU_CPTS0_RFT_CLK_OUT", "Output clock"}, {157, 178, "DEV_BOARD0_MCU_EXT_REFCLK0_OUT", "Output clock"}, {157, 179, "DEV_BOARD0_MCU_HYPERBUS0_CK_IN", "Input clock"}, {157, 180, "DEV_BOARD0_MCU_HYPERBUS0_CKN_IN", "Input clock"}, {157, 181, "DEV_BOARD0_MCU_I2C0_SCL_IN", "Input clock"}, {157, 182, "DEV_BOARD0_MCU_I2C0_SCL_OUT", "Output clock"}, {157, 183, "DEV_BOARD0_MCU_I2C1_SCL_IN", "Input clock"}, {157, 184, "DEV_BOARD0_MCU_I2C1_SCL_OUT", "Output clock"}, {157, 185, "DEV_BOARD0_MCU_I3C0_SCL_IN", "Input clock"}, {157, 186, "DEV_BOARD0_MCU_I3C0_SCL_OUT", "Output clock"}, {157, 187, "DEV_BOARD0_MCU_I3C0_SDA_OUT", "Output clock"}, {157, 188, "DEV_BOARD0_MCU_MCAN0_RX_OUT", "Output clock"}, {157, 189, "DEV_BOARD0_MCU_MCAN1_RX_OUT", "Output clock"}, {157, 190, "DEV_BOARD0_MCU_MDIO0_MDC_IN", "Input clock"}, {157, 191, "DEV_BOARD0_MCU_OBSCLK0_IN", "Input muxed clock"}, {157, 192, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"}, {157, 193, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"}, {157, 224, "DEV_BOARD0_MCU_OSPI0_CLK_IN", "Input clock"}, {157, 225, "DEV_BOARD0_MCU_OSPI0_DQS_OUT", "Output clock"}, {157, 226, "DEV_BOARD0_MCU_OSPI0_LBCLKO_IN", "Input clock"}, {157, 227, "DEV_BOARD0_MCU_OSPI0_LBCLKO_OUT", "Output clock"}, {157, 228, "DEV_BOARD0_MCU_OSPI1_CLK_IN", "Input clock"}, {157, 229, "DEV_BOARD0_MCU_OSPI1_DQS_OUT", "Output clock"}, {157, 230, "DEV_BOARD0_MCU_OSPI1_LBCLKO_IN", "Input clock"}, {157, 231, "DEV_BOARD0_MCU_OSPI1_LBCLKO_OUT", "Output clock"}, {157, 232, "DEV_BOARD0_MCU_RGMII1_RXC_OUT", "Output clock"}, {157, 233, "DEV_BOARD0_MCU_RGMII1_TXC_IN", "Input clock"}, {157, 234, "DEV_BOARD0_MCU_RMII1_REF_CLK_OUT", "Output clock"}, {157, 235, "DEV_BOARD0_MCU_SPI0_CLK_IN", "Input clock"}, {157, 236, "DEV_BOARD0_MCU_SPI0_CLK_OUT", "Output clock"}, {157, 237, "DEV_BOARD0_MCU_SPI1_CLK_IN", "Input clock"}, {157, 238, "DEV_BOARD0_MCU_SPI1_CLK_OUT", "Output clock"}, {157, 239, "DEV_BOARD0_MCU_SYSCLKOUT0_IN", "Input clock"}, {157, 240, "DEV_BOARD0_MDIO0_MDC_IN", "Input clock"}, {157, 241, "DEV_BOARD0_MDIO1_MDC_IN", "Input clock"}, {157, 243, "DEV_BOARD0_MMC1_CLKLB_IN", "Input clock"}, {157, 244, "DEV_BOARD0_MMC1_CLKLB_OUT", "Output clock"}, {157, 245, "DEV_BOARD0_MMC1_CLK_IN", "Input clock"}, {157, 246, "DEV_BOARD0_MMC1_CLK_OUT", "Output clock"}, {157, 247, "DEV_BOARD0_OBSCLK0_IN", "Input clock"}, {157, 248, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 249, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 250, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 251, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 252, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 253, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_5_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 254, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_6_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 255, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_26_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 256, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_27_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 257, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_28_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 260, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 261, "DEV_BOARD0_OBSCLK0_IN_PARENT_OBSCLK1_MUX_OUT0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 262, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_14_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 264, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 265, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 267, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 268, "DEV_BOARD0_OBSCLK0_IN_PARENT_UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_MPHY_TX_REF_SYMBOLCLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 269, "DEV_BOARD0_OBSCLK0_IN_PARENT_UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_MPHY_M31_VCO_19P2M_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 270, "DEV_BOARD0_OBSCLK0_IN_PARENT_UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_MPHY_M31_VCO_26M_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 273, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 274, "DEV_BOARD0_OBSCLK0_IN_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 275, "DEV_BOARD0_OBSCLK0_IN_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 276, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 277, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 278, "DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 279, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 280, "DEV_BOARD0_OBSCLK1_IN", "Input clock"}, {157, 281, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 282, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 283, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 284, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 285, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 286, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_5_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 287, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_6_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 288, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_26_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 289, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_27_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 290, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_28_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 293, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 294, "DEV_BOARD0_OBSCLK1_IN_PARENT_OBSCLK1_MUX_OUT0", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 295, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_14_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 297, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 298, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 300, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 301, "DEV_BOARD0_OBSCLK1_IN_PARENT_UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_MPHY_TX_REF_SYMBOLCLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 302, "DEV_BOARD0_OBSCLK1_IN_PARENT_UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_MPHY_M31_VCO_19P2M_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 303, "DEV_BOARD0_OBSCLK1_IN_PARENT_UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_MPHY_M31_VCO_26M_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 306, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 307, "DEV_BOARD0_OBSCLK1_IN_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 308, "DEV_BOARD0_OBSCLK1_IN_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 309, "DEV_BOARD0_OBSCLK1_IN_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 310, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 311, "DEV_BOARD0_OBSCLK1_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 312, "DEV_BOARD0_OBSCLK1_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"}, {157, 313, "DEV_BOARD0_PCIE_REFCLK0_N_OUT_IN", "Input clock"}, {157, 314, "DEV_BOARD0_PCIE_REFCLK0_P_OUT_IN", "Input clock"}, {157, 315, "DEV_BOARD0_PCIE_REFCLK1_N_OUT_IN", "Input clock"}, {157, 316, "DEV_BOARD0_PCIE_REFCLK1_P_OUT_IN", "Input clock"}, {157, 317, "DEV_BOARD0_PCIE_REFCLK2_N_OUT_IN", "Input clock"}, {157, 318, "DEV_BOARD0_PCIE_REFCLK2_P_OUT_IN", "Input clock"}, {157, 319, "DEV_BOARD0_PCIE_REFCLK3_N_OUT_IN", "Input clock"}, {157, 320, "DEV_BOARD0_PCIE_REFCLK3_P_OUT_IN", "Input clock"}, {157, 321, "DEV_BOARD0_RGMII1_RXC_OUT", "Output clock"}, {157, 322, "DEV_BOARD0_RGMII1_TXC_IN", "Input clock"}, {157, 323, "DEV_BOARD0_RMII_REF_CLK_OUT", "Output clock"}, {157, 324, "DEV_BOARD0_SERDES0_REFCLK_N_IN", "Input clock"}, {157, 325, "DEV_BOARD0_SERDES0_REFCLK_N_OUT", "Output clock"}, {157, 326, "DEV_BOARD0_SERDES0_REFCLK_P_IN", "Input clock"}, {157, 327, "DEV_BOARD0_SERDES0_REFCLK_P_OUT", "Output clock"}, {157, 328, "DEV_BOARD0_SERDES1_REFCLK_N_IN", "Input clock"}, {157, 329, "DEV_BOARD0_SERDES1_REFCLK_N_OUT", "Output clock"}, {157, 330, "DEV_BOARD0_SERDES1_REFCLK_P_IN", "Input clock"}, {157, 331, "DEV_BOARD0_SERDES1_REFCLK_P_OUT", "Output clock"}, {157, 332, "DEV_BOARD0_SERDES2_REFCLK_N_IN", "Input clock"}, {157, 333, "DEV_BOARD0_SERDES2_REFCLK_N_OUT", "Output clock"}, {157, 334, "DEV_BOARD0_SERDES2_REFCLK_P_IN", "Input clock"}, {157, 335, "DEV_BOARD0_SERDES2_REFCLK_P_OUT", "Output clock"}, {157, 336, "DEV_BOARD0_SERDES4_REFCLK_N_IN", "Input clock"}, {157, 337, "DEV_BOARD0_SERDES4_REFCLK_N_OUT", "Output clock"}, {157, 338, "DEV_BOARD0_SERDES4_REFCLK_P_IN", "Input clock"}, {157, 339, "DEV_BOARD0_SERDES4_REFCLK_P_OUT", "Output clock"}, {157, 340, "DEV_BOARD0_SPI0_CLK_IN", "Input clock"}, {157, 341, "DEV_BOARD0_SPI0_CLK_OUT", "Output clock"}, {157, 342, "DEV_BOARD0_SPI1_CLK_IN", "Input clock"}, {157, 343, "DEV_BOARD0_SPI1_CLK_OUT", "Output clock"}, {157, 344, "DEV_BOARD0_SPI2_CLK_IN", "Input clock"}, {157, 345, "DEV_BOARD0_SPI2_CLK_OUT", "Output clock"}, {157, 346, "DEV_BOARD0_SPI3_CLK_IN", "Input clock"}, {157, 347, "DEV_BOARD0_SPI3_CLK_OUT", "Output clock"}, {157, 348, "DEV_BOARD0_SPI5_CLK_IN", "Input clock"}, {157, 349, "DEV_BOARD0_SPI5_CLK_OUT", "Output clock"}, {157, 350, "DEV_BOARD0_SPI6_CLK_IN", "Input clock"}, {157, 351, "DEV_BOARD0_SPI6_CLK_OUT", "Output clock"}, {157, 352, "DEV_BOARD0_SPI7_CLK_IN", "Input clock"}, {157, 353, "DEV_BOARD0_SPI7_CLK_OUT", "Output clock"}, {157, 354, "DEV_BOARD0_SYSCLKOUT0_IN", "Input clock"}, {157, 355, "DEV_BOARD0_TCK_OUT", "Output clock"}, {157, 356, "DEV_BOARD0_TRC_CLK_IN", "Input clock"}, {157, 357, "DEV_BOARD0_UFS0_REF_CLK_IN", "Input clock"}, {157, 358, "DEV_BOARD0_VOUT0_EXTPCLKIN_OUT", "Output clock"}, {157, 359, "DEV_BOARD0_VOUT0_PCLK_IN", "Input clock"}, {157, 360, "DEV_BOARD0_WKUP_I2C0_SCL_IN", "Input clock"}, {157, 361, "DEV_BOARD0_WKUP_I2C0_SCL_OUT", "Output clock"}, {157, 363, "DEV_BOARD0_HFOSC1_CLK_OUT", "Output clock"}, {11, 0, "DEV_CMPEVENT_INTRTR0_INTR_CLK", "Input clock"}, {241, 0, "DEV_CODEC0_VPU_ACLK_CLK", "Input clock"}, {241, 1, "DEV_CODEC0_VPU_BCLK_CLK", "Input clock"}, {241, 2, "DEV_CODEC0_VPU_CCLK_CLK", "Input clock"}, {241, 3, "DEV_CODEC0_VPU_PCLK_CLK", "Input clock"}, {242, 0, "DEV_CODEC1_VPU_ACLK_CLK", "Input clock"}, {242, 1, "DEV_CODEC1_VPU_BCLK_CLK", "Input clock"}, {242, 2, "DEV_CODEC1_VPU_CCLK_CLK", "Input clock"}, {242, 3, "DEV_CODEC1_VPU_PCLK_CLK", "Input clock"}, {30, 3, "DEV_COMPUTE_CLUSTER0_C71SS0_C7X_CLK", "Input clock"}, {30, 4, "DEV_COMPUTE_CLUSTER0_C71SS0_C7X_DIVH_CLK4_OBSCLK_OUT_CLK", "Output clock"}, {31, 0, "DEV_COMPUTE_CLUSTER0_C71SS0_CORE0_C7X_CLK", "Input clock"}, {31, 2, "DEV_COMPUTE_CLUSTER0_C71SS0_CORE0_PLL_CTRL_CLK_CLK", "Input clock"}, {33, 3, "DEV_COMPUTE_CLUSTER0_C71SS1_C7X_CLK", "Input clock"}, {34, 0, "DEV_COMPUTE_CLUSTER0_C71SS1_CORE0_C7X_CLK", "Input clock"}, {34, 2, "DEV_COMPUTE_CLUSTER0_C71SS1_CORE0_PLL_CTRL_CLK_CLK", "Input clock"}, {37, 3, "DEV_COMPUTE_CLUSTER0_C71SS2_C7X_CLK", "Input clock"}, {38, 0, "DEV_COMPUTE_CLUSTER0_C71SS2_CORE0_C7X_CLK", "Input clock"}, {40, 3, "DEV_COMPUTE_CLUSTER0_C71SS3_C7X_CLK", "Input clock"}, {41, 0, "DEV_COMPUTE_CLUSTER0_C71SS3_CORE0_C7X_CLK", "Input clock"}, {45, 1, "DEV_COMPUTE_CLUSTER0_CORE_CORE_PSIL_LEAF_CLK", "Input clock"}, {50, 0, "DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_0_CLK1_CLK_CLK", "Input clock"}, {50, 1, "DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_0_CLK2_CLK_CLK", "Input clock"}, {58, 0, "DEV_COMPUTE_CLUSTER0_GIC500SS_VCLK_CLK", "Input clock"}, {62, 0, "DEV_CPSW1_CPPI_CLK_CLK", "Input clock"}, {62, 1, "DEV_CPSW1_CPTS_GENF0", "Output clock"}, {62, 3, "DEV_CPSW1_CPTS_RFT_CLK", "Input muxed clock"}, {62, 4, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"}, {62, 5, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"}, {62, 6, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"}, {62, 7, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"}, {62, 8, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"}, {62, 9, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"}, {62, 10, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"}, {62, 11, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"}, {62, 12, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"}, {62, 13, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"}, {62, 14, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"}, {62, 15, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"}, {62, 16, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"}, {62, 17, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"}, {62, 18, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"}, {62, 19, "DEV_CPSW1_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK"}, {62, 20, "DEV_CPSW1_GMII1_MR_CLK", "Input clock"}, {62, 21, "DEV_CPSW1_GMII1_MT_CLK", "Input clock"}, {62, 22, "DEV_CPSW1_GMII_RFT_CLK", "Input clock"}, {62, 23, "DEV_CPSW1_MDIO_MDCLK_O", "Output clock"}, {62, 24, "DEV_CPSW1_RGMII1_RXC_I", "Input clock"}, {62, 26, "DEV_CPSW1_RGMII1_TXC_O", "Output clock"}, {62, 27, "DEV_CPSW1_RGMII_MHZ_250_CLK", "Input clock"}, {62, 28, "DEV_CPSW1_RGMII_MHZ_50_CLK", "Input clock"}, {62, 29, "DEV_CPSW1_RGMII_MHZ_5_CLK", "Input clock"}, {62, 30, "DEV_CPSW1_RMII_MHZ_50_CLK", "Input clock"}, {64, 0, "DEV_CPSW_9XUSS_J7AM0_CPPI_CLK_CLK", "Input clock"}, {64, 1, "DEV_CPSW_9XUSS_J7AM0_CPTS_GENF0", "Output clock"}, {64, 3, "DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK", "Input muxed clock"}, {64, 4, "DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK"}, {64, 5, "DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK"}, {64, 6, "DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK"}, {64, 7, "DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK"}, {64, 8, "DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK"}, {64, 9, "DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK"}, {64, 10, "DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK"}, {64, 11, "DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK"}, {64, 12, "DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK", "Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK"}, {64, 13, "DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK", "Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK"}, {64, 14, "DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK"}, {64, 15, "DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK"}, {64, 16, "DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK", "Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK"}, {64, 17, "DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK", "Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK"}, {64, 18, "DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK"}, {64, 19, "DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK"}, {64, 22, "DEV_CPSW_9XUSS_J7AM0_GMII1_MR_CLK", "Input clock"}, {64, 23, "DEV_CPSW_9XUSS_J7AM0_GMII1_MT_CLK", "Input clock"}, {64, 24, "DEV_CPSW_9XUSS_J7AM0_GMII2_MR_CLK", "Input clock"}, {64, 25, "DEV_CPSW_9XUSS_J7AM0_GMII2_MT_CLK", "Input clock"}, {64, 26, "DEV_CPSW_9XUSS_J7AM0_GMII3_MR_CLK", "Input clock"}, {64, 27, "DEV_CPSW_9XUSS_J7AM0_GMII3_MT_CLK", "Input clock"}, {64, 28, "DEV_CPSW_9XUSS_J7AM0_GMII4_MR_CLK", "Input clock"}, {64, 29, "DEV_CPSW_9XUSS_J7AM0_GMII4_MT_CLK", "Input clock"}, {64, 30, "DEV_CPSW_9XUSS_J7AM0_GMII5_MR_CLK", "Input clock"}, {64, 31, "DEV_CPSW_9XUSS_J7AM0_GMII5_MT_CLK", "Input clock"}, {64, 32, "DEV_CPSW_9XUSS_J7AM0_GMII6_MR_CLK", "Input clock"}, {64, 33, "DEV_CPSW_9XUSS_J7AM0_GMII6_MT_CLK", "Input clock"}, {64, 34, "DEV_CPSW_9XUSS_J7AM0_GMII7_MR_CLK", "Input clock"}, {64, 35, "DEV_CPSW_9XUSS_J7AM0_GMII7_MT_CLK", "Input clock"}, {64, 36, "DEV_CPSW_9XUSS_J7AM0_GMII8_MR_CLK", "Input clock"}, {64, 37, "DEV_CPSW_9XUSS_J7AM0_GMII8_MT_CLK", "Input clock"}, {64, 38, "DEV_CPSW_9XUSS_J7AM0_GMII_RFT_CLK", "Input clock"}, {64, 39, "DEV_CPSW_9XUSS_J7AM0_MDIO_MDCLK_O", "Output clock"}, {64, 56, "DEV_CPSW_9XUSS_J7AM0_RGMII_MHZ_250_CLK", "Input clock"}, {64, 57, "DEV_CPSW_9XUSS_J7AM0_RGMII_MHZ_50_CLK", "Input clock"}, {64, 58, "DEV_CPSW_9XUSS_J7AM0_RGMII_MHZ_5_CLK", "Input clock"}, {64, 59, "DEV_CPSW_9XUSS_J7AM0_RMII_MHZ_50_CLK", "Input clock"}, {64, 60, "DEV_CPSW_9XUSS_J7AM0_SERDES1_REFCLK", "Input clock"}, {64, 61, "DEV_CPSW_9XUSS_J7AM0_SERDES1_RXCLK", "Input clock"}, {64, 62, "DEV_CPSW_9XUSS_J7AM0_SERDES1_RXFCLK", "Input clock"}, {64, 63, "DEV_CPSW_9XUSS_J7AM0_SERDES1_TXCLK", "Output clock"}, {64, 64, "DEV_CPSW_9XUSS_J7AM0_SERDES1_TXFCLK", "Input clock"}, {64, 65, "DEV_CPSW_9XUSS_J7AM0_SERDES1_TXMCLK", "Input clock"}, {64, 66, "DEV_CPSW_9XUSS_J7AM0_SERDES2_REFCLK", "Input clock"}, {64, 67, "DEV_CPSW_9XUSS_J7AM0_SERDES2_RXCLK", "Input clock"}, {64, 68, "DEV_CPSW_9XUSS_J7AM0_SERDES2_RXFCLK", "Input clock"}, {64, 69, "DEV_CPSW_9XUSS_J7AM0_SERDES2_TXCLK", "Output clock"}, {64, 70, "DEV_CPSW_9XUSS_J7AM0_SERDES2_TXFCLK", "Input clock"}, {64, 71, "DEV_CPSW_9XUSS_J7AM0_SERDES2_TXMCLK", "Input clock"}, {64, 72, "DEV_CPSW_9XUSS_J7AM0_SERDES3_REFCLK", "Input clock"}, {64, 73, "DEV_CPSW_9XUSS_J7AM0_SERDES3_RXCLK", "Input clock"}, {64, 74, "DEV_CPSW_9XUSS_J7AM0_SERDES3_RXFCLK", "Input clock"}, {64, 75, "DEV_CPSW_9XUSS_J7AM0_SERDES3_TXCLK", "Output clock"}, {64, 76, "DEV_CPSW_9XUSS_J7AM0_SERDES3_TXFCLK", "Input clock"}, {64, 77, "DEV_CPSW_9XUSS_J7AM0_SERDES3_TXMCLK", "Input clock"}, {64, 78, "DEV_CPSW_9XUSS_J7AM0_SERDES4_REFCLK", "Input clock"}, {64, 79, "DEV_CPSW_9XUSS_J7AM0_SERDES4_RXCLK", "Input clock"}, {64, 80, "DEV_CPSW_9XUSS_J7AM0_SERDES4_RXFCLK", "Input clock"}, {64, 81, "DEV_CPSW_9XUSS_J7AM0_SERDES4_TXCLK", "Output clock"}, {64, 82, "DEV_CPSW_9XUSS_J7AM0_SERDES4_TXFCLK", "Input clock"}, {64, 83, "DEV_CPSW_9XUSS_J7AM0_SERDES4_TXMCLK", "Input clock"}, {64, 84, "DEV_CPSW_9XUSS_J7AM0_SERDES5_REFCLK", "Input clock"}, {64, 85, "DEV_CPSW_9XUSS_J7AM0_SERDES5_RXCLK", "Input clock"}, {64, 86, "DEV_CPSW_9XUSS_J7AM0_SERDES5_RXFCLK", "Input clock"}, {64, 87, "DEV_CPSW_9XUSS_J7AM0_SERDES5_TXCLK", "Output clock"}, {64, 88, "DEV_CPSW_9XUSS_J7AM0_SERDES5_TXFCLK", "Input clock"}, {64, 89, "DEV_CPSW_9XUSS_J7AM0_SERDES5_TXMCLK", "Input clock"}, {64, 90, "DEV_CPSW_9XUSS_J7AM0_SERDES6_REFCLK", "Input clock"}, {64, 91, "DEV_CPSW_9XUSS_J7AM0_SERDES6_RXCLK", "Input clock"}, {64, 92, "DEV_CPSW_9XUSS_J7AM0_SERDES6_RXFCLK", "Input clock"}, {64, 93, "DEV_CPSW_9XUSS_J7AM0_SERDES6_TXCLK", "Output clock"}, {64, 94, "DEV_CPSW_9XUSS_J7AM0_SERDES6_TXFCLK", "Input clock"}, {64, 95, "DEV_CPSW_9XUSS_J7AM0_SERDES6_TXMCLK", "Input clock"}, {64, 96, "DEV_CPSW_9XUSS_J7AM0_SERDES7_REFCLK", "Input clock"}, {64, 97, "DEV_CPSW_9XUSS_J7AM0_SERDES7_RXCLK", "Input clock"}, {64, 98, "DEV_CPSW_9XUSS_J7AM0_SERDES7_RXFCLK", "Input clock"}, {64, 99, "DEV_CPSW_9XUSS_J7AM0_SERDES7_TXCLK", "Output clock"}, {64, 100, "DEV_CPSW_9XUSS_J7AM0_SERDES7_TXFCLK", "Input clock"}, {64, 101, "DEV_CPSW_9XUSS_J7AM0_SERDES7_TXMCLK", "Input clock"}, {64, 102, "DEV_CPSW_9XUSS_J7AM0_SERDES8_REFCLK", "Input clock"}, {64, 103, "DEV_CPSW_9XUSS_J7AM0_SERDES8_RXCLK", "Input clock"}, {64, 104, "DEV_CPSW_9XUSS_J7AM0_SERDES8_RXFCLK", "Input clock"}, {64, 105, "DEV_CPSW_9XUSS_J7AM0_SERDES8_TXCLK", "Output clock"}, {64, 106, "DEV_CPSW_9XUSS_J7AM0_SERDES8_TXFCLK", "Input clock"}, {64, 107, "DEV_CPSW_9XUSS_J7AM0_SERDES8_TXMCLK", "Input clock"}, {70, 0, "DEV_CPT2_AGGR0_VCLK_CLK", "Input clock"}, {65, 0, "DEV_CPT2_AGGR1_VCLK_CLK", "Input clock"}, {67, 0, "DEV_CPT2_AGGR2_VCLK_CLK", "Input clock"}, {69, 0, "DEV_CPT2_AGGR3_VCLK_CLK", "Input clock"}, {68, 0, "DEV_CPT2_AGGR4_VCLK_CLK", "Input clock"}, {66, 0, "DEV_CPT2_AGGR5_VCLK_CLK", "Input clock"}, {189, 0, "DEV_CSI_PSILSS0_MAIN_CLK", "Input clock"}, {72, 0, "DEV_CSI_RX_IF0_MAIN_CLK_CLK", "Input clock"}, {72, 1, "DEV_CSI_RX_IF0_PPI_D_RX_ULPS_ESC", "Input clock"}, {72, 2, "DEV_CSI_RX_IF0_PPI_RX_BYTE_CLK", "Input clock"}, {72, 3, "DEV_CSI_RX_IF0_VBUS_CLK_CLK", "Input clock"}, {72, 4, "DEV_CSI_RX_IF0_VP_CLK_CLK", "Input clock"}, {73, 0, "DEV_CSI_RX_IF1_MAIN_CLK_CLK", "Input clock"}, {73, 1, "DEV_CSI_RX_IF1_PPI_D_RX_ULPS_ESC", "Input clock"}, {73, 2, "DEV_CSI_RX_IF1_PPI_RX_BYTE_CLK", "Input clock"}, {73, 3, "DEV_CSI_RX_IF1_VBUS_CLK_CLK", "Input clock"}, {73, 4, "DEV_CSI_RX_IF1_VP_CLK_CLK", "Input clock"}, {74, 0, "DEV_CSI_RX_IF2_MAIN_CLK_CLK", "Input clock"}, {74, 1, "DEV_CSI_RX_IF2_PPI_D_RX_ULPS_ESC", "Input clock"}, {74, 2, "DEV_CSI_RX_IF2_PPI_RX_BYTE_CLK", "Input clock"}, {74, 3, "DEV_CSI_RX_IF2_VBUS_CLK_CLK", "Input clock"}, {74, 4, "DEV_CSI_RX_IF2_VP_CLK_CLK", "Input clock"}, {75, 2, "DEV_CSI_TX_IF_V2_0_DPHY_TXBYTECLKHS_CL_CLK", "Input clock"}, {75, 3, "DEV_CSI_TX_IF_V2_0_ESC_CLK_CLK", "Input clock"}, {75, 4, "DEV_CSI_TX_IF_V2_0_MAIN_CLK_CLK", "Input clock"}, {75, 5, "DEV_CSI_TX_IF_V2_0_VBUS_CLK_CLK", "Input clock"}, {76, 2, "DEV_CSI_TX_IF_V2_1_DPHY_TXBYTECLKHS_CL_CLK", "Input clock"}, {76, 3, "DEV_CSI_TX_IF_V2_1_ESC_CLK_CLK", "Input clock"}, {76, 4, "DEV_CSI_TX_IF_V2_1_MAIN_CLK_CLK", "Input clock"}, {76, 5, "DEV_CSI_TX_IF_V2_1_VBUS_CLK_CLK", "Input clock"}, {78, 0, "DEV_DCC0_DCC_CLKSRC0_CLK", "Input clock"}, {78, 1, "DEV_DCC0_DCC_CLKSRC1_CLK", "Input clock"}, {78, 2, "DEV_DCC0_DCC_CLKSRC2_CLK", "Input clock"}, {78, 3, "DEV_DCC0_DCC_CLKSRC3_CLK", "Input clock"}, {78, 4, "DEV_DCC0_DCC_CLKSRC4_CLK", "Input clock"}, {78, 5, "DEV_DCC0_DCC_CLKSRC5_CLK", "Input clock"}, {78, 6, "DEV_DCC0_DCC_CLKSRC6_CLK", "Input clock"}, {78, 7, "DEV_DCC0_DCC_CLKSRC7_CLK", "Input clock"}, {78, 8, "DEV_DCC0_DCC_INPUT00_CLK", "Input clock"}, {78, 9, "DEV_DCC0_DCC_INPUT01_CLK", "Input clock"}, {78, 10, "DEV_DCC0_DCC_INPUT02_CLK", "Input clock"}, {78, 11, "DEV_DCC0_DCC_INPUT10_CLK", "Input clock"}, {78, 12, "DEV_DCC0_VBUS_CLK", "Input clock"}, {79, 0, "DEV_DCC1_DCC_CLKSRC0_CLK", "Input clock"}, {79, 1, "DEV_DCC1_DCC_CLKSRC1_CLK", "Input clock"}, {79, 2, "DEV_DCC1_DCC_CLKSRC2_CLK", "Input clock"}, {79, 3, "DEV_DCC1_DCC_CLKSRC3_CLK", "Input clock"}, {79, 4, "DEV_DCC1_DCC_CLKSRC4_CLK", "Input clock"}, {79, 5, "DEV_DCC1_DCC_CLKSRC5_CLK", "Input clock"}, {79, 6, "DEV_DCC1_DCC_CLKSRC6_CLK", "Input clock"}, {79, 7, "DEV_DCC1_DCC_CLKSRC7_CLK", "Input clock"}, {79, 8, "DEV_DCC1_DCC_INPUT00_CLK", "Input clock"}, {79, 9, "DEV_DCC1_DCC_INPUT01_CLK", "Input clock"}, {79, 10, "DEV_DCC1_DCC_INPUT02_CLK", "Input clock"}, {79, 11, "DEV_DCC1_DCC_INPUT10_CLK", "Input clock"}, {79, 12, "DEV_DCC1_VBUS_CLK", "Input clock"}, {80, 0, "DEV_DCC2_DCC_CLKSRC0_CLK", "Input clock"}, {80, 1, "DEV_DCC2_DCC_CLKSRC1_CLK", "Input clock"}, {80, 3, "DEV_DCC2_DCC_CLKSRC3_CLK", "Input clock"}, {80, 4, "DEV_DCC2_DCC_CLKSRC4_CLK", "Input clock"}, {80, 5, "DEV_DCC2_DCC_CLKSRC5_CLK", "Input clock"}, {80, 6, "DEV_DCC2_DCC_CLKSRC6_CLK", "Input clock"}, {80, 7, "DEV_DCC2_DCC_CLKSRC7_CLK", "Input clock"}, {80, 8, "DEV_DCC2_DCC_INPUT00_CLK", "Input clock"}, {80, 9, "DEV_DCC2_DCC_INPUT01_CLK", "Input clock"}, {80, 10, "DEV_DCC2_DCC_INPUT02_CLK", "Input clock"}, {80, 11, "DEV_DCC2_DCC_INPUT10_CLK", "Input clock"}, {80, 12, "DEV_DCC2_VBUS_CLK", "Input clock"}, {81, 0, "DEV_DCC3_DCC_CLKSRC0_CLK", "Input clock"}, {81, 1, "DEV_DCC3_DCC_CLKSRC1_CLK", "Input clock"}, {81, 2, "DEV_DCC3_DCC_CLKSRC2_CLK", "Input clock"}, {81, 3, "DEV_DCC3_DCC_CLKSRC3_CLK", "Input clock"}, {81, 5, "DEV_DCC3_DCC_CLKSRC5_CLK", "Input clock"}, {81, 6, "DEV_DCC3_DCC_CLKSRC6_CLK", "Input clock"}, {81, 7, "DEV_DCC3_DCC_CLKSRC7_CLK", "Input clock"}, {81, 8, "DEV_DCC3_DCC_INPUT00_CLK", "Input clock"}, {81, 9, "DEV_DCC3_DCC_INPUT01_CLK", "Input clock"}, {81, 10, "DEV_DCC3_DCC_INPUT02_CLK", "Input clock"}, {81, 11, "DEV_DCC3_DCC_INPUT10_CLK", "Input clock"}, {81, 12, "DEV_DCC3_VBUS_CLK", "Input clock"}, {82, 0, "DEV_DCC4_DCC_CLKSRC0_CLK", "Input clock"}, {82, 1, "DEV_DCC4_DCC_CLKSRC1_CLK", "Input clock"}, {82, 2, "DEV_DCC4_DCC_CLKSRC2_CLK", "Input clock"}, {82, 3, "DEV_DCC4_DCC_CLKSRC3_CLK", "Input clock"}, {82, 4, "DEV_DCC4_DCC_CLKSRC4_CLK", "Input clock"}, {82, 5, "DEV_DCC4_DCC_CLKSRC5_CLK", "Input clock"}, {82, 6, "DEV_DCC4_DCC_CLKSRC6_CLK", "Input clock"}, {82, 7, "DEV_DCC4_DCC_CLKSRC7_CLK", "Input clock"}, {82, 8, "DEV_DCC4_DCC_INPUT00_CLK", "Input clock"}, {82, 9, "DEV_DCC4_DCC_INPUT01_CLK", "Input clock"}, {82, 10, "DEV_DCC4_DCC_INPUT02_CLK", "Input clock"}, {82, 11, "DEV_DCC4_DCC_INPUT10_CLK", "Input clock"}, {82, 12, "DEV_DCC4_VBUS_CLK", "Input clock"}, {83, 1, "DEV_DCC5_DCC_CLKSRC1_CLK", "Input clock"}, {83, 2, "DEV_DCC5_DCC_CLKSRC2_CLK", "Input clock"}, {83, 3, "DEV_DCC5_DCC_CLKSRC3_CLK", "Input clock"}, {83, 4, "DEV_DCC5_DCC_CLKSRC4_CLK", "Input clock"}, {83, 6, "DEV_DCC5_DCC_CLKSRC6_CLK", "Input clock"}, {83, 7, "DEV_DCC5_DCC_CLKSRC7_CLK", "Input clock"}, {83, 8, "DEV_DCC5_DCC_INPUT00_CLK", "Input clock"}, {83, 9, "DEV_DCC5_DCC_INPUT01_CLK", "Input clock"}, {83, 10, "DEV_DCC5_DCC_INPUT02_CLK", "Input clock"}, {83, 11, "DEV_DCC5_DCC_INPUT10_CLK", "Input clock"}, {83, 12, "DEV_DCC5_VBUS_CLK", "Input clock"}, {84, 0, "DEV_DCC6_DCC_CLKSRC0_CLK", "Input clock"}, {84, 1, "DEV_DCC6_DCC_CLKSRC1_CLK", "Input clock"}, {84, 2, "DEV_DCC6_DCC_CLKSRC2_CLK", "Input clock"}, {84, 3, "DEV_DCC6_DCC_CLKSRC3_CLK", "Input clock"}, {84, 4, "DEV_DCC6_DCC_CLKSRC4_CLK", "Input clock"}, {84, 5, "DEV_DCC6_DCC_CLKSRC5_CLK", "Input clock"}, {84, 6, "DEV_DCC6_DCC_CLKSRC6_CLK", "Input clock"}, {84, 7, "DEV_DCC6_DCC_CLKSRC7_CLK", "Input clock"}, {84, 8, "DEV_DCC6_DCC_INPUT00_CLK", "Input clock"}, {84, 9, "DEV_DCC6_DCC_INPUT01_CLK", "Input clock"}, {84, 10, "DEV_DCC6_DCC_INPUT02_CLK", "Input clock"}, {84, 11, "DEV_DCC6_DCC_INPUT10_CLK", "Input clock"}, {84, 12, "DEV_DCC6_VBUS_CLK", "Input clock"}, {85, 0, "DEV_DCC7_DCC_CLKSRC0_CLK", "Input clock"}, {85, 1, "DEV_DCC7_DCC_CLKSRC1_CLK", "Input clock"}, {85, 2, "DEV_DCC7_DCC_CLKSRC2_CLK", "Input clock"}, {85, 5, "DEV_DCC7_DCC_CLKSRC5_CLK", "Input clock"}, {85, 6, "DEV_DCC7_DCC_CLKSRC6_CLK", "Input clock"}, {85, 7, "DEV_DCC7_DCC_CLKSRC7_CLK", "Input clock"}, {85, 8, "DEV_DCC7_DCC_INPUT00_CLK", "Input clock"}, {85, 9, "DEV_DCC7_DCC_INPUT01_CLK", "Input clock"}, {85, 10, "DEV_DCC7_DCC_INPUT02_CLK", "Input clock"}, {85, 11, "DEV_DCC7_DCC_INPUT10_CLK", "Input clock"}, {85, 12, "DEV_DCC7_VBUS_CLK", "Input clock"}, {86, 0, "DEV_DCC8_DCC_CLKSRC0_CLK", "Input clock"}, {86, 1, "DEV_DCC8_DCC_CLKSRC1_CLK", "Input clock"}, {86, 2, "DEV_DCC8_DCC_CLKSRC2_CLK", "Input clock"}, {86, 3, "DEV_DCC8_DCC_CLKSRC3_CLK", "Input clock"}, {86, 4, "DEV_DCC8_DCC_CLKSRC4_CLK", "Input clock"}, {86, 5, "DEV_DCC8_DCC_CLKSRC5_CLK", "Input clock"}, {86, 6, "DEV_DCC8_DCC_CLKSRC6_CLK", "Input clock"}, {86, 7, "DEV_DCC8_DCC_CLKSRC7_CLK", "Input clock"}, {86, 8, "DEV_DCC8_DCC_INPUT00_CLK", "Input clock"}, {86, 9, "DEV_DCC8_DCC_INPUT01_CLK", "Input clock"}, {86, 10, "DEV_DCC8_DCC_INPUT02_CLK", "Input clock"}, {86, 11, "DEV_DCC8_DCC_INPUT10_CLK", "Input clock"}, {86, 12, "DEV_DCC8_VBUS_CLK", "Input clock"}, {87, 0, "DEV_DCC9_DCC_CLKSRC0_CLK", "Input clock"}, {87, 1, "DEV_DCC9_DCC_CLKSRC1_CLK", "Input clock"}, {87, 2, "DEV_DCC9_DCC_CLKSRC2_CLK", "Input clock"}, {87, 3, "DEV_DCC9_DCC_CLKSRC3_CLK", "Input clock"}, {87, 4, "DEV_DCC9_DCC_CLKSRC4_CLK", "Input clock"}, {87, 5, "DEV_DCC9_DCC_CLKSRC5_CLK", "Input clock"}, {87, 6, "DEV_DCC9_DCC_CLKSRC6_CLK", "Input clock"}, {87, 8, "DEV_DCC9_DCC_INPUT00_CLK", "Input clock"}, {87, 9, "DEV_DCC9_DCC_INPUT01_CLK", "Input clock"}, {87, 10, "DEV_DCC9_DCC_INPUT02_CLK", "Input clock"}, {87, 11, "DEV_DCC9_DCC_INPUT10_CLK", "Input clock"}, {87, 12, "DEV_DCC9_VBUS_CLK", "Input clock"}, {191, 0, "DEV_DDR0_DDRSS_CFG_CLK", "Input clock"}, {191, 1, "DEV_DDR0_DDRSS_DDR_PLL_CLK", "Input clock"}, {191, 4, "DEV_DDR0_DDRSS_VBUS_CLK", "Input clock"}, {191, 5, "DEV_DDR0_PLL_CTRL_CLK", "Input clock"}, {192, 0, "DEV_DDR1_DDRSS_CFG_CLK", "Input clock"}, {192, 1, "DEV_DDR1_DDRSS_DDR_PLL_CLK", "Input clock"}, {192, 4, "DEV_DDR1_DDRSS_VBUS_CLK", "Input clock"}, {192, 5, "DEV_DDR1_PLL_CTRL_CLK", "Input clock"}, {193, 0, "DEV_DDR2_DDRSS_CFG_CLK", "Input clock"}, {193, 1, "DEV_DDR2_DDRSS_DDR_PLL_CLK", "Input clock"}, {193, 4, "DEV_DDR2_DDRSS_VBUS_CLK", "Input clock"}, {193, 5, "DEV_DDR2_PLL_CTRL_CLK", "Input clock"}, {194, 0, "DEV_DDR3_DDRSS_CFG_CLK", "Input clock"}, {194, 1, "DEV_DDR3_DDRSS_DDR_PLL_CLK", "Input clock"}, {194, 4, "DEV_DDR3_DDRSS_VBUS_CLK", "Input clock"}, {194, 5, "DEV_DDR3_PLL_CTRL_CLK", "Input clock"}, {91, 0, "DEV_DEBUGSS_WRAP0_ATB_CLK", "Input clock"}, {91, 1, "DEV_DEBUGSS_WRAP0_CORE_CLK", "Input clock"}, {91, 2, "DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK", "Output clock"}, {91, 20, "DEV_DEBUGSS_WRAP0_JTAG_TCK", "Input clock"}, {91, 22, "DEV_DEBUGSS_WRAP0_TREXPT_CLK", "Input clock"}, {190, 0, "DEV_DEBUGSUSPENDRTR0_INTR_CLK", "Input clock"}, {92, 0, "DEV_DMPAC0_CLK", "Input clock"}, {96, 0, "DEV_DMPAC0_SDE_0_CLK", "Input clock"}, {95, 0, "DEV_DMPAC0_UTC_0_PSIL_LEAF_CLK", "Input clock"}, {195, 0, "DEV_DMPAC_VPAC_PSILSS0_MAIN_CLK", "Input clock"}, {212, 2, "DEV_DPHY_RX0_IO_RX_CL_L_M", "Input clock"}, {212, 3, "DEV_DPHY_RX0_IO_RX_CL_L_P", "Input clock"}, {212, 4, "DEV_DPHY_RX0_JTAG_TCK", "Input clock"}, {212, 5, "DEV_DPHY_RX0_MAIN_CLK_CLK", "Input clock"}, {212, 6, "DEV_DPHY_RX0_PPI_D_RX_ULPS_ESC", "Output clock"}, {212, 7, "DEV_DPHY_RX0_PPI_RX_BYTE_CLK", "Output clock"}, {213, 2, "DEV_DPHY_RX1_IO_RX_CL_L_M", "Input clock"}, {213, 3, "DEV_DPHY_RX1_IO_RX_CL_L_P", "Input clock"}, {213, 4, "DEV_DPHY_RX1_JTAG_TCK", "Input clock"}, {213, 5, "DEV_DPHY_RX1_MAIN_CLK_CLK", "Input clock"}, {213, 6, "DEV_DPHY_RX1_PPI_D_RX_ULPS_ESC", "Output clock"}, {213, 7, "DEV_DPHY_RX1_PPI_RX_BYTE_CLK", "Output clock"}, {214, 2, "DEV_DPHY_RX2_IO_RX_CL_L_M", "Input clock"}, {214, 3, "DEV_DPHY_RX2_IO_RX_CL_L_P", "Input clock"}, {214, 4, "DEV_DPHY_RX2_JTAG_TCK", "Input clock"}, {214, 5, "DEV_DPHY_RX2_MAIN_CLK_CLK", "Input clock"}, {214, 6, "DEV_DPHY_RX2_PPI_D_RX_ULPS_ESC", "Output clock"}, {214, 7, "DEV_DPHY_RX2_PPI_RX_BYTE_CLK", "Output clock"}, {402, 0, "DEV_DPHY_TX0_CK_M", "Output clock"}, {402, 1, "DEV_DPHY_TX0_CK_P", "Output clock"}, {402, 2, "DEV_DPHY_TX0_CLK", "Input clock"}, {402, 3, "DEV_DPHY_TX0_DPHY_REF_CLK", "Input muxed clock"}, {402, 4, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"}, {402, 5, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"}, {402, 6, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"}, {402, 7, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"}, {402, 8, "DEV_DPHY_TX0_IP1_PPI_M_RXCLKESC_CLK", "Output clock"}, {402, 9, "DEV_DPHY_TX0_IP1_PPI_M_TXCLKESC_CLK", "Input clock"}, {402, 10, "DEV_DPHY_TX0_IP1_PPI_TXBYTECLKHS_CL_CLK", "Output clock"}, {402, 12, "DEV_DPHY_TX0_IP2_PPI_M_TXCLKESC_CLK", "Input clock"}, {402, 13, "DEV_DPHY_TX0_IP2_PPI_TXBYTECLKHS_CL_CLK", "Output clock"}, {402, 20, "DEV_DPHY_TX0_PSM_CLK", "Input clock"}, {402, 24, "DEV_DPHY_TX0_TAP_TCK", "Input clock"}, {403, 0, "DEV_DPHY_TX1_CK_M", "Output clock"}, {403, 1, "DEV_DPHY_TX1_CK_P", "Output clock"}, {403, 2, "DEV_DPHY_TX1_CLK", "Input clock"}, {403, 3, "DEV_DPHY_TX1_DPHY_REF_CLK", "Input muxed clock"}, {403, 4, "DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_DPHY_TX1_DPHY_REF_CLK"}, {403, 5, "DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_DPHY_TX1_DPHY_REF_CLK"}, {403, 6, "DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_DPHY_TX1_DPHY_REF_CLK"}, {403, 7, "DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_DPHY_TX1_DPHY_REF_CLK"}, {403, 8, "DEV_DPHY_TX1_IP1_PPI_M_RXCLKESC_CLK", "Output clock"}, {403, 9, "DEV_DPHY_TX1_IP1_PPI_M_TXCLKESC_CLK", "Input clock"}, {403, 10, "DEV_DPHY_TX1_IP1_PPI_TXBYTECLKHS_CL_CLK", "Output clock"}, {403, 13, "DEV_DPHY_TX1_IP2_PPI_TXBYTECLKHS_CL_CLK", "Output clock"}, {403, 20, "DEV_DPHY_TX1_PSM_CLK", "Input clock"}, {403, 24, "DEV_DPHY_TX1_TAP_TCK", "Input clock"}, {218, 0, "DEV_DSS0_DSS_FUNC_CLK", "Input clock"}, {218, 1, "DEV_DSS0_DSS_INST0_DPI_0_IN_CLK", "Input clock"}, {218, 2, "DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK", "Input muxed clock"}, {218, 3, "DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK"}, {218, 4, "DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_DPI_1_PCLK_SEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK"}, {218, 5, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK", "Input muxed clock"}, {218, 6, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"}, {218, 7, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"}, {218, 8, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0_DUP0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"}, {218, 9, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"}, {218, 10, "DEV_DSS0_DSS_INST0_DPI_2_IN_CLK", "Input muxed clock"}, {218, 11, "DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_CLK"}, {218, 12, "DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_CLK"}, {218, 13, "DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_CLK"}, {218, 14, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK", "Input muxed clock"}, {218, 15, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK"}, {218, 16, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK"}, {218, 17, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK"}, {218, 18, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK", "Input muxed clock"}, {218, 19, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT1_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"}, {218, 20, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"}, {218, 21, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK_DUP0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"}, {218, 22, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"}, {218, 23, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0_DUP0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"}, {218, 24, "DEV_DSS0_DSS_INST0_PARA_1_OUT_CLK", "Output clock"}, {218, 25, "DEV_DSS0_DSS_INST0_PARA_3_OUT_CLK", "Output clock"}, {218, 26, "DEV_DSS0_DSS_INST0_DPI_0_OUT_CLK", "Output clock"}, {218, 27, "DEV_DSS0_DSS_INST0_DPI_1_OUT_CLK", "Output clock"}, {218, 28, "DEV_DSS0_DSS_INST0_DPI_2_OUT_CLK", "Output clock"}, {218, 29, "DEV_DSS0_DSS_INST0_DPI_3_OUT_CLK", "Output clock"}, {218, 30, "DEV_DSS0_DSS_INST0_DPI_0_OUT_2X_CLK", "Output clock"}, {215, 0, "DEV_DSS_DSI0_DPHY_0_RX_ESC_CLK", "Input clock"}, {215, 1, "DEV_DSS_DSI0_DPHY_0_TX_ESC_CLK", "Input clock"}, {215, 2, "DEV_DSS_DSI0_DPI_0_CLK", "Input clock"}, {215, 3, "DEV_DSS_DSI0_PLL_CTRL_CLK", "Input clock"}, {215, 4, "DEV_DSS_DSI0_PPI_0_TXBYTECLKHS_CL_CLK", "Input clock"}, {215, 5, "DEV_DSS_DSI0_SYS_CLK", "Input clock"}, {216, 0, "DEV_DSS_DSI1_DPHY_0_RX_ESC_CLK", "Input clock"}, {216, 1, "DEV_DSS_DSI1_DPHY_0_TX_ESC_CLK", "Input clock"}, {216, 2, "DEV_DSS_DSI1_DPI_0_CLK", "Input clock"}, {216, 3, "DEV_DSS_DSI1_PLL_CTRL_CLK", "Input clock"}, {216, 4, "DEV_DSS_DSI1_PPI_0_TXBYTECLKHS_CL_CLK", "Input clock"}, {216, 5, "DEV_DSS_DSI1_SYS_CLK", "Input clock"}, {217, 0, "DEV_DSS_EDP0_AIF_I2S_CLK", "Input clock"}, {217, 6, "DEV_DSS_EDP0_DPI_2_2X_CLK", "Input clock"}, {217, 7, "DEV_DSS_EDP0_DPI_2_CLK", "Input clock"}, {217, 8, "DEV_DSS_EDP0_DPI_3_CLK", "Input clock"}, {217, 9, "DEV_DSS_EDP0_DPI_4_CLK", "Input clock"}, {217, 10, "DEV_DSS_EDP0_DPI_5_CLK", "Input clock"}, {217, 11, "DEV_DSS_EDP0_DPTX_MOD_CLK", "Input clock"}, {217, 12, "DEV_DSS_EDP0_PHY_LN0_REFCLK", "Input clock"}, {217, 13, "DEV_DSS_EDP0_PHY_LN0_RXCLK", "Input clock"}, {217, 14, "DEV_DSS_EDP0_PHY_LN0_RXFCLK", "Input clock"}, {217, 15, "DEV_DSS_EDP0_PHY_LN0_TXCLK", "Output clock"}, {217, 16, "DEV_DSS_EDP0_PHY_LN0_TXFCLK", "Input clock"}, {217, 17, "DEV_DSS_EDP0_PHY_LN0_TXMCLK", "Input clock"}, {217, 18, "DEV_DSS_EDP0_PHY_LN1_REFCLK", "Input clock"}, {217, 19, "DEV_DSS_EDP0_PHY_LN1_RXCLK", "Input clock"}, {217, 20, "DEV_DSS_EDP0_PHY_LN1_RXFCLK", "Input clock"}, {217, 21, "DEV_DSS_EDP0_PHY_LN1_TXCLK", "Output clock"}, {217, 22, "DEV_DSS_EDP0_PHY_LN1_TXFCLK", "Input clock"}, {217, 23, "DEV_DSS_EDP0_PHY_LN1_TXMCLK", "Input clock"}, {217, 24, "DEV_DSS_EDP0_PHY_LN2_REFCLK", "Input clock"}, {217, 25, "DEV_DSS_EDP0_PHY_LN2_RXCLK", "Input clock"}, {217, 26, "DEV_DSS_EDP0_PHY_LN2_RXFCLK", "Input clock"}, {217, 27, "DEV_DSS_EDP0_PHY_LN2_TXCLK", "Output clock"}, {217, 28, "DEV_DSS_EDP0_PHY_LN2_TXFCLK", "Input clock"}, {217, 29, "DEV_DSS_EDP0_PHY_LN2_TXMCLK", "Input clock"}, {217, 30, "DEV_DSS_EDP0_PHY_LN3_REFCLK", "Input clock"}, {217, 31, "DEV_DSS_EDP0_PHY_LN3_RXCLK", "Input clock"}, {217, 32, "DEV_DSS_EDP0_PHY_LN3_RXFCLK", "Input clock"}, {217, 33, "DEV_DSS_EDP0_PHY_LN3_TXCLK", "Output clock"}, {217, 34, "DEV_DSS_EDP0_PHY_LN3_TXFCLK", "Input clock"}, {217, 35, "DEV_DSS_EDP0_PHY_LN3_TXMCLK", "Input clock"}, {217, 36, "DEV_DSS_EDP0_PLL_CTRL_CLK", "Input clock"}, {126, 0, "DEV_ECAP0_VBUS_CLK", "Input clock"}, {127, 0, "DEV_ECAP1_VBUS_CLK", "Input clock"}, {128, 0, "DEV_ECAP2_VBUS_CLK", "Input clock"}, {130, 0, "DEV_ELM0_VBUSP_CLK", "Input clock"}, {219, 0, "DEV_EPWM0_VBUSP_CLK", "Input clock"}, {220, 0, "DEV_EPWM1_VBUSP_CLK", "Input clock"}, {221, 0, "DEV_EPWM2_VBUSP_CLK", "Input clock"}, {222, 0, "DEV_EPWM3_VBUSP_CLK", "Input clock"}, {223, 0, "DEV_EPWM4_VBUSP_CLK", "Input clock"}, {224, 0, "DEV_EPWM5_VBUSP_CLK", "Input clock"}, {142, 0, "DEV_EQEP0_VBUS_CLK", "Input clock"}, {143, 0, "DEV_EQEP1_VBUS_CLK", "Input clock"}, {144, 0, "DEV_EQEP2_VBUS_CLK", "Input clock"}, {145, 0, "DEV_ESM0_CLK", "Input clock"}, {417, 0, "DEV_GLUELOGIC_ACSPCIE0_BUFFER_CLKIN0", "Input clock"}, {417, 1, "DEV_GLUELOGIC_ACSPCIE0_BUFFER_CLKIN1", "Input clock"}, {417, 2, "DEV_GLUELOGIC_ACSPCIE0_BUFFER_PAD0_M", "Output clock"}, {417, 3, "DEV_GLUELOGIC_ACSPCIE0_BUFFER_PAD0_P", "Output clock"}, {417, 4, "DEV_GLUELOGIC_ACSPCIE0_BUFFER_PAD1_M", "Output clock"}, {417, 5, "DEV_GLUELOGIC_ACSPCIE0_BUFFER_PAD1_P", "Output clock"}, {418, 0, "DEV_GLUELOGIC_ACSPCIE1_BUFFER_CLKIN0", "Input clock"}, {418, 1, "DEV_GLUELOGIC_ACSPCIE1_BUFFER_CLKIN1", "Input clock"}, {418, 2, "DEV_GLUELOGIC_ACSPCIE1_BUFFER_PAD0_M", "Output clock"}, {418, 3, "DEV_GLUELOGIC_ACSPCIE1_BUFFER_PAD0_P", "Output clock"}, {418, 4, "DEV_GLUELOGIC_ACSPCIE1_BUFFER_PAD1_M", "Output clock"}, {418, 5, "DEV_GLUELOGIC_ACSPCIE1_BUFFER_PAD1_P", "Output clock"}, {163, 0, "DEV_GPIO0_MMR_CLK", "Input clock"}, {164, 0, "DEV_GPIO2_MMR_CLK", "Input clock"}, {165, 0, "DEV_GPIO4_MMR_CLK", "Input clock"}, {166, 0, "DEV_GPIO6_MMR_CLK", "Input clock"}, {10, 0, "DEV_GPIOMUX_INTRTR0_INTR_CLK", "Input clock"}, {169, 0, "DEV_GPMC0_FUNC_CLK", "Input muxed clock"}, {169, 1, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_GPMC0_FUNC_CLK"}, {169, 2, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK6", "Parent input clock option to DEV_GPMC0_FUNC_CLK"}, {169, 3, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK4", "Parent input clock option to DEV_GPMC0_FUNC_CLK"}, {169, 4, "DEV_GPMC0_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_GPMC0_FUNC_CLK"}, {169, 5, "DEV_GPMC0_PI_GPMC_RET_CLK", "Input clock"}, {169, 6, "DEV_GPMC0_PO_GPMC_DEV_CLK", "Output clock"}, {169, 7, "DEV_GPMC0_VBUSM_CLK", "Input clock"}, {61, 0, "DEV_GTC0_GTC_CLK", "Input muxed clock"}, {61, 1, "DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 2, "DEV_GTC0_GTC_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 3, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 4, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 5, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 6, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 7, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 8, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 9, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 10, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 11, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 12, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 13, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 14, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 15, "DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 16, "DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"}, {61, 17, "DEV_GTC0_VBUSP_CLK", "Input clock"}, {270, 0, "DEV_I2C0_CLK", "Input clock"}, {270, 1, "DEV_I2C0_PISCL", "Input clock"}, {270, 2, "DEV_I2C0_PISYS_CLK", "Input clock"}, {270, 3, "DEV_I2C0_PORSCL", "Output clock"}, {271, 0, "DEV_I2C1_CLK", "Input clock"}, {271, 1, "DEV_I2C1_PISCL", "Input clock"}, {271, 2, "DEV_I2C1_PISYS_CLK", "Input clock"}, {271, 3, "DEV_I2C1_PORSCL", "Output clock"}, {272, 0, "DEV_I2C2_CLK", "Input clock"}, {272, 1, "DEV_I2C2_PISCL", "Input clock"}, {272, 2, "DEV_I2C2_PISYS_CLK", "Input clock"}, {272, 3, "DEV_I2C2_PORSCL", "Output clock"}, {273, 0, "DEV_I2C3_CLK", "Input clock"}, {273, 1, "DEV_I2C3_PISCL", "Input clock"}, {273, 2, "DEV_I2C3_PISYS_CLK", "Input clock"}, {273, 3, "DEV_I2C3_PORSCL", "Output clock"}, {274, 0, "DEV_I2C4_CLK", "Input clock"}, {274, 1, "DEV_I2C4_PISCL", "Input clock"}, {274, 2, "DEV_I2C4_PISYS_CLK", "Input clock"}, {274, 3, "DEV_I2C4_PORSCL", "Output clock"}, {275, 0, "DEV_I2C5_CLK", "Input clock"}, {275, 1, "DEV_I2C5_PISCL", "Input clock"}, {275, 2, "DEV_I2C5_PISYS_CLK", "Input clock"}, {275, 3, "DEV_I2C5_PORSCL", "Output clock"}, {276, 0, "DEV_I2C6_CLK", "Input clock"}, {276, 1, "DEV_I2C6_PISCL", "Input clock"}, {276, 2, "DEV_I2C6_PISYS_CLK", "Input clock"}, {276, 3, "DEV_I2C6_PORSCL", "Output clock"}, {181, 1, "DEV_J7AEP_GPU_BXS464_WRAP0_GPU_SS_0_GPU_PLL_CLK", "Input clock"}, {181, 4, "DEV_J7AEP_GPU_BXS464_WRAP0_GPU_SS_0_PLL_CTRL_CLK", "Input clock"}, {183, 0, "DEV_J7AM_32_64_ATB_FUNNEL0_DBG_CLK", "Input clock"}, {184, 0, "DEV_J7AM_32_64_ATB_FUNNEL1_DBG_CLK", "Input clock"}, {185, 0, "DEV_J7AM_32_64_ATB_FUNNEL2_DBG_CLK", "Input clock"}, {187, 0, "DEV_J7AM_BOLT_PGD0_WKUP_OSC0_CLK", "Input clock"}, {188, 0, "DEV_J7AM_BOLT_PSC_WRAP0_CLK", "Input clock"}, {188, 1, "DEV_J7AM_BOLT_PSC_WRAP0_SLOW_CLK", "Input clock"}, {197, 0, "DEV_J7AM_HWA_ATB_FUNNEL0_DBG_CLK", "Input clock"}, {199, 0, "DEV_J7AM_MAIN_16FF0_WKUP_OSC0_CLK", "Input clock"}, {7, 0, "DEV_J7AM_PULSAR_ATB_FUNNEL0_DBG_CLK", "Input clock"}, {172, 0, "DEV_LED0_LED_CLK", "Input clock"}, {172, 1, "DEV_LED0_VBUS_CLK", "Input clock"}, {173, 0, "DEV_MAIN2MCU_LVL_INTRTR0_INTR_CLK", "Input clock"}, {174, 0, "DEV_MAIN2MCU_PLS_INTRTR0_INTR_CLK", "Input clock"}, {245, 0, "DEV_MCAN0_MCANSS_CAN_RXD", "Input clock"}, {245, 1, "DEV_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"}, {245, 2, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, {245, 3, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, {245, 4, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, {245, 5, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, {245, 6, "DEV_MCAN0_MCANSS_HCLK_CLK", "Input clock"}, {246, 0, "DEV_MCAN1_MCANSS_CAN_RXD", "Input clock"}, {246, 1, "DEV_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"}, {246, 2, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, {246, 3, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, {246, 4, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, {246, 5, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"}, {246, 6, "DEV_MCAN1_MCANSS_HCLK_CLK", "Input clock"}, {255, 0, "DEV_MCAN10_MCANSS_CAN_RXD", "Input clock"}, {255, 1, "DEV_MCAN10_MCANSS_CCLK_CLK", "Input muxed clock"}, {255, 2, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"}, {255, 3, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"}, {255, 4, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"}, {255, 5, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"}, {255, 6, "DEV_MCAN10_MCANSS_HCLK_CLK", "Input clock"}, {256, 0, "DEV_MCAN11_MCANSS_CAN_RXD", "Input clock"}, {256, 1, "DEV_MCAN11_MCANSS_CCLK_CLK", "Input muxed clock"}, {256, 2, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"}, {256, 3, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"}, {256, 4, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"}, {256, 5, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"}, {256, 6, "DEV_MCAN11_MCANSS_HCLK_CLK", "Input clock"}, {257, 0, "DEV_MCAN12_MCANSS_CAN_RXD", "Input clock"}, {257, 1, "DEV_MCAN12_MCANSS_CCLK_CLK", "Input muxed clock"}, {257, 2, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"}, {257, 3, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"}, {257, 4, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"}, {257, 5, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"}, {257, 6, "DEV_MCAN12_MCANSS_HCLK_CLK", "Input clock"}, {258, 0, "DEV_MCAN13_MCANSS_CAN_RXD", "Input clock"}, {258, 1, "DEV_MCAN13_MCANSS_CCLK_CLK", "Input muxed clock"}, {258, 2, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"}, {258, 3, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"}, {258, 4, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"}, {258, 5, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"}, {258, 6, "DEV_MCAN13_MCANSS_HCLK_CLK", "Input clock"}, {259, 0, "DEV_MCAN14_MCANSS_CAN_RXD", "Input clock"}, {259, 1, "DEV_MCAN14_MCANSS_CCLK_CLK", "Input muxed clock"}, {259, 2, "DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK"}, {259, 3, "DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK"}, {259, 4, "DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK"}, {259, 5, "DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK"}, {259, 6, "DEV_MCAN14_MCANSS_HCLK_CLK", "Input clock"}, {260, 0, "DEV_MCAN15_MCANSS_CAN_RXD", "Input clock"}, {260, 1, "DEV_MCAN15_MCANSS_CCLK_CLK", "Input muxed clock"}, {260, 2, "DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK"}, {260, 3, "DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK"}, {260, 4, "DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK"}, {260, 5, "DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK"}, {260, 6, "DEV_MCAN15_MCANSS_HCLK_CLK", "Input clock"}, {261, 0, "DEV_MCAN16_MCANSS_CAN_RXD", "Input clock"}, {261, 1, "DEV_MCAN16_MCANSS_CCLK_CLK", "Input muxed clock"}, {261, 2, "DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK"}, {261, 3, "DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK"}, {261, 4, "DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK"}, {261, 5, "DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK"}, {261, 6, "DEV_MCAN16_MCANSS_HCLK_CLK", "Input clock"}, {262, 0, "DEV_MCAN17_MCANSS_CAN_RXD", "Input clock"}, {262, 1, "DEV_MCAN17_MCANSS_CCLK_CLK", "Input muxed clock"}, {262, 2, "DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK"}, {262, 3, "DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK"}, {262, 4, "DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK"}, {262, 5, "DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK"}, {262, 6, "DEV_MCAN17_MCANSS_HCLK_CLK", "Input clock"}, {247, 0, "DEV_MCAN2_MCANSS_CAN_RXD", "Input clock"}, {247, 1, "DEV_MCAN2_MCANSS_CCLK_CLK", "Input muxed clock"}, {247, 2, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"}, {247, 3, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"}, {247, 4, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"}, {247, 5, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"}, {247, 6, "DEV_MCAN2_MCANSS_HCLK_CLK", "Input clock"}, {248, 0, "DEV_MCAN3_MCANSS_CAN_RXD", "Input clock"}, {248, 1, "DEV_MCAN3_MCANSS_CCLK_CLK", "Input muxed clock"}, {248, 2, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"}, {248, 3, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"}, {248, 4, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"}, {248, 5, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"}, {248, 6, "DEV_MCAN3_MCANSS_HCLK_CLK", "Input clock"}, {249, 0, "DEV_MCAN4_MCANSS_CAN_RXD", "Input clock"}, {249, 1, "DEV_MCAN4_MCANSS_CCLK_CLK", "Input muxed clock"}, {249, 2, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"}, {249, 3, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"}, {249, 4, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"}, {249, 5, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"}, {249, 6, "DEV_MCAN4_MCANSS_HCLK_CLK", "Input clock"}, {250, 0, "DEV_MCAN5_MCANSS_CAN_RXD", "Input clock"}, {250, 1, "DEV_MCAN5_MCANSS_CCLK_CLK", "Input muxed clock"}, {250, 2, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"}, {250, 3, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"}, {250, 4, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"}, {250, 5, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"}, {250, 6, "DEV_MCAN5_MCANSS_HCLK_CLK", "Input clock"}, {251, 0, "DEV_MCAN6_MCANSS_CAN_RXD", "Input clock"}, {251, 1, "DEV_MCAN6_MCANSS_CCLK_CLK", "Input muxed clock"}, {251, 2, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"}, {251, 3, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"}, {251, 4, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"}, {251, 5, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"}, {251, 6, "DEV_MCAN6_MCANSS_HCLK_CLK", "Input clock"}, {252, 0, "DEV_MCAN7_MCANSS_CAN_RXD", "Input clock"}, {252, 1, "DEV_MCAN7_MCANSS_CCLK_CLK", "Input muxed clock"}, {252, 2, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"}, {252, 3, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"}, {252, 4, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"}, {252, 5, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"}, {252, 6, "DEV_MCAN7_MCANSS_HCLK_CLK", "Input clock"}, {253, 0, "DEV_MCAN8_MCANSS_CAN_RXD", "Input clock"}, {253, 1, "DEV_MCAN8_MCANSS_CCLK_CLK", "Input muxed clock"}, {253, 2, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"}, {253, 3, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"}, {253, 4, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"}, {253, 5, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"}, {253, 6, "DEV_MCAN8_MCANSS_HCLK_CLK", "Input clock"}, {254, 0, "DEV_MCAN9_MCANSS_CAN_RXD", "Input clock"}, {254, 1, "DEV_MCAN9_MCANSS_CCLK_CLK", "Input muxed clock"}, {254, 2, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"}, {254, 3, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"}, {254, 4, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"}, {254, 5, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"}, {254, 6, "DEV_MCAN9_MCANSS_HCLK_CLK", "Input clock"}, {265, 0, "DEV_MCASP0_AUX_CLK", "Input muxed clock"}, {265, 1, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, {265, 2, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, {265, 5, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, {265, 6, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, {265, 7, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, {265, 8, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, {265, 9, "DEV_MCASP0_MCASP_ACLKR_PIN", "Input clock"}, {265, 10, "DEV_MCASP0_MCASP_ACLKR_POUT", "Output clock"}, {265, 11, "DEV_MCASP0_MCASP_ACLKX_PIN", "Input clock"}, {265, 12, "DEV_MCASP0_MCASP_ACLKX_POUT", "Output clock"}, {265, 13, "DEV_MCASP0_MCASP_AFSR_POUT", "Output clock"}, {265, 14, "DEV_MCASP0_MCASP_AFSX_POUT", "Output clock"}, {265, 15, "DEV_MCASP0_MCASP_AHCLKR_PIN", "Input muxed clock"}, {265, 16, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {265, 17, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {265, 18, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {265, 19, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {265, 24, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {265, 25, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {265, 26, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {265, 27, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {265, 32, "DEV_MCASP0_MCASP_AHCLKR_POUT", "Output clock"}, {265, 33, "DEV_MCASP0_MCASP_AHCLKX_PIN", "Input muxed clock"}, {265, 34, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {265, 35, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {265, 36, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {265, 37, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {265, 42, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {265, 43, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {265, 44, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {265, 45, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {265, 50, "DEV_MCASP0_MCASP_AHCLKX_POUT", "Output clock"}, {265, 51, "DEV_MCASP0_VBUSP_CLK", "Input clock"}, {266, 0, "DEV_MCASP1_AUX_CLK", "Input muxed clock"}, {266, 1, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, {266, 2, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, {266, 5, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, {266, 6, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, {266, 7, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, {266, 8, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, {266, 9, "DEV_MCASP1_MCASP_ACLKR_PIN", "Input clock"}, {266, 10, "DEV_MCASP1_MCASP_ACLKR_POUT", "Output clock"}, {266, 11, "DEV_MCASP1_MCASP_ACLKX_PIN", "Input clock"}, {266, 12, "DEV_MCASP1_MCASP_ACLKX_POUT", "Output clock"}, {266, 13, "DEV_MCASP1_MCASP_AFSR_POUT", "Output clock"}, {266, 14, "DEV_MCASP1_MCASP_AFSX_POUT", "Output clock"}, {266, 15, "DEV_MCASP1_MCASP_AHCLKR_PIN", "Input muxed clock"}, {266, 16, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {266, 17, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {266, 18, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {266, 19, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {266, 24, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {266, 25, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {266, 26, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {266, 27, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {266, 32, "DEV_MCASP1_MCASP_AHCLKR_POUT", "Output clock"}, {266, 33, "DEV_MCASP1_MCASP_AHCLKX_PIN", "Input muxed clock"}, {266, 34, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {266, 35, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {266, 36, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {266, 37, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {266, 42, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {266, 43, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {266, 44, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {266, 45, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {266, 50, "DEV_MCASP1_MCASP_AHCLKX_POUT", "Output clock"}, {266, 51, "DEV_MCASP1_VBUSP_CLK", "Input clock"}, {267, 0, "DEV_MCASP2_AUX_CLK", "Input muxed clock"}, {267, 1, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, {267, 2, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, {267, 5, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, {267, 6, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, {267, 7, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, {267, 8, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, {267, 9, "DEV_MCASP2_MCASP_ACLKR_PIN", "Input clock"}, {267, 10, "DEV_MCASP2_MCASP_ACLKR_POUT", "Output clock"}, {267, 11, "DEV_MCASP2_MCASP_ACLKX_PIN", "Input clock"}, {267, 12, "DEV_MCASP2_MCASP_ACLKX_POUT", "Output clock"}, {267, 13, "DEV_MCASP2_MCASP_AFSR_POUT", "Output clock"}, {267, 14, "DEV_MCASP2_MCASP_AFSX_POUT", "Output clock"}, {267, 15, "DEV_MCASP2_MCASP_AHCLKR_PIN", "Input muxed clock"}, {267, 16, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {267, 17, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {267, 18, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {267, 19, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {267, 24, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {267, 25, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {267, 26, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {267, 27, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {267, 32, "DEV_MCASP2_MCASP_AHCLKR_POUT", "Output clock"}, {267, 33, "DEV_MCASP2_MCASP_AHCLKX_PIN", "Input muxed clock"}, {267, 34, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {267, 35, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {267, 36, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {267, 37, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {267, 42, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {267, 43, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {267, 44, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {267, 45, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {267, 50, "DEV_MCASP2_MCASP_AHCLKX_POUT", "Output clock"}, {267, 51, "DEV_MCASP2_VBUSP_CLK", "Input clock"}, {268, 0, "DEV_MCASP3_AUX_CLK", "Input muxed clock"}, {268, 1, "DEV_MCASP3_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP3_AUX_CLK"}, {268, 2, "DEV_MCASP3_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP3_AUX_CLK"}, {268, 5, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP3_AUX_CLK"}, {268, 6, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP3_AUX_CLK"}, {268, 7, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP3_AUX_CLK"}, {268, 8, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP3_AUX_CLK"}, {268, 9, "DEV_MCASP3_MCASP_ACLKR_PIN", "Input clock"}, {268, 10, "DEV_MCASP3_MCASP_ACLKR_POUT", "Output clock"}, {268, 11, "DEV_MCASP3_MCASP_ACLKX_PIN", "Input clock"}, {268, 12, "DEV_MCASP3_MCASP_ACLKX_POUT", "Output clock"}, {268, 13, "DEV_MCASP3_MCASP_AFSR_POUT", "Output clock"}, {268, 14, "DEV_MCASP3_MCASP_AFSX_POUT", "Output clock"}, {268, 15, "DEV_MCASP3_MCASP_AHCLKR_PIN", "Input muxed clock"}, {268, 16, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, {268, 17, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, {268, 18, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, {268, 19, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, {268, 24, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, {268, 25, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, {268, 26, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, {268, 27, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"}, {268, 32, "DEV_MCASP3_MCASP_AHCLKR_POUT", "Output clock"}, {268, 33, "DEV_MCASP3_MCASP_AHCLKX_PIN", "Input muxed clock"}, {268, 34, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, {268, 35, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, {268, 36, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, {268, 37, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, {268, 42, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, {268, 43, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, {268, 44, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, {268, 45, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"}, {268, 50, "DEV_MCASP3_MCASP_AHCLKX_POUT", "Output clock"}, {268, 51, "DEV_MCASP3_VBUSP_CLK", "Input clock"}, {269, 0, "DEV_MCASP4_AUX_CLK", "Input muxed clock"}, {269, 1, "DEV_MCASP4_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP4_AUX_CLK"}, {269, 2, "DEV_MCASP4_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP4_AUX_CLK"}, {269, 5, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP4_AUX_CLK"}, {269, 6, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP4_AUX_CLK"}, {269, 7, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP4_AUX_CLK"}, {269, 8, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP4_AUX_CLK"}, {269, 9, "DEV_MCASP4_MCASP_ACLKR_PIN", "Input clock"}, {269, 10, "DEV_MCASP4_MCASP_ACLKR_POUT", "Output clock"}, {269, 11, "DEV_MCASP4_MCASP_ACLKX_PIN", "Input clock"}, {269, 12, "DEV_MCASP4_MCASP_ACLKX_POUT", "Output clock"}, {269, 13, "DEV_MCASP4_MCASP_AFSR_POUT", "Output clock"}, {269, 14, "DEV_MCASP4_MCASP_AFSX_POUT", "Output clock"}, {269, 15, "DEV_MCASP4_MCASP_AHCLKR_PIN", "Input muxed clock"}, {269, 16, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, {269, 17, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, {269, 18, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, {269, 19, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, {269, 24, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, {269, 25, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, {269, 26, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, {269, 27, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"}, {269, 32, "DEV_MCASP4_MCASP_AHCLKR_POUT", "Output clock"}, {269, 33, "DEV_MCASP4_MCASP_AHCLKX_PIN", "Input muxed clock"}, {269, 34, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, {269, 35, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, {269, 36, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, {269, 37, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, {269, 42, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, {269, 43, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, {269, 44, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, {269, 45, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"}, {269, 50, "DEV_MCASP4_MCASP_AHCLKX_POUT", "Output clock"}, {269, 51, "DEV_MCASP4_VBUSP_CLK", "Input clock"}, {376, 0, "DEV_MCSPI0_CLKSPIREF_CLK", "Input clock"}, {376, 1, "DEV_MCSPI0_IO_CLKSPII_CLK", "Input muxed clock"}, {376, 2, "DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI0_CLK_OUT", "Parent input clock option to DEV_MCSPI0_IO_CLKSPII_CLK"}, {376, 3, "DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MAIN_0_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI0_IO_CLKSPII_CLK"}, {376, 4, "DEV_MCSPI0_IO_CLKSPIO_CLK", "Output clock"}, {376, 5, "DEV_MCSPI0_VBUSP_CLK", "Input clock"}, {377, 0, "DEV_MCSPI1_CLKSPIREF_CLK", "Input clock"}, {377, 1, "DEV_MCSPI1_IO_CLKSPII_CLK", "Input muxed clock"}, {377, 2, "DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI1_CLK_OUT", "Parent input clock option to DEV_MCSPI1_IO_CLKSPII_CLK"}, {377, 3, "DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_1_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI1_IO_CLKSPII_CLK"}, {377, 4, "DEV_MCSPI1_IO_CLKSPIO_CLK", "Output clock"}, {377, 5, "DEV_MCSPI1_VBUSP_CLK", "Input clock"}, {378, 0, "DEV_MCSPI2_CLKSPIREF_CLK", "Input clock"}, {378, 1, "DEV_MCSPI2_IO_CLKSPII_CLK", "Input muxed clock"}, {378, 2, "DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI2_CLK_OUT", "Parent input clock option to DEV_MCSPI2_IO_CLKSPII_CLK"}, {378, 3, "DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_SPI_MAIN_2_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI2_IO_CLKSPII_CLK"}, {378, 4, "DEV_MCSPI2_IO_CLKSPIO_CLK", "Output clock"}, {378, 5, "DEV_MCSPI2_VBUSP_CLK", "Input clock"}, {379, 0, "DEV_MCSPI3_CLKSPIREF_CLK", "Input clock"}, {379, 1, "DEV_MCSPI3_IO_CLKSPII_CLK", "Input muxed clock"}, {379, 2, "DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI3_IO_CLKSPII_CLK"}, {379, 3, "DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI3_CLK_LPBK_MUX_OUT0", "Parent input clock option to DEV_MCSPI3_IO_CLKSPII_CLK"}, {379, 4, "DEV_MCSPI3_IO_CLKSPIO_CLK", "Output clock"}, {379, 5, "DEV_MCSPI3_VBUSP_CLK", "Input clock"}, {380, 0, "DEV_MCSPI4_CLKSPIREF_CLK", "Input clock"}, {380, 1, "DEV_MCSPI4_IO_CLKSPII_CLK", "Input clock"}, {380, 2, "DEV_MCSPI4_IO_CLKSPIO_CLK", "Output clock"}, {380, 3, "DEV_MCSPI4_VBUSP_CLK", "Input clock"}, {381, 0, "DEV_MCSPI5_CLKSPIREF_CLK", "Input clock"}, {381, 1, "DEV_MCSPI5_IO_CLKSPII_CLK", "Input muxed clock"}, {381, 2, "DEV_MCSPI5_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI5_CLK_OUT", "Parent input clock option to DEV_MCSPI5_IO_CLKSPII_CLK"}, {381, 3, "DEV_MCSPI5_IO_CLKSPII_CLK_PARENT_SPI_MAIN_5_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI5_IO_CLKSPII_CLK"}, {381, 4, "DEV_MCSPI5_IO_CLKSPIO_CLK", "Output clock"}, {381, 5, "DEV_MCSPI5_VBUSP_CLK", "Input clock"}, {382, 0, "DEV_MCSPI6_CLKSPIREF_CLK", "Input clock"}, {382, 1, "DEV_MCSPI6_IO_CLKSPII_CLK", "Input muxed clock"}, {382, 2, "DEV_MCSPI6_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI6_CLK_OUT", "Parent input clock option to DEV_MCSPI6_IO_CLKSPII_CLK"}, {382, 3, "DEV_MCSPI6_IO_CLKSPII_CLK_PARENT_SPI_MAIN_6_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI6_IO_CLKSPII_CLK"}, {382, 4, "DEV_MCSPI6_IO_CLKSPIO_CLK", "Output clock"}, {382, 5, "DEV_MCSPI6_VBUSP_CLK", "Input clock"}, {383, 0, "DEV_MCSPI7_CLKSPIREF_CLK", "Input clock"}, {383, 1, "DEV_MCSPI7_IO_CLKSPII_CLK", "Input muxed clock"}, {383, 2, "DEV_MCSPI7_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI7_CLK_OUT", "Parent input clock option to DEV_MCSPI7_IO_CLKSPII_CLK"}, {383, 3, "DEV_MCSPI7_IO_CLKSPII_CLK_PARENT_SPI_MAIN_7_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI7_IO_CLKSPII_CLK"}, {383, 4, "DEV_MCSPI7_IO_CLKSPIO_CLK", "Output clock"}, {383, 5, "DEV_MCSPI7_VBUSP_CLK", "Input clock"}, {0, 0, "DEV_MCU_ADC12FC_16FFC0_ADC_CLK", "Input muxed clock"}, {0, 1, "DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_ADC12FC_16FFC0_ADC_CLK"}, {0, 2, "DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC12FC_16FFC0_ADC_CLK"}, {0, 3, "DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC12FC_16FFC0_ADC_CLK"}, {0, 4, "DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC12FC_16FFC0_ADC_CLK"}, {0, 5, "DEV_MCU_ADC12FC_16FFC0_SYS_CLK", "Input clock"}, {0, 6, "DEV_MCU_ADC12FC_16FFC0_VBUS_CLK", "Input clock"}, {1, 0, "DEV_MCU_ADC12FC_16FFC1_ADC_CLK", "Input muxed clock"}, {1, 1, "DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_ADC12FC_16FFC1_ADC_CLK"}, {1, 2, "DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC12FC_16FFC1_ADC_CLK"}, {1, 3, "DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC12FC_16FFC1_ADC_CLK"}, {1, 4, "DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC12FC_16FFC1_ADC_CLK"}, {1, 5, "DEV_MCU_ADC12FC_16FFC1_SYS_CLK", "Input clock"}, {1, 6, "DEV_MCU_ADC12FC_16FFC1_VBUS_CLK", "Input clock"}, {63, 0, "DEV_MCU_CPSW0_CPPI_CLK_CLK", "Input clock"}, {63, 1, "DEV_MCU_CPSW0_CPTS_GENF0", "Output clock"}, {63, 3, "DEV_MCU_CPSW0_CPTS_RFT_CLK", "Input muxed clock"}, {63, 4, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {63, 5, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {63, 6, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {63, 7, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {63, 8, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {63, 9, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {63, 10, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {63, 11, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {63, 12, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {63, 13, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {63, 14, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {63, 15, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {63, 16, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {63, 17, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {63, 18, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {63, 19, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"}, {63, 20, "DEV_MCU_CPSW0_GMII1_MR_CLK", "Input clock"}, {63, 21, "DEV_MCU_CPSW0_GMII1_MT_CLK", "Input clock"}, {63, 22, "DEV_MCU_CPSW0_GMII_RFT_CLK", "Input clock"}, {63, 23, "DEV_MCU_CPSW0_MDIO_MDCLK_O", "Output clock"}, {63, 24, "DEV_MCU_CPSW0_RGMII1_RXC_I", "Input clock"}, {63, 26, "DEV_MCU_CPSW0_RGMII1_TXC_O", "Output clock"}, {63, 27, "DEV_MCU_CPSW0_RGMII_MHZ_250_CLK", "Input clock"}, {63, 28, "DEV_MCU_CPSW0_RGMII_MHZ_50_CLK", "Input clock"}, {63, 29, "DEV_MCU_CPSW0_RGMII_MHZ_5_CLK", "Input clock"}, {63, 30, "DEV_MCU_CPSW0_RMII_MHZ_50_CLK", "Input clock"}, {71, 0, "DEV_MCU_CPT2_AGGR0_VCLK_CLK", "Input clock"}, {88, 0, "DEV_MCU_DCC0_DCC_CLKSRC0_CLK", "Input clock"}, {88, 1, "DEV_MCU_DCC0_DCC_CLKSRC1_CLK", "Input clock"}, {88, 2, "DEV_MCU_DCC0_DCC_CLKSRC2_CLK", "Input clock"}, {88, 3, "DEV_MCU_DCC0_DCC_CLKSRC3_CLK", "Input clock"}, {88, 4, "DEV_MCU_DCC0_DCC_CLKSRC4_CLK", "Input clock"}, {88, 5, "DEV_MCU_DCC0_DCC_CLKSRC5_CLK", "Input clock"}, {88, 6, "DEV_MCU_DCC0_DCC_CLKSRC6_CLK", "Input clock"}, {88, 7, "DEV_MCU_DCC0_DCC_CLKSRC7_CLK", "Input clock"}, {88, 8, "DEV_MCU_DCC0_DCC_INPUT00_CLK", "Input clock"}, {88, 9, "DEV_MCU_DCC0_DCC_INPUT01_CLK", "Input clock"}, {88, 10, "DEV_MCU_DCC0_DCC_INPUT02_CLK", "Input clock"}, {88, 11, "DEV_MCU_DCC0_DCC_INPUT10_CLK", "Input clock"}, {88, 12, "DEV_MCU_DCC0_VBUS_CLK", "Input clock"}, {89, 0, "DEV_MCU_DCC1_DCC_CLKSRC0_CLK", "Input clock"}, {89, 1, "DEV_MCU_DCC1_DCC_CLKSRC1_CLK", "Input clock"}, {89, 2, "DEV_MCU_DCC1_DCC_CLKSRC2_CLK", "Input clock"}, {89, 3, "DEV_MCU_DCC1_DCC_CLKSRC3_CLK", "Input clock"}, {89, 4, "DEV_MCU_DCC1_DCC_CLKSRC4_CLK", "Input clock"}, {89, 5, "DEV_MCU_DCC1_DCC_CLKSRC5_CLK", "Input clock"}, {89, 6, "DEV_MCU_DCC1_DCC_CLKSRC6_CLK", "Input clock"}, {89, 7, "DEV_MCU_DCC1_DCC_CLKSRC7_CLK", "Input clock"}, {89, 8, "DEV_MCU_DCC1_DCC_INPUT00_CLK", "Input clock"}, {89, 9, "DEV_MCU_DCC1_DCC_INPUT01_CLK", "Input clock"}, {89, 10, "DEV_MCU_DCC1_DCC_INPUT02_CLK", "Input clock"}, {89, 11, "DEV_MCU_DCC1_DCC_INPUT10_CLK", "Input clock"}, {89, 12, "DEV_MCU_DCC1_VBUS_CLK", "Input clock"}, {90, 0, "DEV_MCU_DCC2_DCC_CLKSRC0_CLK", "Input clock"}, {90, 1, "DEV_MCU_DCC2_DCC_CLKSRC1_CLK", "Input clock"}, {90, 2, "DEV_MCU_DCC2_DCC_CLKSRC2_CLK", "Input clock"}, {90, 3, "DEV_MCU_DCC2_DCC_CLKSRC3_CLK", "Input clock"}, {90, 4, "DEV_MCU_DCC2_DCC_CLKSRC4_CLK", "Input clock"}, {90, 6, "DEV_MCU_DCC2_DCC_CLKSRC6_CLK", "Input clock"}, {90, 7, "DEV_MCU_DCC2_DCC_CLKSRC7_CLK", "Input clock"}, {90, 8, "DEV_MCU_DCC2_DCC_INPUT00_CLK", "Input clock"}, {90, 9, "DEV_MCU_DCC2_DCC_INPUT01_CLK", "Input clock"}, {90, 10, "DEV_MCU_DCC2_DCC_INPUT02_CLK", "Input clock"}, {90, 11, "DEV_MCU_DCC2_DCC_INPUT10_CLK", "Input clock"}, {90, 12, "DEV_MCU_DCC2_VBUS_CLK", "Input clock"}, {148, 0, "DEV_MCU_ESM0_CLK", "Input clock"}, {158, 0, "DEV_MCU_FSS0_FSAS_0_GCLK", "Input clock"}, {160, 0, "DEV_MCU_FSS0_HYPERBUS1P0_0_CBA_CLK", "Input clock"}, {160, 2, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_CLK", "Input clock"}, {160, 4, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_INV_CLK", "Input clock"}, {160, 6, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_CLK", "Input clock"}, {160, 8, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_INV_CLK", "Input clock"}, {160, 10, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_N", "Output clock"}, {160, 11, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_P", "Output clock"}, {161, 0, "DEV_MCU_FSS0_OSPI_0_OSPI_DQS_CLK", "Input clock"}, {161, 1, "DEV_MCU_FSS0_OSPI_0_OSPI_HCLK_CLK", "Input clock"}, {161, 2, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK", "Input muxed clock"}, {161, 3, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI0_DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK"}, {161, 4, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_OSPI_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK"}, {161, 5, "DEV_MCU_FSS0_OSPI_0_OSPI_OCLK_CLK", "Output clock"}, {161, 6, "DEV_MCU_FSS0_OSPI_0_OSPI_PCLK_CLK", "Input clock"}, {161, 7, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK", "Input muxed clock"}, {161, 8, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK"}, {161, 9, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK"}, {162, 0, "DEV_MCU_FSS0_OSPI_1_OSPI_DQS_CLK", "Input clock"}, {162, 1, "DEV_MCU_FSS0_OSPI_1_OSPI_HCLK_CLK", "Input clock"}, {162, 2, "DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK", "Input muxed clock"}, {162, 3, "DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI1_DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK"}, {162, 4, "DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_1_OSPI_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK"}, {162, 5, "DEV_MCU_FSS0_OSPI_1_OSPI_OCLK_CLK", "Output clock"}, {162, 6, "DEV_MCU_FSS0_OSPI_1_OSPI_PCLK_CLK", "Input clock"}, {162, 7, "DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK", "Input muxed clock"}, {162, 8, "DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK"}, {162, 9, "DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK"}, {277, 0, "DEV_MCU_I2C0_CLK", "Input clock"}, {277, 1, "DEV_MCU_I2C0_PISCL", "Input clock"}, {277, 2, "DEV_MCU_I2C0_PISYS_CLK", "Input clock"}, {277, 3, "DEV_MCU_I2C0_PORSCL", "Output clock"}, {278, 0, "DEV_MCU_I2C1_CLK", "Input clock"}, {278, 1, "DEV_MCU_I2C1_PISCL", "Input clock"}, {278, 2, "DEV_MCU_I2C1_PISYS_CLK", "Input clock"}, {278, 3, "DEV_MCU_I2C1_PORSCL", "Output clock"}, {170, 0, "DEV_MCU_I3C0_I3C_PCLK_CLK", "Input clock"}, {170, 1, "DEV_MCU_I3C0_I3C_SCL_DI", "Input clock"}, {170, 2, "DEV_MCU_I3C0_I3C_SCL_DO", "Output clock"}, {170, 3, "DEV_MCU_I3C0_I3C_SCLK_CLK", "Input clock"}, {170, 4, "DEV_MCU_I3C0_I3C_SDA_DI", "Input clock"}, {171, 0, "DEV_MCU_I3C1_I3C_PCLK_CLK", "Input clock"}, {171, 3, "DEV_MCU_I3C1_I3C_SCLK_CLK", "Input clock"}, {263, 0, "DEV_MCU_MCAN0_MCANSS_CAN_RXD", "Input clock"}, {263, 1, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"}, {263, 2, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, {263, 3, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, {263, 4, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, {263, 5, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, {263, 6, "DEV_MCU_MCAN0_MCANSS_HCLK_CLK", "Input clock"}, {264, 0, "DEV_MCU_MCAN1_MCANSS_CAN_RXD", "Input clock"}, {264, 1, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"}, {264, 2, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, {264, 3, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, {264, 4, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, {264, 5, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, {264, 6, "DEV_MCU_MCAN1_MCANSS_HCLK_CLK", "Input clock"}, {384, 0, "DEV_MCU_MCSPI0_CLKSPIREF_CLK", "Input clock"}, {384, 1, "DEV_MCU_MCSPI0_IO_CLKSPII_CLK", "Input muxed clock"}, {384, 2, "DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI0_CLK_OUT", "Parent input clock option to DEV_MCU_MCSPI0_IO_CLKSPII_CLK"}, {384, 3, "DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MCU_0_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCU_MCSPI0_IO_CLKSPII_CLK"}, {384, 4, "DEV_MCU_MCSPI0_IO_CLKSPIO_CLK", "Output clock"}, {384, 5, "DEV_MCU_MCSPI0_VBUSP_CLK", "Input clock"}, {385, 0, "DEV_MCU_MCSPI1_CLKSPIREF_CLK", "Input clock"}, {385, 1, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK", "Input muxed clock"}, {385, 2, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK"}, {385, 3, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_MCU_SPI1_CLK_LPBK_MUX_OUT0", "Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK"}, {385, 4, "DEV_MCU_MCSPI1_IO_CLKSPIO_CLK", "Output clock"}, {385, 5, "DEV_MCU_MCSPI1_VBUSP_CLK", "Input clock"}, {386, 0, "DEV_MCU_MCSPI2_CLKSPIREF_CLK", "Input clock"}, {386, 1, "DEV_MCU_MCSPI2_IO_CLKSPII_CLK", "Input clock"}, {386, 2, "DEV_MCU_MCSPI2_IO_CLKSPIO_CLK", "Output clock"}, {386, 3, "DEV_MCU_MCSPI2_VBUSP_CLK", "Input clock"}, {324, 0, "DEV_MCU_NAVSS0_INTR_ROUTER_0_INTR_CLK", "Input clock"}, {325, 0, "DEV_MCU_NAVSS0_MCRC_0_CLK", "Input clock"}, {326, 0, "DEV_MCU_NAVSS0_MODSS_VD2CLK", "Input clock"}, {327, 0, "DEV_MCU_NAVSS0_PROXY0_CLK_CLK", "Input clock"}, {328, 0, "DEV_MCU_NAVSS0_RINGACC0_SYS_CLK", "Input clock"}, {329, 0, "DEV_MCU_NAVSS0_UDMAP_0_SYS_CLK", "Input clock"}, {330, 0, "DEV_MCU_NAVSS0_UDMASS_VD2CLK", "Input clock"}, {331, 0, "DEV_MCU_NAVSS0_UDMASS_INTA_0_SYS_CLK", "Input clock"}, {238, 0, "DEV_MCU_PBIST0_CLK1_CLK", "Input clock"}, {238, 1, "DEV_MCU_PBIST0_CLK2_CLK", "Input clock"}, {238, 2, "DEV_MCU_PBIST0_CLK3_CLK", "Input clock"}, {238, 3, "DEV_MCU_PBIST0_CLK4_CLK", "Input clock"}, {238, 4, "DEV_MCU_PBIST0_CLK5_CLK", "Input clock"}, {238, 5, "DEV_MCU_PBIST0_CLK6_CLK", "Input clock"}, {238, 6, "DEV_MCU_PBIST0_CLK7_CLK", "Input clock"}, {238, 7, "DEV_MCU_PBIST0_CLK8_CLK", "Input clock"}, {239, 0, "DEV_MCU_PBIST1_CLK1_CLK", "Input clock"}, {239, 1, "DEV_MCU_PBIST1_CLK2_CLK", "Input clock"}, {239, 2, "DEV_MCU_PBIST1_CLK3_CLK", "Input clock"}, {239, 3, "DEV_MCU_PBIST1_CLK4_CLK", "Input clock"}, {239, 4, "DEV_MCU_PBIST1_CLK5_CLK", "Input clock"}, {239, 5, "DEV_MCU_PBIST1_CLK6_CLK", "Input clock"}, {239, 6, "DEV_MCU_PBIST1_CLK7_CLK", "Input clock"}, {239, 7, "DEV_MCU_PBIST1_CLK8_CLK", "Input clock"}, {240, 7, "DEV_MCU_PBIST2_CLK8_CLK", "Input clock"}, {346, 0, "DEV_MCU_R5FSS0_CORE0_CPU_CLK", "Input muxed clock"}, {346, 1, "DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK"}, {346, 2, "DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3", "Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK"}, {346, 3, "DEV_MCU_R5FSS0_CORE0_INTERFACE_CLK", "Input clock"}, {346, 4, "DEV_MCU_R5FSS0_CORE0_INTERFACE_PHASE", "Input clock"}, {347, 0, "DEV_MCU_R5FSS0_CORE1_CPU_CLK", "Input muxed clock"}, {347, 1, "DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK"}, {347, 2, "DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3", "Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK"}, {347, 3, "DEV_MCU_R5FSS0_CORE1_INTERFACE_CLK", "Input clock"}, {347, 4, "DEV_MCU_R5FSS0_CORE1_INTERFACE_PHASE", "Input clock"}, {367, 0, "DEV_MCU_RTI0_RTI_CLK", "Input muxed clock"}, {367, 1, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, {367, 2, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, {367, 3, "DEV_MCU_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, {367, 4, "DEV_MCU_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, {367, 9, "DEV_MCU_RTI0_VBUSP_CLK", "Input clock"}, {368, 0, "DEV_MCU_RTI1_RTI_CLK", "Input muxed clock"}, {368, 1, "DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"}, {368, 2, "DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"}, {368, 3, "DEV_MCU_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"}, {368, 4, "DEV_MCU_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"}, {368, 9, "DEV_MCU_RTI1_VBUSP_CLK", "Input clock"}, {35, 0, "DEV_MCU_TIMER0_TIMER_HCLK_CLK", "Input clock"}, {35, 1, "DEV_MCU_TIMER0_TIMER_PWM", "Output clock"}, {35, 2, "DEV_MCU_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"}, {35, 3, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 4, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 5, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 6, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 7, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 8, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 9, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 10, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {117, 0, "DEV_MCU_TIMER1_TIMER_HCLK_CLK", "Input clock"}, {117, 2, "DEV_MCU_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"}, {117, 3, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT1", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, {117, 4, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, {118, 0, "DEV_MCU_TIMER2_TIMER_HCLK_CLK", "Input clock"}, {118, 1, "DEV_MCU_TIMER2_TIMER_PWM", "Output clock"}, {118, 2, "DEV_MCU_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"}, {118, 3, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {118, 4, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {118, 5, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {118, 6, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {118, 7, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {118, 8, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {118, 9, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {118, 10, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {119, 0, "DEV_MCU_TIMER3_TIMER_HCLK_CLK", "Input clock"}, {119, 2, "DEV_MCU_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"}, {119, 3, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT3", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, {119, 4, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, {120, 0, "DEV_MCU_TIMER4_TIMER_HCLK_CLK", "Input clock"}, {120, 1, "DEV_MCU_TIMER4_TIMER_PWM", "Output clock"}, {120, 2, "DEV_MCU_TIMER4_TIMER_TCLK_CLK", "Input muxed clock"}, {120, 3, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, {120, 4, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, {120, 5, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, {120, 6, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, {120, 7, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, {120, 8, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, {120, 9, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, {120, 10, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"}, {121, 0, "DEV_MCU_TIMER5_TIMER_HCLK_CLK", "Input clock"}, {121, 2, "DEV_MCU_TIMER5_TIMER_TCLK_CLK", "Input muxed clock"}, {121, 3, "DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT5", "Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK"}, {121, 4, "DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_4_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK"}, {122, 0, "DEV_MCU_TIMER6_TIMER_HCLK_CLK", "Input clock"}, {122, 1, "DEV_MCU_TIMER6_TIMER_PWM", "Output clock"}, {122, 2, "DEV_MCU_TIMER6_TIMER_TCLK_CLK", "Input muxed clock"}, {122, 3, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, {122, 4, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, {122, 5, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, {122, 6, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, {122, 7, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, {122, 8, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, {122, 9, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, {122, 10, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"}, {123, 0, "DEV_MCU_TIMER7_TIMER_HCLK_CLK", "Input clock"}, {123, 2, "DEV_MCU_TIMER7_TIMER_TCLK_CLK", "Input muxed clock"}, {123, 3, "DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT7", "Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK"}, {123, 4, "DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_6_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK"}, {124, 0, "DEV_MCU_TIMER8_TIMER_HCLK_CLK", "Input clock"}, {124, 1, "DEV_MCU_TIMER8_TIMER_PWM", "Output clock"}, {124, 2, "DEV_MCU_TIMER8_TIMER_TCLK_CLK", "Input muxed clock"}, {124, 3, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, {124, 4, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, {124, 5, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, {124, 6, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, {124, 7, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, {124, 8, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, {124, 9, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, {124, 10, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"}, {125, 0, "DEV_MCU_TIMER9_TIMER_HCLK_CLK", "Input clock"}, {125, 2, "DEV_MCU_TIMER9_TIMER_TCLK_CLK", "Input muxed clock"}, {125, 3, "DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT9", "Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK"}, {125, 4, "DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_8_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK"}, {149, 0, "DEV_MCU_UART0_FCLK_CLK", "Input muxed clock"}, {149, 1, "DEV_MCU_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_UART0_FCLK_CLK"}, {149, 2, "DEV_MCU_UART0_FCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT5_CLK", "Parent input clock option to DEV_MCU_UART0_FCLK_CLK"}, {149, 5, "DEV_MCU_UART0_VBUSP_CLK", "Input clock"}, {140, 1, "DEV_MMCSD0_EMMCSS_VBUS_CLK", "Input clock"}, {140, 2, "DEV_MMCSD0_EMMCSS_XIN_CLK", "Input muxed clock"}, {140, 3, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"}, {140, 4, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"}, {140, 5, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"}, {140, 6, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"}, {141, 0, "DEV_MMCSD1_EMMCSDSS_IO_CLK_I", "Input clock"}, {141, 1, "DEV_MMCSD1_EMMCSDSS_IO_CLK_O", "Output clock"}, {141, 3, "DEV_MMCSD1_EMMCSDSS_VBUS_CLK", "Input clock"}, {141, 4, "DEV_MMCSD1_EMMCSDSS_XIN_CLK", "Input muxed clock"}, {141, 5, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"}, {141, 6, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"}, {141, 7, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"}, {141, 8, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"}, {280, 0, "DEV_NAVSS0_CPTS0_GENF2", "Output clock"}, {280, 1, "DEV_NAVSS0_CPTS0_GENF3", "Output clock"}, {281, 0, "DEV_NAVSS0_BCDMA_0_CLK", "Input clock"}, {282, 0, "DEV_NAVSS0_CPTS_0_RCLK", "Input muxed clock"}, {282, 1, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {282, 2, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {282, 3, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {282, 4, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {282, 5, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {282, 6, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {282, 7, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {282, 8, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {282, 9, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {282, 10, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {282, 11, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {282, 12, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {282, 13, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {282, 14, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {282, 15, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {282, 16, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"}, {282, 17, "DEV_NAVSS0_CPTS_0_TS_GENF0", "Output clock"}, {282, 18, "DEV_NAVSS0_CPTS_0_TS_GENF1", "Output clock"}, {282, 21, "DEV_NAVSS0_CPTS_0_VBUSP_GCLK", "Input clock"}, {283, 0, "DEV_NAVSS0_INTR_0_INTR_CLK", "Input clock"}, {284, 0, "DEV_NAVSS0_MAILBOX1_0_VCLK_CLK", "Input clock"}, {285, 0, "DEV_NAVSS0_MAILBOX1_1_VCLK_CLK", "Input clock"}, {294, 0, "DEV_NAVSS0_MAILBOX1_10_VCLK_CLK", "Input clock"}, {295, 0, "DEV_NAVSS0_MAILBOX1_11_VCLK_CLK", "Input clock"}, {286, 0, "DEV_NAVSS0_MAILBOX1_2_VCLK_CLK", "Input clock"}, {287, 0, "DEV_NAVSS0_MAILBOX1_3_VCLK_CLK", "Input clock"}, {288, 0, "DEV_NAVSS0_MAILBOX1_4_VCLK_CLK", "Input clock"}, {289, 0, "DEV_NAVSS0_MAILBOX1_5_VCLK_CLK", "Input clock"}, {290, 0, "DEV_NAVSS0_MAILBOX1_6_VCLK_CLK", "Input clock"}, {291, 0, "DEV_NAVSS0_MAILBOX1_7_VCLK_CLK", "Input clock"}, {292, 0, "DEV_NAVSS0_MAILBOX1_8_VCLK_CLK", "Input clock"}, {293, 0, "DEV_NAVSS0_MAILBOX1_9_VCLK_CLK", "Input clock"}, {296, 0, "DEV_NAVSS0_MAILBOX_0_VCLK_CLK", "Input clock"}, {297, 0, "DEV_NAVSS0_MAILBOX_1_VCLK_CLK", "Input clock"}, {306, 0, "DEV_NAVSS0_MAILBOX_10_VCLK_CLK", "Input clock"}, {307, 0, "DEV_NAVSS0_MAILBOX_11_VCLK_CLK", "Input clock"}, {298, 0, "DEV_NAVSS0_MAILBOX_2_VCLK_CLK", "Input clock"}, {299, 0, "DEV_NAVSS0_MAILBOX_3_VCLK_CLK", "Input clock"}, {300, 0, "DEV_NAVSS0_MAILBOX_4_VCLK_CLK", "Input clock"}, {301, 0, "DEV_NAVSS0_MAILBOX_5_VCLK_CLK", "Input clock"}, {302, 0, "DEV_NAVSS0_MAILBOX_6_VCLK_CLK", "Input clock"}, {303, 0, "DEV_NAVSS0_MAILBOX_7_VCLK_CLK", "Input clock"}, {304, 0, "DEV_NAVSS0_MAILBOX_8_VCLK_CLK", "Input clock"}, {305, 0, "DEV_NAVSS0_MAILBOX_9_VCLK_CLK", "Input clock"}, {308, 0, "DEV_NAVSS0_MCRC_0_CLK", "Input clock"}, {309, 0, "DEV_NAVSS0_MODSS_VD2CLK", "Input clock"}, {310, 0, "DEV_NAVSS0_MODSS_INTA_0_SYS_CLK", "Input clock"}, {311, 0, "DEV_NAVSS0_MODSS_INTA_1_SYS_CLK", "Input clock"}, {312, 0, "DEV_NAVSS0_PROXY_0_CLK_CLK", "Input clock"}, {313, 0, "DEV_NAVSS0_PVU_0_CLK_CLK", "Input clock"}, {314, 0, "DEV_NAVSS0_PVU_1_CLK_CLK", "Input clock"}, {315, 0, "DEV_NAVSS0_RINGACC_0_SYS_CLK", "Input clock"}, {316, 0, "DEV_NAVSS0_SPINLOCK_0_CLK", "Input clock"}, {317, 0, "DEV_NAVSS0_TIMERMGR_0_EON_TICK_EVT", "Input clock"}, {317, 1, "DEV_NAVSS0_TIMERMGR_0_VCLK_CLK", "Input clock"}, {318, 0, "DEV_NAVSS0_TIMERMGR_1_EON_TICK_EVT", "Input clock"}, {318, 1, "DEV_NAVSS0_TIMERMGR_1_VCLK_CLK", "Input clock"}, {319, 0, "DEV_NAVSS0_UDMAP_0_SYS_CLK", "Input clock"}, {320, 0, "DEV_NAVSS0_UDMASS_VD2CLK", "Input clock"}, {321, 0, "DEV_NAVSS0_UDMASS_INTA_0_SYS_CLK", "Input clock"}, {322, 0, "DEV_NAVSS0_VIRTSS_VD2CLK", "Input clock"}, {232, 7, "DEV_PBIST0_CLK8_CLK", "Input clock"}, {233, 7, "DEV_PBIST1_CLK8_CLK", "Input clock"}, {236, 7, "DEV_PBIST10_CLK8_CLK", "Input clock"}, {227, 6, "DEV_PBIST11_CLK7_CLK", "Input clock"}, {237, 7, "DEV_PBIST14_CLK8_CLK", "Input clock"}, {235, 7, "DEV_PBIST2_CLK8_CLK", "Input clock"}, {231, 7, "DEV_PBIST3_CLK8_CLK", "Input clock"}, {234, 7, "DEV_PBIST4_CLK8_CLK", "Input clock"}, {226, 7, "DEV_PBIST5_CLK8_CLK", "Input clock"}, {332, 0, "DEV_PCIE0_PCIE_CBA_CLK", "Input clock"}, {332, 2, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK", "Input muxed clock"}, {332, 3, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {332, 4, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {332, 5, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {332, 6, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {332, 7, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {332, 8, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {332, 9, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {332, 10, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {332, 11, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {332, 12, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {332, 13, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {332, 14, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {332, 15, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {332, 16, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {332, 17, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {332, 18, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"}, {332, 19, "DEV_PCIE0_PCIE_LANE0_REFCLK", "Input clock"}, {332, 20, "DEV_PCIE0_PCIE_LANE0_RXCLK", "Input clock"}, {332, 21, "DEV_PCIE0_PCIE_LANE0_RXFCLK", "Input clock"}, {332, 22, "DEV_PCIE0_PCIE_LANE0_TXCLK", "Output clock"}, {332, 23, "DEV_PCIE0_PCIE_LANE0_TXFCLK", "Input clock"}, {332, 24, "DEV_PCIE0_PCIE_LANE0_TXMCLK", "Input clock"}, {332, 25, "DEV_PCIE0_PCIE_LANE1_REFCLK", "Input clock"}, {332, 26, "DEV_PCIE0_PCIE_LANE1_RXCLK", "Input clock"}, {332, 27, "DEV_PCIE0_PCIE_LANE1_RXFCLK", "Input clock"}, {332, 28, "DEV_PCIE0_PCIE_LANE1_TXCLK", "Output clock"}, {332, 29, "DEV_PCIE0_PCIE_LANE1_TXFCLK", "Input clock"}, {332, 30, "DEV_PCIE0_PCIE_LANE1_TXMCLK", "Input clock"}, {332, 31, "DEV_PCIE0_PCIE_LANE2_REFCLK", "Input clock"}, {332, 32, "DEV_PCIE0_PCIE_LANE2_RXCLK", "Input clock"}, {332, 33, "DEV_PCIE0_PCIE_LANE2_RXFCLK", "Input clock"}, {332, 34, "DEV_PCIE0_PCIE_LANE2_TXCLK", "Output clock"}, {332, 35, "DEV_PCIE0_PCIE_LANE2_TXFCLK", "Input clock"}, {332, 36, "DEV_PCIE0_PCIE_LANE2_TXMCLK", "Input clock"}, {332, 37, "DEV_PCIE0_PCIE_LANE3_REFCLK", "Input clock"}, {332, 38, "DEV_PCIE0_PCIE_LANE3_RXCLK", "Input clock"}, {332, 39, "DEV_PCIE0_PCIE_LANE3_RXFCLK", "Input clock"}, {332, 40, "DEV_PCIE0_PCIE_LANE3_TXCLK", "Output clock"}, {332, 41, "DEV_PCIE0_PCIE_LANE3_TXFCLK", "Input clock"}, {332, 42, "DEV_PCIE0_PCIE_LANE3_TXMCLK", "Input clock"}, {332, 43, "DEV_PCIE0_PCIE_PM_CLK", "Input clock"}, {333, 0, "DEV_PCIE1_PCIE_CBA_CLK", "Input clock"}, {333, 2, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK", "Input muxed clock"}, {333, 3, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {333, 4, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {333, 5, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {333, 6, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {333, 7, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {333, 8, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {333, 9, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {333, 10, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {333, 11, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {333, 12, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {333, 13, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {333, 14, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {333, 15, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {333, 16, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {333, 17, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {333, 18, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"}, {333, 19, "DEV_PCIE1_PCIE_LANE0_REFCLK", "Input clock"}, {333, 20, "DEV_PCIE1_PCIE_LANE0_RXCLK", "Input clock"}, {333, 21, "DEV_PCIE1_PCIE_LANE0_RXFCLK", "Input clock"}, {333, 22, "DEV_PCIE1_PCIE_LANE0_TXCLK", "Output clock"}, {333, 23, "DEV_PCIE1_PCIE_LANE0_TXFCLK", "Input clock"}, {333, 24, "DEV_PCIE1_PCIE_LANE0_TXMCLK", "Input clock"}, {333, 25, "DEV_PCIE1_PCIE_LANE1_REFCLK", "Input clock"}, {333, 26, "DEV_PCIE1_PCIE_LANE1_RXCLK", "Input clock"}, {333, 27, "DEV_PCIE1_PCIE_LANE1_RXFCLK", "Input clock"}, {333, 28, "DEV_PCIE1_PCIE_LANE1_TXCLK", "Output clock"}, {333, 29, "DEV_PCIE1_PCIE_LANE1_TXFCLK", "Input clock"}, {333, 30, "DEV_PCIE1_PCIE_LANE1_TXMCLK", "Input clock"}, {333, 31, "DEV_PCIE1_PCIE_LANE2_REFCLK", "Input clock"}, {333, 32, "DEV_PCIE1_PCIE_LANE2_RXCLK", "Input clock"}, {333, 33, "DEV_PCIE1_PCIE_LANE2_RXFCLK", "Input clock"}, {333, 34, "DEV_PCIE1_PCIE_LANE2_TXCLK", "Output clock"}, {333, 35, "DEV_PCIE1_PCIE_LANE2_TXFCLK", "Input clock"}, {333, 36, "DEV_PCIE1_PCIE_LANE2_TXMCLK", "Input clock"}, {333, 37, "DEV_PCIE1_PCIE_LANE3_REFCLK", "Input clock"}, {333, 38, "DEV_PCIE1_PCIE_LANE3_RXCLK", "Input clock"}, {333, 39, "DEV_PCIE1_PCIE_LANE3_RXFCLK", "Input clock"}, {333, 40, "DEV_PCIE1_PCIE_LANE3_TXCLK", "Output clock"}, {333, 41, "DEV_PCIE1_PCIE_LANE3_TXFCLK", "Input clock"}, {333, 42, "DEV_PCIE1_PCIE_LANE3_TXMCLK", "Input clock"}, {333, 43, "DEV_PCIE1_PCIE_PM_CLK", "Input clock"}, {334, 0, "DEV_PCIE2_PCIE_CBA_CLK", "Input clock"}, {334, 2, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK", "Input muxed clock"}, {334, 3, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, {334, 4, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, {334, 5, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, {334, 6, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, {334, 7, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, {334, 8, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, {334, 9, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, {334, 10, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, {334, 11, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, {334, 12, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, {334, 13, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, {334, 14, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, {334, 15, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, {334, 16, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, {334, 17, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, {334, 18, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"}, {334, 19, "DEV_PCIE2_PCIE_LANE0_REFCLK", "Input clock"}, {334, 20, "DEV_PCIE2_PCIE_LANE0_RXCLK", "Input clock"}, {334, 21, "DEV_PCIE2_PCIE_LANE0_RXFCLK", "Input clock"}, {334, 22, "DEV_PCIE2_PCIE_LANE0_TXCLK", "Output clock"}, {334, 23, "DEV_PCIE2_PCIE_LANE0_TXFCLK", "Input clock"}, {334, 24, "DEV_PCIE2_PCIE_LANE0_TXMCLK", "Input clock"}, {334, 25, "DEV_PCIE2_PCIE_LANE1_REFCLK", "Input clock"}, {334, 26, "DEV_PCIE2_PCIE_LANE1_RXCLK", "Input clock"}, {334, 27, "DEV_PCIE2_PCIE_LANE1_RXFCLK", "Input clock"}, {334, 28, "DEV_PCIE2_PCIE_LANE1_TXCLK", "Output clock"}, {334, 29, "DEV_PCIE2_PCIE_LANE1_TXFCLK", "Input clock"}, {334, 30, "DEV_PCIE2_PCIE_LANE1_TXMCLK", "Input clock"}, {334, 43, "DEV_PCIE2_PCIE_PM_CLK", "Input clock"}, {335, 0, "DEV_PCIE3_PCIE_CBA_CLK", "Input clock"}, {335, 2, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK", "Input muxed clock"}, {335, 3, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, {335, 4, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, {335, 5, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, {335, 6, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, {335, 7, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, {335, 8, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, {335, 9, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, {335, 10, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, {335, 11, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, {335, 12, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, {335, 13, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, {335, 14, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, {335, 15, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, {335, 16, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, {335, 17, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, {335, 18, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"}, {335, 19, "DEV_PCIE3_PCIE_LANE0_REFCLK", "Input clock"}, {335, 20, "DEV_PCIE3_PCIE_LANE0_RXCLK", "Input clock"}, {335, 21, "DEV_PCIE3_PCIE_LANE0_RXFCLK", "Input clock"}, {335, 22, "DEV_PCIE3_PCIE_LANE0_TXCLK", "Output clock"}, {335, 23, "DEV_PCIE3_PCIE_LANE0_TXFCLK", "Input clock"}, {335, 24, "DEV_PCIE3_PCIE_LANE0_TXMCLK", "Input clock"}, {335, 25, "DEV_PCIE3_PCIE_LANE1_REFCLK", "Input clock"}, {335, 26, "DEV_PCIE3_PCIE_LANE1_RXCLK", "Input clock"}, {335, 27, "DEV_PCIE3_PCIE_LANE1_RXFCLK", "Input clock"}, {335, 28, "DEV_PCIE3_PCIE_LANE1_TXCLK", "Output clock"}, {335, 29, "DEV_PCIE3_PCIE_LANE1_TXFCLK", "Input clock"}, {335, 30, "DEV_PCIE3_PCIE_LANE1_TXMCLK", "Input clock"}, {335, 43, "DEV_PCIE3_PCIE_PM_CLK", "Input clock"}, {201, 0, "DEV_PSC0_CLK", "Input clock"}, {201, 1, "DEV_PSC0_SLOW_CLK", "Input clock"}, {339, 0, "DEV_R5FSS0_CORE0_CPU_CLK", "Input clock"}, {339, 1, "DEV_R5FSS0_CORE0_INTERFACE_CLK", "Input clock"}, {340, 0, "DEV_R5FSS0_CORE1_CPU_CLK", "Input clock"}, {340, 1, "DEV_R5FSS0_CORE1_INTERFACE_CLK", "Input clock"}, {341, 0, "DEV_R5FSS1_CORE0_CPU_CLK", "Input clock"}, {341, 1, "DEV_R5FSS1_CORE0_INTERFACE_CLK", "Input clock"}, {342, 0, "DEV_R5FSS1_CORE1_CPU_CLK", "Input clock"}, {342, 1, "DEV_R5FSS1_CORE1_INTERFACE_CLK", "Input clock"}, {343, 0, "DEV_R5FSS2_CORE0_CPU_CLK", "Input clock"}, {343, 1, "DEV_R5FSS2_CORE0_INTERFACE_CLK", "Input clock"}, {344, 0, "DEV_R5FSS2_CORE1_CPU_CLK", "Input clock"}, {344, 1, "DEV_R5FSS2_CORE1_INTERFACE_CLK", "Input clock"}, {348, 0, "DEV_RTI0_RTI_CLK", "Input muxed clock"}, {348, 1, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {348, 2, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {348, 3, "DEV_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {348, 4, "DEV_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {348, 5, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {348, 6, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {348, 7, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {348, 8, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {348, 9, "DEV_RTI0_VBUSP_CLK", "Input clock"}, {349, 0, "DEV_RTI1_RTI_CLK", "Input muxed clock"}, {349, 1, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {349, 2, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {349, 3, "DEV_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {349, 4, "DEV_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {349, 5, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {349, 6, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {349, 7, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {349, 8, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {349, 9, "DEV_RTI1_VBUSP_CLK", "Input clock"}, {360, 0, "DEV_RTI15_RTI_CLK", "Input muxed clock"}, {360, 1, "DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI15_RTI_CLK"}, {360, 2, "DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI15_RTI_CLK"}, {360, 3, "DEV_RTI15_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI15_RTI_CLK"}, {360, 4, "DEV_RTI15_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI15_RTI_CLK"}, {360, 5, "DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI15_RTI_CLK"}, {360, 6, "DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI15_RTI_CLK"}, {360, 7, "DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI15_RTI_CLK"}, {360, 8, "DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI15_RTI_CLK"}, {360, 9, "DEV_RTI15_VBUSP_CLK", "Input clock"}, {356, 0, "DEV_RTI16_RTI_CLK", "Input muxed clock"}, {356, 1, "DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI16_RTI_CLK"}, {356, 2, "DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI16_RTI_CLK"}, {356, 3, "DEV_RTI16_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI16_RTI_CLK"}, {356, 4, "DEV_RTI16_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI16_RTI_CLK"}, {356, 5, "DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI16_RTI_CLK"}, {356, 6, "DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI16_RTI_CLK"}, {356, 7, "DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI16_RTI_CLK"}, {356, 8, "DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI16_RTI_CLK"}, {356, 9, "DEV_RTI16_VBUSP_CLK", "Input clock"}, {357, 0, "DEV_RTI17_RTI_CLK", "Input muxed clock"}, {357, 1, "DEV_RTI17_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI17_RTI_CLK"}, {357, 2, "DEV_RTI17_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI17_RTI_CLK"}, {357, 3, "DEV_RTI17_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI17_RTI_CLK"}, {357, 4, "DEV_RTI17_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI17_RTI_CLK"}, {357, 5, "DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI17_RTI_CLK"}, {357, 6, "DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI17_RTI_CLK"}, {357, 7, "DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI17_RTI_CLK"}, {357, 8, "DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI17_RTI_CLK"}, {357, 9, "DEV_RTI17_VBUSP_CLK", "Input clock"}, {358, 0, "DEV_RTI18_RTI_CLK", "Input muxed clock"}, {358, 1, "DEV_RTI18_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI18_RTI_CLK"}, {358, 2, "DEV_RTI18_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI18_RTI_CLK"}, {358, 3, "DEV_RTI18_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI18_RTI_CLK"}, {358, 4, "DEV_RTI18_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI18_RTI_CLK"}, {358, 5, "DEV_RTI18_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI18_RTI_CLK"}, {358, 6, "DEV_RTI18_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI18_RTI_CLK"}, {358, 7, "DEV_RTI18_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI18_RTI_CLK"}, {358, 8, "DEV_RTI18_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI18_RTI_CLK"}, {358, 9, "DEV_RTI18_VBUSP_CLK", "Input clock"}, {359, 0, "DEV_RTI19_RTI_CLK", "Input muxed clock"}, {359, 1, "DEV_RTI19_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI19_RTI_CLK"}, {359, 2, "DEV_RTI19_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI19_RTI_CLK"}, {359, 3, "DEV_RTI19_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI19_RTI_CLK"}, {359, 4, "DEV_RTI19_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI19_RTI_CLK"}, {359, 5, "DEV_RTI19_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI19_RTI_CLK"}, {359, 6, "DEV_RTI19_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI19_RTI_CLK"}, {359, 7, "DEV_RTI19_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI19_RTI_CLK"}, {359, 8, "DEV_RTI19_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI19_RTI_CLK"}, {359, 9, "DEV_RTI19_VBUSP_CLK", "Input clock"}, {350, 0, "DEV_RTI2_RTI_CLK", "Input muxed clock"}, {350, 1, "DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI2_RTI_CLK"}, {350, 2, "DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI2_RTI_CLK"}, {350, 3, "DEV_RTI2_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI2_RTI_CLK"}, {350, 4, "DEV_RTI2_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI2_RTI_CLK"}, {350, 5, "DEV_RTI2_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI2_RTI_CLK"}, {350, 6, "DEV_RTI2_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI2_RTI_CLK"}, {350, 7, "DEV_RTI2_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI2_RTI_CLK"}, {350, 8, "DEV_RTI2_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI2_RTI_CLK"}, {350, 9, "DEV_RTI2_VBUSP_CLK", "Input clock"}, {361, 0, "DEV_RTI28_RTI_CLK", "Input muxed clock"}, {361, 1, "DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI28_RTI_CLK"}, {361, 2, "DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI28_RTI_CLK"}, {361, 3, "DEV_RTI28_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI28_RTI_CLK"}, {361, 4, "DEV_RTI28_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI28_RTI_CLK"}, {361, 5, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI28_RTI_CLK"}, {361, 6, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI28_RTI_CLK"}, {361, 7, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI28_RTI_CLK"}, {361, 8, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI28_RTI_CLK"}, {361, 9, "DEV_RTI28_VBUSP_CLK", "Input clock"}, {362, 0, "DEV_RTI29_RTI_CLK", "Input muxed clock"}, {362, 1, "DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI29_RTI_CLK"}, {362, 2, "DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI29_RTI_CLK"}, {362, 3, "DEV_RTI29_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI29_RTI_CLK"}, {362, 4, "DEV_RTI29_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI29_RTI_CLK"}, {362, 5, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI29_RTI_CLK"}, {362, 6, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI29_RTI_CLK"}, {362, 7, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI29_RTI_CLK"}, {362, 8, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI29_RTI_CLK"}, {362, 9, "DEV_RTI29_VBUSP_CLK", "Input clock"}, {351, 0, "DEV_RTI3_RTI_CLK", "Input muxed clock"}, {351, 1, "DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI3_RTI_CLK"}, {351, 2, "DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI3_RTI_CLK"}, {351, 3, "DEV_RTI3_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI3_RTI_CLK"}, {351, 4, "DEV_RTI3_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI3_RTI_CLK"}, {351, 5, "DEV_RTI3_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI3_RTI_CLK"}, {351, 6, "DEV_RTI3_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI3_RTI_CLK"}, {351, 7, "DEV_RTI3_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI3_RTI_CLK"}, {351, 8, "DEV_RTI3_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI3_RTI_CLK"}, {351, 9, "DEV_RTI3_VBUSP_CLK", "Input clock"}, {363, 0, "DEV_RTI30_RTI_CLK", "Input muxed clock"}, {363, 1, "DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI30_RTI_CLK"}, {363, 2, "DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI30_RTI_CLK"}, {363, 3, "DEV_RTI30_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI30_RTI_CLK"}, {363, 4, "DEV_RTI30_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI30_RTI_CLK"}, {363, 5, "DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI30_RTI_CLK"}, {363, 6, "DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI30_RTI_CLK"}, {363, 7, "DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI30_RTI_CLK"}, {363, 8, "DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI30_RTI_CLK"}, {363, 9, "DEV_RTI30_VBUSP_CLK", "Input clock"}, {364, 0, "DEV_RTI31_RTI_CLK", "Input muxed clock"}, {364, 1, "DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI31_RTI_CLK"}, {364, 2, "DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI31_RTI_CLK"}, {364, 3, "DEV_RTI31_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI31_RTI_CLK"}, {364, 4, "DEV_RTI31_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI31_RTI_CLK"}, {364, 5, "DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI31_RTI_CLK"}, {364, 6, "DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI31_RTI_CLK"}, {364, 7, "DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI31_RTI_CLK"}, {364, 8, "DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI31_RTI_CLK"}, {364, 9, "DEV_RTI31_VBUSP_CLK", "Input clock"}, {365, 0, "DEV_RTI32_RTI_CLK", "Input muxed clock"}, {365, 1, "DEV_RTI32_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI32_RTI_CLK"}, {365, 2, "DEV_RTI32_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI32_RTI_CLK"}, {365, 3, "DEV_RTI32_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI32_RTI_CLK"}, {365, 4, "DEV_RTI32_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI32_RTI_CLK"}, {365, 5, "DEV_RTI32_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI32_RTI_CLK"}, {365, 6, "DEV_RTI32_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI32_RTI_CLK"}, {365, 7, "DEV_RTI32_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI32_RTI_CLK"}, {365, 8, "DEV_RTI32_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI32_RTI_CLK"}, {365, 9, "DEV_RTI32_VBUSP_CLK", "Input clock"}, {366, 0, "DEV_RTI33_RTI_CLK", "Input muxed clock"}, {366, 1, "DEV_RTI33_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI33_RTI_CLK"}, {366, 2, "DEV_RTI33_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI33_RTI_CLK"}, {366, 3, "DEV_RTI33_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI33_RTI_CLK"}, {366, 4, "DEV_RTI33_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI33_RTI_CLK"}, {366, 5, "DEV_RTI33_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI33_RTI_CLK"}, {366, 6, "DEV_RTI33_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI33_RTI_CLK"}, {366, 7, "DEV_RTI33_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI33_RTI_CLK"}, {366, 8, "DEV_RTI33_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI33_RTI_CLK"}, {366, 9, "DEV_RTI33_VBUSP_CLK", "Input clock"}, {352, 0, "DEV_RTI4_RTI_CLK", "Input muxed clock"}, {352, 1, "DEV_RTI4_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI4_RTI_CLK"}, {352, 2, "DEV_RTI4_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI4_RTI_CLK"}, {352, 3, "DEV_RTI4_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI4_RTI_CLK"}, {352, 4, "DEV_RTI4_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI4_RTI_CLK"}, {352, 5, "DEV_RTI4_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI4_RTI_CLK"}, {352, 6, "DEV_RTI4_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI4_RTI_CLK"}, {352, 7, "DEV_RTI4_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI4_RTI_CLK"}, {352, 8, "DEV_RTI4_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI4_RTI_CLK"}, {352, 9, "DEV_RTI4_VBUSP_CLK", "Input clock"}, {353, 0, "DEV_RTI5_RTI_CLK", "Input muxed clock"}, {353, 1, "DEV_RTI5_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI5_RTI_CLK"}, {353, 2, "DEV_RTI5_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI5_RTI_CLK"}, {353, 3, "DEV_RTI5_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI5_RTI_CLK"}, {353, 4, "DEV_RTI5_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI5_RTI_CLK"}, {353, 5, "DEV_RTI5_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI5_RTI_CLK"}, {353, 6, "DEV_RTI5_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI5_RTI_CLK"}, {353, 7, "DEV_RTI5_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI5_RTI_CLK"}, {353, 8, "DEV_RTI5_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI5_RTI_CLK"}, {353, 9, "DEV_RTI5_VBUSP_CLK", "Input clock"}, {354, 0, "DEV_RTI6_RTI_CLK", "Input muxed clock"}, {354, 1, "DEV_RTI6_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI6_RTI_CLK"}, {354, 2, "DEV_RTI6_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI6_RTI_CLK"}, {354, 3, "DEV_RTI6_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI6_RTI_CLK"}, {354, 4, "DEV_RTI6_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI6_RTI_CLK"}, {354, 5, "DEV_RTI6_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI6_RTI_CLK"}, {354, 6, "DEV_RTI6_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI6_RTI_CLK"}, {354, 7, "DEV_RTI6_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI6_RTI_CLK"}, {354, 8, "DEV_RTI6_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI6_RTI_CLK"}, {354, 9, "DEV_RTI6_VBUSP_CLK", "Input clock"}, {355, 0, "DEV_RTI7_RTI_CLK", "Input muxed clock"}, {355, 1, "DEV_RTI7_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI7_RTI_CLK"}, {355, 2, "DEV_RTI7_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI7_RTI_CLK"}, {355, 3, "DEV_RTI7_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI7_RTI_CLK"}, {355, 4, "DEV_RTI7_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI7_RTI_CLK"}, {355, 5, "DEV_RTI7_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI7_RTI_CLK"}, {355, 6, "DEV_RTI7_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI7_RTI_CLK"}, {355, 7, "DEV_RTI7_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI7_RTI_CLK"}, {355, 8, "DEV_RTI7_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI7_RTI_CLK"}, {355, 9, "DEV_RTI7_VBUSP_CLK", "Input clock"}, {8, 0, "DEV_SA2_CPSW_PSILSS0_MAIN_2_CLK", "Input clock"}, {8, 1, "DEV_SA2_CPSW_PSILSS0_MAIN_CLK", "Input clock"}, {369, 0, "DEV_SA2_UL0_PKA_IN_CLK", "Input clock"}, {369, 1, "DEV_SA2_UL0_X1_CLK", "Input clock"}, {369, 2, "DEV_SA2_UL0_X2_CLK", "Input clock"}, {404, 2, "DEV_SERDES_10G0_CLK", "Input clock"}, {404, 3, "DEV_SERDES_10G0_CMN_REFCLK_M", "Input clock"}, {404, 3, "DEV_SERDES_10G0_CMN_REFCLK_M", "Output clock"}, {404, 4, "DEV_SERDES_10G0_CMN_REFCLK_P", "Input clock"}, {404, 4, "DEV_SERDES_10G0_CMN_REFCLK_P", "Output clock"}, {404, 5, "DEV_SERDES_10G0_CORE_REF1_CLK", "Input clock"}, {404, 6, "DEV_SERDES_10G0_CORE_REF_CLK", "Input muxed clock"}, {404, 7, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"}, {404, 8, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"}, {404, 9, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"}, {404, 10, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"}, {404, 15, "DEV_SERDES_10G0_IP1_LN0_TXCLK", "Input clock"}, {404, 21, "DEV_SERDES_10G0_IP1_LN1_TXCLK", "Input clock"}, {404, 24, "DEV_SERDES_10G0_IP1_LN2_REFCLK", "Output clock"}, {404, 25, "DEV_SERDES_10G0_IP1_LN2_RXCLK", "Output clock"}, {404, 26, "DEV_SERDES_10G0_IP1_LN2_RXFCLK", "Output clock"}, {404, 27, "DEV_SERDES_10G0_IP1_LN2_TXCLK", "Input clock"}, {404, 28, "DEV_SERDES_10G0_IP1_LN2_TXFCLK", "Output clock"}, {404, 29, "DEV_SERDES_10G0_IP1_LN2_TXMCLK", "Output clock"}, {404, 30, "DEV_SERDES_10G0_IP1_LN3_REFCLK", "Output clock"}, {404, 31, "DEV_SERDES_10G0_IP1_LN3_RXCLK", "Output clock"}, {404, 32, "DEV_SERDES_10G0_IP1_LN3_RXFCLK", "Output clock"}, {404, 33, "DEV_SERDES_10G0_IP1_LN3_TXCLK", "Input clock"}, {404, 34, "DEV_SERDES_10G0_IP1_LN3_TXFCLK", "Output clock"}, {404, 35, "DEV_SERDES_10G0_IP1_LN3_TXMCLK", "Output clock"}, {404, 36, "DEV_SERDES_10G0_IP2_LN0_REFCLK", "Output clock"}, {404, 37, "DEV_SERDES_10G0_IP2_LN0_RXCLK", "Output clock"}, {404, 38, "DEV_SERDES_10G0_IP2_LN0_RXFCLK", "Output clock"}, {404, 39, "DEV_SERDES_10G0_IP2_LN0_TXCLK", "Input clock"}, {404, 40, "DEV_SERDES_10G0_IP2_LN0_TXFCLK", "Output clock"}, {404, 41, "DEV_SERDES_10G0_IP2_LN0_TXMCLK", "Output clock"}, {404, 42, "DEV_SERDES_10G0_IP2_LN1_REFCLK", "Output clock"}, {404, 43, "DEV_SERDES_10G0_IP2_LN1_RXCLK", "Output clock"}, {404, 44, "DEV_SERDES_10G0_IP2_LN1_RXFCLK", "Output clock"}, {404, 45, "DEV_SERDES_10G0_IP2_LN1_TXCLK", "Input clock"}, {404, 46, "DEV_SERDES_10G0_IP2_LN1_TXFCLK", "Output clock"}, {404, 47, "DEV_SERDES_10G0_IP2_LN1_TXMCLK", "Output clock"}, {404, 48, "DEV_SERDES_10G0_IP2_LN2_REFCLK", "Output clock"}, {404, 49, "DEV_SERDES_10G0_IP2_LN2_RXCLK", "Output clock"}, {404, 50, "DEV_SERDES_10G0_IP2_LN2_RXFCLK", "Output clock"}, {404, 51, "DEV_SERDES_10G0_IP2_LN2_TXCLK", "Input clock"}, {404, 52, "DEV_SERDES_10G0_IP2_LN2_TXFCLK", "Output clock"}, {404, 53, "DEV_SERDES_10G0_IP2_LN2_TXMCLK", "Output clock"}, {404, 54, "DEV_SERDES_10G0_IP2_LN3_REFCLK", "Output clock"}, {404, 55, "DEV_SERDES_10G0_IP2_LN3_RXCLK", "Output clock"}, {404, 56, "DEV_SERDES_10G0_IP2_LN3_RXFCLK", "Output clock"}, {404, 57, "DEV_SERDES_10G0_IP2_LN3_TXCLK", "Input clock"}, {404, 58, "DEV_SERDES_10G0_IP2_LN3_TXFCLK", "Output clock"}, {404, 59, "DEV_SERDES_10G0_IP2_LN3_TXMCLK", "Output clock"}, {404, 78, "DEV_SERDES_10G0_IP3_LN3_REFCLK", "Output clock"}, {404, 79, "DEV_SERDES_10G0_IP3_LN3_RXCLK", "Output clock"}, {404, 80, "DEV_SERDES_10G0_IP3_LN3_RXFCLK", "Output clock"}, {404, 81, "DEV_SERDES_10G0_IP3_LN3_TXCLK", "Input clock"}, {404, 82, "DEV_SERDES_10G0_IP3_LN3_TXFCLK", "Output clock"}, {404, 83, "DEV_SERDES_10G0_IP3_LN3_TXMCLK", "Output clock"}, {404, 84, "DEV_SERDES_10G0_IP4_LN0_REFCLK", "Output clock"}, {404, 85, "DEV_SERDES_10G0_IP4_LN0_RXCLK", "Output clock"}, {404, 86, "DEV_SERDES_10G0_IP4_LN0_RXFCLK", "Output clock"}, {404, 87, "DEV_SERDES_10G0_IP4_LN0_TXCLK", "Input clock"}, {404, 88, "DEV_SERDES_10G0_IP4_LN0_TXFCLK", "Output clock"}, {404, 89, "DEV_SERDES_10G0_IP4_LN0_TXMCLK", "Output clock"}, {404, 90, "DEV_SERDES_10G0_IP4_LN1_REFCLK", "Output clock"}, {404, 91, "DEV_SERDES_10G0_IP4_LN1_RXCLK", "Output clock"}, {404, 92, "DEV_SERDES_10G0_IP4_LN1_RXFCLK", "Output clock"}, {404, 93, "DEV_SERDES_10G0_IP4_LN1_TXCLK", "Input clock"}, {404, 94, "DEV_SERDES_10G0_IP4_LN1_TXFCLK", "Output clock"}, {404, 95, "DEV_SERDES_10G0_IP4_LN1_TXMCLK", "Output clock"}, {404, 96, "DEV_SERDES_10G0_IP4_LN2_REFCLK", "Output clock"}, {404, 97, "DEV_SERDES_10G0_IP4_LN2_RXCLK", "Output clock"}, {404, 98, "DEV_SERDES_10G0_IP4_LN2_RXFCLK", "Output clock"}, {404, 99, "DEV_SERDES_10G0_IP4_LN2_TXCLK", "Input clock"}, {404, 100, "DEV_SERDES_10G0_IP4_LN2_TXFCLK", "Output clock"}, {404, 101, "DEV_SERDES_10G0_IP4_LN2_TXMCLK", "Output clock"}, {404, 102, "DEV_SERDES_10G0_IP4_LN3_REFCLK", "Output clock"}, {404, 103, "DEV_SERDES_10G0_IP4_LN3_RXCLK", "Output clock"}, {404, 104, "DEV_SERDES_10G0_IP4_LN3_RXFCLK", "Output clock"}, {404, 105, "DEV_SERDES_10G0_IP4_LN3_TXCLK", "Input clock"}, {404, 106, "DEV_SERDES_10G0_IP4_LN3_TXFCLK", "Output clock"}, {404, 107, "DEV_SERDES_10G0_IP4_LN3_TXMCLK", "Output clock"}, {404, 124, "DEV_SERDES_10G0_REF_DER_OUT_CLK", "Output clock"}, {404, 125, "DEV_SERDES_10G0_REF_OUT_CLK", "Output clock"}, {404, 129, "DEV_SERDES_10G0_TAP_TCK", "Input clock"}, {405, 2, "DEV_SERDES_10G1_CLK", "Input clock"}, {405, 3, "DEV_SERDES_10G1_CMN_REFCLK_M", "Input clock"}, {405, 3, "DEV_SERDES_10G1_CMN_REFCLK_M", "Output clock"}, {405, 4, "DEV_SERDES_10G1_CMN_REFCLK_P", "Input clock"}, {405, 4, "DEV_SERDES_10G1_CMN_REFCLK_P", "Output clock"}, {405, 5, "DEV_SERDES_10G1_CORE_REF1_CLK", "Input clock"}, {405, 6, "DEV_SERDES_10G1_CORE_REF_CLK", "Input muxed clock"}, {405, 7, "DEV_SERDES_10G1_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_10G1_CORE_REF_CLK"}, {405, 8, "DEV_SERDES_10G1_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_10G1_CORE_REF_CLK"}, {405, 9, "DEV_SERDES_10G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_10G1_CORE_REF_CLK"}, {405, 10, "DEV_SERDES_10G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_10G1_CORE_REF_CLK"}, {405, 12, "DEV_SERDES_10G1_IP1_LN0_REFCLK", "Output clock"}, {405, 13, "DEV_SERDES_10G1_IP1_LN0_RXCLK", "Output clock"}, {405, 14, "DEV_SERDES_10G1_IP1_LN0_RXFCLK", "Output clock"}, {405, 15, "DEV_SERDES_10G1_IP1_LN0_TXCLK", "Input clock"}, {405, 16, "DEV_SERDES_10G1_IP1_LN0_TXFCLK", "Output clock"}, {405, 17, "DEV_SERDES_10G1_IP1_LN0_TXMCLK", "Output clock"}, {405, 18, "DEV_SERDES_10G1_IP1_LN1_REFCLK", "Output clock"}, {405, 19, "DEV_SERDES_10G1_IP1_LN1_RXCLK", "Output clock"}, {405, 20, "DEV_SERDES_10G1_IP1_LN1_RXFCLK", "Output clock"}, {405, 21, "DEV_SERDES_10G1_IP1_LN1_TXCLK", "Input clock"}, {405, 22, "DEV_SERDES_10G1_IP1_LN1_TXFCLK", "Output clock"}, {405, 23, "DEV_SERDES_10G1_IP1_LN1_TXMCLK", "Output clock"}, {405, 24, "DEV_SERDES_10G1_IP1_LN2_REFCLK", "Output clock"}, {405, 25, "DEV_SERDES_10G1_IP1_LN2_RXCLK", "Output clock"}, {405, 26, "DEV_SERDES_10G1_IP1_LN2_RXFCLK", "Output clock"}, {405, 27, "DEV_SERDES_10G1_IP1_LN2_TXCLK", "Input clock"}, {405, 28, "DEV_SERDES_10G1_IP1_LN2_TXFCLK", "Output clock"}, {405, 29, "DEV_SERDES_10G1_IP1_LN2_TXMCLK", "Output clock"}, {405, 30, "DEV_SERDES_10G1_IP1_LN3_REFCLK", "Output clock"}, {405, 31, "DEV_SERDES_10G1_IP1_LN3_RXCLK", "Output clock"}, {405, 32, "DEV_SERDES_10G1_IP1_LN3_RXFCLK", "Output clock"}, {405, 33, "DEV_SERDES_10G1_IP1_LN3_TXCLK", "Input clock"}, {405, 34, "DEV_SERDES_10G1_IP1_LN3_TXFCLK", "Output clock"}, {405, 35, "DEV_SERDES_10G1_IP1_LN3_TXMCLK", "Output clock"}, {405, 36, "DEV_SERDES_10G1_IP2_LN0_REFCLK", "Output clock"}, {405, 37, "DEV_SERDES_10G1_IP2_LN0_RXCLK", "Output clock"}, {405, 38, "DEV_SERDES_10G1_IP2_LN0_RXFCLK", "Output clock"}, {405, 39, "DEV_SERDES_10G1_IP2_LN0_TXCLK", "Input clock"}, {405, 40, "DEV_SERDES_10G1_IP2_LN0_TXFCLK", "Output clock"}, {405, 41, "DEV_SERDES_10G1_IP2_LN0_TXMCLK", "Output clock"}, {405, 42, "DEV_SERDES_10G1_IP2_LN1_REFCLK", "Output clock"}, {405, 43, "DEV_SERDES_10G1_IP2_LN1_RXCLK", "Output clock"}, {405, 44, "DEV_SERDES_10G1_IP2_LN1_RXFCLK", "Output clock"}, {405, 45, "DEV_SERDES_10G1_IP2_LN1_TXCLK", "Input clock"}, {405, 46, "DEV_SERDES_10G1_IP2_LN1_TXFCLK", "Output clock"}, {405, 47, "DEV_SERDES_10G1_IP2_LN1_TXMCLK", "Output clock"}, {405, 48, "DEV_SERDES_10G1_IP2_LN2_REFCLK", "Output clock"}, {405, 49, "DEV_SERDES_10G1_IP2_LN2_RXCLK", "Output clock"}, {405, 50, "DEV_SERDES_10G1_IP2_LN2_RXFCLK", "Output clock"}, {405, 51, "DEV_SERDES_10G1_IP2_LN2_TXCLK", "Input clock"}, {405, 52, "DEV_SERDES_10G1_IP2_LN2_TXFCLK", "Output clock"}, {405, 53, "DEV_SERDES_10G1_IP2_LN2_TXMCLK", "Output clock"}, {405, 54, "DEV_SERDES_10G1_IP2_LN3_REFCLK", "Output clock"}, {405, 55, "DEV_SERDES_10G1_IP2_LN3_RXCLK", "Output clock"}, {405, 56, "DEV_SERDES_10G1_IP2_LN3_RXFCLK", "Output clock"}, {405, 57, "DEV_SERDES_10G1_IP2_LN3_TXCLK", "Input clock"}, {405, 58, "DEV_SERDES_10G1_IP2_LN3_TXFCLK", "Output clock"}, {405, 59, "DEV_SERDES_10G1_IP2_LN3_TXMCLK", "Output clock"}, {405, 72, "DEV_SERDES_10G1_IP3_LN2_REFCLK", "Output clock"}, {405, 73, "DEV_SERDES_10G1_IP3_LN2_RXCLK", "Output clock"}, {405, 74, "DEV_SERDES_10G1_IP3_LN2_RXFCLK", "Output clock"}, {405, 75, "DEV_SERDES_10G1_IP3_LN2_TXCLK", "Input clock"}, {405, 76, "DEV_SERDES_10G1_IP3_LN2_TXFCLK", "Output clock"}, {405, 77, "DEV_SERDES_10G1_IP3_LN2_TXMCLK", "Output clock"}, {405, 78, "DEV_SERDES_10G1_IP3_LN3_REFCLK", "Output clock"}, {405, 79, "DEV_SERDES_10G1_IP3_LN3_RXCLK", "Output clock"}, {405, 80, "DEV_SERDES_10G1_IP3_LN3_RXFCLK", "Output clock"}, {405, 81, "DEV_SERDES_10G1_IP3_LN3_TXCLK", "Input clock"}, {405, 82, "DEV_SERDES_10G1_IP3_LN3_TXFCLK", "Output clock"}, {405, 83, "DEV_SERDES_10G1_IP3_LN3_TXMCLK", "Output clock"}, {405, 124, "DEV_SERDES_10G1_REF_DER_OUT_CLK", "Output clock"}, {405, 125, "DEV_SERDES_10G1_REF_OUT_CLK", "Output clock"}, {405, 129, "DEV_SERDES_10G1_TAP_TCK", "Input clock"}, {406, 2, "DEV_SERDES_10G2_CLK", "Input clock"}, {406, 3, "DEV_SERDES_10G2_CMN_REFCLK_M", "Input clock"}, {406, 3, "DEV_SERDES_10G2_CMN_REFCLK_M", "Output clock"}, {406, 4, "DEV_SERDES_10G2_CMN_REFCLK_P", "Input clock"}, {406, 5, "DEV_SERDES_10G2_CORE_REF1_CLK", "Input clock"}, {406, 6, "DEV_SERDES_10G2_CORE_REF_CLK", "Input muxed clock"}, {406, 7, "DEV_SERDES_10G2_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_10G2_CORE_REF_CLK"}, {406, 8, "DEV_SERDES_10G2_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_10G2_CORE_REF_CLK"}, {406, 9, "DEV_SERDES_10G2_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_10G2_CORE_REF_CLK"}, {406, 10, "DEV_SERDES_10G2_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_10G2_CORE_REF_CLK"}, {406, 12, "DEV_SERDES_10G2_IP1_LN0_REFCLK", "Output clock"}, {406, 13, "DEV_SERDES_10G2_IP1_LN0_RXCLK", "Output clock"}, {406, 14, "DEV_SERDES_10G2_IP1_LN0_RXFCLK", "Output clock"}, {406, 15, "DEV_SERDES_10G2_IP1_LN0_TXCLK", "Input clock"}, {406, 16, "DEV_SERDES_10G2_IP1_LN0_TXFCLK", "Output clock"}, {406, 17, "DEV_SERDES_10G2_IP1_LN0_TXMCLK", "Output clock"}, {406, 18, "DEV_SERDES_10G2_IP1_LN1_REFCLK", "Output clock"}, {406, 19, "DEV_SERDES_10G2_IP1_LN1_RXCLK", "Output clock"}, {406, 20, "DEV_SERDES_10G2_IP1_LN1_RXFCLK", "Output clock"}, {406, 21, "DEV_SERDES_10G2_IP1_LN1_TXCLK", "Input clock"}, {406, 22, "DEV_SERDES_10G2_IP1_LN1_TXFCLK", "Output clock"}, {406, 23, "DEV_SERDES_10G2_IP1_LN1_TXMCLK", "Output clock"}, {406, 24, "DEV_SERDES_10G2_IP1_LN2_REFCLK", "Output clock"}, {406, 25, "DEV_SERDES_10G2_IP1_LN2_RXCLK", "Output clock"}, {406, 26, "DEV_SERDES_10G2_IP1_LN2_RXFCLK", "Output clock"}, {406, 27, "DEV_SERDES_10G2_IP1_LN2_TXCLK", "Input clock"}, {406, 28, "DEV_SERDES_10G2_IP1_LN2_TXFCLK", "Output clock"}, {406, 29, "DEV_SERDES_10G2_IP1_LN2_TXMCLK", "Output clock"}, {406, 30, "DEV_SERDES_10G2_IP1_LN3_REFCLK", "Output clock"}, {406, 31, "DEV_SERDES_10G2_IP1_LN3_RXCLK", "Output clock"}, {406, 32, "DEV_SERDES_10G2_IP1_LN3_RXFCLK", "Output clock"}, {406, 33, "DEV_SERDES_10G2_IP1_LN3_TXCLK", "Input clock"}, {406, 34, "DEV_SERDES_10G2_IP1_LN3_TXFCLK", "Output clock"}, {406, 35, "DEV_SERDES_10G2_IP1_LN3_TXMCLK", "Output clock"}, {406, 48, "DEV_SERDES_10G2_IP2_LN2_REFCLK", "Output clock"}, {406, 49, "DEV_SERDES_10G2_IP2_LN2_RXCLK", "Output clock"}, {406, 50, "DEV_SERDES_10G2_IP2_LN2_RXFCLK", "Output clock"}, {406, 51, "DEV_SERDES_10G2_IP2_LN2_TXCLK", "Input clock"}, {406, 52, "DEV_SERDES_10G2_IP2_LN2_TXFCLK", "Output clock"}, {406, 53, "DEV_SERDES_10G2_IP2_LN2_TXMCLK", "Output clock"}, {406, 54, "DEV_SERDES_10G2_IP2_LN3_REFCLK", "Output clock"}, {406, 55, "DEV_SERDES_10G2_IP2_LN3_RXCLK", "Output clock"}, {406, 56, "DEV_SERDES_10G2_IP2_LN3_RXFCLK", "Output clock"}, {406, 57, "DEV_SERDES_10G2_IP2_LN3_TXCLK", "Input clock"}, {406, 58, "DEV_SERDES_10G2_IP2_LN3_TXFCLK", "Output clock"}, {406, 59, "DEV_SERDES_10G2_IP2_LN3_TXMCLK", "Output clock"}, {406, 129, "DEV_SERDES_10G2_TAP_TCK", "Input clock"}, {407, 2, "DEV_SERDES_10G4_CLK", "Input clock"}, {407, 3, "DEV_SERDES_10G4_CMN_REFCLK_M", "Input clock"}, {407, 3, "DEV_SERDES_10G4_CMN_REFCLK_M", "Output clock"}, {407, 4, "DEV_SERDES_10G4_CMN_REFCLK_P", "Input clock"}, {407, 4, "DEV_SERDES_10G4_CMN_REFCLK_P", "Output clock"}, {407, 5, "DEV_SERDES_10G4_CORE_REF1_CLK", "Input clock"}, {407, 6, "DEV_SERDES_10G4_CORE_REF_CLK", "Input muxed clock"}, {407, 7, "DEV_SERDES_10G4_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_10G4_CORE_REF_CLK"}, {407, 8, "DEV_SERDES_10G4_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_10G4_CORE_REF_CLK"}, {407, 9, "DEV_SERDES_10G4_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_10G4_CORE_REF_CLK"}, {407, 10, "DEV_SERDES_10G4_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_10G4_CORE_REF_CLK"}, {407, 12, "DEV_SERDES_10G4_IP1_LN0_REFCLK", "Output clock"}, {407, 13, "DEV_SERDES_10G4_IP1_LN0_RXCLK", "Output clock"}, {407, 14, "DEV_SERDES_10G4_IP1_LN0_RXFCLK", "Output clock"}, {407, 15, "DEV_SERDES_10G4_IP1_LN0_TXCLK", "Input clock"}, {407, 16, "DEV_SERDES_10G4_IP1_LN0_TXFCLK", "Output clock"}, {407, 17, "DEV_SERDES_10G4_IP1_LN0_TXMCLK", "Output clock"}, {407, 18, "DEV_SERDES_10G4_IP1_LN1_REFCLK", "Output clock"}, {407, 19, "DEV_SERDES_10G4_IP1_LN1_RXCLK", "Output clock"}, {407, 20, "DEV_SERDES_10G4_IP1_LN1_RXFCLK", "Output clock"}, {407, 21, "DEV_SERDES_10G4_IP1_LN1_TXCLK", "Input clock"}, {407, 22, "DEV_SERDES_10G4_IP1_LN1_TXFCLK", "Output clock"}, {407, 23, "DEV_SERDES_10G4_IP1_LN1_TXMCLK", "Output clock"}, {407, 24, "DEV_SERDES_10G4_IP1_LN2_REFCLK", "Output clock"}, {407, 25, "DEV_SERDES_10G4_IP1_LN2_RXCLK", "Output clock"}, {407, 26, "DEV_SERDES_10G4_IP1_LN2_RXFCLK", "Output clock"}, {407, 27, "DEV_SERDES_10G4_IP1_LN2_TXCLK", "Input clock"}, {407, 28, "DEV_SERDES_10G4_IP1_LN2_TXFCLK", "Output clock"}, {407, 29, "DEV_SERDES_10G4_IP1_LN2_TXMCLK", "Output clock"}, {407, 30, "DEV_SERDES_10G4_IP1_LN3_REFCLK", "Output clock"}, {407, 31, "DEV_SERDES_10G4_IP1_LN3_RXCLK", "Output clock"}, {407, 32, "DEV_SERDES_10G4_IP1_LN3_RXFCLK", "Output clock"}, {407, 33, "DEV_SERDES_10G4_IP1_LN3_TXCLK", "Input clock"}, {407, 34, "DEV_SERDES_10G4_IP1_LN3_TXFCLK", "Output clock"}, {407, 35, "DEV_SERDES_10G4_IP1_LN3_TXMCLK", "Output clock"}, {407, 36, "DEV_SERDES_10G4_IP2_LN0_REFCLK", "Output clock"}, {407, 37, "DEV_SERDES_10G4_IP2_LN0_RXCLK", "Output clock"}, {407, 38, "DEV_SERDES_10G4_IP2_LN0_RXFCLK", "Output clock"}, {407, 39, "DEV_SERDES_10G4_IP2_LN0_TXCLK", "Input clock"}, {407, 40, "DEV_SERDES_10G4_IP2_LN0_TXFCLK", "Output clock"}, {407, 41, "DEV_SERDES_10G4_IP2_LN0_TXMCLK", "Output clock"}, {407, 42, "DEV_SERDES_10G4_IP2_LN1_REFCLK", "Output clock"}, {407, 43, "DEV_SERDES_10G4_IP2_LN1_RXCLK", "Output clock"}, {407, 44, "DEV_SERDES_10G4_IP2_LN1_RXFCLK", "Output clock"}, {407, 45, "DEV_SERDES_10G4_IP2_LN1_TXCLK", "Input clock"}, {407, 46, "DEV_SERDES_10G4_IP2_LN1_TXFCLK", "Output clock"}, {407, 47, "DEV_SERDES_10G4_IP2_LN1_TXMCLK", "Output clock"}, {407, 48, "DEV_SERDES_10G4_IP2_LN2_REFCLK", "Output clock"}, {407, 49, "DEV_SERDES_10G4_IP2_LN2_RXCLK", "Output clock"}, {407, 50, "DEV_SERDES_10G4_IP2_LN2_RXFCLK", "Output clock"}, {407, 51, "DEV_SERDES_10G4_IP2_LN2_TXCLK", "Input clock"}, {407, 52, "DEV_SERDES_10G4_IP2_LN2_TXFCLK", "Output clock"}, {407, 53, "DEV_SERDES_10G4_IP2_LN2_TXMCLK", "Output clock"}, {407, 54, "DEV_SERDES_10G4_IP2_LN3_REFCLK", "Output clock"}, {407, 55, "DEV_SERDES_10G4_IP2_LN3_RXCLK", "Output clock"}, {407, 56, "DEV_SERDES_10G4_IP2_LN3_RXFCLK", "Output clock"}, {407, 57, "DEV_SERDES_10G4_IP2_LN3_TXCLK", "Input clock"}, {407, 58, "DEV_SERDES_10G4_IP2_LN3_TXFCLK", "Output clock"}, {407, 59, "DEV_SERDES_10G4_IP2_LN3_TXMCLK", "Output clock"}, {407, 78, "DEV_SERDES_10G4_IP3_LN3_REFCLK", "Output clock"}, {407, 79, "DEV_SERDES_10G4_IP3_LN3_RXCLK", "Output clock"}, {407, 80, "DEV_SERDES_10G4_IP3_LN3_RXFCLK", "Output clock"}, {407, 81, "DEV_SERDES_10G4_IP3_LN3_TXCLK", "Input clock"}, {407, 82, "DEV_SERDES_10G4_IP3_LN3_TXFCLK", "Output clock"}, {407, 83, "DEV_SERDES_10G4_IP3_LN3_TXMCLK", "Output clock"}, {407, 84, "DEV_SERDES_10G4_IP4_LN0_REFCLK", "Output clock"}, {407, 85, "DEV_SERDES_10G4_IP4_LN0_RXCLK", "Output clock"}, {407, 86, "DEV_SERDES_10G4_IP4_LN0_RXFCLK", "Output clock"}, {407, 87, "DEV_SERDES_10G4_IP4_LN0_TXCLK", "Input clock"}, {407, 88, "DEV_SERDES_10G4_IP4_LN0_TXFCLK", "Output clock"}, {407, 89, "DEV_SERDES_10G4_IP4_LN0_TXMCLK", "Output clock"}, {407, 90, "DEV_SERDES_10G4_IP4_LN1_REFCLK", "Output clock"}, {407, 91, "DEV_SERDES_10G4_IP4_LN1_RXCLK", "Output clock"}, {407, 92, "DEV_SERDES_10G4_IP4_LN1_RXFCLK", "Output clock"}, {407, 93, "DEV_SERDES_10G4_IP4_LN1_TXCLK", "Input clock"}, {407, 94, "DEV_SERDES_10G4_IP4_LN1_TXFCLK", "Output clock"}, {407, 95, "DEV_SERDES_10G4_IP4_LN1_TXMCLK", "Output clock"}, {407, 96, "DEV_SERDES_10G4_IP4_LN2_REFCLK", "Output clock"}, {407, 97, "DEV_SERDES_10G4_IP4_LN2_RXCLK", "Output clock"}, {407, 98, "DEV_SERDES_10G4_IP4_LN2_RXFCLK", "Output clock"}, {407, 99, "DEV_SERDES_10G4_IP4_LN2_TXCLK", "Input clock"}, {407, 100, "DEV_SERDES_10G4_IP4_LN2_TXFCLK", "Output clock"}, {407, 101, "DEV_SERDES_10G4_IP4_LN2_TXMCLK", "Output clock"}, {407, 102, "DEV_SERDES_10G4_IP4_LN3_REFCLK", "Output clock"}, {407, 103, "DEV_SERDES_10G4_IP4_LN3_RXCLK", "Output clock"}, {407, 104, "DEV_SERDES_10G4_IP4_LN3_RXFCLK", "Output clock"}, {407, 105, "DEV_SERDES_10G4_IP4_LN3_TXCLK", "Input clock"}, {407, 106, "DEV_SERDES_10G4_IP4_LN3_TXFCLK", "Output clock"}, {407, 107, "DEV_SERDES_10G4_IP4_LN3_TXMCLK", "Output clock"}, {77, 0, "DEV_STM0_ATB_CLK", "Input clock"}, {77, 1, "DEV_STM0_CORE_CLK", "Input clock"}, {77, 2, "DEV_STM0_VBUSP_CLK", "Input clock"}, {97, 0, "DEV_TIMER0_TIMER_HCLK_CLK", "Input clock"}, {97, 1, "DEV_TIMER0_TIMER_PWM", "Output clock"}, {97, 2, "DEV_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"}, {97, 3, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {97, 4, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {97, 5, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {97, 6, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {97, 7, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {97, 8, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {97, 9, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {97, 10, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {97, 11, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {97, 12, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {97, 13, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {97, 14, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {97, 15, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {97, 16, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {97, 17, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {97, 18, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {98, 0, "DEV_TIMER1_TIMER_HCLK_CLK", "Input clock"}, {98, 2, "DEV_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"}, {98, 3, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT1", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {98, 4, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {107, 0, "DEV_TIMER10_TIMER_HCLK_CLK", "Input clock"}, {107, 1, "DEV_TIMER10_TIMER_PWM", "Output clock"}, {107, 2, "DEV_TIMER10_TIMER_TCLK_CLK", "Input muxed clock"}, {107, 3, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {107, 4, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {107, 5, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {107, 6, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {107, 7, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {107, 8, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {107, 9, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {107, 10, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {107, 11, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {107, 12, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {107, 13, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {107, 14, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {107, 15, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {107, 16, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {107, 17, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {107, 18, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"}, {108, 0, "DEV_TIMER11_TIMER_HCLK_CLK", "Input clock"}, {108, 2, "DEV_TIMER11_TIMER_TCLK_CLK", "Input muxed clock"}, {108, 3, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT11", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, {108, 4, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_10_TIMER_PWM", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"}, {109, 0, "DEV_TIMER12_TIMER_HCLK_CLK", "Input clock"}, {109, 1, "DEV_TIMER12_TIMER_PWM", "Output clock"}, {109, 2, "DEV_TIMER12_TIMER_TCLK_CLK", "Input muxed clock"}, {109, 3, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {109, 4, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {109, 5, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {109, 6, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {109, 7, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {109, 8, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {109, 9, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {109, 10, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {109, 11, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {109, 12, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {109, 13, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {109, 14, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {109, 15, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {109, 16, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {109, 17, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {109, 18, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"}, {110, 0, "DEV_TIMER13_TIMER_HCLK_CLK", "Input clock"}, {110, 2, "DEV_TIMER13_TIMER_TCLK_CLK", "Input muxed clock"}, {110, 3, "DEV_TIMER13_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT13", "Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK"}, {110, 4, "DEV_TIMER13_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_12_TIMER_PWM", "Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK"}, {111, 0, "DEV_TIMER14_TIMER_HCLK_CLK", "Input clock"}, {111, 1, "DEV_TIMER14_TIMER_PWM", "Output clock"}, {111, 2, "DEV_TIMER14_TIMER_TCLK_CLK", "Input muxed clock"}, {111, 3, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {111, 4, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {111, 5, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {111, 6, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {111, 7, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {111, 8, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {111, 9, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {111, 10, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {111, 11, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {111, 12, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {111, 13, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {111, 14, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {111, 15, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {111, 16, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {111, 17, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {111, 18, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"}, {112, 0, "DEV_TIMER15_TIMER_HCLK_CLK", "Input clock"}, {112, 2, "DEV_TIMER15_TIMER_TCLK_CLK", "Input muxed clock"}, {112, 3, "DEV_TIMER15_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT15", "Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK"}, {112, 4, "DEV_TIMER15_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_14_TIMER_PWM", "Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK"}, {113, 0, "DEV_TIMER16_TIMER_HCLK_CLK", "Input clock"}, {113, 1, "DEV_TIMER16_TIMER_PWM", "Output clock"}, {113, 2, "DEV_TIMER16_TIMER_TCLK_CLK", "Input muxed clock"}, {113, 3, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT16", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {113, 4, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_MAIN_TIMER16_AFS_SEL_OUT0", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"}, {114, 0, "DEV_TIMER17_TIMER_HCLK_CLK", "Input clock"}, {114, 2, "DEV_TIMER17_TIMER_TCLK_CLK", "Input muxed clock"}, {114, 3, "DEV_TIMER17_TIMER_TCLK_CLK_PARENT_MAIN_TIMER17_AFS_EN_OUT0", "Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK"}, {114, 4, "DEV_TIMER17_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_16_TIMER_PWM", "Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK"}, {115, 0, "DEV_TIMER18_TIMER_HCLK_CLK", "Input clock"}, {115, 1, "DEV_TIMER18_TIMER_PWM", "Output clock"}, {115, 2, "DEV_TIMER18_TIMER_TCLK_CLK", "Input muxed clock"}, {115, 3, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT18", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {115, 4, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_MAIN_TIMER18_AFS_SEL_OUT0", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"}, {116, 0, "DEV_TIMER19_TIMER_HCLK_CLK", "Input clock"}, {116, 2, "DEV_TIMER19_TIMER_TCLK_CLK", "Input muxed clock"}, {116, 3, "DEV_TIMER19_TIMER_TCLK_CLK_PARENT_MAIN_TIMER19_AFS_EN_OUT0", "Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK"}, {116, 4, "DEV_TIMER19_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_18_TIMER_PWM", "Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK"}, {99, 0, "DEV_TIMER2_TIMER_HCLK_CLK", "Input clock"}, {99, 1, "DEV_TIMER2_TIMER_PWM", "Output clock"}, {99, 2, "DEV_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"}, {99, 3, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {99, 4, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {99, 5, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {99, 6, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {99, 7, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {99, 8, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {99, 9, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {99, 10, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {99, 11, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {99, 12, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {99, 13, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {99, 14, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {99, 15, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {99, 16, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {99, 17, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {99, 18, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {100, 0, "DEV_TIMER3_TIMER_HCLK_CLK", "Input clock"}, {100, 2, "DEV_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"}, {100, 3, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT3", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {100, 4, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {101, 0, "DEV_TIMER4_TIMER_HCLK_CLK", "Input clock"}, {101, 1, "DEV_TIMER4_TIMER_PWM", "Output clock"}, {101, 2, "DEV_TIMER4_TIMER_TCLK_CLK", "Input muxed clock"}, {101, 3, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {101, 4, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {101, 5, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {101, 6, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {101, 7, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {101, 8, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {101, 9, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {101, 10, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {101, 11, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {101, 12, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {101, 13, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {101, 14, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {101, 15, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {101, 16, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {101, 17, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {101, 18, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {102, 0, "DEV_TIMER5_TIMER_HCLK_CLK", "Input clock"}, {102, 2, "DEV_TIMER5_TIMER_TCLK_CLK", "Input muxed clock"}, {102, 3, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT5", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {102, 4, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {103, 0, "DEV_TIMER6_TIMER_HCLK_CLK", "Input clock"}, {103, 1, "DEV_TIMER6_TIMER_PWM", "Output clock"}, {103, 2, "DEV_TIMER6_TIMER_TCLK_CLK", "Input muxed clock"}, {103, 3, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {103, 4, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {103, 5, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {103, 6, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {103, 7, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {103, 8, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {103, 9, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {103, 10, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {103, 11, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {103, 12, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {103, 13, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {103, 14, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {103, 15, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {103, 16, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {103, 17, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {103, 18, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {104, 0, "DEV_TIMER7_TIMER_HCLK_CLK", "Input clock"}, {104, 2, "DEV_TIMER7_TIMER_TCLK_CLK", "Input muxed clock"}, {104, 3, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT7", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {104, 4, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {105, 0, "DEV_TIMER8_TIMER_HCLK_CLK", "Input clock"}, {105, 1, "DEV_TIMER8_TIMER_PWM", "Output clock"}, {105, 2, "DEV_TIMER8_TIMER_TCLK_CLK", "Input muxed clock"}, {105, 3, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {105, 4, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {105, 5, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {105, 6, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {105, 7, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {105, 8, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {105, 9, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {105, 10, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {105, 11, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {105, 12, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {105, 13, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {105, 14, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {105, 15, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {105, 16, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {105, 17, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {105, 18, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"}, {106, 0, "DEV_TIMER9_TIMER_HCLK_CLK", "Input clock"}, {106, 2, "DEV_TIMER9_TIMER_TCLK_CLK", "Input muxed clock"}, {106, 3, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT9", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, {106, 4, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_8_TIMER_PWM", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"}, {176, 0, "DEV_TIMESYNC_INTRTR0_INTR_CLK", "Input clock"}, {146, 0, "DEV_UART0_FCLK_CLK", "Input clock"}, {146, 3, "DEV_UART0_VBUSP_CLK", "Input clock"}, {388, 0, "DEV_UART1_FCLK_CLK", "Input clock"}, {388, 3, "DEV_UART1_VBUSP_CLK", "Input clock"}, {389, 0, "DEV_UART2_FCLK_CLK", "Input clock"}, {389, 3, "DEV_UART2_VBUSP_CLK", "Input clock"}, {390, 0, "DEV_UART3_FCLK_CLK", "Input clock"}, {390, 3, "DEV_UART3_VBUSP_CLK", "Input clock"}, {391, 0, "DEV_UART4_FCLK_CLK", "Input clock"}, {391, 3, "DEV_UART4_VBUSP_CLK", "Input clock"}, {392, 0, "DEV_UART5_FCLK_CLK", "Input clock"}, {392, 3, "DEV_UART5_VBUSP_CLK", "Input clock"}, {393, 0, "DEV_UART6_FCLK_CLK", "Input clock"}, {393, 3, "DEV_UART6_VBUSP_CLK", "Input clock"}, {394, 0, "DEV_UART7_FCLK_CLK", "Input clock"}, {394, 3, "DEV_UART7_VBUSP_CLK", "Input clock"}, {395, 0, "DEV_UART8_FCLK_CLK", "Input clock"}, {395, 3, "DEV_UART8_VBUSP_CLK", "Input clock"}, {396, 0, "DEV_UART9_FCLK_CLK", "Input clock"}, {396, 3, "DEV_UART9_VBUSP_CLK", "Input clock"}, {387, 1, "DEV_UFS0_UFSHCI_HCLK_CLK", "Input clock"}, {387, 3, "DEV_UFS0_UFSHCI_MCLK_CLK", "Input muxed clock"}, {387, 4, "DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK"}, {387, 5, "DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK"}, {387, 6, "DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT6_CLK", "Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK"}, {387, 7, "DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK"}, {387, 8, "DEV_UFS0_UFSHCI_MPHY_REFCLK", "Output clock"}, {387, 23, "DEV_UFS0_UFSHCI_MPHY_TX_REF_SYMBOLCLK", "Output clock"}, {387, 24, "DEV_UFS0_UFSHCI_MPHY_M31_VCO_19P2M_CLK", "Output clock"}, {387, 25, "DEV_UFS0_UFSHCI_MPHY_M31_VCO_26M_CLK", "Output clock"}, {398, 0, "DEV_USB0_ACLK_CLK", "Input clock"}, {398, 1, "DEV_USB0_BUF_CLK", "Input clock"}, {398, 2, "DEV_USB0_CLK_LPM_CLK", "Input clock"}, {398, 3, "DEV_USB0_PCLK_CLK", "Input clock"}, {398, 4, "DEV_USB0_PIPE_REFCLK", "Input muxed clock"}, {398, 5, "DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP3_LN3_REFCLK", "Parent input clock option to DEV_USB0_PIPE_REFCLK"}, {398, 6, "DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B8M4CT3_MAIN_4_IP3_LN3_REFCLK", "Parent input clock option to DEV_USB0_PIPE_REFCLK"}, {398, 7, "DEV_USB0_PIPE_RXCLK", "Input muxed clock"}, {398, 8, "DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP3_LN3_RXCLK", "Parent input clock option to DEV_USB0_PIPE_RXCLK"}, {398, 9, "DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B8M4CT3_MAIN_4_IP3_LN3_RXCLK", "Parent input clock option to DEV_USB0_PIPE_RXCLK"}, {398, 10, "DEV_USB0_PIPE_RXFCLK", "Input muxed clock"}, {398, 11, "DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP3_LN3_RXFCLK", "Parent input clock option to DEV_USB0_PIPE_RXFCLK"}, {398, 12, "DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B8M4CT3_MAIN_4_IP3_LN3_RXFCLK", "Parent input clock option to DEV_USB0_PIPE_RXFCLK"}, {398, 13, "DEV_USB0_PIPE_TXCLK", "Output clock"}, {398, 14, "DEV_USB0_PIPE_TXFCLK", "Input muxed clock"}, {398, 15, "DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP3_LN3_TXFCLK", "Parent input clock option to DEV_USB0_PIPE_TXFCLK"}, {398, 16, "DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B8M4CT3_MAIN_4_IP3_LN3_TXFCLK", "Parent input clock option to DEV_USB0_PIPE_TXFCLK"}, {398, 17, "DEV_USB0_PIPE_TXMCLK", "Input muxed clock"}, {398, 18, "DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP3_LN3_TXMCLK", "Parent input clock option to DEV_USB0_PIPE_TXMCLK"}, {398, 19, "DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B8M4CT3_MAIN_4_IP3_LN3_TXMCLK", "Parent input clock option to DEV_USB0_PIPE_TXMCLK"}, {398, 20, "DEV_USB0_USB2_APB_PCLK_CLK", "Input clock"}, {398, 21, "DEV_USB0_USB2_REFCLOCK_CLK", "Input muxed clock"}, {398, 22, "DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK"}, {398, 23, "DEV_USB0_USB2_REFCLOCK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK"}, {398, 28, "DEV_USB0_USB2_TAP_TCK", "Input clock"}, {399, 0, "DEV_VPAC0_LDC0_CLK_CLK", "Input clock"}, {399, 1, "DEV_VPAC0_MAIN_CLK", "Input muxed clock"}, {399, 2, "DEV_VPAC0_MAIN_CLK_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT1_CLK", "Parent input clock option to DEV_VPAC0_MAIN_CLK"}, {399, 3, "DEV_VPAC0_MAIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_VPAC0_MAIN_CLK"}, {399, 4, "DEV_VPAC0_MSC_CLK", "Input clock"}, {399, 5, "DEV_VPAC0_NF_CLK_CLK", "Input clock"}, {399, 6, "DEV_VPAC0_PSIL_LEAF_CLK", "Input clock"}, {399, 7, "DEV_VPAC0_VISS0_CLK_CLK", "Input clock"}, {400, 0, "DEV_VPAC1_LDC0_CLK_CLK", "Input clock"}, {400, 1, "DEV_VPAC1_MAIN_CLK", "Input muxed clock"}, {400, 2, "DEV_VPAC1_MAIN_CLK_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT1_CLK", "Parent input clock option to DEV_VPAC1_MAIN_CLK"}, {400, 3, "DEV_VPAC1_MAIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_VPAC1_MAIN_CLK"}, {400, 4, "DEV_VPAC1_MSC_CLK", "Input clock"}, {400, 5, "DEV_VPAC1_NF_CLK_CLK", "Input clock"}, {400, 6, "DEV_VPAC1_PSIL_LEAF_CLK", "Input clock"}, {400, 7, "DEV_VPAC1_VISS0_CLK_CLK", "Input clock"}, {401, 0, "DEV_VUSR_DUAL0_V0_CLK", "Input clock"}, {401, 1, "DEV_VUSR_DUAL0_V0_RXFL_CLK", "Output clock"}, {401, 2, "DEV_VUSR_DUAL0_V0_RXPM_CLK", "Input clock"}, {401, 3, "DEV_VUSR_DUAL0_V0_TXFL_CLK", "Input clock"}, {401, 4, "DEV_VUSR_DUAL0_V0_TXPM_CLK", "Output clock"}, {401, 5, "DEV_VUSR_DUAL0_V1_CLK", "Input clock"}, {401, 6, "DEV_VUSR_DUAL0_V1_RXFL_CLK", "Output clock"}, {401, 7, "DEV_VUSR_DUAL0_V1_RXPM_CLK", "Input clock"}, {401, 8, "DEV_VUSR_DUAL0_V1_TXFL_CLK", "Input clock"}, {401, 9, "DEV_VUSR_DUAL0_V1_TXPM_CLK", "Output clock"}, {401, 10, "DEV_VUSR_DUAL0_VUSRX_LN0_REFCLK", "Input clock"}, {401, 11, "DEV_VUSR_DUAL0_VUSRX_LN0_RXCLK", "Input clock"}, {401, 12, "DEV_VUSR_DUAL0_VUSRX_LN0_RXFCLK", "Input clock"}, {401, 13, "DEV_VUSR_DUAL0_VUSRX_LN0_TXCLK", "Output clock"}, {401, 14, "DEV_VUSR_DUAL0_VUSRX_LN0_TXFCLK", "Input clock"}, {401, 15, "DEV_VUSR_DUAL0_VUSRX_LN0_TXMCLK", "Input clock"}, {401, 16, "DEV_VUSR_DUAL0_VUSRX_LN1_REFCLK", "Input clock"}, {401, 17, "DEV_VUSR_DUAL0_VUSRX_LN1_RXCLK", "Input clock"}, {401, 18, "DEV_VUSR_DUAL0_VUSRX_LN1_RXFCLK", "Input clock"}, {401, 19, "DEV_VUSR_DUAL0_VUSRX_LN1_TXCLK", "Output clock"}, {401, 20, "DEV_VUSR_DUAL0_VUSRX_LN1_TXFCLK", "Input clock"}, {401, 21, "DEV_VUSR_DUAL0_VUSRX_LN1_TXMCLK", "Input clock"}, {401, 22, "DEV_VUSR_DUAL0_VUSRX_LN2_REFCLK", "Input clock"}, {401, 23, "DEV_VUSR_DUAL0_VUSRX_LN2_RXCLK", "Input clock"}, {401, 24, "DEV_VUSR_DUAL0_VUSRX_LN2_RXFCLK", "Input clock"}, {401, 25, "DEV_VUSR_DUAL0_VUSRX_LN2_TXCLK", "Output clock"}, {401, 26, "DEV_VUSR_DUAL0_VUSRX_LN2_TXFCLK", "Input clock"}, {401, 27, "DEV_VUSR_DUAL0_VUSRX_LN2_TXMCLK", "Input clock"}, {401, 28, "DEV_VUSR_DUAL0_VUSRX_LN3_REFCLK", "Input clock"}, {401, 29, "DEV_VUSR_DUAL0_VUSRX_LN3_RXCLK", "Input clock"}, {401, 30, "DEV_VUSR_DUAL0_VUSRX_LN3_RXFCLK", "Input clock"}, {401, 31, "DEV_VUSR_DUAL0_VUSRX_LN3_TXCLK", "Output clock"}, {401, 32, "DEV_VUSR_DUAL0_VUSRX_LN3_TXFCLK", "Input clock"}, {401, 33, "DEV_VUSR_DUAL0_VUSRX_LN3_TXMCLK", "Input clock"}, {211, 0, "DEV_WKUP_DDPA0_DDPA_CLK", "Input clock"}, {147, 0, "DEV_WKUP_ESM0_CLK", "Input clock"}, {167, 0, "DEV_WKUP_GPIO0_MMR_CLK", "Input clock"}, {168, 0, "DEV_WKUP_GPIO1_MMR_CLK", "Input clock"}, {177, 0, "DEV_WKUP_GPIOMUX_INTRTR0_INTR_CLK", "Input clock"}, {371, 0, "DEV_WKUP_HSM0_DAP_CLK", "Input clock"}, {279, 0, "DEV_WKUP_I2C0_CLK", "Input clock"}, {279, 1, "DEV_WKUP_I2C0_PISCL", "Input clock"}, {279, 2, "DEV_WKUP_I2C0_PISYS_CLK", "Input muxed clock"}, {279, 3, "DEV_WKUP_I2C0_PISYS_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_WKUP_I2C0_PISYS_CLK"}, {279, 4, "DEV_WKUP_I2C0_PISYS_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_WKUP_I2C0_PISYS_CLK"}, {279, 5, "DEV_WKUP_I2C0_PORSCL", "Output clock"}, {9, 0, "DEV_WKUP_J7AM_WAKEUP_16FF0_PLL_CTRL_WKUP_CLK24_CLK", "Input clock"}, {9, 1, "DEV_WKUP_J7AM_WAKEUP_16FF0_WKUP_RCOSC_12P5M_CLK", "Output clock"}, {9, 2, "DEV_WKUP_J7AM_WAKEUP_16FF0_WKUP_RCOSC_32K_CLK", "Output clock"}, {175, 0, "DEV_WKUP_PORZ_SYNC0_CLK_12M_RC_CLK", "Input clock"}, {178, 0, "DEV_WKUP_PSC0_CLK", "Input clock"}, {178, 1, "DEV_WKUP_PSC0_SLOW_CLK", "Input clock"}, {397, 0, "DEV_WKUP_UART0_FCLK_CLK", "Input muxed clock"}, {397, 1, "DEV_WKUP_UART0_FCLK_CLK_PARENT_WKUP_USART_CLKSEL_OUT0", "Parent input clock option to DEV_WKUP_UART0_FCLK_CLK"}, {397, 2, "DEV_WKUP_UART0_FCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_WKUP_UART0_FCLK_CLK"}, {397, 7, "DEV_WKUP_UART0_VBUSP_CLK", "Input clock"}, {243, 0, "DEV_WKUP_VTM0_FIX_REF2_CLK", "Input clock"}, {243, 1, "DEV_WKUP_VTM0_FIX_REF_CLK", "Input clock"}, {243, 2, "DEV_WKUP_VTM0_VBUSP_CLK", "Input clock"}, }; k3conf_0.3/soc/j784s4/j784s4_sec_proxy_info.c0000664000175000017500000003022214375734376015531 0ustar /* * J784S4 Sec Proxy Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_sec_proxy_info j784s4_main_sp_info[] = { {342, "read", 31, "DM", "nonsec_high_priority_rx"}, {341, "read", 103, "DM", "nonsec_low_priority_rx"}, {340, "read", 31, "DM", "nonsec_notify_resp_rx"}, {339, "write", 2, "DM", "nonsec_A72_2_notify_tx"}, {338, "write", 22, "DM", "nonsec_A72_2_response_tx"}, {337, "write", 2, "DM", "nonsec_A72_3_notify_tx"}, {336, "write", 7, "DM", "nonsec_A72_3_response_tx"}, {335, "write", 2, "DM", "nonsec_A72_4_notify_tx"}, {334, "write", 7, "DM", "nonsec_A72_4_response_tx"}, {333, "write", 2, "DM", "nonsec_A72_5_notify_tx"}, {332, "write", 22, "DM", "nonsec_A72_5_response_tx"}, {331, "write", 2, "DM", "nonsec_A72_6_notify_tx"}, {330, "write", 7, "DM", "nonsec_A72_6_response_tx"}, {329, "write", 2, "DM", "nonsec_A72_7_notify_tx"}, {328, "write", 7, "DM", "nonsec_A72_7_response_tx"}, {327, "write", 2, "DM", "nonsec_C7X_0_1_notify_tx"}, {326, "write", 7, "DM", "nonsec_C7X_0_1_response_tx"}, {325, "write", 2, "DM", "nonsec_C7X_1_1_notify_tx"}, {324, "write", 7, "DM", "nonsec_C7X_1_1_response_tx"}, {323, "write", 2, "DM", "nonsec_C7X_2_1_notify_tx"}, {322, "write", 7, "DM", "nonsec_C7X_2_1_response_tx"}, {321, "write", 2, "DM", "nonsec_C7X_3_1_notify_tx"}, {320, "write", 7, "DM", "nonsec_C7X_3_1_response_tx"}, {319, "write", 2, "DM", "nonsec_GPU_0_notify_tx"}, {318, "write", 7, "DM", "nonsec_GPU_0_response_tx"}, {317, "write", 2, "DM", "nonsec_MAIN_0_R5_0_notify_tx"}, {316, "write", 7, "DM", "nonsec_MAIN_0_R5_0_response_tx"}, {315, "write", 1, "DM", "nonsec_MAIN_0_R5_2_notify_tx"}, {314, "write", 2, "DM", "nonsec_MAIN_0_R5_2_response_tx"}, {313, "write", 2, "DM", "nonsec_MAIN_1_R5_0_notify_tx"}, {312, "write", 7, "DM", "nonsec_MAIN_1_R5_0_response_tx"}, {311, "write", 1, "DM", "nonsec_MAIN_1_R5_2_notify_tx"}, {310, "write", 2, "DM", "nonsec_MAIN_1_R5_2_response_tx"}, {309, "write", 2, "DM", "nonsec_MAIN_2_R5_0_notify_tx"}, {308, "write", 7, "DM", "nonsec_MAIN_2_R5_0_response_tx"}, {307, "write", 1, "DM", "nonsec_MAIN_2_R5_2_notify_tx"}, {306, "write", 2, "DM", "nonsec_MAIN_2_R5_2_response_tx"}, {0, "read", 2, "A72_0", "notify"}, {1, "read", 30, "A72_0", "response"}, {2, "write", 10, "A72_0", "high_priority"}, {3, "write", 20, "A72_0", "low_priority"}, {4, "write", 2, "A72_0", "notify_resp"}, {5, "read", 2, "A72_1", "notify"}, {6, "read", 30, "A72_1", "response"}, {7, "write", 10, "A72_1", "high_priority"}, {8, "write", 20, "A72_1", "low_priority"}, {9, "write", 2, "A72_1", "notify_resp"}, {10, "read", 2, "A72_2", "notify"}, {11, "read", 22, "A72_2", "response"}, {12, "write", 2, "A72_2", "high_priority"}, {13, "write", 20, "A72_2", "low_priority"}, {14, "write", 2, "A72_2", "notify_resp"}, {15, "read", 2, "A72_3", "notify"}, {16, "read", 7, "A72_3", "response"}, {17, "write", 2, "A72_3", "high_priority"}, {18, "write", 5, "A72_3", "low_priority"}, {19, "write", 2, "A72_3", "notify_resp"}, {20, "read", 2, "A72_4", "notify"}, {21, "read", 7, "A72_4", "response"}, {22, "write", 2, "A72_4", "high_priority"}, {23, "write", 5, "A72_4", "low_priority"}, {24, "write", 2, "A72_4", "notify_resp"}, {25, "read", 2, "A72_5", "notify"}, {26, "read", 22, "A72_5", "response"}, {27, "write", 2, "A72_5", "high_priority"}, {28, "write", 20, "A72_5", "low_priority"}, {29, "write", 2, "A72_5", "notify_resp"}, {30, "read", 2, "A72_6", "notify"}, {31, "read", 7, "A72_6", "response"}, {32, "write", 2, "A72_6", "high_priority"}, {33, "write", 5, "A72_6", "low_priority"}, {34, "write", 2, "A72_6", "notify_resp"}, {35, "read", 2, "A72_7", "notify"}, {36, "read", 7, "A72_7", "response"}, {37, "write", 2, "A72_7", "high_priority"}, {38, "write", 5, "A72_7", "low_priority"}, {39, "write", 2, "A72_7", "notify_resp"}, {40, "read", 2, "C7X_0_0", "notify"}, {41, "read", 7, "C7X_0_0", "response"}, {42, "write", 2, "C7X_0_0", "high_priority"}, {43, "write", 5, "C7X_0_0", "low_priority"}, {44, "write", 2, "C7X_0_0", "notify_resp"}, {45, "read", 2, "C7X_0_1", "notify"}, {46, "read", 7, "C7X_0_1", "response"}, {47, "write", 2, "C7X_0_1", "high_priority"}, {48, "write", 5, "C7X_0_1", "low_priority"}, {49, "write", 2, "C7X_0_1", "notify_resp"}, {50, "read", 2, "C7X_1_0", "notify"}, {51, "read", 7, "C7X_1_0", "response"}, {52, "write", 2, "C7X_1_0", "high_priority"}, {53, "write", 5, "C7X_1_0", "low_priority"}, {54, "write", 2, "C7X_1_0", "notify_resp"}, {55, "read", 2, "C7X_1_1", "notify"}, {56, "read", 7, "C7X_1_1", "response"}, {57, "write", 2, "C7X_1_1", "high_priority"}, {58, "write", 5, "C7X_1_1", "low_priority"}, {59, "write", 2, "C7X_1_1", "notify_resp"}, {60, "read", 2, "C7X_2_0", "notify"}, {61, "read", 7, "C7X_2_0", "response"}, {62, "write", 2, "C7X_2_0", "high_priority"}, {63, "write", 5, "C7X_2_0", "low_priority"}, {64, "write", 2, "C7X_2_0", "notify_resp"}, {65, "read", 2, "C7X_2_1", "notify"}, {66, "read", 7, "C7X_2_1", "response"}, {67, "write", 2, "C7X_2_1", "high_priority"}, {68, "write", 5, "C7X_2_1", "low_priority"}, {69, "write", 2, "C7X_2_1", "notify_resp"}, {70, "read", 2, "C7X_3_0", "notify"}, {71, "read", 7, "C7X_3_0", "response"}, {72, "write", 2, "C7X_3_0", "high_priority"}, {73, "write", 5, "C7X_3_0", "low_priority"}, {74, "write", 2, "C7X_3_0", "notify_resp"}, {75, "read", 2, "C7X_3_1", "notify"}, {76, "read", 7, "C7X_3_1", "response"}, {77, "write", 2, "C7X_3_1", "high_priority"}, {78, "write", 5, "C7X_3_1", "low_priority"}, {79, "write", 2, "C7X_3_1", "notify_resp"}, {80, "read", 2, "GPU_0", "notify"}, {81, "read", 7, "GPU_0", "response"}, {82, "write", 2, "GPU_0", "high_priority"}, {83, "write", 5, "GPU_0", "low_priority"}, {84, "write", 2, "GPU_0", "notify_resp"}, {85, "read", 2, "MAIN_0_R5_0", "notify"}, {86, "read", 7, "MAIN_0_R5_0", "response"}, {87, "write", 2, "MAIN_0_R5_0", "high_priority"}, {88, "write", 5, "MAIN_0_R5_0", "low_priority"}, {89, "write", 2, "MAIN_0_R5_0", "notify_resp"}, {90, "read", 2, "MAIN_0_R5_1", "notify"}, {91, "read", 7, "MAIN_0_R5_1", "response"}, {92, "write", 2, "MAIN_0_R5_1", "high_priority"}, {93, "write", 5, "MAIN_0_R5_1", "low_priority"}, {94, "write", 2, "MAIN_0_R5_1", "notify_resp"}, {95, "read", 1, "MAIN_0_R5_2", "notify"}, {96, "read", 2, "MAIN_0_R5_2", "response"}, {97, "write", 1, "MAIN_0_R5_2", "high_priority"}, {98, "write", 1, "MAIN_0_R5_2", "low_priority"}, {99, "write", 1, "MAIN_0_R5_2", "notify_resp"}, {100, "read", 1, "MAIN_0_R5_3", "notify"}, {101, "read", 2, "MAIN_0_R5_3", "response"}, {102, "write", 1, "MAIN_0_R5_3", "high_priority"}, {103, "write", 1, "MAIN_0_R5_3", "low_priority"}, {104, "write", 1, "MAIN_0_R5_3", "notify_resp"}, {105, "read", 2, "MAIN_1_R5_0", "notify"}, {106, "read", 7, "MAIN_1_R5_0", "response"}, {107, "write", 2, "MAIN_1_R5_0", "high_priority"}, {108, "write", 5, "MAIN_1_R5_0", "low_priority"}, {109, "write", 2, "MAIN_1_R5_0", "notify_resp"}, {110, "read", 2, "MAIN_1_R5_1", "notify"}, {111, "read", 7, "MAIN_1_R5_1", "response"}, {112, "write", 2, "MAIN_1_R5_1", "high_priority"}, {113, "write", 5, "MAIN_1_R5_1", "low_priority"}, {114, "write", 2, "MAIN_1_R5_1", "notify_resp"}, {115, "read", 1, "MAIN_1_R5_2", "notify"}, {116, "read", 2, "MAIN_1_R5_2", "response"}, {117, "write", 1, "MAIN_1_R5_2", "high_priority"}, {118, "write", 1, "MAIN_1_R5_2", "low_priority"}, {119, "write", 1, "MAIN_1_R5_2", "notify_resp"}, {120, "read", 1, "MAIN_1_R5_3", "notify"}, {121, "read", 2, "MAIN_1_R5_3", "response"}, {122, "write", 1, "MAIN_1_R5_3", "high_priority"}, {123, "write", 1, "MAIN_1_R5_3", "low_priority"}, {124, "write", 1, "MAIN_1_R5_3", "notify_resp"}, {125, "read", 2, "MAIN_2_R5_0", "notify"}, {126, "read", 7, "MAIN_2_R5_0", "response"}, {127, "write", 2, "MAIN_2_R5_0", "high_priority"}, {128, "write", 5, "MAIN_2_R5_0", "low_priority"}, {129, "write", 2, "MAIN_2_R5_0", "notify_resp"}, {130, "read", 2, "MAIN_2_R5_1", "notify"}, {131, "read", 7, "MAIN_2_R5_1", "response"}, {132, "write", 2, "MAIN_2_R5_1", "high_priority"}, {133, "write", 5, "MAIN_2_R5_1", "low_priority"}, {134, "write", 2, "MAIN_2_R5_1", "notify_resp"}, {135, "read", 1, "MAIN_2_R5_2", "notify"}, {136, "read", 2, "MAIN_2_R5_2", "response"}, {137, "write", 1, "MAIN_2_R5_2", "high_priority"}, {138, "write", 1, "MAIN_2_R5_2", "low_priority"}, {139, "write", 1, "MAIN_2_R5_2", "notify_resp"}, {140, "read", 1, "MAIN_2_R5_3", "notify"}, {141, "read", 2, "MAIN_2_R5_3", "response"}, {142, "write", 1, "MAIN_2_R5_3", "high_priority"}, {143, "write", 1, "MAIN_2_R5_3", "low_priority"}, {144, "write", 1, "MAIN_2_R5_3", "notify_resp"}, }; struct ti_sci_sec_proxy_info j784s4_mcu_sp_info[] = { {78, "read", 13, "DM", "nonsec_high_priority_rx"}, {77, "read", 13, "DM", "nonsec_low_priority_rx"}, {76, "read", 5, "DM", "nonsec_notify_resp_rx"}, {75, "write", 2, "DM", "nonsec_MCU_0_R5_0_notify_tx"}, {74, "write", 20, "DM", "nonsec_MCU_0_R5_0_response_tx"}, {73, "write", 1, "DM", "nonsec_MCU_0_R5_2_notify_tx"}, {72, "write", 2, "DM", "nonsec_MCU_0_R5_2_response_tx"}, {71, "write", 2, "DM", "nonsec_TIFS2DM_notify_tx"}, {70, "write", 4, "DM", "nonsec_TIFS2DM_response_tx"}, {0, "read", 2, "MCU_0_R5_0", "notify"}, {1, "read", 20, "MCU_0_R5_0", "response"}, {2, "write", 10, "MCU_0_R5_0", "high_priority"}, {3, "write", 10, "MCU_0_R5_0", "low_priority"}, {4, "write", 2, "MCU_0_R5_0", "notify_resp"}, {5, "read", 2, "MCU_0_R5_1", "notify"}, {6, "read", 20, "MCU_0_R5_1", "response"}, {7, "write", 10, "MCU_0_R5_1", "high_priority"}, {8, "write", 10, "MCU_0_R5_1", "low_priority"}, {9, "write", 2, "MCU_0_R5_1", "notify_resp"}, {10, "read", 1, "MCU_0_R5_2", "notify"}, {11, "read", 2, "MCU_0_R5_2", "response"}, {12, "write", 1, "MCU_0_R5_2", "high_priority"}, {13, "write", 1, "MCU_0_R5_2", "low_priority"}, {14, "write", 1, "MCU_0_R5_2", "notify_resp"}, {15, "read", 1, "MCU_0_R5_3", "notify"}, {16, "read", 2, "MCU_0_R5_3", "response"}, {17, "write", 1, "MCU_0_R5_3", "high_priority"}, {18, "write", 1, "MCU_0_R5_3", "low_priority"}, {19, "write", 1, "MCU_0_R5_3", "notify_resp"}, {20, "read", 2, "DM2TIFS", "notify"}, {21, "read", 4, "DM2TIFS", "response"}, {22, "write", 2, "DM2TIFS", "high_priority"}, {23, "write", 2, "DM2TIFS", "low_priority"}, {24, "write", 2, "DM2TIFS", "notify_resp"}, {25, "read", 2, "TIFS2DM", "notify"}, {26, "read", 4, "TIFS2DM", "response"}, {27, "write", 2, "TIFS2DM", "high_priority"}, {28, "write", 2, "TIFS2DM", "low_priority"}, {29, "write", 2, "TIFS2DM", "notify_resp"}, {30, "read", 1, "HSM", "notify"}, {31, "read", 2, "HSM", "response"}, {32, "write", 1, "HSM", "high_priority"}, {33, "write", 1, "HSM", "low_priority"}, {34, "write", 1, "HSM", "notify_resp"}, }; k3conf_0.3/soc/j784s4/j784s4_host_info.c0000664000175000017500000001030414375734376014472 0ustar /* * J784S4 Hosts Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_host_info j784s4_host_info[] = { {0, "TIFS", "Secure", "Security Controller"}, {3, "MCU_0_R5_0", "Non Secure", "Cortex R5 context 0 on MCU island"}, {4, "MCU_0_R5_1", "Secure", "Cortex R5 context 1 on MCU island(Boot)"}, {5, "MCU_0_R5_2", "Non Secure", "Cortex R5 context 2 on MCU island"}, {6, "MCU_0_R5_3", "Secure", "Cortex R5 context 3 on MCU island"}, {10, "A72_0", "Secure", "Cortex A72 context 0 on Main island"}, {11, "A72_1", "Secure", "Cortex A72 context 1 on Main island"}, {12, "A72_2", "Non Secure", "Cortex A72 context 2 on Main island"}, {13, "A72_3", "Non Secure", "Cortex A72 context 3 on Main island"}, {14, "A72_4", "Non Secure", "Cortex A72 context 4 on Main island"}, {15, "A72_5", "Non Secure", "Cortex A72 context 5 on Main island"}, {16, "A72_6", "Non Secure", "Cortex A72 context 6 on Main island"}, {17, "A72_7", "Non Secure", "Cortex A72 context 7 on Main island"}, {20, "C7X_0_0", "Secure", "C7x_0 Context 0 on Main island"}, {21, "C7X_0_1", "Non Secure", "C7x_0 context 1 on Main island"}, {22, "C7X_1_0", "Secure", "C7x_1 Context 0 on Main island"}, {23, "C7X_1_1", "Non Secure", "C7x_1 context 1 on Main island"}, {24, "C7X_2_0", "Secure", "C7x_2 Context 0 on Main island"}, {25, "C7X_2_1", "Non Secure", "C7x_2 context 1 on Main island"}, {26, "C7X_3_0", "Secure", "C7x_2 Context 0 on Main island"}, {27, "C7X_3_1", "Non Secure", "C7x_3 context 1 on Main island"}, {30, "GPU_0", "Non Secure", "BXS context 0 on Main island"}, {35, "MAIN_0_R5_0", "Non Secure", "Cortex R5_0 context 0 on Main island"}, {36, "MAIN_0_R5_1", "Secure", "Cortex R5_0 context 1 on Main island"}, {37, "MAIN_0_R5_2", "Non Secure", "Cortex R5_0 context 2 on Main island"}, {38, "MAIN_0_R5_3", "Secure", "Cortex R5_0 context 3 on Main island"}, {40, "MAIN_1_R5_0", "Non Secure", "Cortex R5_1 context 0 on Main island"}, {41, "MAIN_1_R5_1", "Secure", "Cortex R5_1 context 1 on Main island"}, {42, "MAIN_1_R5_2", "Non Secure", "Cortex R5_1 context 2 on Main island"}, {43, "MAIN_1_R5_3", "Secure", "Cortex R5_1 context 3 on Main island"}, {45, "MAIN_2_R5_0", "Non Secure", "Cortex R5_2 context 0 on Main island"}, {46, "MAIN_2_R5_1", "Secure", "Cortex R5_2 context 1 on Main island"}, {47, "MAIN_2_R5_2", "Non Secure", "Cortex R5_2 context 2 on Main island"}, {48, "MAIN_2_R5_3", "Secure", "Cortex R5_2 context 3 on Main island"}, {250, "DM2TIFS", "Secure", "DM to TIFS communication"}, {251, "TIFS2DM", "Non Secure", "TIFS to DM communication"}, {253, "HSM", "Secure", "HSM Controller"}, {254, "DM", "Non Secure", "Device Management"}, }; k3conf_0.3/soc/j784s4/j784s4_rm_info.h0000664000175000017500000000342714375734376014150 0ustar /* * J784S4 RM Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __J784S4_RM_INFO_H #define __J784S4_RM_INFO_H #define J784S4_MAX_RES 68 extern struct ti_sci_rm_info j784s4_rm_info[]; #endif /* __J784S4_RM_INFO_H */ k3conf_0.3/soc/j784s4/j784s4_devices_info.c0000664000175000017500000003666014375734376015154 0ustar /* * J784S4 Devices Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_devices_info j784s4_devices_info[] = { {0, "J784S4_DEV_MCU_ADC12FC_16FFC0"}, {1, "J784S4_DEV_MCU_ADC12FC_16FFC1"}, {2, "J784S4_DEV_ATL0"}, {3, "J784S4_DEV_C71X_0_PBIST_VD"}, {5, "J784S4_DEV_C71X_1_PBIST_VD"}, {6, "J784S4_DEV_COMPUTE_CLUSTER0"}, {7, "J784S4_DEV_J7AM_PULSAR_ATB_FUNNEL0"}, {8, "J784S4_DEV_SA2_CPSW_PSILSS0"}, {9, "J784S4_DEV_WKUP_J7AM_WAKEUP_16FF0"}, {10, "J784S4_DEV_GPIOMUX_INTRTR0"}, {11, "J784S4_DEV_CMPEVENT_INTRTR0"}, {17, "J784S4_DEV_COMPUTE_CLUSTER0_AC71_4_DFT_EMBED_PBIST_0"}, {18, "J784S4_DEV_COMPUTE_CLUSTER0_AC71_5_DFT_EMBED_PBIST_0"}, {19, "J784S4_DEV_COMPUTE_CLUSTER0_AC71_6_DFT_EMBED_PBIST_0"}, {20, "J784S4_DEV_COMPUTE_CLUSTER0_AC71_7_DFT_EMBED_PBIST_0"}, {21, "J784S4_DEV_COMPUTE_CLUSTER0_ARM0_DFT_EMBED_PBIST_0"}, {22, "J784S4_DEV_WKUP_SMS0"}, {23, "J784S4_DEV_COMPUTE_CLUSTER0_ARM0_DFT_EMBED_PBIST_1"}, {24, "J784S4_DEV_COMPUTE_CLUSTER0_ARM1_DFT_EMBED_PBIST_0"}, {25, "J784S4_DEV_COMPUTE_CLUSTER0_ARM1_DFT_EMBED_PBIST_1"}, {26, "J784S4_DEV_COMPUTE_CLUSTER0_AW4_MSMC_DFT_EMBED_PBIST_0"}, {27, "J784S4_DEV_COMPUTE_CLUSTER0_AW5_MSMC_DFT_EMBED_PBIST_0"}, {28, "J784S4_DEV_COMPUTE_CLUSTER0_AW6_MSMC_DFT_EMBED_PBIST_0"}, {29, "J784S4_DEV_COMPUTE_CLUSTER0_AW7_MSMC_DFT_EMBED_PBIST_0"}, {30, "J784S4_DEV_COMPUTE_CLUSTER0_C71SS0"}, {31, "J784S4_DEV_COMPUTE_CLUSTER0_C71SS0_CORE0"}, {32, "J784S4_DEV_COMPUTE_CLUSTER0_C71SS0_MMA_0"}, {33, "J784S4_DEV_COMPUTE_CLUSTER0_C71SS1"}, {34, "J784S4_DEV_COMPUTE_CLUSTER0_C71SS1_CORE0"}, {35, "J784S4_DEV_MCU_TIMER0"}, {36, "J784S4_DEV_COMPUTE_CLUSTER0_C71SS1_MMA_0"}, {37, "J784S4_DEV_COMPUTE_CLUSTER0_C71SS2"}, {38, "J784S4_DEV_COMPUTE_CLUSTER0_C71SS2_CORE0"}, {39, "J784S4_DEV_COMPUTE_CLUSTER0_C71SS2_MMA_0"}, {40, "J784S4_DEV_COMPUTE_CLUSTER0_C71SS3"}, {41, "J784S4_DEV_COMPUTE_CLUSTER0_C71SS3_CORE0"}, {42, "J784S4_DEV_COMPUTE_CLUSTER0_C71SS3_MMA_0"}, {43, "J784S4_DEV_COMPUTE_CLUSTER0_CFG_WRAP_0"}, {44, "J784S4_DEV_COMPUTE_CLUSTER0_CLEC"}, {45, "J784S4_DEV_COMPUTE_CLUSTER0_CORE_CORE"}, {46, "J784S4_DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF_0"}, {47, "J784S4_DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF_1"}, {48, "J784S4_DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF_2"}, {49, "J784S4_DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF_3"}, {50, "J784S4_DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_0"}, {51, "J784S4_DEV_COMPUTE_CLUSTER0_DIVH2_DIVH_0"}, {52, "J784S4_DEV_COMPUTE_CLUSTER0_DIVH2_DIVH_1"}, {53, "J784S4_DEV_COMPUTE_CLUSTER0_DIVP_TFT_0"}, {54, "J784S4_DEV_COMPUTE_CLUSTER0_DIVP_TFT_1"}, {55, "J784S4_DEV_COMPUTE_CLUSTER0_DMSC_WRAP_0"}, {57, "J784S4_DEV_COMPUTE_CLUSTER0_EN_MSMC_DOMAIN_0"}, {58, "J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS"}, {59, "J784S4_DEV_COMPUTE_CLUSTER0_MSMC2_WRAP_0"}, {60, "J784S4_DEV_COMPUTE_CLUSTER0_MSMC_DFT_EMBED_PBIST_0"}, {61, "J784S4_DEV_GTC0"}, {62, "J784S4_DEV_CPSW1"}, {63, "J784S4_DEV_MCU_CPSW0"}, {64, "J784S4_DEV_CPSW_9XUSS_J7AM0"}, {65, "J784S4_DEV_CPT2_AGGR1"}, {66, "J784S4_DEV_CPT2_AGGR5"}, {67, "J784S4_DEV_CPT2_AGGR2"}, {68, "J784S4_DEV_CPT2_AGGR4"}, {69, "J784S4_DEV_CPT2_AGGR3"}, {70, "J784S4_DEV_CPT2_AGGR0"}, {71, "J784S4_DEV_MCU_CPT2_AGGR0"}, {72, "J784S4_DEV_CSI_RX_IF0"}, {73, "J784S4_DEV_CSI_RX_IF1"}, {74, "J784S4_DEV_CSI_RX_IF2"}, {75, "J784S4_DEV_CSI_TX_IF_V2_0"}, {76, "J784S4_DEV_CSI_TX_IF_V2_1"}, {77, "J784S4_DEV_STM0"}, {78, "J784S4_DEV_DCC0"}, {79, "J784S4_DEV_DCC1"}, {80, "J784S4_DEV_DCC2"}, {81, "J784S4_DEV_DCC3"}, {82, "J784S4_DEV_DCC4"}, {83, "J784S4_DEV_DCC5"}, {84, "J784S4_DEV_DCC6"}, {85, "J784S4_DEV_DCC7"}, {86, "J784S4_DEV_DCC8"}, {87, "J784S4_DEV_DCC9"}, {88, "J784S4_DEV_MCU_DCC0"}, {89, "J784S4_DEV_MCU_DCC1"}, {90, "J784S4_DEV_MCU_DCC2"}, {91, "J784S4_DEV_DEBUGSS_WRAP0"}, {92, "J784S4_DEV_DMPAC0"}, {93, "J784S4_DEV_DMPAC0_CTSET_0"}, {94, "J784S4_DEV_DMPAC0_INTD_0"}, {95, "J784S4_DEV_DMPAC0_UTC_0"}, {96, "J784S4_DEV_DMPAC0_SDE_0"}, {97, "J784S4_DEV_TIMER0"}, {98, "J784S4_DEV_TIMER1"}, {99, "J784S4_DEV_TIMER2"}, {100, "J784S4_DEV_TIMER3"}, {101, "J784S4_DEV_TIMER4"}, {102, "J784S4_DEV_TIMER5"}, {103, "J784S4_DEV_TIMER6"}, {104, "J784S4_DEV_TIMER7"}, {105, "J784S4_DEV_TIMER8"}, {106, "J784S4_DEV_TIMER9"}, {107, "J784S4_DEV_TIMER10"}, {108, "J784S4_DEV_TIMER11"}, {109, "J784S4_DEV_TIMER12"}, {110, "J784S4_DEV_TIMER13"}, {111, "J784S4_DEV_TIMER14"}, {112, "J784S4_DEV_TIMER15"}, {113, "J784S4_DEV_TIMER16"}, {114, "J784S4_DEV_TIMER17"}, {115, "J784S4_DEV_TIMER18"}, {116, "J784S4_DEV_TIMER19"}, {117, "J784S4_DEV_MCU_TIMER1"}, {118, "J784S4_DEV_MCU_TIMER2"}, {119, "J784S4_DEV_MCU_TIMER3"}, {120, "J784S4_DEV_MCU_TIMER4"}, {121, "J784S4_DEV_MCU_TIMER5"}, {122, "J784S4_DEV_MCU_TIMER6"}, {123, "J784S4_DEV_MCU_TIMER7"}, {124, "J784S4_DEV_MCU_TIMER8"}, {125, "J784S4_DEV_MCU_TIMER9"}, {126, "J784S4_DEV_ECAP0"}, {127, "J784S4_DEV_ECAP1"}, {128, "J784S4_DEV_ECAP2"}, {130, "J784S4_DEV_ELM0"}, {131, "J784S4_DEV_EMIF_DATA_0_VD"}, {132, "J784S4_DEV_EMIF_DATA_1_VD"}, {133, "J784S4_DEV_EMIF_DATA_2_VD"}, {139, "J784S4_DEV_EMIF_DATA_3_VD"}, {140, "J784S4_DEV_MMCSD0"}, {141, "J784S4_DEV_MMCSD1"}, {142, "J784S4_DEV_EQEP0"}, {143, "J784S4_DEV_EQEP1"}, {144, "J784S4_DEV_EQEP2"}, {145, "J784S4_DEV_ESM0"}, {146, "J784S4_DEV_UART0"}, {147, "J784S4_DEV_WKUP_ESM0"}, {148, "J784S4_DEV_MCU_ESM0"}, {149, "J784S4_DEV_MCU_UART0"}, {150, "J784S4_DEV_FFI_MAIN_AC_CBASS_VD"}, {151, "J784S4_DEV_FFI_MAIN_AC_QM_CBASS_VD"}, {152, "J784S4_DEV_FFI_MAIN_HC_CBASS_VD"}, {153, "J784S4_DEV_FFI_MAIN_INFRA_CBASS_VD"}, {154, "J784S4_DEV_FFI_MAIN_IP_CBASS_VD"}, {155, "J784S4_DEV_FFI_MAIN_RC_CBASS_VD"}, {156, "J784S4_DEV_MCU_FSS0"}, {157, "J784S4_DEV_BOARD0"}, {158, "J784S4_DEV_MCU_FSS0_FSAS_0"}, {160, "J784S4_DEV_MCU_FSS0_HYPERBUS1P0_0"}, {161, "J784S4_DEV_MCU_FSS0_OSPI_0"}, {162, "J784S4_DEV_MCU_FSS0_OSPI_1"}, {163, "J784S4_DEV_GPIO0"}, {164, "J784S4_DEV_GPIO2"}, {165, "J784S4_DEV_GPIO4"}, {166, "J784S4_DEV_GPIO6"}, {167, "J784S4_DEV_WKUP_GPIO0"}, {168, "J784S4_DEV_WKUP_GPIO1"}, {169, "J784S4_DEV_GPMC0"}, {170, "J784S4_DEV_MCU_I3C0"}, {171, "J784S4_DEV_MCU_I3C1"}, {172, "J784S4_DEV_LED0"}, {173, "J784S4_DEV_MAIN2MCU_LVL_INTRTR0"}, {174, "J784S4_DEV_MAIN2MCU_PLS_INTRTR0"}, {175, "J784S4_DEV_WKUP_PORZ_SYNC0"}, {176, "J784S4_DEV_TIMESYNC_INTRTR0"}, {177, "J784S4_DEV_WKUP_GPIOMUX_INTRTR0"}, {178, "J784S4_DEV_WKUP_PSC0"}, {179, "J784S4_DEV_J7AEP_GPU_BXS464_WRAP0"}, {180, "J784S4_DEV_J7AEP_GPU_BXS464_WRAP0_DFT_EMBED_PBIST_0"}, {181, "J784S4_DEV_J7AEP_GPU_BXS464_WRAP0_GPU_SS_0"}, {182, "J784S4_DEV_J7AEP_GPU_BXS464_WRAP0_GPUCORE_0"}, {183, "J784S4_DEV_J7AM_32_64_ATB_FUNNEL0"}, {184, "J784S4_DEV_J7AM_32_64_ATB_FUNNEL1"}, {185, "J784S4_DEV_J7AM_32_64_ATB_FUNNEL2"}, {186, "J784S4_DEV_AGGR_ATB0"}, {187, "J784S4_DEV_J7AM_BOLT_PGD0"}, {188, "J784S4_DEV_J7AM_BOLT_PSC_WRAP0"}, {189, "J784S4_DEV_CSI_PSILSS0"}, {190, "J784S4_DEV_DEBUGSUSPENDRTR0"}, {191, "J784S4_DEV_DDR0"}, {192, "J784S4_DEV_DDR1"}, {193, "J784S4_DEV_DDR2"}, {194, "J784S4_DEV_DDR3"}, {195, "J784S4_DEV_DMPAC_VPAC_PSILSS0"}, {197, "J784S4_DEV_J7AM_HWA_ATB_FUNNEL0"}, {198, "J784S4_DEV_A72SS0"}, {199, "J784S4_DEV_J7AM_MAIN_16FF0"}, {200, "J784S4_DEV_A72SS1"}, {201, "J784S4_DEV_PSC0"}, {202, "J784S4_DEV_A72SS0_CORE0"}, {203, "J784S4_DEV_A72SS0_CORE1"}, {204, "J784S4_DEV_A72SS0_CORE2"}, {205, "J784S4_DEV_A72SS0_CORE3"}, {206, "J784S4_DEV_A72SS1_CORE0"}, {207, "J784S4_DEV_A72SS1_CORE1"}, {208, "J784S4_DEV_A72SS1_CORE2"}, {209, "J784S4_DEV_A72SS1_CORE3"}, {211, "J784S4_DEV_WKUP_DDPA0"}, {212, "J784S4_DEV_DPHY_RX0"}, {213, "J784S4_DEV_DPHY_RX1"}, {214, "J784S4_DEV_DPHY_RX2"}, {215, "J784S4_DEV_DSS_DSI0"}, {216, "J784S4_DEV_DSS_DSI1"}, {217, "J784S4_DEV_DSS_EDP0"}, {218, "J784S4_DEV_DSS0"}, {219, "J784S4_DEV_EPWM0"}, {220, "J784S4_DEV_EPWM1"}, {221, "J784S4_DEV_EPWM2"}, {222, "J784S4_DEV_EPWM3"}, {223, "J784S4_DEV_EPWM4"}, {224, "J784S4_DEV_EPWM5"}, {225, "J784S4_DEV_PBIST7"}, {226, "J784S4_DEV_PBIST5"}, {227, "J784S4_DEV_PBIST11"}, {228, "J784S4_DEV_PBIST15"}, {229, "J784S4_DEV_PBIST8"}, {230, "J784S4_DEV_PBIST13"}, {231, "J784S4_DEV_PBIST3"}, {232, "J784S4_DEV_PBIST0"}, {233, "J784S4_DEV_PBIST1"}, {234, "J784S4_DEV_PBIST4"}, {235, "J784S4_DEV_PBIST2"}, {236, "J784S4_DEV_PBIST10"}, {237, "J784S4_DEV_PBIST14"}, {238, "J784S4_DEV_MCU_PBIST0"}, {239, "J784S4_DEV_MCU_PBIST1"}, {240, "J784S4_DEV_MCU_PBIST2"}, {241, "J784S4_DEV_CODEC0"}, {242, "J784S4_DEV_CODEC1"}, {243, "J784S4_DEV_WKUP_VTM0"}, {244, "J784S4_DEV_MAIN2WKUPMCU_VD"}, {245, "J784S4_DEV_MCAN0"}, {246, "J784S4_DEV_MCAN1"}, {247, "J784S4_DEV_MCAN2"}, {248, "J784S4_DEV_MCAN3"}, {249, "J784S4_DEV_MCAN4"}, {250, "J784S4_DEV_MCAN5"}, {251, "J784S4_DEV_MCAN6"}, {252, "J784S4_DEV_MCAN7"}, {253, "J784S4_DEV_MCAN8"}, {254, "J784S4_DEV_MCAN9"}, {255, "J784S4_DEV_MCAN10"}, {256, "J784S4_DEV_MCAN11"}, {257, "J784S4_DEV_MCAN12"}, {258, "J784S4_DEV_MCAN13"}, {259, "J784S4_DEV_MCAN14"}, {260, "J784S4_DEV_MCAN15"}, {261, "J784S4_DEV_MCAN16"}, {262, "J784S4_DEV_MCAN17"}, {263, "J784S4_DEV_MCU_MCAN0"}, {264, "J784S4_DEV_MCU_MCAN1"}, {265, "J784S4_DEV_MCASP0"}, {266, "J784S4_DEV_MCASP1"}, {267, "J784S4_DEV_MCASP2"}, {268, "J784S4_DEV_MCASP3"}, {269, "J784S4_DEV_MCASP4"}, {270, "J784S4_DEV_I2C0"}, {271, "J784S4_DEV_I2C1"}, {272, "J784S4_DEV_I2C2"}, {273, "J784S4_DEV_I2C3"}, {274, "J784S4_DEV_I2C4"}, {275, "J784S4_DEV_I2C5"}, {276, "J784S4_DEV_I2C6"}, {277, "J784S4_DEV_MCU_I2C0"}, {278, "J784S4_DEV_MCU_I2C1"}, {279, "J784S4_DEV_WKUP_I2C0"}, {280, "J784S4_DEV_NAVSS0"}, {281, "J784S4_DEV_NAVSS0_BCDMA_0"}, {282, "J784S4_DEV_NAVSS0_CPTS_0"}, {283, "J784S4_DEV_NAVSS0_INTR_0"}, {284, "J784S4_DEV_NAVSS0_MAILBOX1_0"}, {285, "J784S4_DEV_NAVSS0_MAILBOX1_1"}, {286, "J784S4_DEV_NAVSS0_MAILBOX1_2"}, {287, "J784S4_DEV_NAVSS0_MAILBOX1_3"}, {288, "J784S4_DEV_NAVSS0_MAILBOX1_4"}, {289, "J784S4_DEV_NAVSS0_MAILBOX1_5"}, {290, "J784S4_DEV_NAVSS0_MAILBOX1_6"}, {291, "J784S4_DEV_NAVSS0_MAILBOX1_7"}, {292, "J784S4_DEV_NAVSS0_MAILBOX1_8"}, {293, "J784S4_DEV_NAVSS0_MAILBOX1_9"}, {294, "J784S4_DEV_NAVSS0_MAILBOX1_10"}, {295, "J784S4_DEV_NAVSS0_MAILBOX1_11"}, {296, "J784S4_DEV_NAVSS0_MAILBOX_0"}, {297, "J784S4_DEV_NAVSS0_MAILBOX_1"}, {298, "J784S4_DEV_NAVSS0_MAILBOX_2"}, {299, "J784S4_DEV_NAVSS0_MAILBOX_3"}, {300, "J784S4_DEV_NAVSS0_MAILBOX_4"}, {301, "J784S4_DEV_NAVSS0_MAILBOX_5"}, {302, "J784S4_DEV_NAVSS0_MAILBOX_6"}, {303, "J784S4_DEV_NAVSS0_MAILBOX_7"}, {304, "J784S4_DEV_NAVSS0_MAILBOX_8"}, {305, "J784S4_DEV_NAVSS0_MAILBOX_9"}, {306, "J784S4_DEV_NAVSS0_MAILBOX_10"}, {307, "J784S4_DEV_NAVSS0_MAILBOX_11"}, {308, "J784S4_DEV_NAVSS0_MCRC_0"}, {309, "J784S4_DEV_NAVSS0_MODSS"}, {310, "J784S4_DEV_NAVSS0_MODSS_INTA_0"}, {311, "J784S4_DEV_NAVSS0_MODSS_INTA_1"}, {312, "J784S4_DEV_NAVSS0_PROXY_0"}, {313, "J784S4_DEV_NAVSS0_PVU_0"}, {314, "J784S4_DEV_NAVSS0_PVU_1"}, {315, "J784S4_DEV_NAVSS0_RINGACC_0"}, {316, "J784S4_DEV_NAVSS0_SPINLOCK_0"}, {317, "J784S4_DEV_NAVSS0_TIMERMGR_0"}, {318, "J784S4_DEV_NAVSS0_TIMERMGR_1"}, {319, "J784S4_DEV_NAVSS0_UDMAP_0"}, {320, "J784S4_DEV_NAVSS0_UDMASS"}, {321, "J784S4_DEV_NAVSS0_UDMASS_INTA_0"}, {322, "J784S4_DEV_NAVSS0_VIRTSS"}, {323, "J784S4_DEV_MCU_NAVSS0"}, {324, "J784S4_DEV_MCU_NAVSS0_INTR_ROUTER_0"}, {325, "J784S4_DEV_MCU_NAVSS0_MCRC_0"}, {326, "J784S4_DEV_MCU_NAVSS0_MODSS"}, {327, "J784S4_DEV_MCU_NAVSS0_PROXY0"}, {328, "J784S4_DEV_MCU_NAVSS0_RINGACC0"}, {329, "J784S4_DEV_MCU_NAVSS0_UDMAP_0"}, {330, "J784S4_DEV_MCU_NAVSS0_UDMASS"}, {331, "J784S4_DEV_MCU_NAVSS0_UDMASS_INTA_0"}, {332, "J784S4_DEV_PCIE0"}, {333, "J784S4_DEV_PCIE1"}, {334, "J784S4_DEV_PCIE2"}, {335, "J784S4_DEV_PCIE3"}, {336, "J784S4_DEV_R5FSS0"}, {337, "J784S4_DEV_R5FSS1"}, {338, "J784S4_DEV_R5FSS2"}, {339, "J784S4_DEV_R5FSS0_CORE0"}, {340, "J784S4_DEV_R5FSS0_CORE1"}, {341, "J784S4_DEV_R5FSS1_CORE0"}, {342, "J784S4_DEV_R5FSS1_CORE1"}, {343, "J784S4_DEV_R5FSS2_CORE0"}, {344, "J784S4_DEV_R5FSS2_CORE1"}, {345, "J784S4_DEV_MCU_R5FSS0"}, {346, "J784S4_DEV_MCU_R5FSS0_CORE0"}, {347, "J784S4_DEV_MCU_R5FSS0_CORE1"}, {348, "J784S4_DEV_RTI0"}, {349, "J784S4_DEV_RTI1"}, {350, "J784S4_DEV_RTI2"}, {351, "J784S4_DEV_RTI3"}, {352, "J784S4_DEV_RTI4"}, {353, "J784S4_DEV_RTI5"}, {354, "J784S4_DEV_RTI6"}, {355, "J784S4_DEV_RTI7"}, {356, "J784S4_DEV_RTI16"}, {357, "J784S4_DEV_RTI17"}, {358, "J784S4_DEV_RTI18"}, {359, "J784S4_DEV_RTI19"}, {360, "J784S4_DEV_RTI15"}, {361, "J784S4_DEV_RTI28"}, {362, "J784S4_DEV_RTI29"}, {363, "J784S4_DEV_RTI30"}, {364, "J784S4_DEV_RTI31"}, {365, "J784S4_DEV_RTI32"}, {366, "J784S4_DEV_RTI33"}, {367, "J784S4_DEV_MCU_RTI0"}, {368, "J784S4_DEV_MCU_RTI1"}, {369, "J784S4_DEV_SA2_UL0"}, {371, "J784S4_DEV_WKUP_HSM0"}, {376, "J784S4_DEV_MCSPI0"}, {377, "J784S4_DEV_MCSPI1"}, {378, "J784S4_DEV_MCSPI2"}, {379, "J784S4_DEV_MCSPI3"}, {380, "J784S4_DEV_MCSPI4"}, {381, "J784S4_DEV_MCSPI5"}, {382, "J784S4_DEV_MCSPI6"}, {383, "J784S4_DEV_MCSPI7"}, {384, "J784S4_DEV_MCU_MCSPI0"}, {385, "J784S4_DEV_MCU_MCSPI1"}, {386, "J784S4_DEV_MCU_MCSPI2"}, {387, "J784S4_DEV_UFS0"}, {388, "J784S4_DEV_UART1"}, {389, "J784S4_DEV_UART2"}, {390, "J784S4_DEV_UART3"}, {391, "J784S4_DEV_UART4"}, {392, "J784S4_DEV_UART5"}, {393, "J784S4_DEV_UART6"}, {394, "J784S4_DEV_UART7"}, {395, "J784S4_DEV_UART8"}, {396, "J784S4_DEV_UART9"}, {397, "J784S4_DEV_WKUP_UART0"}, {398, "J784S4_DEV_USB0"}, {399, "J784S4_DEV_VPAC0"}, {400, "J784S4_DEV_VPAC1"}, {401, "J784S4_DEV_VUSR_DUAL0"}, {402, "J784S4_DEV_DPHY_TX0"}, {403, "J784S4_DEV_DPHY_TX1"}, {404, "J784S4_DEV_SERDES_10G0"}, {405, "J784S4_DEV_SERDES_10G1"}, {406, "J784S4_DEV_SERDES_10G2"}, {407, "J784S4_DEV_SERDES_10G4"}, {408, "J784S4_DEV_WKUPMCU2MAIN_VD"}, {409, "J784S4_DEV_COMPUTE_CLUSTER0_DRU0"}, {410, "J784S4_DEV_COMPUTE_CLUSTER0_DRU4"}, {411, "J784S4_DEV_COMPUTE_CLUSTER0_DRU5"}, {412, "J784S4_DEV_COMPUTE_CLUSTER0_DRU6"}, {413, "J784S4_DEV_COMPUTE_CLUSTER0_DRU7"}, {414, "J784S4_DEV_COMPUTE_CLUSTER0_DIVH4_DIVH_0"}, {415, "J784S4_DEV_ACSPCIE0_BUFCLK_MUX"}, {416, "J784S4_DEV_ACSPCIE1_BUFCLK_MUX"}, {417, "J784S4_DEV_GLUELOGIC_ACSPCIE0_BUFFER"}, {418, "J784S4_DEV_GLUELOGIC_ACSPCIE1_BUFFER"}, }; k3conf_0.3/soc/j784s4/j784s4_rm_info.c0000664000175000017500000001134214375734376014136 0ustar /* * J784S4 RM Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_rm_info j784s4_rm_info[] = { {0x0280, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x02C0, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x2B40, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x2B80, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x2C00, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x2C40, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x4642, "RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER"}, {0x4643, "RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG"}, {0x464E, "RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN"}, {0x464F, "RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN"}, {0x4661, "RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN"}, {0x4662, "RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN"}, {0x46C0, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x4D8A, "RESASG_SUBTYPE_IA_VINT"}, {0x4D8D, "RESASG_SUBTYPE_GLOBAL_EVENT_SEVT"}, {0x4DCA, "RESASG_SUBTYPE_IA_VINT"}, {0x4DCD, "RESASG_SUBTYPE_GLOBAL_EVENT_SEVT"}, {0x4E00, "RESASG_SUBTYPE_PROXY_PROXIES"}, {0x4EC0, "RESASG_SUBTYPE_RA_ERROR_OES"}, {0x4EC1, "RESASG_SUBTYPE_RA_GP"}, {0x4EC2, "RESASG_SUBTYPE_RA_UDMAP_RX"}, {0x4EC3, "RESASG_SUBTYPE_RA_UDMAP_TX"}, {0x4EC4, "RESASG_SUBTYPE_RA_UDMAP_TX_EXT"}, {0x4EC5, "RESASG_SUBTYPE_RA_UDMAP_RX_H"}, {0x4EC6, "RESASG_SUBTYPE_RA_UDMAP_RX_UH"}, {0x4EC7, "RESASG_SUBTYPE_RA_UDMAP_TX_H"}, {0x4EC8, "RESASG_SUBTYPE_RA_UDMAP_TX_UH"}, {0x4ECA, "RESASG_SUBTYPE_RA_VIRTID"}, {0x4ECB, "RESASG_SUBTYPE_RA_MONITORS"}, {0x4FC0, "RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON"}, {0x4FC1, "RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES"}, {0x4FC2, "RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER"}, {0x4FC3, "RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG"}, {0x4FCA, "RESASG_SUBTYPE_UDMAP_RX_CHAN"}, {0x4FCB, "RESASG_SUBTYPE_UDMAP_RX_HCHAN"}, {0x4FCC, "RESASG_SUBTYPE_UDMAP_RX_UHCHAN"}, {0x4FCD, "RESASG_SUBTYPE_UDMAP_TX_CHAN"}, {0x4FCE, "RESASG_SUBTYPE_UDMAP_TX_ECHAN"}, {0x4FCF, "RESASG_SUBTYPE_UDMAP_TX_HCHAN"}, {0x4FD0, "RESASG_SUBTYPE_UDMAP_TX_UHCHAN"}, {0x504A, "RESASG_SUBTYPE_IA_VINT"}, {0x504D, "RESASG_SUBTYPE_GLOBAL_EVENT_SEVT"}, {0x504F, "RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_ERROR_OES"}, {0x5050, "RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_DATA_COMPLETION_OES"}, {0x5051, "RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_RING_COMPLETION_OES"}, {0x5052, "RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_ERROR_OES"}, {0x5053, "RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_DATA_COMPLETION_OES"}, {0x5054, "RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_RING_COMPLETION_OES"}, {0x5100, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x51C0, "RESASG_SUBTYPE_PROXY_PROXIES"}, {0x5200, "RESASG_SUBTYPE_RA_ERROR_OES"}, {0x5201, "RESASG_SUBTYPE_RA_GP"}, {0x5202, "RESASG_SUBTYPE_RA_UDMAP_RX"}, {0x5203, "RESASG_SUBTYPE_RA_UDMAP_TX"}, {0x5205, "RESASG_SUBTYPE_RA_UDMAP_RX_H"}, {0x5207, "RESASG_SUBTYPE_RA_UDMAP_TX_H"}, {0x520A, "RESASG_SUBTYPE_RA_VIRTID"}, {0x520B, "RESASG_SUBTYPE_RA_MONITORS"}, {0x5240, "RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON"}, {0x5241, "RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES"}, {0x5242, "RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER"}, {0x5243, "RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG"}, {0x524A, "RESASG_SUBTYPE_UDMAP_RX_CHAN"}, {0x524B, "RESASG_SUBTYPE_UDMAP_RX_HCHAN"}, {0x524D, "RESASG_SUBTYPE_UDMAP_TX_CHAN"}, {0x524F, "RESASG_SUBTYPE_UDMAP_TX_HCHAN"}, {0x52CA, "RESASG_SUBTYPE_IA_VINT"}, {0x52CD, "RESASG_SUBTYPE_GLOBAL_EVENT_SEVT"}, }; k3conf_0.3/soc/j784s4/j784s4_clocks_info.h0000664000175000017500000000346414375734376015011 0ustar /* * J784S4 Clocks Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __J784S4_CLOCKS_INFO_H #define __J784S4_CLOCKS_INFO_H #define J784S4_MAX_CLOCKS 2641 extern struct ti_sci_clocks_info j784s4_clocks_info[]; #endif /* __J784S4_CLOCKS_INFO_H */ k3conf_0.3/soc/j784s4/j784s4_host_info.h0000664000175000017500000000612214375734376014502 0ustar /* * J784S4 Host Info * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __J784S4_HOST_INFO_H #define __J784S4_HOST_INFO_H #define J784S4_HOST_ID_TIFS 0 #define J784S4_HOST_ID_MCU_0_R5_0 3 #define J784S4_HOST_ID_MCU_0_R5_1 4 #define J784S4_HOST_ID_MCU_0_R5_2 5 #define J784S4_HOST_ID_MCU_0_R5_3 6 #define J784S4_HOST_ID_A72_0 10 #define J784S4_HOST_ID_A72_1 11 #define J784S4_HOST_ID_A72_2 12 #define J784S4_HOST_ID_A72_3 13 #define J784S4_HOST_ID_A72_4 14 #define J784S4_HOST_ID_A72_5 15 #define J784S4_HOST_ID_A72_6 16 #define J784S4_HOST_ID_A72_7 17 #define J784S4_HOST_ID_C7X_0_0 20 #define J784S4_HOST_ID_C7X_0_1 21 #define J784S4_HOST_ID_C7X_1_0 22 #define J784S4_HOST_ID_C7X_1_1 23 #define J784S4_HOST_ID_C7X_2_0 24 #define J784S4_HOST_ID_C7X_2_1 25 #define J784S4_HOST_ID_C7X_3_0 26 #define J784S4_HOST_ID_C7X_3_1 27 #define J784S4_HOST_ID_GPU_0 30 #define J784S4_HOST_ID_MAIN_0_R5_0 35 #define J784S4_HOST_ID_MAIN_0_R5_1 36 #define J784S4_HOST_ID_MAIN_0_R5_2 37 #define J784S4_HOST_ID_MAIN_0_R5_3 38 #define J784S4_HOST_ID_MAIN_1_R5_0 40 #define J784S4_HOST_ID_MAIN_1_R5_1 41 #define J784S4_HOST_ID_MAIN_1_R5_2 42 #define J784S4_HOST_ID_MAIN_1_R5_3 43 #define J784S4_HOST_ID_MAIN_2_R5_0 45 #define J784S4_HOST_ID_MAIN_2_R5_1 46 #define J784S4_HOST_ID_MAIN_2_R5_2 47 #define J784S4_HOST_ID_MAIN_2_R5_3 48 #define J784S4_HOST_ID_DM2TIFS 250 #define J784S4_HOST_ID_TIFS2DM 251 #define J784S4_HOST_ID_HSM 253 #define J784S4_HOST_ID_DM 254 #define J784S4_MAX_HOST_IDS 38 extern struct ti_sci_host_info j784s4_host_info[]; #endif /* __J784S4_HOST_INFO_H */ k3conf_0.3/soc/am62ax/0000775000175000017500000000000014456530612011433 5ustar k3conf_0.3/soc/am62ax/am62ax_host_info.h0000664000175000017500000000451114375734376014770 0ustar /* * AM62AX Host Info * * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM62AX_HOST_INFO_H #define __AM62AX_HOST_INFO_H #define AM62AX_HOST_ID_TIFS 0 #define AM62AX_HOST_ID_A53_0 10 #define AM62AX_HOST_ID_A53_1 11 #define AM62AX_HOST_ID_A53_2 12 #define AM62AX_HOST_ID_A53_3 13 #define AM62AX_HOST_ID_A53_4 14 #define AM62AX_HOST_ID_C7X_0_0 20 #define AM62AX_HOST_ID_MCU_0_R5_0 30 #define AM62AX_HOST_ID_MAIN_0_R5_0 35 #define AM62AX_HOST_ID_MAIN_0_R5_1 36 #define AM62AX_HOST_ID_MAIN_0_R5_2 37 #define AM62AX_HOST_ID_MAIN_0_R5_3 38 #define AM62AX_HOST_ID_DM2TIFS 250 #define AM62AX_HOST_ID_TIFS2DM 251 #define AM62AX_HOST_ID_HSM 253 #define AM62AX_HOST_ID_DM 254 #define AM62AX_MAX_HOST_IDS 16 extern struct ti_sci_host_info am62ax_host_info[]; #endif /* __AM62AX_HOST_INFO_H */ k3conf_0.3/soc/am62ax/am62ax_processors_info.c0000664000175000017500000000376614375734376016223 0ustar /* * AM62AX Processor Info * * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_processors_info am62ax_processors_info[] = { {121, 0, 0x01, "WKUP_R5FSS0_CORE0"}, {9, 0, 0x03, "MCU_R5FSS0_CORE0"}, {208, 0, 0x04, "C7X256V0_C7XV_CORE_0"}, {135, 0, 0x20, "A53SS0_CORE_0"}, {136, 0, 0x21, "A53SS0_CORE_1"}, {137, 0, 0x22, "A53SS0_CORE_2"}, {138, 0, 0x23, "A53SS0_CORE_3"}, {225, 0, 0x80, "HSM0"}, }; k3conf_0.3/soc/am62ax/am62ax_rm_info.c0000664000175000017500000001241014375734376014421 0ustar /* * AM62AX RM Info * * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_rm_info am62ax_rm_info[] = { {0x0040, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x00C0, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x0140, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x0180, "RESASG_SUBTYPE_IR_OUTPUT"}, {0x0682, "RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER"}, {0x0683, "RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG"}, {0x068D, "RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN"}, {0x068E, "RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN"}, {0x068F, "RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN"}, {0x06A0, "RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN"}, {0x06A1, "RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN"}, {0x06A2, "RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN"}, {0x070A, "RESASG_SUBTYPE_IA_VINT"}, {0x070D, "RESASG_SUBTYPE_GLOBAL_EVENT_SEVT"}, {0x070F, "RESASG_SUBTYPE_IA_TIMERMGR_EVT_OES"}, {0x0710, "RESASG_SUBTYPE_IA_PKTDMA_TX_CHAN_ERROR_OES"}, {0x0711, "RESASG_SUBTYPE_IA_PKTDMA_TX_FLOW_COMPLETION_OES"}, {0x0712, "RESASG_SUBTYPE_IA_PKTDMA_RX_CHAN_ERROR_OES"}, {0x0713, "RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_COMPLETION_OES"}, {0x0714, "RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_STARVATION_OES"}, {0x0715, "RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_FIREWALL_OES"}, {0x0716, "RESASG_SUBTYPE_IA_BCDMA_CHAN_ERROR_OES"}, {0x0717, "RESASG_SUBTYPE_IA_BCDMA_CHAN_DATA_COMPLETION_OES"}, {0x0718, "RESASG_SUBTYPE_IA_BCDMA_CHAN_RING_COMPLETION_OES"}, {0x0719, "RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_ERROR_OES"}, {0x071A, "RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_DATA_COMPLETION_OES"}, {0x071B, "RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_RING_COMPLETION_OES"}, {0x071C, "RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_ERROR_OES"}, {0x071D, "RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_DATA_COMPLETION_OES"}, {0x071E, "RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_RING_COMPLETION_OES"}, {0x0783, "RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG"}, {0x0790, "RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN"}, {0x0791, "RESASG_SUBTYPE_PKTDMA_RING_CPSW_TX_CHAN"}, {0x0792, "RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_0_CHAN"}, {0x0793, "RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_1_CHAN"}, {0x0796, "RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN"}, {0x0797, "RESASG_SUBTYPE_PKTDMA_RING_CPSW_RX_CHAN"}, {0x0798, "RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_0_CHAN"}, {0x0799, "RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_1_CHAN"}, {0x079A, "RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_2_CHAN"}, {0x079B, "RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_3_CHAN"}, {0x07A3, "RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN"}, {0x07A4, "RESASG_SUBTYPE_PKTDMA_CPSW_TX_CHAN"}, {0x07A5, "RESASG_SUBTYPE_PKTDMA_SAUL_TX_0_CHAN"}, {0x07A6, "RESASG_SUBTYPE_PKTDMA_SAUL_TX_1_CHAN"}, {0x07A9, "RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN"}, {0x07AA, "RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN"}, {0x07AB, "RESASG_SUBTYPE_PKTDMA_CPSW_RX_CHAN"}, {0x07AC, "RESASG_SUBTYPE_PKTDMA_FLOW_CPSW_RX_CHAN"}, {0x07AD, "RESASG_SUBTYPE_PKTDMA_SAUL_RX_0_CHAN"}, {0x07AE, "RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_0_CHAN"}, {0x07AF, "RESASG_SUBTYPE_PKTDMA_SAUL_RX_1_CHAN"}, {0x07B0, "RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_1_CHAN"}, {0x07B1, "RESASG_SUBTYPE_PKTDMA_SAUL_RX_2_CHAN"}, {0x07B2, "RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_2_CHAN"}, {0x07B3, "RESASG_SUBTYPE_PKTDMA_SAUL_RX_3_CHAN"}, {0x07B4, "RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_3_CHAN"}, {0x0840, "RESASG_SUBTYPE_RA_ERROR_OES"}, {0x084A, "RESASG_SUBTYPE_RA_VIRTID"}, {0x31C2, "RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER"}, {0x31C3, "RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG"}, {0x31CE, "RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN"}, {0x31E1, "RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN"}, {0x320A, "RESASG_SUBTYPE_IA_VINT"}, {0x320D, "RESASG_SUBTYPE_GLOBAL_EVENT_SEVT"}, {0x321C, "RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_ERROR_OES"}, {0x321D, "RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_DATA_COMPLETION_OES"}, {0x321E, "RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_RING_COMPLETION_OES"}, }; k3conf_0.3/soc/am62ax/am62ax_processors_info.h0000664000175000017500000000351414375734376016217 0ustar /* * AM62AX Processor Info * * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM62AX_PROCESSOR_INFO_H #define __AM62AX_PROCESSOR_INFO_H #define AM62AX_MAX_PROCESSORS_IDS 8 extern struct ti_sci_processors_info am62ax_processors_info[]; #endif /* __AM62AX_PROCESSOR_INFO_H */ k3conf_0.3/soc/am62ax/am62ax_clocks_info.h0000664000175000017500000000346314375734376015276 0ustar /* * AM62AX Clocks Info * * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM62AX_CLOCKS_INFO_H #define __AM62AX_CLOCKS_INFO_H #define AM62AX_MAX_CLOCKS 865 extern struct ti_sci_clocks_info am62ax_clocks_info[]; #endif /* __AM62AX_CLOCKS_INFO_H */ k3conf_0.3/soc/am62ax/am62ax_sec_proxy_info.h0000664000175000017500000000365714375734376016040 0ustar /* * AM62AX Sec Proxy Info * * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM62AX_SEC_PROXY_INFO_H #define __AM62AX_SEC_PROXY_INFO_H #define AM62AX_MAIN_SEC_PROXY_THREADS 35 #define AM62AX_MCU_SEC_PROXY_THREADS 4 extern struct ti_sci_sec_proxy_info am62ax_main_sp_info[]; extern struct ti_sci_sec_proxy_info am62ax_mcu_sp_info[]; #endif /* __AM62AX_SEC_PROXY_INFO_H */ k3conf_0.3/soc/am62ax/am62ax_host_info.c0000664000175000017500000000530714375734376014767 0ustar /* * AM62AX Hosts Info * * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_host_info am62ax_host_info[] = { {0, "TIFS", "Secure", "TI Foundational Security"}, {10, "A53_0", "Secure", "Cortex A53 context 0 on Main island"}, {11, "A53_1", "Secure", "Cortex A53 context 1 on Main island"}, {12, "A53_2", "Non Secure", "Cortex A53 context 2 on Main island"}, {13, "A53_3", "Non Secure", "Cortex A53 context 3 on Main island"}, {14, "A53_4", "Non Secure", "Cortex A53 context 4 on Main island"}, {20, "C7X_0_0", "Non Secure", "C7x_0 Context 0 on Main island"}, {30, "MCU_0_R5_0", "Non Secure", "MCU R5"}, {35, "MAIN_0_R5_0", "Secure", "Cortex R5_0 context 0 on Main island(BOOT)"}, {36, "MAIN_0_R5_1", "Non Secure", "Cortex R5_0 context 1 on Main island"}, {37, "MAIN_0_R5_2", "Secure", "Cortex R5_0 context 2 on Main island"}, {38, "MAIN_0_R5_3", "Non Secure", "Cortex R5_0 context 3 on Main island"}, {250, "DM2TIFS", "Secure", "DM to TIFS communication"}, {251, "TIFS2DM", "Non Secure", "TIFS to DM communication"}, {253, "HSM", "Secure", "HSM Controller"}, {254, "DM", "Non Secure", "Device Management"}, }; k3conf_0.3/soc/am62ax/am62ax_devices_info.h0000664000175000017500000000347214375734376015442 0ustar /* * AM62AX Devices Info * * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM62AX_DEVICES_INFO_H #define __AM62AX_DEVICES_INFO_H #define AM62AX_MAX_DEVICES 171 extern struct ti_sci_devices_info am62ax_devices_info[]; #endif /* __AM62AX_DEVICES_INFO_H */ k3conf_0.3/soc/am62ax/am62ax_devices_info.c0000664000175000017500000001616514375734376015440 0ustar /* * AM62AX Devices Info * * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_devices_info am62ax_devices_info[] = { {1, "AM62AX_DEV_CMP_EVENT_INTROUTER0"}, {2, "AM62AX_DEV_DBGSUSPENDROUTER0"}, {3, "AM62AX_DEV_MAIN_GPIOMUX_INTROUTER0"}, {5, "AM62AX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0"}, {6, "AM62AX_DEV_TIMESYNC_EVENT_ROUTER0"}, {7, "AM62AX_DEV_MCU_R5FSS0"}, {9, "AM62AX_DEV_MCU_R5FSS0_CORE0"}, {13, "AM62AX_DEV_CPSW0"}, {15, "AM62AX_DEV_STM0"}, {16, "AM62AX_DEV_DCC0"}, {17, "AM62AX_DEV_DCC1"}, {18, "AM62AX_DEV_DCC2"}, {19, "AM62AX_DEV_DCC3"}, {20, "AM62AX_DEV_DCC4"}, {21, "AM62AX_DEV_DCC5"}, {22, "AM62AX_DEV_SMS0"}, {23, "AM62AX_DEV_MCU_DCC0"}, {24, "AM62AX_DEV_DEBUGSS_WRAP0"}, {25, "AM62AX_DEV_DMASS0"}, {26, "AM62AX_DEV_DMASS0_BCDMA_0"}, {27, "AM62AX_DEV_DMASS0_CBASS_0"}, {28, "AM62AX_DEV_DMASS0_INTAGGR_0"}, {29, "AM62AX_DEV_DMASS0_IPCSS_0"}, {30, "AM62AX_DEV_DMASS0_PKTDMA_0"}, {33, "AM62AX_DEV_DMASS0_RINGACC_0"}, {35, "AM62AX_DEV_MCU_TIMER0"}, {36, "AM62AX_DEV_TIMER0"}, {37, "AM62AX_DEV_TIMER1"}, {38, "AM62AX_DEV_TIMER2"}, {39, "AM62AX_DEV_TIMER3"}, {40, "AM62AX_DEV_TIMER4"}, {41, "AM62AX_DEV_TIMER5"}, {42, "AM62AX_DEV_TIMER6"}, {43, "AM62AX_DEV_TIMER7"}, {48, "AM62AX_DEV_MCU_TIMER1"}, {49, "AM62AX_DEV_MCU_TIMER2"}, {50, "AM62AX_DEV_MCU_TIMER3"}, {51, "AM62AX_DEV_ECAP0"}, {52, "AM62AX_DEV_ECAP1"}, {53, "AM62AX_DEV_ECAP2"}, {54, "AM62AX_DEV_ELM0"}, {55, "AM62AX_DEV_EMIF_DATA_ISO_VD"}, {57, "AM62AX_DEV_MMCSD0"}, {58, "AM62AX_DEV_MMCSD1"}, {59, "AM62AX_DEV_EQEP0"}, {60, "AM62AX_DEV_EQEP1"}, {61, "AM62AX_DEV_WKUP_GTC0"}, {62, "AM62AX_DEV_EQEP2"}, {63, "AM62AX_DEV_ESM0"}, {64, "AM62AX_DEV_WKUP_ESM0"}, {73, "AM62AX_DEV_FSS0"}, {74, "AM62AX_DEV_FSS0_FSAS_0"}, {75, "AM62AX_DEV_FSS0_OSPI_0"}, {76, "AM62AX_DEV_GICSS0"}, {77, "AM62AX_DEV_GPIO0"}, {78, "AM62AX_DEV_GPIO1"}, {79, "AM62AX_DEV_MCU_GPIO0"}, {80, "AM62AX_DEV_GPMC0"}, {83, "AM62AX_DEV_LED0"}, {85, "AM62AX_DEV_DDPA0"}, {86, "AM62AX_DEV_EPWM0"}, {87, "AM62AX_DEV_EPWM1"}, {88, "AM62AX_DEV_EPWM2"}, {95, "AM62AX_DEV_WKUP_VTM0"}, {96, "AM62AX_DEV_MAILBOX0"}, {97, "AM62AX_DEV_MAIN2MCU_VD"}, {98, "AM62AX_DEV_MCAN0"}, {100, "AM62AX_DEV_MCU_MCRC64_0"}, {102, "AM62AX_DEV_I2C0"}, {103, "AM62AX_DEV_I2C1"}, {104, "AM62AX_DEV_I2C2"}, {105, "AM62AX_DEV_I2C3"}, {106, "AM62AX_DEV_MCU_I2C0"}, {107, "AM62AX_DEV_WKUP_I2C0"}, {110, "AM62AX_DEV_WKUP_TIMER0"}, {111, "AM62AX_DEV_WKUP_TIMER1"}, {114, "AM62AX_DEV_WKUP_UART0"}, {116, "AM62AX_DEV_MCRC64_0"}, {117, "AM62AX_DEV_WKUP_RTCSS0"}, {118, "AM62AX_DEV_WKUP_R5FSS0_SS0"}, {119, "AM62AX_DEV_WKUP_R5FSS0"}, {121, "AM62AX_DEV_WKUP_R5FSS0_CORE0"}, {125, "AM62AX_DEV_RTI0"}, {126, "AM62AX_DEV_RTI1"}, {127, "AM62AX_DEV_RTI2"}, {128, "AM62AX_DEV_RTI3"}, {131, "AM62AX_DEV_MCU_RTI0"}, {132, "AM62AX_DEV_WKUP_RTI0"}, {134, "AM62AX_DEV_COMPUTE_CLUSTER0"}, {135, "AM62AX_DEV_A53SS0_CORE_0"}, {136, "AM62AX_DEV_A53SS0_CORE_1"}, {137, "AM62AX_DEV_A53SS0_CORE_2"}, {138, "AM62AX_DEV_A53SS0_CORE_3"}, {139, "AM62AX_DEV_PSCSS0"}, {140, "AM62AX_DEV_WKUP_PSC0"}, {141, "AM62AX_DEV_MCSPI0"}, {142, "AM62AX_DEV_MCSPI1"}, {143, "AM62AX_DEV_MCSPI2"}, {146, "AM62AX_DEV_UART0"}, {147, "AM62AX_DEV_MCU_MCSPI0"}, {148, "AM62AX_DEV_MCU_MCSPI1"}, {149, "AM62AX_DEV_MCU_UART0"}, {150, "AM62AX_DEV_SPINLOCK0"}, {152, "AM62AX_DEV_UART1"}, {153, "AM62AX_DEV_UART2"}, {154, "AM62AX_DEV_UART3"}, {155, "AM62AX_DEV_UART4"}, {156, "AM62AX_DEV_UART5"}, {157, "AM62AX_DEV_BOARD0"}, {158, "AM62AX_DEV_UART6"}, {161, "AM62AX_DEV_USB0"}, {162, "AM62AX_DEV_USB1"}, {163, "AM62AX_DEV_PBIST0"}, {165, "AM62AX_DEV_WKUP_PBIST0"}, {166, "AM62AX_DEV_A53SS0"}, {167, "AM62AX_DEV_COMPUTE_CLUSTER0_PBIST_0"}, {168, "AM62AX_DEV_PSC0_FW_0"}, {169, "AM62AX_DEV_PSC0"}, {170, "AM62AX_DEV_DDR32SS0"}, {171, "AM62AX_DEV_DEBUGSS0"}, {172, "AM62AX_DEV_A53_RS_BW_LIMITER0"}, {173, "AM62AX_DEV_A53_WS_BW_LIMITER1"}, {176, "AM62AX_DEV_WKUP_DEEPSLEEP_SOURCES0"}, {177, "AM62AX_DEV_EMIF_CFG_ISO_VD"}, {178, "AM62AX_DEV_MAIN_USB0_ISO_VD"}, {179, "AM62AX_DEV_MAIN_USB1_ISO_VD"}, {180, "AM62AX_DEV_MCU_MCU_16FF0"}, {182, "AM62AX_DEV_CSI_RX_IF0"}, {183, "AM62AX_DEV_DCC6"}, {184, "AM62AX_DEV_MMCSD2"}, {185, "AM62AX_DEV_DPHY_RX0"}, {186, "AM62AX_DEV_DSS0"}, {188, "AM62AX_DEV_MCU_MCAN0"}, {189, "AM62AX_DEV_MCU_MCAN1"}, {190, "AM62AX_DEV_MCASP0"}, {191, "AM62AX_DEV_MCASP1"}, {192, "AM62AX_DEV_MCASP2"}, {193, "AM62AX_DEV_CLK_32K_RC_SEL_DEV_VD"}, {194, "AM62AX_DEV_CPT2_AGGR1"}, {195, "AM62AX_DEV_CPT2_AGGR0"}, {196, "AM62AX_DEV_MCU_CPT2_AGGR0"}, {197, "AM62AX_DEV_MCU_DCC1"}, {198, "AM62AX_DEV_DMASS1"}, {199, "AM62AX_DEV_DMASS1_BCDMA_0"}, {200, "AM62AX_DEV_DMASS1_INTAGGR_0"}, {201, "AM62AX_DEV_JPGENC0"}, {202, "AM62AX_DEV_WKUP_PBIST1"}, {203, "AM62AX_DEV_MCU_PBIST0"}, {204, "AM62AX_DEV_CODEC0"}, {205, "AM62AX_DEV_RTI4"}, {206, "AM62AX_DEV_C7XV_RSWS_BS_LIMITER6"}, {207, "AM62AX_DEV_C7X256V0"}, {208, "AM62AX_DEV_C7X256V0_C7XV_CORE_0"}, {209, "AM62AX_DEV_C7X256V0_CORE0"}, {210, "AM62AX_DEV_C7X256V0_CLEC"}, {211, "AM62AX_DEV_C7X256V0_CLK"}, {212, "AM62AX_DEV_C7X256V0_DEBUG"}, {213, "AM62AX_DEV_C7X256V0_GICSS"}, {214, "AM62AX_DEV_C7X256V0_PBIST"}, {215, "AM62AX_DEV_JPGENC_RS_BW_LIMITER4"}, {216, "AM62AX_DEV_JPGENC_WS_BW_LIMITER5"}, {217, "AM62AX_DEV_VPAC_RSWS_BW_LIMITER8"}, {218, "AM62AX_DEV_VPAC_RSWS_BW_LIMITER7"}, {219, "AM62AX_DEV_VPAC0"}, {220, "AM62AX_DEV_PBIST3"}, {221, "AM62AX_DEV_CODEC_RS_BW_LIMITER2"}, {222, "AM62AX_DEV_CODEC_WS_BW_LIMITER3"}, {225, "AM62AX_DEV_HSM0"}, {226, "AM62AX_DEV_WKUP_CLKOUT_SEL_DEV_VD"}, {227, "AM62AX_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD"}, {228, "AM62AX_DEV_OBSCLK0_MUX_SEL_DEV_VD"}, }; k3conf_0.3/soc/am62ax/am62ax_clocks_info.c0000664000175000017500000022107714375734376015274 0ustar /* * AM62AX Clocks Info * * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_clocks_info am62ax_clocks_info[] = { {166, 2, "DEV_A53SS0_A53_DIVH_CLK4_OBSCLK_OUT_CLK", "Output clock"}, {166, 3, "DEV_A53SS0_COREPAC_ARM_CLK_CLK", "Input clock"}, {166, 5, "DEV_A53SS0_PLL_CTRL_CLK", "Input clock"}, {135, 0, "DEV_A53SS0_CORE_0_A53_CORE0_ARM_CLK_CLK", "Input clock"}, {136, 0, "DEV_A53SS0_CORE_1_A53_CORE1_ARM_CLK_CLK", "Input clock"}, {137, 0, "DEV_A53SS0_CORE_2_A53_CORE2_ARM_CLK_CLK", "Input clock"}, {138, 0, "DEV_A53SS0_CORE_3_A53_CORE3_ARM_CLK_CLK", "Input clock"}, {172, 0, "DEV_A53_RS_BW_LIMITER0_CLK_CLK", "Input clock"}, {173, 0, "DEV_A53_WS_BW_LIMITER1_CLK_CLK", "Input clock"}, {157, 0, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN", "Input muxed clock"}, {157, 1, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 2, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 3, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 4, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 5, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 6, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 7, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 8, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"}, {157, 9, "DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT", "Output clock"}, {157, 10, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN", "Input muxed clock"}, {157, 11, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 12, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 13, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 14, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 15, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 16, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 17, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 18, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"}, {157, 19, "DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT", "Output clock"}, {157, 20, "DEV_BOARD0_CLKOUT0_IN", "Input muxed clock"}, {157, 21, "DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK5", "Parent input clock option to DEV_BOARD0_CLKOUT0_IN"}, {157, 22, "DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK10", "Parent input clock option to DEV_BOARD0_CLKOUT0_IN"}, {157, 23, "DEV_BOARD0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Output clock"}, {157, 24, "DEV_BOARD0_DDR0_CK0_IN", "Input clock"}, {157, 25, "DEV_BOARD0_DDR0_CK0_N_IN", "Input clock"}, {157, 27, "DEV_BOARD0_DDR0_CK0_OUT", "Output clock"}, {157, 33, "DEV_BOARD0_EXT_REFCLK1_OUT", "Output clock"}, {157, 34, "DEV_BOARD0_GPMC0_CLKLB_IN", "Input clock"}, {157, 35, "DEV_BOARD0_GPMC0_CLKLB_OUT", "Output clock"}, {157, 36, "DEV_BOARD0_GPMC0_CLK_IN", "Input clock"}, {157, 37, "DEV_BOARD0_GPMC0_FCLK_MUX_IN", "Input muxed clock"}, {157, 38, "DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_BOARD0_GPMC0_FCLK_MUX_IN"}, {157, 39, "DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK", "Parent input clock option to DEV_BOARD0_GPMC0_FCLK_MUX_IN"}, {157, 40, "DEV_BOARD0_I2C0_SCL_IN", "Input clock"}, {157, 41, "DEV_BOARD0_I2C0_SCL_OUT", "Output clock"}, {157, 42, "DEV_BOARD0_I2C1_SCL_IN", "Input clock"}, {157, 43, "DEV_BOARD0_I2C1_SCL_OUT", "Output clock"}, {157, 44, "DEV_BOARD0_I2C2_SCL_IN", "Input clock"}, {157, 45, "DEV_BOARD0_I2C2_SCL_OUT", "Output clock"}, {157, 46, "DEV_BOARD0_I2C3_SCL_IN", "Input clock"}, {157, 47, "DEV_BOARD0_I2C3_SCL_OUT", "Output clock"}, {157, 49, "DEV_BOARD0_MCASP0_ACLKR_IN", "Input clock"}, {157, 50, "DEV_BOARD0_MCASP0_ACLKR_OUT", "Output clock"}, {157, 51, "DEV_BOARD0_MCASP0_ACLKX_IN", "Input clock"}, {157, 52, "DEV_BOARD0_MCASP0_ACLKX_OUT", "Output clock"}, {157, 53, "DEV_BOARD0_MCASP0_AFSR_IN", "Input clock"}, {157, 54, "DEV_BOARD0_MCASP0_AFSX_IN", "Input clock"}, {157, 55, "DEV_BOARD0_MCASP1_ACLKR_IN", "Input clock"}, {157, 56, "DEV_BOARD0_MCASP1_ACLKR_OUT", "Output clock"}, {157, 57, "DEV_BOARD0_MCASP1_ACLKX_IN", "Input clock"}, {157, 58, "DEV_BOARD0_MCASP1_ACLKX_OUT", "Output clock"}, {157, 59, "DEV_BOARD0_MCASP1_AFSR_IN", "Input clock"}, {157, 60, "DEV_BOARD0_MCASP1_AFSX_IN", "Input clock"}, {157, 61, "DEV_BOARD0_MCASP2_ACLKR_IN", "Input clock"}, {157, 62, "DEV_BOARD0_MCASP2_ACLKR_OUT", "Output clock"}, {157, 63, "DEV_BOARD0_MCASP2_ACLKX_IN", "Input clock"}, {157, 64, "DEV_BOARD0_MCASP2_ACLKX_OUT", "Output clock"}, {157, 65, "DEV_BOARD0_MCASP2_AFSR_IN", "Input clock"}, {157, 66, "DEV_BOARD0_MCASP2_AFSX_IN", "Input clock"}, {157, 67, "DEV_BOARD0_MCU_EXT_REFCLK0_OUT", "Output clock"}, {157, 69, "DEV_BOARD0_MCU_I2C0_SCL_OUT", "Output clock"}, {157, 70, "DEV_BOARD0_MCU_OBSCLK0_IN", "Input muxed clock"}, {157, 71, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"}, {157, 72, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"}, {157, 73, "DEV_BOARD0_MCU_SPI0_CLK_IN", "Input clock"}, {157, 74, "DEV_BOARD0_MCU_SPI0_CLK_OUT", "Output clock"}, {157, 75, "DEV_BOARD0_MCU_SPI1_CLK_IN", "Input clock"}, {157, 76, "DEV_BOARD0_MCU_SPI1_CLK_OUT", "Output clock"}, {157, 77, "DEV_BOARD0_MCU_SYSCLKOUT0_IN", "Input clock"}, {157, 78, "DEV_BOARD0_MCU_TIMER_IO0_IN", "Input clock"}, {157, 79, "DEV_BOARD0_MCU_TIMER_IO1_IN", "Input clock"}, {157, 80, "DEV_BOARD0_MCU_TIMER_IO2_IN", "Input clock"}, {157, 81, "DEV_BOARD0_MCU_TIMER_IO3_IN", "Input clock"}, {157, 82, "DEV_BOARD0_MDIO0_MDC_IN", "Input clock"}, {157, 83, "DEV_BOARD0_MMC0_CLKLB_IN", "Input clock"}, {157, 84, "DEV_BOARD0_MMC0_CLKLB_OUT", "Output clock"}, {157, 85, "DEV_BOARD0_MMC0_CLK_IN", "Input clock"}, {157, 86, "DEV_BOARD0_MMC0_CLK_OUT", "Output clock"}, {157, 87, "DEV_BOARD0_MMC1_CLKLB_IN", "Input clock"}, {157, 88, "DEV_BOARD0_MMC1_CLKLB_OUT", "Output clock"}, {157, 89, "DEV_BOARD0_MMC1_CLK_IN", "Input clock"}, {157, 90, "DEV_BOARD0_MMC1_CLK_OUT", "Output clock"}, {157, 91, "DEV_BOARD0_MMC2_CLKLB_IN", "Input clock"}, {157, 92, "DEV_BOARD0_MMC2_CLKLB_OUT", "Output clock"}, {157, 93, "DEV_BOARD0_MMC2_CLK_IN", "Input clock"}, {157, 94, "DEV_BOARD0_MMC2_CLK_OUT", "Output clock"}, {157, 95, "DEV_BOARD0_OBSCLK0_IN", "Input muxed clock"}, {157, 96, "DEV_BOARD0_OBSCLK0_IN_PARENT_MAIN_OBSCLK_DIV_OUT0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 97, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"}, {157, 128, "DEV_BOARD0_OBSCLK1_IN", "Input clock"}, {157, 129, "DEV_BOARD0_OSPI0_DQS_OUT", "Output clock"}, {157, 130, "DEV_BOARD0_OSPI0_LBCLKO_IN", "Input clock"}, {157, 131, "DEV_BOARD0_OSPI0_LBCLKO_OUT", "Output clock"}, {157, 132, "DEV_BOARD0_RGMII1_RXC_OUT", "Output clock"}, {157, 133, "DEV_BOARD0_RGMII1_TXC_IN", "Input clock"}, {157, 134, "DEV_BOARD0_RGMII1_TXC_OUT", "Output clock"}, {157, 135, "DEV_BOARD0_RGMII2_RXC_OUT", "Output clock"}, {157, 136, "DEV_BOARD0_RGMII2_TXC_IN", "Input clock"}, {157, 137, "DEV_BOARD0_RGMII2_TXC_OUT", "Output clock"}, {157, 138, "DEV_BOARD0_RMII1_REF_CLK_OUT", "Output clock"}, {157, 139, "DEV_BOARD0_RMII2_REF_CLK_OUT", "Output clock"}, {157, 140, "DEV_BOARD0_SPI0_CLK_IN", "Input clock"}, {157, 141, "DEV_BOARD0_SPI0_CLK_OUT", "Output clock"}, {157, 142, "DEV_BOARD0_SPI1_CLK_IN", "Input clock"}, {157, 143, "DEV_BOARD0_SPI1_CLK_OUT", "Output clock"}, {157, 144, "DEV_BOARD0_SPI2_CLK_IN", "Input clock"}, {157, 145, "DEV_BOARD0_SPI2_CLK_OUT", "Output clock"}, {157, 146, "DEV_BOARD0_SYSCLKOUT0_IN", "Input clock"}, {157, 147, "DEV_BOARD0_TCK_OUT", "Output clock"}, {157, 148, "DEV_BOARD0_TIMER_IO0_IN", "Input clock"}, {157, 149, "DEV_BOARD0_TIMER_IO1_IN", "Input clock"}, {157, 150, "DEV_BOARD0_TIMER_IO2_IN", "Input clock"}, {157, 151, "DEV_BOARD0_TIMER_IO3_IN", "Input clock"}, {157, 152, "DEV_BOARD0_TIMER_IO4_IN", "Input clock"}, {157, 153, "DEV_BOARD0_TIMER_IO5_IN", "Input clock"}, {157, 154, "DEV_BOARD0_TIMER_IO6_IN", "Input clock"}, {157, 155, "DEV_BOARD0_TIMER_IO7_IN", "Input clock"}, {157, 156, "DEV_BOARD0_TRC_CLK_IN", "Input clock"}, {157, 157, "DEV_BOARD0_VOUT0_EXTPCLKIN_OUT", "Output clock"}, {157, 158, "DEV_BOARD0_VOUT0_PCLK_IN", "Input clock"}, {157, 159, "DEV_BOARD0_WKUP_CLKOUT0_IN", "Input muxed clock"}, {157, 160, "DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_WKUP_CLKOUT_SEL_OUT0", "Parent input clock option to DEV_BOARD0_WKUP_CLKOUT0_IN"}, {157, 161, "DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_WKUP_CLKOUT0_IN"}, {208, 0, "DEV_C7X256V0_C7XV_CORE_0_C7XV_CLK", "Input clock"}, {211, 0, "DEV_C7X256V0_CLK_C7XV_CLK", "Input clock"}, {211, 1, "DEV_C7X256V0_CLK_C7XV_DIVH_CLK4_OBSCLK_OUT_CLK", "Output clock"}, {211, 2, "DEV_C7X256V0_CLK_DIVH_CLK2_SOC_GCLK", "Output clock"}, {211, 3, "DEV_C7X256V0_CLK_DIVH_CLK4_GCLK", "Output clock"}, {211, 4, "DEV_C7X256V0_CLK_DIVH_CLK4_SOC_GCLK", "Output clock"}, {211, 5, "DEV_C7X256V0_CLK_DIVP_CLK1_GCLK", "Output clock"}, {211, 6, "DEV_C7X256V0_CLK_DIVP_CLK1_SOC_GCLK", "Output clock"}, {211, 7, "DEV_C7X256V0_CLK_PLL_CTRL_CLK", "Input clock"}, {209, 0, "DEV_C7X256V0_CORE0_DIVH_CLK2_SOC_GCLK", "Input clock"}, {209, 1, "DEV_C7X256V0_CORE0_DIVH_CLK4_GCLK", "Input clock"}, {209, 2, "DEV_C7X256V0_CORE0_DIVH_CLK4_SOC_GCLK", "Input clock"}, {209, 3, "DEV_C7X256V0_CORE0_DIVP_CLK1_GCLK", "Input clock"}, {209, 4, "DEV_C7X256V0_CORE0_DIVP_CLK1_SOC_GCLK", "Input clock"}, {206, 0, "DEV_C7XV_RSWS_BS_LIMITER6_CLK_CLK", "Input clock"}, {193, 0, "DEV_CLK_32K_RC_SEL_DEV_VD_CLK", "Input muxed clock"}, {193, 1, "DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_CLK_32K_RC_SEL_DEV_VD_CLK"}, {193, 2, "DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT8", "Parent input clock option to DEV_CLK_32K_RC_SEL_DEV_VD_CLK"}, {193, 3, "DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3_DUP0", "Parent input clock option to DEV_CLK_32K_RC_SEL_DEV_VD_CLK"}, {193, 4, "DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_LFOSC0_CLKOUT", "Parent input clock option to DEV_CLK_32K_RC_SEL_DEV_VD_CLK"}, {1, 0, "DEV_CMP_EVENT_INTROUTER0_INTR_CLK", "Input clock"}, {204, 0, "DEV_CODEC0_VPU_ACLK_CLK", "Input clock"}, {204, 1, "DEV_CODEC0_VPU_BCLK_CLK", "Input clock"}, {204, 2, "DEV_CODEC0_VPU_CCLK_CLK", "Input clock"}, {204, 3, "DEV_CODEC0_VPU_PCLK_CLK", "Input clock"}, {221, 0, "DEV_CODEC_RS_BW_LIMITER2_CLK_CLK", "Input clock"}, {222, 0, "DEV_CODEC_WS_BW_LIMITER3_CLK_CLK", "Input clock"}, {13, 0, "DEV_CPSW0_CPPI_CLK_CLK", "Input clock"}, {13, 1, "DEV_CPSW0_CPTS_GENF0", "Output clock"}, {13, 2, "DEV_CPSW0_CPTS_GENF1", "Output clock"}, {13, 3, "DEV_CPSW0_CPTS_RFT_CLK", "Input muxed clock"}, {13, 4, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {13, 5, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {13, 6, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {13, 8, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {13, 9, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {13, 10, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {13, 11, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"}, {13, 13, "DEV_CPSW0_GMII1_MR_CLK", "Input clock"}, {13, 14, "DEV_CPSW0_GMII1_MT_CLK", "Input clock"}, {13, 15, "DEV_CPSW0_GMII2_MR_CLK", "Input clock"}, {13, 16, "DEV_CPSW0_GMII2_MT_CLK", "Input clock"}, {13, 17, "DEV_CPSW0_GMII_RFT_CLK", "Input clock"}, {13, 18, "DEV_CPSW0_MDIO_MDCLK_O", "Output clock"}, {13, 19, "DEV_CPSW0_RGMII1_RXC_I", "Input clock"}, {13, 20, "DEV_CPSW0_RGMII1_TXC_I", "Input clock"}, {13, 21, "DEV_CPSW0_RGMII1_TXC_O", "Output clock"}, {13, 22, "DEV_CPSW0_RGMII2_RXC_I", "Input clock"}, {13, 23, "DEV_CPSW0_RGMII2_TXC_I", "Input clock"}, {13, 24, "DEV_CPSW0_RGMII2_TXC_O", "Output clock"}, {13, 25, "DEV_CPSW0_RGMII_MHZ_250_CLK", "Input clock"}, {13, 26, "DEV_CPSW0_RGMII_MHZ_50_CLK", "Input clock"}, {13, 27, "DEV_CPSW0_RGMII_MHZ_5_CLK", "Input clock"}, {13, 28, "DEV_CPSW0_RMII1_MHZ_50_CLK", "Input clock"}, {13, 29, "DEV_CPSW0_RMII2_MHZ_50_CLK", "Input clock"}, {195, 0, "DEV_CPT2_AGGR0_VCLK_CLK", "Input clock"}, {194, 0, "DEV_CPT2_AGGR1_VCLK_CLK", "Input clock"}, {182, 0, "DEV_CSI_RX_IF0_MAIN_CLK_CLK", "Input clock"}, {182, 2, "DEV_CSI_RX_IF0_PPI_RX_BYTE_CLK", "Input clock"}, {182, 3, "DEV_CSI_RX_IF0_VBUS_CLK_CLK", "Input clock"}, {182, 4, "DEV_CSI_RX_IF0_VP_CLK_CLK", "Input clock"}, {2, 0, "DEV_DBGSUSPENDROUTER0_INTR_CLK", "Input clock"}, {16, 0, "DEV_DCC0_DCC_CLKSRC0_CLK", "Input clock"}, {16, 1, "DEV_DCC0_DCC_CLKSRC1_CLK", "Input clock"}, {16, 2, "DEV_DCC0_DCC_CLKSRC2_CLK", "Input clock"}, {16, 3, "DEV_DCC0_DCC_CLKSRC3_CLK", "Input clock"}, {16, 4, "DEV_DCC0_DCC_CLKSRC4_CLK", "Input clock"}, {16, 5, "DEV_DCC0_DCC_CLKSRC5_CLK", "Input clock"}, {16, 6, "DEV_DCC0_DCC_CLKSRC6_CLK", "Input clock"}, {16, 7, "DEV_DCC0_DCC_CLKSRC7_CLK", "Input clock"}, {16, 8, "DEV_DCC0_DCC_INPUT00_CLK", "Input clock"}, {16, 9, "DEV_DCC0_DCC_INPUT01_CLK", "Input clock"}, {16, 10, "DEV_DCC0_DCC_INPUT02_CLK", "Input clock"}, {16, 11, "DEV_DCC0_DCC_INPUT10_CLK", "Input clock"}, {16, 12, "DEV_DCC0_VBUS_CLK", "Input clock"}, {17, 0, "DEV_DCC1_DCC_CLKSRC0_CLK", "Input clock"}, {17, 1, "DEV_DCC1_DCC_CLKSRC1_CLK", "Input clock"}, {17, 2, "DEV_DCC1_DCC_CLKSRC2_CLK", "Input clock"}, {17, 3, "DEV_DCC1_DCC_CLKSRC3_CLK", "Input clock"}, {17, 4, "DEV_DCC1_DCC_CLKSRC4_CLK", "Input clock"}, {17, 5, "DEV_DCC1_DCC_CLKSRC5_CLK", "Input clock"}, {17, 6, "DEV_DCC1_DCC_CLKSRC6_CLK", "Input clock"}, {17, 7, "DEV_DCC1_DCC_CLKSRC7_CLK", "Input clock"}, {17, 8, "DEV_DCC1_DCC_INPUT00_CLK", "Input clock"}, {17, 9, "DEV_DCC1_DCC_INPUT01_CLK", "Input clock"}, {17, 10, "DEV_DCC1_DCC_INPUT02_CLK", "Input clock"}, {17, 11, "DEV_DCC1_DCC_INPUT10_CLK", "Input clock"}, {17, 12, "DEV_DCC1_VBUS_CLK", "Input clock"}, {18, 0, "DEV_DCC2_DCC_CLKSRC0_CLK", "Input clock"}, {18, 1, "DEV_DCC2_DCC_CLKSRC1_CLK", "Input clock"}, {18, 2, "DEV_DCC2_DCC_CLKSRC2_CLK", "Input clock"}, {18, 3, "DEV_DCC2_DCC_CLKSRC3_CLK", "Input clock"}, {18, 4, "DEV_DCC2_DCC_CLKSRC4_CLK", "Input clock"}, {18, 5, "DEV_DCC2_DCC_CLKSRC5_CLK", "Input clock"}, {18, 6, "DEV_DCC2_DCC_CLKSRC6_CLK", "Input clock"}, {18, 7, "DEV_DCC2_DCC_CLKSRC7_CLK", "Input clock"}, {18, 8, "DEV_DCC2_DCC_INPUT00_CLK", "Input clock"}, {18, 9, "DEV_DCC2_DCC_INPUT01_CLK", "Input clock"}, {18, 10, "DEV_DCC2_DCC_INPUT02_CLK", "Input clock"}, {18, 11, "DEV_DCC2_DCC_INPUT10_CLK", "Input clock"}, {18, 12, "DEV_DCC2_VBUS_CLK", "Input clock"}, {19, 0, "DEV_DCC3_DCC_CLKSRC0_CLK", "Input clock"}, {19, 1, "DEV_DCC3_DCC_CLKSRC1_CLK", "Input clock"}, {19, 2, "DEV_DCC3_DCC_CLKSRC2_CLK", "Input clock"}, {19, 3, "DEV_DCC3_DCC_CLKSRC3_CLK", "Input clock"}, {19, 4, "DEV_DCC3_DCC_CLKSRC4_CLK", "Input clock"}, {19, 5, "DEV_DCC3_DCC_CLKSRC5_CLK", "Input clock"}, {19, 6, "DEV_DCC3_DCC_CLKSRC6_CLK", "Input clock"}, {19, 7, "DEV_DCC3_DCC_CLKSRC7_CLK", "Input clock"}, {19, 8, "DEV_DCC3_DCC_INPUT00_CLK", "Input clock"}, {19, 9, "DEV_DCC3_DCC_INPUT01_CLK", "Input clock"}, {19, 10, "DEV_DCC3_DCC_INPUT02_CLK", "Input clock"}, {19, 11, "DEV_DCC3_DCC_INPUT10_CLK", "Input clock"}, {19, 12, "DEV_DCC3_VBUS_CLK", "Input clock"}, {20, 0, "DEV_DCC4_DCC_CLKSRC0_CLK", "Input clock"}, {20, 1, "DEV_DCC4_DCC_CLKSRC1_CLK", "Input clock"}, {20, 2, "DEV_DCC4_DCC_CLKSRC2_CLK", "Input clock"}, {20, 3, "DEV_DCC4_DCC_CLKSRC3_CLK", "Input clock"}, {20, 4, "DEV_DCC4_DCC_CLKSRC4_CLK", "Input clock"}, {20, 5, "DEV_DCC4_DCC_CLKSRC5_CLK", "Input clock"}, {20, 6, "DEV_DCC4_DCC_CLKSRC6_CLK", "Input clock"}, {20, 7, "DEV_DCC4_DCC_CLKSRC7_CLK", "Input clock"}, {20, 8, "DEV_DCC4_DCC_INPUT00_CLK", "Input clock"}, {20, 9, "DEV_DCC4_DCC_INPUT01_CLK", "Input clock"}, {20, 10, "DEV_DCC4_DCC_INPUT02_CLK", "Input clock"}, {20, 11, "DEV_DCC4_DCC_INPUT10_CLK", "Input clock"}, {20, 12, "DEV_DCC4_VBUS_CLK", "Input clock"}, {21, 0, "DEV_DCC5_DCC_CLKSRC0_CLK", "Input clock"}, {21, 2, "DEV_DCC5_DCC_CLKSRC2_CLK", "Input clock"}, {21, 3, "DEV_DCC5_DCC_CLKSRC3_CLK", "Input clock"}, {21, 4, "DEV_DCC5_DCC_CLKSRC4_CLK", "Input clock"}, {21, 5, "DEV_DCC5_DCC_CLKSRC5_CLK", "Input clock"}, {21, 6, "DEV_DCC5_DCC_CLKSRC6_CLK", "Input clock"}, {21, 7, "DEV_DCC5_DCC_CLKSRC7_CLK", "Input clock"}, {21, 8, "DEV_DCC5_DCC_INPUT00_CLK", "Input clock"}, {21, 9, "DEV_DCC5_DCC_INPUT01_CLK", "Input clock"}, {21, 10, "DEV_DCC5_DCC_INPUT02_CLK", "Input clock"}, {21, 11, "DEV_DCC5_DCC_INPUT10_CLK", "Input clock"}, {21, 12, "DEV_DCC5_VBUS_CLK", "Input clock"}, {183, 0, "DEV_DCC6_DCC_CLKSRC0_CLK", "Input clock"}, {183, 1, "DEV_DCC6_DCC_CLKSRC1_CLK", "Input clock"}, {183, 2, "DEV_DCC6_DCC_CLKSRC2_CLK", "Input clock"}, {183, 3, "DEV_DCC6_DCC_CLKSRC3_CLK", "Input clock"}, {183, 4, "DEV_DCC6_DCC_CLKSRC4_CLK", "Input clock"}, {183, 5, "DEV_DCC6_DCC_CLKSRC5_CLK", "Input clock"}, {183, 6, "DEV_DCC6_DCC_CLKSRC6_CLK", "Input clock"}, {183, 7, "DEV_DCC6_DCC_CLKSRC7_CLK", "Input clock"}, {183, 8, "DEV_DCC6_DCC_INPUT00_CLK", "Input clock"}, {183, 9, "DEV_DCC6_DCC_INPUT01_CLK", "Input clock"}, {183, 10, "DEV_DCC6_DCC_INPUT02_CLK", "Input clock"}, {183, 11, "DEV_DCC6_DCC_INPUT10_CLK", "Input clock"}, {183, 12, "DEV_DCC6_VBUS_CLK", "Input clock"}, {85, 0, "DEV_DDPA0_DDPA_CLK", "Input clock"}, {170, 0, "DEV_DDR32SS0_DDR_PLL_DIVH_CLK4_OBSCLK_OUT_CLK", "Output clock"}, {170, 1, "DEV_DDR32SS0_DDRSS_DDR_PLL_CLK", "Input clock"}, {170, 2, "DEV_DDR32SS0_DDRSS_TCK", "Input clock"}, {170, 3, "DEV_DDR32SS0_PLL_CTRL_CLK", "Input clock"}, {171, 0, "DEV_DEBUGSS0_CFG_CLK", "Input clock"}, {171, 1, "DEV_DEBUGSS0_DBG_CLK", "Input clock"}, {171, 2, "DEV_DEBUGSS0_SYS_CLK", "Input clock"}, {24, 0, "DEV_DEBUGSS_WRAP0_ATB_CLK", "Input clock"}, {24, 1, "DEV_DEBUGSS_WRAP0_CORE_CLK", "Input clock"}, {24, 2, "DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK", "Output clock"}, {24, 20, "DEV_DEBUGSS_WRAP0_JTAG_TCK", "Input clock"}, {24, 21, "DEV_DEBUGSS_WRAP0_P1500_WRCK", "Input clock"}, {24, 22, "DEV_DEBUGSS_WRAP0_TREXPT_CLK", "Input clock"}, {26, 0, "DEV_DMASS0_BCDMA_0_CLK", "Input clock"}, {27, 0, "DEV_DMASS0_CBASS_0_CLK", "Input clock"}, {28, 0, "DEV_DMASS0_INTAGGR_0_CLK", "Input clock"}, {29, 0, "DEV_DMASS0_IPCSS_0_CLK", "Input clock"}, {30, 0, "DEV_DMASS0_PKTDMA_0_CLK", "Input clock"}, {33, 0, "DEV_DMASS0_RINGACC_0_CLK", "Input clock"}, {199, 0, "DEV_DMASS1_BCDMA_0_CLK", "Input clock"}, {200, 0, "DEV_DMASS1_INTAGGR_0_CLK", "Input clock"}, {185, 2, "DEV_DPHY_RX0_IO_RX_CL_L_M", "Input clock"}, {185, 2, "DEV_DPHY_RX0_IO_RX_CL_L_M", "Output clock"}, {185, 3, "DEV_DPHY_RX0_IO_RX_CL_L_P", "Input clock"}, {185, 3, "DEV_DPHY_RX0_IO_RX_CL_L_P", "Output clock"}, {185, 4, "DEV_DPHY_RX0_JTAG_TCK", "Input clock"}, {185, 5, "DEV_DPHY_RX0_MAIN_CLK_CLK", "Input clock"}, {185, 6, "DEV_DPHY_RX0_PPI_RX_BYTE_CLK", "Output clock"}, {186, 0, "DEV_DSS0_DPI_0_IN_CLK", "Input clock"}, {186, 2, "DEV_DSS0_DPI_1_IN_CLK", "Input muxed clock"}, {186, 3, "DEV_DSS0_DPI_1_IN_CLK_PARENT_HSDIV0_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DPI_1_IN_CLK"}, {186, 4, "DEV_DSS0_DPI_1_IN_CLK_PARENT_BOARD_0_VOUT0_EXTPCLKIN_OUT", "Parent input clock option to DEV_DSS0_DPI_1_IN_CLK"}, {186, 5, "DEV_DSS0_DPI_1_OUT_CLK", "Output clock"}, {186, 6, "DEV_DSS0_DSS_FUNC_CLK", "Input clock"}, {51, 0, "DEV_ECAP0_VBUS_CLK", "Input clock"}, {52, 0, "DEV_ECAP1_VBUS_CLK", "Input clock"}, {53, 0, "DEV_ECAP2_VBUS_CLK", "Input clock"}, {54, 0, "DEV_ELM0_VBUSP_CLK", "Input clock"}, {86, 0, "DEV_EPWM0_VBUSP_CLK", "Input clock"}, {87, 0, "DEV_EPWM1_VBUSP_CLK", "Input clock"}, {88, 0, "DEV_EPWM2_VBUSP_CLK", "Input clock"}, {59, 0, "DEV_EQEP0_VBUS_CLK", "Input clock"}, {60, 0, "DEV_EQEP1_VBUS_CLK", "Input clock"}, {62, 0, "DEV_EQEP2_VBUS_CLK", "Input clock"}, {63, 0, "DEV_ESM0_CLK", "Input clock"}, {74, 0, "DEV_FSS0_FSAS_0_GCLK", "Input clock"}, {75, 0, "DEV_FSS0_OSPI_0_OSPI_DQS_CLK", "Input clock"}, {75, 1, "DEV_FSS0_OSPI_0_OSPI_HCLK_CLK", "Input clock"}, {75, 2, "DEV_FSS0_OSPI_0_OSPI_ICLK_CLK", "Input muxed clock"}, {75, 3, "DEV_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI0_DQS_OUT", "Parent input clock option to DEV_FSS0_OSPI_0_OSPI_ICLK_CLK"}, {75, 4, "DEV_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI0_LBCLKO_OUT", "Parent input clock option to DEV_FSS0_OSPI_0_OSPI_ICLK_CLK"}, {75, 5, "DEV_FSS0_OSPI_0_OSPI_OCLK_CLK", "Output clock"}, {75, 6, "DEV_FSS0_OSPI_0_OSPI_PCLK_CLK", "Input clock"}, {75, 7, "DEV_FSS0_OSPI_0_OSPI_RCLK_CLK", "Input muxed clock"}, {75, 8, "DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_FSS0_OSPI_0_OSPI_RCLK_CLK"}, {75, 9, "DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT5_CLK", "Parent input clock option to DEV_FSS0_OSPI_0_OSPI_RCLK_CLK"}, {76, 0, "DEV_GICSS0_VCLK_CLK", "Input clock"}, {77, 0, "DEV_GPIO0_MMR_CLK", "Input clock"}, {78, 0, "DEV_GPIO1_MMR_CLK", "Input clock"}, {80, 0, "DEV_GPMC0_FUNC_CLK", "Input muxed clock"}, {80, 1, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_GPMC0_FUNC_CLK"}, {80, 2, "DEV_GPMC0_FUNC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK", "Parent input clock option to DEV_GPMC0_FUNC_CLK"}, {80, 3, "DEV_GPMC0_PI_GPMC_RET_CLK", "Input clock"}, {80, 4, "DEV_GPMC0_PO_GPMC_DEV_CLK", "Output clock"}, {80, 5, "DEV_GPMC0_VBUSM_CLK", "Input clock"}, {225, 0, "DEV_HSM0_DAP_CLK", "Input clock"}, {102, 0, "DEV_I2C0_CLK", "Input clock"}, {102, 1, "DEV_I2C0_PISCL", "Input clock"}, {102, 2, "DEV_I2C0_PISYS_CLK", "Input clock"}, {102, 3, "DEV_I2C0_PORSCL", "Output clock"}, {103, 0, "DEV_I2C1_CLK", "Input clock"}, {103, 1, "DEV_I2C1_PISCL", "Input clock"}, {103, 2, "DEV_I2C1_PISYS_CLK", "Input clock"}, {103, 3, "DEV_I2C1_PORSCL", "Output clock"}, {104, 0, "DEV_I2C2_CLK", "Input clock"}, {104, 1, "DEV_I2C2_PISCL", "Input clock"}, {104, 2, "DEV_I2C2_PISYS_CLK", "Input clock"}, {104, 3, "DEV_I2C2_PORSCL", "Output clock"}, {105, 0, "DEV_I2C3_CLK", "Input clock"}, {105, 1, "DEV_I2C3_PISCL", "Input clock"}, {105, 2, "DEV_I2C3_PISYS_CLK", "Input clock"}, {105, 3, "DEV_I2C3_PORSCL", "Output clock"}, {201, 0, "DEV_JPGENC0_CORE_CLK", "Input clock"}, {215, 0, "DEV_JPGENC_RS_BW_LIMITER4_CLK_CLK", "Input clock"}, {216, 0, "DEV_JPGENC_WS_BW_LIMITER5_CLK_CLK", "Input clock"}, {83, 1, "DEV_LED0_VBUS_CLK", "Input clock"}, {3, 0, "DEV_MAIN_GPIOMUX_INTROUTER0_INTR_CLK", "Input clock"}, {98, 1, "DEV_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"}, {98, 2, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, {98, 3, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, {98, 4, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, {98, 5, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"}, {98, 6, "DEV_MCAN0_MCANSS_HCLK_CLK", "Input clock"}, {190, 0, "DEV_MCASP0_AUX_CLK", "Input muxed clock"}, {190, 1, "DEV_MCASP0_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, {190, 2, "DEV_MCASP0_AUX_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"}, {190, 3, "DEV_MCASP0_MCASP_ACLKR_PIN", "Input clock"}, {190, 4, "DEV_MCASP0_MCASP_ACLKR_POUT", "Output clock"}, {190, 5, "DEV_MCASP0_MCASP_ACLKX_PIN", "Input clock"}, {190, 6, "DEV_MCASP0_MCASP_ACLKX_POUT", "Output clock"}, {190, 7, "DEV_MCASP0_MCASP_AFSR_POUT", "Output clock"}, {190, 8, "DEV_MCASP0_MCASP_AFSX_POUT", "Output clock"}, {190, 9, "DEV_MCASP0_MCASP_AHCLKR_PIN", "Input muxed clock"}, {190, 10, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {190, 11, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {190, 12, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {190, 13, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"}, {190, 14, "DEV_MCASP0_MCASP_AHCLKR_POUT", "Output clock"}, {190, 15, "DEV_MCASP0_MCASP_AHCLKX_PIN", "Input muxed clock"}, {190, 16, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {190, 17, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {190, 18, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {190, 19, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"}, {190, 20, "DEV_MCASP0_MCASP_AHCLKX_POUT", "Output clock"}, {190, 21, "DEV_MCASP0_VBUSP_CLK", "Input clock"}, {191, 0, "DEV_MCASP1_AUX_CLK", "Input muxed clock"}, {191, 1, "DEV_MCASP1_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, {191, 2, "DEV_MCASP1_AUX_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"}, {191, 3, "DEV_MCASP1_MCASP_ACLKR_PIN", "Input clock"}, {191, 4, "DEV_MCASP1_MCASP_ACLKR_POUT", "Output clock"}, {191, 5, "DEV_MCASP1_MCASP_ACLKX_PIN", "Input clock"}, {191, 6, "DEV_MCASP1_MCASP_ACLKX_POUT", "Output clock"}, {191, 7, "DEV_MCASP1_MCASP_AFSR_POUT", "Output clock"}, {191, 8, "DEV_MCASP1_MCASP_AFSX_POUT", "Output clock"}, {191, 9, "DEV_MCASP1_MCASP_AHCLKR_PIN", "Input muxed clock"}, {191, 10, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {191, 11, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {191, 12, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {191, 13, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"}, {191, 14, "DEV_MCASP1_MCASP_AHCLKR_POUT", "Output clock"}, {191, 15, "DEV_MCASP1_MCASP_AHCLKX_PIN", "Input muxed clock"}, {191, 16, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {191, 17, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {191, 18, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {191, 19, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"}, {191, 20, "DEV_MCASP1_MCASP_AHCLKX_POUT", "Output clock"}, {191, 21, "DEV_MCASP1_VBUSP_CLK", "Input clock"}, {192, 0, "DEV_MCASP2_AUX_CLK", "Input muxed clock"}, {192, 1, "DEV_MCASP2_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, {192, 2, "DEV_MCASP2_AUX_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"}, {192, 3, "DEV_MCASP2_MCASP_ACLKR_PIN", "Input clock"}, {192, 4, "DEV_MCASP2_MCASP_ACLKR_POUT", "Output clock"}, {192, 5, "DEV_MCASP2_MCASP_ACLKX_PIN", "Input clock"}, {192, 6, "DEV_MCASP2_MCASP_ACLKX_POUT", "Output clock"}, {192, 7, "DEV_MCASP2_MCASP_AFSR_POUT", "Output clock"}, {192, 8, "DEV_MCASP2_MCASP_AFSX_POUT", "Output clock"}, {192, 9, "DEV_MCASP2_MCASP_AHCLKR_PIN", "Input muxed clock"}, {192, 10, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {192, 11, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {192, 12, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {192, 13, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"}, {192, 14, "DEV_MCASP2_MCASP_AHCLKR_POUT", "Output clock"}, {192, 15, "DEV_MCASP2_MCASP_AHCLKX_PIN", "Input muxed clock"}, {192, 16, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {192, 17, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {192, 18, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {192, 19, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"}, {192, 20, "DEV_MCASP2_MCASP_AHCLKX_POUT", "Output clock"}, {192, 21, "DEV_MCASP2_VBUSP_CLK", "Input clock"}, {116, 0, "DEV_MCRC64_0_CLK", "Input clock"}, {141, 0, "DEV_MCSPI0_CLKSPIREF_CLK", "Input clock"}, {141, 2, "DEV_MCSPI0_IO_CLKSPIO_CLK", "Output clock"}, {141, 3, "DEV_MCSPI0_VBUSP_CLK", "Input clock"}, {141, 4, "DEV_MCSPI0_IO_CLKSPII_CLK", "Input muxed clock"}, {141, 5, "DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI0_CLK_OUT", "Parent input clock option to DEV_MCSPI0_IO_CLKSPII_CLK"}, {141, 6, "DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MAIN_0_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI0_IO_CLKSPII_CLK"}, {142, 0, "DEV_MCSPI1_CLKSPIREF_CLK", "Input clock"}, {142, 2, "DEV_MCSPI1_IO_CLKSPIO_CLK", "Output clock"}, {142, 3, "DEV_MCSPI1_VBUSP_CLK", "Input clock"}, {142, 4, "DEV_MCSPI1_IO_CLKSPII_CLK", "Input muxed clock"}, {142, 5, "DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI1_CLK_OUT", "Parent input clock option to DEV_MCSPI1_IO_CLKSPII_CLK"}, {142, 6, "DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_1_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI1_IO_CLKSPII_CLK"}, {143, 0, "DEV_MCSPI2_CLKSPIREF_CLK", "Input clock"}, {143, 2, "DEV_MCSPI2_IO_CLKSPIO_CLK", "Output clock"}, {143, 3, "DEV_MCSPI2_VBUSP_CLK", "Input clock"}, {143, 4, "DEV_MCSPI2_IO_CLKSPII_CLK", "Input muxed clock"}, {143, 5, "DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI2_CLK_OUT", "Parent input clock option to DEV_MCSPI2_IO_CLKSPII_CLK"}, {143, 6, "DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_SPI_MAIN_2_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI2_IO_CLKSPII_CLK"}, {196, 0, "DEV_MCU_CPT2_AGGR0_VCLK_CLK", "Input clock"}, {23, 0, "DEV_MCU_DCC0_DCC_CLKSRC0_CLK", "Input clock"}, {23, 1, "DEV_MCU_DCC0_DCC_CLKSRC1_CLK", "Input clock"}, {23, 2, "DEV_MCU_DCC0_DCC_CLKSRC2_CLK", "Input clock"}, {23, 3, "DEV_MCU_DCC0_DCC_CLKSRC3_CLK", "Input clock"}, {23, 4, "DEV_MCU_DCC0_DCC_CLKSRC4_CLK", "Input clock"}, {23, 5, "DEV_MCU_DCC0_DCC_CLKSRC5_CLK", "Input clock"}, {23, 6, "DEV_MCU_DCC0_DCC_CLKSRC6_CLK", "Input clock"}, {23, 7, "DEV_MCU_DCC0_DCC_CLKSRC7_CLK", "Input clock"}, {23, 8, "DEV_MCU_DCC0_DCC_INPUT00_CLK", "Input clock"}, {23, 9, "DEV_MCU_DCC0_DCC_INPUT01_CLK", "Input clock"}, {23, 10, "DEV_MCU_DCC0_DCC_INPUT02_CLK", "Input clock"}, {23, 11, "DEV_MCU_DCC0_DCC_INPUT10_CLK", "Input clock"}, {23, 12, "DEV_MCU_DCC0_VBUS_CLK", "Input clock"}, {197, 0, "DEV_MCU_DCC1_DCC_CLKSRC0_CLK", "Input clock"}, {197, 1, "DEV_MCU_DCC1_DCC_CLKSRC1_CLK", "Input clock"}, {197, 5, "DEV_MCU_DCC1_DCC_CLKSRC5_CLK", "Input clock"}, {197, 6, "DEV_MCU_DCC1_DCC_CLKSRC6_CLK", "Input clock"}, {197, 7, "DEV_MCU_DCC1_DCC_CLKSRC7_CLK", "Input clock"}, {197, 8, "DEV_MCU_DCC1_DCC_INPUT00_CLK", "Input clock"}, {197, 9, "DEV_MCU_DCC1_DCC_INPUT01_CLK", "Input clock"}, {197, 10, "DEV_MCU_DCC1_DCC_INPUT02_CLK", "Input clock"}, {197, 11, "DEV_MCU_DCC1_DCC_INPUT10_CLK", "Input clock"}, {197, 12, "DEV_MCU_DCC1_VBUS_CLK", "Input clock"}, {79, 0, "DEV_MCU_GPIO0_MMR_CLK", "Input muxed clock"}, {79, 1, "DEV_MCU_GPIO0_MMR_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_MCU_GPIO0_MMR_CLK"}, {79, 2, "DEV_MCU_GPIO0_MMR_CLK_PARENT_GLUELOGIC_LFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_GPIO0_MMR_CLK"}, {79, 3, "DEV_MCU_GPIO0_MMR_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_MCU_GPIO0_MMR_CLK"}, {79, 4, "DEV_MCU_GPIO0_MMR_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_GPIO0_MMR_CLK"}, {106, 0, "DEV_MCU_I2C0_CLK", "Input clock"}, {106, 1, "DEV_MCU_I2C0_PISCL", "Input clock"}, {106, 2, "DEV_MCU_I2C0_PISYS_CLK", "Input clock"}, {106, 3, "DEV_MCU_I2C0_PORSCL", "Output clock"}, {188, 1, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"}, {188, 2, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, {188, 3, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, {188, 4, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, {188, 5, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT_DUP0", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"}, {188, 6, "DEV_MCU_MCAN0_MCANSS_HCLK_CLK", "Input clock"}, {189, 1, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"}, {189, 2, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, {189, 3, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, {189, 4, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, {189, 5, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT_DUP0", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"}, {189, 6, "DEV_MCU_MCAN1_MCANSS_HCLK_CLK", "Input clock"}, {100, 0, "DEV_MCU_MCRC64_0_CLK", "Input clock"}, {147, 0, "DEV_MCU_MCSPI0_CLKSPIREF_CLK", "Input clock"}, {147, 2, "DEV_MCU_MCSPI0_IO_CLKSPIO_CLK", "Output clock"}, {147, 3, "DEV_MCU_MCSPI0_VBUSP_CLK", "Input clock"}, {147, 4, "DEV_MCU_MCSPI0_IO_CLKSPII_CLK", "Input muxed clock"}, {147, 5, "DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI0_CLK_OUT", "Parent input clock option to DEV_MCU_MCSPI0_IO_CLKSPII_CLK"}, {147, 6, "DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MCU_0_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCU_MCSPI0_IO_CLKSPII_CLK"}, {148, 0, "DEV_MCU_MCSPI1_CLKSPIREF_CLK", "Input clock"}, {148, 2, "DEV_MCU_MCSPI1_IO_CLKSPIO_CLK", "Output clock"}, {148, 3, "DEV_MCU_MCSPI1_VBUSP_CLK", "Input clock"}, {148, 4, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK", "Input muxed clock"}, {148, 5, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI1_CLK_OUT", "Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK"}, {148, 6, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MCU_1_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK"}, {180, 3, "DEV_MCU_MCU_16FF0_PLL_CTRL_MCU_CLK24_CLK", "Input clock"}, {227, 0, "DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK", "Input muxed clock"}, {227, 1, "DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK"}, {227, 2, "DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK"}, {227, 3, "DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK"}, {227, 4, "DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK_DUP0", "Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK"}, {227, 5, "DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK"}, {227, 6, "DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK"}, {227, 7, "DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT8", "Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK"}, {227, 8, "DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK"}, {227, 9, "DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK"}, {203, 7, "DEV_MCU_PBIST0_CLK8_CLK", "Input clock"}, {9, 0, "DEV_MCU_R5FSS0_CORE0_CPU0_CLK", "Input clock"}, {9, 1, "DEV_MCU_R5FSS0_CORE0_INTERFACE0_CLK", "Input clock"}, {131, 0, "DEV_MCU_RTI0_RTI_CLK", "Input muxed clock"}, {131, 1, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, {131, 2, "DEV_MCU_RTI0_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, {131, 3, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, {131, 4, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"}, {131, 5, "DEV_MCU_RTI0_VBUSP_CLK", "Input clock"}, {35, 0, "DEV_MCU_TIMER0_TIMER_HCLK_CLK", "Input clock"}, {35, 1, "DEV_MCU_TIMER0_TIMER_PWM", "Output clock"}, {35, 2, "DEV_MCU_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"}, {35, 3, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 4, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 5, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 6, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV1_16FFT_MCU_0_HSDIVOUT5_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 7, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 8, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 9, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {35, 10, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"}, {48, 0, "DEV_MCU_TIMER1_TIMER_HCLK_CLK", "Input clock"}, {48, 1, "DEV_MCU_TIMER1_TIMER_PWM", "Output clock"}, {48, 2, "DEV_MCU_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"}, {48, 3, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMERCLKN_SEL_OUT1", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, {48, 4, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"}, {49, 0, "DEV_MCU_TIMER2_TIMER_HCLK_CLK", "Input clock"}, {49, 1, "DEV_MCU_TIMER2_TIMER_PWM", "Output clock"}, {49, 2, "DEV_MCU_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"}, {49, 3, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {49, 4, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {49, 5, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {49, 6, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV1_16FFT_MCU_0_HSDIVOUT5_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {49, 7, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {49, 8, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {49, 9, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {49, 10, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"}, {50, 0, "DEV_MCU_TIMER3_TIMER_HCLK_CLK", "Input clock"}, {50, 1, "DEV_MCU_TIMER3_TIMER_PWM", "Output clock"}, {50, 2, "DEV_MCU_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"}, {50, 3, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMERCLKN_SEL_OUT3", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, {50, 4, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"}, {149, 0, "DEV_MCU_UART0_FCLK_CLK", "Input clock"}, {149, 3, "DEV_MCU_UART0_VBUSP_CLK", "Input clock"}, {57, 0, "DEV_MMCSD0_EMMCSDSS_IO_CLK_I", "Input muxed clock"}, {57, 1, "DEV_MMCSD0_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC0_CLKLB_OUT", "Parent input clock option to DEV_MMCSD0_EMMCSDSS_IO_CLK_I"}, {57, 2, "DEV_MMCSD0_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC0_CLK_OUT", "Parent input clock option to DEV_MMCSD0_EMMCSDSS_IO_CLK_I"}, {57, 3, "DEV_MMCSD0_EMMCSDSS_IO_CLK_O", "Output clock"}, {57, 5, "DEV_MMCSD0_EMMCSDSS_VBUS_CLK", "Input clock"}, {57, 6, "DEV_MMCSD0_EMMCSDSS_XIN_CLK", "Input muxed clock"}, {57, 7, "DEV_MMCSD0_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSDSS_XIN_CLK"}, {57, 8, "DEV_MMCSD0_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSDSS_XIN_CLK"}, {58, 0, "DEV_MMCSD1_EMMCSDSS_IO_CLK_I", "Input muxed clock"}, {58, 1, "DEV_MMCSD1_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC1_CLKLB_OUT", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_IO_CLK_I"}, {58, 2, "DEV_MMCSD1_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC1_CLK_OUT", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_IO_CLK_I"}, {58, 3, "DEV_MMCSD1_EMMCSDSS_IO_CLK_O", "Output clock"}, {58, 5, "DEV_MMCSD1_EMMCSDSS_VBUS_CLK", "Input clock"}, {58, 6, "DEV_MMCSD1_EMMCSDSS_XIN_CLK", "Input muxed clock"}, {58, 7, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"}, {58, 8, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"}, {184, 0, "DEV_MMCSD2_EMMCSDSS_IO_CLK_I", "Input muxed clock"}, {184, 1, "DEV_MMCSD2_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC2_CLKLB_OUT", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_IO_CLK_I"}, {184, 2, "DEV_MMCSD2_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC2_CLK_OUT", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_IO_CLK_I"}, {184, 3, "DEV_MMCSD2_EMMCSDSS_IO_CLK_O", "Output clock"}, {184, 5, "DEV_MMCSD2_EMMCSDSS_VBUS_CLK", "Input clock"}, {184, 6, "DEV_MMCSD2_EMMCSDSS_XIN_CLK", "Input muxed clock"}, {184, 7, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"}, {184, 8, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"}, {228, 0, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK", "Input muxed clock"}, {228, 1, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 2, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 3, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 4, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 5, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 6, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 7, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV0_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 8, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 9, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 10, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_5_HSDIVOUT0_CLK", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 11, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_SAM62A_C7XV_WRAP_MAIN_0_CLOCK_CONTROL_0_C7XV_DIVH_CLK4_OBSCLK_", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 12, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 13, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_SAM62A_A53_512KB_WRAP_MAIN_0_ARM_COREPACK_0_A53_DIVH_CLK4_OBSC", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 14, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_SAM62A_DDR_WRAP_MAIN_0_DDR_PLL_DIVH_CLK4_OBSCLK_OUT_CLK", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 15, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 16, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT8", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 17, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 18, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {228, 19, "DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK"}, {163, 7, "DEV_PBIST0_CLK8_CLK", "Input clock"}, {163, 9, "DEV_PBIST0_TCLK_CLK", "Input clock"}, {220, 1, "DEV_PBIST3_CLK8_CLK", "Input clock"}, {169, 0, "DEV_PSC0_CLK", "Input clock"}, {169, 1, "DEV_PSC0_SLOW_CLK", "Input clock"}, {168, 0, "DEV_PSC0_FW_0_CLK", "Input clock"}, {125, 0, "DEV_RTI0_RTI_CLK", "Input muxed clock"}, {125, 1, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {125, 2, "DEV_RTI0_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {125, 3, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {125, 4, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_RTI0_RTI_CLK"}, {125, 5, "DEV_RTI0_VBUSP_CLK", "Input clock"}, {126, 0, "DEV_RTI1_RTI_CLK", "Input muxed clock"}, {126, 1, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {126, 2, "DEV_RTI1_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {126, 3, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {126, 4, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_RTI1_RTI_CLK"}, {126, 5, "DEV_RTI1_VBUSP_CLK", "Input clock"}, {127, 0, "DEV_RTI2_RTI_CLK", "Input muxed clock"}, {127, 1, "DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI2_RTI_CLK"}, {127, 2, "DEV_RTI2_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_RTI2_RTI_CLK"}, {127, 3, "DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI2_RTI_CLK"}, {127, 4, "DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_RTI2_RTI_CLK"}, {127, 5, "DEV_RTI2_VBUSP_CLK", "Input clock"}, {128, 0, "DEV_RTI3_RTI_CLK", "Input muxed clock"}, {128, 1, "DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI3_RTI_CLK"}, {128, 2, "DEV_RTI3_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_RTI3_RTI_CLK"}, {128, 3, "DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI3_RTI_CLK"}, {128, 4, "DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_RTI3_RTI_CLK"}, {128, 5, "DEV_RTI3_VBUSP_CLK", "Input clock"}, {205, 0, "DEV_RTI4_RTI_CLK", "Input muxed clock"}, {205, 1, "DEV_RTI4_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI4_RTI_CLK"}, {205, 2, "DEV_RTI4_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_RTI4_RTI_CLK"}, {205, 3, "DEV_RTI4_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI4_RTI_CLK"}, {205, 4, "DEV_RTI4_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_RTI4_RTI_CLK"}, {205, 5, "DEV_RTI4_VBUSP_CLK", "Input clock"}, {150, 0, "DEV_SPINLOCK0_VCLK_CLK", "Input clock"}, {15, 0, "DEV_STM0_ATB_CLK", "Input clock"}, {15, 1, "DEV_STM0_CORE_CLK", "Input clock"}, {15, 2, "DEV_STM0_VBUSP_CLK", "Input clock"}, {36, 0, "DEV_TIMER0_TIMER_HCLK_CLK", "Input clock"}, {36, 1, "DEV_TIMER0_TIMER_PWM", "Output clock"}, {36, 2, "DEV_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"}, {36, 3, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 4, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 5, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 6, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 7, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 8, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 10, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 11, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 12, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 13, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 14, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {36, 15, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_5_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"}, {37, 0, "DEV_TIMER1_TIMER_HCLK_CLK", "Input clock"}, {37, 1, "DEV_TIMER1_TIMER_PWM", "Output clock"}, {37, 2, "DEV_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"}, {37, 3, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT1", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {37, 4, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"}, {38, 0, "DEV_TIMER2_TIMER_HCLK_CLK", "Input clock"}, {38, 1, "DEV_TIMER2_TIMER_PWM", "Output clock"}, {38, 2, "DEV_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"}, {38, 3, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 4, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 5, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 6, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 7, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 8, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 10, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 11, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 12, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 13, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 14, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {38, 15, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_5_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"}, {39, 0, "DEV_TIMER3_TIMER_HCLK_CLK", "Input clock"}, {39, 1, "DEV_TIMER3_TIMER_PWM", "Output clock"}, {39, 2, "DEV_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"}, {39, 3, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT3", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {39, 4, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"}, {40, 0, "DEV_TIMER4_TIMER_HCLK_CLK", "Input clock"}, {40, 1, "DEV_TIMER4_TIMER_PWM", "Output clock"}, {40, 2, "DEV_TIMER4_TIMER_TCLK_CLK", "Input muxed clock"}, {40, 3, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 4, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 5, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 6, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 7, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 8, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 10, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 11, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 12, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 13, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 14, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {40, 15, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_5_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"}, {41, 0, "DEV_TIMER5_TIMER_HCLK_CLK", "Input clock"}, {41, 1, "DEV_TIMER5_TIMER_PWM", "Output clock"}, {41, 2, "DEV_TIMER5_TIMER_TCLK_CLK", "Input muxed clock"}, {41, 3, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT5", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {41, 4, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"}, {42, 0, "DEV_TIMER6_TIMER_HCLK_CLK", "Input clock"}, {42, 1, "DEV_TIMER6_TIMER_PWM", "Output clock"}, {42, 2, "DEV_TIMER6_TIMER_TCLK_CLK", "Input muxed clock"}, {42, 3, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 4, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 5, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 6, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 7, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 8, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 10, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 11, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 12, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 13, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 14, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {42, 15, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_5_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"}, {43, 0, "DEV_TIMER7_TIMER_HCLK_CLK", "Input clock"}, {43, 1, "DEV_TIMER7_TIMER_PWM", "Output clock"}, {43, 2, "DEV_TIMER7_TIMER_TCLK_CLK", "Input muxed clock"}, {43, 3, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT7", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {43, 4, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"}, {6, 0, "DEV_TIMESYNC_EVENT_ROUTER0_INTR_CLK", "Input clock"}, {146, 0, "DEV_UART0_FCLK_CLK", "Input muxed clock"}, {146, 1, "DEV_UART0_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT0", "Parent input clock option to DEV_UART0_FCLK_CLK"}, {146, 2, "DEV_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART0_FCLK_CLK"}, {146, 5, "DEV_UART0_VBUSP_CLK", "Input clock"}, {152, 0, "DEV_UART1_FCLK_CLK", "Input muxed clock"}, {152, 1, "DEV_UART1_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT1", "Parent input clock option to DEV_UART1_FCLK_CLK"}, {152, 2, "DEV_UART1_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART1_FCLK_CLK"}, {152, 5, "DEV_UART1_VBUSP_CLK", "Input clock"}, {153, 0, "DEV_UART2_FCLK_CLK", "Input muxed clock"}, {153, 1, "DEV_UART2_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT2", "Parent input clock option to DEV_UART2_FCLK_CLK"}, {153, 2, "DEV_UART2_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART2_FCLK_CLK"}, {153, 5, "DEV_UART2_VBUSP_CLK", "Input clock"}, {154, 0, "DEV_UART3_FCLK_CLK", "Input muxed clock"}, {154, 1, "DEV_UART3_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT3", "Parent input clock option to DEV_UART3_FCLK_CLK"}, {154, 2, "DEV_UART3_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART3_FCLK_CLK"}, {154, 5, "DEV_UART3_VBUSP_CLK", "Input clock"}, {155, 0, "DEV_UART4_FCLK_CLK", "Input muxed clock"}, {155, 1, "DEV_UART4_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT4", "Parent input clock option to DEV_UART4_FCLK_CLK"}, {155, 2, "DEV_UART4_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART4_FCLK_CLK"}, {155, 5, "DEV_UART4_VBUSP_CLK", "Input clock"}, {156, 0, "DEV_UART5_FCLK_CLK", "Input muxed clock"}, {156, 1, "DEV_UART5_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT5", "Parent input clock option to DEV_UART5_FCLK_CLK"}, {156, 2, "DEV_UART5_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART5_FCLK_CLK"}, {156, 5, "DEV_UART5_VBUSP_CLK", "Input clock"}, {158, 0, "DEV_UART6_FCLK_CLK", "Input muxed clock"}, {158, 1, "DEV_UART6_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT6", "Parent input clock option to DEV_UART6_FCLK_CLK"}, {158, 2, "DEV_UART6_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART6_FCLK_CLK"}, {158, 5, "DEV_UART6_VBUSP_CLK", "Input clock"}, {161, 0, "DEV_USB0_BUS_CLK", "Input clock"}, {161, 1, "DEV_USB0_CFG_CLK", "Input clock"}, {161, 2, "DEV_USB0_USB2_APB_PCLK_CLK", "Input clock"}, {161, 3, "DEV_USB0_USB2_REFCLOCK_CLK", "Input muxed clock"}, {161, 4, "DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK"}, {161, 5, "DEV_USB0_USB2_REFCLOCK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK"}, {161, 10, "DEV_USB0_USB2_TAP_TCK", "Input clock"}, {162, 0, "DEV_USB1_BUS_CLK", "Input clock"}, {162, 1, "DEV_USB1_CFG_CLK", "Input clock"}, {162, 2, "DEV_USB1_USB2_APB_PCLK_CLK", "Input clock"}, {162, 3, "DEV_USB1_USB2_REFCLOCK_CLK", "Input muxed clock"}, {162, 4, "DEV_USB1_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_USB1_USB2_REFCLOCK_CLK"}, {162, 5, "DEV_USB1_USB2_REFCLOCK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_USB1_USB2_REFCLOCK_CLK"}, {162, 10, "DEV_USB1_USB2_TAP_TCK", "Input clock"}, {219, 1, "DEV_VPAC0_PLL_CTRL_CLK", "Input clock"}, {219, 3, "DEV_VPAC0_VPAC_PLL_CFG_CLK", "Input clock"}, {219, 4, "DEV_VPAC0_VPAC_PLL_CLK", "Input clock"}, {218, 0, "DEV_VPAC_RSWS_BW_LIMITER7_CLK_CLK", "Input clock"}, {217, 0, "DEV_VPAC_RSWS_BW_LIMITER8_CLK_CLK", "Input clock"}, {226, 0, "DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK", "Input muxed clock"}, {226, 1, "DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_LFOSC0_CLKOUT", "Parent input clock option to DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK"}, {226, 2, "DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK"}, {226, 3, "DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK"}, {226, 4, "DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT9_CLK", "Parent input clock option to DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK"}, {226, 5, "DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK"}, {226, 6, "DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK"}, {226, 7, "DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK"}, {176, 0, "DEV_WKUP_DEEPSLEEP_SOURCES0_CLK_12M_RC_CLK", "Input clock"}, {64, 0, "DEV_WKUP_ESM0_CLK", "Input clock"}, {61, 0, "DEV_WKUP_GTC0_GTC_CLK", "Input muxed clock"}, {61, 1, "DEV_WKUP_GTC0_GTC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK", "Parent input clock option to DEV_WKUP_GTC0_GTC_CLK"}, {61, 2, "DEV_WKUP_GTC0_GTC_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_WKUP_GTC0_GTC_CLK"}, {61, 3, "DEV_WKUP_GTC0_GTC_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_WKUP_GTC0_GTC_CLK"}, {61, 5, "DEV_WKUP_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_WKUP_GTC0_GTC_CLK"}, {61, 6, "DEV_WKUP_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_WKUP_GTC0_GTC_CLK"}, {61, 7, "DEV_WKUP_GTC0_GTC_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_WKUP_GTC0_GTC_CLK"}, {61, 8, "DEV_WKUP_GTC0_GTC_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_WKUP_GTC0_GTC_CLK"}, {61, 9, "DEV_WKUP_GTC0_VBUSP_CLK", "Input muxed clock"}, {61, 10, "DEV_WKUP_GTC0_VBUSP_CLK_PARENT_HSDIV2_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_GTC0_VBUSP_CLK"}, {61, 11, "DEV_WKUP_GTC0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_GTC0_VBUSP_CLK"}, {107, 0, "DEV_WKUP_I2C0_CLK", "Input muxed clock"}, {107, 1, "DEV_WKUP_I2C0_CLK_PARENT_HSDIV2_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_I2C0_CLK"}, {107, 2, "DEV_WKUP_I2C0_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_I2C0_CLK"}, {107, 4, "DEV_WKUP_I2C0_PISYS_CLK", "Input clock"}, {107, 5, "DEV_WKUP_I2C0_PORSCL", "Output clock"}, {5, 0, "DEV_WKUP_MCU_GPIOMUX_INTROUTER0_INTR_CLK", "Input clock"}, {165, 7, "DEV_WKUP_PBIST0_CLK8_CLK", "Input clock"}, {140, 0, "DEV_WKUP_PSC0_CLK", "Input clock"}, {140, 1, "DEV_WKUP_PSC0_SLOW_CLK", "Input clock"}, {121, 0, "DEV_WKUP_R5FSS0_CORE0_CPU_CLK", "Input muxed clock"}, {121, 1, "DEV_WKUP_R5FSS0_CORE0_CPU_CLK_PARENT_HSDIV2_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_WKUP_R5FSS0_CORE0_CPU_CLK"}, {121, 2, "DEV_WKUP_R5FSS0_CORE0_CPU_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_R5FSS0_CORE0_CPU_CLK"}, {121, 5, "DEV_WKUP_R5FSS0_CORE0_INTERFACE_CLK", "Input clock"}, {117, 0, "DEV_WKUP_RTCSS0_ANA_OSC32K_CLK", "Input muxed clock"}, {117, 1, "DEV_WKUP_RTCSS0_ANA_OSC32K_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_WKUP_RTCSS0_ANA_OSC32K_CLK"}, {117, 2, "DEV_WKUP_RTCSS0_ANA_OSC32K_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_WKUP_RTCSS0_ANA_OSC32K_CLK"}, {117, 4, "DEV_WKUP_RTCSS0_JTAG_WRCK", "Input clock"}, {117, 6, "DEV_WKUP_RTCSS0_VCLK_CLK", "Input muxed clock"}, {117, 7, "DEV_WKUP_RTCSS0_VCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_RTCSS0_VCLK_CLK"}, {117, 8, "DEV_WKUP_RTCSS0_VCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_RTCSS0_VCLK_CLK"}, {132, 0, "DEV_WKUP_RTI0_RTI_CLK", "Input muxed clock"}, {132, 1, "DEV_WKUP_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_WKUP_RTI0_RTI_CLK"}, {132, 2, "DEV_WKUP_RTI0_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_WKUP_RTI0_RTI_CLK"}, {132, 3, "DEV_WKUP_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_WKUP_RTI0_RTI_CLK"}, {132, 4, "DEV_WKUP_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_WKUP_RTI0_RTI_CLK"}, {132, 5, "DEV_WKUP_RTI0_VBUSP_CLK", "Input muxed clock"}, {132, 6, "DEV_WKUP_RTI0_VBUSP_CLK_PARENT_HSDIV2_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_RTI0_VBUSP_CLK"}, {132, 7, "DEV_WKUP_RTI0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_RTI0_VBUSP_CLK"}, {110, 0, "DEV_WKUP_TIMER0_TIMER_HCLK_CLK", "Input muxed clock"}, {110, 1, "DEV_WKUP_TIMER0_TIMER_HCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_HCLK_CLK"}, {110, 2, "DEV_WKUP_TIMER0_TIMER_HCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_HCLK_CLK"}, {110, 3, "DEV_WKUP_TIMER0_TIMER_PWM", "Output clock"}, {110, 4, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"}, {110, 5, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK"}, {110, 6, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_WKUP_CLKSEL_OUT04", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK"}, {110, 7, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK"}, {110, 8, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV1_16FFT_MCU_0_HSDIVOUT5_CLK", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK"}, {110, 9, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK"}, {110, 10, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK"}, {110, 11, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK"}, {110, 12, "DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK"}, {111, 0, "DEV_WKUP_TIMER1_TIMER_HCLK_CLK", "Input muxed clock"}, {111, 1, "DEV_WKUP_TIMER1_TIMER_HCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_TIMER1_TIMER_HCLK_CLK"}, {111, 2, "DEV_WKUP_TIMER1_TIMER_HCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_TIMER1_TIMER_HCLK_CLK"}, {111, 4, "DEV_WKUP_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"}, {111, 5, "DEV_WKUP_TIMER1_TIMER_TCLK_CLK_PARENT_WKUP_TIMERCLKN_SEL_OUT1", "Parent input clock option to DEV_WKUP_TIMER1_TIMER_TCLK_CLK"}, {111, 6, "DEV_WKUP_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_WKUP_0_TIMER_PWM", "Parent input clock option to DEV_WKUP_TIMER1_TIMER_TCLK_CLK"}, {114, 0, "DEV_WKUP_UART0_FCLK_CLK", "Input clock"}, {114, 3, "DEV_WKUP_UART0_VBUSP_CLK", "Input muxed clock"}, {114, 4, "DEV_WKUP_UART0_VBUSP_CLK_PARENT_HSDIV2_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_UART0_VBUSP_CLK"}, {114, 5, "DEV_WKUP_UART0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_UART0_VBUSP_CLK"}, {95, 0, "DEV_WKUP_VTM0_FIX_REF2_CLK", "Input clock"}, {95, 1, "DEV_WKUP_VTM0_FIX_REF_CLK", "Input clock"}, {95, 2, "DEV_WKUP_VTM0_VBUSP_CLK", "Input muxed clock"}, {95, 3, "DEV_WKUP_VTM0_VBUSP_CLK_PARENT_HSDIV2_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_VTM0_VBUSP_CLK"}, {95, 4, "DEV_WKUP_VTM0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_WKUP_VTM0_VBUSP_CLK"}, }; k3conf_0.3/soc/am62ax/am62ax_rm_info.h0000664000175000017500000000342714375734376014436 0ustar /* * AM62AX RM Info * * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AM62AX_RM_INFO_H #define __AM62AX_RM_INFO_H #define AM62AX_MAX_RES 68 extern struct ti_sci_rm_info am62ax_rm_info[]; #endif /* __AM62AX_RM_INFO_H */ k3conf_0.3/soc/am62ax/am62ax_sec_proxy_info.c0000664000175000017500000000707514375734376016031 0ustar /* * AM62AX Sec Proxy Info * * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_sec_proxy_info am62ax_main_sp_info[] = { {69, "read", 38, "DM", "nonsec_low_priority_rx"}, {68, "write", 11, "DM", "nonsec_MAIN_0_R5_1_response_tx"}, {67, "write", 2, "DM", "nonsec_MAIN_0_R5_3_response_tx"}, {66, "write", 6, "DM", "nonsec_A53_2_response_tx"}, {65, "write", 6, "DM", "nonsec_A53_3_response_tx"}, {64, "write", 6, "DM", "nonsec_MCU_0_R5_0_response_tx"}, {63, "write", 6, "DM", "nonsec_A53_4_response_tx"}, {62, "write", 7, "DM", "nonsec_C7X_0_0_response_tx"}, {61, "write", 4, "DM", "nonsec_TIFS2DM_response_tx"}, {0, "read", 11, "MAIN_0_R5_0", "response"}, {1, "write", 10, "MAIN_0_R5_0", "low_priority"}, {2, "read", 11, "MAIN_0_R5_1", "response"}, {3, "write", 10, "MAIN_0_R5_1", "low_priority"}, {4, "read", 2, "MAIN_0_R5_2", "response"}, {5, "write", 1, "MAIN_0_R5_2", "low_priority"}, {6, "read", 2, "MAIN_0_R5_3", "response"}, {7, "write", 1, "MAIN_0_R5_3", "low_priority"}, {8, "read", 11, "A53_0", "response"}, {9, "write", 10, "A53_0", "low_priority"}, {10, "read", 11, "A53_1", "response"}, {11, "write", 10, "A53_1", "low_priority"}, {12, "read", 6, "A53_2", "response"}, {13, "write", 5, "A53_2", "low_priority"}, {14, "read", 6, "A53_3", "response"}, {15, "write", 5, "A53_3", "low_priority"}, {16, "read", 6, "MCU_0_R5_0", "response"}, {17, "write", 5, "MCU_0_R5_0", "low_priority"}, {18, "read", 6, "A53_4", "response"}, {19, "write", 5, "A53_4", "low_priority"}, {20, "read", 7, "C7X_0_0", "response"}, {21, "write", 5, "C7X_0_0", "low_priority"}, {22, "read", 4, "DM2TIFS", "response"}, {23, "write", 2, "DM2TIFS", "low_priority"}, {24, "read", 4, "TIFS2DM", "response"}, {25, "write", 2, "TIFS2DM", "low_priority"}, }; struct ti_sci_sec_proxy_info am62ax_mcu_sp_info[] = { {15, "read", 8, "TIFS_HSM", "sec_low_priority_rx"}, {14, "write", 8, "TIFS_HSM", "sec_HSM_response_tx"}, {0, "read", 8, "HSM", "response"}, {1, "write", 8, "HSM", "low_priority"}, }; k3conf_0.3/.project0000664000175000017500000000144714456001511011215 0ustar k3conf org.eclipse.cdt.managedbuilder.core.genmakebuilder clean,full,incremental, org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder full,incremental, org.eclipse.cdt.core.cnature org.eclipse.cdt.core.ccnature org.eclipse.cdt.managedbuilder.core.managedBuildNature org.eclipse.cdt.managedbuilder.core.ScannerConfigNature k3conf_0.3/common/0000775000175000017500000000000014605602064011036 5ustar k3conf_0.3/common/cmd_show.c0000664000175000017500000002564414375734376013040 0ustar /* * K3CONF Command Show * * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include static int show_hosts_info(void) { struct ti_sci_host_info *hosts = soc_info.sci_info.host_info; char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN]; uint32_t row = 0; autoadjust_table_init(table); strncpy(table[row][0], "Host ID", TABLE_MAX_ELT_LEN); strncpy(table[row][1], "Host Name", TABLE_MAX_ELT_LEN); strncpy(table[row][2], "Security Status", TABLE_MAX_ELT_LEN); strncpy(table[row][3], "Description", TABLE_MAX_ELT_LEN); for (row = 0; row < soc_info.sci_info.num_hosts; row++) { snprintf(table[row + 1][0], TABLE_MAX_ELT_LEN, "%d", hosts[row].host_id); strncpy(table[row + 1][1], hosts[row].host_name, TABLE_MAX_ELT_LEN); strncpy(table[row + 1][2], hosts[row].security_status, TABLE_MAX_ELT_LEN); strncpy(table[row + 1][3], hosts[row].description, TABLE_MAX_ELT_LEN); } return autoadjust_table_print(table, row + 1, 4); } static int show_sp_threads_info(void) { char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN]; struct ti_sci_sec_proxy_info *sp; uint32_t row = 0, i; autoadjust_table_init(table); strncpy(table[row][0], "Secure Proxy thread allocation for main_sec_proxy0", TABLE_MAX_ELT_LEN); row++; strncpy(table[row][0], "Thread ID", TABLE_MAX_ELT_LEN); strncpy(table[row][1], "Direction", TABLE_MAX_ELT_LEN); strncpy(table[row][2], "No. of msgs", TABLE_MAX_ELT_LEN); strncpy(table[row][3], "Host", TABLE_MAX_ELT_LEN); strncpy(table[row][4], "Host Function", TABLE_MAX_ELT_LEN); row++; sp = soc_info.sci_info.sp_info[MAIN_SEC_PROXY]; for (i = 0; i < soc_info.sci_info.num_sp_threads[MAIN_SEC_PROXY]; row++, i++) { snprintf(table[row][0], TABLE_MAX_ELT_LEN, "%5d", sp[i].sp_id); strncpy(table[row][1], sp[i].sp_dir, TABLE_MAX_ELT_LEN); snprintf(table[row][2], TABLE_MAX_ELT_LEN, "%7d", sp[i].num_msgs); strncpy(table[row][3], sp[i].host, TABLE_MAX_ELT_LEN); strncpy(table[row][4], sp[i].host_function, TABLE_MAX_ELT_LEN); } autoadjust_table_generic_fprint(stdout, table, row, 5, TABLE_HAS_SUBTITLE | TABLE_HAS_TITLE); row = 0; autoadjust_table_init(table); strncpy(table[row][0], "Secure Proxy thread allocation for mcu_sec_proxy0", TABLE_MAX_ELT_LEN); row++; strncpy(table[row][0], "Thread ID", TABLE_MAX_ELT_LEN); strncpy(table[row][1], "Direction", TABLE_MAX_ELT_LEN); strncpy(table[row][2], "No. of msgs", TABLE_MAX_ELT_LEN); strncpy(table[row][3], "Host", TABLE_MAX_ELT_LEN); strncpy(table[row][4], "Host Function", TABLE_MAX_ELT_LEN); row++; sp = soc_info.sci_info.sp_info[MCU_SEC_PROXY]; for (i = 0; i < soc_info.sci_info.num_sp_threads[MCU_SEC_PROXY]; row++, i++) { snprintf(table[row][0], TABLE_MAX_ELT_LEN, "%5d", sp[i].sp_id); strncpy(table[row][1], sp[i].sp_dir, TABLE_MAX_ELT_LEN); snprintf(table[row][2], TABLE_MAX_ELT_LEN, "%7d", sp[i].num_msgs); strncpy(table[row][3], sp[i].host, TABLE_MAX_ELT_LEN); strncpy(table[row][4], sp[i].host_function, TABLE_MAX_ELT_LEN); } return autoadjust_table_generic_fprint(stdout, table, row, 5, TABLE_HAS_SUBTITLE | TABLE_HAS_TITLE); } static int show_clocks_info(int argc, char *argv[]) { struct ti_sci_clocks_info *c = soc_info.sci_info.clocks_info; char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN]; uint32_t row = 0, dev_id; int found = 0, ret; autoadjust_table_init(table); strncpy(table[row][0], "Device ID", TABLE_MAX_ELT_LEN); strncpy(table[row][1], "Clock ID", TABLE_MAX_ELT_LEN); strncpy(table[row][2], "Clock Name", TABLE_MAX_ELT_LEN); strncpy(table[row][3], "Clock Function", TABLE_MAX_ELT_LEN); if (argc) goto print_single_device; for (row = 0; row < soc_info.sci_info.num_clocks; row++) { snprintf(table[row + 1][0], TABLE_MAX_ELT_LEN, "%5d", c[row].dev_id); snprintf(table[row + 1][1], TABLE_MAX_ELT_LEN, "%5d", c[row].clk_id); strncpy(table[row + 1][2], c[row].clk_name, TABLE_MAX_ELT_LEN); strncpy(table[row + 1][3], c[row].clk_function, TABLE_MAX_ELT_LEN); } return autoadjust_table_print(table, row + 1, 4); print_single_device: ret = sscanf(argv[0], "%u", &dev_id); if (ret != 1) return -1; for (row = 0; row < soc_info.sci_info.num_clocks; row++) { if (dev_id == c[row].dev_id) { snprintf(table[found + 1][0], TABLE_MAX_ELT_LEN, "%5d", c[row].dev_id); snprintf(table[found + 1][1], TABLE_MAX_ELT_LEN, "%5d", c[row].clk_id); strncpy(table[found + 1][2], c[row].clk_name, TABLE_MAX_ELT_LEN); strncpy(table[found + 1][3], c[row].clk_function, TABLE_MAX_ELT_LEN); found++; } } if (!found) return -1; return autoadjust_table_print(table, found + 1, 4); } static int show_devices_info(int argc, char *argv[]) { struct ti_sci_devices_info *p = soc_info.sci_info.devices_info; char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN]; uint32_t row = 0, dev_id; int found = 0, ret; autoadjust_table_init(table); strncpy(table[row][0], "Device ID", TABLE_MAX_ELT_LEN); strncpy(table[row][1], "Device Name", TABLE_MAX_ELT_LEN); if (argc) goto print_single_device; for (row = 0; row < soc_info.sci_info.num_devices; row++) { snprintf(table[row + 1][0], TABLE_MAX_ELT_LEN, "%5d", p[row].dev_id); strncpy(table[row + 1][1], p[row].name, TABLE_MAX_ELT_LEN); } return autoadjust_table_print(table, row + 1, 2); print_single_device: ret = sscanf(argv[0], "%u", &dev_id); if (ret != 1) return -1; for (row = 0; row < soc_info.sci_info.num_devices; row++) { if (dev_id == p[row].dev_id) { snprintf(table[1][0], TABLE_MAX_ELT_LEN, "%5d", p[row].dev_id); strncpy(table[1][1], p[row].name, TABLE_MAX_ELT_LEN); found = 1; break; } } if (!found) return -1; return autoadjust_table_print(table, 2, 2); } static int show_rm_info(int argc, char *argv[]) { struct ti_sci_devices_info *d = soc_info.sci_info.devices_info; char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN]; struct ti_sci_rm_info *r = soc_info.sci_info.rm_info; uint32_t filter_type = 0, type, subtype, i, j, row; char *subtype_name; if (argc > 1) return -1; if (argc == 1) sscanf(argv[0], "%u", &filter_type); snprintf(table[0][0], TABLE_MAX_ELT_LEN, "Resources managed by System Firmware"); snprintf(table[1][0], TABLE_MAX_ELT_LEN, "Unique Type"); snprintf(table[1][1], TABLE_MAX_ELT_LEN, "dev_id"); snprintf(table[1][2], TABLE_MAX_ELT_LEN, "Device name"); snprintf(table[1][3], TABLE_MAX_ELT_LEN, "subtype_id"); snprintf(table[1][4], TABLE_MAX_ELT_LEN, "Subtype name"); row = 2; for (i = 0; i < soc_info.sci_info.num_res; i++) { type = r[i].utype >> 6; subtype = r[i].utype & 0x3F; subtype_name = r[i].subtype_name; if (filter_type && filter_type != type) continue; for (j = 0; j < soc_info.sci_info.num_devices; j++) { if (type == d[j].dev_id) break; } snprintf(table[row][0], TABLE_MAX_ELT_LEN, "0x%04x", r[i].utype); snprintf(table[row][1], TABLE_MAX_ELT_LEN, "%d", d[j].dev_id); snprintf(table[row][2], TABLE_MAX_ELT_LEN, "%s", d[j].name); snprintf(table[row][3], TABLE_MAX_ELT_LEN, "%d", subtype); snprintf(table[row][4], TABLE_MAX_ELT_LEN, "%s", subtype_name); row++; } if (row == 2) { fprintf(stderr, "Resources for type %d are not managed by SYSFW\n", filter_type); return -1; } return autoadjust_table_generic_fprint(stdout, table, row, 5, TABLE_HAS_SUBTITLE | TABLE_HAS_TITLE); } static int show_processors_info(void) { struct ti_sci_processors_info *p = soc_info.sci_info.processors_info; char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN]; uint32_t row = 0; autoadjust_table_init(table); strncpy(table[row][0], "Device ID", TABLE_MAX_ELT_LEN); strncpy(table[row][1], "Processor ID", TABLE_MAX_ELT_LEN); strncpy(table[row][2], "Processor Name", TABLE_MAX_ELT_LEN); for (row = 0; row < soc_info.sci_info.num_processors; row++) { snprintf(table[row + 1][0], TABLE_MAX_ELT_LEN, "%5d", p[row].dev_id); snprintf(table[row + 1][1], TABLE_MAX_ELT_LEN, "%7d", p[row].processor_id); strncpy(table[row + 1][2], p[row].name, TABLE_MAX_ELT_LEN); } return autoadjust_table_print(table, row + 1, 3); } int process_show_command(int argc, char *argv[]) { int ret; if (argc < 1) { help(HELP_SHOW); return -1; } if (!strncmp(argv[0], "host", 4)) { ret = show_hosts_info(); if (ret) help(HELP_SHOW_HOST); } else if (!strncmp(argv[0], "thread", 6)) { ret = show_sp_threads_info(); if (ret) help(HELP_SHOW_SEC_PROXY); } else if (!strncmp(argv[0], "device", 6)) { argc--; argv++; ret = show_devices_info(argc, argv); if (ret) { fprintf(stderr, "Invalid device arguments\n"); help(HELP_SHOW_DEVICE); } } else if (!strncmp(argv[0], "clock", 5)) { argc--; argv++; ret = show_clocks_info(argc, argv); if (ret) { fprintf(stderr, "Invalid clock arguments\n"); help(HELP_SHOW_CLOCK); } } else if(!strncmp(argv[0], "processor", 9)) { ret = show_processors_info(); if (ret) help(HELP_SHOW_PROCESSOR); } else if(!strncmp(argv[0], "rm", 2)) { argc--; argv++; ret = show_rm_info(argc, argv); if (ret) { fprintf(stderr, "Invalid device_id arguments\n"); help(HELP_SHOW_RM); } } else if (!strcmp(argv[0], "--help")) { help(HELP_SHOW); return 0; } else { fprintf(stderr, "Invalid argument %s\n", argv[1]); help(HELP_SHOW); return -1; } return ret; } k3conf_0.3/common/cmd_enable.c0000664000175000017500000000613314375734376013276 0ustar /* * K3CONF Command Enable * * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include static int enable_device(int argc, char *argv[]) { uint32_t dev_id, ret; if (argc < 1) return -1; ret = sscanf(argv[0], "%u", &dev_id); if (ret != 1) return -1; ret = ti_sci_cmd_enable_device(dev_id); if (ret) return ret; return dump_devices_info(argc, argv); } static int enable_clock(int argc, char *argv[]) { uint32_t dev_id, clk_id, ret; if (argc < 2) return -1; ret = sscanf(argv[0], "%u", &dev_id); if (ret != 1) return -1; ret = sscanf(argv[1], "%u", &clk_id); if (ret != 1) return -1; ret = ti_sci_cmd_get_clk(dev_id, clk_id); if (ret) return ret; return dump_clocks_info(argc, argv); } int process_enable_command(int argc, char *argv[]) { int ret; if (argc < 1) { help(HELP_ENABLE); return -1; } if (!strncmp(argv[0], "device", 6)) { argc--; argv++; ret = enable_device(argc, argv); if (ret) { fprintf(stderr, "Invalid device arguments\n"); help(HELP_ENABLE_DEVICE); } } else if (!strncmp(argv[0], "clock", 5)) { argc--; argv++; ret = enable_clock(argc, argv); if (ret) { fprintf(stderr, "Invalid clock arguments\n"); help(HELP_ENABLE_CLOCK); } } else if (!strcmp(argv[0], "--help")) { help(HELP_ENABLE); return 0; } else { fprintf(stderr, "Invalid argument %s\n", argv[1]); help(HELP_ENABLE); return -1; } return ret; } k3conf_0.3/common/sec_proxy.c0000664000175000017500000002033714375734376013242 0ustar /* * K3 Secure proxy driver * * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #ifdef DEBUG #define dprintf(format, ...) printf(format, ## __VA_ARGS__) #else #define dprintf(format, ...) #endif /* SEC PROXY RT THREAD STATUS */ #define RT_THREAD_STATUS 0x0 #define RT_THREAD_THRESHOLD 0x4 #define RT_THREAD_STATUS_ERROR_SHIFT 31 #define RT_THREAD_STATUS_ERROR_MASK (1 << 31) #define RT_THREAD_STATUS_CUR_CNT_SHIFT 0 #define RT_THREAD_STATUS_CUR_CNT_MASK 0xff /* SEC PROXY SCFG THREAD CTRL */ #define SCFG_THREAD_CTRL 0x1000 #define SCFG_THREAD_CTRL_DIR_SHIFT 31 #define SCFG_THREAD_CTRL_DIR_MASK (1 << 31) #define SEC_PROXY_THREAD(base, x) ((base) + (0x1000 * (x))) #define SEC_PROXY_TX_THREAD 0 #define SEC_PROXY_RX_THREAD 1 #define SEC_PROXY_MAX_THREADS 2 #define SEC_PROXY_TIMEOUT_US 1000000 #define SEC_PROXY_DATA_START_OFFS 0x4 #define SEC_PROXY_DATA_END_OFFS 0x3c struct k3_sec_proxy_base k3_generic_sec_proxy_base = { .src_target_data = 0x32c00000, .cfg_scfg = 0x32800000, .cfg_rt = 0x32400000, }; struct k3_sec_proxy_base k3_lite_sec_proxy_base = { .src_target_data = 0x4d000000, .cfg_scfg = 0x4a400000, .cfg_rt = 0x4a600000, }; struct k3_sec_proxy_thread { uint32_t id; uintptr_t data; uintptr_t scfg; uintptr_t rt; } spts[SEC_PROXY_MAX_THREADS]; static inline uint32_t sp_readl(uintptr_t addr) { return mmio_read_32(addr); } static inline void sp_writel(uintptr_t addr, uint32_t data) { mmio_write_32(addr, data); } static int k3_sec_proxy_verify_thread(uint32_t dir) { struct k3_sec_proxy_thread *spt = &spts[dir]; /* Check for any errors already available */ if (sp_readl(spt->rt + RT_THREAD_STATUS) & RT_THREAD_STATUS_ERROR_MASK) { fprintf(stderr, "%s: Thread %d is corrupted, cannot send data.\n", __func__, spt->id); return -1; } /* Make sure thread is configured for right direction */ if ((sp_readl(spt->scfg + SCFG_THREAD_CTRL) & SCFG_THREAD_CTRL_DIR_MASK) >> SCFG_THREAD_CTRL_DIR_SHIFT != dir) { if (dir) fprintf(stderr, "%s: Trying to receive data on tx Thread %d\n", __func__, spt->id); else fprintf(stderr, "%s: Trying to send data on rx Thread %d\n", __func__, spt->id); return -1; } /* Check the message queue before sending/receiving data */ if (!(sp_readl(spt->rt + RT_THREAD_STATUS) & RT_THREAD_STATUS_CUR_CNT_MASK)) return -2; return 0; } int k3_sec_proxy_send(struct k3_sec_proxy_msg *msg) { struct k3_sec_proxy_thread *spt = &spts[SEC_PROXY_TX_THREAD]; int num_words, trail_bytes, ret; uint32_t *word_data; uintptr_t data_reg; ret = k3_sec_proxy_verify_thread(SEC_PROXY_TX_THREAD); if (ret) { fprintf(stderr, "%s: Thread%d verification failed. ret = %d\n", __func__, spt->id, ret); return ret; } /* Check the message size. */ if (msg->len > SEC_PROXY_MAX_MSG_SIZE) { fprintf(stderr, "%s: Thread %u message length %zu > max msg size %d\n", __func__, spt->id, msg->len, SEC_PROXY_MAX_MSG_SIZE); return -1; } /* Send the message */ data_reg = spt->data + SEC_PROXY_DATA_START_OFFS; word_data = (uint32_t *)msg->buf; for (num_words = msg->len / sizeof(uint32_t); num_words; num_words--, data_reg += sizeof(uint32_t), word_data++) sp_writel(data_reg, *word_data); trail_bytes = msg->len % sizeof(uint32_t); if (trail_bytes) { uint32_t data_trail = *word_data; /* Ensure all unused data is 0 */ data_trail &= 0xFFFFFFFF >> (8 * (sizeof(uint32_t) - trail_bytes)); sp_writel(data_reg, data_trail); data_reg++; } /* * 'data_reg' indicates next register to write. If we did not already * write on tx complete reg(last reg), we must do so for transmit */ if (data_reg <= (spt->data + SEC_PROXY_DATA_END_OFFS)) sp_writel(spt->data + SEC_PROXY_DATA_END_OFFS, 0); return 0; } int k3_sec_proxy_recv(struct k3_sec_proxy_msg *msg) { struct k3_sec_proxy_thread *spt = &spts[SEC_PROXY_RX_THREAD]; int num_words, ret = -1, retry = 10000; uint32_t *word_data; uintptr_t data_reg; while (retry-- && ret) { ret = k3_sec_proxy_verify_thread(SEC_PROXY_RX_THREAD); if ((ret && ret != -2) || !retry) { fprintf(stderr, "%s: Thread%d verification failed. ret = %d\n", __func__, spt->id, ret); return ret; } } data_reg = spt->data + SEC_PROXY_DATA_START_OFFS; word_data = (uint32_t *)(uintptr_t)msg->buf; for (num_words = SEC_PROXY_MAX_MSG_SIZE / sizeof(uint32_t); num_words; num_words--, data_reg += sizeof(uint32_t), word_data++) *word_data = sp_readl(data_reg); return 0; } static int get_thread_id(char *host_name, char *function) { struct ti_sci_info *sci_info = &soc_info.sci_info; uint32_t i; for (i = 0; i < sci_info->num_sp_threads[MAIN_SEC_PROXY]; i++) if (!strcmp(host_name, sci_info->sp_info[MAIN_SEC_PROXY][i].host) && !strcmp(function, sci_info->sp_info[MAIN_SEC_PROXY][i].host_function)) return sci_info->sp_info[MAIN_SEC_PROXY][i].sp_id; return -1; } static char* get_host_name(uint32_t host_id) { struct ti_sci_info *sci_info = &soc_info.sci_info; uint32_t i; for (i = 0; i < sci_info->num_hosts; i++) if (host_id == sci_info->host_info[i].host_id) return sci_info->host_info[i].host_name; return NULL; } int k3_sec_proxy_init(void) { struct k3_sec_proxy_base *spb = soc_info.sec_proxy; int rx_thread, tx_thread; char *host_name; host_name = get_host_name(soc_info.host_id); if (!host_name) { fprintf(stderr, "Invalid host id %d, using default host_id %d\n", soc_info.host_id, DEFAULT_HOST_ID); soc_info.host_id = DEFAULT_HOST_ID; host_name = get_host_name(soc_info.host_id); } rx_thread = get_thread_id(host_name, "response"); if (rx_thread < 0) { fprintf(stderr, "Invalid host id %d, using default host_id %d\n", soc_info.host_id, DEFAULT_HOST_ID); soc_info.host_id = DEFAULT_HOST_ID; host_name = get_host_name(soc_info.host_id); rx_thread = get_thread_id(host_name, "response"); } tx_thread = get_thread_id(host_name, "low_priority"); dprintf("host_name = %s, tx_thread = %d, rx_thread = %d\n", host_name, tx_thread, rx_thread); spts[SEC_PROXY_TX_THREAD].id = tx_thread; spts[SEC_PROXY_TX_THREAD].data = SEC_PROXY_THREAD(spb->src_target_data, tx_thread); spts[SEC_PROXY_TX_THREAD].scfg = SEC_PROXY_THREAD(spb->cfg_scfg, tx_thread); spts[SEC_PROXY_TX_THREAD].rt = SEC_PROXY_THREAD(spb->cfg_rt, tx_thread); spts[SEC_PROXY_RX_THREAD].id = rx_thread; spts[SEC_PROXY_RX_THREAD].data = SEC_PROXY_THREAD(spb->src_target_data, rx_thread); spts[SEC_PROXY_RX_THREAD].scfg = SEC_PROXY_THREAD(spb->cfg_scfg, rx_thread); spts[SEC_PROXY_RX_THREAD].rt = SEC_PROXY_THREAD(spb->cfg_rt, rx_thread); return 0; } k3conf_0.3/common/cmd_ddr_perf.c0000664000175000017500000001475714504336530013630 0ustar /* * K3CONF DDR b/w capture * * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ * Aarya Chaumal * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include #include #define TO_USEC(ts) ((ts).tv_sec * 1000000 + (ts).tv_nsec / 1000) #define MAX_PERF_NUM_DDR_INSTANCES (4u) /* A value of 0x00 configures counter 0 to return number of write transactions */ #define PERF_DDR_STATS_CTR0 (0x00) /* A value of 0x01 configures counter 1 to return number of read transactions */ #define PERF_DDR_STATS_CTR1 (0x01) #define PERF_CNT_SEL_REG_OFFSET (0) #define PERF_CTR0_REG_OFFSET (4) #define PERF_CTR1_REG_OFFSET (8) struct data_capture_per_inst { uint32_t initial_read; uint32_t initial_write; uint32_t final_read; uint32_t final_write; struct timespec first_time; struct timespec last_time; }; static inline uintptr_t ctrl_reg_addr(struct ddr_perf_soc_info *pinfo, uint8_t inst) { return pinfo->perf_inst_base[inst] + PERF_CNT_SEL_REG_OFFSET; } static inline uintptr_t read_counter_addr(struct ddr_perf_soc_info *pinfo, uint8_t inst) { return pinfo->perf_inst_base[inst] + PERF_CTR0_REG_OFFSET; } static inline uintptr_t write_counter_addr(struct ddr_perf_soc_info *pinfo, uint8_t inst) { return pinfo->perf_inst_base[inst] + PERF_CTR1_REG_OFFSET; } int ddrbw_info(int argc, char *argv[]) { char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN]; uint32_t row = 0; int ret = 0; uint32_t duration = 1; int auto_refresh = -1; struct ddr_perf_soc_info *pinfo = soc_info.ddr_perf_info; struct data_capture_per_inst *dcap; if (!pinfo) { fprintf(stderr, "DDR performance monitoring is not supported on this SoC\n"); return -1; } if (argc >= 1) { ret = sscanf(argv[0], "%u", &duration); if (ret != 1) { fprintf(stderr, "Invalid argument for duration.\n"); help(HELP_DUMP_DDRBW); return -1; } } if (argc == 2) { ret = sscanf(argv[1], "%d", &auto_refresh); if (ret != 1) { fprintf(stderr, "Invalid argument for auto_refresh.\n"); help(HELP_DUMP_DDRBW); return -1; } } dcap = calloc(sizeof(struct data_capture_per_inst), pinfo->num_perf_insts); if (dcap == NULL) { fprintf(stderr, "Unable to allocate capture memory\n"); return -2; } /* Set counter 0 and 1 to read and write resp. */ for (int i = 0; i < pinfo->num_perf_insts; i++) { mmio_write_32(ctrl_reg_addr(pinfo, i), PERF_DDR_STATS_CTR1 << 8 | PERF_DDR_STATS_CTR0 << 0); } autoadjust_table_init(table); strncpy(table[row][0], "DDR instance", TABLE_MAX_ELT_LEN); strncpy(table[row][1], "Read data (MB)", TABLE_MAX_ELT_LEN); strncpy(table[row][2], "Avg Read B/W (MB/s)", TABLE_MAX_ELT_LEN); strncpy(table[row][3], "Write data (MB)", TABLE_MAX_ELT_LEN); strncpy(table[row][4], "Avg Write B/W (MB/s)", TABLE_MAX_ELT_LEN); while (auto_refresh--) { struct timespec timer; for (int i = 0; i < pinfo->num_perf_insts; i++) { clock_gettime(CLOCK_MONOTONIC, &dcap[i].first_time); dcap[i].initial_read = mmio_read_32(read_counter_addr(pinfo, i)); dcap[i].initial_write = mmio_read_32(write_counter_addr(pinfo, i)); } timer = dcap[pinfo->num_perf_insts - 1].first_time; timer.tv_sec += duration; clock_nanosleep(CLOCK_MONOTONIC, TIMER_ABSTIME, &timer, NULL); for (int i = 0; i < pinfo->num_perf_insts; i++) { clock_gettime(CLOCK_MONOTONIC, &dcap[i].last_time); dcap[i].final_read = mmio_read_32(read_counter_addr(pinfo, i)); dcap[i].final_write = mmio_read_32(write_counter_addr(pinfo, i)); } for (int i = 0; i < pinfo->num_perf_insts; i++) { uint32_t read_count = 0, write_count = 0; uint32_t read_bytes = 0, write_bytes = 0; uint64_t time = 0; float read_bw = 0, write_bw = 0; if (dcap[i].final_read < dcap[i].initial_read) { /* wrap around case */ read_count = (0xFFFFFFFFu - dcap[i].final_read); read_count += dcap[i].initial_read; } else { read_count = dcap[i].final_read - dcap[i].initial_read; } if (dcap[i].final_write < dcap[i].initial_write) { /* wrap around case */ write_count = (0xFFFFFFFFu - dcap[i].final_write); write_count += dcap[i].initial_write; } else { write_count = dcap[i].final_write - dcap[i].initial_write; } read_bytes = read_count * pinfo->burst_size; write_bytes = write_count * pinfo->burst_size; time = TO_USEC(dcap[i].last_time) - TO_USEC(dcap[i].first_time); read_bw = read_bytes / time; write_bw = write_bytes / time; snprintf(table[i + 1][0], TABLE_MAX_ELT_LEN, "DDR%d", i); snprintf(table[i + 1][1], TABLE_MAX_ELT_LEN, "%u", read_bytes / 1000000u); snprintf(table[i + 1][2], TABLE_MAX_ELT_LEN, "%.3f", read_bw); snprintf(table[i + 1][3], TABLE_MAX_ELT_LEN, "%u", write_bytes / 1000000u); snprintf(table[i + 1][4], TABLE_MAX_ELT_LEN, "%.3f", write_bw); } ret = autoadjust_table_print(table, 1 + pinfo->num_perf_insts, 5); } free(dcap); return ret; } k3conf_0.3/common/cmd_dump.c0000664000175000017500000003655714375734376013032 0ustar /* * K3CONF Command Dump * * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include int dump_cpu_info(void) { struct ti_sci_processors_info *p = soc_info.sci_info.processors_info; char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN]; uint32_t row = 0, found = 0; uint64_t freq; autoadjust_table_init(table); strncpy(table[row][0], "Processor Name", TABLE_MAX_ELT_LEN); strncpy(table[row][1], "Processor State", TABLE_MAX_ELT_LEN); strncpy(table[row][2], "Processor Frequency", TABLE_MAX_ELT_LEN); for (row = 0; row < soc_info.sci_info.num_processors; row++) { if (strncmp(p[row].name, "A", 1)) continue; strncpy(table[found + 1][0], p[row].name, TABLE_MAX_ELT_LEN); /* ToDo: Should we get the state from proc ops */ snprintf(table[found + 1][1], TABLE_MAX_ELT_LEN, "%s", ti_sci_cmd_get_device_status(p[row].dev_id)); ti_sci_cmd_get_clk_freq(p[row].dev_id, p[row].clk_id, &freq); snprintf(table[found + 1][2], TABLE_MAX_ELT_LEN, "%lu", freq); found++; } return autoadjust_table_print(table, found + 1, 3); } int dump_clocks_info(int argc, char *argv[]) { struct ti_sci_clocks_info *c = soc_info.sci_info.clocks_info; char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN]; uint32_t row = 0, dev_id; int found = 0, ret; uint64_t freq; autoadjust_table_init(table); strncpy(table[row][0], "Device ID", TABLE_MAX_ELT_LEN); strncpy(table[row][1], "Clock ID", TABLE_MAX_ELT_LEN); strncpy(table[row][2], "Clock Name", TABLE_MAX_ELT_LEN); strncpy(table[row][3], "Status", TABLE_MAX_ELT_LEN); strncpy(table[row][4], "Clock Frequency", TABLE_MAX_ELT_LEN); if (argc) goto print_single_device; for (row = 0; row < soc_info.sci_info.num_clocks; row++) { snprintf(table[row + 1][0], TABLE_MAX_ELT_LEN, "%5d", c[row].dev_id); snprintf(table[row + 1][1], TABLE_MAX_ELT_LEN, "%5d", c[row].clk_id); strncpy(table[row + 1][2], c[row].clk_name, TABLE_MAX_ELT_LEN); snprintf(table[row + 1][3], TABLE_MAX_ELT_LEN, "%s", ti_sci_cmd_get_clk_state(c[row].dev_id, c[row].clk_id)); ti_sci_cmd_get_clk_freq(c[row].dev_id, c[row].clk_id, &freq); snprintf(table[row + 1][4], TABLE_MAX_ELT_LEN, "%lu", freq); } return autoadjust_table_print(table, row + 1, 5); print_single_device: ret = sscanf(argv[0], "%u", &dev_id); if (ret != 1) return -1; for (row = 0; row < soc_info.sci_info.num_clocks; row++) { if (dev_id == c[row].dev_id) { snprintf(table[found + 1][0], TABLE_MAX_ELT_LEN, "%5d", c[row].dev_id); snprintf(table[found + 1][1], TABLE_MAX_ELT_LEN, "%5d", c[row].clk_id); strncpy(table[found + 1][2], c[row].clk_name, TABLE_MAX_ELT_LEN); strncpy(table[found + 1][3], ti_sci_cmd_get_clk_state(dev_id, c[row].clk_id), TABLE_MAX_ELT_LEN); ti_sci_cmd_get_clk_freq(c[row].dev_id, c[row].clk_id, &freq); snprintf(table[found + 1][4], TABLE_MAX_ELT_LEN, "%lu", freq); found++; } } if (!found) return -1; return autoadjust_table_print(table, found + 1, 5); } int dump_clock_parent_info(int argc, char *argv[]) { struct ti_sci_clocks_info *c = soc_info.sci_info.clocks_info; char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN]; char clk_name[TABLE_MAX_ELT_LEN]; char clk_name_len = 0; uint32_t row = 0, dev_id, clk_id, parent_clk_id = 0xffffffff; int found = 0, ret; uint64_t freq; if (argc != 2) return -1; ret = sscanf(argv[0], "%u", &dev_id); if (ret != 1) return -1; ret = sscanf(argv[1], "%u", &clk_id); if (ret != 1) return -1; autoadjust_table_init(table); strncpy(table[row][0], "Clock information", TABLE_MAX_ELT_LEN); row++; strncpy(table[row][0], "Device ID", TABLE_MAX_ELT_LEN); strncpy(table[row][1], "Clock ID", TABLE_MAX_ELT_LEN); strncpy(table[row][2], "Clock Name", TABLE_MAX_ELT_LEN); strncpy(table[row][3], "Status", TABLE_MAX_ELT_LEN); strncpy(table[row][4], "Clock Frequency", TABLE_MAX_ELT_LEN); for (found = 1, row = 0; row < soc_info.sci_info.num_clocks; row++) { if (dev_id != c[row].dev_id) continue; if (c[row].clk_id != clk_id) continue; snprintf(table[found + 1][0], TABLE_MAX_ELT_LEN, "%5d", c[row].dev_id); snprintf(table[found + 1][1], TABLE_MAX_ELT_LEN, "%5d", c[row].clk_id); strncpy(table[found + 1][2], c[row].clk_name, TABLE_MAX_ELT_LEN); strncpy(table[found + 1][3], ti_sci_cmd_get_clk_state(dev_id, c[row].clk_id), TABLE_MAX_ELT_LEN); ti_sci_cmd_get_clk_freq(c[row].dev_id, c[row].clk_id, &freq); snprintf(table[found + 1][4], TABLE_MAX_ELT_LEN, "%lu", freq); ti_sci_cmd_get_clk_parent(dev_id, clk_id, &parent_clk_id); strncpy(clk_name, c[row].clk_name, TABLE_MAX_ELT_LEN); clk_name_len = strnlen(clk_name, TABLE_MAX_ELT_LEN); found++; break; } if (found == 1) return -1; ret = autoadjust_table_generic_fprint(stdout, table, found + 1, 5, TABLE_HAS_TITLE | TABLE_HAS_SUBTITLE); if (ret != 0) return ret; /* List out the parents and Mark the one that is selected */ row = 0; autoadjust_table_init(table); strncpy(table[row][0], "Clock Parent information", TABLE_MAX_ELT_LEN); row++; strncpy(table[row][0], "Selected", TABLE_MAX_ELT_LEN); strncpy(table[row][1], "Clock ID", TABLE_MAX_ELT_LEN); strncpy(table[row][2], "Clock Name", TABLE_MAX_ELT_LEN); strncpy(table[row][3], "Status", TABLE_MAX_ELT_LEN); strncpy(table[row][4], "Clock Frequency", TABLE_MAX_ELT_LEN); for (found = 1, row = 0; row < soc_info.sci_info.num_clocks; row++) { int found_parent = 0; if (dev_id != c[row].dev_id) continue; if (c[row].clk_id == clk_id) continue; if (c[row].clk_id == parent_clk_id) found_parent = 1; else if (strncmp(c[row].clk_name, clk_name, clk_name_len)) continue; snprintf(table[found + 1][0], TABLE_MAX_ELT_LEN, "%5s", found_parent ? "==>" : ""); snprintf(table[found + 1][1], TABLE_MAX_ELT_LEN, "%5d", c[row].clk_id); strncpy(table[found + 1][2], c[row].clk_name, TABLE_MAX_ELT_LEN); strncpy(table[found + 1][3], ti_sci_cmd_get_clk_state(dev_id, c[row].clk_id), TABLE_MAX_ELT_LEN); ti_sci_cmd_get_clk_freq(c[row].dev_id, c[row].clk_id, &freq); snprintf(table[found + 1][4], TABLE_MAX_ELT_LEN, "%lu", freq); found++; } if (!found) return -1; return autoadjust_table_generic_fprint(stdout, table, found + 1, 5, TABLE_HAS_TITLE | TABLE_HAS_SUBTITLE); } int dump_devices_info(int argc, char *argv[]) { struct ti_sci_devices_info *p = soc_info.sci_info.devices_info; char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN]; uint32_t row = 0, dev_id; int found = 0, ret; autoadjust_table_init(table); strncpy(table[row][0], "Device ID", TABLE_MAX_ELT_LEN); strncpy(table[row][1], "Device Name", TABLE_MAX_ELT_LEN); strncpy(table[row][2], "Device Status", TABLE_MAX_ELT_LEN); if (argc) goto print_single_device; for (row = 0; row < soc_info.sci_info.num_devices; row++) { snprintf(table[row + 1][0], TABLE_MAX_ELT_LEN, "%5d", p[row].dev_id); strncpy(table[row + 1][1], p[row].name, TABLE_MAX_ELT_LEN); snprintf(table[row + 1][2], TABLE_MAX_ELT_LEN, "%s", ti_sci_cmd_get_device_status(p[row].dev_id)); } return autoadjust_table_print(table, row + 1, 3); print_single_device: ret = sscanf(argv[0], "%u", &dev_id); if (ret != 1) return -1; for (row = 0; row < soc_info.sci_info.num_devices; row++) { if (dev_id == p[row].dev_id) { snprintf(table[1][0], TABLE_MAX_ELT_LEN, "%5d", p[row].dev_id); strncpy(table[1][1], p[row].name, TABLE_MAX_ELT_LEN); snprintf(table[1][2], TABLE_MAX_ELT_LEN, "%s", ti_sci_cmd_get_device_status(p[row].dev_id)); found = 1; break; } } if (!found) return -1; return autoadjust_table_print(table, 2, 3); } static int dump_processors_info(int argc, char *argv[]) { struct ti_sci_processors_info *p = soc_info.sci_info.processors_info; char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN]; uint32_t row = 0, proc_id; int found = 0, ret; uint64_t freq; autoadjust_table_init(table); strncpy(table[row][0], "Device ID", TABLE_MAX_ELT_LEN); strncpy(table[row][1], "Processor ID", TABLE_MAX_ELT_LEN); strncpy(table[row][2], "Processor Name", TABLE_MAX_ELT_LEN); strncpy(table[row][3], "Processor State", TABLE_MAX_ELT_LEN); strncpy(table[row][4], "Processor Frequency", TABLE_MAX_ELT_LEN); if (argc) goto print_single_processor; for (row = 0; row < soc_info.sci_info.num_processors; row++) { snprintf(table[row + 1][0], TABLE_MAX_ELT_LEN, "%5d", p[row].dev_id); snprintf(table[row + 1][1], TABLE_MAX_ELT_LEN, "%7d", p[row].processor_id); strncpy(table[row + 1][2], p[row].name, TABLE_MAX_ELT_LEN); /* ToDo: Should we get the state from proc ops */ snprintf(table[row + 1][3], TABLE_MAX_ELT_LEN, "%s", ti_sci_cmd_get_device_status(p[row].dev_id)); ti_sci_cmd_get_clk_freq(p[row].dev_id, p[row].clk_id, &freq); snprintf(table[row + 1][4], TABLE_MAX_ELT_LEN, "%lu", freq); } return autoadjust_table_print(table, row + 1, 5); print_single_processor: ret = sscanf(argv[0], "%u", &proc_id); if (ret != 1) return -1; for (row = 0; row < soc_info.sci_info.num_processors; row++) { if (proc_id != p[row].processor_id) continue; snprintf(table[found + 1][0], TABLE_MAX_ELT_LEN, "%5d", p[row].dev_id); snprintf(table[found + 1][1], TABLE_MAX_ELT_LEN, "%7d", p[row].processor_id); strncpy(table[found + 1][2], p[row].name, TABLE_MAX_ELT_LEN); /* ToDo: Should we get the state from proc ops */ snprintf(table[found + 1][3], TABLE_MAX_ELT_LEN, "%s", ti_sci_cmd_get_device_status(p[row].dev_id)); ti_sci_cmd_get_clk_freq(p[row].dev_id, p[row].clk_id, &freq); snprintf(table[found + 1][4], TABLE_MAX_ELT_LEN, "%lu", freq); found++; break; } if (!found) return -1; return autoadjust_table_print(table, found + 1, 5); } static int dump_rm_resource(u_int32_t type, u_int32_t subtype, u_int32_t host_id, char *value) { struct ti_sci_rm_desc desc; int ret; ret = ti_sci_cmd_get_range(type, subtype, host_id, &desc); if (ret) return ret; if (desc.num_sec && desc.num) { /* Print Primary + Secondary range */ snprintf(value, TABLE_MAX_ELT_LEN, "[%5d +%4d] (%4d +%3d)", desc.start, desc.num, desc.start_sec, desc.num_sec); } else if (desc.num_sec) { /* Print blank + Secondary range */ snprintf(value, TABLE_MAX_ELT_LEN, "[ ] (%4d +%3d)", desc.start_sec, desc.num_sec); } else if (desc.num) { /* Print only Primary range */ snprintf(value, TABLE_MAX_ELT_LEN, "[%5d +%4d]", desc.start, desc.num); } else { *value = 0; } return 0; } static int dump_rm_info(int argc, char *argv[]) { uint32_t filter_host_id = 0, filter_type = 0, filter_subtype = 0xFFF; char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN]; struct ti_sci_host_info *h = soc_info.sci_info.host_info; struct ti_sci_rm_info *r = soc_info.sci_info.rm_info; uint32_t type, subtype, host_id, host_valid; char cell[TABLE_MAX_ELT_LEN], *host_name; uint32_t i, j, row, col; int ret; if (argc > 0 && !strcmp(argv[0], "-h")) { if (argc == 1) return -1; sscanf(argv[1], "%u", &filter_host_id); argc -= 2; argv += 2; } if (argc > 0) { sscanf(argv[0], "%u", &filter_type); argc--; argv++; } if (argc > 0) { sscanf(argv[0], "%u", &filter_subtype); argc--; argv++; } autoadjust_table_init(table); snprintf(table[0][0], TABLE_MAX_ELT_LEN, "Resource allocation => [Primary start +count] (Secondary start +count)"); snprintf(table[1][0], TABLE_MAX_ELT_LEN, "utype"); snprintf(table[1][1], TABLE_MAX_ELT_LEN, "type"); snprintf(table[1][2], TABLE_MAX_ELT_LEN, "subtype"); row = 2; col = 3; for (i = 0; i < soc_info.sci_info.num_hosts; i++) { host_valid = 0; host_id = h[i].host_id; host_name = h[i].host_name; if (filter_host_id && host_id != filter_host_id) continue; row = 2; for (j = 0; j < soc_info.sci_info.num_res; j++) { type = r[j].utype >> 6; subtype = r[j].utype & 0x3F; if (filter_type && type != filter_type) continue; if (filter_subtype != 0xFFF && subtype != filter_subtype) continue; snprintf(table[row][0], TABLE_MAX_ELT_LEN, "0x%04x", r[j].utype); snprintf(table[row][1], TABLE_MAX_ELT_LEN, "%d", type); snprintf(table[row][2], TABLE_MAX_ELT_LEN, "%d", subtype); ret = dump_rm_resource(type, subtype, host_id, cell); if (ret) return ret; if (!cell[0]) { row++; continue; } host_valid = 1; snprintf(table[row][col], TABLE_MAX_ELT_LEN, "%s", cell); row++; } if (!host_valid) continue; snprintf(table[1][col], TABLE_MAX_ELT_LEN, "%s", host_name); col++; } return autoadjust_table_generic_fprint(stdout, table, row, col, TABLE_HAS_TITLE | TABLE_HAS_SUBTITLE); } int process_dump_command(int argc, char *argv[]) { int ret; if (argc < 1) { help(HELP_DUMP); return -1; } if (!strncmp(argv[0], "device", 6)) { argc--; argv++; ret = dump_devices_info(argc, argv); if (ret) { fprintf(stderr, "Invalid device arguments\n"); help(HELP_DUMP_DEVICE); } } else if (!strncmp(argv[0], "clock", 5)) { argc--; argv++; ret = dump_clocks_info(argc, argv); if (ret) { fprintf(stderr, "Invalid clock arguments\n"); help(HELP_DUMP_CLOCK); } } else if (!strncmp(argv[0], "parent_clock", 12)) { argc--; argv++; ret = dump_clock_parent_info(argc, argv); if (ret) { fprintf(stderr, "Invalid clock_parent arguments\n"); help(HELP_DUMP_CLOCK_PARENT); } } else if(!strncmp(argv[0], "processor", 9)) { argc--; argv++; ret = dump_processors_info(argc, argv); if (ret) help(HELP_DUMP_PROCESSOR); } else if(!strncmp(argv[0], "rm", 2)) { argc--; argv++; ret = dump_rm_info(argc, argv); if (ret) { fprintf(stderr, "Invalid arguments\n"); help(HELP_DUMP_RM); } } else if (!strcmp(argv[0], "--help")) { help(HELP_DUMP); return 0; } else { fprintf(stderr, "Invalid argument %s\n", argv[1]); help(HELP_DUMP); return -1; } return ret; } k3conf_0.3/common/cmd_rw.c0000664000175000017500000000751714504336513012470 0ustar /* * K3CONF Command Read and write * * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include int process_read_command(int argc, char *argv[]) { uint64_t addr = 0; int ret, num_read_bits = 32; if (argc < 1) { help(HELP_READ); return -1; } ret = sscanf(argv[0], "%lx", &addr); if (ret != 1) { help(HELP_READ); return -1; } if (argc == 2) { ret = sscanf(argv[1], "%d", &num_read_bits); if (ret != 1) { help(HELP_READ); return -1; } } switch (num_read_bits) { case 8: fprintf(stdout, "Value at addr 0x%lx = 0x%x\n\n", addr, mmio_read_8(addr)); break; case 16: fprintf(stdout, "Value at addr 0x%lx = 0x%x\n\n", addr, mmio_read_16(addr)); break; case 32: fprintf(stdout, "Value at addr 0x%lx = 0x%x\n\n", addr, mmio_read_32(addr)); break; case 64: fprintf(stdout, "Value at addr 0x%lx = 0x%lx\n\n", addr, mmio_read_64(addr)); break; default: fprintf(stdout, "Wrong input size, expected input size is 8,16,32,64\n"); return -1; }; return 0; } int process_write_command(int argc, char *argv[]) { unsigned long val; uint64_t addr; int ret, num_write_bits = 32; if (argc < 2) { help(HELP_WRITE); return -1; } ret = sscanf(argv[0], "%lx", &addr); if (ret != 1) { help(HELP_WRITE); return -1; } ret = sscanf(argv[1], "%lx", &val); if (ret != 1) { help(HELP_WRITE); return -1; } if (argc == 3) { ret = sscanf(argv[2], "%d", &num_write_bits); if (ret != 1) { help(HELP_READ); return -1; } } switch (num_write_bits) { case 8: mmio_write_8(addr, val); fprintf(stdout, "Value at addr 0x%lx = 0x%x\n\n", addr, mmio_read_8(addr)); break; case 16: mmio_write_16(addr, val); fprintf(stdout, "Value at addr 0x%lx = 0x%x\n\n", addr, mmio_read_16(addr)); break; case 32: mmio_write_32(addr, val); fprintf(stdout, "Value at addr 0x%lx = 0x%x\n\n", addr, mmio_read_32(addr)); break; case 64: mmio_write_64(addr, val); fprintf(stdout, "Value at addr 0x%lx = 0x%lx\n\n", addr, mmio_read_64(addr)); break; default: fprintf(stdout, "Wrong input size, expected input size is 8,16,32,64\n"); return -1; }; return 0; } k3conf_0.3/common/mmio.c0000664000175000017500000001201614504336513012144 0ustar /* * K3CONF mmio helpers * * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla * Nishanth Menon * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #define MEMORY "/dev/mem" unsigned page_size, mapped_size, offset_in_page; void *map_base, *virt_addr; int fd; static int warn_user_once = 0; static int map_address(off_t target) { unsigned int width = 8 * sizeof(uint64_t); uid_t uid = getuid(); uid_t euid = geteuid(); /* Ensure that user privilege is proper */ if (uid || uid != euid) { if (!warn_user_once) fprintf(stderr, "Missing sudo to access %s?\n", MEMORY); warn_user_once = 1; return NON_ROOT_USER; } fd = open(MEMORY, (O_RDWR | O_SYNC)); if (fd < 0) { fprintf(stderr, "Could not open %s!\n", MEMORY); return -5; } mapped_size = page_size = getpagesize(); offset_in_page = (unsigned)target & (page_size - 1); if (offset_in_page + width > page_size) { /* * This access spans pages. * Must map two pages to make it possible: */ mapped_size *= 2; } map_base = mmap(NULL, mapped_size, (PROT_READ | PROT_WRITE), MAP_SHARED, fd, target & ~(off_t) (page_size - 1)); if (map_base == MAP_FAILED) { fprintf(stderr, "Map fail\n"); return -1; } virt_addr = (char *)map_base + offset_in_page; return 0; } static uint64_t read_reg(int width) { uint64_t read_result = 0x0; switch (width) { case 8: read_result = *(volatile uint8_t *)virt_addr; break; case 16: read_result = *(volatile uint16_t *)virt_addr; break; case 32: read_result = *(volatile uint32_t *)virt_addr; break; case 64: read_result = *(volatile uint64_t *)virt_addr; break; default: fprintf(stderr, "bad width"); } return read_result; } static void write_reg(int width, uint64_t writeval) { switch (width) { case 8: *(volatile uint8_t *)virt_addr = writeval; break; case 16: *(volatile uint16_t *)virt_addr = writeval; break; case 32: *(volatile uint32_t *)virt_addr = writeval; break; case 64: *(volatile uint64_t *)virt_addr = writeval; break; default: fprintf(stderr, "bad width"); } } static void unmap_address(void) { if (munmap(map_base, mapped_size) == -1) fprintf(stderr, "munmap"); close(fd); } void mmio_write_8(uintptr_t addr, uint8_t value) { int r; r = map_address(addr); if (r) return; write_reg(8, value); unmap_address(); } uint8_t mmio_read_8(uintptr_t addr) { uint8_t v = 0; int r; r = map_address(addr); if (r) return 0; v = read_reg(8); unmap_address(); return v; } void mmio_write_16(uintptr_t addr, uint16_t value) { int r; r = map_address(addr); if (r) return; write_reg(16, value); unmap_address(); } uint16_t mmio_read_16(uintptr_t addr) { uint16_t v = 0; int r; r = map_address(addr); if (r) return 0; v = read_reg(16); unmap_address(); return v; } void mmio_write_32(uintptr_t addr, uint32_t value) { int r; r = map_address(addr); if (r) return; write_reg(32, value); unmap_address(); } uint32_t mmio_read_32(uintptr_t addr) { uint32_t v = 0; int r; r = map_address(addr); if (r) return 0; v = read_reg(32); unmap_address(); return v; } void mmio_write_64(uintptr_t addr, uint64_t value) { int r; r = map_address(addr); if (r) return; write_reg(64, value); unmap_address(); } uint64_t mmio_read_64(uintptr_t addr) { uint64_t v = 0; int r; r = map_address(addr); if (r) return 0; v = read_reg(64); unmap_address(); return v; } k3conf_0.3/common/autoadjust_table.c0000664000175000017500000003444114504336513014543 0ustar /* * Table printing Libraries * * Copyright (C) 2010-2019 Texas Instruments Incorporated - https://www.ti.com/ * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ #include #include #include #include /* #define AUTOADJUST_TABLE_DEBUG */ #ifdef AUTOADJUST_TABLE_DEBUG #define dprintf(format, ...) printf(format, ## __VA_ARGS__) #else #define dprintf(format, ...) #endif /* ------------------------------------------------------------------------*//** * @FUNCTION autoadjust_table_generic_fprint * @BRIEF print elements into a table which size automatically * adjusts. * @RETURNS 0 in case of success * -1 in case of incorrect pointer * -2 in case of memory allocation error * -3 one element of the table is longer than * TABLE_MAX_ELT_LEN * @param[in,out] stream: output file * @param[in] table: elements to be printed * format: table[row][col][string] * @param[in] row_nbr: number of rows * @param[in] col_nbr: number of columns * @param[in] flags: table format flags * @DESCRIPTION print elements into a table which size automatically * adjusts. The printed table depends on the format flags: * * TABLE_HAS_TITLE: * * |------------------------------------------------------------------| * | elements[0][0] | * |------------------------------------------------------------------| * | elements[1][0] | elements[1][1] | elements[1][col-1] | * | elements[2][0] | elements[2][1] | elements[2][col-1] | * | elements[row-1][0] | elements[row-1][1] | elements[row-1][col-1] | * |------------------------------------------------------------------| * * TABLE_HAS_SUBTITLE: * * |------------------------------------------------------------------| * | elements[0][0] | elements[0][1] | elements[0][col-1] | * |------------------------------------------------------------------| * | elements[1][0] | elements[1][1] | elements[1][col-1] | * | elements[2][0] | elements[2][1] | elements[2][col-1] | * | elements[row-1][0] | elements[row-1][1] | elements[row-1][col-1] | * |------------------------------------------------------------------| * * TABLE_HAS_TITLE | TABLE_HAS_SUBTITLE: * * |------------------------------------------------------------------| * | elements[0][0] | * |------------------------------------------------------------------| * | elements[1][0] | elements[1][1] | elements[1][col-1] | * |------------------------------------------------------------------| * | elements[2][0] | elements[2][1] | elements[2][col-1] | * | elements[row-1][0] | elements[row-1][1] | elements[row-1][col-1] | * |------------------------------------------------------------------| *//*------------------------------------------------------------------------ */ int autoadjust_table_generic_fprint(FILE *stream, char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN], unsigned int row_nbr, unsigned int col_nbr, unsigned int flags) { int has_title = !!(flags & TABLE_HAS_TITLE); unsigned int max_elt_size[TABLE_MAX_COL]; unsigned int total_dash_nbr = 0; unsigned int total_width = 0; char *dash_line = NULL; unsigned int col, row; unsigned int strln; char *title = NULL; char *line = NULL; unsigned int tmp; if (stream == NULL) { printf("autoadjust_table_fprint() error: stream == NULL!\n"); return -1; } if (table == NULL) { printf("autoadjust_table_fprint() error: table == NULL!\n"); return -1; } if (row_nbr > TABLE_MAX_ROW) { printf("autoadjust_table_fprint() error: row_nbr (%d) > " "TABLE_MAX_ROW (%d)!\n", row_nbr, TABLE_MAX_ROW); return -1; } if (col_nbr > TABLE_MAX_COL) { printf("autoadjust_table_fprint() error: col_nbr (%d) > " "TABLE_MAX_COL (%d)!\n", col_nbr, TABLE_MAX_COL); return -1; } if (has_title) title = table[0][0]; #ifdef AUTOADJUST_TABLE_DEBUG dprintf("row_nbr = %d, col_nbr = %d\n", row_nbr, col_nbr); for (row = 0; row < row_nbr; row++) { for (col = 0; col < col_nbr; col++) dprintf("element[%d][%d] = %s\n", row, col, table[row][col]); } #endif /* compute width of each column of the table */ for (col = 0; col < col_nbr; col++) max_elt_size[col] = 0; /* title length will be added to total width later */ row = has_title ? 1 : 0; for (; row < row_nbr; row++) { /* Get total length of strings in this line */ for (col = 0; col < col_nbr; col++) { strln = strlen(table[row][col]); if (strln > TABLE_MAX_ELT_LEN) { printf("%s(): WARNING: \"%s\" size (%u) > " "TABLE_MAX_ELT_LEN (%u)!\n", __func__, table[row][col], strln, TABLE_MAX_ELT_LEN); strln = TABLE_MAX_ELT_LEN; } if (strln > max_elt_size[col]) { max_elt_size[col] = strln; dprintf("new max_elt_size[%d] = %d\n", col, max_elt_size[col]); } } } /* Compute the total width of the table, and allocate memory for it */ for (col = 0; col < col_nbr; col++) total_width += max_elt_size[col]; /* Add number of '|' separators per line */ total_width += (col_nbr + 1); /* Add number of space character separators (2 per element) */ total_width += col_nbr * 2; /* Compensate if the title is longer than table width */ if (has_title) { unsigned int avail; strln = strlen(title); avail = total_width - 4; /* exclude left and right borders */ dprintf("title_width=%d\n", strln); if (avail < strln) { /* Number of chars to compensate per column */ tmp = (strln - avail + col_nbr - 1) / col_nbr; total_width = 0; for (col = 0; col < col_nbr; col++) { max_elt_size[col] += tmp; total_width += max_elt_size[col]; dprintf("new max_elt_size[%d] = %d\n", col, max_elt_size[col]); } /* Add number of separators per line */ total_width += (col_nbr + 1); total_width += col_nbr * 2; } } dprintf("total_width = %d\n", total_width); line = malloc(sizeof(char) * (total_width + 1)); if (line == NULL) { printf("autoadjust_table_fprint(): line malloc error!\n"); return -2; } line[0] = '\0'; line[total_width] = '\0'; /* * Compute the total number of dash characters, * used to delimit the table, and allocate memory for it */ total_dash_nbr = total_width - 2; dash_line = malloc(sizeof(char) * (total_width + 1)); dprintf("total_dash_nbr = %d\n", total_dash_nbr); if (dash_line == NULL) { printf("autoadjust_table_fprint(): dash_line malloc error!\n"); free(line); return -2; } dash_line[0] = '\0'; dash_line[total_width] = '\0'; dprintf("total_dash_nbr=%d\n", total_dash_nbr); dprintf("total_width=%d\n", total_width); /* Print table */ dash_line[0] = '|'; memset(dash_line + sizeof(char), '-', total_dash_nbr); dash_line[total_dash_nbr + 1] = '|'; fprintf(stream, "%s\n", dash_line); row = 0; if (has_title) { strcpy(line, "| "); strcat(line, title); tmp = total_width - 4 - strlen(title); while (tmp--) strcat(line, " "); strcat(line, " |"); fprintf(stream, "%s\n", line); fprintf(stream, "%s\n", dash_line); row++; } for (; row < row_nbr; row++) { strcpy(line, "|"); for (col = 0; col < col_nbr; col++) { strcat(line, " "); strncat(line, table[row][col], TABLE_MAX_ELT_LEN); if (strlen(table[row][col]) != TABLE_MAX_ELT_LEN) { for (tmp = strlen(table[row][col]); tmp < max_elt_size[col]; tmp++) strcat(line, " "); } strcat(line, " |"); } fprintf(stream, "%s\n", line); if (flags & TABLE_HAS_SUBTITLE) { fprintf(stream, "%s\n", dash_line); flags &= ~TABLE_HAS_SUBTITLE; } } fprintf(stream, "%s\n\n", dash_line); free(dash_line); free(line); return 0; } /* ------------------------------------------------------------------------*//** * @FUNCTION autoadjust_table_fprint * @BRIEF print elements into a table which size automatically * adjusts. * @RETURNS 0 in case of success * -1 in case of incorrect pointer * -2 in case of memory allocation error * -3 one element of the table is longer than * TABLE_MAX_ELT_LEN * @param[in,out] stream: output file * @param[in] table: elements to be printed * format: table[row][col][string] * @param[in] row_nbr: number of rows * @param[in] col_nbr: number of columns * @DESCRIPTION print elements into a table which size automatically * adjusts. The printed table looks like this: * |------------------------------------------------------------------| * | elements[0][0] | elements[0][1] | elements[0][col-1] | * |------------------------------------------------------------------| * | elements[1][0] | elements[1][1] | elements[1][col-1] | * | elements[2][0] | elements[2][1] | elements[2][col-1] | * | elements[row-1][0] | elements[row-1][1] | elements[row-1][col-1] | * |------------------------------------------------------------------| *//*------------------------------------------------------------------------ */ int autoadjust_table_fprint(FILE *stream, char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN], unsigned int row_nbr, unsigned int col_nbr) { return autoadjust_table_generic_fprint(stream, table, row_nbr, col_nbr, TABLE_HAS_SUBTITLE); } /* ------------------------------------------------------------------------*//** * @FUNCTION autoadjust_table_print * @BRIEF print to console elements into a table which size * automatically adjusts. * @RETURNS 0 in case of success * -1 in case of incorrect pointer * -2 in case of memory allocation error * -3 one element of the table is longer than * TABLE_MAX_ELT_LEN * @param[in] table: elements to be printed * format: table[row][col][string] * @param[in] row_nbr: number of rows * @param[in] col_nbr: number of columns * @DESCRIPTION print to console elements into a table which size * automatically adjusts. The printed table is like this: * |------------------------------------------------------------------| * | elements[0][0] | elements[0][1] | elements[0][col-1] | * |------------------------------------------------------------------| * | elements[1][0] | elements[1][1] | elements[1][col-1] | * | elements[2][0] | elements[2][1] | elements[2][col-1] | * | elements[row-1][0] | elements[row-1][1] | elements[row-1][col-1] | * |------------------------------------------------------------------| *//*------------------------------------------------------------------------ */ int autoadjust_table_print( char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN], unsigned int row_nbr, unsigned int col_nbr) { return autoadjust_table_fprint(stdout, table, row_nbr, col_nbr); } /* ------------------------------------------------------------------------*//** * @FUNCTION autoadjust_table_strncpy * @BRIEF copy string into table element, making sure it can fit. * @RETURNS 0 in case of success * -1 in case of incorrect argument(s) * -3 one element of the table longer than * TABLE_MAX_ELT_LEN * @param[in,out] table: elements to be printed * format: table[row][col][string] * @param[in] row: number of rows * @param[in] col: number of columns * @param[in] s: string to copy * @DESCRIPTION copy string into table element, making sure it can fit. *//*------------------------------------------------------------------------ */ int autoadjust_table_strncpy( char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN], unsigned int row, unsigned int col, char s[TABLE_MAX_ELT_LEN]) { if (table == NULL) { fprintf(stderr, "%s(): table == NULL!!!\n", __func__); return -1; } if (s == NULL) { fprintf(stderr, "%s(): s == NULL!!!\n", __func__); return -1; } if (row >= TABLE_MAX_ROW) { fprintf(stderr, "%s(): row (%u) >= TABLE_MAX_ROW (%u)\n", __func__, row, TABLE_MAX_ROW); return -1; } if (col >= TABLE_MAX_COL) { fprintf(stderr, "%s(): col (%u) >= TABLE_MAX_COL (%u)\n", __func__, col, TABLE_MAX_COL); return -1; } if (strlen(s) >= TABLE_MAX_ELT_LEN) { fprintf(stderr, "%s(): " "strlen(%s)=%lu >= TABLE_MAX_ELT_LEN (%u)!\n", __func__, s, strlen(s), TABLE_MAX_ELT_LEN); return -3; } strncpy(table[row][col], s, TABLE_MAX_ELT_LEN); return 0; } /* ------------------------------------------------------------------------*//** * @FUNCTION autoadjust_table_init * @BRIEF fill table with empty strings * @RETURNS 0 in case of success * -1 in case of incorrect pointer * @param[in,out] table: table to fill with empty strings * @DESCRIPTION fill table with empty strings, so that user does not * need to fill empty cell(s). *//*------------------------------------------------------------------------ */ int autoadjust_table_init( char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN]) { unsigned int col, row; if (table == NULL) { printf("autoadjust_table_init() error: table == NULL!\n"); return -1; } for (row = 0; row < TABLE_MAX_ROW; row++) for (col = 0; col < TABLE_MAX_COL; col++) table[row][col][0] = '\0'; return 0; } k3conf_0.3/common/help.c0000664000175000017500000002250114605602064012132 0ustar /* * Help Library for K3CONF * * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #define HELP_CLK_SET_PARENT_URL1 "http://downloads.ti.com/tisci/esd/latest/2_tisci_msgs/pm/clocks.html#power-management-clock-frequency-configuration-example-with-mux-programming" #define HELP_CLK_SET_PARENT_URL2 "http://downloads.ti.com/tisci/esd/latest/2_tisci_msgs/pm/clocks.html#tisci-msg-set-clock-parent" void help(help_category cat) { if (cat >= HELP_CATEGORY_MAX) { fprintf(stderr, "help called with incorrect category!!! (%d)\n", cat); return; } if ((cat == HELP_ALL) || (cat == HELP_USAGE)) { printf("\n"); printf("NAME\n"); printf(" k3conf - TI K3 Configuration Diagnostic Tool\n"); printf("\n"); printf("SYNOPSIS\n"); printf(" k3conf [--host ] [--version] [--help] [--cpuinfo] []\n"); if (cat == HELP_USAGE) { printf("\n"); printf(" See 'k3conf --help' for more information.\n"); printf("\n"); } } if (cat == HELP_ALL) { printf("\n"); printf("DESCRIPTION\n"); printf(" k3conf is standalone application designed to provide a quick'n easy way to \n" " diagnose/debug/audit TI K3 architecture based processors configuration at\n" " runtime, with no particular kernel dependency.\n"); printf(" k3conf is designed to be as much platform-agnostic as possible, being able to \n" " run on any Linux platform and easily ported to other OS.\n"); printf(" Even if k3conf today focuses mainly on TISCI related functionality, it is \n" " intended to be extended to any other area.\n"); printf("\n"); printf("OPTIONS\n"); printf(" --host \n"); printf(" Use this host id for communicating with sysfw\n"); printf("\n"); printf(" --help\n"); printf(" Print k3conf help.\n"); printf("\n"); printf(" --version\n"); printf(" Print k3conf version.\n"); printf("\n"); printf(" --cpuinfo\n"); printf(" Print the host processor information.\n"); } if (cat != HELP_USAGE) { printf("\n"); printf("COMMANDS\n"); } if ((cat == HELP_ALL) || (cat == HELP_SHOW) || (cat == HELP_SHOW_HOST)) { printf("\n"); printf(" k3conf show hosts\n"); printf(" Prints all the available TISCI hosts\n"); } if ((cat == HELP_ALL) || (cat == HELP_SHOW) || (cat == HELP_SHOW_SEC_PROXY)) { printf("\n"); printf(" k3conf show threads\n"); printf(" Prints all the available TISCI secure proxy threads\n"); } if ((cat == HELP_ALL) || (cat == HELP_SHOW) || (cat == HELP_SHOW_DEVICE)) { printf("\n"); printf(" k3conf show device\n"); printf(" Prints all the available TISCI devices\n"); printf("\n"); printf(" k3conf show device \n"); printf(" Prints the corresponding device id information\n"); } if ((cat == HELP_ALL) || (cat == HELP_SHOW) || (cat == HELP_SHOW_CLOCK)) { printf("\n k3conf show clock\n"); printf(" Prints all the available TISCI clocks\n"); printf("\n k3conf show clock \n"); printf(" Prints the clocks for corresponding device id\n"); } if ((cat == HELP_ALL) || (cat == HELP_SHOW) || (cat == HELP_SHOW_PROCESSOR)) { printf("\n"); printf(" k3conf show processor\n"); printf(" Prints all the available TISCI processors\n"); } if ((cat == HELP_ALL) || (cat == HELP_SHOW) || (cat == HELP_SHOW_RM)) { printf("\n"); printf(" k3conf show rm\n"); printf(" Prints resources managed by System firmware\n"); printf("\n"); printf(" k3conf show rm \n"); printf(" Prints resources managed by System firmware for corresponding device\n"); } if ((cat == HELP_ALL) || (cat == HELP_DUMP) || (cat == HELP_DUMP_DEVICE)) { printf("\n"); printf(" k3conf dump device\n"); printf(" Prints device status of all the TISCI devices\n"); printf("\n"); printf(" k3conf dump device \n"); printf(" Prints the corresponding device id status\n"); } if ((cat == HELP_ALL) || (cat == HELP_DUMP) || (cat == HELP_DUMP_CLOCK)) { printf("\n"); printf(" k3conf dump clock\n"); printf(" Prints clock status all the available TISCI clocks\n"); printf("\n"); printf(" k3conf dump clock \n"); printf(" Prints the available clock status for corresponding device id\n"); } if ((cat == HELP_ALL) || (cat == HELP_DUMP) || (cat == HELP_DUMP_CLOCK_PARENT)) { printf("\n"); printf(" k3conf dump parent_clock \n"); printf(" Prints the clock parent of provided clock\n"); } if ((cat == HELP_ALL) || (cat == HELP_DUMP) || (cat == HELP_DUMP_PROCESSOR)) { printf("\n"); printf(" k3conf dump processor\n"); printf(" Prints status of all the available TISCI processors\n"); printf("\n"); printf(" k3conf dump processor \n"); printf(" Prints status of the given TISCI processors\n"); } if ((cat == HELP_ALL) || (cat == HELP_DUMP) || (cat == HELP_DUMP_RM)) { printf("\n"); printf(" k3conf dump rm [OPTIONS]\n"); printf(" Prints resource allocation for all utypes / hosts\n"); printf("\n"); printf(" k3conf dump rm [OPTIONS] \n"); printf(" Prints resource allocation for corresponding type\n"); printf("\n"); printf(" k3conf dump rm [OPTIONS] \n"); printf(" Prints resource allocation for corresponding device/type\n"); printf("\n"); printf(" [OPTIONS]\n"); printf(" -h \n"); printf(" Filter only for corresponding host_id\n"); } if ((cat == HELP_ALL) || (cat == HELP_ENABLE) || (cat == HELP_ENABLE_DEVICE)) { printf("\n"); printf(" k3conf enable device \n"); printf(" Enables the TISCI device and prints the status\n"); } if ((cat == HELP_ALL) || (cat == HELP_ENABLE) || (cat == HELP_ENABLE_CLOCK)) { printf("\n"); printf(" k3conf enable clock \n"); printf(" Enables the TISCI clock and prints the status\n"); } if ((cat == HELP_ALL) || (cat == HELP_DISABLE) || (cat == HELP_DISABLE_DEVICE)) { printf("\n"); printf(" k3conf disable device \n"); printf(" Disables the TISCI device and prints the status\n"); } if ((cat == HELP_ALL) || (cat == HELP_DISABLE) || (cat == HELP_DISABLE_CLOCK)) { printf("\n"); printf(" k3conf disable clock \n"); printf(" Disables the TISCI clock and prints the status\n"); } if ((cat == HELP_ALL) || (cat == HELP_SET) || (cat == HELP_SET_CLOCK)) { printf("\n"); printf(" k3conf set clock \n"); printf(" Sets the clock frequency and prints the status\n"); } if ((cat == HELP_ALL) || (cat == HELP_SET) || (cat == HELP_SET_CLOCK_PARENT)) { printf("\n"); printf(" k3conf set parent_clock \n"); printf(" Sets the parent clock for a clock mux and prints the mux status\n"); printf(" Refer to the following documentation for preconditions:\n"); printf(" %s\n", HELP_CLK_SET_PARENT_URL1); printf(" %s\n", HELP_CLK_SET_PARENT_URL2); } if ((cat == HELP_ALL) || (cat == HELP_READ)) { printf("\n"); printf(" k3conf read []\n"); printf(" No.of bits to be read is given in the size argument\n"); printf(" Expected input size is 8,16,32,64\n"); printf(" Prints the value at the specified io memory\n"); } if ((cat == HELP_ALL) || (cat == HELP_WRITE)) { printf("\n"); printf(" k3conf write []\n"); printf(" No.of bits to be written is given in the size argument\n"); printf(" Expected input size is 8,16,32,64\n"); printf(" Writes the value at the specified io memory\n"); } if ((cat == HELP_ALL) || (cat == HELP_DUMP_DDRBW)) { printf("\n"); printf(" k3conf ddrbw \n"); printf(" Prints DDR bandwidth utilization on all DDR instances\n"); printf(" sample_duration is delay between samples in seconds (default: 1 second)\n"); printf(" count is number of samples to capture before stopping (default: -1 infinite)\n"); } } k3conf_0.3/common/socinfo.c0000664000175000017500000003767214522734227012666 0ustar /* * K3 SoC detection and helper apis * * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include /* Assuming these addresses and definitions stay common across K3 devices */ #define CTRLMMR_WKUP_JTAG_DEVICE_ID 0x43000018 #define DEVICE_ID_FAMILY_SHIFT 26 #define DEVICE_ID_FAMILY_MASK (0x3f << 26) #define DEVICE_ID_BASE_SHIFT 11 #define DEVICE_ID_BASE_MASK (0x1fff << 11) #define DEVICE_ID_SPEED_SHIFT 6 #define DEVICE_ID_SPEED_MASK (0x1f << 6) #define DEVICE_ID_TEMP_SHIFT 3 #define DEVICE_ID_TEMP_MASK (0x7 << 3) #define CTRLMMR_WKUP_JTAG_ID 0x43000014 #define JTAG_ID_VARIANT_SHIFT 28 #define JTAG_ID_VARIANT_MASK (0xf << 28) #define JTAG_ID_PARTNO_SHIFT 12 #define JTAG_ID_PARTNO_MASK (0xffff << 12) #define CTRLMMR_WKUP_DIE_ID0 0x43000020 #define CTRLMMR_WKUP_DIE_ID1 0x43000024 #define CTRLMMR_WKUP_DIE_ID2 0x43000028 #define CTRLMMR_WKUP_DIE_ID3 0x4300002c #define CTRLMMR_WKUP_DEVSTAT 0x43000030 #define CTRLMMR_WKUP_BOOTCFG 0x43000034 struct k3conf_soc_info soc_info; int soc_info_valid = 0; typedef enum { REV_1, REV_2, REV_PG_MAX } k3_soc_rev; static const char *soc_revision_j721e[] = { [REV_1] = " SR1.0", [REV_2] = " SR1.1", }; static const char *soc_revision_generic[] = { [REV_1] = " SR1.0", [REV_2] = " SR2.0", }; static void am654_init(void) { struct ti_sci_info *sci_info = &soc_info.sci_info; sci_info->host_info = am65x_host_info; sci_info->num_hosts = AM65X_MAX_HOST_IDS; sci_info->sp_info[MAIN_SEC_PROXY] = am65x_main_sp_info; sci_info->num_sp_threads[MAIN_SEC_PROXY] = AM65X_MAIN_SEC_PROXY_THREADS; sci_info->sp_info[MCU_SEC_PROXY] = am65x_mcu_sp_info; sci_info->num_sp_threads[MCU_SEC_PROXY] = AM65X_MCU_SEC_PROXY_THREADS; sci_info->processors_info = am65x_processors_info; sci_info->num_processors = AM65X_MAX_PROCESSORS_IDS; sci_info->devices_info = am65x_devices_info; sci_info->num_devices = AM65X_MAX_DEVICES; sci_info->clocks_info = am65x_clocks_info; sci_info->num_clocks = AM65X_MAX_CLOCKS; sci_info->rm_info = am65x_rm_info; sci_info->num_res = AM65X_MAX_RES; soc_info.host_id = DEFAULT_HOST_ID; soc_info.sec_proxy = &k3_generic_sec_proxy_base; } static void am654_sr2_init(void) { struct ti_sci_info *sci_info = &soc_info.sci_info; sci_info->host_info = am65x_sr2_host_info; sci_info->num_hosts = AM65X_SR2_MAX_HOST_IDS; sci_info->sp_info[MAIN_SEC_PROXY] = am65x_sr2_main_sp_info; sci_info->num_sp_threads[MAIN_SEC_PROXY] = AM65X_SR2_MAIN_SEC_PROXY_THREADS; sci_info->sp_info[MCU_SEC_PROXY] = am65x_sr2_mcu_sp_info; sci_info->num_sp_threads[MCU_SEC_PROXY] = AM65X_SR2_MCU_SEC_PROXY_THREADS; sci_info->processors_info = am65x_sr2_processors_info; sci_info->num_processors = AM65X_SR2_MAX_PROCESSORS_IDS; sci_info->devices_info = am65x_sr2_devices_info; sci_info->num_devices = AM65X_SR2_MAX_DEVICES; sci_info->clocks_info = am65x_sr2_clocks_info; sci_info->num_clocks = AM65X_SR2_MAX_CLOCKS; sci_info->rm_info = am65x_sr2_rm_info; sci_info->num_res = AM65X_SR2_MAX_RES; soc_info.host_id = DEFAULT_HOST_ID; soc_info.sec_proxy = &k3_generic_sec_proxy_base; } static void j721s2_init(void) { struct ti_sci_info *sci_info = &soc_info.sci_info; sci_info->sp_info[MAIN_SEC_PROXY] = j721s2_main_sp_info; sci_info->num_sp_threads[MAIN_SEC_PROXY] = J721S2_MAIN_SEC_PROXY_THREADS; sci_info->sp_info[MCU_SEC_PROXY] = j721s2_mcu_sp_info; sci_info->num_sp_threads[MCU_SEC_PROXY] = J721S2_MCU_SEC_PROXY_THREADS; sci_info->rm_info = j721s2_rm_info; sci_info->num_res = J721S2_MAX_RES; sci_info->host_info = j721s2_host_info; sci_info->num_hosts = J721S2_MAX_HOST_IDS; sci_info->clocks_info = j721s2_clocks_info; sci_info->num_clocks = J721S2_MAX_CLOCKS; sci_info->devices_info = j721s2_devices_info; sci_info->num_devices = J721S2_MAX_DEVICES; sci_info->processors_info = j721s2_processors_info; sci_info->num_processors = J721S2_MAX_PROCESSORS_IDS; soc_info.host_id = DEFAULT_HOST_ID; soc_info.sec_proxy = &k3_generic_sec_proxy_base; } static void j721e_init(void) { struct ti_sci_info *sci_info = &soc_info.sci_info; sci_info->host_info = j721e_host_info; sci_info->num_hosts = J721E_MAX_HOST_IDS; sci_info->sp_info[MAIN_SEC_PROXY] = j721e_main_sp_info; sci_info->num_sp_threads[MAIN_SEC_PROXY] = J721E_MAIN_SEC_PROXY_THREADS; sci_info->sp_info[MCU_SEC_PROXY] = j721e_mcu_sp_info; sci_info->num_sp_threads[MCU_SEC_PROXY] = J721E_MCU_SEC_PROXY_THREADS; sci_info->processors_info = j721e_processors_info; sci_info->num_processors = J721E_MAX_PROCESSORS_IDS; sci_info->devices_info = j721e_devices_info; sci_info->num_devices = J721E_MAX_DEVICES; sci_info->clocks_info = j721e_clocks_info; sci_info->num_clocks = J721E_MAX_CLOCKS; sci_info->rm_info = j721e_rm_info; sci_info->num_res = J721E_MAX_RES; soc_info.host_id = DEFAULT_HOST_ID; soc_info.sec_proxy = &k3_generic_sec_proxy_base; soc_info.ddr_perf_info = &j721e_ddr_perf_info; } static void j7200_init(void) { struct ti_sci_info *sci_info = &soc_info.sci_info; sci_info->host_info = j7200_host_info; sci_info->num_hosts = J7200_MAX_HOST_IDS; sci_info->sp_info[MAIN_SEC_PROXY] = j7200_main_sp_info; sci_info->num_sp_threads[MAIN_SEC_PROXY] = J7200_MAIN_SEC_PROXY_THREADS; sci_info->sp_info[MCU_SEC_PROXY] = j7200_mcu_sp_info; sci_info->num_sp_threads[MCU_SEC_PROXY] = J7200_MCU_SEC_PROXY_THREADS; sci_info->processors_info = j7200_processors_info; sci_info->num_processors = J7200_MAX_PROCESSORS_IDS; sci_info->devices_info = j7200_devices_info; sci_info->num_devices = J7200_MAX_DEVICES; sci_info->clocks_info = j7200_clocks_info; sci_info->num_clocks = J7200_MAX_CLOCKS; sci_info->rm_info = j7200_rm_info; sci_info->num_res = J7200_MAX_RES; soc_info.host_id = DEFAULT_HOST_ID; soc_info.sec_proxy = &k3_generic_sec_proxy_base; soc_info.ddr_perf_info = &j7200_ddr_perf_info; } static void am64x_init(void) { struct ti_sci_info *sci_info = &soc_info.sci_info; sci_info->host_info = am64x_host_info; sci_info->num_hosts = AM64X_MAX_HOST_IDS; sci_info->sp_info[MAIN_SEC_PROXY] = am64x_main_sp_info; sci_info->num_sp_threads[MAIN_SEC_PROXY] = AM64X_MAIN_SEC_PROXY_THREADS; sci_info->sp_info[MCU_SEC_PROXY] = NULL; sci_info->num_sp_threads[MCU_SEC_PROXY] = 0; sci_info->processors_info = am64x_processors_info; sci_info->num_processors = AM64X_MAX_PROCESSORS_IDS; sci_info->devices_info = am64x_devices_info; sci_info->num_devices = AM64X_MAX_DEVICES; sci_info->clocks_info = am64x_clocks_info; sci_info->num_clocks = AM64X_MAX_CLOCKS; sci_info->rm_info = am64x_rm_info; sci_info->num_res = AM64X_MAX_RES; soc_info.host_id = 13; soc_info.sec_proxy = &k3_lite_sec_proxy_base; } static void am62x_init(void) { struct ti_sci_info *sci_info = &soc_info.sci_info; sci_info->sp_info[MAIN_SEC_PROXY] = am62x_main_sp_info; sci_info->num_sp_threads[MAIN_SEC_PROXY] = AM62X_MAIN_SEC_PROXY_THREADS; sci_info->sp_info[MCU_SEC_PROXY] = NULL; sci_info->num_sp_threads[MCU_SEC_PROXY] = 0; sci_info->rm_info = am62x_rm_info; sci_info->num_res = AM62X_MAX_RES; sci_info->processors_info = am62x_processors_info; sci_info->num_processors = AM62X_MAX_PROCESSORS_IDS; sci_info->host_info = am62x_host_info; sci_info->num_hosts = AM62X_MAX_HOST_IDS; sci_info->devices_info = am62x_devices_info; sci_info->num_devices = AM62X_MAX_DEVICES; sci_info->clocks_info = am62x_clocks_info; sci_info->num_clocks = AM62X_MAX_CLOCKS; soc_info.host_id = 13; soc_info.sec_proxy = &k3_lite_sec_proxy_base; soc_info.ddr_perf_info = &am62x_ddr_perf_info; } static void j784s4_init(void) { struct ti_sci_info *sci_info = &soc_info.sci_info; sci_info->clocks_info = j784s4_clocks_info; sci_info->num_clocks = J784S4_MAX_CLOCKS; sci_info->devices_info = j784s4_devices_info; sci_info->num_devices = J784S4_MAX_DEVICES; sci_info->host_info = j784s4_host_info; sci_info->num_hosts = J784S4_MAX_HOST_IDS; sci_info->processors_info = j784s4_processors_info; sci_info->num_processors = J784S4_MAX_PROCESSORS_IDS; sci_info->rm_info = j784s4_rm_info; sci_info->num_res = J784S4_MAX_RES; sci_info->sp_info[MAIN_SEC_PROXY] = j784s4_main_sp_info; sci_info->num_sp_threads[MAIN_SEC_PROXY] = J784S4_MAIN_SEC_PROXY_THREADS; sci_info->sp_info[MCU_SEC_PROXY] = j784s4_mcu_sp_info; sci_info->num_sp_threads[MCU_SEC_PROXY] = J784S4_MCU_SEC_PROXY_THREADS; soc_info.host_id = DEFAULT_HOST_ID; soc_info.sec_proxy = &k3_generic_sec_proxy_base; } static void am62ax_init(void) { struct ti_sci_info *sci_info = &soc_info.sci_info; sci_info->clocks_info = am62ax_clocks_info; sci_info->num_clocks = AM62AX_MAX_CLOCKS; sci_info->devices_info = am62ax_devices_info; sci_info->num_devices = AM62AX_MAX_DEVICES; sci_info->host_info = am62ax_host_info; sci_info->num_hosts = AM62AX_MAX_HOST_IDS; sci_info->processors_info = am62ax_processors_info; sci_info->num_processors = AM62AX_MAX_PROCESSORS_IDS; sci_info->rm_info = am62ax_rm_info; sci_info->num_res = AM62AX_MAX_RES; sci_info->sp_info[MAIN_SEC_PROXY] = am62ax_main_sp_info; sci_info->num_sp_threads[MAIN_SEC_PROXY] = AM62AX_MAIN_SEC_PROXY_THREADS; sci_info->sp_info[MCU_SEC_PROXY] = am62ax_mcu_sp_info; sci_info->num_sp_threads[MCU_SEC_PROXY] = AM62AX_MCU_SEC_PROXY_THREADS; soc_info.host_id = 13; soc_info.sec_proxy = &k3_lite_sec_proxy_base; } static void am62px_init(void) { struct ti_sci_info *sci_info = &soc_info.sci_info; sci_info->clocks_info = am62px_clocks_info; sci_info->num_clocks = AM62PX_MAX_CLOCKS; sci_info->devices_info = am62px_devices_info; sci_info->num_devices = AM62PX_MAX_DEVICES; sci_info->host_info = am62px_host_info; sci_info->num_hosts = AM62PX_MAX_HOST_IDS; sci_info->processors_info = am62px_processors_info; sci_info->num_processors = AM62PX_MAX_PROCESSORS_IDS; sci_info->rm_info = am62px_rm_info; sci_info->num_res = AM62PX_MAX_RES; sci_info->sp_info[MAIN_SEC_PROXY] = am62px_main_sp_info; sci_info->num_sp_threads[MAIN_SEC_PROXY] = AM62PX_MAIN_SEC_PROXY_THREADS; sci_info->sp_info[MCU_SEC_PROXY] = am62px_mcu_sp_info; sci_info->num_sp_threads[MCU_SEC_PROXY] = AM62PX_MCU_SEC_PROXY_THREADS; soc_info.host_id = 13; soc_info.sec_proxy = &k3_lite_sec_proxy_base; } int soc_init(uint32_t host_id) { memset(&soc_info, 0, sizeof(soc_info)); uint32_t soc = (mmio_read_32(CTRLMMR_WKUP_JTAG_ID) & JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT; k3_soc_rev rev = (mmio_read_32(CTRLMMR_WKUP_JTAG_ID) & JTAG_ID_VARIANT_MASK) >> JTAG_ID_VARIANT_SHIFT; switch (soc) { case AM65X: soc_info.soc_name = "AM65x"; break; case J721S2: soc_info.soc_name = "J721S2"; break; case J721E: soc_info.soc_name = "J721E"; break; case J7200: soc_info.soc_name = "J7200"; break; case AM64X: soc_info.soc_name = "AM64x"; break; case AM62X: soc_info.soc_name = "AM62X"; break; case AM62AX: soc_info.soc_name = "AM62Ax"; break; case AM62PX: soc_info.soc_name = "AM62Px"; break; case J784S4: soc_info.soc_name = "J784S4"; break; default: fprintf(stderr, "Unknown Silicon %d\n", soc); return SOC_INFO_UNKNOWN_SILICON; }; if (rev >= REV_PG_MAX) { fprintf(stderr, "Unknown Silicon revision %d for SoC %s\n", rev, soc_info.soc_name); return SOC_INFO_UNKNOWN_SILICON; } switch (soc) { case J721E: soc_info.rev_name = soc_revision_j721e[rev]; break; default: soc_info.rev_name = soc_revision_generic[rev]; }; if (soc == AM65X && rev == REV_1) am654_init(); else if (soc == AM65X && rev == REV_2) am654_sr2_init(); else if (soc == J721S2) j721s2_init(); else if (soc == J721E) j721e_init(); else if (soc == J7200) j7200_init(); else if (soc == AM64X) am64x_init(); else if (soc == AM62X) am62x_init(); else if (soc == AM62AX) am62ax_init(); else if (soc == AM62PX) am62px_init(); else if (soc == J784S4) j784s4_init(); if (host_id != INVALID_HOST_ID) soc_info.host_id = host_id; /* ToDo: Add error if sec_proxy_init/sci_init is failed */ if(!k3_sec_proxy_init()) if (!ti_sci_init()) soc_info.ti_sci_enabled = 1; soc_info_valid = 1; return 0; } k3conf_0.3/common/k3conf.c0000664000175000017500000001301714605602064012367 0ustar /* * K3CONF main entry file * * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include #include #include #ifdef DEBUG #define dprintf(format, ...) printf(format, ## __VA_ARGS__) #else #define dprintf(format, ...) #endif void k3conf_print_version(FILE *stream) { char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN]; struct ti_sci_version_info ver = soc_info.sci_info.version; uint32_t row = 0; if (stream == NULL) { fprintf(stderr, "%s(): stream == NULL!!!\n", __func__); return; } autoadjust_table_init(table); strncpy(table[row][0], "VERSION INFO", TABLE_MAX_ELT_LEN); row++; strncpy(table[row][0], "K3CONF", TABLE_MAX_ELT_LEN); snprintf(table[row][1], TABLE_MAX_ELT_LEN, "(version %s built %s)", k3conf_version, builddate); row++; /* Following information is only available if soc_info is valid */ if (!soc_info_valid) goto no_chip_info; strncpy(table[row][0], "SoC", TABLE_MAX_ELT_LEN); snprintf(table[row][1], TABLE_MAX_ELT_LEN, "%s%s", soc_info.soc_name, soc_info.rev_name); row++; if (soc_info.ti_sci_enabled) { strncpy(table[row][0], "SYSFW", TABLE_MAX_ELT_LEN); snprintf(table[row][1], TABLE_MAX_ELT_LEN, "ABI: %d.%d (firmware version 0x%04x '%.*s)')", ver.abi_major, ver.abi_minor, ver.firmware_version, (int)sizeof(ver.firmware_description), ver.firmware_description); row++; } no_chip_info: autoadjust_table_generic_fprint(stream, table, row, 2, TABLE_HAS_TITLE); return; } int main(int argc, char *argv[]) { uint32_t host_id; int ret = 0; /* Scan user arguments for options */ argc--; argv++; if (argc == 0) { help(HELP_USAGE); ret = -1; goto main_exit; } if (!strcmp(argv[0], "--help")) { help(HELP_ALL); goto main_exit; } host_id = INVALID_HOST_ID; if (!strcmp(argv[0], "--host")) { argc--; argv++; ret = sscanf(argv[0], "%u", &host_id); if (ret != 1) { fprintf(stderr, "Invalid host id %s\n", argv[0]); return -1; } dprintf("%s: host_id from user = %d\n", __func__, soc_info.host_id); argc--; argv++; } ret = soc_init(host_id); if (!strcmp(argv[0], "--version")) { k3conf_print_version(stdout); goto main_exit; } if (ret && ret != SOC_INFO_UNKNOWN_SILICON) { fprintf(stderr, "Unable to execute '%s' command: Potentially no access to memory\n", argv[0]); goto main_exit; } if (!strcmp(argv[0], "read")) { argc--; argv++; k3conf_print_version(stdout); return process_read_command(argc, argv); } if (!strcmp(argv[0], "write")) { argc--; argv++; k3conf_print_version(stdout); return process_write_command(argc, argv); } if (ret || !soc_info_valid) { ret = ret ? ret : -1; fprintf(stderr, "Unable to execute '%s' command - no access to memory or unable to detect silicon\n", argv[0]); goto main_exit; } if (!strcmp(argv[0], "--cpuinfo")) { k3conf_print_version(stdout); dump_cpu_info(); goto main_exit; } if (!strcmp(argv[0], "show")) { argc--; argv++; k3conf_print_version(stdout); return process_show_command(argc, argv); } if (!strcmp(argv[0], "dump")) { argc--; argv++; k3conf_print_version(stdout); return process_dump_command(argc, argv); } if (!strcmp(argv[0], "enable")) { argc--; argv++; k3conf_print_version(stdout); return process_enable_command(argc, argv); } if (!strcmp(argv[0], "disable")) { argc--; argv++; k3conf_print_version(stdout); return process_disable_command(argc, argv); } if (!strcmp(argv[0], "set")) { argc--; argv++; k3conf_print_version(stdout); return process_set_command(argc, argv); } if (!strcmp(argv[0], "ddrbw")) { argc--; argv++; k3conf_print_version(stdout); return ddrbw_info(argc, argv); } fprintf(stderr, "Invalid argument %s", argv[0]); help(HELP_USAGE); ret = -1; /* Fallthrough */ main_exit: return ret; } k3conf_0.3/common/cmd_set.c0000664000175000017500000001022214375734376012635 0ustar /* * K3CONF Command Set * * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #define HELP_SET_PARENT_URL1 "http://downloads.ti.com/tisci/esd/latest/2_tisci_msgs/pm/clocks.html#power-management-clock-frequency-configuration-example-with-mux-programming" #define HELP_SET_PARENT_URL2 "http://downloads.ti.com/tisci/esd/latest/2_tisci_msgs/pm/clocks.html#tisci-msg-set-clock-parent" static int set_clock(int argc, char *argv[]) { uint32_t dev_id, clk_id, ret; uint64_t freq; if (argc < 3) return -1; ret = sscanf(argv[0], "%u", &dev_id); if (ret != 1) return -1; ret = sscanf(argv[1], "%u", &clk_id); if (ret != 1) return -1; ret = sscanf(argv[2], "%lu", &freq); if (ret != 1) return -1; ret = ti_sci_cmd_set_clk_freq(dev_id, clk_id, freq); if (ret) return ret; return dump_clocks_info(argc, argv); } static int set_clock_parent(int argc, char *argv[]) { uint32_t dev_id, clk_id, parent_clk_id; int ret; if (argc < 3) return -1; ret = sscanf(argv[0], "%u", &dev_id); if (ret != 1) return -1; ret = sscanf(argv[1], "%u", &clk_id); if (ret != 1) return -1; ret = sscanf(argv[2], "%u", &parent_clk_id); if (ret != 1) return -1; ret = ti_sci_cmd_set_clk_parent(dev_id, clk_id, parent_clk_id); if (ret) { fprintf(stderr, "Request to set parent failed: %d\n",ret); fprintf(stderr, "Clock state is probably wrong!\n"); fprintf(stderr, "Clock state of clk_id %d: %s\n", clk_id, ti_sci_cmd_get_clk_state(dev_id, clk_id)); fprintf(stderr, "Clock state of parent_clk_id %d: %s\n", parent_clk_id, ti_sci_cmd_get_clk_state(dev_id, parent_clk_id)); fprintf(stderr, "\nRefer to:\n\t%s\n\t%s\n", HELP_SET_PARENT_URL1, HELP_SET_PARENT_URL2); return ret; } return dump_clock_parent_info(argc - 1, argv); } int process_set_command(int argc, char *argv[]) { int ret; if (argc < 1) { help(HELP_SET); return -1; } if (!strncmp(argv[0], "clock", 5)) { argc--; argv++; ret = set_clock(argc, argv); if (ret) { fprintf(stderr, "Invalid clock arguments\n"); help(HELP_SET_CLOCK); } } else if (!strncmp(argv[0], "parent_clock", 5)) { argc--; argv++; ret = set_clock_parent(argc, argv); if (ret) { if (ret == -1) { fprintf(stderr, "Invalid parent_clock arguments\n"); help(HELP_SET_CLOCK_PARENT); } } } else if (!strcmp(argv[0], "--help")) { help(HELP_SET); return 0; } else { fprintf(stderr, "Invalid argument %s\n", argv[1]); help(HELP_SET); return -1; } return ret; } k3conf_0.3/common/tisci/0000775000175000017500000000000014456530612012154 5ustar k3conf_0.3/common/tisci/tisci_clock.c0000664000175000017500000001523314375734376014627 0ustar /* * TISCI clock ops library * * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include static const char clock_state[MAX_CLOCK_HW_STATES + 1][MAX_CLOCK_STATE_LENGTH] = { [MSG_CLOCK_HW_STATE_NOT_READY] = "CLK_STATE_NOT_READY", [MSG_CLOCK_HW_STATE_READY] = "CLK_STATE_READY", [MAX_CLOCK_HW_STATES] = "CLK_STATE_UNKNOWN" }; static int ti_sci_set_clock_state(uint32_t dev_id, uint32_t clk_id, uint32_t flags, uint8_t state) { struct ti_sci_msg_req_set_clock_state *req; uint8_t buf[SEC_PROXY_MAX_MSG_SIZE]; struct k3_sec_proxy_msg msg; memset(buf, 0, sizeof(buf)); ti_sci_setup_header((struct ti_sci_msg_hdr *)buf, TI_SCI_MSG_SET_CLOCK_STATE, flags); req = (struct ti_sci_msg_req_set_clock_state *)buf; req->dev_id = dev_id; if (clk_id < 255) { req->clk_id = clk_id; } else { req->clk_id = 255; req->clk_id_32 = clk_id; } req->request_state = state; msg.len = sizeof(*req); msg.buf = buf; return ti_sci_xfer_msg(&msg); } int ti_sci_cmd_get_clk(uint32_t dev_id, uint32_t clk_id) { return ti_sci_set_clock_state(dev_id, clk_id, MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE, MSG_CLOCK_SW_STATE_REQ); } int ti_sci_cmd_put_clk(uint32_t dev_id, uint32_t clk_id) { return ti_sci_set_clock_state(dev_id, clk_id, MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE, MSG_CLOCK_SW_STATE_UNREQ); } const char *ti_sci_cmd_get_clk_state(uint32_t dev_id, uint32_t clk_id) { struct ti_sci_msg_resp_get_clock_state *resp; struct ti_sci_msg_req_get_clock_state *req; uint8_t buf[SEC_PROXY_MAX_MSG_SIZE]; struct k3_sec_proxy_msg msg; int ret; memset(buf, 0, sizeof(buf)); ti_sci_setup_header((struct ti_sci_msg_hdr *)buf, TI_SCI_MSG_GET_CLOCK_STATE, 0); req = (struct ti_sci_msg_req_get_clock_state *)buf; req->dev_id = dev_id; if (clk_id < 255) { req->clk_id = clk_id; } else { req->clk_id = 255; req->clk_id_32 = clk_id; } msg.len = sizeof(*req); msg.buf = buf; ret = ti_sci_xfer_msg(&msg); if (ret) return NULL; resp = (struct ti_sci_msg_resp_get_clock_state *)buf; return clock_state[resp->current_state]; } int ti_sci_cmd_set_clk_freq(uint32_t dev_id, uint32_t clk_id, uint64_t freq) { struct ti_sci_msg_req_set_clock_freq *req; uint8_t buf[SEC_PROXY_MAX_MSG_SIZE]; struct k3_sec_proxy_msg msg; memset(buf, 0, sizeof(buf)); ti_sci_setup_header((struct ti_sci_msg_hdr *)buf, TI_SCI_MSG_SET_CLOCK_FREQ, 0); req = (struct ti_sci_msg_req_set_clock_freq *)buf; req->dev_id = dev_id; if (clk_id < 255) { req->clk_id = clk_id; } else { req->clk_id = 255; req->clk_id_32 = clk_id; } /* ToDo: Get best match freq and set that freq */ req->min_freq_hz = freq; req->target_freq_hz = freq; req->max_freq_hz = freq; msg.len = sizeof(*req); msg.buf = buf; return ti_sci_xfer_msg(&msg); } int ti_sci_cmd_get_clk_freq(uint32_t dev_id, uint32_t clk_id, uint64_t *freq) { struct ti_sci_msg_resp_get_clock_freq *resp; struct ti_sci_msg_req_get_clock_freq *req; uint8_t buf[SEC_PROXY_MAX_MSG_SIZE]; struct k3_sec_proxy_msg msg; int ret; memset(buf, 0, sizeof(buf)); ti_sci_setup_header((struct ti_sci_msg_hdr *)buf, TI_SCI_MSG_GET_CLOCK_FREQ, 0); req = (struct ti_sci_msg_req_get_clock_freq *)buf; req->dev_id = dev_id; if (clk_id < 255) { req->clk_id = clk_id; } else { req->clk_id = 255; req->clk_id_32 = clk_id; } msg.len = sizeof(*req); msg.buf = buf; ret = ti_sci_xfer_msg(&msg); if (ret) return ret; resp = (struct ti_sci_msg_resp_get_clock_freq *)buf; *freq = resp->freq_hz; return 0; } int ti_sci_cmd_get_clk_parent(uint32_t dev_id, uint32_t clk_id, uint32_t *parent_clk_id) { struct ti_sci_msg_get_clock_parent_resp *resp; struct ti_sci_msg_get_clock_parent_req *req; uint8_t buf[SEC_PROXY_MAX_MSG_SIZE]; struct k3_sec_proxy_msg msg; int ret; memset(buf, 0, sizeof(buf)); ti_sci_setup_header((struct ti_sci_msg_hdr *)buf, TI_SCI_MSG_GET_CLOCK_PARENT, 0); req = (struct ti_sci_msg_get_clock_parent_req *)buf; req->dev_id = dev_id; if (clk_id < 255) { req->clk_id = clk_id; } else { req->clk_id = 255; req->clk_id_32 = clk_id; } msg.len = sizeof(*req); msg.buf = buf; ret = ti_sci_xfer_msg(&msg); if (ret) return ret; resp = (struct ti_sci_msg_get_clock_parent_resp *)buf; if (resp->parent_clk_id < 255) *parent_clk_id = resp->parent_clk_id; else *parent_clk_id = resp->parent_clk_id_32; return 0; } int ti_sci_cmd_set_clk_parent(uint32_t dev_id, uint32_t clk_id, uint32_t parent_clk_id) { struct ti_sci_msg_set_clock_parent_req *req; uint8_t buf[SEC_PROXY_MAX_MSG_SIZE]; struct k3_sec_proxy_msg msg; memset(buf, 0, sizeof(buf)); ti_sci_setup_header((struct ti_sci_msg_hdr *)buf, TI_SCI_MSG_SET_CLOCK_PARENT, 0); req = (struct ti_sci_msg_set_clock_parent_req *)buf; req->dev_id = dev_id; if (clk_id < 255) { req->clk_id = clk_id; } else { req->clk_id = 255; req->clk_id_32 = clk_id; } if (parent_clk_id < 255) { req->parent_clk_id = parent_clk_id; } else { req->parent_clk_id = 255; req->parent_clk_id_32 = parent_clk_id; } msg.len = sizeof(*req); msg.buf = buf; return ti_sci_xfer_msg(&msg); } k3conf_0.3/common/tisci/tisci_device.c0000664000175000017500000000653314375734376014776 0ustar /* * TISCI device ops library * * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include static const char device_state[MAX_DEVICE_HW_STATES + 1][MAX_DEVICE_STATE_LENGTH] = { [MSG_DEVICE_HW_STATE_OFF] = "DEVICE_STATE_OFF", [MSG_DEVICE_HW_STATE_ON] = "DEVICE_STATE_ON", [MSG_DEVICE_HW_STATE_TRANS] = "DEVICE_STATE_TRANS", [MAX_DEVICE_HW_STATES] = "DEVICE_STATE_UNKNOWN" }; static int ti_sci_set_device_state(uint32_t id, uint32_t flags, uint8_t state) { struct ti_sci_msg_req_set_device_state *req; uint8_t buf[SEC_PROXY_MAX_MSG_SIZE]; struct k3_sec_proxy_msg msg; memset(buf, 0, sizeof(buf)); ti_sci_setup_header((struct ti_sci_msg_hdr *)buf, TI_SCI_MSG_SET_DEVICE_STATE, flags); req = (struct ti_sci_msg_req_set_device_state *)buf; req->id = id; req->state = state; msg.len = sizeof(*req); msg.buf = buf; return ti_sci_xfer_msg(&msg); } int ti_sci_cmd_enable_device(uint32_t dev_id) { return ti_sci_set_device_state(dev_id, 0, MSG_DEVICE_SW_STATE_ON); } int ti_sci_cmd_disable_device(uint32_t dev_id) { return ti_sci_set_device_state(dev_id, 0, MSG_DEVICE_SW_STATE_AUTO_OFF); } const char *ti_sci_cmd_get_device_status(uint32_t dev_id) { struct ti_sci_msg_resp_get_device_state *resp; struct ti_sci_msg_req_get_device_state *req; uint8_t buf[SEC_PROXY_MAX_MSG_SIZE]; struct k3_sec_proxy_msg msg; int ret = 0; memset(buf, 0, sizeof(buf)); ti_sci_setup_header((struct ti_sci_msg_hdr *)buf, TI_SCI_MSG_GET_DEVICE_STATE, 0); req = (struct ti_sci_msg_req_get_device_state *)buf; req->id = dev_id; msg.len = sizeof(*req); msg.buf = buf; ret = ti_sci_xfer_msg(&msg); if (ret) return NULL; resp = (struct ti_sci_msg_resp_get_device_state *)buf; return device_state[resp->current_state]; } k3conf_0.3/common/tisci/tisci_core.c0000664000175000017500000000761414473720245014455 0ustar /* * TISCI core library * * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include static int seq = 0; void ti_sci_setup_header(struct ti_sci_msg_hdr *hdr, uint16_t type, uint32_t flags) { hdr->type = type; hdr->host = soc_info.host_id; hdr->seq = seq++; hdr->flags = TI_SCI_FLAG_REQ_ACK_ON_PROCESSED | flags; } int ti_sci_xfer_msg(struct k3_sec_proxy_msg *msg) { int ret; if (!msg->len || !msg->buf) return -1; ret = k3_sec_proxy_send(msg); if (ret) return ret; memset(msg->buf, 0, msg->len); ret = k3_sec_proxy_recv(msg); if (ret) return ret; if (!ti_sci_is_response_ack(msg->buf)) return -1; return 0; } int ti_sci_init(void) { struct ti_sci_msg_resp_version *version; struct ti_sci_version_info *glb_ver; uint8_t buf[SEC_PROXY_MAX_MSG_SIZE]; struct k3_sec_proxy_msg msg; int ret; memset(buf, 0, sizeof(buf)); ti_sci_setup_header((struct ti_sci_msg_hdr *)buf, TI_SCI_MSG_VERSION, 0); msg.len = sizeof(struct ti_sci_msg_hdr); msg.buf = buf; ret = ti_sci_xfer_msg(&msg); if (ret) return ret; version = (struct ti_sci_msg_resp_version *)buf; glb_ver = &soc_info.sci_info.version; glb_ver->abi_major = version->abi_major; glb_ver->abi_minor = version->abi_minor; glb_ver->firmware_version = version->version; strncpy(glb_ver->firmware_description, version->firmware_description, sizeof(glb_ver->firmware_description)); return 0; } int ti_sci_cmd_get_range(uint16_t type, uint16_t subtype, uint16_t host_id, struct ti_sci_rm_desc *desc) { struct ti_sci_msg_resp_get_resource_range *resp; struct ti_sci_msg_req_get_resource_range *req; uint8_t buf[SEC_PROXY_MAX_MSG_SIZE]; struct k3_sec_proxy_msg msg; int ret = 0; memset(buf, 0, sizeof(buf)); ti_sci_setup_header((struct ti_sci_msg_hdr *)buf, TI_SCI_MSG_GET_RESOURCE_RANGE, 0); req = (struct ti_sci_msg_req_get_resource_range *)buf; req->type = type; req->subtype = subtype; req->secondary_host = host_id; msg.len = sizeof(*req); msg.buf = buf; ret = ti_sci_xfer_msg(&msg); if (ret) return ret; resp = (struct ti_sci_msg_resp_get_resource_range *)buf; desc->start = resp->range_start; desc->num = resp->range_num; desc->start_sec = resp->range_start_sec; desc->num_sec = resp->range_num_sec; return 0; } k3conf_0.3/common/cmd_disable.c0000664000175000017500000000614714375734376013460 0ustar /* * K3CONF Command Disable * * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include static int disable_device(int argc, char *argv[]) { uint32_t dev_id, ret; if (argc < 1) return -1; ret = sscanf(argv[0], "%u", &dev_id); if (ret != 1) return -1; ret = ti_sci_cmd_disable_device(dev_id); if (ret) return ret; return dump_devices_info(argc, argv); } static int disable_clock(int argc, char *argv[]) { uint32_t dev_id, clk_id, ret; if (argc < 2) return -1; ret = sscanf(argv[0], "%u", &dev_id); if (ret != 1) return -1; ret = sscanf(argv[1], "%u", &clk_id); if (ret != 1) return -1; ret = ti_sci_cmd_put_clk(dev_id, clk_id); if (ret) return ret; return dump_clocks_info(argc, argv); } int process_disable_command(int argc, char *argv[]) { int ret; if (argc < 1) { help(HELP_DISABLE); return -1; } if (!strncmp(argv[0], "device", 6)) { argc--; argv++; ret = disable_device(argc, argv); if (ret) { fprintf(stderr, "Invalid device arguments\n"); help(HELP_DISABLE_DEVICE); } } else if (!strncmp(argv[0], "clock", 5)) { argc--; argv++; ret = disable_clock(argc, argv); if (ret) { fprintf(stderr, "Invalid clock arguments\n"); help(HELP_DISABLE_CLOCK); } } else if (!strcmp(argv[0], "--help")) { help(HELP_DISABLE); return 0; } else { fprintf(stderr, "Invalid argument %s\n", argv[1]); help(HELP_DISABLE); return -1; } return ret; } k3conf_0.3/.settings/0000775000175000017500000000000014456001511011456 5ustar k3conf_0.3/.settings/language.settings.xml0000664000175000017500000000223114504337421015626 0ustar k3conf_0.3/include/0000775000175000017500000000000014511032107011160 5ustar k3conf_0.3/include/tisci.h0000664000175000017500000000770214375734376012503 0ustar /* * TISCI helper apis header file * * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __TISCI_H #define __TISCI_H #include struct ti_sci_version_info { uint8_t abi_major; uint8_t abi_minor; uint16_t firmware_version; char firmware_description[32]; }; struct ti_sci_host_info { uint32_t host_id; char host_name[15]; char security_status[15]; char description[50]; }; #define MAIN_SEC_PROXY 0 #define MCU_SEC_PROXY 1 struct ti_sci_sec_proxy_info { uint32_t sp_id; char sp_dir[6]; uint32_t num_msgs; char host[15]; char host_function[50]; }; struct ti_sci_processors_info { uint32_t dev_id; uint32_t clk_id; uint32_t processor_id; char name[30]; }; struct ti_sci_devices_info { uint32_t dev_id; char name[60]; }; struct ti_sci_clocks_info { uint32_t dev_id; uint32_t clk_id; char clk_name[100]; char clk_function[100]; }; struct ti_sci_rm_info { uint32_t utype; char subtype_name[100]; }; struct ti_sci_info { uint8_t host_id; struct ti_sci_version_info version; struct ti_sci_host_info *host_info; uint32_t num_hosts; struct ti_sci_sec_proxy_info *sp_info[2]; uint32_t num_sp_threads[2]; struct ti_sci_processors_info *processors_info; uint32_t num_processors; struct ti_sci_devices_info *devices_info; uint32_t num_devices; struct ti_sci_clocks_info *clocks_info; uint32_t num_clocks; struct ti_sci_rm_info *rm_info; uint32_t num_res; }; struct ti_sci_rm_desc { uint16_t start; uint16_t num; uint16_t start_sec; uint16_t num_sec; }; #define MAX_DEVICE_STATE_LENGTH 25 #define MAX_CLOCK_STATE_LENGTH 25 int ti_sci_init(void); const char *ti_sci_cmd_get_device_status(uint32_t dev_id); int ti_sci_cmd_disable_device(uint32_t dev_id); int ti_sci_cmd_enable_device(uint32_t dev_id); int ti_sci_cmd_get_clk(uint32_t dev_id, uint32_t clk_id); int ti_sci_cmd_put_clk(uint32_t dev_id, uint32_t clk_id); const char *ti_sci_cmd_get_clk_state(uint32_t dev_id, uint32_t clk_id); int ti_sci_cmd_set_clk_freq(uint32_t dev_id, uint32_t clk_id, uint64_t freq); int ti_sci_cmd_get_clk_freq(uint32_t dev_id, uint32_t clk_id, uint64_t *freq); int ti_sci_cmd_get_range(uint16_t type, uint16_t subtype, uint16_t host_id, struct ti_sci_rm_desc *desc); int ti_sci_cmd_get_clk_parent(uint32_t dev_id, uint32_t clk_id, uint32_t *parent_clk_id); int ti_sci_cmd_set_clk_parent(uint32_t dev_id, uint32_t clk_id, uint32_t parent_clk_id); #endif k3conf_0.3/include/mmio.h0000664000175000017500000000520214504336513012303 0ustar /* * MMIO helper library header file. * * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla * Nishanth Menon * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __MMIO_H #define __MMIO_H #include #include #include #include #include void mmio_write_8(uintptr_t addr, uint8_t value); uint8_t mmio_read_8(uintptr_t addr); void mmio_write_16(uintptr_t addr, uint16_t value); uint16_t mmio_read_16(uintptr_t addr); void mmio_write_32(uintptr_t addr, uint32_t value); uint32_t mmio_read_32(uintptr_t addr); void mmio_write_64(uintptr_t addr, uint64_t value); uint64_t mmio_read_64(uintptr_t addr); static inline void mmio_clrbits_32(uintptr_t addr, uint32_t clear) { mmio_write_32(addr, mmio_read_32(addr) & ~clear); } static inline void mmio_setbits_32(uintptr_t addr, uint32_t set) { mmio_write_32(addr, mmio_read_32(addr) | set); } static inline void mmio_clrsetbits_32(uintptr_t addr, uint32_t clear, uint32_t set) { mmio_write_32(addr, (mmio_read_32(addr) & ~clear) | set); } #define NON_ROOT_USER (-13) #endif /* __MMIO_H */ k3conf_0.3/include/sec_proxy.h0000664000175000017500000000456114504336513013364 0ustar /* * Secure Proxy header file * * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #ifndef __SEC_PROXY_H #define __SEC_PROXY_H #define DEFAULT_HOST_ID 14 #define INVALID_HOST_ID 0xff #define DEFAULT_SEC_PROXY_RX_THREAD 21 #define DEFAULT_SEC_PROXY_TX_THREAD 23 #define SEC_PROXY_MAX_MSG_SIZE 60 #define SEC_PROXY_HOST 14 struct k3_sec_proxy_msg { size_t len; uint8_t *buf; }; struct k3_sec_proxy_base { uint32_t src_target_data; uint32_t cfg_scfg; uint32_t cfg_rt; }; int k3_sec_proxy_send(struct k3_sec_proxy_msg *msg); int k3_sec_proxy_recv(struct k3_sec_proxy_msg *msg); int k3_sec_proxy_init(void); extern struct k3_sec_proxy_base k3_generic_sec_proxy_base; extern struct k3_sec_proxy_base k3_lite_sec_proxy_base; #endif /* __SEC_PROXY_H */ k3conf_0.3/include/tisci_protocol.h0000664000175000017500000001556514504336513014413 0ustar /* * TISCI Protocol header file. * * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __TISCI_P_H #define __TISCI_P_H #include #include #define TI_SCI_MSG_VERSION 0x0002 /* Device requests */ #define TI_SCI_MSG_SET_DEVICE_STATE 0x0200 #define TI_SCI_MSG_GET_DEVICE_STATE 0x0201 /* Clock requests */ #define TI_SCI_MSG_SET_CLOCK_STATE 0x0100 #define TI_SCI_MSG_GET_CLOCK_STATE 0x0101 #define TI_SCI_MSG_SET_CLOCK_PARENT 0x0102 #define TI_SCI_MSG_GET_CLOCK_PARENT 0x0103 #define TI_SCI_MSG_SET_CLOCK_FREQ 0x010c #define TI_SCI_MSG_QUERY_CLOCK_FREQ 0x010d #define TI_SCI_MSG_GET_CLOCK_FREQ 0x010e /* Resource Management Requests */ #define TI_SCI_MSG_GET_RESOURCE_RANGE 0x1500 #define TI_SCI_MSG_FLAG(val) (1 << (val)) #define TI_SCI_FLAG_REQ_GENERIC_NORESPONSE 0x0 #define TI_SCI_FLAG_REQ_ACK_ON_RECEIVED TI_SCI_MSG_FLAG(0) #define TI_SCI_FLAG_REQ_ACK_ON_PROCESSED TI_SCI_MSG_FLAG(1) #define TI_SCI_FLAG_RESP_GENERIC_NACK 0x0 #define TI_SCI_FLAG_RESP_GENERIC_ACK TI_SCI_MSG_FLAG(1) struct ti_sci_msg_hdr { uint16_t type; uint8_t host; uint8_t seq; uint32_t flags; } __attribute__ ((__packed__)); struct ti_sci_msg_resp_version { struct ti_sci_msg_hdr hdr; char firmware_description[32]; uint16_t version; uint8_t abi_major; uint8_t abi_minor; } __attribute__ ((__packed__)); struct ti_sci_secure_msg_hdr { uint16_t checksum; uint16_t reserved; } __attribute__ ((__packed__)); struct ti_sci_msg_req_set_device_state { /* Additional hdr->flags options */ #define MSG_FLAG_DEVICE_WAKE_ENABLED TI_SCI_MSG_FLAG(8) #define MSG_FLAG_DEVICE_RESET_ISO TI_SCI_MSG_FLAG(9) #define MSG_FLAG_DEVICE_EXCLUSIVE TI_SCI_MSG_FLAG(10) struct ti_sci_msg_hdr hdr; uint32_t id; uint32_t reserved; #define MSG_DEVICE_SW_STATE_AUTO_OFF 0 #define MSG_DEVICE_SW_STATE_RETENTION 1 #define MSG_DEVICE_SW_STATE_ON 2 uint8_t state; } __attribute__ ((__packed__)); struct ti_sci_msg_req_get_device_state { struct ti_sci_msg_hdr hdr; uint32_t id; } __attribute__ ((__packed__)); struct ti_sci_msg_resp_get_device_state { struct ti_sci_msg_hdr hdr; uint32_t context_loss_count; uint32_t resets; uint8_t programmed_state; #define MSG_DEVICE_HW_STATE_OFF 0 #define MSG_DEVICE_HW_STATE_ON 1 #define MSG_DEVICE_HW_STATE_TRANS 2 #define MAX_DEVICE_HW_STATES 3 uint8_t current_state; } __attribute__ ((__packed__)); struct ti_sci_msg_req_get_resource_range { struct ti_sci_msg_hdr hdr; #define MSG_RM_RESOURCE_TYPE_MASK 0x3ff #define MSG_RM_RESOURCE_SUBTYPE_MASK 0x3f uint16_t type; uint8_t subtype; uint8_t secondary_host; } __attribute__ ((__packed__)); struct ti_sci_msg_resp_get_resource_range { struct ti_sci_msg_hdr hdr; uint16_t range_start; uint16_t range_num; uint16_t range_start_sec; uint16_t range_num_sec; } __attribute__ ((__packed__)); struct ti_sci_msg_req_set_clock_state { /* Additional hdr->flags options */ #define MSG_FLAG_CLOCK_ALLOW_SSC TI_SCI_MSG_FLAG(8) #define MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE TI_SCI_MSG_FLAG(9) #define MSG_FLAG_CLOCK_INPUT_TERM TI_SCI_MSG_FLAG(10) struct ti_sci_msg_hdr hdr; uint32_t dev_id; uint8_t clk_id; #define MSG_CLOCK_SW_STATE_UNREQ 0 #define MSG_CLOCK_SW_STATE_AUTO 1 #define MSG_CLOCK_SW_STATE_REQ 2 uint8_t request_state; uint32_t clk_id_32; } __attribute__ ((__packed__)); struct ti_sci_msg_req_get_clock_state { struct ti_sci_msg_hdr hdr; uint32_t dev_id; uint8_t clk_id; uint32_t clk_id_32; } __attribute__ ((__packed__)); struct ti_sci_msg_resp_get_clock_state { struct ti_sci_msg_hdr hdr; uint8_t programmed_state; #define MSG_CLOCK_HW_STATE_NOT_READY 0 #define MSG_CLOCK_HW_STATE_READY 1 #define MAX_CLOCK_HW_STATES 2 uint8_t current_state; } __attribute__ ((__packed__)); struct ti_sci_msg_req_query_clock_freq { struct ti_sci_msg_hdr hdr; uint32_t dev_id; uint64_t min_freq_hz; uint64_t target_freq_hz; uint64_t max_freq_hz; uint8_t clk_id; uint32_t clk_id_32; } __attribute__ ((__packed__)); struct ti_sci_msg_resp_query_clock_freq { struct ti_sci_msg_hdr hdr; uint64_t freq_hz; } __attribute__ ((__packed__)); struct ti_sci_msg_req_set_clock_freq { struct ti_sci_msg_hdr hdr; uint32_t dev_id; uint64_t min_freq_hz; uint64_t target_freq_hz; uint64_t max_freq_hz; uint8_t clk_id; uint32_t clk_id_32; } __attribute__ ((__packed__)); struct ti_sci_msg_req_get_clock_freq { struct ti_sci_msg_hdr hdr; uint32_t dev_id; uint8_t clk_id; uint32_t clk_id_32; } __attribute__ ((__packed__)); struct ti_sci_msg_resp_get_clock_freq { struct ti_sci_msg_hdr hdr; uint64_t freq_hz; } __attribute__ ((__packed__)); struct ti_sci_msg_get_clock_parent_req { struct ti_sci_msg_hdr hdr; uint32_t dev_id; uint8_t clk_id; uint32_t clk_id_32; } __attribute__((__packed__)); struct ti_sci_msg_get_clock_parent_resp { struct ti_sci_msg_hdr hdr; uint8_t parent_clk_id; uint32_t parent_clk_id_32; } __attribute__((__packed__)); struct ti_sci_msg_set_clock_parent_req { struct ti_sci_msg_hdr hdr; uint32_t dev_id; uint8_t clk_id; uint8_t parent_clk_id; uint32_t clk_id_32; uint32_t parent_clk_id_32; } __attribute__((__packed__)); void ti_sci_setup_header(struct ti_sci_msg_hdr *hdr, uint16_t type, uint32_t flags); int ti_sci_xfer_msg(struct k3_sec_proxy_msg *msg); static inline uint8_t ti_sci_is_response_ack(uint8_t *resp) { struct ti_sci_msg_hdr *hdr = (struct ti_sci_msg_hdr *)resp; return hdr->flags & TI_SCI_FLAG_RESP_GENERIC_ACK ? 1 : 0; } #endif k3conf_0.3/include/k3conf.h0000664000175000017500000000457714504336530012542 0ustar /* * K3CONF Main Header file. * * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #ifndef __K3CONF_H #define __K3CONF_H int process_show_command(int argc, char *argv[]); int process_dump_command(int argc, char *argv[]); int dump_clocks_info(int argc, char *argv[]); int dump_clock_parent_info(int argc, char *argv[]); int dump_devices_info(int argc, char *argv[]); int dump_cpu_info(void); int process_enable_command(int argc, char *argv[]); int process_disable_command(int argc, char *argv[]); int process_set_command(int argc, char *argv[]); int process_read_command(int argc, char *argv[]); int process_write_command(int argc, char *argv[]); int ddrbw_info(int argc, char *argv[]); #endif k3conf_0.3/include/version.h0000664000175000017500000000341714375734376013054 0ustar /* * Version info header file. * * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __VERSION_H__ #define __VERSION_H__ extern char *k3conf_version; extern char *builddate; #endif k3conf_0.3/include/autoadjust_table.h0000664000175000017500000000517614375734376014725 0ustar /* * Table printing library helpers * * Copyright (C) 2010-2019 Texas Instruments Incorporated - https://www.ti.com/ * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ #ifndef __AUTOADJUST_TABLE_H #define __AUTOADJUST_TABLE_H #include #include #include #include #define TABLE_MAX_ROW 4000 #define TABLE_MAX_COL 20 #define TABLE_MAX_ELT_LEN 100 #define TABLE_HAS_TITLE 1 #define TABLE_HAS_SUBTITLE 2 int autoadjust_table_init( char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN]); int autoadjust_table_print( char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN], unsigned int row_nbr, unsigned int col_nbr); int autoadjust_table_fprint(FILE *stream, char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN], unsigned int row_nbr, unsigned int col_nbr); int autoadjust_table_generic_fprint(FILE *stream, char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN], unsigned int row_nbr, unsigned int col_nbr, unsigned int flags); int autoadjust_table_strncpy( char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN], unsigned int row, unsigned int col, char s[TABLE_MAX_ELT_LEN]); #endif k3conf_0.3/include/ddr_perf.h0000664000175000017500000000353414504336530013134 0ustar /* * DDR performance counter information * * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ * Aarya Chaumal * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __DDRPERF_H #define __DDRPERF_H #include struct ddr_perf_soc_info { uint8_t num_perf_insts; uint8_t burst_size; uintptr_t *perf_inst_base; }; #endif k3conf_0.3/include/help.h0000664000175000017500000000441214504336530012273 0ustar /* * Help Library Header File for K3CONF * * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __K3CONF_HELP #define __K3CONF_HELP typedef enum { HELP_USAGE, HELP_SHOW, HELP_SHOW_HOST, HELP_SHOW_SEC_PROXY, HELP_SHOW_DEVICE, HELP_SHOW_CLOCK, HELP_SHOW_PROCESSOR, HELP_SHOW_RM, HELP_DUMP, HELP_DUMP_DEVICE, HELP_DUMP_CLOCK, HELP_DUMP_CLOCK_PARENT, HELP_DUMP_PROCESSOR, HELP_DUMP_RM, HELP_ENABLE, HELP_ENABLE_DEVICE, HELP_ENABLE_CLOCK, HELP_DISABLE, HELP_DISABLE_DEVICE, HELP_DISABLE_CLOCK, HELP_SET, HELP_SET_CLOCK, HELP_SET_CLOCK_PARENT, HELP_READ, HELP_WRITE, HELP_DUMP_DDRBW, HELP_ALL, HELP_CATEGORY_MAX, } help_category; void help(help_category cat); #endif k3conf_0.3/include/socinfo.h0000664000175000017500000000453114511032107012774 0ustar /* * SoC info header file * * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __SOCINFO_H #define __SOCINFO_H #include #include #include "sec_proxy.h" #include "ddr_perf.h" #define AM62X 0xbb7e #define AM62AX 0xbb8d #define AM62PX 0xbb9d #define AM65X 0xbb5a #define J721E 0xbb64 #define J7200 0xbb6d #define AM64X 0xbb38 #define J721S2 0xbb75 #define J784S4 0xbb80 struct k3conf_soc_info { const char *soc_name; const char *rev_name; uint8_t host_id; uint8_t ti_sci_enabled; struct ti_sci_info sci_info; struct ddr_perf_soc_info *ddr_perf_info; struct k3_sec_proxy_base *sec_proxy; }; extern struct k3conf_soc_info soc_info; int soc_init(uint32_t host_id); extern int soc_info_valid; #define SOC_INFO_UNKNOWN_SILICON (-19) #endif k3conf_0.3/.cproject0000664000175000017500000000663714456001511011366 0ustar k3conf_0.3/CMakeLists.txt0000664000175000017500000000701314560756656012330 0ustar cmake_minimum_required(VERSION 3.8) project(k3conf C) set(VERSION_MAJOR 0) set(VERSION_MINOR 3) set(K3CONF_SOURCES # Common common/k3conf.c common/help.c common/mmio.c common/socinfo.c common/sec_proxy.c common/tisci/tisci_core.c common/tisci/tisci_device.c common/tisci/tisci_clock.c common/autoadjust_table.c common/cmd_show.c common/cmd_dump.c common/cmd_enable.c common/cmd_disable.c common/cmd_set.c common/cmd_rw.c common/cmd_ddr_perf.c # AM65x soc/am65x/am65x_host_info.c soc/am65x/am65x_sec_proxy_info.c soc/am65x/am65x_processors_info.c soc/am65x/am65x_devices_info.c soc/am65x/am65x_clocks_info.c soc/am65x/am65x_rm_info.c soc/am65x_sr2/am65x_sr2_host_info.c soc/am65x_sr2/am65x_sr2_sec_proxy_info.c soc/am65x_sr2/am65x_sr2_processors_info.c soc/am65x_sr2/am65x_sr2_devices_info.c soc/am65x_sr2/am65x_sr2_clocks_info.c soc/am65x_sr2/am65x_sr2_rm_info.c # J721e soc/j721e/j721e_host_info.c soc/j721e/j721e_sec_proxy_info.c soc/j721e/j721e_processors_info.c soc/j721e/j721e_devices_info.c soc/j721e/j721e_clocks_info.c soc/j721e/j721e_rm_info.c soc/j721e/j721e_ddr_info.c soc/j7200/j7200_host_info.c soc/j7200/j7200_sec_proxy_info.c soc/j7200/j7200_processors_info.c soc/j7200/j7200_devices_info.c soc/j7200/j7200_clocks_info.c soc/j7200/j7200_rm_info.c soc/j7200/j7200_ddr_info.c # AM64x soc/am64x/am64x_host_info.c soc/am64x/am64x_sec_proxy_info.c soc/am64x/am64x_processors_info.c soc/am64x/am64x_devices_info.c soc/am64x/am64x_clocks_info.c soc/am64x/am64x_rm_info.c # AM62x soc/am62x/am62x_devices_info.c soc/am62x/am62x_clocks_info.c soc/am62x/am62x_host_info.c soc/am62x/am62x_processors_info.c soc/am62x/am62x_rm_info.c soc/am62x/am62x_sec_proxy_info.c soc/am62x/am62x_ddr_info.c # J721s2 soc/j721s2/j721s2_devices_info.c soc/j721s2/j721s2_clocks_info.c soc/j721s2/j721s2_host_info.c soc/j721s2/j721s2_processors_info.c soc/j721s2/j721s2_rm_info.c soc/j721s2/j721s2_sec_proxy_info.c # J784s4 soc/j784s4/j784s4_clocks_info.c soc/j784s4/j784s4_devices_info.c soc/j784s4/j784s4_host_info.c soc/j784s4/j784s4_processors_info.c soc/j784s4/j784s4_rm_info.c soc/j784s4/j784s4_sec_proxy_info.c # AM62Ax soc/am62ax/am62ax_clocks_info.c soc/am62ax/am62ax_devices_info.c soc/am62ax/am62ax_host_info.c soc/am62ax/am62ax_processors_info.c soc/am62ax/am62ax_rm_info.c soc/am62ax/am62ax_sec_proxy_info.c # AM62Px soc/am62px/am62px_clocks_info.c soc/am62px/am62px_devices_info.c soc/am62px/am62px_host_info.c soc/am62px/am62px_processors_info.c soc/am62px/am62px_rm_info.c soc/am62px/am62px_sec_proxy_info.c ) # Set build timestamp string(TIMESTAMP TIMEDATE "%a %b %d %H:%M:%S UTC %Y" UTC) file(WRITE ${CMAKE_CURRENT_BINARY_DIR}/builddate.c "char *builddate=\"${TIMEDATE}\";\n") list(APPEND K3CONF_SOURCES ${CMAKE_CURRENT_BINARY_DIR}/builddate.c) # Set version from Git execute_process(COMMAND git describe --dirty --tags OUTPUT_VARIABLE GIT_VERSION ERROR_QUIET) if ("${GIT_VERSION}" STREQUAL "") set(GIT_VERSION "${VERSION_MAJOR}.${VERSION_MINOR}-nogit") else() string(STRIP "${GIT_VERSION}" GIT_VERSION) endif() file(WRITE ${CMAKE_CURRENT_BINARY_DIR}/version.c "char *k3conf_version=\"${GIT_VERSION}\";\n") list(APPEND K3CONF_SOURCES ${CMAKE_CURRENT_BINARY_DIR}/version.c) add_executable(k3conf ${K3CONF_SOURCES}) target_include_directories(k3conf PUBLIC ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/include ) target_compile_options(k3conf PRIVATE -Wall;-Wextra;-Wpedantic;-Wno-missing-field-initializers) install(TARGETS k3conf RUNTIME DESTINATION bin)