pax_global_header00006660000000000000000000000064131353151750014516gustar00rootroot0000000000000052 comment=b9da911eae4cd34a5d0012eae3d7e036e5536cdb mspdebug-0.25/000077500000000000000000000000001313531517500132525ustar00rootroot00000000000000mspdebug-0.25/.gitignore000066400000000000000000000000411313531517500152350ustar00rootroot00000000000000.*.swp *.o mspdebug mspdebug.exe mspdebug-0.25/AUTHORS000066400000000000000000000052351313531517500143270ustar00rootroot00000000000000MSPDebug is mostly written by Daniel Beer . Other people who have made significant contributions are listed here. Doug Forman : * Testing and analysis for TI Chronos devices. * Testing and analysis for FET430UIF firmware version 20404000. Robert Kavaler : * Author of uif430, from which much of the code in fet.c is derived (uif430 is available from www.relavak.com). Hans Nieuwenhuis : * Support for MSP430F2132. Peter Jansen : * Support for MSP430F169. * Testing and analysis for Olimex MSP430-JTAG-TINY. * libusb driver for Olimex MSP430-JTAG-TINY. Aurélien Gauducheau , Bondois Nicolas. Laboratoire Domus: Recherche en domotique et en informatique mobile (http://domus.usherbrooke.ca/?locale=en). Under supervision of Bessam Abdulrazak (http://pages.usherbrooke.ca/babdulrazak/): * Testing and analysis for MSP430F5529. Andres Vahter : * Support for MSP430F2234. Robert Spanton : * Support for FET430UIF bootloader programming. * GDB protocol improvements. Stephen Kench * Support for MSP430F47197. Sören Höckner : * Testing and debugging of flash memory word-alignment bug. Andrew Armenia : * flash-bsl driver. James Laird : * Support for CC430F5133. Stefan Mahr : * Initial support, testing and analysis for Olimex MSP430-JTAG-ISO. Jasper Lievisse Adriaanse : * Ported to OpenBSD. Ionut Nicu : * Support for MSP430F47173 and MSP430F5526. * --force-reset option. Paul Fleischer : * Support for MSP430G2553. Kurt Snieckus : * Testing and analysis for MSP430FR5739. James Nuss : * Support for MSP430F5418. Tamas Tevesz : * Improvements to interactive interface. * Support for MSP430AFE253. Ingo van Lil : * Support for demangling of C++ function names. * load_raw, verify_raw and save_raw commands. Stanimir Bonev : * Olimex chip database. * Improved identification/configuration system for Olimex debuggers. Peter Bägel : * JTAG interface library and parallel-port JTAG driver. Jose Angel Caso Sanchez : * FET v2 database from MSP430.DLL. Paolo Zebelloni : * Testing, debugging and research for the ROM BSL driver. * BSL entry via GPIOs. Jan Willeke : * GPIO JTAG driver. mspdebug-0.25/BSDmakefile000066400000000000000000000015221313531517500153030ustar00rootroot00000000000000# MSPDebug - debugging tool for the eZ430 # Copyright (C) 2013 Daniel Beer # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 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Version 0.24 - 14 May 2016 * Various bug fixes. * Persistent history and tab completion with libreadline. * Address expressions now support register names. * Add support for new 64-bit TI library API. Version 0.23 - 2 Mar 2015 * Support for raw JTAG via GPIOs. * Raw JTAG drivers now support single stepping and breakpoints. * Support for MSP430F5xx USB bootloader. * Added experimental fet3/eZ-FET driver. * Added "blow_jtag_fuse" command. * Added "!" command for dropping to a shell. * flash_bsl now allows custom entry/exit sequences. * Added ROM BSL driver. * Add support for BSL entry via GPIO toggling. * Many bug and portability fixes. Version 0.22 - 18 Jul 2013 * Support for erasing/programming information and bootloader flash memories. * Support for new chips: MSP430G2352, MSP430FG4616, MSP430FR5728, MSP430G2955, MSP430FR5729. * Windows build fixes. * Various fixes for disassembly and simulation of some types of instructions. * Fixed segment erase for FET-like and tilib drivers. * Support for alternative and directory-local configuration files. * Fixes for Intel HEX file generation. * Fixed drivers for Olimex MSP430-JTAG-TINY rev 1. Version 0.21 - 26 Nov 2012 * Support for flat binary files. * Bug fixes and refactoring of drivers. * Support for UIF BSL access via USB. * Support for Olimex MSP430-JTAG-ISO-MK2, including power profiling. * Support for parallel JTAG. * Support for many new chips when using Olimex drivers. * Add new interface mode for use with front-ends. Version 0.20 - 14 Aug 2012 * Support for new chips: MSP430F6736, MSP430F2252, MSP430G2403, MSP430F6435. * Support for building under Cygwin. * Support for watchpoints using MSP430.DLL (tilib) driver. * Support for GoodFET (memory access/programming only). * Various bug fixes, including many disassembly fixes and an issue causing FRAM reset-vector corruption. * Basic C++ demangling support. * New commands: "fill" and "verify". * Erase requests are now ignored when using FRAM chips. Version 0.19 - 3 Mar 2012 * Support for MSP430-JTAG-ISO on platforms other than Linux, via both serial drivers and raw USB access. * Support for new chips: MSP430F5342, MSP430F5329, MSP430F2418. * Fixed support for later-model MSP430-JTAG-TINY rev 2. * Fixed build warnings on many systems. * Fixed output buffering to allow correct interaction with Eclipse plugins. Version 0.18 - 8 Nov 2011 * Support for new chips: MSP430F2121, MSP430F2012, MSP430F449. * Support for raw USB access to FET430UIF and eZ430-F2013. * Support for TI MSP430 library. * Various Win32 bug fixes. * GDB protocol bug fixes. * Section names are displayed when programming. Version 0.17 - 24 Aug 2011 * Support for new chips: MSP430FR5739, MSP430F5418, MSP430AFE253, MSP430F5527, MSP430F5510, MSP430F5528. * Added -s option to distinguish programming tools by serial number. * Ported to Win32 (can be compiled with MinGW). * Bug fixes for GDB stub interface and simulator. * Reader now supports tilde-expansion and ^[# key. * Better diagnostics for FET devices (more error codes). Version 0.16 - 14 Jun 2011 * Support for new chips: MSP430G2252, MSP430G2553, MSP430F235, MSP430F427. * Added GDB client driver. * Added support for Olimex MSP-JTAG-TINY rev 2. * Bug fix in flash-bsl driver for large memory transfers. Version 0.15 - 5 Apr 2011 * Support for new chips: MSP430G2452, MSP430F5525, MSP430F47173, MSP430F5526. * Added --force-reset option. * Added "alias" command. * IO peripheral simulator (interrupts, hardware multiplier, GPIO, Timer_A, Watchdog Timer+). * Configurable block size for FET memory transfers. * Fix build problems on Cygwin and OpenBSD. * Various corrections to manual page. Version 0.14 - 7 Feb 2011 * Corrected email address in AUTHORS file. * Support for new chips: MSP430F2272, MSP430F2122. * Support for different erase types with flash_bsl driver. * Fixed build problems on OS/X and OpenBSD. * Bug fix: incorrect simulation of SUB/SUBC/CMP opcodes. * Bug fix: faulty response to gdb "read registers" command. Version 0.13 - 9 Nov 2010 * Bug fix: incorrect handling of Intel HEX segment offsets. * Support for new chips: MSP430F1121, MSP430F2131, MSP430F2617, MSP430F247, MSP430F4270, MSP430G2231, CC430F5133. * Support for Olimex MSP430-JTAG-ISO. * FET driver retries with a reset if the first attempt to connect fails. This should fix the problem which requires devices to be replugged after each session. * Notify the user when programming in quiet mode, and display version banner unless starting in quiet mode. Version 0.12 - 12 Oct 2010 * Bug fixes: unaligned flash read/write, reduced memory block size, MSP430F5438 support, BSL memory ranges. * Support for MSP430FG4618. * New commands: load, locka, exit. * Support for flash BSL (but see notes in manual). * Preliminary support for segment and mass erase (see "erase" command). * Reset is now issued on disconnect, rather than on init. * Allow specification of default input radix (see "iradix" option). * Allow partial unambiguous command matches. * Repeat execution of certain commands in reader. * Commands read from a file are now printed as they are executed. Version 0.11 - 9 Sep 2010 * Support for programming and debugging 20-bit devices. * Support for MSP430X instruction set. * Support for new chips: MSP430F2234, CC430F5137, MSP430F2618, MSP430F1612, MSP430F47197, MSP430F1232, MSP430F413, MSP430F2370. * Bug fixes: RF2500 support on OS/X, chip identification using FET. * Added quiet mode to supress debug output. * Faster gdb transfers. * Faster polling with FET driver (quicker single-stepping and breakpoint detection). * Commands can now be issued, and output received, via the gdb interface (using "monitor"). * Support for FET430UIF firmware updates via BSL. Version 0.10 - 4 Aug 2010 * Bug fixes for gdb interface, FET driver. * Added support for MSP430F5529. * Added support for COFF, S19 and TI-Text file formats. * Support multiple breakpoints (see "setbreak", "delbreak" and "break" commands). Version 0.9 - 29 Jun 2010 * Added support for MSP430F2132, MSP430F169. * Fixed support for FET430UIF JTAG with 5xxx series devices. * Added support for Olimex MSP-JTAG-TINY programmer. * Multiple instances of USB programmers can now be used simultaneously. * Cleaner command line options (see "--help" for information). Version 0.8 - 22 May 2010 * Bug fixes for disassembly, chip erase, gdb interface, simulation. * Modifications to improve portability to Cygwin and Mac OS X. * Implemented call graph analysis (see "cgraph" command). * Better FET protocol support for firmware versions >= 20300000. Version 0.7 - 30 Apr 2010 * Symbol tables can now be edited and exported (see "sym" command). * Bug fixes for disassembly. * Added option for coloured output. * Can search memory for instructions matching a pattern (see "isearch" command). * Can now include initialization commands in ~/.mspdebug RC file. * Address expressions are now algebraic expressions. * Added support for TI Chronos devices. * Added support for C-style quoted command arguments. Version 0.6 - 23 Mar 2010 * Bug fixes for simulation and disassembly. * Added new commands: erase, mw, read. * Added support for GNU readline. * Implemented GDB remote stub (see "gdb" command). Version 0.5 - 20 Mar 2010 * Added support for BSD-style symbol table files (*.map). * Disassembly bug fixes. * Fixed BSL version reporting. * Added more device IDs. * Added manual page. * Added CPU core emulation. Version 0.4 - 15 Jan 2010 * Bug fixes for FET430UIF devices. * Added ELF32 support. * Added symbol table support. * Added support for the FET430UIF bootloader. * Added simulation/dummy mode. * Added "hexout" command for extracting images. Version 0.3 - 4 Jan 2010 * Better diagnostics (recognises and shows protocol errors). * Protocol bug fixes for non-RF2500 devices. * Added JTAG support. Version 0.2 - 17 Nov 2009 * Added Makefile. * Added support for FET430UIF and eZ430-F2013 devices. * Commands can now be executed non-interactively. Version 0.1 - 15 Oct 2009 * First version. mspdebug-0.25/EmbeddedMode.txt000066400000000000000000000130061313531517500163110ustar00rootroot00000000000000 MSPDebug embedded mode Daniel Beer 9 Oct 2012 This document describes mspdebug's embedded mode, which makes it easier to use it as a back-end to a third-party user interface. The key differences between the normal terminal interface and embedded mode are: * Command reading: in embedded mode, commands are read without displaying a prompt to the user. * Output processing: rather than directing errors to stderr, all output is sent to stdout, so that all messages remain in sync relative to one another. Output lines are prefixed with a sigil character to indicate their type (error/normal/debug). * Interrupt processing: normally, Ctrl+C or Ctrl+Break sequences can be used to interrupt a running command via the SIGINT signal, or a console event handler. In embedded mode, a terminal is not available, so another method which relies only on standard line-oriented IO is provided. * Additional output: additional data is provided which can be used by a third-party user interface to improve interaction. These differences are explained in more detail in the following sections. To enabled embedded mode, add the --embedded flag to mspdebug's command-line arguments. Output processing ================= In embedded mode, all output is directed to stdout. This ensures that the logical streams generated by mspdebug stay in order relative to one another when written to an asynchronous pipe. To distinguish the streams, each is prefixed with a single sigil character. These sigil characters are: Sigil Output type -------- ----------------- : Normal output - Debug output (suppressed in quiet mode) ! Error messages \ Shell messages Another feature of output processing in embedded mode is that when colourized output is enabled (``opt color true``), colourization is always implemented by including ANSI escape codes in the output, even on Windows. Normally, colourized output on Windows is implemented by changing console text attributes. Shell messages -------------- Shell messages are emitted only when in embedded mode. They provide additional information to the front-end and consist of a type identifier string immediately following the sigil, then optionally a space and arguments. Currently, the following shell messages may be emitted: \ready ~ The command processor is ready to receive a command. \busy ~ The command process has accepted a command and is now executing it. \power-sample-us ~ Indicates that power profiling is enabled. The period argument is a decimal number giving the sample period in microseconds. \power-samples ~ Power data captured from the running device. The data argument is a Base64-encoded string. When decoded, it consists of a sequence of 32-bit little-endian unsigned integers. Integers with bit 31 set are MAB values, and those without bit 31 set are current consumption readings, in microamps. Input processing and interruption ================================= A different input processor is used in embedded mode, to allow for interruption of running commands without the use of signals or console control handlers. When embedded mode is enabled, a prompt is never displayed. Lines of text are read from stdin in a separate thread, and any commands are posted through to the main thread. The lines of text read are also prefixed with sigils -- either ':' to indicate a command, or '\' to indicate a special reader operation. Lines of text without a sigil are assumed to be commands. Currently, the only implemented special operation is "\break", which raises a break condition to interrupt any running command. End-of-input is signalled by closing stdin. If the command processor is running a command when this occurs, it will wait until the command finishes before exiting. If a command is sent before the reader is ready to accept one, it is discarded. To avoid race conditions, a front end should: * Send a command only after the "\ready" shell message is received, and do not send further commands until it has finished executing. * To interrupt a running command by sending a "\break" operation, the front-end should first wait until the "\busy" message is received. Otherwise, the break condition may be lost. Example ======= In the following example, arrows are used to indicate text sent to mspdebug (=>) and text received from the mspdebug process (<=): $ ./mspdebug --embedded sim -q <= \ready => :prog ../fet-fw/20401004.hex <= \busy <= :Erasing... <= :Programming... <= :Done, 55472 bytes total <= \ready => :reset <= \busy <= \ready => :run <= \busy <= :Running. Press Ctrl+C to interrupt... => \break <= : <= : ( PC: 0c682) ( R4: 00000) ( R8: 00000) (R12: 00000) <= : ( SP: 024f2) ( R5: 00000) ( R9: 00000) (R13: 00000) <= : ( SR: 0000d) ( R6: 00000) (R10: 0ffff) (R14: 00002) <= : ( R3: 00000) ( R7: 00000) (R11: 00000) (R15: 00063) <= :0xc682: <= : 0c682: 0d 43 CLR R13 <= : 0c684: 3a 41 POP R10 <= : 0c686: 30 41 RET <= : 0c688: 0a 12 PUSH R10 <= : 0c68a: 0b 12 PUSH R11 <= : 0c68c: 08 12 PUSH R8 <= : 0c68e: 0b 4c MOV R12, R11 <= : 0c690: 08 4e MOV R14, R8 <= \ready mspdebug-0.25/Makefile000066400000000000000000000134241313531517500147160ustar00rootroot00000000000000# MSPDebug - debugging tool for the eZ430 # Copyright (C) 2009-2015 Daniel Beer # Copyright (C) 2010 Andrew Armenia # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA CC ?= gcc INSTALL = /usr/bin/install PREFIX ?= /usr/local LDFLAGS ?= -s BINDIR = ${PREFIX}/bin/ MANDIR = ${PREFIX}/share/man/man1 LIBDIR = ${PREFIX}/lib/ UNAME_S := $(shell sh -c 'uname -s') UNAME_O := $(shell sh -c 'uname -o 2> /dev/null') ifdef WITHOUT_READLINE READLINE_CFLAGS = READLINE_LIBS = CONSOLE_INPUT_OBJ = ui/input_console.o else READLINE_CFLAGS = -DUSE_READLINE READLINE_LIBS = -lreadline CONSOLE_INPUT_OBJ = ui/input_readline.o endif BSLHID_OBJ ?= transport/bslhid.o RF25000_OBJ ?= transport/rf2500.o ifeq ($(OS),Windows_NT) MSPDEBUG_CC = $(CC) BINARY = mspdebug.exe ifneq ($(UNAME_O),Cygwin) OS_LIBS = -lws2_32 -lregex OS_CFLAGS = -D__Windows__ -DNO_SHELLCMD RM = del endif else MSPDEBUG_CC = $(CC) BINARY = mspdebug ifneq ($(filter $(UNAME_S),OpenBSD NetBSD),) OS_LIBS = else ifneq ($(filter $(UNAME_S),FreeBSD DragonFly),) OS_CFLAGS = -pthread OS_LIBS = -lpthread else ifneq ($(filter $(UNAME_S),SunOS),) OS_LIBS = -lpthread -ldl -lresolv -lsocket -lnsl else OS_LIBS = -lpthread -ldl endif ifeq ($(UNAME_S),Darwin) # Mac OS X/MacPorts stuff ifeq ($(shell fink -V > /dev/null 2>&1 && echo ok),ok) PORTS_CFLAGS := $(shell pkg-config --cflags hidapi libusb) PORTS_LDFLAGS := $(shell pkg-config --libs hidapi libusb) -ltermcap -pthread else ifeq ($(shell brew --version > /dev/null 2>&1 && echo ok),ok) PORTS_CFLAGS := $(shell pkg-config --cflags hidapi) PORTS_LDFLAGS := $(shell pkg-config --libs hidapi) -framework IOKit -framework CoreFoundation else PORTS_CFLAGS := -I/opt/local/include PORTS_LDFLAGS := -L/opt/local/lib -lhidapi -framework IOKit -framework CoreFoundation endif BSLHID_OBJ = transport/bslosx.o RF25000_OBJ = transport/rf2500hidapi.o LDFLAGS = else ifneq ($(filter $(UNAME_S),OpenBSD NetBSD DragonFly),) PORTS_CFLAGS := $(shell pkg-config --cflags libusb) PORTS_LDFLAGS := $(shell pkg-config --libs libusb) -ltermcap -pthread else PORTS_CFLAGS := PORTS_LDFLAGS := endif endif INCLUDES = -I. -Isimio -Iformats -Itransport -Idrivers -Iutil -Iui GCC_CFLAGS = -O1 -Wall -Wno-char-subscripts -ggdb CONFIG_CFLAGS = -DLIB_DIR=\"$(LIBDIR)\" MSPDEBUG_LDFLAGS = $(LDFLAGS) $(PORTS_LDFLAGS) MSPDEBUG_LIBS = -L. -lusb $(READLINE_LIBS) $(OS_LIBS) MSPDEBUG_CFLAGS = $(CFLAGS) $(READLINE_CFLAGS) $(PORTS_CFLAGS)\ $(GCC_CFLAGS) $(INCLUDES) $(CONFIG_CFLAGS) $(OS_CFLAGS) all: $(BINARY) ifeq ($(OS),Windows_NT) clean: ifeq ($(UNAME_O),Cygwin) $(RM) */*.o $(RM) $(BINARY) else $(RM) drivers\*.o $(RM) formats\*.o $(RM) simio\*.o $(RM) transport\*.o $(RM) ui\*.o $(RM) util\*.o $(RM) $(BINARY) endif else clean: $(RM) */*.o $(RM) $(BINARY) endif install: $(BINARY) mspdebug.man mkdir -p $(DESTDIR)$(BINDIR) $(INSTALL) -m 0755 $(BINARY) $(DESTDIR)$(BINDIR) mkdir -p $(DESTDIR)$(MANDIR) $(INSTALL) -m 0644 mspdebug.man $(DESTDIR)$(MANDIR)/mspdebug.1 mkdir -p $(DESTDIR)$(LIBDIR)/mspdebug $(INSTALL) -m 0644 ti_3410.fw.ihex \ $(DESTDIR)$(LIBDIR)/mspdebug/ti_3410.fw.ihex .SUFFIXES: .c .o OBJ=\ util/btree.o \ util/expr.o \ util/list.o \ util/sockets.o \ util/sport.o \ util/usbutil.o \ util/util.o \ util/vector.o \ util/output.o \ util/output_util.o \ util/opdb.o \ util/prog.o \ util/stab.o \ util/dis.o \ util/gdb_proto.o \ util/dynload.o \ util/demangle.o \ util/powerbuf.o \ util/ctrlc.o \ util/chipinfo.o \ util/gpio.o \ transport/cp210x.o \ transport/cdc_acm.o \ transport/ftdi.o \ transport/ti3410.o \ transport/comport.o \ $(BSLHID_OBJ) \ $(RF25000_OBJ) \ drivers/device.o \ drivers/bsl.o \ drivers/fet.o \ drivers/fet_core.o \ drivers/fet_proto.o \ drivers/fet_error.o \ drivers/fet_db.o \ drivers/flash_bsl.o \ drivers/gdbc.o \ drivers/sim.o \ drivers/tilib.o \ drivers/goodfet.o \ drivers/obl.o \ drivers/devicelist.o \ drivers/fet_olimex_db.o \ drivers/jtdev.o \ drivers/jtdev_bus_pirate.o \ drivers/jtdev_gpio.o \ drivers/jtaglib.o \ drivers/pif.o \ drivers/loadbsl.o \ drivers/loadbsl_fw.o \ drivers/hal_proto.o \ drivers/v3hil.o \ drivers/fet3.o \ drivers/bsllib.o \ drivers/rom_bsl.o \ drivers/tilib_api.o \ formats/binfile.o \ formats/coff.o \ formats/elf32.o \ formats/ihex.o \ formats/symmap.o \ formats/srec.o \ formats/titext.o \ simio/simio.o \ simio/simio_tracer.o \ simio/simio_timer.o \ simio/simio_wdt.o \ simio/simio_hwmult.o \ simio/simio_gpio.o \ simio/simio_console.o \ ui/gdb.o \ ui/rtools.o \ ui/sym.o \ ui/devcmd.o \ ui/flatfile.o \ ui/reader.o \ ui/cmddb.o \ ui/stdcmd.o \ ui/aliasdb.o \ ui/power.o \ ui/input.o \ ui/input_async.o \ $(CONSOLE_INPUT_OBJ) \ ui/main.o $(BINARY): $(OBJ) $(MSPDEBUG_CC) $(MSPDEBUG_LDFLAGS) -o $@ $^ $(MSPDEBUG_LIBS) util/chipinfo.o: chipinfo.db .c.o: $(MSPDEBUG_CC) $(MSPDEBUG_CFLAGS) -o $@ -c $*.c mspdebug-0.25/README000066400000000000000000000035501313531517500141350ustar00rootroot00000000000000MSPDebug ======== MSPDebug is a free debugger for use with MSP430 MCUs. It supports FET430UIF, eZ430, RF2500 and Olimex MSP430-JTAG-TINY programmers, as well as many other compatible devices. It can be used as a proxy for gdb or as an independent debugger with support for programming, disassembly and reverse engineering. Features -------- * Userspace only: no kernel modifications required. * Works with RF2500, eZ430, FET430UIF (V2 and V3), Launchpad, Chronos, GoodFET, Olimex MSP430-JTAG-TINY and MSP430-JTAG-ISO programmers. Also supports the TI flash bootloader. * Can act as a GDB remote stub (replacement for msp430-gdbproxy) and/or a GDB client. * Can single-step, program, run to breakpoint and inspect memory on supported devices. * Can be used to access the FET430UIF bootloader. * Supports Intel HEX, ELF32, BSD symbol table, COFF, TI Text and SREC file formats. * Can disassemble code in memory, including translating addresses to symbols. * Includes reverse-engineering features such as instruction search, call-graph analysis and symbol table editing. * Simulation mode allows execution of MSP430 code without hardware. * Cross-platform: compiles on Linux, *BSD, OS/X and Windows. Compiling from source --------------------- Ensure that you have the necessary packages to compile programs that use libusb (on Debian or Ubuntu systems, you might need to do apt-get install libusb-dev). After that, unpack and compile the source code with: tar xvfz mspdebug-version.tar.gz cd mspdebug-version make On Debian Ubuntu systems sudo apt-get install libreadline-dev may be required. If you don't want GNU readline support, you can invoke make with: make WITHOUT_READLINE=1 After compiling, install the binary and manual page by running (as root): make install Type "mspdebug --help" for usage instructions. mspdebug-0.25/chipinfo.db000066400000000000000000054733651313531517500154070ustar00rootroot00000000000000/* MSP430 chip database * * THIS FILE WAS GENERATED FROM MSP430.DLL v3.3.1.4 * * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #define CI_DLL430_VERSION_MAJOR 3 #define CI_DLL430_VERSION_MINOR 3 #define CI_DLL430_VERSION_PATCH 1 #define CI_DLL430_VERSION_BUILD 4 #define CI_DLL430_VERSION_STRING "3.3.1.4" static const struct chipinfo_funclet erase_fll = { .code_size = 48, .max_payload = 4, .entry_point = 0x0000, .code = { 0x400a, 0x40b2, 0x5a80, 0x0120, 0x503a, 0x005c, 0x40ba, 0xbeef, 0x0000, 0x3c06, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x403b, 0xdead, 0xea2b, 0x23fc, 0x403b, 0x000a, 0x4982, 0x0128, 0x450c, 0x40bc, 0xdead, 0x0000, 0x403c, 0x227a, 0x831c, 0x23fe, 0x40b2, 0xa500, 0x0128, 0x831b, 0x23f1, 0x3c08, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x3fff, 0x4303, } }; static const struct chipinfo_funclet erase_dco = { .code_size = 48, .max_payload = 4, .entry_point = 0x0000, .code = { 0x400a, 0x40b2, 0x5a80, 0x0120, 0x4bc2, 0x0056, 0x4cc2, 0x0057, 0x503a, 0x005c, 0x40ba, 0xbeef, 0x0000, 0x3c02, 0x0000, 0x0000, 0x403b, 0xdead, 0xea2b, 0x23fc, 0x403b, 0x000a, 0x4982, 0x0128, 0x450c, 0x40bc, 0xdead, 0x0000, 0x403c, 0x227a, 0x831c, 0x23fe, 0x40b2, 0xa500, 0x0128, 0x831b, 0x23f1, 0x40f2, 0x0087, 0x0057, 0x3c05, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3fff, 0x4303, } }; static const struct chipinfo_funclet write_fll = { .code_size = 48, .max_payload = 128, .entry_point = 0x0000, .code = { 0x400a, 0x40b2, 0x5a80, 0x0120, 0x503a, 0x005c, 0x40ba, 0xbeef, 0x0000, 0x3c06, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x403b, 0xdead, 0xea2b, 0x23fc, 0x4a0b, 0x532b, 0x450c, 0x9bac, 0x0000, 0x240e, 0x40b2, 0xa540, 0x0128, 0x4bac, 0x0000, 0xb392, 0x012c, 0x23fd, 0x40b2, 0xa500, 0x0128, 0x40b2, 0xa500, 0x012c, 0x532b, 0x532c, 0x8316, 0x23eb, 0x3c01, 0xffff, 0x3fff, 0x4303, } }; static const struct chipinfo_funclet write_430i = { .code_size = 48, .max_payload = 128, .entry_point = 0x0000, .code = { 0x400a, 0x40b2, 0x5a80, 0x0120, 0x503a, 0x005c, 0x40ba, 0xbeef, 0x0000, 0x3c06, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x403b, 0xdead, 0xea2b, 0x23fc, 0x4a0b, 0x532b, 0x450c, 0x40b2, 0xa540, 0x0128, 0x4bac, 0x0000, 0xb392, 0x012c, 0x23fd, 0x40b2, 0xa500, 0x0128, 0x532b, 0x532c, 0x8316, 0x23f1, 0x40b2, 0xa500, 0x012c, 0x3c04, 0xffff, 0xffff, 0xffff, 0xffff, 0x3fff, 0x4303, } }; static const struct chipinfo_funclet write_dco = { .code_size = 48, .max_payload = 128, .entry_point = 0x0000, .code = { 0x400a, 0x40b2, 0x5a80, 0x0120, 0x4bc2, 0x0056, 0x4cc2, 0x0057, 0x503a, 0x005c, 0x40ba, 0xbeef, 0x0000, 0x3c02, 0x0000, 0x0000, 0x403b, 0xdead, 0xea2b, 0x23fc, 0x4a0b, 0x532b, 0x450c, 0x40b2, 0xa540, 0x0128, 0x4bac, 0x0000, 0xb392, 0x012c, 0x23fd, 0x40b2, 0xa500, 0x0128, 0x40b2, 0xa500, 0x012c, 0x532b, 0x532c, 0x8316, 0x23ee, 0x40f2, 0x0087, 0x0057, 0x3c01, 0x0000, 0x3fff, 0x4303, } }; static const struct chipinfo_funclet erase_xfll = { .code_size = 54, .max_payload = 4, .entry_point = 0x0000, .code = { 0x1800, 0x404a, 0x40b2, 0x5a80, 0x0120, 0x1840, 0x503a, 0x0066, 0x1840, 0x40ba, 0xbeef, 0x0000, 0x3c04, 0x0000, 0x0000, 0x0000, 0x0000, 0x403b, 0xdead, 0x1840, 0xea1b, 0x0000, 0x23fa, 0x1840, 0x403b, 0x000a, 0x1840, 0x4982, 0x0128, 0x1800, 0x454c, 0x1840, 0x40bc, 0xdead, 0x0000, 0x1840, 0x403c, 0x227a, 0x832c, 0x23fe, 0x1840, 0x40b2, 0xa500, 0x0128, 0x832b, 0x23ec, 0x3c05, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3fff, 0x4303, } }; static const struct chipinfo_funclet erase_xdco = { .code_size = 54, .max_payload = 4, .entry_point = 0x0000, .code = { 0x1800, 0x404a, 0x40b2, 0x5a80, 0x0120, 0x4bc2, 0x0056, 0x4cc2, 0x0057, 0x1840, 0x503a, 0x0066, 0x1840, 0x40ba, 0xbeef, 0x0000, 0x3c00, 0x403b, 0xdead, 0x1840, 0xea1b, 0x0000, 0x23fa, 0x1840, 0x403b, 0x000a, 0x1840, 0x4982, 0x0128, 0x1800, 0x454c, 0x1840, 0x40bc, 0xdead, 0x0000, 0x1840, 0x403c, 0x227a, 0x832c, 0x23fe, 0x1840, 0x40b2, 0xa500, 0x0128, 0x832b, 0x23ec, 0x40f2, 0x0087, 0x0057, 0x3c02, 0x0000, 0x0000, 0x3fff, 0x4303, } }; static const struct chipinfo_funclet write_xfll = { .code_size = 54, .max_payload = 256, .entry_point = 0x0000, .code = { 0x1800, 0x404a, 0x40b2, 0x5a80, 0x0120, 0x1840, 0x503a, 0x0066, 0x1840, 0x40ba, 0xbeef, 0x0000, 0x3c04, 0xffff, 0xffff, 0xffff, 0xffff, 0x403b, 0xdead, 0x1840, 0xea1b, 0x0000, 0x23fa, 0x1840, 0x4a0b, 0x1840, 0x532b, 0x1800, 0x454c, 0x1840, 0x9bac, 0x0000, 0x240e, 0x40b2, 0xa540, 0x0128, 0x4bac, 0x0000, 0xb392, 0x012c, 0x23fd, 0x40b2, 0xa500, 0x0128, 0x40b2, 0xa500, 0x012c, 0x03eb, 0x03ec, 0x8316, 0x23ea, 0x3c00, 0x3fff, 0x4303, } }; static const struct chipinfo_funclet write_xdco = { .code_size = 54, .max_payload = 256, .entry_point = 0x0000, .code = { 0x1800, 0x404a, 0x40b2, 0x5a80, 0x0120, 0x4bc2, 0x0056, 0x4cc2, 0x0057, 0x1840, 0x503a, 0x0066, 0x1840, 0x40ba, 0xbeef, 0x0000, 0x3c00, 0x403b, 0xdead, 0x1840, 0xea1b, 0x0000, 0x23fa, 0x1840, 0x4a0b, 0x1840, 0x532b, 0x1800, 0x454c, 0x40b2, 0xa540, 0x0128, 0x4bac, 0x0000, 0xb392, 0x012c, 0x23fd, 0x40b2, 0xa500, 0x0128, 0x40b2, 0xa500, 0x012c, 0x03eb, 0x03ec, 0x8316, 0x23ee, 0x40f2, 0x0087, 0x0057, 0x3c01, 0x0000, 0x3fff, 0x4303, } }; static const struct chipinfo_funclet erase_xv2_fram = { .code_size = 60, .max_payload = 0, .entry_point = 0x000c, .code = { 0x000c, 0x0076, 0xdead, 0x000b, 0xdead, 0x000b, 0x40b2, 0x5a80, 0x015c, 0x180f, 0x4ac0, 0xffee, 0x180f, 0x4bc0, 0xffec, 0x40b2, 0x00d0, 0x0186, 0x40b2, 0xabad, 0x018e, 0x40b2, 0xbabe, 0x018c, 0xb3a2, 0x0186, 0x27fd, 0x90b2, 0xbeef, 0x0188, 0x23f9, 0x90b2, 0xdead, 0x018a, 0x23f5, 0x1800, 0x454a, 0x1800, 0x464b, 0x43ba, 0x0000, 0x1800, 0x536a, 0x1800, 0x836b, 0x930b, 0x23f8, 0x1f80, 0x405a, 0xffa2, 0x1f80, 0x405b, 0xffa0, 0x40b2, 0xcafe, 0x018e, 0x40b2, 0xbabe, 0x018c, 0x3fff, } }; static const struct chipinfo_funclet write_xv2_fram = { .code_size = 71, .max_payload = 0, .entry_point = 0x0012, .code = { 0x0012, 0x008c, 0x0000, 0xa500, 0xa500, 0xdead, 0x000b, 0xdead, 0x000b, 0x40b2, 0x5a80, 0x015c, 0x40b2, 0xabad, 0x018e, 0x40b2, 0xbabe, 0x018c, 0x180f, 0x4ac0, 0xffe2, 0x180f, 0x4bc0, 0xffe0, 0x1800, 0x454a, 0x1800, 0x464b, 0x40b2, 0x00d0, 0x0186, 0xb3a2, 0x0186, 0x27fd, 0x429a, 0x0188, 0x0000, 0xc392, 0x0186, 0x1800, 0x536a, 0x1800, 0x835b, 0x930b, 0x2001, 0x3c0c, 0x429a, 0x018a, 0x0000, 0xc3a2, 0x0186, 0x1800, 0x536a, 0x1800, 0x835b, 0x930b, 0x23e6, 0x3c00, 0x1f80, 0x405a, 0xff92, 0x1f80, 0x405b, 0xff90, 0x40b2, 0xcafe, 0x018e, 0x40b2, 0xbabe, 0x018c, 0x3fff, } }; static const struct chipinfo_funclet bsl_unlock_xv2 = { .code_size = 72, .max_payload = 0, .entry_point = 0x0018, .code = { 0x0018, 0x008e, 0xdead, 0x000b, 0xdead, 0x000b, 0xdead, 0x000b, 0xdead, 0x000b, 0xdead, 0x000b, 0x40b2, 0x5a80, 0x015c, 0x4180, 0xfff4, 0x180f, 0x4bc0, 0xffea, 0x180f, 0x4cc0, 0xffd8, 0x180f, 0x4dc0, 0xffd6, 0x40b2, 0x00d0, 0x0186, 0x40b2, 0xabad, 0x018e, 0x40b2, 0xbabe, 0x018c, 0xb3a2, 0x0186, 0x27fd, 0x90b2, 0xbeef, 0x0188, 0x23f9, 0x90b2, 0xdead, 0x018a, 0x23f5, 0x1800, 0x435c, 0x403d, 0xdead, 0x403e, 0xbeef, 0x13b0, 0x1002, 0x4011, 0xffa6, 0x1f80, 0x405b, 0xff9c, 0x1f80, 0x405c, 0xff8a, 0x1f80, 0x405d, 0xff88, 0x40b2, 0xcafe, 0x018e, 0x40b2, 0xbabe, 0x018c, 0x3fff, } }; static const struct chipinfo_funclet erase_xv2 = { .code_size = 102, .max_payload = 0, .entry_point = 0x000e, .code = { 0x000e, 0x00ca, 0xa508, 0xa500, 0xa500, 0xdead, 0x000b, 0x40b2, 0x5a80, 0x015c, 0x4213, 0xfffe, 0x4290, 0x0140, 0xffea, 0x4290, 0x0144, 0xffe6, 0x180f, 0x4ac0, 0xffe2, 0x40b2, 0x00d0, 0x0186, 0x40b2, 0xabad, 0x018e, 0x40b2, 0xbabe, 0x018c, 0xb3a2, 0x0186, 0x27fd, 0x90b2, 0xbeef, 0x0188, 0x23f9, 0x90b2, 0xdead, 0x018a, 0x23f5, 0xb392, 0x0144, 0x23fd, 0x4882, 0x0144, 0x4290, 0x0144, 0xffa4, 0x98c0, 0xffa0, 0x2405, 0x480a, 0xd03a, 0x0040, 0x4a82, 0x0144, 0x1800, 0x454a, 0x4982, 0x0140, 0x40ba, 0xdead, 0x0000, 0xb392, 0x0144, 0x23fd, 0x1f80, 0x405a, 0xff80, 0xe0b0, 0x3300, 0xff76, 0xe0b0, 0x3300, 0xff72, 0x4092, 0xff6c, 0x0140, 0x4092, 0xff68, 0x0144, 0x4290, 0x0144, 0xff5c, 0x90d0, 0xff5c, 0xff56, 0x2406, 0xd0b0, 0x0040, 0xff52, 0x4092, 0xff4e, 0x0144, 0x40b2, 0xcafe, 0x018e, 0x40b2, 0xbabe, 0x018c, 0x3fff, } }; static const struct chipinfo_funclet write_xv2 = { .code_size = 122, .max_payload = 0, .entry_point = 0x0012, .code = { 0x0012, 0x00f2, 0xa508, 0xa500, 0xa500, 0xdead, 0x000b, 0xdead, 0x000b, 0x40b2, 0x5a80, 0x015c, 0x40b2, 0xabad, 0x018e, 0x40b2, 0xbabe, 0x018c, 0x4290, 0x0140, 0xffde, 0x4290, 0x0144, 0xffda, 0x180f, 0x4ac0, 0xffd6, 0x180f, 0x4bc0, 0xffd4, 0xb392, 0x0144, 0x23fd, 0x4882, 0x0144, 0x4290, 0x0144, 0xffba, 0x98c0, 0xffb6, 0x2405, 0x480a, 0xd03a, 0x0040, 0x4a82, 0x0144, 0x1800, 0x454a, 0x1800, 0x464b, 0x40b2, 0x00d0, 0x0186, 0xb3a2, 0x0186, 0x27fd, 0x40b2, 0xa580, 0x0140, 0x429a, 0x0188, 0x0000, 0x1800, 0x536a, 0x1800, 0x835b, 0x429a, 0x018a, 0x0000, 0xc3a2, 0x0186, 0xc392, 0x0186, 0xb392, 0x0144, 0x23fd, 0x40b2, 0xa500, 0x0140, 0x1800, 0x536a, 0x1800, 0x835b, 0x23e1, 0x1f80, 0x405a, 0xff5e, 0x1f80, 0x405b, 0xff5c, 0xe0b0, 0x3300, 0xff4e, 0xe0b0, 0x3300, 0xff4a, 0x4092, 0xff44, 0x0140, 0x4092, 0xff40, 0x0144, 0x4290, 0x0144, 0xff34, 0x90d0, 0xff34, 0xff2e, 0x2406, 0xd0b0, 0x0040, 0xff2a, 0x4092, 0xff26, 0x0144, 0x40b2, 0xcafe, 0x018e, 0x40b2, 0xbabe, 0x018c, 0x3fff, } }; static const struct chipinfo_funclet write_xv2_word = { .code_size = 144, .max_payload = 0, .entry_point = 0x0012, .code = { 0x0012, 0x011e, 0xa508, 0xa500, 0xa500, 0xdead, 0x000b, 0xdead, 0x000b, 0x40b2, 0x5a80, 0x015c, 0x40b2, 0xabad, 0x018e, 0x40b2, 0xbabe, 0x018c, 0x4290, 0x0140, 0xffde, 0x4290, 0x0144, 0xffda, 0x180f, 0x4ac0, 0xffd6, 0x180f, 0x4bc0, 0xffd4, 0xb392, 0x0144, 0x23fd, 0x4882, 0x0144, 0x4290, 0x0144, 0xffba, 0x98c0, 0xffb6, 0x2405, 0x480a, 0xd03a, 0x0040, 0x4a82, 0x0144, 0x1800, 0x454a, 0x1800, 0x464b, 0x40b2, 0x00d0, 0x0186, 0xb392, 0x0186, 0x27fd, 0x421d, 0x0188, 0xc392, 0x0186, 0xb392, 0x0144, 0x23fd, 0x40b2, 0xa500, 0x0140, 0x40b2, 0xa540, 0x0140, 0x4d8a, 0x0000, 0x1800, 0x536a, 0x1800, 0x835b, 0x2417, 0xb3a2, 0x0186, 0x27fd, 0x421e, 0x018a, 0xc3a2, 0x0186, 0xb392, 0x0144, 0x23fd, 0x40b2, 0xa500, 0x0140, 0x40b2, 0xa540, 0x0140, 0x4e8a, 0x0000, 0x1800, 0x536a, 0x1800, 0x835b, 0x23d2, 0xb392, 0x0144, 0x23fd, 0xc3a2, 0x0186, 0xc392, 0x0186, 0x1f80, 0x405a, 0xff32, 0x1f80, 0x405b, 0xff30, 0xe0b0, 0x3300, 0xff22, 0xe0b0, 0x3300, 0xff1e, 0x4092, 0xff18, 0x0140, 0x4092, 0xff14, 0x0144, 0x4290, 0x0144, 0xff08, 0x90d0, 0xff08, 0xff02, 0x2406, 0xd0b0, 0x0040, 0xfefe, 0x4092, 0xfefa, 0x0144, 0x40b2, 0xcafe, 0x018e, 0x40b2, 0xbabe, 0x018c, 0x3fff, } }; const struct chipinfo chipinfo_db[] = { { .name = "DeviceUnknown", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x00, .mclk_control = 0x0000, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x0000, .ver_sub_id = 0x0000, .revision = 0xff, .fab = 0xff, .self = 0xffff, .config = 0xff, .fuses = 0xff, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0xff, .fab = 0xff, .self = 0xffff, .config = 0xff, .fuses = 0xff, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "DeviceUnknown", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 0, .offset = 0x00000, .seg_size = 0, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "F20x1_G2x0x_G2x1x", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x01f2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x01, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_NO_BSL, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x0f800, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "F20x2_G2x2x_G2x3x", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x01f2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x02, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_NO_BSL, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x0f800, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F20x3", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x01f2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x03, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_NO_BSL, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x0f800, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F11x1", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x00, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x12f1, .ver_sub_id = 0x0000, .revision = 0x10, .fab = 0x40, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0xff, .fab = 0xff, .self = 0xffff, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX, .features = 0, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x0f000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F11x1A", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x00, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x12f1, .ver_sub_id = 0x0000, .revision = 0x13, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0xff, .fab = 0x00, .self = 0xffff, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX, .features = 0, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x0f000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5513", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {0}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x1355, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F21x1", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x13f2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x01, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F2132", .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x13f2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x02, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x03, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F2122", .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x13f2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x02, .fuses = 0x01, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x03, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x0f000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F2112", .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x13f2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x02, .fuses = 0x02, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x03, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x0f800, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F41x", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x13f4, .ver_sub_id = 0x0000, .revision = 0x02, .fab = 0x40, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0xff, .fab = 0xff, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x1f] = 0x20, [0x21] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_SFLLDH | CHIPINFO_FEATURE_JTAG | CHIPINFO_FEATURE_INSTR, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 13, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5514", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {0}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x1455, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 65536, .offset = 0x04400, .seg_size = 512, .bank_size = 65536, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 2, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5515", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {0}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x1555, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 65536, .offset = 0x04400, .seg_size = 512, .bank_size = 65536, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 2, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5517", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {0}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x1755, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 98304, .offset = 0x04400, .seg_size = 512, .bank_size = 65536, .banks = 3, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 6144, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 3, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5418", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {0}, {"ADC12A", 0x38}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {"Timer0_B7", 0x1c}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x1854, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x05c00, .seg_size = 512, .bank_size = 65536, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5419", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {0}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {"Timer0_B7", 0x1c}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x1954, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x05c00, .seg_size = 512, .bank_size = 65536, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5519", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {0}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x1955, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04400, .seg_size = 512, .bank_size = 65536, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430I204x_I203x_I202x", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x03, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x2040, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x49] = 0x53, [0x4c] = 0x52, }, .v3_erase = &erase_dco, .v3_write = &write_430i, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 1024, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01000, .seg_size = 1024, .bank_size = 1024, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5521", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x2155, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5522", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x2255, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F12x", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x00, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x23f1, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x1f] = 0x20, [0x21] = 0x22, }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX, .features = 0 | CHIPINFO_FEATURE_JTAG, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5524", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x2455, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 65536, .offset = 0x04400, .seg_size = 512, .bank_size = 65536, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 2, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5525", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x2555, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 65536, .offset = 0x04400, .seg_size = 512, .bank_size = 65536, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 2, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "CC430F6125", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {0}, {"AES128", 0x04}, {"Comparator B", 0x2a}, {0}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"LCDB", 0x2c}, {0}, {0}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x2561, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, .bank_size = 65536, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5526", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x2655, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 98304, .offset = 0x04400, .seg_size = 512, .bank_size = 65536, .banks = 3, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 6144, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 3, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "CC430F6126", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {0}, {"AES128", 0x04}, {"Comparator B", 0x2a}, {0}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"LCDB", 0x2c}, {0}, {0}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x2661, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5527", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x2755, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 98304, .offset = 0x04400, .seg_size = 512, .bank_size = 65536, .banks = 3, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 6144, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 3, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "CC430F6127", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {0}, {"AES128", 0x04}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"LCDB", 0x2c}, {0}, {0}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x2761, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 2, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F2274", .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x27f2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x07, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_PSACH, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F2254", .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x27f2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x01, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x07, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_PSACH, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F2234", .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x27f2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x02, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x07, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_PSACH, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F2272_G2744", .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x27f2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x04, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x07, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_PSACH, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F2252_G2544", .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x27f2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x05, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x07, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_PSACH, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F2232_G2444", .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x27f2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x06, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x07, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_PSACH, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FE427", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x27f4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x45, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x1f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 2700, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2700, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_SFLLDH | CHIPINFO_FEATURE_SYNC, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 21, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FE425", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x27f4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x45, .fuses = 0x01, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x1f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 2700, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2700, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_SFLLDH | CHIPINFO_FEATURE_SYNC, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 21, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FE423", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x27f4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x45, .fuses = 0x02, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x1f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 2700, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2700, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_SFLLDH | CHIPINFO_FEATURE_SYNC, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 21, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F427", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x27f4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x45, .fuses = 0x04, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x1f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 2700, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2700, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_SFLLDH | CHIPINFO_FEATURE_SYNC, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 21, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F425", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x27f4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x45, .fuses = 0x05, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x1f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 2700, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2700, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_SFLLDH | CHIPINFO_FEATURE_SYNC, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 21, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F423", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x27f4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x45, .fuses = 0x06, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x1f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 2700, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2700, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_SFLLDH | CHIPINFO_FEATURE_SYNC, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 21, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FG42x0", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x27f4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x47, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x07, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2500, .vcc_secure_min = 2700, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_SFLLDH | CHIPINFO_FEATURE_SYNC | CHIPINFO_FEATURE_INSTR, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FG4250", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x27f4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x47, .fuses = 0x01, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x07, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2500, .vcc_secure_min = 2700, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_SFLLDH | CHIPINFO_FEATURE_SYNC | CHIPINFO_FEATURE_INSTR, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F42x0", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x27f4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x47, .fuses = 0x04, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x07, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2500, .vcc_secure_min = 2700, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_SFLLDH | CHIPINFO_FEATURE_SYNC | CHIPINFO_FEATURE_INSTR, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F4250", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x27f4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x47, .fuses = 0x05, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x07, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2500, .vcc_secure_min = 2700, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_SFLLDH | CHIPINFO_FEATURE_SYNC | CHIPINFO_FEATURE_INSTR, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F4230", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x27f4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x47, .fuses = 0x06, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x07, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2500, .vcc_secure_min = 2700, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_SFLLDH | CHIPINFO_FEATURE_SYNC | CHIPINFO_FEATURE_INSTR, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FW42x/F41x", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x27f4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x57, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_SFLLDH, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 13, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5528", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x2855, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04400, .seg_size = 512, .bank_size = 65536, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5529", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x2955, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04400, .seg_size = 512, .bank_size = 65536, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FW429", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x29f4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x57, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_SFLLDH | CHIPINFO_FEATURE_INSTR, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 61184, .offset = 0x01100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 21, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F11x2", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x00, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x3211, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX, .features = 0, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F12x2/F11x2", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x00, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x3212, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "CC430F5133", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {0}, {"AES128", 0x04}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x3351, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, .bank_size = 65536, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "CC430F5135", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {0}, {"AES128", 0x04}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x3551, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, .bank_size = 65536, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5435", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {0}, {"ADC12A", 0x38}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {"Timer0_B7", 0x1c}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x3554, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 196608, .offset = 0x05c00, .seg_size = 512, .bank_size = 65536, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "CC430F6135", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {0}, {"AES128", 0x04}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"LCDB", 0x2c}, {0}, {0}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x3561, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, .bank_size = 65536, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5436", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {0}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {"Timer0_B7", 0x1c}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x3654, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 196608, .offset = 0x05c00, .seg_size = 512, .bank_size = 65536, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "CC430F5137", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {0}, {"AES128", 0x04}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x3751, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 2, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5437", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {0}, {"ADC12A", 0x38}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {"Timer0_B7", 0x1c}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x3754, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x05c00, .seg_size = 512, .bank_size = 65536, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "CC430F6137", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {0}, {"AES128", 0x04}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"LCDB", 0x2c}, {0}, {0}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x3761, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 2, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F2370", .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x37f2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x03, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F2350", .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x37f2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x01, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x03, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F2330", .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x37f2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x02, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x03, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F43x", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, {0}, {"USART0", 0x00}, {0}, {0}, {"LCD Frequency", 0x00}, {"BasicTimer", 0x00}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x37f4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x00, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_SYNC, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 21, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5438", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {0}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {"Timer0_B7", 0x1c}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x3854, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x05c00, .seg_size = 512, .bank_size = 65536, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FG43x_F43x", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, {0}, {"USART0", 0x00}, {0}, {0}, {"LCD Frequency", 0x00}, {"BasicTimer", 0x00}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x39f4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x47, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x01, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 61184, .offset = 0x01100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 13, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F149", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x00, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x49f1, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x02, .trig_mem = 0x03, .trig_reg = 0x00, .trig_combinations = 0x03, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 61184, .offset = 0x01100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F148", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x00, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x49f1, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x01, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x02, .trig_mem = 0x03, .trig_reg = 0x00, .trig_combinations = 0x03, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 49152, .offset = 0x04000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F147", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x00, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x49f1, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x02, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x02, .trig_mem = 0x03, .trig_reg = 0x00, .trig_combinations = 0x03, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F1471", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x00, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x49f1, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x03, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x02, .trig_mem = 0x03, .trig_reg = 0x00, .trig_combinations = 0x03, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 5120, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F135", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x00, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x49f1, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x04, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x02, .trig_mem = 0x03, .trig_reg = 0x00, .trig_combinations = 0x03, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F133", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x00, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x49f1, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x05, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x02, .trig_mem = 0x03, .trig_reg = 0x00, .trig_combinations = 0x03, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F1491", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x00, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x49f1, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x06, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x02, .trig_mem = 0x03, .trig_reg = 0x00, .trig_combinations = 0x03, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 61184, .offset = 0x01100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 5120, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F249", .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {0}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x49f2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x02, .trig_mem = 0x03, .trig_reg = 0x00, .trig_combinations = 0x03, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 61184, .offset = 0x01100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F248", .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {0}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x49f2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x01, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x02, .trig_mem = 0x03, .trig_reg = 0x00, .trig_combinations = 0x03, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 49152, .offset = 0x04000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F247", .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {0}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x49f2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x02, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x02, .trig_mem = 0x03, .trig_reg = 0x00, .trig_combinations = 0x03, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F235", .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {0}, {0}, {"USCI0", 0x1f}, {0}, {0}, {0}, {0}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x49f2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x03, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x02, .trig_mem = 0x03, .trig_reg = 0x00, .trig_combinations = 0x03, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F2491", .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {0}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x49f2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x04, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x02, .trig_mem = 0x03, .trig_reg = 0x00, .trig_combinations = 0x03, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 61184, .offset = 0x01100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F2481", .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {0}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x49f2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x05, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x02, .trig_mem = 0x03, .trig_reg = 0x00, .trig_combinations = 0x03, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 49152, .offset = 0x04000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F2471", .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {0}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x49f2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x06, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x02, .trig_mem = 0x03, .trig_reg = 0x00, .trig_combinations = 0x03, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F233", .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {0}, {0}, {"USCI0", 0x1f}, {0}, {0}, {0}, {0}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x49f2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x07, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x02, .trig_mem = 0x03, .trig_reg = 0x00, .trig_combinations = 0x03, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F2410", .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {0}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x49f2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x08, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x02, .trig_mem = 0x03, .trig_reg = 0x00, .trig_combinations = 0x03, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 57088, .offset = 0x02100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F44x", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, {"USART1", 0x00}, {"USART0", 0x00}, {0}, {0}, {"LCD Frequency", 0x00}, {"BasicTimer", 0x00}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x49f4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x00, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_SYNC, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 61184, .offset = 0x01100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 21, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F43x", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, {0}, {"USART0", 0x00}, {0}, {0}, {"LCD Frequency", 0x00}, {"BasicTimer", 0x00}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x49f4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x02, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x00, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_SYNC, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 21, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F4794", .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {"SD16", 0x00}, {"Flash Control", 0x00}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {"LCD Frequency", 0x00}, {"BasicTimer", 0x00}, {0}, {"TimerB/MCLK (Pin)", 0x00}, {"TimerA/SMCLK (Pin)", 0x00}, {"Watchdog Timer/ACLK (Pin)", 0x00}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x49f4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x02, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x07, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_SYNC, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 61184, .offset = 0x01100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2560, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F4784", .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {"SD16", 0x00}, {"Flash Control", 0x00}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {"LCD Frequency", 0x00}, {"BasicTimer", 0x00}, {0}, {"TimerB/MCLK (Pin)", 0x00}, {"TimerA/SMCLK (Pin)", 0x00}, {"Watchdog Timer/ACLK (Pin)", 0x00}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x49f4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x02, .fuses = 0x03, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x07, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_SYNC, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 49152, .offset = 0x04000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F4793", .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {"SD16", 0x00}, {"Flash Control", 0x00}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {"LCD Frequency", 0x00}, {"BasicTimer", 0x00}, {0}, {"TimerB/MCLK (Pin)", 0x00}, {"TimerA/SMCLK (Pin)", 0x00}, {"Watchdog Timer/ACLK (Pin)", 0x00}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x49f4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x02, .fuses = 0x04, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x07, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_SYNC, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 61184, .offset = 0x01100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2560, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F4783", .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {"SD16", 0x00}, {"Flash Control", 0x00}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {"LCD Frequency", 0x00}, {"BasicTimer", 0x00}, {0}, {"TimerB/MCLK (Pin)", 0x00}, {"TimerA/SMCLK (Pin)", 0x00}, {"Watchdog Timer/ACLK (Pin)", 0x00}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x49f4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x02, .fuses = 0x07, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x07, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_SYNC, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 49152, .offset = 0x04000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430G2xx2", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x5224, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_NO_BSL, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F4152", .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {0}, {"Flash Controller", 0x00}, {0}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"BasicTimer/RTC", 0x00}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x5241, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x01, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2700, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F4132", .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {0}, {"Flash Controller", 0x00}, {0}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"BasicTimer/RTC", 0x00}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x5241, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x01, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x01, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2700, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FE4272", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x5242, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x45, .fuses = 0x10, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x1f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 2700, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2700, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_SFLLDH | CHIPINFO_FEATURE_SYNC, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 21, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FE42x2", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x5242, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x45, .fuses = 0x11, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x1f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 2700, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2700, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_SFLLDH | CHIPINFO_FEATURE_SYNC, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 21, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FE4232", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x5242, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x45, .fuses = 0x12, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x1f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 2700, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2700, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_SFLLDH | CHIPINFO_FEATURE_SYNC, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 21, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430AFE253", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x5302, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x19] = 0x1a, }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_NO_BSL, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430AFE233", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x5302, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x02, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x19] = 0x1a, }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_NO_BSL, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430AFE223", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x5302, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x03, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x19] = 0x1a, }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_NO_BSL, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x0f000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430AFE252", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x5302, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x04, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x19] = 0x1a, }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_NO_BSL, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430AFE232", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x5302, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x06, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x19] = 0x1a, }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_NO_BSL, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430AFE222", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x5302, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x07, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x19] = 0x1a, }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_NO_BSL, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x0f000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430AFE251", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x5302, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x08, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x19] = 0x1a, }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_NO_BSL, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430AFE231", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x5302, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0a, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x19] = 0x1a, }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_NO_BSL, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430AFE221", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x5302, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0b, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x19] = 0x1a, }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_NO_BSL, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x0f000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430AFE250", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x5302, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0c, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x19] = 0x1a, }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_NO_BSL, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430AFE230", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x5302, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0e, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x19] = 0x1a, }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_NO_BSL, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430AFE220", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x5302, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x19] = 0x1a, }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_NO_BSL, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x0f000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430G2xx3", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x5325, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_NO_BSL, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430G2x55", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x03, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x5529, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x19] = 0x1a, }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_NO_BSL, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 57088, .offset = 0x02100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430TCH5E", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x5c25, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_NO_BSL, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F169", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, {"USART1", 0x00}, {"USART0", 0x00}, {0}, {0}, {0}, {0}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x69f1, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX, .features = 0 | CHIPINFO_FEATURE_I2C | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 61184, .offset = 0x01100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F168", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, {"USART1", 0x00}, {"USART0", 0x00}, {0}, {0}, {0}, {0}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x69f1, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x01, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX, .features = 0 | CHIPINFO_FEATURE_I2C | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 49152, .offset = 0x04000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F167", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, {"USART1", 0x00}, {"USART0", 0x00}, {0}, {0}, {0}, {0}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x69f1, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x02, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX, .features = 0 | CHIPINFO_FEATURE_I2C | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F157", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, {0}, {"USART0", 0x00}, {0}, {0}, {0}, {0}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x69f1, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x04, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX, .features = 0 | CHIPINFO_FEATURE_I2C | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F156", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, {0}, {"USART0", 0x00}, {0}, {0}, {0}, {0}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x69f1, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x05, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX, .features = 0 | CHIPINFO_FEATURE_I2C | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 24576, .offset = 0x0a000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F155", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, {0}, {"USART0", 0x00}, {0}, {0}, {0}, {0}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x69f1, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x06, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX, .features = 0 | CHIPINFO_FEATURE_I2C | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F1611", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, {"USART1", 0x00}, {"USART0", 0x00}, {0}, {0}, {0}, {0}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x6cf1, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x07, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX, .features = 0 | CHIPINFO_FEATURE_I2C | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 49152, .offset = 0x04000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 10240, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F1610", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, {"USART1", 0x00}, {"USART0", 0x00}, {0}, {0}, {0}, {0}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x6cf1, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x03, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x07, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX, .features = 0 | CHIPINFO_FEATURE_I2C | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 5120, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F1612", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, {"USART1", 0x00}, {"USART0", 0x00}, {0}, {0}, {0}, {0}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x6cf1, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x06, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x07, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX, .features = 0 | CHIPINFO_FEATURE_I2C | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 56064, .offset = 0x02500, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 5120, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F169", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, {"USART1", 0x00}, {"USART0", 0x00}, {0}, {0}, {0}, {0}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x6cf1, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x07, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x07, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX, .features = 0 | CHIPINFO_FEATURE_I2C | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 61184, .offset = 0x01100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F2619", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"BasicTimer", 0x00}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x6ff2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x07, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, [0x15] = 0x2a, [0x16] = 0x2b, [0x18] = 0x2d, [0x19] = 0x2e, [0x1b] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, [0x21] = 0x34, [0x25] = 0x36, }, .v3_erase = &erase_xdco, .v3_write = &write_xdco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 122624, .offset = 0x02100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F2618", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"BasicTimer", 0x00}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x6ff2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x01, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x07, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, [0x15] = 0x2a, [0x16] = 0x2b, [0x18] = 0x2d, [0x19] = 0x2e, [0x1b] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, [0x21] = 0x34, [0x25] = 0x36, }, .v3_erase = &erase_xdco, .v3_write = &write_xdco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 118528, .offset = 0x03100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F2617", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"BasicTimer", 0x00}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x6ff2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x02, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x07, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, [0x15] = 0x2a, [0x16] = 0x2b, [0x18] = 0x2d, [0x19] = 0x2e, [0x1b] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, [0x21] = 0x34, [0x25] = 0x36, }, .v3_erase = &erase_xdco, .v3_write = &write_xdco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 93952, .offset = 0x03100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F2616", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"BasicTimer", 0x00}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x6ff2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x03, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x07, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, [0x15] = 0x2a, [0x16] = 0x2b, [0x18] = 0x2d, [0x19] = 0x2e, [0x1b] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, [0x21] = 0x34, [0x25] = 0x36, }, .v3_erase = &erase_xdco, .v3_write = &write_xdco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 93952, .offset = 0x02100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F2419", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"BasicTimer", 0x00}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x6ff2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x04, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x07, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, [0x15] = 0x2a, [0x16] = 0x2b, [0x18] = 0x2d, [0x19] = 0x2e, [0x1b] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, [0x21] = 0x34, [0x25] = 0x36, }, .v3_erase = &erase_xdco, .v3_write = &write_xdco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 122624, .offset = 0x02100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F2418", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"BasicTimer", 0x00}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x6ff2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x05, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x07, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, [0x15] = 0x2a, [0x16] = 0x2b, [0x18] = 0x2d, [0x19] = 0x2e, [0x1b] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, [0x21] = 0x34, [0x25] = 0x36, }, .v3_erase = &erase_xdco, .v3_write = &write_xdco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 118528, .offset = 0x03100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F2417", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"BasicTimer", 0x00}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x6ff2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x06, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x07, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, [0x15] = 0x2a, [0x16] = 0x2b, [0x18] = 0x2d, [0x19] = 0x2e, [0x1b] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, [0x21] = 0x34, [0x25] = 0x36, }, .v3_erase = &erase_xdco, .v3_write = &write_xdco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 93952, .offset = 0x03100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F2416", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"BasicTimer", 0x00}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x6ff2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x07, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x07, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, [0x15] = 0x2a, [0x16] = 0x2b, [0x18] = 0x2d, [0x19] = 0x2e, [0x1b] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, [0x21] = 0x34, [0x25] = 0x36, }, .v3_erase = &erase_xdco, .v3_write = &write_xdco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 93952, .offset = 0x02100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FG4619", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {"LCD Frequency", 0x00}, {"BasicTimer", 0x00}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x6ff4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x47, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x03, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, [0x15] = 0x2a, [0x16] = 0x2b, [0x18] = 0x2d, [0x19] = 0x2e, [0x1b] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, [0x21] = 0x35, [0x25] = 0x36, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 122624, .offset = 0x02100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 13, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FG4618", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {"LCD Frequency", 0x00}, {"BasicTimer", 0x00}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x6ff4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x47, .fuses = 0x01, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x03, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, [0x15] = 0x2a, [0x16] = 0x2b, [0x18] = 0x2d, [0x19] = 0x2e, [0x1b] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, [0x21] = 0x35, [0x25] = 0x36, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 118528, .offset = 0x03100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 13, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FG4617", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {"LCD Frequency", 0x00}, {"BasicTimer", 0x00}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x6ff4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x47, .fuses = 0x02, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x03, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, [0x15] = 0x2a, [0x16] = 0x2b, [0x18] = 0x2d, [0x19] = 0x2e, [0x1b] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, [0x21] = 0x35, [0x25] = 0x36, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 93952, .offset = 0x03100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 13, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FG4616", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {"LCD Frequency", 0x00}, {"BasicTimer", 0x00}, {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x6ff4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x47, .fuses = 0x03, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x03, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, [0x15] = 0x2a, [0x16] = 0x2b, [0x18] = 0x2d, [0x19] = 0x2e, [0x1b] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, [0x21] = 0x35, [0x25] = 0x36, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 93952, .offset = 0x02100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 13, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FG479", .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {0}, {"Flash Controller", 0x00}, {0}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"BasicTimer/RTC", 0x00}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x79f4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x47, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x07, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2700, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 61184, .offset = 0x01100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FG478", .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {0}, {"Flash Controller", 0x00}, {0}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"BasicTimer/RTC", 0x00}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x79f4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x47, .fuses = 0x01, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x07, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2700, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 49152, .offset = 0x04000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FG477", .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {0}, {"Flash Controller", 0x00}, {0}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"BasicTimer/RTC", 0x00}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x79f4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x47, .fuses = 0x02, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x07, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2700, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F479", .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {0}, {"Flash Controller", 0x00}, {0}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"BasicTimer/RTC", 0x00}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x79f4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x47, .fuses = 0x04, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x07, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2700, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 61184, .offset = 0x01100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F478", .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {0}, {"Flash Controller", 0x00}, {0}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"BasicTimer/RTC", 0x00}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x79f4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x47, .fuses = 0x05, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x07, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2700, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 49152, .offset = 0x04000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F477", .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {0}, {"Flash Controller", 0x00}, {0}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"BasicTimer/RTC", 0x00}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x79f4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x47, .fuses = 0x06, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x07, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2700, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FE427A", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x7a42, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x45, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x1f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 2700, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2700, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_SFLLDH | CHIPINFO_FEATURE_SYNC, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 21, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FE425A", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x7a42, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x45, .fuses = 0x01, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x1f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 2700, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2700, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_SFLLDH | CHIPINFO_FEATURE_SYNC, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 21, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FE423A", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x7a42, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x45, .fuses = 0x02, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x1f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 2700, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2700, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_SFLLDH | CHIPINFO_FEATURE_SYNC, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 21, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F427A", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x7a42, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x45, .fuses = 0x04, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x1f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 2700, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2700, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_SFLLDH | CHIPINFO_FEATURE_SYNC, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 21, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F425A", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x7a42, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x45, .fuses = 0x05, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x1f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 2700, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2700, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_SFLLDH | CHIPINFO_FEATURE_SYNC, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 21, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F423A", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, .mclk_control = 0x60d7, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x7a42, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x45, .fuses = 0x06, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x7f, .fuses = 0x1f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x01, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x00, .trig_dma = 0x00, .trig_read_write = 0x00, .trig_reg_ops = 0x00, .trig_comp_level = 0x00, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 2700, .vcc_max = 3600, .vcc_flash_min = 2700, .vcc_secure_min = 2700, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x21] = 0x23, }, .v3_erase = &erase_fll, .v3_write = &write_fll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_SFLLDH | CHIPINFO_FEATURE_SYNC, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, .bank_size = 128, .banks = 2, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 21, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F47197", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {0}, {"Flash Control", 0x00}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"BTRTC", 0x29}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x7ff4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x00, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, [0x15] = 0x2a, [0x16] = 0x2b, [0x18] = 0x2d, [0x19] = 0x2e, [0x1b] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, [0x21] = 0x35, [0x25] = 0x36, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 122624, .offset = 0x02100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 21, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F47187", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {0}, {"Flash Control", 0x00}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"BTRTC", 0x29}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x7ff4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x01, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x00, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, [0x15] = 0x2a, [0x16] = 0x2b, [0x18] = 0x2d, [0x19] = 0x2e, [0x1b] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, [0x21] = 0x35, [0x25] = 0x36, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 118528, .offset = 0x03100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 21, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F47177", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {0}, {"Flash Control", 0x00}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"BTRTC", 0x29}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x7ff4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x02, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x00, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, [0x15] = 0x2a, [0x16] = 0x2b, [0x18] = 0x2d, [0x19] = 0x2e, [0x1b] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, [0x21] = 0x35, [0x25] = 0x36, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 93952, .offset = 0x03100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 21, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F47167", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {0}, {"Flash Control", 0x00}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"BTRTC", 0x29}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x7ff4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x03, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x00, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, [0x15] = 0x2a, [0x16] = 0x2b, [0x18] = 0x2d, [0x19] = 0x2e, [0x1b] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, [0x21] = 0x35, [0x25] = 0x36, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 93952, .offset = 0x02100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 21, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F47196", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {0}, {"Flash Control", 0x00}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"BTRTC", 0x29}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x7ff4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x04, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x00, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, [0x15] = 0x2a, [0x16] = 0x2b, [0x18] = 0x2d, [0x19] = 0x2e, [0x1b] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, [0x21] = 0x35, [0x25] = 0x36, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 122624, .offset = 0x02100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 21, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F47186", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {0}, {"Flash Control", 0x00}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"BTRTC", 0x29}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x7ff4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x05, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x00, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, [0x15] = 0x2a, [0x16] = 0x2b, [0x18] = 0x2d, [0x19] = 0x2e, [0x1b] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, [0x21] = 0x35, [0x25] = 0x36, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 118528, .offset = 0x03100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 21, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F47176", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {0}, {"Flash Control", 0x00}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"BTRTC", 0x29}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x7ff4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x06, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x00, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, [0x15] = 0x2a, [0x16] = 0x2b, [0x18] = 0x2d, [0x19] = 0x2e, [0x1b] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, [0x21] = 0x35, [0x25] = 0x36, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 93952, .offset = 0x03100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 21, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F47166", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {0}, {"Flash Control", 0x00}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"BTRTC", 0x29}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x7ff4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x07, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x00, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, [0x15] = 0x2a, [0x16] = 0x2b, [0x18] = 0x2d, [0x19] = 0x2e, [0x1b] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, [0x21] = 0x35, [0x25] = 0x36, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 93952, .offset = 0x02100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 21, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F47193", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {0}, {"Flash Control", 0x00}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"BTRTC", 0x29}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x7ff4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x08, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x00, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, [0x15] = 0x2a, [0x16] = 0x2b, [0x18] = 0x2d, [0x19] = 0x2e, [0x1b] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, [0x21] = 0x35, [0x25] = 0x36, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 122624, .offset = 0x02100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 21, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F47183", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {0}, {"Flash Control", 0x00}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"BTRTC", 0x29}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x7ff4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x09, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x00, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, [0x15] = 0x2a, [0x16] = 0x2b, [0x18] = 0x2d, [0x19] = 0x2e, [0x1b] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, [0x21] = 0x35, [0x25] = 0x36, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 118528, .offset = 0x03100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 21, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F47173", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {0}, {"Flash Control", 0x00}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"BTRTC", 0x29}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x7ff4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0a, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x00, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, [0x15] = 0x2a, [0x16] = 0x2b, [0x18] = 0x2d, [0x19] = 0x2e, [0x1b] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, [0x21] = 0x35, [0x25] = 0x36, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 93952, .offset = 0x03100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 21, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F47163", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {0}, {"Flash Control", 0x00}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"BTRTC", 0x29}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x7ff4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0b, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x00, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, [0x15] = 0x2a, [0x16] = 0x2b, [0x18] = 0x2d, [0x19] = 0x2e, [0x1b] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, [0x21] = 0x35, [0x25] = 0x36, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 93952, .offset = 0x02100, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 21, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F47127", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {0}, {"Flash Control", 0x00}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"BTRTC", 0x29}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x7ff4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0c, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x00, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, [0x15] = 0x2a, [0x16] = 0x2b, [0x18] = 0x2d, [0x19] = 0x2e, [0x1b] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, [0x21] = 0x35, [0x25] = 0x36, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 57344, .offset = 0x02000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 21, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F47126", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x60d7, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, {"SMCLK (Pin)", 0x00}, {"ACLK (Pin)", 0x00}, {0}, {"Flash Control", 0x00}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"BTRTC", 0x29}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x7ff4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0d, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x0f, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x00, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x03, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x08, .trig_options = 0x01, .trig_dma = 0x00, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x01, .seq_start = 0x02, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 2200, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 0, }, .v3_functions = { [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, [0x15] = 0x2a, [0x16] = 0x2b, [0x18] = 0x2d, [0x19] = 0x2e, [0x1b] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, [0x21] = 0x35, [0x25] = 0x36, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 57344, .offset = 0x02000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, .bank_size = 64, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, .bank_size = 0, .banks = 1, }, { .name = "lcd", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 21, .offset = 0x00090, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5418A", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {0}, {"ADC12A", 0x38}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {"Timer0_B7", 0x1c}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8000, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x05c00, .seg_size = 512, .bank_size = 65536, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5419A", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {0}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {"Timer0_B7", 0x1c}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8001, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x05c00, .seg_size = 512, .bank_size = 65536, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5435A", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {0}, {"ADC12A", 0x38}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {"Timer0_B7", 0x1c}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8002, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 196608, .offset = 0x05c00, .seg_size = 512, .bank_size = 65536, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5436A", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {0}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {"Timer0_B7", 0x1c}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8003, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 196608, .offset = 0x05c00, .seg_size = 512, .bank_size = 65536, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5437A", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {0}, {"ADC12A", 0x38}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {"Timer0_B7", 0x1c}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8004, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x05c00, .seg_size = 512, .bank_size = 65536, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5438A", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {0}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {"Timer0_B7", 0x1c}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8005, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x05c00, .seg_size = 512, .bank_size = 65536, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5438A", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {0}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {"Timer0_B7", 0x1c}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8005, .ver_sub_id = 0x0001, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x05c00, .seg_size = 512, .bank_size = 65536, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5635", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x800e, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5636", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {"DAC12", 0x32}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8010, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5637", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {"DAC12", 0x32}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8012, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 196608, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 3, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5638", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {"DAC12", 0x32}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8014, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6635", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {"LCDB", 0x2c}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8016, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6636", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {"LCDB", 0x2c}, {"DAC12", 0x32}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8018, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6637", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {"LCDB", 0x2c}, {"DAC12", 0x32}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x801a, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 196608, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 3, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6638", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {"LCDB", 0x2c}, {"DAC12", 0x32}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x801c, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5131", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {0}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer1_D3", 0x13}, {"Timer0_D3", 0x12}, {"Timer0_A3", 0x08}, {0}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8026, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, .bank_size = 32768, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5132", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC10", 0x36}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer1_D3", 0x13}, {"Timer0_D3", 0x12}, {"Timer0_A3", 0x08}, {0}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8028, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, .bank_size = 32768, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5151", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {0}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer1_D3", 0x13}, {"Timer0_D3", 0x12}, {"Timer0_A3", 0x08}, {0}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x802a, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, .bank_size = 32768, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5152", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC10", 0x36}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer1_D3", 0x13}, {"Timer0_D3", 0x12}, {"Timer0_A3", 0x08}, {0}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x802c, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, .bank_size = 32768, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5171", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {0}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer1_D3", 0x13}, {"Timer0_D3", 0x12}, {"Timer0_A3", 0x08}, {0}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x802e, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 32768, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5172", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC10", 0x36}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer1_D3", 0x13}, {"Timer0_D3", 0x12}, {"Timer0_A3", 0x08}, {0}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8030, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 32768, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5510", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC10", 0x36}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8031, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, .bank_size = 2, .banks = 2, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5501", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC10", 0x36}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8032, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, .bank_size = 2, .banks = 2, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5502", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC10", 0x36}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8033, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 24576, .offset = 0x0a000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, .bank_size = 2, .banks = 2, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5503", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC10", 0x36}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8034, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, .bank_size = 2, .banks = 2, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5504", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {0}, {"ADC10", 0x36}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8035, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, .bank_size = 2, .banks = 2, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5505", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {0}, {"ADC10", 0x36}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8036, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, .bank_size = 2, .banks = 2, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5506", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {0}, {"ADC10", 0x36}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8037, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 24576, .offset = 0x0a000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, .bank_size = 2, .banks = 2, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5507", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {0}, {"ADC10", 0x36}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8038, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, .bank_size = 2, .banks = 2, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5508", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC10", 0x36}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8039, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, .bank_size = 2, .banks = 2, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5509", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC10", 0x36}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x803a, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 24576, .offset = 0x0a000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, .bank_size = 2, .banks = 2, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5500", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC10", 0x36}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x803b, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, .bank_size = 65536, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, .bank_size = 2, .banks = 2, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5630", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {0}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x803c, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5631", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {0}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x803e, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 196608, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 3, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5632", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {0}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8040, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5633", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8042, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5634", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8044, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 196608, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 3, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6630", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {"LCDB", 0x2c}, {0}, {"Comparator B", 0x2a}, {0}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8046, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6631", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {"LCDB", 0x2c}, {0}, {"Comparator B", 0x2a}, {0}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8048, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 196608, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 3, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6632", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {"LCDB", 0x2c}, {0}, {"Comparator B", 0x2a}, {0}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x804a, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6633", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {"LCDB", 0x2c}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x804c, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6634", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {"LCDB", 0x2c}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x804e, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 196608, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 3, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6720", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {0}, {0}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {0}, {0}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8058, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, .bank_size = 32768, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6721", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {0}, {0}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {0}, {0}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8059, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 32768, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6722", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {0}, {0}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {0}, {0}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8060, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 49152, .offset = 0x04000, .seg_size = 512, .bank_size = 32768, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6723", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {0}, {0}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {0}, {0}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8061, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 65536, .offset = 0x04000, .seg_size = 512, .bank_size = 32768, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6730", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {0}, {0}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {0}, {0}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8062, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, .bank_size = 32768, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6731", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {0}, {0}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {0}, {0}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8063, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 32768, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6732", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {0}, {0}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {0}, {0}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8064, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 49152, .offset = 0x04000, .seg_size = 512, .bank_size = 32768, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6733", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {0}, {0}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {0}, {0}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8065, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 65536, .offset = 0x04000, .seg_size = 512, .bank_size = 32768, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5721", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {"Comparator D", 0x2b}, {"ADC10B", 0x37}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B3", 0x16}, {"Timer1_B3", 0x17}, {"Timer2_B3", 0x18}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8077, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10010, .disable_lpm5 = 0x00018, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x0f000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5725", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {"Comparator D", 0x2b}, {"ADC10B", 0x37}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B3", 0x16}, {"Timer1_B3", 0x17}, {"Timer2_B3", 0x18}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8078, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10010, .disable_lpm5 = 0x00018, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5727", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {"Comparator D", 0x2b}, {0}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B3", 0x16}, {"Timer1_B3", 0x17}, {"Timer2_B3", 0x18}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8079, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10010, .disable_lpm5 = 0x00018, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 15872, .offset = 0x0c200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5728", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {"Comparator D", 0x2b}, {"ADC10B", 0x37}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {0}, {"eUSCIA0", 0x23}, {"Timer0_B3", 0x16}, {0}, {0}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x807a, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10010, .disable_lpm5 = 0x00018, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 15872, .offset = 0x0c200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5729", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {"Comparator D", 0x2b}, {"ADC10B", 0x37}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B3", 0x16}, {"Timer1_B3", 0x17}, {"Timer2_B3", 0x18}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x807b, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10010, .disable_lpm5 = 0x00018, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 15872, .offset = 0x0c200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5730", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {"Comparator D", 0x2b}, {"ADC10B", 0x37}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {0}, {"eUSCIA0", 0x23}, {"Timer0_B3", 0x16}, {0}, {0}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x807c, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10010, .disable_lpm5 = 0x00018, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x0f000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5731", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {"Comparator D", 0x2b}, {"ADC10B", 0x37}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B3", 0x16}, {"Timer1_B3", 0x17}, {"Timer2_B3", 0x18}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x807e, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10010, .disable_lpm5 = 0x00018, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x0f000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5733", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {"Comparator D", 0x2b}, {0}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B3", 0x16}, {"Timer1_B3", 0x17}, {"Timer2_B3", 0x18}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x807f, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10010, .disable_lpm5 = 0x00018, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5734", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {"Comparator D", 0x2b}, {"ADC10B", 0x37}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {0}, {"eUSCIA0", 0x23}, {"Timer0_B3", 0x16}, {0}, {0}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8100, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10010, .disable_lpm5 = 0x00018, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5737", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {"Comparator D", 0x2b}, {0}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B3", 0x16}, {"Timer1_B3", 0x17}, {"Timer2_B3", 0x18}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8101, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10010, .disable_lpm5 = 0x00018, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 15872, .offset = 0x0c200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5738", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {"Comparator D", 0x2b}, {"ADC10B", 0x37}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {0}, {"eUSCIA0", 0x23}, {"Timer0_B3", 0x16}, {0}, {0}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8102, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10010, .disable_lpm5 = 0x00018, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 15872, .offset = 0x0c200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5739", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {"Comparator D", 0x2b}, {"ADC10B", 0x37}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B3", 0x16}, {"Timer1_B3", 0x17}, {"Timer2_B3", 0x18}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8103, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10010, .disable_lpm5 = 0x00018, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 15872, .offset = 0x0c200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5304", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {0}, {"ADC10", 0x36}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8112, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, .bank_size = 32768, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5308", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC10", 0x36}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8113, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, .bank_size = 32768, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5309", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC10", 0x36}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8114, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 24576, .offset = 0x0a000, .seg_size = 512, .bank_size = 32768, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5310", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC10", 0x36}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8115, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 32768, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5324", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8116, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 65536, .offset = 0x04400, .seg_size = 512, .bank_size = 32768, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5325", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8117, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 65536, .offset = 0x04400, .seg_size = 512, .bank_size = 32768, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5326", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8118, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 98304, .offset = 0x04400, .seg_size = 512, .bank_size = 32768, .banks = 3, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 6144, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5327", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8119, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 98304, .offset = 0x04400, .seg_size = 512, .bank_size = 32768, .banks = 3, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 6144, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5328", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x811a, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04400, .seg_size = 512, .bank_size = 32768, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5329", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x811b, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04400, .seg_size = 512, .bank_size = 32768, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5340", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x811c, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 65536, .offset = 0x04400, .seg_size = 512, .bank_size = 32768, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5341", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x811d, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 98304, .offset = 0x04400, .seg_size = 512, .bank_size = 32768, .banks = 3, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 6144, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5342", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x811e, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04400, .seg_size = 512, .bank_size = 32768, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6433", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {"LCDB", 0x2c}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x811f, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6435", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {"LCDB", 0x2c}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8121, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6436", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {"LCDB", 0x2c}, {"DAC12", 0x32}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8122, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6438", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {"LCDB", 0x2c}, {"DAC12", 0x32}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8124, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5333", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8125, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5335", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8127, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5336", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {"DAC12", 0x32}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8128, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5338", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {"DAC12", 0x32}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x812a, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6659", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {"LCDB", 0x2c}, {"DAC12", 0x32}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x812b, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 524288, .offset = 0x08000, .seg_size = 512, .bank_size = 131072, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 65536, .offset = 0xf0000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6658", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {"LCDB", 0x2c}, {"DAC12", 0x32}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x812c, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 393216, .offset = 0x08000, .seg_size = 512, .bank_size = 131072, .banks = 3, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0xf8000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6459", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {"LCDB", 0x2c}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x812d, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 524288, .offset = 0x08000, .seg_size = 512, .bank_size = 131072, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 65536, .offset = 0xf0000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6458", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {"LCDB", 0x2c}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x812e, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 393216, .offset = 0x08000, .seg_size = 512, .bank_size = 131072, .banks = 3, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0xf8000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5659", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {"DAC12", 0x32}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8130, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 524288, .offset = 0x08000, .seg_size = 512, .bank_size = 131072, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 65536, .offset = 0xf0000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5658", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {"DAC12", 0x32}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"USB", 0x03}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8131, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 393216, .offset = 0x08000, .seg_size = 512, .bank_size = 131072, .banks = 3, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0xf8000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5359", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {"DAC12", 0x32}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8132, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 524288, .offset = 0x08000, .seg_size = 512, .bank_size = 131072, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 65536, .offset = 0xf0000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5358", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {"DAC12", 0x32}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {0}, {0}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8133, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 393216, .offset = 0x08000, .seg_size = 512, .bank_size = 131072, .banks = 3, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "usbram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0xf8000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "CC430F6147", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {0}, {"AES128", 0x04}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"LCDB", 0x2c}, {0}, {0}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8135, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 3968, .offset = 0x01c80, .seg_size = 1, .bank_size = 0, .banks = 2, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "CC430F6145", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {0}, {"AES128", 0x04}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"LCDB", 0x2c}, {0}, {0}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8136, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, .bank_size = 65536, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1920, .offset = 0x01c80, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "CC430F6143", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {0}, {"AES128", 0x04}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {"LCDB", 0x2c}, {0}, {0}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8137, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, .bank_size = 65536, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1920, .offset = 0x01c80, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "CC430F5147", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {0}, {"AES128", 0x04}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8138, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, .bank_size = 65536, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 3968, .offset = 0x01c80, .seg_size = 1, .bank_size = 0, .banks = 2, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "CC430F5145", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {0}, {"AES128", 0x04}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8139, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, .bank_size = 65536, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1920, .offset = 0x01c80, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "CC430F5143", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {0}, {"AES128", 0x04}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x813a, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, .bank_size = 65536, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1920, .offset = 0x01c80, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "CC430F5125", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {0}, {"AES128", 0x04}, {"Comparator B", 0x2a}, {0}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x813b, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, .bank_size = 65536, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1920, .offset = 0x01c80, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "CC430F5123", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {0}, {"AES128", 0x04}, {"Comparator B", 0x2a}, {0}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {0}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x813c, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, .bank_size = 65536, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1920, .offset = 0x01c80, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5212", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {0}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8140, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 65536, .offset = 0x04400, .seg_size = 512, .bank_size = 32768, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5213", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {0}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8141, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 98304, .offset = 0x04400, .seg_size = 512, .bank_size = 32768, .banks = 3, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5214", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {0}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8142, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04400, .seg_size = 512, .bank_size = 32768, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5217", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {0}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8145, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 65536, .offset = 0x04400, .seg_size = 512, .bank_size = 32768, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5218", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {0}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8146, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 98304, .offset = 0x04400, .seg_size = 512, .bank_size = 32768, .banks = 3, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5219", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {0}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8147, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04400, .seg_size = 512, .bank_size = 32768, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5222", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x814a, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 65536, .offset = 0x04400, .seg_size = 512, .bank_size = 32768, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5223", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x814b, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 98304, .offset = 0x04400, .seg_size = 512, .bank_size = 32768, .banks = 3, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5224", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x814c, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04400, .seg_size = 512, .bank_size = 32768, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5227", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x814f, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 65536, .offset = 0x04400, .seg_size = 512, .bank_size = 32768, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5228", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8150, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 98304, .offset = 0x04400, .seg_size = 512, .bank_size = 32768, .banks = 3, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5229", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8151, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04400, .seg_size = 512, .bank_size = 32768, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5949", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0xbdff, .clock_map = { {"Timer1_A2", 0x06}, {0}, {"AES128", 0x04}, {"Comparator D", 0x2b}, {"ADC12B", 0x38}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B7", 0x1c}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Timer2_A3", 0x0a}, {"Timer0_A2", 0x05}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8161, .ver_sub_id = 0x0000, .revision = 0x12, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0xff, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x0a] = 0x0a, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10018, .disable_lpm5 = 0x10000, .reg_mask_3v = 0x0c020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 64512, .offset = 0x04400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5949", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0xbdff, .clock_map = { {"Timer1_A2", 0x06}, {0}, {"AES128", 0x04}, {"Comparator D", 0x2b}, {"ADC12B", 0x38}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B7", 0x1c}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Timer2_A3", 0x0a}, {"Timer0_A2", 0x05}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8161, .ver_sub_id = 0x0000, .revision = 0x20, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0xff, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x0a] = 0x49, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x4f, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10018, .disable_lpm5 = 0x10000, .reg_mask_3v = 0x0c020, .enable_lpm5_3v = 0x0c020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 64512, .offset = 0x04400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5949", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0xbdff, .clock_map = { {"Timer1_A2", 0x06}, {0}, {"AES128", 0x04}, {"Comparator D", 0x2b}, {"ADC12B", 0x38}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B7", 0x1c}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Timer2_A3", 0x0a}, {"Timer0_A2", 0x05}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8161, .ver_sub_id = 0x0000, .revision = 0x21, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0xff, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x0a] = 0x49, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x4f, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10018, .disable_lpm5 = 0x10000, .reg_mask_3v = 0x0c020, .enable_lpm5_3v = 0x0c020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 64512, .offset = 0x04400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5969", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0xbdff, .clock_map = { {"Timer1_A2", 0x06}, {0}, {"AES128", 0x04}, {"Comparator D", 0x2b}, {"ADC12B", 0x38}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B7", 0x1c}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Timer2_A3", 0x0a}, {"Timer0_A2", 0x05}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8169, .ver_sub_id = 0x0000, .revision = 0x12, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0xff, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x0a] = 0x0a, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10018, .disable_lpm5 = 0x10000, .reg_mask_3v = 0x0c020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 64512, .offset = 0x04400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5969", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0xbdff, .clock_map = { {"Timer1_A2", 0x06}, {0}, {"AES128", 0x04}, {"Comparator D", 0x2b}, {"ADC12B", 0x38}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B7", 0x1c}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Timer2_A3", 0x0a}, {"Timer0_A2", 0x05}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8169, .ver_sub_id = 0x0000, .revision = 0x20, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0xff, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x0a] = 0x49, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x4f, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10018, .disable_lpm5 = 0x10000, .reg_mask_3v = 0x0c020, .enable_lpm5_3v = 0x0c020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 64512, .offset = 0x04400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5969", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0xbdff, .clock_map = { {"Timer1_A2", 0x06}, {0}, {"AES128", 0x04}, {"Comparator D", 0x2b}, {"ADC12B", 0x38}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B7", 0x1c}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Timer2_A3", 0x0a}, {"Timer0_A2", 0x05}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8169, .ver_sub_id = 0x0000, .revision = 0x21, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0xff, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x0a] = 0x49, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x4f, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10018, .disable_lpm5 = 0x10000, .reg_mask_3v = 0x0c020, .enable_lpm5_3v = 0x0c020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 64512, .offset = 0x04400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6734", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {0}, {0}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {0}, {0}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x816a, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 98304, .offset = 0x04000, .seg_size = 512, .bank_size = 32768, .banks = 3, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6735", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {0}, {0}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {0}, {0}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x816b, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04000, .seg_size = 512, .bank_size = 32768, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6736", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {0}, {0}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {0}, {0}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x816c, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04000, .seg_size = 512, .bank_size = 32768, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6724", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {0}, {0}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {0}, {0}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x816d, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 98304, .offset = 0x04000, .seg_size = 512, .bank_size = 32768, .banks = 3, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6725", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {0}, {0}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {0}, {0}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x816e, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04000, .seg_size = 512, .bank_size = 32768, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6726", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {0}, {0}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {0}, {0}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x816f, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04000, .seg_size = 512, .bank_size = 32768, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5720", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {"Comparator D", 0x2b}, {"ADC10B", 0x37}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {0}, {"eUSCIA0", 0x23}, {"Timer0_B3", 0x16}, {0}, {0}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8170, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10010, .disable_lpm5 = 0x00018, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x0f000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5722", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {"Comparator D", 0x2b}, {0}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {0}, {"eUSCIA0", 0x23}, {"Timer0_B3", 0x16}, {0}, {0}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8171, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10010, .disable_lpm5 = 0x00018, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5723", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {"Comparator D", 0x2b}, {0}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B3", 0x16}, {"Timer1_B3", 0x17}, {"Timer2_B3", 0x18}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8172, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10010, .disable_lpm5 = 0x00018, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5724", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {"Comparator D", 0x2b}, {"ADC10B", 0x37}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {0}, {"eUSCIA0", 0x23}, {"Timer0_B3", 0x16}, {0}, {0}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8173, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10010, .disable_lpm5 = 0x00018, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5726", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {"Comparator D", 0x2b}, {0}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {0}, {"eUSCIA0", 0x23}, {"Timer0_B3", 0x16}, {0}, {0}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8174, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10010, .disable_lpm5 = 0x00018, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 15872, .offset = 0x0c200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5732", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {"Comparator D", 0x2b}, {0}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {0}, {"eUSCIA0", 0x23}, {"Timer0_B3", 0x16}, {0}, {0}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8175, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10010, .disable_lpm5 = 0x00018, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5735", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {"Comparator D", 0x2b}, {"ADC10B", 0x37}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B3", 0x16}, {"Timer1_B3", 0x17}, {"Timer2_B3", 0x18}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8176, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10010, .disable_lpm5 = 0x00018, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5736", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {"Comparator D", 0x2b}, {0}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {0}, {"eUSCIA0", 0x23}, {"Timer0_B3", 0x16}, {0}, {0}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8177, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x01, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10010, .disable_lpm5 = 0x00018, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 15872, .offset = 0x0c200, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6745", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {"AES128", 0x04}, {"eUSCIA3", 0x26}, {"eUSCIA2", 0x25}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"eUSCIB1", 0x3b}, {"Comparator B", 0x2a}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8188, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x0c000, .seg_size = 512, .bank_size = 131072, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6746", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {"AES128", 0x04}, {"eUSCIA3", 0x26}, {"eUSCIA2", 0x25}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"eUSCIB1", 0x3b}, {"Comparator B", 0x2a}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8189, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x0c000, .seg_size = 512, .bank_size = 131072, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6747", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {"AES128", 0x04}, {"eUSCIA3", 0x26}, {"eUSCIA2", 0x25}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"eUSCIB1", 0x3b}, {"Comparator B", 0x2a}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x818a, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x0c000, .seg_size = 512, .bank_size = 131072, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6748", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {"AES128", 0x04}, {"eUSCIA3", 0x26}, {"eUSCIA2", 0x25}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"eUSCIB1", 0x3b}, {"Comparator B", 0x2a}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x818b, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 524288, .offset = 0x0c000, .seg_size = 512, .bank_size = 131072, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6749", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {"AES128", 0x04}, {"eUSCIA3", 0x26}, {"eUSCIA2", 0x25}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"eUSCIB1", 0x3b}, {"Comparator B", 0x2a}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x818c, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 524288, .offset = 0x0c000, .seg_size = 512, .bank_size = 131072, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6765", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {"AES128", 0x04}, {"eUSCIA3", 0x26}, {"eUSCIA2", 0x25}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"eUSCIB1", 0x3b}, {"Comparator B", 0x2a}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x818d, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x0c000, .seg_size = 512, .bank_size = 131072, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6766", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {"AES128", 0x04}, {"eUSCIA3", 0x26}, {"eUSCIA2", 0x25}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"eUSCIB1", 0x3b}, {"Comparator B", 0x2a}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x818e, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x0c000, .seg_size = 512, .bank_size = 131072, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6767", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {"AES128", 0x04}, {"eUSCIA3", 0x26}, {"eUSCIA2", 0x25}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"eUSCIB1", 0x3b}, {"Comparator B", 0x2a}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x818f, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x0c000, .seg_size = 512, .bank_size = 131072, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6768", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {"AES128", 0x04}, {"eUSCIA3", 0x26}, {"eUSCIA2", 0x25}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"eUSCIB1", 0x3b}, {"Comparator B", 0x2a}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8190, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 524288, .offset = 0x0c000, .seg_size = 512, .bank_size = 131072, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6769", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {"AES128", 0x04}, {"eUSCIA3", 0x26}, {"eUSCIA2", 0x25}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"eUSCIB1", 0x3b}, {"Comparator B", 0x2a}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8191, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 524288, .offset = 0x0c000, .seg_size = 512, .bank_size = 131072, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6775", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {"AES128", 0x04}, {"eUSCIA3", 0x26}, {"eUSCIA2", 0x25}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"eUSCIB1", 0x3b}, {"Comparator B", 0x2a}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8192, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x0c000, .seg_size = 512, .bank_size = 131072, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6776", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {"AES128", 0x04}, {"eUSCIA3", 0x26}, {"eUSCIA2", 0x25}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"eUSCIB1", 0x3b}, {"Comparator B", 0x2a}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8193, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x0c000, .seg_size = 512, .bank_size = 131072, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6777", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {"AES128", 0x04}, {"eUSCIA3", 0x26}, {"eUSCIA2", 0x25}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"eUSCIB1", 0x3b}, {"Comparator B", 0x2a}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8194, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x0c000, .seg_size = 512, .bank_size = 131072, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6778", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {"AES128", 0x04}, {"eUSCIA3", 0x26}, {"eUSCIA2", 0x25}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"eUSCIB1", 0x3b}, {"Comparator B", 0x2a}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8195, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 524288, .offset = 0x0c000, .seg_size = 512, .bank_size = 131072, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F6779", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {"AES128", 0x04}, {"eUSCIA3", 0x26}, {"eUSCIA2", 0x25}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"eUSCIB1", 0x3b}, {"Comparator B", 0x2a}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8196, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 524288, .offset = 0x0c000, .seg_size = 512, .bank_size = 131072, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F67451", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {"eUSCIA3", 0x26}, {"eUSCIA2", 0x25}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"eUSCIB1", 0x3b}, {"Comparator B", 0x2a}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8197, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x0c000, .seg_size = 512, .bank_size = 131072, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F67461", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {"eUSCIA3", 0x26}, {"eUSCIA2", 0x25}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"eUSCIB1", 0x3b}, {"Comparator B", 0x2a}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8198, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x0c000, .seg_size = 512, .bank_size = 131072, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F67471", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {"eUSCIA3", 0x26}, {"eUSCIA2", 0x25}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"eUSCIB1", 0x3b}, {"Comparator B", 0x2a}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8199, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x0c000, .seg_size = 512, .bank_size = 131072, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F67481", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {"eUSCIA3", 0x26}, {"eUSCIA2", 0x25}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"eUSCIB1", 0x3b}, {"Comparator B", 0x2a}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x819a, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 524288, .offset = 0x0c000, .seg_size = 512, .bank_size = 131072, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F67491", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {"eUSCIA3", 0x26}, {"eUSCIA2", 0x25}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"eUSCIB1", 0x3b}, {"Comparator B", 0x2a}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x819b, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 524288, .offset = 0x0c000, .seg_size = 512, .bank_size = 131072, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F67651", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {"eUSCIA3", 0x26}, {"eUSCIA2", 0x25}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"eUSCIB1", 0x3b}, {"Comparator B", 0x2a}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x819c, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x0c000, .seg_size = 512, .bank_size = 131072, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F67661", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {"eUSCIA3", 0x26}, {"eUSCIA2", 0x25}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"eUSCIB1", 0x3b}, {"Comparator B", 0x2a}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x819d, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x0c000, .seg_size = 512, .bank_size = 131072, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F67671", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {"eUSCIA3", 0x26}, {"eUSCIA2", 0x25}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"eUSCIB1", 0x3b}, {"Comparator B", 0x2a}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x819e, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x0c000, .seg_size = 512, .bank_size = 131072, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F67681", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {"eUSCIA3", 0x26}, {"eUSCIA2", 0x25}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"eUSCIB1", 0x3b}, {"Comparator B", 0x2a}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x819f, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 524288, .offset = 0x0c000, .seg_size = 512, .bank_size = 131072, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F67691", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {"eUSCIA3", 0x26}, {"eUSCIA2", 0x25}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"eUSCIB1", 0x3b}, {"Comparator B", 0x2a}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81a0, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 524288, .offset = 0x0c000, .seg_size = 512, .bank_size = 131072, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F67751", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {"eUSCIA3", 0x26}, {"eUSCIA2", 0x25}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"eUSCIB1", 0x3b}, {"Comparator B", 0x2a}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81a1, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x0c000, .seg_size = 512, .bank_size = 131072, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F67761", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {"eUSCIA3", 0x26}, {"eUSCIA2", 0x25}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"eUSCIB1", 0x3b}, {"Comparator B", 0x2a}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81a2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x0c000, .seg_size = 512, .bank_size = 131072, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F67771", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {"eUSCIA3", 0x26}, {"eUSCIA2", 0x25}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"eUSCIB1", 0x3b}, {"Comparator B", 0x2a}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81a3, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x0c000, .seg_size = 512, .bank_size = 131072, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F67781", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {"eUSCIA3", 0x26}, {"eUSCIA2", 0x25}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"eUSCIB1", 0x3b}, {"Comparator B", 0x2a}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81a4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 524288, .offset = 0x0c000, .seg_size = 512, .bank_size = 131072, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F67791", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x2407, .clock_map = { {0}, {"eUSCIA3", 0x26}, {"eUSCIA2", 0x25}, {"SD24B", 0x35}, {"ADC10", 0x36}, {"RTC", 0x28}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"eUSCIB1", 0x3b}, {"Comparator B", 0x2a}, {"Timer0_A3", 0x08}, {"Timer1_A2", 0x06}, {"Timer2_A2", 0x07}, {"Timer3_A2", 0x0b}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81a5, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x04020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 524288, .offset = 0x0c000, .seg_size = 512, .bank_size = 131072, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR6987", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0xbdff, .clock_map = { {"Timer1_A2", 0x06}, {"LCDB", 0x2c}, {"AES128", 0x04}, {"Comparator D", 0x2b}, {"ADC12B", 0x38}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B7", 0x1c}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Timer2_A3", 0x0a}, {"Timer0_A2", 0x05}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81a6, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10000, .disable_lpm5 = 0x10000, .reg_mask_3v = 0x0c020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 64512, .offset = 0x04400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x03c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR6988", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0xbdff, .clock_map = { {"Timer1_A2", 0x06}, {"LCDB", 0x2c}, {"AES128", 0x04}, {"Comparator D", 0x2b}, {"ADC12B", 0x38}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B7", 0x1c}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Timer2_A3", 0x0a}, {"Timer0_A2", 0x05}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81a7, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10000, .disable_lpm5 = 0x10000, .reg_mask_3v = 0x0c020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 97280, .offset = 0x04400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x03c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR6989", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0xbdff, .clock_map = { {"Timer1_A2", 0x06}, {"LCDB", 0x2c}, {"AES128", 0x04}, {"Comparator D", 0x2b}, {"ADC12B", 0x38}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B7", 0x1c}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Timer2_A3", 0x0a}, {"Timer0_A2", 0x05}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81a8, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10000, .disable_lpm5 = 0x10000, .reg_mask_3v = 0x0c020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 130048, .offset = 0x04400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x03c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5988", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0xbdff, .clock_map = { {"Timer1_A2", 0x06}, {0}, {"AES128", 0x04}, {"Comparator D", 0x2b}, {"ADC12B", 0x38}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B7", 0x1c}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Timer2_A3", 0x0a}, {"Timer0_A2", 0x05}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81aa, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10000, .disable_lpm5 = 0x10000, .reg_mask_3v = 0x0c020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 97280, .offset = 0x04400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x03c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5989", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0xbdff, .clock_map = { {"Timer1_A2", 0x06}, {0}, {"AES128", 0x04}, {"Comparator D", 0x2b}, {"ADC12B", 0x38}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B7", 0x1c}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Timer2_A3", 0x0a}, {"Timer0_A2", 0x05}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81ab, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10000, .disable_lpm5 = 0x10000, .reg_mask_3v = 0x0c020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 130048, .offset = 0x04400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x03c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR6977", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0xbdff, .clock_map = { {"Timer1_A2", 0x06}, {"LCDB", 0x2c}, {"AES128", 0x04}, {"Comparator D", 0x2b}, {"ADC12B", 0x38}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B7", 0x1c}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Timer2_A3", 0x0a}, {"Timer0_A2", 0x05}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81ac, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10000, .disable_lpm5 = 0x10000, .reg_mask_3v = 0x0c020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 64512, .offset = 0x04400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x03c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR6978", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0xbdff, .clock_map = { {"Timer1_A2", 0x06}, {"LCDB", 0x2c}, {"AES128", 0x04}, {"Comparator D", 0x2b}, {"ADC12B", 0x38}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B7", 0x1c}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Timer2_A3", 0x0a}, {"Timer0_A2", 0x05}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81ad, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10000, .disable_lpm5 = 0x10000, .reg_mask_3v = 0x0c020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 97280, .offset = 0x04400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x03c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR6979", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0xbdff, .clock_map = { {"Timer1_A2", 0x06}, {"LCDB", 0x2c}, {"AES128", 0x04}, {"Comparator D", 0x2b}, {"ADC12B", 0x38}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B7", 0x1c}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Timer2_A3", 0x0a}, {"Timer0_A2", 0x05}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81ae, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10000, .disable_lpm5 = 0x10000, .reg_mask_3v = 0x0c020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 130048, .offset = 0x04400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x03c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5977", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0xbdff, .clock_map = { {"Timer1_A2", 0x06}, {0}, {"AES128", 0x04}, {"Comparator D", 0x2b}, {"ADC12B", 0x38}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B7", 0x1c}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Timer2_A3", 0x0a}, {"Timer0_A2", 0x05}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81af, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10000, .disable_lpm5 = 0x10000, .reg_mask_3v = 0x0c020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 64512, .offset = 0x04400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x03c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5978", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0xbdff, .clock_map = { {"Timer1_A2", 0x06}, {0}, {"AES128", 0x04}, {"Comparator D", 0x2b}, {"ADC12B", 0x38}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B7", 0x1c}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Timer2_A3", 0x0a}, {"Timer0_A2", 0x05}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81b0, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10000, .disable_lpm5 = 0x10000, .reg_mask_3v = 0x0c020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 97280, .offset = 0x04400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x03c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5979", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0xbdff, .clock_map = { {"Timer1_A2", 0x06}, {0}, {"AES128", 0x04}, {"Comparator D", 0x2b}, {"ADC12B", 0x38}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B7", 0x1c}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Timer2_A3", 0x0a}, {"Timer0_A2", 0x05}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81b1, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10000, .disable_lpm5 = 0x10000, .reg_mask_3v = 0x0c020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 130048, .offset = 0x04400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x03c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR6928", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0xbdff, .clock_map = { {"Timer1_A2", 0x06}, {"LCDB", 0x2c}, {"AES128", 0x04}, {"Comparator D", 0x2b}, {"ADC12B", 0x38}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B7", 0x1c}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Timer2_A3", 0x0a}, {"Timer0_A2", 0x05}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81b3, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10000, .disable_lpm5 = 0x10000, .reg_mask_3v = 0x0c020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 97280, .offset = 0x04400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x03c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR6929", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0xbdff, .clock_map = { {"Timer1_A2", 0x06}, {"LCDB", 0x2c}, {"AES128", 0x04}, {"Comparator D", 0x2b}, {"ADC12B", 0x38}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B7", 0x1c}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Timer2_A3", 0x0a}, {"Timer0_A2", 0x05}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81b4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10000, .disable_lpm5 = 0x10000, .reg_mask_3v = 0x0c020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 130048, .offset = 0x04400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x03c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR6887", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0xbdff, .clock_map = { {"Timer1_A2", 0x06}, {"LCDB", 0x2c}, {0}, {"Comparator D", 0x2b}, {"ADC12B", 0x38}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B7", 0x1c}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Timer2_A3", 0x0a}, {"Timer0_A2", 0x05}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81be, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10000, .disable_lpm5 = 0x10000, .reg_mask_3v = 0x0c020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 64512, .offset = 0x04400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x03c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR6888", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0xbdff, .clock_map = { {"Timer1_A2", 0x06}, {"LCDB", 0x2c}, {0}, {"Comparator D", 0x2b}, {"ADC12B", 0x38}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B7", 0x1c}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Timer2_A3", 0x0a}, {"Timer0_A2", 0x05}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81bf, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10000, .disable_lpm5 = 0x10000, .reg_mask_3v = 0x0c020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 97280, .offset = 0x04400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x03c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR6889", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0xbdff, .clock_map = { {"Timer1_A2", 0x06}, {"LCDB", 0x2c}, {0}, {"Comparator D", 0x2b}, {"ADC12B", 0x38}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B7", 0x1c}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Timer2_A3", 0x0a}, {"Timer0_A2", 0x05}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81c0, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10000, .disable_lpm5 = 0x10000, .reg_mask_3v = 0x0c020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 130048, .offset = 0x04400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x03c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5888", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0xbdff, .clock_map = { {"Timer1_A2", 0x06}, {0}, {0}, {"Comparator D", 0x2b}, {"ADC12B", 0x38}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B7", 0x1c}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Timer2_A3", 0x0a}, {"Timer0_A2", 0x05}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81c2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10000, .disable_lpm5 = 0x10000, .reg_mask_3v = 0x0c020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 97280, .offset = 0x04400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x03c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5889", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0xbdff, .clock_map = { {"Timer1_A2", 0x06}, {0}, {0}, {"Comparator D", 0x2b}, {"ADC12B", 0x38}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B7", 0x1c}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Timer2_A3", 0x0a}, {"Timer0_A2", 0x05}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81c3, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10000, .disable_lpm5 = 0x10000, .reg_mask_3v = 0x0c020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 130048, .offset = 0x04400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x03c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5878", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0xbdff, .clock_map = { {"Timer1_A2", 0x06}, {0}, {0}, {"Comparator D", 0x2b}, {"ADC12B", 0x38}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B7", 0x1c}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Timer2_A3", 0x0a}, {"Timer0_A2", 0x05}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81c8, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10000, .disable_lpm5 = 0x10000, .reg_mask_3v = 0x0c020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 97280, .offset = 0x04400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x03c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430FR5879", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0xbdff, .clock_map = { {"Timer1_A2", 0x06}, {0}, {0}, {"Comparator D", 0x2b}, {"ADC12B", 0x38}, {"RTC", 0x28}, {0}, {"eUSCIB0", 0x27}, {"eUSCIA1", 0x24}, {"eUSCIA0", 0x23}, {"Timer0_B7", 0x1c}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Timer2_A3", 0x0a}, {"Timer0_A2", 0x05}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81c9, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x38, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, .enable_lpm5 = 0x10000, .disable_lpm5 = 0x10000, .reg_mask_3v = 0x0c020, .enable_lpm5_3v = 0x04020, .disable_lpm5_3v = 0x04020, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 130048, .offset = 0x04400, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "information", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x03c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430SL5438A", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x040f, .clock_map = { {0}, {0}, {0}, {0}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {0}, {"Timer0_B7", 0x1c}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81ee, .ver_sub_id = 0x0001, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x08, .cycle_counter = 0x02, .cycle_counter_ops = 0x01, .trig_emulation_level = 0x07, .trig_mem = 0x08, .trig_reg = 0x02, .trig_combinations = 0x0a, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x02, .trig_mem_umask_level = 0x01, .seq_states = 0x03, .seq_start = 0x04, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x05c00, .seg_size = 512, .bank_size = 65536, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5249", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81f3, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04400, .seg_size = 512, .bank_size = 32768, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5247", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81f4, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 65536, .offset = 0x04400, .seg_size = 512, .bank_size = 32768, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5244", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81f5, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04400, .seg_size = 512, .bank_size = 32768, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5242", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81f6, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 65536, .offset = 0x04400, .seg_size = 512, .bank_size = 32768, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5239", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {0}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81f7, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04400, .seg_size = 512, .bank_size = 32768, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5237", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {0}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81f8, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 65536, .offset = 0x04400, .seg_size = 512, .bank_size = 32768, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5234", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {0}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81f9, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04400, .seg_size = 512, .bank_size = 32768, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5232", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {0}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81fa, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 65536, .offset = 0x04400, .seg_size = 512, .bank_size = 32768, .banks = 2, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5259", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x81ff, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x0a400, .seg_size = 512, .bank_size = 32768, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5258", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {0}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8200, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x0a400, .seg_size = 512, .bank_size = 32768, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5257", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8201, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x0a400, .seg_size = 512, .bank_size = 32768, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5256", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {0}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8202, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x0a400, .seg_size = 512, .bank_size = 32768, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5255", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8203, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x0a400, .seg_size = 512, .bank_size = 32768, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5254", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {0}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8204, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x0a400, .seg_size = 512, .bank_size = 32768, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5253", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {"ADC12A", 0x38}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8205, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x0a400, .seg_size = 512, .bank_size = 32768, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430F5252", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, .mclk_control = 0x041f, .clock_map = { {0}, {0}, {0}, {"Comparator B", 0x2a}, {0}, {"RTC", 0x28}, {"USCI3", 0x22}, {"USCI2", 0x21}, {"USCI1", 0x20}, {"USCI0", 0x1f}, {0}, {"Timer0_B7", 0x1c}, {"Timer2_A3", 0x3a}, {"Timer1_A3", 0x39}, {"Timer0_A5", 0x0c}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0x8206, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x05, .trig_mem = 0x03, .trig_reg = 0x01, .trig_combinations = 0x04, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x01, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, .vcc_flash_min = 1800, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, .has_test_vpp = 1, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_1337, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x0a400, .seg_size = 512, .bank_size = 32768, .banks = 4, }, { .name = "information", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 512, .offset = 0x01800, .seg_size = 128, .bank_size = 128, .banks = 4, }, { .name = "boot", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01000, .seg_size = 512, .bank_size = 0, .banks = 4, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, .bank_size = 0, .banks = 4, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430L092", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x0417, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {"CCS", 0x02}, {"APOOL", 0x2d}, {0}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0xc092, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x5aa55aa5, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0xffffffff, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x04, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x00, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 900, .vcc_max = 1800, .vcc_flash_min = 0, .vcc_secure_min = 0, .vpp_secure_min = 0, .vpp_secure_max = 0, .has_test_vpp = 0, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1888, .offset = 0x0f880, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x02380, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x0f800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "VectorTable", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32, .offset = 0x0ffe0, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430L092", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x0417, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {"CCS", 0x02}, {"APOOL", 0x2d}, {0}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0xc092, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0xa55aa55a, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0xffffffff, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x04, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x00, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 900, .vcc_max = 1800, .vcc_flash_min = 0, .vcc_secure_min = 0, .vpp_secure_min = 0, .vpp_secure_max = 0, .has_test_vpp = 0, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1920, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x02380, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2016, .offset = 0x0f800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "VectorTable", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32, .offset = 0x0ffe0, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, { .name = "MSP430C092", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, .mclk_control = 0x0417, .clock_map = { {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {"CCS", 0x02}, {"APOOL", 0x2d}, {0}, {"Timer0_A3", 0x08}, {"Timer1_A3", 0x09}, {"Watchdog Timer", 0x01}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, }, .id = { .ver_id = 0xc092, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0xdeadbabe, }, .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0xffffffff, }, .eem = { .state_storage = 0x00, .cycle_counter = 0x01, .cycle_counter_ops = 0x00, .trig_emulation_level = 0x04, .trig_mem = 0x02, .trig_reg = 0x00, .trig_combinations = 0x02, .trig_options = 0x01, .trig_dma = 0x01, .trig_read_write = 0x01, .trig_reg_ops = 0x00, .trig_comp_level = 0x02, .trig_mem_cond_level = 0x00, .trig_mem_umask_level = 0x00, .seq_states = 0x00, .seq_start = 0x00, .seq_end = 0x00, .seq_reset = 0x00, .seq_blocked = 0x00, }, .voltage = { .vcc_min = 900, .vcc_max = 1800, .vcc_flash_min = 0, .vcc_secure_min = 0, .vpp_secure_min = 0, .vpp_secure_max = 0, .has_test_vpp = 0, }, .v3_functions = { [0x09] = 0x37, [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, [0x15] = 0x3c, [0x16] = 0x3d, [0x17] = 0x3e, [0x18] = 0x3e, [0x19] = 0x3f, [0x1b] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, [0x25] = 0x36, [0x49] = 0x4a, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, .reg_mask_3v = 0x00000, .enable_lpm5_3v = 0x00000, .disable_lpm5_3v = 0x00000, }, .memory = { { .name = "main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 96, .offset = 0x01c00, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "system", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x02380, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "bootcode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 2016, .offset = 0x0f800, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "CPU", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 16, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "EEM", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, .bank_size = 0, .banks = 1, }, { .name = "VectorTable", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 32, .offset = 0x0ffe0, .seg_size = 1, .bank_size = 0, .banks = 1, }, {0} }, }, {0} }; mspdebug-0.25/drivers/000077500000000000000000000000001313531517500147305ustar00rootroot00000000000000mspdebug-0.25/drivers/bsl.c000066400000000000000000000207701313531517500156620ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include #include #include #include "fet_proto.h" #include "bsl.h" #include "util.h" #include "output.h" #include "transport.h" #include "comport.h" #include "ti3410.h" struct bsl_device { struct device base; transport_t serial; uint8_t reply_buf[256]; int reply_len; }; #define DATA_HDR 0x80 #define DATA_ACK 0x90 #define DATA_NAK 0xA0 static int bsl_ack(struct bsl_device *dev) { uint8_t reply; if (dev->serial->ops->recv(dev->serial, &reply, 1) < 0) { printc_err("bsl: failed to receive reply\n"); return -1; } if (reply == DATA_NAK) { printc_err("bsl: received NAK\n"); return -1; } if (reply != DATA_ACK) { printc_err("bsl: bad ack character: %x\n", reply); return -1; } return 0; } static int bsl_sync(struct bsl_device *dev) { static const uint8_t c = DATA_HDR; int tries = 2; if (dev->serial->ops->flush(dev->serial) < 0) { pr_error("bsl: tcflush"); return -1; } while (tries--) if (!(dev->serial->ops->send(dev->serial, &c, 1) || bsl_ack(dev))) return 0; printc_err("bsl: sync failed\n"); return -1; } static int send_command(struct bsl_device *dev, int code, uint16_t addr, const uint8_t *data, int len) { uint8_t pktbuf[256]; uint8_t cklow = 0xff; uint8_t ckhigh = 0xff; int pktlen = data ? len + 4 : 4; int i; if (pktlen + 6 > sizeof(pktbuf)) { printc_err("bsl: payload too large: %d\n", len); return -1; } pktbuf[0] = DATA_HDR; pktbuf[1] = code; pktbuf[2] = pktlen; pktbuf[3] = pktlen; pktbuf[4] = addr & 0xff; pktbuf[5] = addr >> 8; pktbuf[6] = len & 0xff; pktbuf[7] = len >> 8; if (data) memcpy(pktbuf + 8, data, len); for (i = 0; i < pktlen + 4; i += 2) cklow ^= pktbuf[i]; for (i = 1; i < pktlen + 4; i += 2) ckhigh ^= pktbuf[i]; pktbuf[pktlen + 4] = cklow; pktbuf[pktlen + 5] = ckhigh; return dev->serial->ops->send(dev->serial, pktbuf, pktlen + 6); } static int verify_checksum(struct bsl_device *dev) { uint8_t cklow = 0xff; uint8_t ckhigh = 0xff; int i; for (i = 0; i < dev->reply_len; i += 2) cklow ^= dev->reply_buf[i]; for (i = 1; i < dev->reply_len; i += 2) ckhigh ^= dev->reply_buf[i]; if (cklow || ckhigh) { printc_err("bsl: checksum invalid (%02x %02x)\n", cklow, ckhigh); return -1; } return 0; } static int fetch_reply(struct bsl_device *dev) { dev->reply_len = 0; for (;;) { int r = dev->serial->ops->recv(dev->serial, dev->reply_buf + dev->reply_len, sizeof(dev->reply_buf) - dev->reply_len); if (r < 0) return -1; dev->reply_len += r; if (dev->reply_buf[0] == DATA_ACK) { return 0; } else if (dev->reply_buf[0] == DATA_HDR) { if (dev->reply_len >= 6 && dev->reply_len == dev->reply_buf[2] + 6) return verify_checksum(dev); } else if (dev->reply_buf[0] == DATA_NAK) { printc_err("bsl: received NAK\n"); return -1; } else { printc_err("bsl: unknown reply type: %02x\n", dev->reply_buf[0]); return -1; } if (dev->reply_len >= sizeof(dev->reply_buf)) { printc_err("bsl: reply buffer overflow\n"); return -1; } } } static int bsl_xfer(struct bsl_device *dev, int command_code, uint16_t addr, const uint8_t *txdata, int len) { if (bsl_sync(dev) < 0 || send_command(dev, command_code, addr, txdata, len) < 0 || fetch_reply(dev) < 0) { printc_err("bsl: failed on command 0x%02x " "(addr = 0x%04x, len = 0x%04x)\n", command_code, addr, len); return -1; } return 0; } #define CMD_TX_DATA 0x38 #define CMD_ERASE 0x39 #define CMD_RX_DATA 0x3a #define CMD_RESET 0x3b static void bsl_destroy(device_t dev_base) { struct bsl_device *dev = (struct bsl_device *)dev_base; bsl_xfer(dev, CMD_RESET, 0, NULL, 0); dev->serial->ops->destroy(dev->serial); free(dev); } static int bsl_ctl(device_t dev_base, device_ctl_t type) { (void)dev_base; switch (type) { case DEVICE_CTL_HALT: /* Ignore halt requests */ return 0; case DEVICE_CTL_RESET: /* Ignore reset requests */ return 0; default: printc_err("bsl: CPU control is not possible\n"); } return -1; } static device_status_t bsl_poll(device_t dev_base) { (void)dev_base; return DEVICE_STATUS_HALTED; } static int bsl_getregs(device_t dev_base, address_t *regs) { (void)dev_base; (void)regs; printc_err("bsl: register fetch is not implemented\n"); return -1; } static int bsl_setregs(device_t dev_base, const address_t *regs) { (void)dev_base; (void)regs; printc_err("bsl: register store is not implemented\n"); return -1; } static int bsl_writemem(device_t dev_base, address_t addr, const uint8_t *mem, address_t len) { struct bsl_device *dev = (struct bsl_device *)dev_base; if (addr >= 0x10000 || len > 0x10000 || addr + len > 0x10000) { printc_err("bsl: memory write out of range\n"); return -1; } while (len) { int wlen = len > 100 ? 100 : len; int r; r = bsl_xfer(dev, CMD_RX_DATA, addr, mem, wlen); if (r < 0) { printc_err("bsl: failed to write to 0x%04x\n", addr); return -1; } mem += wlen; len -= wlen; addr += wlen; } return 0; } static int bsl_readmem(device_t dev_base, address_t addr, uint8_t *mem, address_t len) { struct bsl_device *dev = (struct bsl_device *)dev_base; if (addr >= 0x10000 || len > 0x10000 || addr + len > 0x10000) { printc_err("bsl: memory read out of range\n"); return -1; } while (len) { address_t count = len; if (count > 128) count = 128; if (bsl_xfer(dev, CMD_TX_DATA, addr, NULL, count) < 0) { printc_err("bsl: failed to read memory\n"); return -1; } if (count > dev->reply_buf[2]) count = dev->reply_buf[2]; memcpy(mem, dev->reply_buf + 4, count); mem += count; len -= count; addr += count; } return 0; } static int bsl_erase(device_t dev_base, device_erase_type_t type, address_t addr) { struct bsl_device *dev = (struct bsl_device *)dev_base; (void)addr; if (type != DEVICE_ERASE_MAIN) { printc_err("bsl: only main erase is supported\n"); return -1; } /* Constants found from viewing gdbproxy's activities */ return bsl_xfer(dev, CMD_ERASE, 0x2500, NULL, 0x0069); } static int enter_via_fet(struct bsl_device *dev) { struct fet_proto proto; fet_proto_init(&proto, dev->serial, 0); if (fet_proto_xfer(&proto, 0x24, NULL, 0, 0) < 0) { printc_err("bsl: failed to enter bootloader\n"); return -1; } return 0; } static device_t bsl_open(const struct device_args *args) { struct bsl_device *dev; dev = malloc(sizeof(*dev)); if (!dev) { pr_error("bsl: can't allocate memory"); return NULL; } memset(dev, 0, sizeof(*dev)); dev->base.type = &device_bsl; if (args->flags & DEVICE_FLAG_TTY) dev->serial = comport_open(args->path, 460800); else dev->serial = ti3410_open(args->path, args->requested_serial); if (!dev->serial) { free(dev); return NULL; } if (enter_via_fet(dev) < 0) printc_err("bsl: warning: FET firmware not responding\n"); delay_ms(500); /* Show chip info */ if (bsl_xfer(dev, CMD_TX_DATA, 0xff0, NULL, 0x10) < 0) { printc_err("bsl: failed to read chip info\n"); goto fail; } if (dev->reply_len < 0x16) { printc_err("bsl: missing chip info\n"); goto fail; } printc_dbg("Device ID: 0x%02x%02x\n", dev->reply_buf[4], dev->reply_buf[5]); printc_dbg("BSL version is %x.%02x\n", dev->reply_buf[14], dev->reply_buf[15]); return (device_t)dev; fail: dev->serial->ops->destroy(dev->serial); free(dev); return NULL; } const struct device_class device_bsl = { .name = "uif-bsl", .help = "TI FET430UIF bootloader.", .open = bsl_open, .destroy = bsl_destroy, .readmem = bsl_readmem, .writemem = bsl_writemem, .erase = bsl_erase, .getregs = bsl_getregs, .setregs = bsl_setregs, .ctl = bsl_ctl, .poll = bsl_poll, .getconfigfuses = NULL }; mspdebug-0.25/drivers/bsl.h000066400000000000000000000016741313531517500156710ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef BSL_H_ #define BSL_H_ #include "device.h" /* MSP430 FET Bootloader implementation. */ extern const struct device_class device_bsl; #endif mspdebug-0.25/drivers/bsllib.c000066400000000000000000000043601313531517500163460ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include "util/util.h" #include "bsllib.h" #include "gpio.h" int bsllib_seq_do(sport_t fd, const char *seq) { int state = 0; while (*seq && *seq != ':') { const char c = *(seq++); switch (c) { case 'R': state |= SPORT_MC_RTS; break; case 'r': state &= ~SPORT_MC_RTS; break; case 'D': state |= SPORT_MC_DTR; break; case 'd': state &= ~SPORT_MC_DTR; break; case ',': if (sport_set_modem(fd, state) < 0) return -1; delay_ms(50); break; } } if (sport_set_modem(fd, state) < 0) return -1; delay_ms(50); return 0; } int bsllib_seq_do_gpio(int rts, int dtr, const char *seq) { int was_rts_exported = gpio_is_exported(rts); int was_dtr_exported = gpio_is_exported(dtr); gpio_export ( rts ); gpio_set_dir ( rts, 1 ); gpio_export ( dtr ); gpio_set_dir ( dtr, 1 ); while (*seq && *seq != ':') { const char c = *(seq++); // Logic is reversed! switch (c) { case 'R': gpio_set_value ( rts, 0 ); break; case 'r': gpio_set_value ( rts, 1 ); break; case 'D': gpio_set_value ( dtr, 0 ); break; case 'd': gpio_set_value ( dtr, 1 ); break; case ',': delay_ms(50); break; } } if (was_rts_exported == 0) { gpio_unexport ( rts ); } if (was_dtr_exported == 0) { gpio_unexport ( dtr ); } delay_ms(50); return 0; } const char *bsllib_seq_next(const char *seq) { while (*seq && *seq != ':') seq++; if (*seq == ':') seq++; return seq; } mspdebug-0.25/drivers/bsllib.h000066400000000000000000000022041313531517500163460ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef BSLLIB_H_ #define BSLLIB_H_ #include "util/sport.h" /* Execute the given sequence specifier with the modem control lines */ int bsllib_seq_do(sport_t sport, const char *seq); int bsllib_seq_do_gpio(int rts, int dtr, const char *seq); /* Skip to the next part of a sequence specified */ const char *bsllib_seq_next(const char *seq); #endif mspdebug-0.25/drivers/device.c000066400000000000000000000235061313531517500163410ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include "output.h" #include "device.h" device_t device_default; static int addbrk(device_t dev, address_t addr, device_bptype_t type) { int i; int which = -1; struct device_breakpoint *bp; for (i = 0; i < dev->max_breakpoints; i++) { bp = &dev->breakpoints[i]; if (bp->flags & DEVICE_BP_ENABLED) { if (bp->addr == addr && bp->type == type) return i; } else if (which < 0) { which = i; } } if (which < 0) return -1; bp = &dev->breakpoints[which]; bp->flags = DEVICE_BP_ENABLED | DEVICE_BP_DIRTY; bp->addr = addr; bp->type = type; return which; } static void delbrk(device_t dev, address_t addr, device_bptype_t type) { int i; for (i = 0; i < dev->max_breakpoints; i++) { struct device_breakpoint *bp = &dev->breakpoints[i]; if ((bp->flags & DEVICE_BP_ENABLED) && bp->addr == addr && bp->type == type) { bp->flags = DEVICE_BP_DIRTY; bp->addr = 0; } } } int device_setbrk(device_t dev, int which, int enabled, address_t addr, device_bptype_t type) { if (which < 0) { if (enabled) return addbrk(dev, addr, type); delbrk(dev, addr, type); } else { struct device_breakpoint *bp = &dev->breakpoints[which]; int new_flags = enabled ? DEVICE_BP_ENABLED : 0; if (!enabled) addr = 0; if (bp->addr != addr || (bp->flags & DEVICE_BP_ENABLED) != new_flags) { bp->flags = new_flags | DEVICE_BP_DIRTY; bp->addr = addr; bp->type = type; } } return 0; } static uint8_t tlv_data[1024]; int tlv_read(device_t dev) { if (dev->type->readmem(dev, 0x1a00, tlv_data, 8) < 0) return -1; uint8_t info_len = tlv_data[0]; if (info_len < 1 || info_len > 8) return -1; int tlv_size = 4 * (1 << info_len); if (dev->type->readmem(dev, 0x1a00+8, tlv_data+8, tlv_size-8) < 0) return -1; return 0; } int tlv_find(const uint8_t type, uint8_t * const size, uint8_t ** const ptr) { const int tlv_size = 4 * (1 << tlv_data[0]); int i = 8; *ptr = NULL; *size = 0; while (i + 3 < tlv_size) { uint8_t tag = tlv_data[i++]; uint8_t len = tlv_data[i++]; if (tag == 0xff) break; if (tag == type) { *ptr = tlv_data + i; *size = len; break; } i += len; } return *ptr != NULL; } static void show_device_type(device_t dev) { printc("Device: %s", dev->chip->name); if (device_is_fram(dev)) printc(" [FRAM]"); printc("\n"); } int device_probe_id(device_t dev, const char *force_id) { /* skip probe if driver already did it */ if (dev->chip) { show_device_type(dev); return 0; } /* use forced id if present */ if (force_id) { dev->chip = chipinfo_find_by_name(force_id); if (!dev->chip) { printc_err("unknown chip: %s\n", force_id); return -1; } printc("Device: %s (forced)\n", dev->chip->name); return 0; } /* proceed with identification */ uint8_t data[16]; if (dev->type->readmem(dev, 0xff0, data, sizeof(data)) < 0) { printc_err("device_probe_id: read failed\n"); return -1; } struct chipinfo_id id; memset(&id, 0, sizeof(id)); if (data[0] == 0x80) { if (tlv_read(dev) < 0) { printc_err("device_probe_id: tlv_read failed\n"); return -1; } dev->dev_id[0] = tlv_data[4]; dev->dev_id[1] = tlv_data[5]; dev->dev_id[2] = tlv_data[6]; id.ver_id = r16le(tlv_data + 4); id.revision = tlv_data[6]; id.config = tlv_data[7]; id.fab = 0x55; id.self = 0x5555; id.fuses = 0x55; /* Search TLV for sub-ID */ uint8_t len; uint8_t *p; if (tlv_find(0x14, &len, &p)) { if (len >= 2) id.ver_sub_id = r16le(p); } } else { dev->dev_id[0] = data[0]; dev->dev_id[1] = data[1]; dev->dev_id[2] = data[13]; id.ver_id = r16le(data); id.ver_sub_id = 0; id.revision = data[2]; id.fab = data[3]; id.self = r16le(data + 8); id.config = data[13] & 0x7f; if(dev->type->getconfigfuses != NULL) { id.fuses = dev->type->getconfigfuses(dev); } } printc_dbg("Chip ID data:\n"); printc_dbg(" ver_id: %04x\n", id.ver_id); printc_dbg(" ver_sub_id: %04x\n", id.ver_sub_id); printc_dbg(" revision: %02x\n", id.revision); printc_dbg(" fab: %02x\n", id.fab); printc_dbg(" self: %04x\n", id.self); printc_dbg(" config: %02x\n", id.config); printc_dbg(" fuses: %02x\n", id.fuses); //printc_dbg(" activation_key: %08x\n", id.activation_key); dev->chip = chipinfo_find_by_id(&id); if (!dev->chip) { printc_err("warning: unknown chip\n"); return 0; } show_device_type(dev); return 0; } /* Is there a more reliable way of doing this? */ int device_is_fram(device_t dev) { return dev->chip && (dev->chip->features & CHIPINFO_FEATURE_FRAM); } int device_erase(device_erase_type_t et, address_t addr) { if (device_is_fram(device_default)) { printc_err("warning: not attempting erase of FRAM device\n"); return 0; } return device_default->type->erase(device_default, et, addr); } static const struct chipinfo default_chip = { .name = "DefaultChip", .bits = 20, .memory = { { .name = "DefaultFlash", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 20, .mapped = 1, .size = 0xff000, .offset = 0x01000, .seg_size = 0, .bank_size = 0, .banks = 1, }, { .name = "DefaultRam", .type = CHIPINFO_MEMTYPE_RAM, .bits = 20, .mapped = 1, .size = 0x01000, .offset = 0x00000, .seg_size = 0, .bank_size = 0, .banks = 1, }, {0} }, }; /* Given an address range, specified by a start and a size (in bytes), * return a size which is trimmed so as to not overrun a region boundary * in the chip's memory map. * * The single region occupied is optionally returned in m_ret. If the * range doesn't start in a valid region, it's trimmed to the start of * the next valid region, and m_ret is NULL. */ address_t check_range(const struct chipinfo *chip, address_t addr, address_t size, const struct chipinfo_memory **m_ret) { if (!chip) { chip = &default_chip; } const struct chipinfo_memory *m = chipinfo_find_mem_by_addr(chip, addr); if (m) { if (m->offset > addr) { address_t n = m->offset - addr; if (size > n) size = n; m = NULL; } else if (addr + size > m->offset + m->size) { size = m->offset + m->size - addr; } } *m_ret = m; return size; } /* Read bytes from device taking care of memory types. * Function read_words is only called for existing memory ranges and * with a word aligned address. * Non-existing memory locations read as 0x55. * returns 0 on success, -1 on failure */ int readmem(device_t dev, address_t addr, uint8_t *mem, address_t len, int (*read_words)(device_t dev, const struct chipinfo_memory *m, address_t addr, address_t len, uint8_t *data) ) { const struct chipinfo_memory *m; if (!len) return 0; /* Handle unaligned start */ if (addr & 1) { uint8_t data[2]; check_range(dev->chip, addr - 1, 2, &m); if (!m) data[1] = 0x55; else if (read_words(dev, m, addr - 1, 2, data) < 0) return -1; mem[0] = data[1]; addr++; mem++; len--; } /* Read aligned blocks */ while (len >= 2) { int rlen = check_range(dev->chip, addr, len & ~1, &m); if (!m) memset(mem, 0x55, rlen); else { rlen = read_words(dev, m, addr, rlen, mem); if (rlen < 0) return -1; } addr += rlen; mem += rlen; len -= rlen; } /* Handle unaligned end */ if (len) { uint8_t data[2]; check_range(dev->chip, addr, 2, &m); if (!m) data[0] = 0x55; else if (read_words(dev, m, addr, 2, data) < 0) return -1; mem[0] = data[0]; } return 0; } /* Write bytes to device taking care of memory types. * Functions write_words and read_words are only called for existing memory ranges and * with a word aligned address and length. * Writes to non-existing memory locations fail. * returns 0 on success, -1 on failure */ int writemem(device_t dev, address_t addr, const uint8_t *mem, address_t len, int (*write_words)(device_t dev, const struct chipinfo_memory *m, address_t addr, address_t len, const uint8_t *data), int (*read_words)(device_t dev, const struct chipinfo_memory *m, address_t addr, address_t len, uint8_t *data) ) { const struct chipinfo_memory *m; if (!len) return 0; /* Handle unaligned start */ if (addr & 1) { uint8_t data[2]; check_range(dev->chip, addr - 1, 2, &m); if (!m) goto fail; // fail on unmapped regions if (read_words(dev, m, addr - 1, 2, data) < 0) return -1; data[1] = mem[0]; if (write_words(dev, m, addr - 1, 2, data) < 0) return -1; addr++; mem++; len--; } while (len >= 2) { int wlen = check_range(dev->chip, addr, len & ~1, &m); if (!m) goto fail; // fail on unmapped regions wlen = write_words(dev, m, addr, wlen, mem); if (wlen < 0) return -1; addr += wlen; mem += wlen; len -= wlen; } /* Handle unaligned end */ if (len) { uint8_t data[2]; check_range(dev->chip, addr, 2, &m); if (!m) goto fail; // fail on unmapped regions if (read_words(dev, m, addr, 2, data) < 0) return -1; data[0] = mem[0]; if (write_words(dev, m, addr, 2, data) < 0) return -1; } return 0; fail: printc_err("writemem failed at 0x%x\n", addr); return -1; } mspdebug-0.25/drivers/device.h000066400000000000000000000133751313531517500163510ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef DEVICE_H_ #define DEVICE_H_ #include #include "util.h" #include "powerbuf.h" #include "chipinfo.h" #include "bytes.h" struct device; typedef struct device *device_t; typedef enum { DEVICE_CTL_RESET, DEVICE_CTL_RUN, DEVICE_CTL_HALT, DEVICE_CTL_STEP, DEVICE_CTL_SECURE } device_ctl_t; typedef enum { DEVICE_STATUS_HALTED, DEVICE_STATUS_RUNNING, DEVICE_STATUS_INTR, DEVICE_STATUS_ERROR } device_status_t; typedef enum { DEVICE_ERASE_ALL, DEVICE_ERASE_MAIN, DEVICE_ERASE_SEGMENT } device_erase_type_t; #define DEVICE_NUM_REGS 16 #define DEVICE_MAX_BREAKPOINTS 32 #define DEVICE_BP_ENABLED 0x01 #define DEVICE_BP_DIRTY 0x02 typedef enum { DEVICE_BPTYPE_BREAK, DEVICE_BPTYPE_WATCH, DEVICE_BPTYPE_READ, DEVICE_BPTYPE_WRITE } device_bptype_t; struct device_breakpoint { device_bptype_t type; address_t addr; int flags; }; #define DEVICE_FLAG_JTAG 0x01 /* default is SBW */ #define DEVICE_FLAG_LONG_PW 0x02 #define DEVICE_FLAG_TTY 0x04 /* default is USB */ #define DEVICE_FLAG_FORCE_RESET 0x08 #define DEVICE_FLAG_DO_FWUPDATE 0x10 #define DEVICE_FLAG_SKIP_CLOSE 0x20 struct device_args { int flags; int vcc_mv; const char *path; const char *forced_chip_id; const char *requested_serial; const char *require_fwupdate; const char *bsl_entry_seq; int bsl_gpio_used; int bsl_gpio_rts; int bsl_gpio_dtr; }; struct device_class { const char *name; const char *help; /* Create a new device */ device_t (*open)(const struct device_args *args); /* Close the connection to the device and destroy the driver object */ void (*destroy)(device_t dev); /* Read/write memory */ int (*readmem)(device_t dev, address_t addr, uint8_t *mem, address_t len); int (*writemem)(device_t dev, address_t addr, const uint8_t *mem, address_t len); /* Erase memory */ int (*erase)(device_t dev, device_erase_type_t type, address_t address); /* Read/write registers */ int (*getregs)(device_t dev, address_t *regs); int (*setregs)(device_t dev, const address_t *regs); /* CPU control */ int (*ctl)(device_t dev, device_ctl_t op); /* Wait a little while for the CPU to change state */ device_status_t (*poll)(device_t dev); /* Get the configuration fuse values */ int (*getconfigfuses)(device_t dev); }; struct device { const struct device_class *type; uint8_t dev_id[3]; /* Breakpoint table. This should not be modified directly. * Instead, you should use the device_setbrk() helper function. This * will set the appropriate flags and ensure that the breakpoint is * reloaded before the next run. */ int max_breakpoints; struct device_breakpoint breakpoints[DEVICE_MAX_BREAKPOINTS]; /* Power sample buffer, if power profiling is supported by this * device. */ powerbuf_t power_buf; /* Chip information data. */ const struct chipinfo *chip; int need_probe; }; /* Probe the device memory and extract ID bytes. This should be called * after the device structure is ready. */ int device_probe_id(device_t dev, const char *force_id); /* Determine, from the device ID bytes, whether this chip is an FRAM or * flash-based device. */ int device_is_fram(device_t dev); /* Set or clear a breakpoint. The index of the modified entry is * returned, or -1 if no free entries were available. The modified * entry is flagged so that it will be reloaded on the next run. * * If which is specified, a particular breakpoint slot is * modified. Otherwise, if which < 0, breakpoint slots are selected * automatically. */ int device_setbrk(device_t dev, int which, int enabled, address_t address, device_bptype_t type); extern device_t device_default; /* Helper macros for operating on the default device */ #define device_destroy() device_default->type->destroy(device_default) #define device_readmem(addr, mem, len) \ device_default->type->readmem(device_default, addr, mem, len) #define device_writemem(addr, mem, len) \ device_default->type->writemem(device_default, addr, mem, len) #define device_getregs(regs) \ device_default->type->getregs(device_default, regs) #define device_setregs(regs) \ device_default->type->setregs(device_default, regs) #define device_ctl(op) \ device_default->type->ctl(device_default, op) #define device_poll() \ device_default->type->poll(device_default) int device_erase(device_erase_type_t et, address_t addr); address_t check_range(const struct chipinfo *chip, address_t addr, address_t size, const struct chipinfo_memory **m_ret); int readmem(device_t dev, address_t addr, uint8_t *mem, address_t len, int (*read_words)(device_t dev, const struct chipinfo_memory *m, address_t addr, address_t len, uint8_t *data) ); int writemem(device_t dev, address_t addr, const uint8_t *mem, address_t len, int (*write_words)(device_t dev, const struct chipinfo_memory *m, address_t addr, address_t len, const uint8_t *data), int (*read_words)(device_t dev, const struct chipinfo_memory *m, address_t addr, address_t len, uint8_t *data) ); #endif mspdebug-0.25/drivers/devicelist.c000066400000000000000000000764631313531517500172470ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * Copyright (C) 2012 Stanimir Bonev * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include "devicelist.h" const struct device_table sdeviceID[] = { /* Fuse parameter is set without lock bit * 0x0 0x1 0x2 0x3 0x8 0x9 0xD Fuse Fuse DeviceTypeID Device String * ID0 ID1 Rev Fab Self0 Self1 Confg Pattern */ {{ 0 , 0 , - 1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_UNKNOWN_DEVICE, "Device_unknown"}, {{0xf1, 0x12, 0x00, 0x43, 0x00, 0x08, -1 , -1 , -1 }, DT_MSP430F11x1, "Prototype_MSP430F11x1"}, {{0xf1, 0x12, 0x10, 0x40, 0x00, 0x00, -1 , -1 , -1 }, DT_MSP430F11x1D, "MSP430F11x1"}, {{0xf1, 0x49, -1 , -1 , -1 , -1 , -1 , 0x05 , 0x0f }, DT_MSP430F133, "MSP430F133"}, {{0xf1, 0x49, -1 , -1 , -1 , -1 , -1 , 0x04 , 0x0f }, DT_MSP430F135, "MSP430F135"}, {{0xf1, 0x49, -1 , -1 , -1 , -1 , -1 , 0x02 , 0x0f }, DT_MSP430F147, "MSP430F147"}, {{0xf1, 0x49, -1 , -1 , -1 , -1 , -1 , 0x01 , 0x0f }, DT_MSP430F148, "MSP430F148"}, {{0xf1, 0x49, -1 , -1 , -1 , -1 , -1 , 0x00 , 0x0f }, DT_MSP430F149, "MSP430F149"}, {{0xf4, 0x03, 0x00, 0x40, -1 , -1 , -1 , -1 , -1 }, DT_MSP430F413P, "Preliminary_MSP430F413"}, {{0xf4, 0x13, 0x02, 0x40, -1 , -1 , -1 , -1 , -1 }, DT_MSP430F41xC, "MSP430F41x"}, {{0xf1, 0x12, 0x13, -1, 0x00, 0x00, -1 , -1 , -1 }, DT_MSP430F11x1A, "MSP430F11x1A"}, {{0xf1, 0x23, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F12x, "MSP430F12x"}, {{0xf4, 0x37, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F43x, "MSP430F43x"}, //- 80 Pin {{0xf4, 0x49, -1 , -1 , -1 , -1 , -1 , 0x02 , 0x0f }, DT_MSP430F43x, "MSP430F43x"}, //- 100 Pin {{0xf4, 0x49, -1 , -1 , -1 , -1 ,0x00 , 0x00 , 0x0f }, DT_MSP430F44x, "MSP430F44x"}, {{0x12, 0x32, 0x00, 0x40, -1 , -1 , -1 , -1 , -1 }, DT_MSP430F12x2, "Preliminary_MSP430F12x2"}, {{0x11, 0x32, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F11x2, "MSP430F11x2"}, {{0x12, 0x32, 0x10, 0x40, -1 , -1 , -1 , -1 , -1 }, DT_MSP430F12x2C, "MSP430F12x2/F11x2"}, {{0xf1, 0x69, 0x00, 0x40, -1 , -1 , -1 , -1 , -1 }, DT_PMS430F16x, "Preliminary_MSP430F16x"}, //DT_PMS430F169}, {{0xf4, 0x27, 0x00, -1 , -1 , -1 , 'E' , 0x02 , 0x1f }, DT_MSP430FE423, "MSP430FE423_P"}, {{0xf4, 0x27, 0x00, -1 , -1 , -1 , 'E' , 0x01 , 0x1f }, DT_MSP430FE425, "MSP430FE425_P"}, {{0xf4, 0x27, 0x00, -1 , -1 , -1 , 'E' , 0x00 , 0x1f }, DT_MSP430FE427, "MSP430FE427_P"}, {{0xf4, 0x27, 0x10, -1 , -1 , -1 , 'E' , 0x02 , 0x1f }, DT_MSP430FE423, "MSP430FE423_N"}, {{0xf4, 0x27, 0x10, -1 , -1 , -1 , 'E' , 0x01 , 0x1f }, DT_MSP430FE425, "MSP430FE425_N"}, {{0xf4, 0x27, 0x10, -1 , -1 , -1 , 'E' , 0x00 , 0x1f }, DT_MSP430FE427, "MSP430FE427_N"}, {{0xf4, 0x27, -1 , -1 , -1 , -1 , 'E' , 0x02 , 0x1f }, DT_MSP430FE423, "MSP430FE423"}, // 4nd revision {{0xf4, 0x27, -1 , -1 , -1 , -1 , 'E' , 0x01 , 0x1f }, DT_MSP430FE425, "MSP430FE425"}, {{0xf4, 0x27, -1 , -1 , -1 , -1 , 'E' , 0x00 , 0x1f }, DT_MSP430FE427, "MSP430FE427"}, {{0xf4, 0x27, -1 , -1 , -1 , -1 , 'E' , 0x06 , 0x1f }, DT_MSP430F423, "MSP430F423"}, //F42x based on FE42x {{0xf4, 0x27, -1 , -1 , -1 , -1 , 'E' , 0x05 , 0x1f }, DT_MSP430F425, "MSP430F425"}, {{0xf4, 0x27, -1 , -1 , -1 , -1 , 'E' , 0x04 , 0x1f }, DT_MSP430F427, "MSP430F427"}, {{0xf4, 0x27, -1 , -1 , -1 , -1 , 'W' , -1 , -1 }, DT_MSP430FW42x, "MSP430FW42x/F41x"}, // FW42x and F41x based on FW42x {{0xf4, 0x27, -1 , -1 , -1 , -1 , 'G' , 0x06 , 0x07 }, DT_MSP430F4230, "MSP430F4230"}, //F42x0 {{0xf4, 0x27, -1 , -1 , -1 , -1 , 'G' , 0x05 , 0x07 }, DT_MSP430F4250, "MSP430F4250"}, {{0xf4, 0x27, -1 , -1 , -1 , -1 , 'G' , 0x04 , 0x07 }, DT_MSP430F42x0, "MSP430F42x0"}, {{0xf1, 0x69, -1 , -1 , -1 , -1 , -1 , 0x06 , 0x0f }, DT_MSP430F155, "MSP430F155"}, {{0xf1, 0x69, -1 , -1 , -1 , -1 , -1 , 0x05 , 0x0f }, DT_MSP430F156, "MSP430F156"}, {{0xf1, 0x69, -1 , -1 , -1 , -1 , -1 , 0x04 , 0x0f }, DT_MSP430F157, "MSP430F157"}, {{0xf1, 0x69, -1 , -1 , -1 , -1 , -1 , 0x02 , 0x0f }, DT_MSP430F167, "MSP430F167"}, {{0xf1, 0x69, -1 , -1 , -1 , -1 , -1 , 0x01 , 0x0f }, DT_MSP430F168, "MSP430F168"}, {{0xf1, 0x69, -1 , -1 , -1 , -1 , -1 , 0x00 , 0x0f }, DT_MSP430F169, "MSP430F169"}, {{0xf1, 0x6C, -1 , -1 , -1 , -1 , -1 , 0x03 , 0x07 }, DT_MSP430F1610, "MSP430F1610"}, {{0xf1, 0x6C, -1 , -1 , -1 , -1 , -1 , 0x00 , 0x07 }, DT_MSP430F1611, "MSP430F1611"}, {{0xf1, 0x6C, -1 , -1 , -1 , -1 , -1 , 0x06 , 0x07 }, DT_MSP430F1612, "MSP430F1612"}, {{0xf1, 0x6C, -1 , -1 , -1 , -1 , -1 , 0x07 , 0x07 }, DT_MSP430F169, "MSP430F169"}, //MSP430F169 based on F1611 {{0xf4, 0x39, -1 , -1 , -1 , -1 , 'G' , -1 , -1 }, DT_MSP430FG43x, "MSP430FG43x_F43x"}, //DT_MSP430FG439/ F43x {{0xf4, 0x6F, -1 , -1 , -1 , -1 , 'G' , 0x00 , 0x03 }, DT_MSP430FG4619, "MSP430FG4619"}, //DT_MSP430FG4619 {{0xf2, 0x13, -1 , -1 , -1 , -1 , 0x01, -1 , -1 }, DT_MSP430F21x1, "MSP430F21x1"}, //MSP430F21x1 devices {{0xaf, 0x13, 0x90, -1 , -1 , -1 , -1 , -1 , -1 }, DT_TMS430F1390, "TMS430FCAS001"}, //Automotive Device {{0xaf, 0x12, 0x50, -1 , -1 , -1 , -1 , -1 , -1 }, DT_TMS430F1250, "TMS430FCAS003"}, //Automotive Device {{0xA0, 0x54, 0x49, -1 , -1 , -1 , -1 , -1 , -1 }, DT_TMS430C1250, "TMS430ROMSHUTTLE"}, //Automotive Device {{0xAE, 0x10, 0x00, -1 , -1 , -1 , -1 , -1 , -1 }, DT_TMS430EMU, "TMS430EMU"}, //Automotive Device {{0xF2, 0x01, -1, -1 , -1 , -1 , 0x03, -1 , -1 }, DT_MSP430F20x3, "MSP430F20x3"}, // MSP430F20x3 {{0xF2, 0x01, -1, -1 , -1 , -1 , 0x02, -1 , -1 }, DT_MSP430F20x2, "F20x2_G2x2x_G2x3x"},// MSP430F20x2 {{0xF2, 0x01, -1, -1 , -1 , -1 , 0x01, -1 , -1 }, DT_MSP430F20x1, "F20x1_G2x0x_G2x1x"}, // MSP430F20x1 {{0xF2, 0x27, -1, -1 , -1 , -1 , -1 , 0x02 , 0x07 }, DT_MSP430F2234, "MSP430F2234"}, // MSP430F2234 {{0xF2, 0x27, -1, -1 , -1 , -1 , -1 , 0x01 , 0x07 }, DT_MSP430F2254, "MSP430F2254"}, // MSP430F2254 {{0xF2, 0x27, -1, -1 , -1 , -1 , -1 , 0x00 , 0x07 }, DT_MSP430F2274, "MSP430F2274"}, // MSP430F2274 {{0xf4, 0x6F, -1 , -1 , -1 , -1 , 'G' , 0x01 , 0x03 }, DT_MSP430FG4618, "MSP430FG4618"}, //DT_MSP430FG4618 {{0xf2, 0x37, -1 , -1 , -1 , -1 , -1 , 0x02 , 0x03 }, DT_MSP430F2330, "MSP430F2330"}, //MSP430F2330 {{0xf2, 0x37, -1 , -1 , -1 , -1 , -1 , 0x01 , 0x03 }, DT_MSP430F2350, "MSP430F2350"}, //MSP430F2350 {{0xf2, 0x37, -1 , -1 , -1 , -1 , -1 , 0x00 , 0x03 }, DT_MSP430F2370, "MSP430F2370"}, //MSP430F2370 {{0xF2, 0x27, -1, -1 , -1 , -1 , -1 , 0x06 , 0x07 }, DT_MSP430F2232, "MSP430F2232"}, // MSP430F2232 {{0xF2, 0x27, -1, -1 , -1 , -1 , -1 , 0x05 , 0x07 }, DT_MSP430F2252, "MSP430F2252"}, // MSP430F2252 {{0xF2, 0x27, -1, -1 , -1 , -1 , -1 , 0x04 , 0x07 }, DT_MSP430F2272, "MSP430F2272"}, // MSP430F2272 {{0xF2, 0x6F, -1 , -1 , -1 , -1 , -1 , 0x00 , 0x07 }, DT_MSP430F2619, "MSP430F2619"}, // MSP430F2619 {{0xF2, 0x6F, -1 , -1 , -1 , -1 , -1 , 0x01 , 0x07 }, DT_MSP430F2618, "MSP430F2618"}, // MSP430F2618 {{0xF2, 0x6F, -1 , -1 , -1 , -1 , -1 , 0x04 , 0x07 }, DT_MSP430F2419, "MSP430F2419"}, // MSP430F2419 {{0xF2, 0x6F, -1 , -1 , -1 , -1 , -1 , 0x05 , 0x07 }, DT_MSP430F2418, "MSP430F2418"}, // MSP430F2418 {{0x42, 0x7A, -1 , -1 , -1 , -1 , 'E' , 0x02 , 0x1f }, DT_MSP430FE423A, "MSP430FE423A"}, // 4nd revision {{0x42, 0x7A, -1 , -1 , -1 , -1 , 'E' , 0x01 , 0x1f }, DT_MSP430FE425A, "MSP430FE425A"}, {{0x42, 0x7A, -1 , -1 , -1 , -1 , 'E' , 0x00 , 0x1f }, DT_MSP430FE427A, "MSP430FE427A"}, {{0x42, 0x7A, -1 , -1 , -1 , -1 , 'E' , 0x06 , 0x1f }, DT_MSP430F423A, "MSP430F423A"}, //F42x based on FE42x {{0x42, 0x7A, -1 , -1 , -1 , -1 , 'E' , 0x05 , 0x1f }, DT_MSP430F425A, "MSP430F425A"}, {{0x42, 0x7A, -1 , -1 , -1 , -1 , 'E' , 0x04 , 0x1f }, DT_MSP430F427A, "MSP430F427A"}, {{0xf4, 0x49, -1 , -1 , -1 , -1 , 0x02, 0x07 , 0x07 }, DT_MSP430F4783, "MSP430F4783"}, //DT_MSP430F4783 {{0xf4, 0x49, -1 , -1 , -1 , -1 , 0x02, 0x03 , 0x07 }, DT_MSP430F4784, "MSP430F4784"}, //DT_MSP430F4784 {{0xf4, 0x49, -1 , -1 , -1 , -1 , 0x02, 0x04 , 0x07 }, DT_MSP430F4793, "MSP430F4793"}, //DT_MSP430F4793 {{0xf4, 0x49, -1 , -1 , -1 , -1 , 0x02, 0x00 , 0x07 }, DT_MSP430F4794, "MSP430F4794"}, //DT_MSP430F4794 {{0xF2, 0x49, -1 , -1 , -1 , -1 , -1 , 0x00 , 0x0F }, DT_MSP430F249, "MSP430F249"}, // MSP430F249 {{0xF2, 0x49, -1 , -1 , -1 , -1 , -1 , 0x01 , 0x0F }, DT_MSP430F248, "MSP430F248"}, // MSP430F248 {{0xF2, 0x49, -1 , -1 , -1 , -1 , -1 , 0x02 , 0x0F }, DT_MSP430F247, "MSP430F247"}, // MSP430F247 {{0xF2, 0x49, -1 , -1 , -1 , -1 , -1 , 0x03 , 0x0F }, DT_MSP430F235, "MSP430F235"}, // MSP430F235 {{0xF2, 0x49, -1 , -1 , -1 , -1 , -1 , 0x04 , 0x0F }, DT_MSP430F2491, "MSP430F2491"}, // MSP430F2491 {{0xF2, 0x49, -1 , -1 , -1 , -1 , -1 , 0x05 , 0x0F }, DT_MSP430F2481, "MSP430F2481"}, // MSP430F2481 {{0xF2, 0x49, -1 , -1 , -1 , -1 , -1 , 0x06 , 0x0F }, DT_MSP430F2471, "MSP430F2471"}, // MSP430F2471 {{0xF2, 0x49, -1 , -1 , -1 , -1 , -1 , 0x07 , 0x0F }, DT_MSP430F233, "MSP430F233"}, // MSP430F233 {{0xF2, 0x49, -1 , -1 , -1 , -1 , -1 , 0x08 , 0x0F }, DT_MSP430F2410, "MSP430F2410"}, // MSP430F2410 {{0xF2, 0x13, -1 , -1 , -1 , -1 , 0x02, 0x00 , 0x03 }, DT_MSP430F2132, "MSP430F2132"}, // MSP430F2132 {{0xF2, 0x13, -1 , -1 , -1 , -1 , 0x02, 0x01 , 0x03 }, DT_MSP430F2122, "MSP430F2122"}, // MSP430F2122 {{0xF2, 0x13, -1 , -1 , -1 , -1 , 0x02, 0x02 , 0x03 }, DT_MSP430F2112, "MSP430F2112"}, // MSP430F2112 {{0x54, 0x38,0x01 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_XMS430F5438, "XMS430F5438"}, // XMS430F5438 {{0x54, 0x38, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5438, "MSP430F5438"}, // MSP430F5438 {{0x54, 0x36, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5436, "MSP430F5436"}, // MSP430F5436 {{0x54, 0x19, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5419, "MSP430F5419"}, // MSP430F5419 {{0x42, 0x52, -1 , -1 , -1 , -1 , 'E' , 0x12 , 0x1f }, DT_MSP430FE4232, "MSP430FE4232"}, // MSP430FE4232 {{0x42, 0x52, -1 , -1 , -1 , -1 , 'E' , 0x11 , 0x1f }, DT_MSP430FE42x2, "MSP430FE42x2"}, // MSP430FE42x2 (MSP430FE4242 and MSP430FE4252) {{0x54, 0x37, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5437, "MSP430F5437"}, // MSP430F5437 {{0x54, 0x35, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5435, "MSP430F5435"}, // MSP430F5435 {{0x54, 0x18, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5418, "MSP430F5418"}, // MSP430F5418 {{0xf4, 0x27, -1 , -1 , -1 , -1 , 'G' , 0x01 , 0x07 }, DT_MSP430FG4250, "MSP430FG4250"}, // MSP430FG4250 {{0xf4, 0x27, -1 , -1 , -1 , -1 , 'G' , 0x00 , 0x07 }, DT_MSP430FG42x0, "MSP430FG42x0"}, // MSP430FG42x0 {{0x42, 0x52, -1 , -1 , -1 , -1 , 'E' , 0x10 , 0x1f }, DT_MSP430FE4272, "MSP430FE4272"}, // MSP430FE4272 {{0xF4, 0x79, -1 , -1 , -1 , -1 , 'G' , 0x02 , 0x07 }, DT_MSP430FG477, "MSP430FG477"}, // MSP430FG477 {{0xF4, 0x79, -1 , -1 , -1 , -1 , 'G' , 0x01 , 0x07 }, DT_MSP430FG478, "MSP430FG478"}, // MSP430FG478 {{0xF4, 0x79, -1 , -1 , -1 , -1 , 'G' , 0x00 , 0x07 }, DT_MSP430FG479, "MSP430FG479"}, // MSP430FG479 {{0xF4, 0x79, -1 , -1 , -1 , -1 , 'G' , 0x06 , 0x07 }, DT_MSP430F477, "MSP430F477"}, // MSP430F477 {{0xF4, 0x79, -1 , -1 , -1 , -1 , 'G' , 0x05 , 0x07 }, DT_MSP430F478, "MSP430F478"}, // MSP430F478 {{0xF4, 0x79, -1 , -1 , -1 , -1 , 'G' , 0x04 , 0x07 }, DT_MSP430F479, "MSP430F479"}, // MSP430F479 {{0xf4, 0x7f, -1 , -1 , -1 , -1 , -1 , 0x00 , 0x0F }, DT_MSP430F47197, "MSP430F47197"}, // MSP430F47197 {{0xf4, 0x7f, -1 , -1 , -1 , -1 , -1 , 0x01 , 0x0F }, DT_MSP430F47187, "MSP430F47187"}, // MSP430F47187 {{0xf4, 0x7f, -1 , -1 , -1 , -1 , -1 , 0x02 , 0x0F }, DT_MSP430F47177, "MSP430F47177"}, // MSP430F47177 {{0xf4, 0x7f, -1 , -1 , -1 , -1 , -1 , 0x03 , 0x0F }, DT_MSP430F47167, "MSP430F47167"}, // MSP430F47167 {{0xf4, 0x7f, -1 , -1 , -1 , -1 , -1 , 0x04 , 0x0F }, DT_MSP430F47196, "MSP430F47196"}, // MSP430F47196 {{0xf4, 0x7f, -1 , -1 , -1 , -1 , -1 , 0x05 , 0x0F }, DT_MSP430F47186, "MSP430F47186"}, // MSP430F47186 {{0xf4, 0x7f, -1 , -1 , -1 , -1 , -1 , 0x06 , 0x0F }, DT_MSP430F47176, "MSP430F47176"}, // MSP430F47176 {{0xf4, 0x7f, -1 , -1 , -1 , -1 , -1 , 0x07 , 0x0F }, DT_MSP430F47166, "MSP430F47166"}, // MSP430F47166 {{0x41, 0x52, -1 , -1 , -1 , -1 , -1 , 0x00 , 0x01 }, DT_MSP430F4152, "MSP430F4152"}, // MSP430F4152 {{0x41, 0x52, -1 , -1 , -1 , -1 , -1 , 0x01 , 0x01 }, DT_MSP430F4132, "MSP430F4132"}, // MSP430F4132 {{0x61, 0x37, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_CC430F6137, "CC430F6137"}, // CC430F6137 {{0x61, 0x35, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_CC430F6135, "CC430F6135"}, // CC430F6135 {{0x61, 0x27, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_CC430F6127, "CC430F6127"}, // CC430F6127 {{0x61, 0x26, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_CC430F6126, "CC430F6126"}, // CC430F6126 {{0x61, 0x25, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_CC430F6125, "CC430F6125"}, // CC430F6125 {{0x51, 0x37, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_CC430F5137, "CC430F5137"}, // CC430F5137 {{0x51, 0x35, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_CC430F5135, "CC430F5135"}, // CC430F5135 {{0x51, 0x33, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_CC430F5133, "CC430F5133"}, // CC430F5133 {{0x55, 0x13, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5513, "MSP430F5513"}, // MSP430F5513 {{0x55, 0x14, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5514, "MSP430F5514"}, // MSP430F5514 {{0x55, 0x15, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5515, "MSP430F5515"}, // MSP430F5515 {{0x55, 0x17, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5517, "MSP430F5517"}, // MSP430F5517 {{0x55, 0x19, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5519, "MSP430F5519"}, // MSP430F5519 {{0x55, 0x21, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5521, "MSP430F5521"}, // MSP430F5521 {{0x55, 0x22, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5522, "MSP430F5522"}, // MSP430F5522 {{0x55, 0x24, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5524, "MSP430F5524"}, // MSP430F5524 {{0x55, 0x25, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5525, "MSP430F5525"}, // MSP430F5525 {{0x55, 0x26, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5526, "MSP430F5526"}, // MSP430F5526 {{0x55, 0x27, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5527, "MSP430F5527"}, // MSP430F5527 {{0x55, 0x28, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5528, "MSP430F5528"}, // MSP430F5528 {{0x55, 0x29, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5529, "MSP430F5529"}, // MSP430F5529 {{0x05, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5438A, "MSP430F5438A"}, // MSP430F5438A {{0x03, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5436A, "MSP430F5436A"}, // MSP430F5436A {{0x01, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5419A, "MSP430F5419A"}, // MSP430F5419A {{0x04, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5437A, "MSP430F5437A"}, // MSP430F5437A {{0x02, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5435A, "MSP430F5435A"}, // MSP430F5435A {{0x00, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5418A, "MSP430F5418A"}, // MSP430F5418A {{0x31, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5510, "MSP430F5510"}, // MSP430F5510 {{0x26, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5131, "MSP430F5131"}, // MSP430F5131 {{0x28, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5132, "MSP430F5132"}, // MSP430F5132 {{0x2A, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5151, "MSP430F5151"}, // MSP430F5151 {{0x2C, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5152, "MSP430F5152"}, // MSP430F5152 {{0x2E, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5171, "MSP430F5171"}, // MSP430F5171 {{0x30, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5172, "MSP430F5172"}, // MSP430F5172 {{0x3C, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5630, "MSP430F5630"}, // MSP430F5630 {{0x3E, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5631, "MSP430F5631"}, // MSP430F5631 {{0x40, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5632, "MSP430F5632"}, // MSP430F5632 {{0x42, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5633, "MSP430F5633"}, // MSP430F5633 {{0x44, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5634, "MSP430F5634"}, // MSP430F5634 {{0x0E, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5635, "MSP430F5635"}, // MSP430F5635 {{0x10, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5636, "MSP430F5636"}, // MSP430F5636 {{0x12, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5637, "MSP430F5637"}, // MSP430F5637 {{0x14, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5638, "MSP430F5638"}, // MSP430F5638 {{0x46, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6630, "MSP430F6630"}, // MSP430F6630 {{0x48, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6631, "MSP430F6631"}, // MSP430F6631 {{0x4A, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6632, "MSP430F6632"}, // MSP430F6632 {{0x4C, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6633, "MSP430F6633"}, // MSP430F6633 {{0x4E, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6634, "MSP430F6634"}, // MSP430F6634 {{0x16, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6635, "MSP430F6635"}, // MSP430F6635 {{0x18, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6636, "MSP430F6636"}, // MSP430F6636 {{0x1A, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6637, "MSP430F6637"}, // MSP430F6637 {{0x1C, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6638, "MSP430F6638"}, // MSP430F6638 {{0x03, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5739, "MSP430FR5739"}, // MSP430FR5739 {{0x92, 0xC0, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430L092 , "MSP430L092" }, // MSP430L092 {{0x54, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6700, "MSP430F6700"}, // MSP430F6700 {{0x55, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6701, "MSP430F6701"}, // MSP430F6701 {{0x56, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6702, "MSP430F6702"}, // MSP430F6702 {{0x57, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6703, "MSP430F6703"}, // MSP430F6703 {{0x58, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6720, "MSP430F6720"}, // MSP430F6720 {{0x59, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6721, "MSP430F6721"}, // MSP430F6721 {{0x60, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6722, "MSP430F6722"}, // MSP430F6722 {{0x61, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6723, "MSP430F6723"}, // MSP430F6723 {{0x62, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6730, "MSP430F6730"}, // MSP430F6730 {{0x63, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6731, "MSP430F6731"}, // MSP430F6731 {{0x64, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6732, "MSP430F6732"}, // MSP430F6732 {{0x65, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6733, "MSP430F6733"}, // MSP430F6733 {{0x3A, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5509, "MSP430F5509"}, // MSP430F5509 {{0x39, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5508, "MSP430F5508"}, // MSP430F5508 {{0x38, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5507, "MSP430F5507"}, // MSP430F5507 {{0x37, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5506, "MSP430F5506"}, // MSP430F5506 {{0x36, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5505, "MSP430F5505"}, // MSP430F5505 {{0x35, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5504, "MSP430F5504"}, // MSP430F5504 {{0x34, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5503, "MSP430F5503"}, // MSP430F5503 {{0x33, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5502, "MSP430F5502"}, // MSP430F5502 {{0x32, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5501, "MSP430F5501"}, // MSP430F5501 {{0x3B, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5500, "MSP430F5500"}, // MSP430F5500 {{0x12, 0x32, -1, -1, -1 , -1 , -1 , -1 , -1 }, DT_MSP430F12x2New, "MSP430F12x2/F11x2"}, // all new spins of 11x2 & 12x2 {{0x15, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5310, "MSP430F5310"}, // MSP430F5310 {{0x14, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5309, "MSP430F5309"}, // MSP430F5309 {{0x13, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5308, "MSP430F5308"}, // MSP430F5308 {{0x12, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5304, "MSP430F5304"}, // MSP430F5304 {{0x02, 0x53, -1 , -1 , -1 , -1 , -1 , 0x0 , 0xF}, DT_MSP430AFE253, "MSP430AFE253"}, // MSP430AFE253,/ {{0x1b, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5329, "MSP430F5329"}, // MSP430F5329 {{0x1a, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5328, "MSP430F5328"}, // MSP430F5328 {{0x19, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5327, "MSP430F5327"}, // MSP430F5327 {{0x18, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5326, "MSP430F5326"}, // MSP430F5326 {{0x17, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5325, "MSP430F5325"}, // MSP430F5325 {{0x16, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5324, "MSP430F5324"}, // MSP430F5324 {{0x24, 0x52, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430G2452, "MSP430G2xx2"}, // MSP430G2452 {{0x1e, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5342, "MSP430F5342"}, // MSP430F5342 {{0x1d, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5341, "MSP430F5341"}, // MSP430F5341 {{0x1c, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5340, "MSP430F5340"}, // MSP430F5340 {{0xf4, 0x29, -1 , -1 , -1 , -1 , 'W' , -1 , -1 }, DT_MSP430FW429, "MSP430FW429"}, // FW428 FW429 {{0x2b, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6659, "MSP430F6659"}, // MSP430F6659 {{0x2c, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6658, "MSP430F6658"}, // MSP430F6658 {{0x2d, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6459, "MSP430F6459"}, // MSP430F6459 {{0x2e, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6458, "MSP430F6458"}, // MSP430F6459 {{0x2f, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6457, "MSP430F6457"}, // MSP430F6457 {{0x30, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5659, "MSP430F5659"}, // MSP430F5659 {{0x31, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5658, "MSP430F5658"}, // MSP430F5658 {{0x32, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5359, "MSP430F5359"}, // MSP430F5359 {{0x33, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5358, "MSP430F5358"}, // MSP430F5358 {{0x34, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5357, "MSP430F5357"}, // MSP430F5357 {{0x25, 0x53, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430G2553, "MSP430G2xx3"}, // MSP430G2x53 {{0x02, 0x53, -1 , -1 , -1 , -1 , -1 , 0x2 , 0xF}, DT_MSP430AFE233, "MSP430AFE233"}, // MSP430AFE233 {{0x02, 0x53, -1 , -1 , -1 , -1 , -1 , 0x3 , 0xF}, DT_MSP430AFE223, "MSP430AFE223"}, // MSP430AFE223 {{0x02, 0x53, -1 , -1 , -1 , -1 , -1 , 0x4 , 0xF}, DT_MSP430AFE252, "MSP430AFE252"}, // MSP430AFE252 {{0x02, 0x53, -1 , -1 , -1 , -1 , -1 , 0x6 , 0xF}, DT_MSP430AFE232, "MSP430AFE232"}, // MSP430AFE232 {{0x02, 0x53, -1 , -1 , -1 , -1 , -1 , 0x7 , 0xF}, DT_MSP430AFE222, "MSP430AFE222"}, // MSP430AFE222 {{0x02, 0x53, -1 , -1 , -1 , -1 , -1 , 0x8 , 0xF}, DT_MSP430AFE251, "MSP430AFE251"}, // MSP430AFE251 {{0x02, 0x53, -1 , -1 , -1 , -1 , -1 , 0xA , 0xF}, DT_MSP430AFE231, "MSP430AFE231"}, // MSP430AFE231 {{0x02, 0x53, -1 , -1 , -1 , -1 , -1 , 0xB , 0xF}, DT_MSP430AFE221, "MSP430AFE221"}, // MSP430AFE221 {{0x02, 0x53, -1 , -1 , -1 , -1 , -1 , 0xC , 0xF}, DT_MSP430AFE250, "MSP430AFE250"}, // MSP430AFE250 {{0x02, 0x53, -1 , -1 , -1 , -1 , -1 , 0xE , 0xF}, DT_MSP430AFE230, "MSP430AFE230"}, // MSP430AFE230 {{0x02, 0x53, -1 , -1 , -1 , -1 , -1 , 0xF , 0xF}, DT_MSP430AFE220, "MSP430AFE220"}, // MSP430AFE220 {{0x51, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5229, "MSP430F5229"}, // MSP430F5529 {{0x02, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5738, "MSP430FR5738"}, // MSP430FR5738 {{0x76, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5735, "MSP430FR5735"}, // MSP430FR5735 {{0x7c, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5730, "MSP430FR5730"}, // MSP430FR5730 {{0x7b, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5729, "MSP430FR5729"}, // MSP430FR5729 {{0x7a, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5728, "MSP430FR5728"}, // MSP430FR5728 {{0x78, 0x80, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5725, "MSP430FR5725"}, // MSP430FR5725 {{0x70, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5720, "MSP430FR5720"}, // MSP430FR5720 {{0x69, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5969, "MSP430FR5969"}, // MSP430FR5969 {{0x35, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_CC430F6147, "CC430F6147"}, // CC430F6147 {{0x36, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_CC430F6145, "CC430F6145"}, // CC430F6145 {{0x37, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_CC430F6143, "CC430F6143"}, // CC430F6143 {{0x38, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_CC430F5147, "CC430F5147"}, // CC430F5147 {{0x39, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_CC430F5145, "CC430F5145"}, // CC430F5145 {{0x3A, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_CC430F5143, "CC430F5143"}, // CC430F5143 {{0x3B, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_CC430F5125, "CC430F5125"}, // CC430F5125 {{0x3C, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_CC430F5123, "CC430F5123"}, // CC430F5123 {{0x6D, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6723, "MSP430F6724"}, // MSP430F6724 {{0x6E, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6723, "MSP430F6725"}, // MSP430F6725 {{0x6F, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6723, "MSP430F6726"}, // MSP430F6726 {{0x6A, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6736, "MSP430F6734"}, // MSP430F6734 {{0x6B, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6736, "MSP430F6735"}, // MSP430F6735 {{0x6C, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6736, "MSP430F6736"}, // MSP430F6736 {{0x25, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5333, "MSP430F5333"}, // MSP430F5333 {{0x27, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5335, "MSP430F5335"}, // MSP430F5335 {{0x28, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5336, "MSP430F5336"}, // MSP430F5336 {{0x2A, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5338, "MSP430F5338"}, // MSP430F5338 {{0x1F, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6433, "MSP430F6433"}, // MSP430F6433 {{0x21, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6435, "MSP430F6435"}, // MSP430F6435 {{0x22, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6436, "MSP430F6436"}, // MSP430F6436 {{0x24, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F6438, "MSP430F6438"}, // MSP430F6438 {{0x01, 0x81 , -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5737, "MSP430FR5737"}, // MSP430FR5737 {{0x77, 0x81 , -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5736, "MSP430FR5736"}, // MSP430FR5736 {{0x00, 0x81 , -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5734, "MSP430FR5734"}, // MSP430FR5734 {{0x7F, 0x80 , -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5733, "MSP430FR5733"}, // MSP430FR5733 {{0x75, 0x81 , -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5732, "MSP430FR5732"}, // MSP430FR5732 {{0x7E, 0x80 , -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5731, "MSP430FR5731"}, // MSP430FR5731 {{0x79, 0x80 , -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5727, "MSP430FR5727"}, // MSP430FR5727 {{0x74, 0x81 , -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5726, "MSP430FR5726"}, // MSP430FR5726 {{0x73, 0x81 , -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5724, "MSP430FR5724"}, // MSP430FR5724 {{0x72, 0x81 , -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5723, "MSP430FR5723"}, // MSP430FR5723 {{0x71, 0x81 , -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5722, "MSP430FR5722"}, // MSP430FR5722 {{0x77, 0x80 , -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5721, "MSP430FR5721"}, // MSP430FR5721 {{0x50, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5228, "MSP430F5228"}, // MSP430F5528 {{0x4F, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5227, "MSP430F5227"}, // MSP430F5527 {{0x4C, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5224, "MSP430F5224"}, // MSP430F5524 {{0x4B, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5223, "MSP430F5223"}, // MSP430F5523 {{0x4A, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5222, "MSP430F5222"}, // MSP430F5522 {{0x47, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5219, "MSP430F5219"}, // MSP430F5519 {{0x46, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5218, "MSP430F5218"}, // MSP430F5518 {{0x45, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5217, "MSP430F5217"}, // MSP430F5517 {{0x42, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5229, "MSP430F5214"}, // MSP430F5529 {{0x41, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5229, "MSP430F5213"}, // MSP430F5529 {{0x40, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5229, "MSP430F5212"}, // MSP430F5529 {{0x29, 0x55, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430G2955, "MSP430G2955"}, // end of device table default return value {{ 0 , -1 , -1 , -1 , -1 , -1 , -1 , -1 , -1 }, -1, NULL} }; mspdebug-0.25/drivers/devicelist.h000066400000000000000000000135251313531517500172420ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * Copyright (C) 2012 Stanimir Bonev * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef DEVICELIST_H_ #define DEVICELIST_H_ #include struct device_table { uint8_t device_id_param[9]; uint16_t device_type_id; const char *name; }; typedef enum { DT_UNKNOWN_DEVICE = 0, DT_MSP430F11x1, DT_MSP430F11x1D, DT_MSP430F133, DT_MSP430F135, DT_MSP430F147, DT_MSP430F148, DT_MSP430F149, DT_MSP430F413P, DT_MSP430F41xC, DT_MSP430F11x1A, DT_MSP430F12x, DT_MSP430F43x, DT_MSP430F44x, DT_MSP430F12x2, DT_MSP430F11x2, DT_MSP430F12x2C, DT_PMS430F16x, DT_MSP430FE423, DT_MSP430FE425, DT_MSP430FE427, DT_MSP430F423, DT_MSP430F425, DT_MSP430F427, DT_MSP430FW42x, DT_MSP430F4230, DT_MSP430F4250, DT_MSP430F42x0, DT_MSP430F155, DT_MSP430F156, DT_MSP430F157, DT_MSP430F167, DT_MSP430F168, DT_MSP430F169, DT_MSP430F1610, DT_MSP430F1611, DT_MSP430F1612, DT_MSP430FG43x, DT_MSP430FG4619, DT_MSP430F21x1, DT_TMS430F1390, DT_TMS430F1250, DT_TMS430C1250, DT_TMS430EMU, DT_MSP430F20x3, DT_MSP430F20x2, DT_MSP430F20x1, DT_MSP430F2234, DT_MSP430F2254, DT_MSP430F2274, DT_MSP430FG4618, DT_MSP430F2330, DT_MSP430F2350, DT_MSP430F2370, DT_MSP430F2232, DT_MSP430F2252, DT_MSP430F2272, DT_MSP430F2619, DT_MSP430F2618, DT_MSP430F2419, DT_MSP430F2418, DT_MSP430FE423A, DT_MSP430FE425A, DT_MSP430FE427A, DT_MSP430F423A, DT_MSP430F425A, DT_MSP430F427A, DT_MSP430F4783, DT_MSP430F4784, DT_MSP430F4793, DT_MSP430F4794, DT_MSP430F249, DT_MSP430F248, DT_MSP430F247, DT_MSP430F235, DT_MSP430F2491, DT_MSP430F2481, DT_MSP430F2471, DT_MSP430F233, DT_MSP430F2410, DT_MSP430F2132, DT_MSP430F2122, DT_MSP430F2112, DT_XMS430F5438, DT_MSP430F5438, DT_MSP430F5436, DT_MSP430F5419, DT_MSP430FE4232, DT_MSP430FE42x2, DT_MSP430F5437, DT_MSP430F5435, DT_MSP430F5418, DT_MSP430FG4250, DT_MSP430FG42x0, DT_MSP430FE4272, DT_MSP430FG477, DT_MSP430FG478, DT_MSP430FG479, DT_MSP430F477, DT_MSP430F478, DT_MSP430F479, DT_MSP430F47197, DT_MSP430F47187, DT_MSP430F47177, DT_MSP430F47167, DT_MSP430F47196, DT_MSP430F47186, DT_MSP430F47176, DT_MSP430F47166, DT_MSP430F4152, DT_MSP430F4132, DT_CC430F6137, DT_CC430F6135, DT_CC430F6127, DT_CC430F6126, DT_CC430F6125, DT_CC430F5137, DT_CC430F5135, DT_CC430F5133, DT_MSP430F5513, DT_MSP430F5514, DT_MSP430F5515, DT_MSP430F5517, DT_MSP430F5519, DT_MSP430F5521, DT_MSP430F5522, DT_MSP430F5524, DT_MSP430F5525, DT_MSP430F5526, DT_MSP430F5527, DT_MSP430F5528, DT_MSP430F5529, DT_MSP430F5438A, DT_MSP430F5436A, DT_MSP430F5419A, DT_MSP430F5437A, DT_MSP430F5435A, DT_MSP430F5418A, DT_MSP430F5510, DT_MSP430F5131, DT_MSP430F5132, DT_MSP430F5151, DT_MSP430F5152, DT_MSP430F5171, DT_MSP430F5172, DT_MSP430F5630, DT_MSP430F5631, DT_MSP430F5632, DT_MSP430F5633, DT_MSP430F5634, DT_MSP430F5635, DT_MSP430F5636, DT_MSP430F5637, DT_MSP430F5638, DT_MSP430F6630, DT_MSP430F6631, DT_MSP430F6632, DT_MSP430F6633, DT_MSP430F6634, DT_MSP430F6635, DT_MSP430F6636, DT_MSP430F6637, DT_MSP430F6638, DT_MSP430FR5739, DT_MSP430L092, DT_MSP430F6700, DT_MSP430F6701, DT_MSP430F6702, DT_MSP430F6703, DT_MSP430F6720, DT_MSP430F6721, DT_MSP430F6722, DT_MSP430F6723, DT_MSP430F6730, DT_MSP430F6731, DT_MSP430F6732, DT_MSP430F6733, DT_MSP430F5509, DT_MSP430F5508, DT_MSP430F5507, DT_MSP430F5506, DT_MSP430F5505, DT_MSP430F5504, DT_MSP430F5503, DT_MSP430F5502, DT_MSP430F5501, DT_MSP430F5500, DT_MSP430F12x2New, DT_MSP430F5310, DT_MSP430F5309, DT_MSP430F5308, DT_MSP430F5304, DT_MSP430AFE253, DT_MSP430F5329, DT_MSP430F5328, DT_MSP430F5327, DT_MSP430F5326, DT_MSP430F5325, DT_MSP430F5324, DT_MSP430G2452, DT_MSP430F5342, DT_MSP430F5341, DT_MSP430F5340, DT_MSP430FW429, DT_MSP430F6659, DT_MSP430F6658, DT_MSP430F6459, DT_MSP430F6458, DT_MSP430F6457, DT_MSP430F5659, DT_MSP430F5658, DT_MSP430F5359, DT_MSP430F5358, DT_MSP430F5357, DT_MSP430G2553, DT_MSP430AFE233, DT_MSP430AFE223, DT_MSP430AFE252, DT_MSP430AFE232, DT_MSP430AFE222, DT_MSP430AFE251, DT_MSP430AFE231, DT_MSP430AFE221, DT_MSP430AFE250, DT_MSP430AFE230, DT_MSP430AFE220, DT_MSP430F5229, DT_MSP430FR5738, DT_MSP430FR5735, DT_MSP430FR5730, DT_MSP430FR5729, DT_MSP430FR5728, DT_MSP430FR5725, DT_MSP430FR5720, DT_MSP430FR5969, DT_CC430F6147, DT_CC430F6145, DT_CC430F6143, DT_CC430F5147, DT_CC430F5145, DT_CC430F5143, DT_CC430F5125, DT_CC430F5123, DT_MSP430F6724, DT_MSP430F6725, DT_MSP430F6726, DT_MSP430F6734, DT_MSP430F6735, DT_MSP430F6736, DT_MSP430F5333, DT_MSP430F5335, DT_MSP430F5336, DT_MSP430F5338, DT_MSP430F6433, DT_MSP430F6435, DT_MSP430F6436, DT_MSP430F6438, DT_MSP430FR5737, DT_MSP430FR5736, DT_MSP430FR5734, DT_MSP430FR5733, DT_MSP430FR5732, DT_MSP430FR5731, DT_MSP430FR5727, DT_MSP430FR5726, DT_MSP430FR5724, DT_MSP430FR5723, DT_MSP430FR5722, DT_MSP430FR5721, DT_MSP430F5228, DT_MSP430F5227, DT_MSP430F5224, DT_MSP430F5223, DT_MSP430F5222, DT_MSP430F5219, DT_MSP430F5218, DT_MSP430F5217, DT_MSP430F5214, DT_MSP430F5213, DT_MSP430F5212, DT_MSP430G2955, } devicetype_t; /* Mapping between device types and identification bytes. */ extern const struct device_table sdeviceID[]; #endif mspdebug-0.25/drivers/eem_defs.h000066400000000000000000000162641313531517500166610ustar00rootroot00000000000000/* * EEM_defs.h * * * * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _EEM_DEFS_H_ #define _EEM_DEFS_H_ #define FALSE 0 #define TRUE 1 #define WRITE 0 #define READ 1 #define TRIGFLAG 0x8E #define EEMVER 0x86 /* Definition for EEM General Clock Control Register */ #define GENCLKCTRL 0x88 /* Definitions for EEM General Clock Control Register */ #define MCLK_SEL0 0x0000 #define SMCLK_SEL0 0x0000 #define ACLK_SEL0 0x0000 #define MCLK_SEL3 0x6000 #define SMCLK_SEL3 0x0C00 #define ACLK_SEL3 0x0180 #define STOP_MCLK 0x0008 #define STOP_SMCLK 0x0004 #define STOP_ACLK 0x0002 /* Definition for EEM Module Clock Control Register 0 */ #define MODCLKCTRL0 0x8A /* Definition for EEM General Debug Control Register */ #define GENCTRL 0x82 /* Definitions for EEM General Debug Control Register */ #define EEM_EN 0x0001 #define CLEAR_STOP 0x0002 #define EMU_CLK_EN 0x0004 #define EMU_FEAT_EN 0x0008 #define DEB_TRIG_LATCH 0x0010 #define EEM_RST 0x0040 #define E_STOPPED 0x0080 /* Defintions for Trigger Block base addresses */ #define TB0 0x0000 #define TB1 0x0008 #define TB2 0x0010 #define TB3 0x0018 #define TB4 0x0020 #define TB5 0x0028 #define TB6 0x0030 #define TB7 0x0038 #define TB8 0x0040 #define TB9 0x0048 /* Definitions for Trigger Block register addresses */ #define MBTRIGxVAL 0x0000 #define MBTRIGxCTL 0x0002 #define MBTRIGxMSK 0x0004 #define MBTRIGxCMB 0x0006 /* Definitions for MAB/MDB Trigger Control Register */ #define MAB 0x0000 #define MDB 0x0001 #define TRIG_0 0x0000 // Instruction Fetch #define TRIG_1 0x0002 // Instruction Fetch Hold #define TRIG_2 0x0004 // No Instruction Fetch #define TRIG_3 0x0006 // Don't care #define TRIG_4 0x0020 // No Instruction Fetch & Read #define TRIG_5 0x0022 // No Instruction Fetch & Write #define TRIG_6 0x0024 // Read #define TRIG_7 0x0026 // Write #define TRIG_8 0x0040 // No Instruction Fetch & No DMA Access #define TRIG_9 0x0042 // DMA Access (Read or Write) #define TRIG_A 0x0044 // No DMA Access #define TRIG_B 0x0046 // Write & No DMA Access #define TRIG_C 0x0060 // No Instruction Fetch & Read & No DMA Access #define TRIG_D 0x0062 // Read & No DMA Access #define TRIG_E 0x0064 // Read & DMA Access #define TRIG_F 0x0066 // Write & DMA Access #define CMP_EQUAL 0x0000 #define CMP_GREATER 0x0008 #define CMP_LESS 0x0010 #define CMP_NOT_EQUAL 0x0018 /* Definitions for MAB/MDB Trigger Mask Register */ #define NO_MASK 0x00000 #define MASK_ALL 0xFFFFF #define MASK_XADDR 0xF0000 #define MASK_HBYTE 0x0FF00 #define MASK_LBYTE 0x000FF /* Definitions for MAB/MDB Combination Register & Reaction Registers*/ #define EN0 0x0001 #define EN1 0x0002 #define EN2 0x0004 #define EN3 0x0008 #define EN4 0x0010 #define EN5 0x0020 #define EN6 0x0040 #define EN7 0x0080 #define EN8 0x0100 #define EN9 0x0200 #define STOR_CTL 0x9E /* Definitions for State Storage Control Register */ #define VAR_WATCH0 0x0000 // Two #define VAR_WATCH1 0x2000 // Four #define VAR_WATCH2 0x4000 // Six #define VAR_WATCH3 0x6000 // Eight #define STOR_FULL 0x0200 #define STOR_WRIT 0x0100 #define STOR_TEST 0x0080 #define STOR_RST 0x0040 #define STOR_STOP_ON_TRIG 0x0020 #define STOR_START_ON_TRIG 0x0010 #define STOR_ONE_SHOT 0x0008 #define STOR_MODE0 0x0000 // Store on enabled triggers #define STOR_MODE1 0x0002 // Store on Instruction Fetch #define STOR_MODE2 0x0004 // Variable Watch #define STOR_MODE3 0x0006 // Store all bus cycles #define STOR_EN 0x0001 // enable state storage /* Definitions for Reaction Registers */ #define STOR_REACT 0x98 #define BREAKREACT 0x80 #define EVENT_REACT 0x94 #define EVENT_CTRL 0x96 #define EVENT_TRIG 0x0001 /* Definitions for Cycle Counters */ #define CCNT0CTL 0xB0 #define CCNT0L 0xB2 #define CCNT0H 0xB4 #define CCNT1CTL 0xB8 #define CCNT1L 0xBA #define CCNT1H 0xBC #define CCNT1REACT 0xBE /* Definitions for Cycle Counter Control Register */ #define CCNTMODE0 0x0000 // Counter stopped #define CCNTMODE1 0x0001 // Increment on reaction #define CCNTMODE4 0x0004 // Increment on instruction fetch cycles #define CCNTMODE5 0x0005 // Increment on all bus cycles (including DMA cycles) #define CCNTMODE6 0x0006 // Increment on all CPU bus cycles (excluding DMA cycles) #define CCNTMODE7 0x0007 // Increment on all DMA bus cycles #define CCNT_RST 0x0040 #define CCNTSTT0 0x0000 // Start when CPU released from JTAG/EEM #define CCNTSTT1 0x0100 // Start on reaction CCNT1REACT (only CCNT1) #define CCNTSTT2 0x0200 // Start when other (second) counter is started (only if available) #define CCNTSTT3 0x0300 // Start immediately #define CCNTSTP0 0x0000 // Stop when CPU is stopped by EEM or under JTAG control #define CCNTSTP1 0x0400 // Stop on reaction CCNT1REACT (only CCNT1) #define CCNTSTP2 0x0800 // Stop when other (second) counter is started (only if available) #define CCNTSTP3 0x0C00 // No stop event #define CCNTCLR0 0x0000 // No clear event #define CCNTCLR1 0x1000 // Clear on reaction CCNT1REACT (only CCNT1) #define CCNTCLR2 0x2000 // Clear when other (second) counter is started (only if available) #define CCNTCLR3 0x3000 // Reserved #define GCC_NONE 0x0000 // No clock control #define GCC_STANDARD 0x0001 // Standard clock control #define GCC_EXTENDED 0x0002 // Extended clock control #endif mspdebug-0.25/drivers/fet.c000066400000000000000000000143751313531517500156640ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009-2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * * Various constants and tables come from uif430, written by Robert * Kavaler (kavaler@diva.com). This is available under the same license * as this program, from www.relavak.com. */ #include #include "fet.h" #include "fet_proto.h" #include "fet_core.h" #include "output.h" #include "comport.h" #include "ftdi.h" #include "rf2500.h" #include "ti3410.h" #include "cp210x.h" #include "cdc_acm.h" #include "obl.h" static device_t fet_open_rf2500(const struct device_args *args) { transport_t trans; if (args->flags & DEVICE_FLAG_TTY) { printc_err("This driver does not support TTY devices.\n"); return NULL; } trans = rf2500_open(args->path, args->requested_serial); if (!trans) return NULL; return fet_open(args, FET_PROTO_SEPARATE_DATA, trans, 0, &device_rf2500); } const struct device_class device_rf2500 = { .name = "rf2500", .help = "eZ430-RF2500 devices. Only USB connection is supported.", .open = fet_open_rf2500, .destroy = fet_destroy, .readmem = fet_readmem, .writemem = fet_writemem, .erase = fet_erase, .getregs = fet_getregs, .setregs = fet_setregs, .ctl = fet_ctl, .poll = fet_poll, .getconfigfuses = NULL }; static device_t fet_open_olimex_iso_mk2(const struct device_args *args) { transport_t trans; uint32_t version; if (args->flags & DEVICE_FLAG_TTY) trans = comport_open(args->path, 115200); else trans = cdc_acm_open(args->path, args->requested_serial, 115200, 0x15ba, 0x0100); if (!trans) return NULL; if (args->require_fwupdate) { if (obl_update(trans, args->require_fwupdate) < 0) { trans->ops->destroy(trans); return NULL; } obl_reset(trans); trans->ops->destroy(trans); printc("Resetting, please wait...\n"); delay_s(15); if (args->flags & DEVICE_FLAG_TTY) trans = comport_open(args->path, 115200); else trans = cdc_acm_open(args->path, args->requested_serial, 115200, 0x15ba, 0x0100); if (!trans) return NULL; } if (!obl_get_version(trans, &version)) printc_dbg("Olimex firmware version: %x\n", version); return fet_open(args, FET_PROTO_NOLEAD_SEND | FET_PROTO_EXTRA_RECV, trans, FET_FORCE_RESET | FET_IDENTIFY_NEW, &device_olimex_iso_mk2); } const struct device_class device_olimex_iso_mk2 = { .name = "olimex-iso-mk2", .help = "Olimex MSP430-JTAG-ISO-MK2.", .open = fet_open_olimex_iso_mk2, .destroy = fet_destroy, .readmem = fet_readmem, .writemem = fet_writemem, .erase = fet_erase, .getregs = fet_getregs, .setregs = fet_setregs, .ctl = fet_ctl, .poll = fet_poll, .getconfigfuses = NULL }; static device_t fet_open_olimex(const struct device_args *args) { transport_t trans; if (args->flags & DEVICE_FLAG_TTY) trans = comport_open(args->path, 115200); else trans = cdc_acm_open(args->path, args->requested_serial, 115200, 0x15ba, 0x0031); if (!trans) return NULL; return fet_open(args, FET_PROTO_NOLEAD_SEND | FET_PROTO_EXTRA_RECV, trans, FET_IDENTIFY_NEW | FET_FORCE_RESET, &device_olimex); } const struct device_class device_olimex = { .name = "olimex", .help = "Olimex MSP-JTAG-TINY.", .open = fet_open_olimex, .destroy = fet_destroy, .readmem = fet_readmem, .writemem = fet_writemem, .erase = fet_erase, .getregs = fet_getregs, .setregs = fet_setregs, .ctl = fet_ctl, .poll = fet_poll, .getconfigfuses = NULL }; static device_t fet_open_olimex_v1(const struct device_args *args) { transport_t trans; if (args->flags & DEVICE_FLAG_TTY) trans = comport_open(args->path, 500000); else trans = cp210x_open(args->path, args->requested_serial, 500000, 0x15ba, 0x0002); if (!trans) return NULL; return fet_open(args, FET_PROTO_NOLEAD_SEND | FET_PROTO_EXTRA_RECV, trans, FET_IDENTIFY_NEW, &device_olimex_v1); } const struct device_class device_olimex_v1 = { .name = "olimex-v1", .help = "Olimex MSP-JTAG-TINY (V1).", .open = fet_open_olimex_v1, .destroy = fet_destroy, .readmem = fet_readmem, .writemem = fet_writemem, .erase = fet_erase, .getregs = fet_getregs, .setregs = fet_setregs, .ctl = fet_ctl, .poll = fet_poll }; static device_t fet_open_olimex_iso(const struct device_args *args) { transport_t trans; if (args->flags & DEVICE_FLAG_TTY) trans = comport_open(args->path, 200000); else trans = ftdi_open(args->path, args->requested_serial, 0x15ba, 0x0008, 200000); if (!trans) return NULL; return fet_open(args, FET_PROTO_NOLEAD_SEND | FET_PROTO_EXTRA_RECV, trans, FET_IDENTIFY_NEW, &device_olimex_iso); } const struct device_class device_olimex_iso = { .name = "olimex-iso", .help = "Olimex MSP-JTAG-ISO.", .open = fet_open_olimex_iso, .destroy = fet_destroy, .readmem = fet_readmem, .writemem = fet_writemem, .erase = fet_erase, .getregs = fet_getregs, .setregs = fet_setregs, .ctl = fet_ctl, .poll = fet_poll, .getconfigfuses = NULL }; static device_t fet_open_uif(const struct device_args *args) { transport_t trans; if (args->flags & DEVICE_FLAG_TTY) trans = comport_open(args->path, 460800); else trans = ti3410_open(args->path, args->requested_serial); if (!trans) return NULL; return fet_open(args, 0, trans, 0, &device_uif); } const struct device_class device_uif = { .name = "uif", .help = "TI FET430UIF and compatible devices (e.g. eZ430).", .open = fet_open_uif, .destroy = fet_destroy, .readmem = fet_readmem, .writemem = fet_writemem, .erase = fet_erase, .getregs = fet_getregs, .setregs = fet_setregs, .ctl = fet_ctl, .poll = fet_poll, .getconfigfuses = NULL }; mspdebug-0.25/drivers/fet.h000066400000000000000000000022171313531517500156610ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef FET_H_ #define FET_H_ #include "device.h" extern const struct device_class device_rf2500; extern const struct device_class device_olimex; extern const struct device_class device_olimex_v1; extern const struct device_class device_olimex_iso; extern const struct device_class device_olimex_iso_mk2; extern const struct device_class device_uif; #endif mspdebug-0.25/drivers/fet3.c000066400000000000000000000144331313531517500157420ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include "util/ctrlc.h" #include "dis.h" #include "output.h" #include "comport.h" #include "cdc_acm.h" #include "fet3.h" #include "chipinfo.h" #include "v3hil.h" struct fet3 { struct device base; struct v3hil hil; }; static int fet3_readmem(device_t dev_base, address_t addr, uint8_t *mem, address_t len) { struct fet3 *fet = (struct fet3 *)dev_base; if (addr & 1) { uint8_t word[2]; if (v3hil_read(&fet->hil, addr - 1, word, 2) < 0) return -1; mem[0] = word[1]; addr++; len--; } while (len >= 2) { int r = 128; if (r > len) r = len; r = v3hil_read(&fet->hil, addr, mem, r & ~1); if (r < 0) return -1; addr += r; mem += r; len -= r; } if (len) { uint8_t word[2]; if (v3hil_read(&fet->hil, addr, word, 2) < 0) return -1; mem[0] = word[0]; addr++; len--; } return 0; } static int fet3_writemem(device_t dev_base, address_t addr, const uint8_t *mem, address_t len) { struct fet3 *fet = (struct fet3 *)dev_base; if (addr & 1) { uint8_t word[2]; if (v3hil_read(&fet->hil, addr - 1, word, 2) < 0) return -1; word[1] = mem[0]; if (v3hil_write(&fet->hil, addr - 1, word, 2) < 0) return -1; addr++; len--; } while (len >= 2) { int r = 128; if (r > len) r = len; r = v3hil_write(&fet->hil, addr, mem, r & ~1); if (r < 0) return -1; addr += r; mem += r; len -= r; } if (len) { uint8_t word[2]; if (v3hil_read(&fet->hil, addr, word, 2) < 0) return -1; word[0] = mem[0]; if (v3hil_write(&fet->hil, addr, word, 2) < 0) return -1; addr++; len--; } return 0; } static int fet3_setregs(device_t dev_base, const address_t *regs) { struct fet3 *fet = (struct fet3 *)dev_base; memcpy(fet->hil.regs, regs, sizeof(fet->hil.regs)); return -1; } static int fet3_getregs(device_t dev_base, address_t *regs) { struct fet3 *fet = (struct fet3 *)dev_base; memcpy(regs, fet->hil.regs, sizeof(fet->hil.regs)); return 0; } static int fet3_ctl(device_t dev_base, device_ctl_t type) { struct fet3 *fet = (struct fet3 *)dev_base; switch (type) { case DEVICE_CTL_RESET: if (v3hil_sync(&fet->hil) < 0) return -1; return v3hil_update_regs(&fet->hil); case DEVICE_CTL_RUN: if (v3hil_flush_regs(&fet->hil) < 0) return -1; return v3hil_context_restore(&fet->hil, 0); case DEVICE_CTL_HALT: if (v3hil_context_save(&fet->hil) < 0) return -1; return v3hil_update_regs(&fet->hil); case DEVICE_CTL_STEP: if (v3hil_flush_regs(&fet->hil) < 0) return -1; if (v3hil_single_step(&fet->hil) < 0) return -1; return v3hil_update_regs(&fet->hil); default: printc_err("fet3: unsupported operation\n"); return -1; } return 0; } static device_status_t fet3_poll(device_t dev_base) { /* We don't support breakpoints yet, so there's nothing to poll * for. */ if(delay_ms(500) < 0) return DEVICE_STATUS_INTR; return DEVICE_STATUS_RUNNING; } static int fet3_erase(device_t dev_base, device_erase_type_t type, address_t addr) { struct fet3 *fet = (struct fet3 *)dev_base; if (type == DEVICE_ERASE_ALL) { printc_err("fet3: mass erase is not supported\n"); return -1; } return v3hil_erase(&fet->hil, (type == DEVICE_ERASE_MAIN) ? ADDRESS_NONE : addr); } static int debug_init(struct fet3 *fet, const struct device_args *args) { if (v3hil_comm_init(&fet->hil) < 0) return -1; printc_dbg("Set VCC: %d mV\n", args->vcc_mv); if (v3hil_set_vcc(&fet->hil, args->vcc_mv) < 0) return -1; printc_dbg("Starting interface...\n"); if (v3hil_start_jtag(&fet->hil, (args->flags & DEVICE_FLAG_JTAG) ? V3HIL_JTAG_JTAG : V3HIL_JTAG_SPYBIWIRE) < 0) return -1; if (args->forced_chip_id) { fet->hil.chip = chipinfo_find_by_name(args->forced_chip_id); if (!fet->hil.chip) { printc_err("fet3: unknown chip: %s\n", args->forced_chip_id); goto fail_stop_jtag; } } else { if (v3hil_identify(&fet->hil) < 0) goto fail_stop_jtag; } fet->base.chip = fet->hil.chip; if (v3hil_configure(&fet->hil) < 0) goto fail_stop_jtag; if (v3hil_update_regs(&fet->hil) < 0) goto fail_stop_jtag; return 0; fail_stop_jtag: v3hil_stop_jtag(&fet->hil); return -1; } static device_t fet3_open(const struct device_args *args) { struct fet3 *fet; transport_t trans; if (args->flags & DEVICE_FLAG_TTY) trans = comport_open(args->path, 460800); else trans = cdc_acm_open(args->path, args->requested_serial, 460800, 0x2047, 0x0013); if (!trans) { printc_err("fet3: failed to open transport\n"); return NULL; } fet = malloc(sizeof(*fet)); if (!fet) { printc_err("fet3: malloc: %s\n", last_error()); trans->ops->destroy(trans); return NULL; } memset(fet, 0, sizeof(*fet)); fet->base.type = &device_ezfet; /* Breakpoints aren't supported yet */ fet->base.max_breakpoints = 0; v3hil_init(&fet->hil, trans, 0); if (debug_init(fet, args) < 0) { trans->ops->destroy(trans); free(fet); return NULL; } return &fet->base; } static void fet3_destroy(device_t dev_base) { struct fet3 *fet = (struct fet3 *)dev_base; transport_t tr = fet->hil.hal.trans; v3hil_flush_regs(&fet->hil); v3hil_context_restore(&fet->hil, 1); v3hil_stop_jtag(&fet->hil); tr->ops->destroy(tr); free(fet); } const struct device_class device_ezfet = { .name = "ezfet", .help = "Texas Instruments eZ-FET", .open = fet3_open, .destroy = fet3_destroy, .readmem = fet3_readmem, .writemem = fet3_writemem, .getregs = fet3_getregs, .setregs = fet3_setregs, .ctl = fet3_ctl, .poll = fet3_poll, .erase = fet3_erase, .getconfigfuses = NULL }; mspdebug-0.25/drivers/fet3.h000066400000000000000000000016401313531517500157430ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef FET3_H_ #define FET3_H_ #include "device.h" /* eZ-FET */ extern const struct device_class device_ezfet; #endif mspdebug-0.25/drivers/fet_core.c000066400000000000000000000622461313531517500166740ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009-2012 Daniel Beer * Copyright (C) 2012 Stanimir Bonev * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * * Various constants and tables come from uif430, written by Robert * Kavaler (kavaler@diva.com). This is available under the same license * as this program, from www.relavak.com. */ #include #include #include #include #include #include #include "util.h" #include "fet.h" #include "fet_core.h" #include "fet_error.h" #include "fet_proto.h" #include "fet_db.h" #include "output.h" #include "opdb.h" #include "ctrlc.h" #include "fet_olimex_db.h" #include "devicelist.h" struct fet_device { struct device base; int version; int fet_flags; int poll_enable; struct fet_proto proto; fperm_t active_fperm; }; /********************************************************************** * FET command codes. * * These come from uif430 by Robert Kavaler (kavaler@diva.com). * www.relavak.com */ #define C_INITIALIZE 0x01 #define C_CLOSE 0x02 #define C_IDENTIFY 0x03 #define C_DEVICE 0x04 #define C_CONFIGURE 0x05 #define C_VCC 0x06 #define C_RESET 0x07 #define C_READREGISTERS 0x08 #define C_WRITEREGISTERS 0x09 #define C_READREGISTER 0x0a #define C_WRITEREGISTER 0x0b #define C_ERASE 0x0c #define C_READMEMORY 0x0d #define C_WRITEMEMORY 0x0e #define C_FASTFLASHER 0x0f #define C_BREAKPOINT 0x10 #define C_RUN 0x11 #define C_STATE 0x12 #define C_SECURE 0x13 #define C_VERIFYMEMORY 0x14 #define C_FASTVERIFYMEMORY 0x15 #define C_ERASECHECK 0x16 #define C_EEMOPEN 0x17 #define C_EEMREADREGISTER 0x18 #define C_EEMREADREGISTERTEST 0x19 #define C_EEMWRITEREGISTER 0x1a #define C_EEMCLOSE 0x1b #define C_ERRORNUMBER 0x1c #define C_GETCURVCCT 0x1d #define C_GETEXTVOLTAGE 0x1e #define C_FETSELFTEST 0x1f #define C_FETSETSIGNALS 0x20 #define C_FETRESET 0x21 #define C_READI2C 0x22 #define C_WRITEI2C 0x23 #define C_ENTERBOOTLOADER 0x24 #define C_IDENT1 0x28 #define C_IDENT2 0x29 #define C_IDENT3 0x2b #define C_CMM_PARAM 0x36 #define C_CMM_CTRL 0x37 #define C_CMM_READ 0x38 /* Constants for parameters of various FET commands */ #define FET_CONFIG_VERIFICATION 0 #define FET_CONFIG_EMULATION 1 #define FET_CONFIG_CLKCTRL 2 #define FET_CONFIG_MCLKCTRL 3 #define FET_CONFIG_FLASH_TESET 4 #define FET_CONFIG_FLASH_LOCK 5 #define FET_CONFIG_PROTOCOL 8 #define FET_CONFIG_UNLOCK_BSL 11 #define FET_RUN_FREE 1 #define FET_RUN_STEP 2 #define FET_RUN_BREAKPOINT 3 #define FET_RESET_PUC 0x01 #define FET_RESET_RST 0x02 #define FET_RESET_VCC 0x04 #define FET_RESET_ALL 0x07 #define FET_ERASE_SEGMENT 0 #define FET_ERASE_MAIN 1 #define FET_ERASE_ALL 2 #define FET_POLL_RUNNING 0x01 #define FET_POLL_BREAKPOINT 0x02 /********************************************************************** * MSP430 high-level control functions */ static void show_dev_info(const char *name, const struct fet_device *dev) { printc_dbg("Device: %s\n", name); printc_dbg("Number of breakpoints: %d\n", dev->base.max_breakpoints); } static int identify_old(struct fet_device *dev) { char idtext[64]; if (fet_proto_xfer(&dev->proto, C_IDENTIFY, NULL, 0, 2, 70, 0) < 0) return -1; if (dev->proto.datalen < 0x26) { printc_err("fet: missing info\n"); return -1; } memcpy(idtext, dev->proto.data + 4, 32); idtext[32] = 0; dev->base.max_breakpoints = LE_WORD(dev->proto.data, 0x2a); show_dev_info(idtext, dev); return 0; } static int identify_new(struct fet_device *dev, const char *force_id) { const struct fet_db_record *r; if (fet_proto_xfer(&dev->proto, C_IDENT1, NULL, 0, 2, 0, 0) < 0) { printc_err("fet: command C_IDENT1 failed\n"); return -1; } if (dev->proto.datalen < 2) { printc_err("fet: missing info\n"); return -1; } printc_dbg("Device ID: 0x%02x%02x\n", dev->proto.data[0], dev->proto.data[1]); if (force_id) r = fet_db_find_by_name(force_id); else r = fet_db_find_by_msg28(dev->proto.data, dev->proto.datalen); if (!r) { printc_err("fet: unknown device\n"); debug_hexdump("msg28_data:", dev->proto.data, dev->proto.datalen); return -1; } dev->base.max_breakpoints = r->msg29_data[0x14]; printc_dbg(" Code start address: 0x%x\n", LE_WORD(r->msg29_data, 0)); /* * The value at 0x02 seems to contain a "virtual code end * address". So this value seems to be useful only for * calculating the total ROM size. * * For example, as for the msp430f6736 with 128kb ROM, the ROM * is split into two areas: A "near" ROM, and a "far ROM". */ const uint32_t codeSize = LE_LONG(r->msg29_data, 0x02) - LE_WORD(r->msg29_data, 0) + 1; printc_dbg(" Code size : %u byte = %u kb\n", codeSize, codeSize / 1024); printc_dbg(" RAM start address: 0x%x\n", LE_WORD(r->msg29_data, 0x0c)); printc_dbg(" RAM end address: 0x%x\n", LE_WORD(r->msg29_data, 0x0e)); const uint16_t ramSize = LE_WORD(r->msg29_data, 0x0e) - LE_WORD(r->msg29_data, 0x0c) + 1; printc_dbg(" RAM size : %u byte = %u kb\n", ramSize, ramSize / 1024); show_dev_info(r->name, dev); if (fet_proto_xfer(&dev->proto, C_IDENT3, r->msg2b_data, r->msg2b_len, 0) < 0) printc_err("fet: warning: message C_IDENT3 failed\n"); if (fet_proto_xfer(&dev->proto, C_IDENT2, r->msg29_data, FET_DB_MSG29_LEN, 3, r->msg29_params[0], r->msg29_params[1], r->msg29_params[2]) < 0) { printc_err("fet: message C_IDENT2 failed\n"); return -1; } return 0; } static int identify_olimex(struct fet_device *dev, const char *force_id) { const struct fet_olimex_db_record *r; int db_indx; devicetype_t set_id = DT_UNKNOWN_DEVICE; devicetype_t dev_id = DT_UNKNOWN_DEVICE; uint8_t jtag_id; printc_dbg("Using Olimex identification procedure\n"); if (force_id) { db_indx = fet_olimex_db_find_by_name(force_id); if (db_indx < 0) { printc_err("fet: no such device: %s\n", force_id); return -1; } dev_id = set_id = fet_olimex_db_index_to_type(db_indx); } /* first try */ if (fet_proto_xfer(&dev->proto, C_IDENT1, NULL, 0, 3, set_id, set_id, 0) < 0 && (4 != dev->proto.error)) /* No device error */ { printc_err("fet: command C_IDENT1 failed\n"); return -1; } if (dev->proto.datalen < 19) { printc_err("fet: missing info\n"); return -1; } jtag_id = dev->proto.data[18]; /* find device in data base */ if (DT_UNKNOWN_DEVICE == dev_id) { db_indx = fet_olimex_db_identify(dev->proto.data); dev_id = fet_olimex_db_index_to_type(db_indx); } if ((DT_UNKNOWN_DEVICE == dev_id && 0x91 == jtag_id) || (4 == dev->proto.error)) { /* second try with magic pattern */ if (fet_proto_xfer(&dev->proto, C_IDENT1, NULL, 0, 3, set_id, dev_id, 0) < 0) { printc_err("fet: command C_IDENT1 with " "magic patern failed\n"); return -1; } db_indx = fet_olimex_db_identify(dev->proto.data); dev_id = fet_olimex_db_index_to_type(db_indx); } printc_dbg("Device ID: 0x%02x%02x\n", dev->proto.data[0], dev->proto.data[1]); if (DT_UNKNOWN_DEVICE == dev_id) { printc_err("fet: can't find device in DB\n"); return -1; } r = fet_db_get_record(dev_id); dev->base.max_breakpoints = r->msg29_data[0x14]; printc_dbg(" Code start address: 0x%x\n", LE_WORD(r->msg29_data, 0)); /* * The value at 0x02 seems to contain a "virtual code end * address". So this value seems to be useful only for * calculating the total ROM size. * * For example, as for the msp430f6736 with 128kb ROM, the ROM * is split into two areas: A "near" ROM, and a "far ROM". */ const uint32_t codeSize = LE_LONG(r->msg29_data, 0x02) - LE_WORD(r->msg29_data, 0) + 1; printc_dbg(" Code size : %u byte = %u kb\n", codeSize, codeSize / 1024); printc_dbg(" RAM start address: 0x%x\n", LE_WORD(r->msg29_data, 0x0c)); printc_dbg(" RAM end address: 0x%x\n", LE_WORD(r->msg29_data, 0x0e)); const uint16_t ramSize = LE_WORD(r->msg29_data, 0x0e) - LE_WORD(r->msg29_data, 0x0c) + 1; printc_dbg(" RAM size : %u byte = %u kb\n", ramSize, ramSize / 1024); show_dev_info(r->name, dev); if (fet_proto_xfer(&dev->proto, C_IDENT3, r->msg2b_data, r->msg2b_len, 0) < 0) printc_err("fet: warning: message C_IDENT3 failed\n"); if (fet_proto_xfer(&dev->proto, C_IDENT2, r->msg29_data, FET_DB_MSG29_LEN, 3, r->msg29_params[0], r->msg29_params[1], r->msg29_params[2]) < 0) { printc_err("fet: message C_IDENT2 failed\n"); return -1; } return 0; } static int is_new_olimex(const struct fet_device *dev) { if ((&device_olimex_iso_mk2 == dev->base.type) && (20000004 <= dev->version)) return 1; if (((&device_olimex == dev->base.type) || (&device_olimex_v1 == dev->base.type) || (&device_olimex_iso == dev->base.type)) && (10004003 <= dev->version)) return 1; return 0; } static int try_new(struct fet_device *dev, const char *force_id) { if (!identify_new(dev, force_id)) return 0; return identify_olimex(dev, force_id); } static int do_identify(struct fet_device *dev, const char *force_id) { if (is_new_olimex(dev)) return identify_olimex(dev, force_id); if (dev->fet_flags & FET_IDENTIFY_NEW) return try_new(dev, force_id); if (dev->version < 20300000) return identify_old(dev); return try_new(dev, force_id); } static void power_init(struct fet_device *dev) { if (fet_proto_xfer(&dev->proto, C_CMM_PARAM, NULL, 0, 0) < 0) { printc_err("warning: device does not support power " "profiling\n"); return; } if (dev->proto.argv[0] <= 0 || dev->proto.argv[0] <= 0) { printc_err("Bad parameters returned by C_CMM_PARAM: " "bufsize = %d bytes, %d us/sample\n", dev->proto.argv[1], dev->proto.argv[0]); return; } printc("Power profiling enabled: bufsize = %d bytes, %d us/sample\n", dev->proto.argv[1], dev->proto.argv[0]); printc_shell("power-sample-us %d\n", dev->proto.argv[0]); dev->base.power_buf = powerbuf_new(POWERBUF_DEFAULT_SAMPLES, dev->proto.argv[0]); if (!dev->base.power_buf) { printc_err("Failed to allocate memory for power profile\n"); return; } } static int power_start(struct fet_device *dev) { if (!dev->base.power_buf) return 0; if (fet_proto_xfer(&dev->proto, C_CMM_CTRL, NULL, 0, 1, 1) < 0) { printc_err("fet: failed to start power profiling, " "disabling\n"); powerbuf_free(dev->base.power_buf); dev->base.power_buf = NULL; return -1; } powerbuf_begin_session(dev->base.power_buf, time(NULL)); dev->poll_enable = 1; return 0; } static int power_end(struct fet_device *dev) { if (!dev->base.power_buf) return 0; powerbuf_end_session(dev->base.power_buf); dev->poll_enable = 0; if (fet_proto_xfer(&dev->proto, C_CMM_CTRL, NULL, 0, 1, 1) < 0) { printc_err("fet: failed to end power profiling\n"); return -1; } return 0; } static void shell_power(const uint8_t *data, int len) { while (len > 0) { int plen = 128; char text[256]; if (plen > len) plen = len; base64_encode(data, plen, text, sizeof(text)); printc_shell("power-samples %s\n", text); len -= plen; data += plen; } } static int power_poll(struct fet_device *dev) { address_t mab; address_t mab_samples[1024]; unsigned int cur_samples[1024]; unsigned int count = 0; int i; if (!dev->base.power_buf || !dev->poll_enable) return 0; if (fet_proto_xfer(&dev->proto, C_CMM_READ, NULL, 0, 0) < 0) { printc_err("fet: failed to fetch power data, disabling\n"); power_end(dev); powerbuf_free(dev->base.power_buf); dev->base.power_buf = NULL; dev->poll_enable = 0; return -1; } shell_power(dev->proto.data, dev->proto.datalen); mab = powerbuf_last_mab(dev->base.power_buf); for (i = 0; i + 3 < dev->proto.datalen; i += 4) { uint32_t s = LE_LONG(dev->proto.data, i); if (s & 0x80000000) { mab = s & 0x7fffffff; } else if (count + 1 < ARRAY_LEN(cur_samples)) { cur_samples[count] = s; mab_samples[count] = mab; count++; } } powerbuf_add_samples(dev->base.power_buf, count, cur_samples, mab_samples); return 0; } static int refresh_fperm(struct fet_device *dev) { fperm_t fp = opdb_read_fperm(); fperm_t delta = dev->active_fperm ^ fp; if (delta & FPERM_LOCKED_FLASH) { int opt = (fp & FPERM_LOCKED_FLASH) ? 1 : 0; printc_dbg("%s locked flash access\n", opt ? "Enabling" : "Disabling"); if (fet_proto_xfer(&dev->proto, C_CONFIGURE, NULL, 0, 2, FET_CONFIG_FLASH_LOCK, opt) < 0) { printc_err("fet: FET_CONFIG_FLASH_LOCK failed\n"); return -1; } } if (delta & FPERM_BSL) { int opt = (fp & FPERM_BSL) ? 1 : 0; printc_dbg("%s BSL access\n", opt ? "Enabling" : "Disabling"); if (fet_proto_xfer(&dev->proto, C_CONFIGURE, NULL, 0, 2, FET_CONFIG_UNLOCK_BSL, opt) < 0) { printc_err("fet: FET_CONFIG_UNLOCK_BSL failed\n"); return -1; } } dev->active_fperm = fp; return 0; } static int do_run(struct fet_device *dev, int type) { if (fet_proto_xfer(&dev->proto, C_RUN, NULL, 0, 2, type, 0) < 0) { printc_err("fet: failed to restart CPU\n"); return -1; } return 0; } int fet_erase(device_t dev_base, device_erase_type_t type, address_t addr) { struct fet_device *dev = (struct fet_device *)dev_base; int fet_erase_type = FET_ERASE_MAIN; if (fet_proto_xfer(&dev->proto, C_CONFIGURE, NULL, 0, 2, FET_CONFIG_CLKCTRL, 0x26) < 0) { printc_err("fet: config (1) failed\n"); return -1; } refresh_fperm(dev); switch (type) { case DEVICE_ERASE_MAIN: fet_erase_type = FET_ERASE_MAIN; addr = 0xfffe; break; case DEVICE_ERASE_SEGMENT: fet_erase_type = FET_ERASE_SEGMENT; break; case DEVICE_ERASE_ALL: fet_erase_type = FET_ERASE_ALL; addr = 0xfffe; break; default: printc_err("fet: unsupported erase type\n"); return -1; } if (fet_proto_xfer(&dev->proto, C_ERASE, NULL, 0, 3, fet_erase_type, addr, 1) < 0) { printc_err("fet: erase command failed\n"); return -1; } if (fet_proto_xfer(&dev->proto, C_RESET, NULL, 0, 3, FET_RESET_ALL, 0, 0) < 0) { printc_err("fet: reset failed\n"); return -1; } return 0; } device_status_t fet_poll(device_t dev_base) { struct fet_device *dev = (struct fet_device *)dev_base; if (fet_proto_xfer(&dev->proto, C_STATE, NULL, 0, 1, 0) < 0) { printc_err("fet: polling failed\n"); power_end(dev); return DEVICE_STATUS_ERROR; } if (dev->base.power_buf) power_poll(dev); else delay_ms(50); if (!(dev->proto.argv[0] & FET_POLL_RUNNING)) { power_end(dev); return DEVICE_STATUS_HALTED; } if (ctrlc_check()) return DEVICE_STATUS_INTR; return DEVICE_STATUS_RUNNING; } static int refresh_bps(struct fet_device *dev) { int i; int ret = 0; for (i = 0; i < dev->base.max_breakpoints; i++) { struct device_breakpoint *bp = &dev->base.breakpoints[i]; if ((bp->flags & DEVICE_BP_DIRTY) && bp->type == DEVICE_BPTYPE_BREAK) { uint16_t addr = bp->addr; if (!(bp->flags & DEVICE_BP_ENABLED)) addr = 0; if (fet_proto_xfer(&dev->proto, C_BREAKPOINT, NULL, 0, 2, i, addr) < 0) { printc_err("fet: failed to refresh " "breakpoint #%d\n", i); ret = -1; } else { bp->flags &= ~DEVICE_BP_DIRTY; } } } return ret; } int fet_ctl(device_t dev_base, device_ctl_t action) { struct fet_device *dev = (struct fet_device *)dev_base; switch (action) { case DEVICE_CTL_RESET: if (fet_proto_xfer(&dev->proto, C_RESET, NULL, 0, 3, FET_RESET_ALL, 0, 0) < 0) { printc_err("fet: reset failed\n"); return -1; } break; case DEVICE_CTL_RUN: if (refresh_bps(dev) < 0) printc_err("warning: fet: failed to refresh " "breakpoints\n"); power_start(dev); if (do_run(dev, FET_RUN_BREAKPOINT) < 0) { power_end(dev); return -1; } return 0; case DEVICE_CTL_HALT: power_end(dev); if (fet_proto_xfer(&dev->proto, C_STATE, NULL, 0, 1, 1) < 0) { printc_err("fet: failed to halt CPU\n"); return -1; } break; case DEVICE_CTL_STEP: if (do_run(dev, FET_RUN_STEP) < 0) return -1; for (;;) { device_status_t status = fet_poll(dev_base); if (status == DEVICE_STATUS_ERROR || status == DEVICE_STATUS_INTR) return -1; if (status == DEVICE_STATUS_HALTED) break; } break; case DEVICE_CTL_SECURE: if (fet_proto_xfer(&dev->proto, C_SECURE, NULL, 0, 0) < 0) { printc_err("fet: failed to secure device\n"); return -1; } break; } return 0; } void fet_destroy(device_t dev_base) { struct fet_device *dev = (struct fet_device *)dev_base; if (dev->fet_flags & FET_SKIP_CLOSE) { printc_dbg("Skipping close procedure\n"); } else { /* The second argument to C_RESET is a boolean which * specifies whether the chip should run or not. The * final argument is also a boolean. Setting it non-zero * is required to get the RST pin working on the G2231, * but it must be zero on the FR5739, or else the value * of the reset vector gets set to 0xffff at the start * of the next JTAG session. */ if (fet_proto_xfer(&dev->proto, C_RESET, NULL, 0, 3, FET_RESET_ALL, 1, !device_is_fram(dev_base)) < 0) printc_err("fet: final reset failed\n"); if (fet_proto_xfer(&dev->proto, C_CLOSE, NULL, 0, 1, 0) < 0) printc_err("fet: close command failed\n"); if (dev->base.power_buf) powerbuf_free(dev->base.power_buf); } dev->proto.transport->ops->destroy(dev->proto.transport); free(dev); } static int read_byte(struct fet_device *dev, address_t addr, uint8_t *out) { address_t base = addr & ~1; if (fet_proto_xfer(&dev->proto, C_READMEMORY, NULL, 0, 2, base, 2) < 0) { printc_err("fet: failed to read byte from 0x%04x\n", addr); return -1; } *out = dev->proto.data[addr & 1]; return 0; } static int write_byte(struct fet_device *dev, address_t addr, uint8_t value) { uint8_t buf[2]; address_t base = addr & ~1; if (fet_proto_xfer(&dev->proto, C_READMEMORY, NULL, 0, 2, base, 2) < 0) { printc_err("fet: failed to read byte from 0x%04x\n", addr); return -1; } buf[0] = dev->proto.data[0]; buf[1] = dev->proto.data[1]; buf[addr & 1] = value; if (fet_proto_xfer(&dev->proto, C_WRITEMEMORY, buf, 2, 1, base) < 0) { printc_err("fet: failed to write byte from 0x%04x\n", addr); return -1; } return 0; } static int get_adjusted_block_size(void) { int block_size = opdb_get_numeric("fet_block_size") & ~1; if (block_size < 2) block_size = 2; if (block_size > FET_PROTO_MAX_BLOCK) block_size = FET_PROTO_MAX_BLOCK; return block_size; } int fet_readmem(device_t dev_base, address_t addr, uint8_t *buffer, address_t count) { struct fet_device *dev = (struct fet_device *)dev_base; int block_size = get_adjusted_block_size(); if (addr & 1) { if (read_byte(dev, addr, buffer) < 0) return -1; addr++; buffer++; count--; } while (count > 1) { int plen = count > block_size ? block_size : count; plen &= ~0x1; if (fet_proto_xfer(&dev->proto, C_READMEMORY, NULL, 0, 2, addr, plen) < 0) { printc_err("fet: failed to read " "from 0x%04x\n", addr); return -1; } if (dev->proto.datalen < plen) { printc_err("fet: short data: " "%d bytes\n", dev->proto.datalen); return -1; } memcpy(buffer, dev->proto.data, plen); buffer += plen; count -= plen; addr += plen; } if (count && read_byte(dev, addr, buffer) < 0) return -1; return 0; } int fet_writemem(device_t dev_base, address_t addr, const uint8_t *buffer, address_t count) { struct fet_device *dev = (struct fet_device *)dev_base; int block_size = get_adjusted_block_size(); refresh_fperm(dev); if (addr & 1) { if (write_byte(dev, addr, *buffer) < 0) return -1; addr++; buffer++; count--; } while (count > 1) { int plen = count > block_size ? block_size : count; int ret; plen &= ~0x1; ret = fet_proto_xfer(&dev->proto, C_WRITEMEMORY, buffer, plen, 1, addr); if (ret < 0) { printc_err("fet: failed to write to 0x%04x\n", addr); return -1; } buffer += plen; count -= plen; addr += plen; } if (count && write_byte(dev, addr, *buffer) < 0) return -1; return 0; } int fet_getregs(device_t dev_base, address_t *regs) { struct fet_device *dev = (struct fet_device *)dev_base; int i; if (fet_proto_xfer(&dev->proto, C_READREGISTERS, NULL, 0, 0) < 0) return -1; if (dev->proto.datalen < DEVICE_NUM_REGS * 4) { printc_err("fet: short reply (%d bytes)\n", dev->proto.datalen); return -1; } for (i = 0; i < DEVICE_NUM_REGS; i++) regs[i] = LE_LONG(dev->proto.data, i * 4); return 0; } int fet_setregs(device_t dev_base, const address_t *regs) { struct fet_device *dev = (struct fet_device *)dev_base; uint8_t buf[DEVICE_NUM_REGS * 4];; int i; int ret; memset(buf, 0, sizeof(buf)); for (i = 0; i < DEVICE_NUM_REGS; i++) { buf[i * 4] = regs[i] & 0xff; buf[i * 4 + 1] = (regs[i] >> 8) & 0xff; buf[i * 4 + 2] = (regs[i] >> 16) & 0xff; buf[i * 4 + 3] = regs[i] >> 24; } ret = fet_proto_xfer(&dev->proto, C_WRITEREGISTERS, buf, sizeof(buf), 1, 0xffff); if (ret < 0) { printc_err("fet: context set failed\n"); return -1; } return 0; } static int do_configure(struct fet_device *dev, const struct device_args *args) { if (!(args->flags & DEVICE_FLAG_JTAG)) { if (!fet_proto_xfer(&dev->proto, C_CONFIGURE, NULL, 0, 2, FET_CONFIG_PROTOCOL, 1)) { printc_dbg("Configured for Spy-Bi-Wire\n"); return 0; } printc_err("fet: Spy-Bi-Wire configuration failed\n"); return -1; } if (!fet_proto_xfer(&dev->proto, C_CONFIGURE, NULL, 0, 2, FET_CONFIG_PROTOCOL, 2)) { printc_dbg("Configured for JTAG (2)\n"); return 0; } printc_err("fet: warning: JTAG configuration failed -- " "retrying\n"); if (!fet_proto_xfer(&dev->proto, C_CONFIGURE, NULL, 0, 2, FET_CONFIG_PROTOCOL, 0)) { printc_dbg("Configured for JTAG (0)\n"); return 0; } printc_err("fet: JTAG configuration failed\n"); return -1; } int try_open(struct fet_device *dev, const struct device_args *args, int send_reset) { transport_t transport = dev->proto.transport; if (dev->proto.proto_flags & FET_PROTO_NOLEAD_SEND) { printc("Resetting Olimex command processor...\n"); transport->ops->send(transport, (const uint8_t *)"\x7e", 1); delay_ms(5); transport->ops->send(transport, (const uint8_t *)"\x7e", 1); delay_ms(5); } printc_dbg("Initializing FET...\n"); if (fet_proto_xfer(&dev->proto, C_INITIALIZE, NULL, 0, 0) < 0) { printc_err("fet: open failed\n"); return -1; } dev->version = dev->proto.argv[0]; printc_dbg("FET protocol version is %d\n", dev->version); if (fet_proto_xfer(&dev->proto, 0x27, NULL, 0, 1, 4) < 0) { printc_err("fet: init failed\n"); return -1; } /* set VCC */ if (fet_proto_xfer(&dev->proto, C_VCC, NULL, 0, 1, args->vcc_mv) < 0) printc_err("warning: fet: set VCC failed\n"); else printc_dbg("Set Vcc: %d mV\n", args->vcc_mv); if (do_configure(dev, args) < 0) return -1; if (send_reset || args->flags & DEVICE_FLAG_FORCE_RESET) { printc_dbg("Sending reset...\n"); if (fet_proto_xfer(&dev->proto, C_RESET, NULL, 0, 3, FET_RESET_ALL, 0, 0) < 0) printc_err("warning: fet: reset failed\n"); } /* Identify the chip */ if (do_identify(dev, args->forced_chip_id) < 0) { printc_err("fet: identify failed\n"); return -1; } return 0; } device_t fet_open(const struct device_args *args, int proto_flags, transport_t transport, int fet_flags, const struct device_class *type) { struct fet_device *dev = malloc(sizeof(*dev)); int i; if (args->flags & DEVICE_FLAG_SKIP_CLOSE) fet_flags |= FET_SKIP_CLOSE; if (!dev) { pr_error("fet: failed to allocate memory"); return NULL; } memset(dev, 0, sizeof(*dev)); fet_proto_init(&dev->proto, transport, proto_flags); dev->base.type = type; dev->fet_flags = fet_flags; if (try_open(dev, args, fet_flags & FET_FORCE_RESET) < 0) { delay_ms(500); printc_dbg("Trying again...\n"); if (try_open(dev, args, !is_new_olimex(dev)) < 0) goto fail; } /* Make sure breakpoints get reset on the first run */ if (dev->base.max_breakpoints > DEVICE_MAX_BREAKPOINTS) dev->base.max_breakpoints = DEVICE_MAX_BREAKPOINTS; for (i = 0; i < dev->base.max_breakpoints; i++) dev->base.breakpoints[i].flags = DEVICE_BP_DIRTY; /* Initialize power profiling */ power_init(dev); return (device_t)dev; fail: transport->ops->destroy(transport); free(dev); return NULL; } mspdebug-0.25/drivers/fet_core.h000066400000000000000000000042311313531517500166670ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef FET_CORE_H_ #define FET_CORE_H_ #include "device.h" #include "transport.h" /* Don't attempt to close JTAG on exit */ #define FET_SKIP_CLOSE 0x04 /* The new identify method should always be used */ #define FET_IDENTIFY_NEW 0x08 /* A reset on startup should always be performed */ #define FET_FORCE_RESET 0x10 /* To create a FET-like driver, you need to call this function to return * a device object. You need to provide: * * - device arguments * - a transport (serial port) * - protocol flags for the FET protocol * - flags which might affect FET high-level behaviour * - a device class (vtable) */ device_t fet_open(const struct device_args *args, int proto_flags, transport_t transport, int fet_flags, const struct device_class *type); /* These methods implement the device interface for FET-like drivers. */ int fet_erase(device_t dev_base, device_erase_type_t type, address_t addr); device_status_t fet_poll(device_t dev_base); int fet_ctl(device_t dev_base, device_ctl_t action); void fet_destroy(device_t dev_base); int fet_readmem(device_t dev_base, address_t addr, uint8_t *buffer, address_t count); int fet_writemem(device_t dev_base, address_t addr, const uint8_t *buffer, address_t count); int fet_getregs(device_t dev_base, address_t *regs); int fet_setregs(device_t dev_base, const address_t *regs); #endif mspdebug-0.25/drivers/fet_db.c000066400000000000000000050426421313531517500163340ustar00rootroot00000000000000/** * AUTHOR: Jose Angel Caso Sanchez, 2004 ( altomaltes@gmail.com ) * * Copyright (C) 2014, 2012 JACS * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * * FILE: fet_db.c * DATE: ene 2012 * * DESCRIPCION: MSP 430 V2 FET device satabase. * * * Original file and project: * * MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * */ #include #include "fet_db.h" #include "util.h" #define ETWPID_EMPTY 0x00 #define ETWPID_WDT_A 0x0A #define ETWPID_APOOL 0x1E #define ETWPID_USCI0 0x28 #define ETWPID_USCI1 0x29 #define ETWPID_USCI2 0x2A #define ETWPID_USCI3 0x2B #define ETWPID_USCIA0 0x2C #define ETWPID_USCIA1 0x2D #define ETWPID_USCI 0x2E #define ETWPID_USCIB0 0x30 #define ETWPID_USCIB1 0x31 #define ETWPID_USB 0x40 #define ETWPID_AES128 0x60 #define ETWPID_TMR0_A3 0x74 #define ETWPID_TMR0_D3 0x75 #define ETWPID_TMR3_A2 0x88 #define ETWPID_TMR2_A2 0x8C #define ETWPID_RTC 0x8A #define ETWPID_TMR1_A2 0x8D #define ETWPID_TA3_0 0x8E #define ETWPID_TA3_1 0x8F #define ETWPID_TMR0_A5 0x91 #define ETWPID_TB3_0 0x97 #define ETWPID_TB3_1 0x98 #define ETWPID_TB3_2 0x99 #define ETWPID_TMR0_B7 0x9D #define ETWPID_COMP_B 0xA8 #define ETWPID_LCDB 0xB0 #define ETWPID_CCS 0xB5 #define ETWPID_DAC12 0xC0 #define ETWPID_SD24B 0xD5 #define ETWPID_ADC10_A 0xD6 #define ETWPID_ADC11_A 0xD7 #define ETWPID_ADC12_A 0xD8 static const struct fet_db_record fet_db[] = {{ .name= "Prototype_MSP430F11x1" /* database IDX 1*/ , .msg28_data= { 0xF1, 0x12 /* ID (off: 0)*/ , 0x00 /* REV (off: 2)*/ , 0x43 /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0x00 /* SELF0 (off: 8)*/ , 0x08 /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x01, 0x01 /*, 0x4A */ } , .msg29_data={ 0x00, 0xF0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0xEF, 0xFF, 0xEF, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x02 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x00, 0x00 /* off: 22 Emulation */ , 0x00, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x00, 0x00 /* off: 36 Vcc 2 : 0 */ , 0x00, 0x00 /* off: 38 Vcc 3 : 0 */ , 0x00, 0x00 /* off: 40 Vcc 4 : 0 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x00, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x13, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x01 /* Identification number.*/ , .string = "Prototype_MSP430F11x1" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xF000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0xEF00, .infoEnd = 0xEFFF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x02FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 0 /* Clock control level.*/ , .emulation = 0x0000 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F11x1" /* database IDX 2*/ , .msg28_data= { 0xF1, 0x12 /* ID (off: 0)*/ , 0x10 /* REV (off: 2)*/ , 0x40 /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0x00 /* SELF0 (off: 8)*/ , 0x00 /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x02, 0x02 /*, 0x4A */ } , .msg29_data={ 0x00, 0xF0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x02 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x00, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x00, 0x00 /* off: 36 Vcc 2 : 0 */ , 0x00, 0x00 /* off: 38 Vcc 3 : 0 */ , 0x00, 0x00 /* off: 40 Vcc 4 : 0 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x00, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x13, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x02 /* Identification number.*/ , .string = "MSP430F11x1" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xF000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x02FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 0 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F133" /* database IDX 3*/ , .msg28_data= { 0xF1, 0x49 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x05 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x03, 0x03 /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x02 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x02, 0x00 /* off: 22 Emulation */ , 0x00, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x00, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x03, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x03 /* Identification number.*/ , .string = "MSP430F133" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x02FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 3 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 0 /* Clock control level.*/ , .emulation = 0x0002 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F135" /* database IDX 4*/ , .msg28_data= { 0xF1, 0x49 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x04 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x04, 0x04 /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x03 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x02, 0x00 /* off: 22 Emulation */ , 0x00, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x00, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x03, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x04 /* Identification number.*/ , .string = "MSP430F135" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x03FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 3 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 0 /* Clock control level.*/ , .emulation = 0x0002 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F147" /* database IDX 5*/ , .msg28_data= { 0xF1, 0x49 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x02 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x05, 0x05 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x05 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x02, 0x00 /* off: 22 Emulation */ , 0x00, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x00, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x03, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x05 /* Identification number.*/ , .string = "MSP430F147" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x05FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 3 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 0 /* Clock control level.*/ , .emulation = 0x0002 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F148" /* database IDX 6*/ , .msg28_data= { 0xF1, 0x49 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x01 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x06, 0x06 /*, 0x4A */ } , .msg29_data={ 0x00, 0x40, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x02, 0x00 /* off: 22 Emulation */ , 0x00, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x00, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x03, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x06 /* Identification number.*/ , .string = "MSP430F148" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 3 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 0 /* Clock control level.*/ , .emulation = 0x0002 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F149" /* database IDX 7*/ , .msg28_data= { 0xF1, 0x49 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x00 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x07, 0x07 /*, 0x4A */ } , .msg29_data={ 0x00, 0x11, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x02, 0x00 /* off: 22 Emulation */ , 0x00, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x00, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x03, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x07 /* Identification number.*/ , .string = "MSP430F149" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x1100, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 3 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 0 /* Clock control level.*/ , .emulation = 0x0002 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "Preliminary_MSP430F413" /* database IDX 8*/ , .msg28_data= { 0xF4, 0x03 /* ID (off: 0)*/ , 0x00 /* REV (off: 2)*/ , 0x40 /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x08, 0x08 /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x02 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0x9C, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x33, 0x00 /* SET */ , 0x13, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x08 /* Identification number.*/ , .string = "Preliminary_MSP430F413" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x02FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x009C /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F41x" /* database IDX 9*/ , .msg28_data= { 0xF4, 0x13 /* ID (off: 0)*/ , 0x02 /* REV (off: 2)*/ , 0x40 /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x09, 0x09 /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x02 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0x9C, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x33, 0x00 /* SET */ , 0x13, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x09 /* Identification number.*/ , .string = "MSP430F41x" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x02FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x009C /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F11x1A" /* database IDX A*/ , .msg28_data= { 0xF1, 0x12 /* ID (off: 0)*/ , 0x13 /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0x00 /* SELF0 (off: 8)*/ , 0x00 /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x0A, 0x0A /*, 0x4A */ } , .msg29_data={ 0x00, 0xF0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x02 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x00, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x00, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x13, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x0A /* Identification number.*/ , .string = "MSP430F11x1A" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xF000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x02FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 0 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F12x" /* database IDX B*/ , .msg28_data= { 0xF1, 0x23 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x0B, 0x0B /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x02 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x00, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x00, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x13, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x0B /* Identification number.*/ , .string = "MSP430F12x" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x02FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 0 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F43x" /* database IDX C*/ , .msg28_data= { 0xF4, 0x37 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x0C, 0x0C /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x05 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xA4, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x08, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x0C /* Identification number.*/ , .string = "MSP430F43x" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x05FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00A4 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 8 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 0 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F43x" /* database IDX D*/ , .msg28_data= { 0xF4, 0x49 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x02 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x0D, 0x0C /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x05 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xA4, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x08, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x0D /* Identification number.*/ , .string = "MSP430F43x" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x05FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00A4 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 8 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 0 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F44x" /* database IDX E*/ , .msg28_data= { 0xF4, 0x49 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x00 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x00 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x0E, 0x0D /*, 0x4A */ } , .msg29_data={ 0x00, 0x11, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xA4, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x08, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x0E /* Identification number.*/ , .string = "MSP430F44x" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x1100, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00A4 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 8 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 0 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "Preliminary_MSP430F12x2" /* database IDX F*/ , .msg28_data= { 0x12, 0x32 /* ID (off: 0)*/ , 0x00 /* REV (off: 2)*/ , 0x40 /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x0F, 0x0E /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x02 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x00, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x00, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x13, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x0F /* Identification number.*/ , .string = "Preliminary_MSP430F12x2" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x02FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 0 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F11x2" /* database IDX 10*/ , .msg28_data= { 0x11, 0x32 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x10, 0x0F /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x02 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x00, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x00, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x13, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x10 /* Identification number.*/ , .string = "MSP430F11x2" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x02FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 0 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F12x2/F11x2" /* database IDX 11*/ , .msg28_data= { 0x12, 0x32 /* ID (off: 0)*/ , 0x10 /* REV (off: 2)*/ , 0x40 /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x11, 0x10 /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x02 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x00, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x00, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x13, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x11 /* Identification number.*/ , .string = "MSP430F12x2/F11x2" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x02FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 0 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "Preliminary_MSP430F16x" /* database IDX 12*/ , .msg28_data= { 0xF1, 0x69 /* ID (off: 0)*/ , 0x00 /* REV (off: 2)*/ , 0x40 /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x12, 0x11 /*, 0x4A */ } , .msg29_data={ 0x00, 0x11, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x02, 0x00 /* off: 22 Emulation */ , 0x00, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x00, 0x00 /* off: 44 3-> Default clock control */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x03, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x12 /* Identification number.*/ , .string = "Preliminary_MSP430F16x" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x1100, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 3 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 0 /* Clock control level.*/ , .emulation = 0x0002 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FE423_P" /* database IDX 13*/ , .msg28_data= { 0xF4, 0x27 /* ID (off: 0)*/ , 0x00 /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x45 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x02 /* FUSES (off: 16)*/ , 0x1F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x13, 0x12 /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x02 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xA4, 0x00 /* off: 28 LCD MEM */ , 0x8C, 0x0A /* off: 32 Vcc 0 : 2700 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x8C, 0x0A /* off: 36 Vcc 2 : 2700 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x13 /* Identification number.*/ , .string = "MSP430FE423_P" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x02FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00A4 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0A8C, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FE425_P" /* database IDX 14*/ , .msg28_data= { 0xF4, 0x27 /* ID (off: 0)*/ , 0x00 /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x45 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x01 /* FUSES (off: 16)*/ , 0x1F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x14, 0x13 /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x03 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xA4, 0x00 /* off: 28 LCD MEM */ , 0x8C, 0x0A /* off: 32 Vcc 0 : 2700 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x8C, 0x0A /* off: 36 Vcc 2 : 2700 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x14 /* Identification number.*/ , .string = "MSP430FE425_P" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x03FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00A4 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0A8C, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FE427_P" /* database IDX 15*/ , .msg28_data= { 0xF4, 0x27 /* ID (off: 0)*/ , 0x00 /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x45 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x00 /* FUSES (off: 16)*/ , 0x1F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x15, 0x14 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x05 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xA4, 0x00 /* off: 28 LCD MEM */ , 0x8C, 0x0A /* off: 32 Vcc 0 : 2700 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x8C, 0x0A /* off: 36 Vcc 2 : 2700 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x15 /* Identification number.*/ , .string = "MSP430FE427_P" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x05FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00A4 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0A8C, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FE423_N" /* database IDX 16*/ , .msg28_data= { 0xF4, 0x27 /* ID (off: 0)*/ , 0x10 /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x45 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x02 /* FUSES (off: 16)*/ , 0x1F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x16, 0x12 /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x02 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xA4, 0x00 /* off: 28 LCD MEM */ , 0x8C, 0x0A /* off: 32 Vcc 0 : 2700 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x8C, 0x0A /* off: 36 Vcc 2 : 2700 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x16 /* Identification number.*/ , .string = "MSP430FE423_N" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x02FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00A4 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0A8C, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FE425_N" /* database IDX 17*/ , .msg28_data= { 0xF4, 0x27 /* ID (off: 0)*/ , 0x10 /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x45 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x01 /* FUSES (off: 16)*/ , 0x1F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x17, 0x13 /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x03 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xA4, 0x00 /* off: 28 LCD MEM */ , 0x8C, 0x0A /* off: 32 Vcc 0 : 2700 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x8C, 0x0A /* off: 36 Vcc 2 : 2700 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x17 /* Identification number.*/ , .string = "MSP430FE425_N" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x03FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00A4 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0A8C, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FE427_N" /* database IDX 18*/ , .msg28_data= { 0xF4, 0x27 /* ID (off: 0)*/ , 0x10 /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x45 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x00 /* FUSES (off: 16)*/ , 0x1F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x18, 0x14 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x05 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xA4, 0x00 /* off: 28 LCD MEM */ , 0x8C, 0x0A /* off: 32 Vcc 0 : 2700 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x8C, 0x0A /* off: 36 Vcc 2 : 2700 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x18 /* Identification number.*/ , .string = "MSP430FE427_N" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x05FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00A4 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0A8C, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FE423" /* database IDX 19*/ , .msg28_data= { 0xF4, 0x27 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x45 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x02 /* FUSES (off: 16)*/ , 0x1F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x19, 0x12 /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x02 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xA4, 0x00 /* off: 28 LCD MEM */ , 0x8C, 0x0A /* off: 32 Vcc 0 : 2700 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x8C, 0x0A /* off: 36 Vcc 2 : 2700 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x19 /* Identification number.*/ , .string = "MSP430FE423" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x02FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00A4 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0A8C, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FE425" /* database IDX 1A*/ , .msg28_data= { 0xF4, 0x27 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x45 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x01 /* FUSES (off: 16)*/ , 0x1F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x1A, 0x13 /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x03 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xA4, 0x00 /* off: 28 LCD MEM */ , 0x8C, 0x0A /* off: 32 Vcc 0 : 2700 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x8C, 0x0A /* off: 36 Vcc 2 : 2700 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x1A /* Identification number.*/ , .string = "MSP430FE425" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x03FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00A4 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0A8C, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FE427" /* database IDX 1B*/ , .msg28_data= { 0xF4, 0x27 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x45 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x00 /* FUSES (off: 16)*/ , 0x1F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x1B, 0x14 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x05 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xA4, 0x00 /* off: 28 LCD MEM */ , 0x8C, 0x0A /* off: 32 Vcc 0 : 2700 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x8C, 0x0A /* off: 36 Vcc 2 : 2700 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x1B /* Identification number.*/ , .string = "MSP430FE427" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x05FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00A4 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0A8C, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F423" /* database IDX 1C*/ , .msg28_data= { 0xF4, 0x27 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x45 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x06 /* FUSES (off: 16)*/ , 0x1F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x1C, 0x15 /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x02 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xA4, 0x00 /* off: 28 LCD MEM */ , 0x8C, 0x0A /* off: 32 Vcc 0 : 2700 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x8C, 0x0A /* off: 36 Vcc 2 : 2700 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x1C /* Identification number.*/ , .string = "MSP430F423" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x02FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00A4 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0A8C, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F425" /* database IDX 1D*/ , .msg28_data= { 0xF4, 0x27 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x45 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x05 /* FUSES (off: 16)*/ , 0x1F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x1D, 0x16 /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x03 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xA4, 0x00 /* off: 28 LCD MEM */ , 0x8C, 0x0A /* off: 32 Vcc 0 : 2700 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x8C, 0x0A /* off: 36 Vcc 2 : 2700 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x1D /* Identification number.*/ , .string = "MSP430F425" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x03FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00A4 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0A8C, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F427" /* database IDX 1E*/ , .msg28_data= { 0xF4, 0x27 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x45 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x04 /* FUSES (off: 16)*/ , 0x1F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x1E, 0x17 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x05 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xA4, 0x00 /* off: 28 LCD MEM */ , 0x8C, 0x0A /* off: 32 Vcc 0 : 2700 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x8C, 0x0A /* off: 36 Vcc 2 : 2700 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x1E /* Identification number.*/ , .string = "MSP430F427" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x05FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00A4 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0A8C, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FW42x/F41x" /* database IDX 1F*/ , .msg28_data= { 0xF4, 0x27 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x57 /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x1F, 0x18 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x05 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0x9C, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x33, 0x00 /* SET */ , 0x13, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x1F /* Identification number.*/ , .string = "MSP430FW42x/F41x" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x05FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x009C /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F4230" /* database IDX 20*/ , .msg28_data= { 0xF4, 0x27 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x47 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x06 /* FUSES (off: 16)*/ , 0x07 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x20, 0x19 /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x02 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xAF, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x8C, 0x0A /* off: 36 Vcc 2 : 2700 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x20 /* Identification number.*/ , .string = "MSP430F4230" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x02FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00AF /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F4250" /* database IDX 21*/ , .msg28_data= { 0xF4, 0x27 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x47 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x05 /* FUSES (off: 16)*/ , 0x07 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x21, 0x1A /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x02 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xAF, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x8C, 0x0A /* off: 36 Vcc 2 : 2700 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x21 /* Identification number.*/ , .string = "MSP430F4250" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x02FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00AF /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F42x0" /* database IDX 22*/ , .msg28_data= { 0xF4, 0x27 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x47 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x04 /* FUSES (off: 16)*/ , 0x07 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x22, 0x1B /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x02 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xAF, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x8C, 0x0A /* off: 36 Vcc 2 : 2700 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x22 /* Identification number.*/ , .string = "MSP430F42x0" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x02FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00AF /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F155" /* database IDX 23*/ , .msg28_data= { 0xF1, 0x69 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x06 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x23, 0x1C /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x03 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x00, 0x00 /* off: 44 3-> Default clock control */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x08, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x23 /* Identification number.*/ , .string = "MSP430F155" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x03FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 8 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F156" /* database IDX 24*/ , .msg28_data= { 0xF1, 0x69 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x05 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x24, 0x1D /*, 0x4A */ } , .msg29_data={ 0x00, 0xA0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x05 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x00, 0x00 /* off: 44 3-> Default clock control */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x08, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x24 /* Identification number.*/ , .string = "MSP430F156" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xA000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x05FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 8 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F157" /* database IDX 25*/ , .msg28_data= { 0xF1, 0x69 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x04 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x25, 0x1E /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x05 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x00, 0x00 /* off: 44 3-> Default clock control */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x08, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x25 /* Identification number.*/ , .string = "MSP430F157" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x05FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 8 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F167" /* database IDX 26*/ , .msg28_data= { 0xF1, 0x69 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x02 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x26, 0x1F /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x05 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x00, 0x00 /* off: 44 3-> Default clock control */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x08, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x26 /* Identification number.*/ , .string = "MSP430F167" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x05FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 8 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F168" /* database IDX 27*/ , .msg28_data= { 0xF1, 0x69 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x01 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x27, 0x20 /*, 0x4A */ } , .msg29_data={ 0x00, 0x40, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x00, 0x00 /* off: 44 3-> Default clock control */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x08, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x27 /* Identification number.*/ , .string = "MSP430F168" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 8 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F169" /* database IDX 28*/ , .msg28_data= { 0xF1, 0x69 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x00 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x28, 0x21 /*, 0x4A */ } , .msg29_data={ 0x00, 0x11, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x00, 0x00 /* off: 44 3-> Default clock control */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x08, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x28 /* Identification number.*/ , .string = "MSP430F169" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x1100, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 8 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F1610" /* database IDX 29*/ , .msg28_data= { 0xF1, 0x6C /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x03 /* FUSES (off: 16)*/ , 0x07 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x29, 0x22 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x00, 0x00 /* off: 44 3-> Default clock control */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x11 , 0x00, 0x00 , 0x00, 0x24 , 0x00, 0x00 , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x08, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x11 , 0x00, 0x00 , 0xFF, 0x24 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x29 /* Identification number.*/ , .string = "MSP430F1610" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x1100, .ram2End = 0x24FF /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 8 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F1611" /* database IDX 2A*/ , .msg28_data= { 0xF1, 0x6C /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x00 /* FUSES (off: 16)*/ , 0x07 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x2A, 0x23 /*, 0x4A */ } , .msg29_data={ 0x00, 0x40, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x00, 0x00 /* off: 44 3-> Default clock control */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x11 , 0x00, 0x00 , 0x00, 0x38 , 0x00, 0x00 , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x08, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x11 , 0x00, 0x00 , 0xFF, 0x38 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x2A /* Identification number.*/ , .string = "MSP430F1611" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x1100, .ram2End = 0x38FF /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 8 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F1612" /* database IDX 2B*/ , .msg28_data= { 0xF1, 0x6C /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x06 /* FUSES (off: 16)*/ , 0x07 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x2B, 0x24 /*, 0x4A */ } , .msg29_data={ 0x00, 0x25, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x00, 0x00 /* off: 44 3-> Default clock control */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x11 , 0x00, 0x00 , 0x00, 0x24 , 0x00, 0x00 , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x08, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x11 , 0x00, 0x00 , 0xFF, 0x24 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x2B /* Identification number.*/ , .string = "MSP430F1612" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x2500, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x1100, .ram2End = 0x24FF /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 8 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F169" /* database IDX 2C*/ , .msg28_data= { 0xF1, 0x6C /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x07 /* FUSES (off: 16)*/ , 0x07 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x2C, 0x21 /*, 0x4A */ } , .msg29_data={ 0x00, 0x11, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x00, 0x00 /* off: 44 3-> Default clock control */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x08, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x2C /* Identification number.*/ , .string = "MSP430F169" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x1100, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 8 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FG43x_F43x" /* database IDX 2D*/ , .msg28_data= { 0xF4, 0x39 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x47 /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x2D, 0x25 /*, 0x4A */ } , .msg29_data={ 0x00, 0x11, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0x9C, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x2D /* Identification number.*/ , .string = "MSP430FG43x_F43x" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x1100, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x009C /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FG4619" /* database IDX 2E*/ , .msg28_data= { 0xF4, 0x6F /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x47 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x00 /* FUSES (off: 16)*/ , 0x03 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x2E, 0x26 /*, 0x4A */ } , .msg29_data={ 0x00, 0x21, 0xFF, 0xFF, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0x9C, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x11 , 0x00, 0x00 , 0x00, 0x20 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x13, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x08, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x11 , 0x00, 0x00 , 0xFF, 0x20 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x2E /* Identification number.*/ , .string = "MSP430FG4619" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x2100, .mainEnd = 0x1FFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x1100, .ram2End = 0x20FF /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x009C /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 8 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F21x1" /* database IDX 2F*/ , .msg28_data= { 0xF2, 0x13 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x01 /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x2F, 0x27 /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x02 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x2F /* Identification number.*/ , .string = "MSP430F21x1" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x02FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "TMS430FCAS001" /* database IDX 30*/ , .msg28_data= { 0xAF, 0x13 /* ID (off: 0)*/ , 0x90 /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x30, 0x28 /*, 0x4A */ } , .msg29_data={ 0x00, 0x10, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0x7F, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x05, 0xFF, 0x0C /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x29, 0x00 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x9A, 0x0B /* off: 32 Vcc 0 : 2970 */ , 0x7C, 0x15 /* off: 34 Vcc 1 : 5500 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x02, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x37, 0x00 /* SET */ , 0x17, 0x00 /* SET */ , 0x00, 0x00 } , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x00, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x02, 0x00 /* SET */ , 0x08, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x30 /* Identification number.*/ , .string = "TMS430FCAS001" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x1000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x107F /* INFO Memory range */ , .ramStart = 0x0500, .ramEnd = 0x0CFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0B9A, .vccMaxOp= 0x157C /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 0 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 2 /* Breakpoint Modes*/ , .nBreakRdWr = 8 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "TMS430FCAS003" /* database IDX 31*/ , .msg28_data= { 0xAF, 0x12 /* ID (off: 0)*/ , 0x50 /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x31, 0x29 /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0x7F, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x05, 0xFF, 0x07 /* off: 12 RAM */ , 0x00, 0x00, 0x00, 0x00 /* off: 16 RAM2 */ , 0x00, 0x00 /* off: 20 Breakpoints */ , 0x00, 0x00 /* off: 22 Emulation */ , 0x00, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x29, 0x00 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x3F, 0x0C /* off: 32 Vcc 0 : 3135 */ , 0x82, 0x14 /* off: 34 Vcc 1 : 5250 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x02, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x37, 0x00 /* SET */ , 0x17, 0x00 /* SET */ , 0x00, 0x00 } , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x00, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x31 /* Identification number.*/ , .string = "TMS430FCAS003" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x107F /* INFO Memory range */ , .ramStart = 0x0500, .ramEnd = 0x07FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0C3F, .vccMaxOp= 0x1482 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 0 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 0 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 0 /* Clock control level.*/ , .emulation = 0x0000 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "TMS430ROMSHUTTLE" /* database IDX 32*/ , .msg28_data= { 0xA0, 0x54 /* ID (off: 0)*/ , 0x49 /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x32, 0x2A /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0x7F, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x05, 0xFF, 0x07 /* off: 12 RAM */ , 0x00, 0x00, 0x00, 0x00 /* off: 16 RAM2 */ , 0x00, 0x00 /* off: 20 Breakpoints */ , 0x00, 0x00 /* off: 22 Emulation */ , 0x00, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x29, 0x00 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x3F, 0x0C /* off: 32 Vcc 0 : 3135 */ , 0x82, 0x14 /* off: 34 Vcc 1 : 5250 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x02, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x37, 0x00 /* SET */ , 0x17, 0x00 /* SET */ , 0x00, 0x00 } , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x00, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x32 /* Identification number.*/ , .string = "TMS430ROMSHUTTLE" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x107F /* INFO Memory range */ , .ramStart = 0x0500, .ramEnd = 0x07FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0C3F, .vccMaxOp= 0x1482 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 0 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 0 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 0 /* Clock control level.*/ , .emulation = 0x0000 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "TMS430EMU" /* database IDX 33*/ , .msg28_data= { 0xAE, 0x10 /* ID (off: 0)*/ , 0x00 /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x33, 0x2B /*, 0x4A */ } , .msg29_data={ 0x00, 0x10, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0x7F, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x05, 0xFF, 0x0C /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x29, 0x00 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x9A, 0x0B /* off: 32 Vcc 0 : 2970 */ , 0x7C, 0x15 /* off: 34 Vcc 1 : 5500 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x02, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x37, 0x00 /* SET */ , 0x17, 0x00 /* SET */ , 0x00, 0x00 } , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x00, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x02, 0x00 /* SET */ , 0x08, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x33 /* Identification number.*/ , .string = "TMS430EMU" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x1000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x107F /* INFO Memory range */ , .ramStart = 0x0500, .ramEnd = 0x0CFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0B9A, .vccMaxOp= 0x157C /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 0 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 2 /* Breakpoint Modes*/ , .nBreakRdWr = 8 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F20x3" /* database IDX 34*/ , .msg28_data= { 0xF2, 0x01 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x03 /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x34, 0x2C /*, 0x4A */ } , .msg29_data={ 0x00, 0xF8, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0x7F, 0x02 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x00, 0x00, 0x00, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x34 /* Identification number.*/ , .string = "MSP430F20x3" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xF800, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x027F /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0000, .bslEnd = 0x0000 /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "F20x2_G2x2x_G2x3x" /* database IDX 35*/ , .msg28_data= { 0xF2, 0x01 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x02 /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x35, 0x2D /*, 0x4A */ } , .msg29_data={ 0x00, 0xF8, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0x7F, 0x02 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x00, 0x00, 0x00, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x35 /* Identification number.*/ , .string = "F20x2_G2x2x_G2x3x" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xF800, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x027F /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0000, .bslEnd = 0x0000 /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "F20x1_G2x0x_G2x1x" /* database IDX 36*/ , .msg28_data= { 0xF2, 0x01 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x01 /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x36, 0x2E /*, 0x4A */ } , .msg29_data={ 0x00, 0xF8, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0x7F, 0x02 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x00, 0x00, 0x00, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x36 /* Identification number.*/ , .string = "F20x1_G2x0x_G2x1x" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xF800, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x027F /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0000, .bslEnd = 0x0000 /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F2234" /* database IDX 37*/ , .msg28_data= { 0xF2, 0x27 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x02 /* FUSES (off: 16)*/ , 0x07 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x37, 0x2F /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x03 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x37 /* Identification number.*/ , .string = "MSP430F2234" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x03FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F2254" /* database IDX 38*/ , .msg28_data= { 0xF2, 0x27 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x01 /* FUSES (off: 16)*/ , 0x07 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x38, 0x30 /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x03 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x38 /* Identification number.*/ , .string = "MSP430F2254" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x03FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F2274" /* database IDX 39*/ , .msg28_data= { 0xF2, 0x27 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x80 /* FUSES (off: 16)*/ , 0x07 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x39, 0x31 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x05 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x39 /* Identification number.*/ , .string = "MSP430F2274" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x05FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FG4618" /* database IDX 3A*/ , .msg28_data= { 0xF4, 0x6F /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x47 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x01 /* FUSES (off: 16)*/ , 0x03 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x3A, 0x32 /*, 0x4A */ } , .msg29_data={ 0x00, 0x31, 0xFF, 0xFF, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0x9C, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x11 , 0x00, 0x00 , 0x00, 0x30 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x13, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x08, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x11 , 0x00, 0x00 , 0xFF, 0x30 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x3A /* Identification number.*/ , .string = "MSP430FG4618" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x3100, .mainEnd = 0x1FFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x1100, .ram2End = 0x30FF /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x009C /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 8 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F2330" /* database IDX 3B*/ , .msg28_data= { 0xF2, 0x37 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x02 /* FUSES (off: 16)*/ , 0x03 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x3B, 0x33 /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x05 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x3B /* Identification number.*/ , .string = "MSP430F2330" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x05FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F2350" /* database IDX 3C*/ , .msg28_data= { 0xF2, 0x37 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x01 /* FUSES (off: 16)*/ , 0x03 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x3C, 0x34 /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x3C /* Identification number.*/ , .string = "MSP430F2350" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F2370" /* database IDX 3D*/ , .msg28_data= { 0xF2, 0x37 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x00 /* FUSES (off: 16)*/ , 0x03 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x3D, 0x35 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x3D /* Identification number.*/ , .string = "MSP430F2370" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F2232" /* database IDX 3E*/ , .msg28_data= { 0xF2, 0x27 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x06 /* FUSES (off: 16)*/ , 0x07 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x3E, 0x36 /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x03 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x3E /* Identification number.*/ , .string = "MSP430F2232" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x03FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F2252" /* database IDX 3F*/ , .msg28_data= { 0xF2, 0x27 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x05 /* FUSES (off: 16)*/ , 0x07 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x3F, 0x37 /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x03 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x3F /* Identification number.*/ , .string = "MSP430F2252" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x03FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F2272" /* database IDX 40*/ , .msg28_data= { 0xF2, 0x27 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x04 /* FUSES (off: 16)*/ , 0x07 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x40, 0x38 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x05 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x40 /* Identification number.*/ , .string = "MSP430F2272" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x05FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F2619" /* database IDX 41*/ , .msg28_data= { 0xF2, 0x6F /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x00 /* FUSES (off: 16)*/ , 0x07 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x41, 0x39 /*, 0x4A */ } , .msg29_data={ 0x00, 0x21, 0xFF, 0xFF, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x11 , 0x00, 0x00 , 0x00, 0x20 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x08, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x11 , 0x00, 0x00 , 0xFF, 0x20 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x41 /* Identification number.*/ , .string = "MSP430F2619" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x2100, .mainEnd = 0x1FFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x1100, .ram2End = 0x20FF /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 8 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F2618" /* database IDX 42*/ , .msg28_data= { 0xF2, 0x6F /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x01 /* FUSES (off: 16)*/ , 0x07 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x42, 0x3A /*, 0x4A */ } , .msg29_data={ 0x00, 0x31, 0xFF, 0xFF, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x11 , 0x00, 0x00 , 0x00, 0x30 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x08, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x11 , 0x00, 0x00 , 0xFF, 0x30 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x42 /* Identification number.*/ , .string = "MSP430F2618" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x3100, .mainEnd = 0x1FFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x1100, .ram2End = 0x30FF /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 8 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F2419" /* database IDX 43*/ , .msg28_data= { 0xF2, 0x6F /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x04 /* FUSES (off: 16)*/ , 0x07 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x43, 0x3B /*, 0x4A */ } , .msg29_data={ 0x00, 0x21, 0xFF, 0xFF, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x11 , 0x00, 0x00 , 0x00, 0x20 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x08, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x11 , 0x00, 0x00 , 0xFF, 0x20 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x43 /* Identification number.*/ , .string = "MSP430F2419" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x2100, .mainEnd = 0x1FFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x1100, .ram2End = 0x20FF /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 8 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F2418" /* database IDX 44*/ , .msg28_data= { 0xF2, 0x6F /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x05 /* FUSES (off: 16)*/ , 0x07 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x44, 0x3C /*, 0x4A */ } , .msg29_data={ 0x00, 0x31, 0xFF, 0xFF, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x11 , 0x00, 0x00 , 0x00, 0x30 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x08, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x11 , 0x00, 0x00 , 0xFF, 0x30 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x44 /* Identification number.*/ , .string = "MSP430F2418" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x3100, .mainEnd = 0x1FFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x1100, .ram2End = 0x30FF /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 8 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FE423A" /* database IDX 45*/ , .msg28_data= { 0x42, 0x7A /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x45 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x02 /* FUSES (off: 16)*/ , 0x1F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x45, 0x3D /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x02 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xA4, 0x00 /* off: 28 LCD MEM */ , 0x8C, 0x0A /* off: 32 Vcc 0 : 2700 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x8C, 0x0A /* off: 36 Vcc 2 : 2700 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x45 /* Identification number.*/ , .string = "MSP430FE423A" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x02FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00A4 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0A8C, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FE425A" /* database IDX 46*/ , .msg28_data= { 0x42, 0x7A /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x45 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x01 /* FUSES (off: 16)*/ , 0x1F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x46, 0x3E /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x03 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xA4, 0x00 /* off: 28 LCD MEM */ , 0x8C, 0x0A /* off: 32 Vcc 0 : 2700 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x8C, 0x0A /* off: 36 Vcc 2 : 2700 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x46 /* Identification number.*/ , .string = "MSP430FE425A" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x03FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00A4 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0A8C, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FE427A" /* database IDX 47*/ , .msg28_data= { 0x42, 0x7A /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x45 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x00 /* FUSES (off: 16)*/ , 0x1F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x47, 0x3F /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x05 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xA4, 0x00 /* off: 28 LCD MEM */ , 0x8C, 0x0A /* off: 32 Vcc 0 : 2700 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x8C, 0x0A /* off: 36 Vcc 2 : 2700 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x47 /* Identification number.*/ , .string = "MSP430FE427A" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x05FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00A4 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0A8C, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F423A" /* database IDX 48*/ , .msg28_data= { 0x42, 0x7A /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x45 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x06 /* FUSES (off: 16)*/ , 0x1F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x48, 0x40 /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x02 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xA4, 0x00 /* off: 28 LCD MEM */ , 0x8C, 0x0A /* off: 32 Vcc 0 : 2700 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x8C, 0x0A /* off: 36 Vcc 2 : 2700 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x48 /* Identification number.*/ , .string = "MSP430F423A" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x02FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00A4 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0A8C, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F425A" /* database IDX 49*/ , .msg28_data= { 0x42, 0x7A /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x45 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x05 /* FUSES (off: 16)*/ , 0x1F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x49, 0x41 /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x03 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xA4, 0x00 /* off: 28 LCD MEM */ , 0x8C, 0x0A /* off: 32 Vcc 0 : 2700 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x8C, 0x0A /* off: 36 Vcc 2 : 2700 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x49 /* Identification number.*/ , .string = "MSP430F425A" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x03FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00A4 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0A8C, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F427A" /* database IDX 4A*/ , .msg28_data= { 0x42, 0x7A /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x45 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x04 /* FUSES (off: 16)*/ , 0x1F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x4A, 0x42 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x05 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xA4, 0x00 /* off: 28 LCD MEM */ , 0x8C, 0x0A /* off: 32 Vcc 0 : 2700 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x8C, 0x0A /* off: 36 Vcc 2 : 2700 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x4A /* Identification number.*/ , .string = "MSP430F427A" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x05FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00A4 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0A8C, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F4783" /* database IDX 4B*/ , .msg28_data= { 0xF4, 0x49 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x02 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x07 /* FUSES (off: 16)*/ , 0x07 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x4B, 0x43 /*, 0x4A */ } , .msg29_data={ 0x00, 0x40, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xAF, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x4B /* Identification number.*/ , .string = "MSP430F4783" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00AF /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F4784" /* database IDX 4C*/ , .msg28_data= { 0xF4, 0x49 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x02 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x03 /* FUSES (off: 16)*/ , 0x07 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x4C, 0x44 /*, 0x4A */ } , .msg29_data={ 0x00, 0x40, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xAF, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x4C /* Identification number.*/ , .string = "MSP430F4784" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00AF /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F4793" /* database IDX 4D*/ , .msg28_data= { 0xF4, 0x49 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x02 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x04 /* FUSES (off: 16)*/ , 0x07 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x4D, 0x45 /*, 0x4A */ } , .msg29_data={ 0x00, 0x11, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x0B /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xAF, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x4D /* Identification number.*/ , .string = "MSP430F4793" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x1100, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x0BFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00AF /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F4794" /* database IDX 4E*/ , .msg28_data= { 0xF4, 0x49 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x02 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x00 /* FUSES (off: 16)*/ , 0x07 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x4E, 0x46 /*, 0x4A */ } , .msg29_data={ 0x00, 0x11, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x0B /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xAF, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x4E /* Identification number.*/ , .string = "MSP430F4794" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x1100, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x0BFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00AF /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F249" /* database IDX 4F*/ , .msg28_data= { 0xF2, 0x49 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x00 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x4F, 0x47 /*, 0x4A */ } , .msg29_data={ 0x00, 0x11, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x01, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x4F /* Identification number.*/ , .string = "MSP430F249" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x1100, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 1 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F248" /* database IDX 50*/ , .msg28_data= { 0xF2, 0x49 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x01 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x50, 0x48 /*, 0x4A */ } , .msg29_data={ 0x00, 0x40, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x11 , 0x00, 0x00 , 0x00, 0x20 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x01, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x11 , 0x00, 0x00 , 0xFF, 0x20 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x50 /* Identification number.*/ , .string = "MSP430F248" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x1100, .ram2End = 0x20FF /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 1 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F247" /* database IDX 51*/ , .msg28_data= { 0xF2, 0x49 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x02 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x51, 0x49 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x11 , 0x00, 0x00 , 0x00, 0x20 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x01, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x11 , 0x00, 0x00 , 0xFF, 0x20 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x51 /* Identification number.*/ , .string = "MSP430F247" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x1100, .ram2End = 0x20FF /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 1 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F235" /* database IDX 52*/ , .msg28_data= { 0xF2, 0x49 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x03 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x52, 0x4A /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x01, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x52 /* Identification number.*/ , .string = "MSP430F235" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 1 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F2491" /* database IDX 53*/ , .msg28_data= { 0xF2, 0x49 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x04 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x53, 0x4B /*, 0x4A */ } , .msg29_data={ 0x00, 0x11, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x01, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x53 /* Identification number.*/ , .string = "MSP430F2491" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x1100, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 1 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F2481" /* database IDX 54*/ , .msg28_data= { 0xF2, 0x49 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x05 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x54, 0x4C /*, 0x4A */ } , .msg29_data={ 0x00, 0x40, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x11 , 0x00, 0x00 , 0x00, 0x20 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x01, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x11 , 0x00, 0x00 , 0xFF, 0x20 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x54 /* Identification number.*/ , .string = "MSP430F2481" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x1100, .ram2End = 0x20FF /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 1 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F2471" /* database IDX 55*/ , .msg28_data= { 0xF2, 0x49 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x06 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x55, 0x4D /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x11 , 0x00, 0x00 , 0x00, 0x20 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x01, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x11 , 0x00, 0x00 , 0xFF, 0x20 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x55 /* Identification number.*/ , .string = "MSP430F2471" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x1100, .ram2End = 0x20FF /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 1 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F233" /* database IDX 56*/ , .msg28_data= { 0xF2, 0x49 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x07 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x56, 0x4E /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x05 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x01, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x56 /* Identification number.*/ , .string = "MSP430F233" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x05FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 1 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F2410" /* database IDX 57*/ , .msg28_data= { 0xF2, 0x49 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x08 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x57, 0x4F /*, 0x4A */ } , .msg29_data={ 0x00, 0x21, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x11 , 0x00, 0x00 , 0x00, 0x20 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x01, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x11 , 0x00, 0x00 , 0xFF, 0x20 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x57 /* Identification number.*/ , .string = "MSP430F2410" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x2100, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x1100, .ram2End = 0x20FF /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 1 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F2132" /* database IDX 58*/ , .msg28_data= { 0xF2, 0x13 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x02 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x00 /* FUSES (off: 16)*/ , 0x03 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x58, 0x50 /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x03 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x58 /* Identification number.*/ , .string = "MSP430F2132" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x03FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F2122" /* database IDX 59*/ , .msg28_data= { 0xF2, 0x13 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x02 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x01 /* FUSES (off: 16)*/ , 0x03 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x59, 0x51 /*, 0x4A */ } , .msg29_data={ 0x00, 0xF0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x03 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x59 /* Identification number.*/ , .string = "MSP430F2122" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xF000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x03FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F2112" /* database IDX 5A*/ , .msg28_data= { 0xF2, 0x13 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x02 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x02 /* FUSES (off: 16)*/ , 0x03 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x5A, 0x52 /*, 0x4A */ } , .msg29_data={ 0x00, 0xF8, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x02 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x5A /* Identification number.*/ , .string = "MSP430F2112" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xF800, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x02FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "XMS430F5438" /* database IDX 5B*/ , .msg28_data= { 0x54, 0x38 /* ID (off: 0)*/ , 0x01 /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x5B, 0x53 /*, 0x4A */ } , .msg29_data={ 0x00, 0x5C, 0xFF, 0x5B, 0x04, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x5B /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TMR0_B7 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x5B /* Identification number.*/ , .string = "XMS430F5438" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x5C00, .mainEnd = 0x45BFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x5BFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5438" /* database IDX 5C*/ , .msg28_data= { 0x54, 0x38 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x5C, 0x54 /*, 0x4A */ } , .msg29_data={ 0x00, 0x5C, 0xFF, 0x5B, 0x04, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x5B /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TMR0_B7 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x5C /* Identification number.*/ , .string = "MSP430F5438" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x5C00, .mainEnd = 0x45BFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x5BFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5436" /* database IDX 5D*/ , .msg28_data= { 0x54, 0x36 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x5D, 0x55 /*, 0x4A */ } , .msg29_data={ 0x00, 0x5C, 0xFF, 0x5B, 0x03, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x5B /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TMR0_B7 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x5D /* Identification number.*/ , .string = "MSP430F5436" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x5C00, .mainEnd = 0x35BFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x5BFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5419" /* database IDX 5E*/ , .msg28_data= { 0x54, 0x19 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x5E, 0x56 /*, 0x4A */ } , .msg29_data={ 0x00, 0x5C, 0xFF, 0x5B, 0x02, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x5B /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TMR0_B7 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x5E /* Identification number.*/ , .string = "MSP430F5419" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x5C00, .mainEnd = 0x25BFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x5BFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FE4232" /* database IDX 5F*/ , .msg28_data= { 0x42, 0x52 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x45 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x12 /* FUSES (off: 16)*/ , 0x1F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x5F, 0x57 /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x02 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xA4, 0x00 /* off: 28 LCD MEM */ , 0x8C, 0x0A /* off: 32 Vcc 0 : 2700 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x8C, 0x0A /* off: 36 Vcc 2 : 2700 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x5F /* Identification number.*/ , .string = "MSP430FE4232" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x02FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00A4 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0A8C, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FE42x2" /* database IDX 60*/ , .msg28_data= { 0x42, 0x52 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x45 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x11 /* FUSES (off: 16)*/ , 0x1F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x60, 0x58 /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x03 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xA4, 0x00 /* off: 28 LCD MEM */ , 0x8C, 0x0A /* off: 32 Vcc 0 : 2700 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x8C, 0x0A /* off: 36 Vcc 2 : 2700 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x60 /* Identification number.*/ , .string = "MSP430FE42x2" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x03FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00A4 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0A8C, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5437" /* database IDX 61*/ , .msg28_data= { 0x54, 0x37 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x61, 0x59 /*, 0x4A */ } , .msg29_data={ 0x00, 0x5C, 0xFF, 0x5B, 0x04, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x5B /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TMR0_B7 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x61 /* Identification number.*/ , .string = "MSP430F5437" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x5C00, .mainEnd = 0x45BFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x5BFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5435" /* database IDX 62*/ , .msg28_data= { 0x54, 0x35 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x62, 0x5A /*, 0x4A */ } , .msg29_data={ 0x00, 0x5C, 0xFF, 0x5B, 0x03, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x5B /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TMR0_B7 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x62 /* Identification number.*/ , .string = "MSP430F5435" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x5C00, .mainEnd = 0x35BFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x5BFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5418" /* database IDX 63*/ , .msg28_data= { 0x54, 0x18 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x63, 0x5B /*, 0x4A */ } , .msg29_data={ 0x00, 0x5C, 0xFF, 0x5B, 0x02, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x5B /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TMR0_B7 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x63 /* Identification number.*/ , .string = "MSP430F5418" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x5C00, .mainEnd = 0x25BFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x5BFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FG4250" /* database IDX 64*/ , .msg28_data= { 0xF4, 0x27 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x47 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x01 /* FUSES (off: 16)*/ , 0x07 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x64, 0x5C /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x02 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xAF, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x8C, 0x0A /* off: 36 Vcc 2 : 2700 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x64 /* Identification number.*/ , .string = "MSP430FG4250" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x02FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00AF /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FG42x0" /* database IDX 65*/ , .msg28_data= { 0xF4, 0x27 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x47 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x00 /* FUSES (off: 16)*/ , 0x07 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x65, 0x5D /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x02 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xAF, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x8C, 0x0A /* off: 36 Vcc 2 : 2700 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x65 /* Identification number.*/ , .string = "MSP430FG42x0" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x02FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00AF /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FE4272" /* database IDX 66*/ , .msg28_data= { 0x42, 0x52 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x45 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x10 /* FUSES (off: 16)*/ , 0x1F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x66, 0x5E /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x05 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xA4, 0x00 /* off: 28 LCD MEM */ , 0x8C, 0x0A /* off: 32 Vcc 0 : 2700 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x8C, 0x0A /* off: 36 Vcc 2 : 2700 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xD3, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x66 /* Identification number.*/ , .string = "MSP430FE4272" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x05FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00A4 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0A8C, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FG477" /* database IDX 67*/ , .msg28_data= { 0xF4, 0x79 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x47 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x02 /* FUSES (off: 16)*/ , 0x07 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x67, 0x5F /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xAF, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x8C, 0x0A /* off: 36 Vcc 2 : 2700 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x67 /* Identification number.*/ , .string = "MSP430FG477" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00AF /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FG478" /* database IDX 68*/ , .msg28_data= { 0xF4, 0x79 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x47 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x01 /* FUSES (off: 16)*/ , 0x07 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x68, 0x60 /*, 0x4A */ } , .msg29_data={ 0x00, 0x40, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xAF, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x8C, 0x0A /* off: 36 Vcc 2 : 2700 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x68 /* Identification number.*/ , .string = "MSP430FG478" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00AF /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FG479" /* database IDX 69*/ , .msg28_data= { 0xF4, 0x79 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x47 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x00 /* FUSES (off: 16)*/ , 0x07 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x69, 0x61 /*, 0x4A */ } , .msg29_data={ 0x00, 0x11, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xAF, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x8C, 0x0A /* off: 36 Vcc 2 : 2700 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x69 /* Identification number.*/ , .string = "MSP430FG479" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x1100, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00AF /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F477" /* database IDX 6A*/ , .msg28_data= { 0xF4, 0x79 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x47 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x06 /* FUSES (off: 16)*/ , 0x07 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x6A, 0x62 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xAF, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x8C, 0x0A /* off: 36 Vcc 2 : 2700 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x6A /* Identification number.*/ , .string = "MSP430F477" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00AF /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F478" /* database IDX 6B*/ , .msg28_data= { 0xF4, 0x79 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x47 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x05 /* FUSES (off: 16)*/ , 0x07 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x6B, 0x63 /*, 0x4A */ } , .msg29_data={ 0x00, 0x40, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xAF, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x8C, 0x0A /* off: 36 Vcc 2 : 2700 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x6B /* Identification number.*/ , .string = "MSP430F478" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00AF /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F479" /* database IDX 6C*/ , .msg28_data= { 0xF4, 0x79 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x47 /* CONF (off: 13)*/ , 0x00, 0x00 , 0x04 /* FUSES (off: 16)*/ , 0x07 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x6C, 0x64 /*, 0x4A */ } , .msg29_data={ 0x00, 0x11, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xAF, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x8C, 0x0A /* off: 36 Vcc 2 : 2700 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x6C /* Identification number.*/ , .string = "MSP430F479" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x1100, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00AF /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F47197" /* database IDX 6D*/ , .msg28_data= { 0xF4, 0x7F /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x00 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x6D, 0x65 /*, 0x4A */ } , .msg29_data={ 0x00, 0x21, 0xFF, 0xFF, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xA4, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x11 , 0x00, 0x00 , 0x00, 0x20 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x08, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x11 , 0x00, 0x00 , 0xFF, 0x20 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x6D /* Identification number.*/ , .string = "MSP430F47197" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x2100, .mainEnd = 0x1FFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x1100, .ram2End = 0x20FF /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00A4 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 8 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 0 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F47187" /* database IDX 6E*/ , .msg28_data= { 0xF4, 0x7F /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x01 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x6E, 0x66 /*, 0x4A */ } , .msg29_data={ 0x00, 0x31, 0xFF, 0xFF, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xA4, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x11 , 0x00, 0x00 , 0x00, 0x30 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x08, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x11 , 0x00, 0x00 , 0xFF, 0x30 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x6E /* Identification number.*/ , .string = "MSP430F47187" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x3100, .mainEnd = 0x1FFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x1100, .ram2End = 0x30FF /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00A4 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 8 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 0 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F47177" /* database IDX 6F*/ , .msg28_data= { 0xF4, 0x7F /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x02 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x6F, 0x67 /*, 0x4A */ } , .msg29_data={ 0x00, 0x31, 0xFF, 0x9F, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xA4, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x11 , 0x00, 0x00 , 0x00, 0x30 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x08, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x11 , 0x00, 0x00 , 0xFF, 0x30 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x6F /* Identification number.*/ , .string = "MSP430F47177" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x3100, .mainEnd = 0x19FFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x1100, .ram2End = 0x30FF /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00A4 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 8 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 0 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F47167" /* database IDX 70*/ , .msg28_data= { 0xF4, 0x7F /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x03 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x70, 0x68 /*, 0x4A */ } , .msg29_data={ 0x00, 0x21, 0xFF, 0x8F, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xA4, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x11 , 0x00, 0x00 , 0x00, 0x20 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x08, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x11 , 0x00, 0x00 , 0xFF, 0x20 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x70 /* Identification number.*/ , .string = "MSP430F47167" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x2100, .mainEnd = 0x18FFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x1100, .ram2End = 0x20FF /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00A4 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 8 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 0 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F47196" /* database IDX 71*/ , .msg28_data= { 0xF4, 0x7F /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x04 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x71, 0x69 /*, 0x4A */ } , .msg29_data={ 0x00, 0x21, 0xFF, 0xFF, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xA4, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x11 , 0x00, 0x00 , 0x00, 0x20 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x08, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x11 , 0x00, 0x00 , 0xFF, 0x20 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x71 /* Identification number.*/ , .string = "MSP430F47196" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x2100, .mainEnd = 0x1FFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x1100, .ram2End = 0x20FF /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00A4 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 8 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 0 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F47186" /* database IDX 72*/ , .msg28_data= { 0xF4, 0x7F /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x05 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x72, 0x6A /*, 0x4A */ } , .msg29_data={ 0x00, 0x31, 0xFF, 0xFF, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xA4, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x11 , 0x00, 0x00 , 0x00, 0x30 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x08, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x11 , 0x00, 0x00 , 0xFF, 0x30 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x72 /* Identification number.*/ , .string = "MSP430F47186" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x3100, .mainEnd = 0x1FFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x1100, .ram2End = 0x30FF /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00A4 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 8 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 0 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F47176" /* database IDX 73*/ , .msg28_data= { 0xF4, 0x7F /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x06 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x73, 0x6B /*, 0x4A */ } , .msg29_data={ 0x00, 0x31, 0xFF, 0x9F, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xA4, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x11 , 0x00, 0x00 , 0x00, 0x30 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x08, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x11 , 0x00, 0x00 , 0xFF, 0x30 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x73 /* Identification number.*/ , .string = "MSP430F47176" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x3100, .mainEnd = 0x19FFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x1100, .ram2End = 0x30FF /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00A4 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 8 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 0 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F47166" /* database IDX 74*/ , .msg28_data= { 0xF4, 0x7F /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x07 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x74, 0x6C /*, 0x4A */ } , .msg29_data={ 0x00, 0x21, 0xFF, 0x8F, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x03, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xA4, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x11 , 0x00, 0x00 , 0x00, 0x20 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x08, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x11 , 0x00, 0x00 , 0xFF, 0x20 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x74 /* Identification number.*/ , .string = "MSP430F47166" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x2100, .mainEnd = 0x18FFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x1100, .ram2End = 0x20FF /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00A4 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 8 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 0 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0003 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F4152" /* database IDX 75*/ , .msg28_data= { 0x41, 0x52 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x00 /* FUSES (off: 16)*/ , 0x01 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x75, 0x6D /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x03 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xAF, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x8C, 0x0A /* off: 36 Vcc 2 : 2700 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x75 /* Identification number.*/ , .string = "MSP430F4152" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x03FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00AF /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F4132" /* database IDX 76*/ , .msg28_data= { 0x41, 0x52 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x01 /* FUSES (off: 16)*/ , 0x01 } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x76, 0x6E /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x03 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0xAF, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0x8C, 0x0A /* off: 36 Vcc 2 : 2700 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x76 /* Identification number.*/ , .string = "MSP430F4132" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x03FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00AF /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "CC430F6137" /* database IDX 77*/ , .msg28_data= { 0x61, 0x37 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x77, 0x6F /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x2B /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x07, 0x24 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_LCDB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_AES128 , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x77 /* Identification number.*/ , .string = "CC430F6137" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x2BFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "CC430F6135" /* database IDX 78*/ , .msg28_data= { 0x61, 0x35 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x78, 0x70 /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x23 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x07, 0x24 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_LCDB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_AES128 , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x78 /* Identification number.*/ , .string = "CC430F6135" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x23FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "CC430F6127" /* database IDX 79*/ , .msg28_data= { 0x61, 0x27 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x79, 0x71 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x2B /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x07, 0x24 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_LCDB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_AES128 , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x79 /* Identification number.*/ , .string = "CC430F6127" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x2BFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "CC430F6126" /* database IDX 7A*/ , .msg28_data= { 0x61, 0x26 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x7A, 0x72 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x23 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x07, 0x24 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_LCDB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_EMPTY , ETWPID_COMP_B , ETWPID_AES128 , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x7A /* Identification number.*/ , .string = "CC430F6126" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x23FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "CC430F6125" /* database IDX 7B*/ , .msg28_data= { 0x61, 0x25 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x7B, 0x73 /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x23 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x07, 0x24 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_LCDB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_EMPTY , ETWPID_COMP_B , ETWPID_AES128 , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x7B /* Identification number.*/ , .string = "CC430F6125" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x23FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "CC430F5137" /* database IDX 7C*/ , .msg28_data= { 0x51, 0x37 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x7C, 0x74 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x2B /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x07, 0x24 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_AES128 , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x7C /* Identification number.*/ , .string = "CC430F5137" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x2BFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "CC430F5135" /* database IDX 7D*/ , .msg28_data= { 0x51, 0x35 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x7D, 0x75 /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x23 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x07, 0x24 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_AES128 , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x7D /* Identification number.*/ , .string = "CC430F5135" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x23FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "CC430F5133" /* database IDX 7E*/ , .msg28_data= { 0x51, 0x33 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x7E, 0x76 /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x23 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x07, 0x24 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_AES128 , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x7E /* Identification number.*/ , .string = "CC430F5133" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x23FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5513" /* database IDX 7F*/ , .msg28_data= { 0x55, 0x13 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x7F, 0x77 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x33 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_EMPTY , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x7F /* Identification number.*/ , .string = "MSP430F5513" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x33FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5514" /* database IDX 80*/ , .msg28_data= { 0x55, 0x14 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x80, 0x78 /*, 0x4A */ } , .msg29_data={ 0x00, 0x44, 0xFF, 0x43, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x33 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_EMPTY , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x80 /* Identification number.*/ , .string = "MSP430F5514" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4400, .mainEnd = 0x143FF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x33FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5515" /* database IDX 81*/ , .msg28_data= { 0x55, 0x15 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x81, 0x79 /*, 0x4A */ } , .msg29_data={ 0x00, 0x44, 0xFF, 0x43, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x33 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_EMPTY , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x81 /* Identification number.*/ , .string = "MSP430F5515" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4400, .mainEnd = 0x143FF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x33FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5517" /* database IDX 82*/ , .msg28_data= { 0x55, 0x17 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x82, 0x7A /*, 0x4A */ } , .msg29_data={ 0x00, 0x44, 0xFF, 0xC3, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x3B /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_EMPTY , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x82 /* Identification number.*/ , .string = "MSP430F5517" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4400, .mainEnd = 0x1C3FF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x3BFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5519" /* database IDX 83*/ , .msg28_data= { 0x55, 0x19 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x83, 0x7B /*, 0x4A */ } , .msg29_data={ 0x00, 0x44, 0xFF, 0x43, 0x02, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x43 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_EMPTY , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x83 /* Identification number.*/ , .string = "MSP430F5519" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4400, .mainEnd = 0x243FF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x43FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5521" /* database IDX 84*/ , .msg28_data= { 0x55, 0x21 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x84, 0x7C /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x3B /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x84 /* Identification number.*/ , .string = "MSP430F5521" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x3BFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5522" /* database IDX 85*/ , .msg28_data= { 0x55, 0x22 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x85, 0x7D /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x43 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x85 /* Identification number.*/ , .string = "MSP430F5522" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x43FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5524" /* database IDX 86*/ , .msg28_data= { 0x55, 0x24 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x86, 0x7E /*, 0x4A */ } , .msg29_data={ 0x00, 0x44, 0xFF, 0x43, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x33 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x86 /* Identification number.*/ , .string = "MSP430F5524" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4400, .mainEnd = 0x143FF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x33FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5525" /* database IDX 87*/ , .msg28_data= { 0x55, 0x25 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x87, 0x7F /*, 0x4A */ } , .msg29_data={ 0x00, 0x44, 0xFF, 0x43, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x33 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x87 /* Identification number.*/ , .string = "MSP430F5525" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4400, .mainEnd = 0x143FF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x33FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5526" /* database IDX 88*/ , .msg28_data= { 0x55, 0x26 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x88, 0x80 /*, 0x4A */ } , .msg29_data={ 0x00, 0x44, 0xFF, 0xC3, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x3B /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x88 /* Identification number.*/ , .string = "MSP430F5526" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4400, .mainEnd = 0x1C3FF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x3BFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5527" /* database IDX 89*/ , .msg28_data= { 0x55, 0x27 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x89, 0x81 /*, 0x4A */ } , .msg29_data={ 0x00, 0x44, 0xFF, 0xC3, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x3B /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x89 /* Identification number.*/ , .string = "MSP430F5527" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4400, .mainEnd = 0x1C3FF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x3BFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5528" /* database IDX 8A*/ , .msg28_data= { 0x55, 0x28 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x8A, 0x82 /*, 0x4A */ } , .msg29_data={ 0x00, 0x44, 0xFF, 0x43, 0x02, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x43 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x8A /* Identification number.*/ , .string = "MSP430F5528" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4400, .mainEnd = 0x243FF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x43FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5529" /* database IDX 8B*/ , .msg28_data= { 0x55, 0x29 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x8B, 0x83 /*, 0x4A */ } , .msg29_data={ 0x00, 0x44, 0xFF, 0x43, 0x02, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x43 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x8B /* Identification number.*/ , .string = "MSP430F5529" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4400, .mainEnd = 0x243FF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x43FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5438A" /* database IDX 8C*/ , .msg28_data= { 0x05, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x8C, 0x84 /*, 0x4A */ } , .msg29_data={ 0x00, 0x5C, 0xFF, 0x5B, 0x04, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x5B /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TMR0_B7 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x8C /* Identification number.*/ , .string = "MSP430F5438A" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x5C00, .mainEnd = 0x45BFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x5BFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5436A" /* database IDX 8D*/ , .msg28_data= { 0x03, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x8D, 0x85 /*, 0x4A */ } , .msg29_data={ 0x00, 0x5C, 0xFF, 0x5B, 0x03, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x5B /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TMR0_B7 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x8D /* Identification number.*/ , .string = "MSP430F5436A" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x5C00, .mainEnd = 0x35BFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x5BFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5419A" /* database IDX 8E*/ , .msg28_data= { 0x01, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x8E, 0x86 /*, 0x4A */ } , .msg29_data={ 0x00, 0x5C, 0xFF, 0x5B, 0x02, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x5B /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TMR0_B7 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x8E /* Identification number.*/ , .string = "MSP430F5419A" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x5C00, .mainEnd = 0x25BFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x5BFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5437A" /* database IDX 8F*/ , .msg28_data= { 0x04, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x8F, 0x87 /*, 0x4A */ } , .msg29_data={ 0x00, 0x5C, 0xFF, 0x5B, 0x04, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x5B /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TMR0_B7 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x8F /* Identification number.*/ , .string = "MSP430F5437A" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x5C00, .mainEnd = 0x45BFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x5BFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5435A" /* database IDX 90*/ , .msg28_data= { 0x02, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x90, 0x88 /*, 0x4A */ } , .msg29_data={ 0x00, 0x5C, 0xFF, 0x5B, 0x03, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x5B /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TMR0_B7 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x90 /* Identification number.*/ , .string = "MSP430F5435A" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x5C00, .mainEnd = 0x35BFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x5BFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5418A" /* database IDX 91*/ , .msg28_data= { 0x00, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x91, 0x89 /*, 0x4A */ } , .msg29_data={ 0x00, 0x5C, 0xFF, 0x5B, 0x02, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x5B /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TMR0_B7 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x91 /* Identification number.*/ , .string = "MSP430F5418A" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x5C00, .mainEnd = 0x25BFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x5BFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5510" /* database IDX 92*/ , .msg28_data= { 0x31, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x92, 0x8A /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x33 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x92 /* Identification number.*/ , .string = "MSP430F5510" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x33FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5131" /* database IDX 93*/ , .msg28_data= { 0x26, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x93, 0x8B /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x1F /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_EMPTY , ETWPID_TA3_0 , ETWPID_TMR0_A3 , ETWPID_TMR0_D3, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_EMPTY , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x93 /* Identification number.*/ , .string = "MSP430F5131" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x1FFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5132" /* database IDX 94*/ , .msg28_data= { 0x28, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x94, 0x8C /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x1F /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_EMPTY , ETWPID_TA3_0 , ETWPID_TMR0_A3 , ETWPID_TMR0_D3, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x94 /* Identification number.*/ , .string = "MSP430F5132" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x1FFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5151" /* database IDX 95*/ , .msg28_data= { 0x2A, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x95, 0x8D /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x23 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_EMPTY , ETWPID_TA3_0 , ETWPID_TMR0_A3 , ETWPID_TMR0_D3, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_EMPTY , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x95 /* Identification number.*/ , .string = "MSP430F5151" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x23FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5152" /* database IDX 96*/ , .msg28_data= { 0x2C, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x96, 0x8E /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x23 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_EMPTY , ETWPID_TA3_0 , ETWPID_TMR0_A3 , ETWPID_TMR0_D3, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x96 /* Identification number.*/ , .string = "MSP430F5152" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x23FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5171" /* database IDX 97*/ , .msg28_data= { 0x2E, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x97, 0x8F /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x23 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_EMPTY , ETWPID_TA3_0 , ETWPID_TMR0_A3 , ETWPID_TMR0_D3, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_EMPTY , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x97 /* Identification number.*/ , .string = "MSP430F5171" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x23FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5172" /* database IDX 98*/ , .msg28_data= { 0x30, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x98, 0x90 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x23 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_EMPTY , ETWPID_TA3_0 , ETWPID_TMR0_A3 , ETWPID_TMR0_D3, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x98 /* Identification number.*/ , .string = "MSP430F5172" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x23FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5630" /* database IDX 99*/ , .msg28_data= { 0x3C, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x99, 0x91 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x02, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x63 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_EMPTY , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x99 /* Identification number.*/ , .string = "MSP430F5630" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x27FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x63FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5631" /* database IDX 9A*/ , .msg28_data= { 0x3E, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x9A, 0x92 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x03, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x63 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_EMPTY , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x9A /* Identification number.*/ , .string = "MSP430F5631" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x37FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x63FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5632" /* database IDX 9B*/ , .msg28_data= { 0x40, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x9B, 0x93 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x04, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x63 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_EMPTY , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x9B /* Identification number.*/ , .string = "MSP430F5632" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x47FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x63FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5633" /* database IDX 9C*/ , .msg28_data= { 0x42, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x9C, 0x94 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x02, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x63 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x9C /* Identification number.*/ , .string = "MSP430F5633" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x27FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x63FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5634" /* database IDX 9D*/ , .msg28_data= { 0x44, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x9D, 0x95 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x03, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x63 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x9D /* Identification number.*/ , .string = "MSP430F5634" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x37FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x63FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5635" /* database IDX 9E*/ , .msg28_data= { 0x0E, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x9E, 0x96 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x04, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x63 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x9E /* Identification number.*/ , .string = "MSP430F5635" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x47FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x63FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5636" /* database IDX 9F*/ , .msg28_data= { 0x10, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x9F, 0x97 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x02, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x63 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_DAC12 , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x9F /* Identification number.*/ , .string = "MSP430F5636" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x27FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x63FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5637" /* database IDX A0*/ , .msg28_data= { 0x12, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xA0, 0x98 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x03, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x63 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_DAC12 , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xA0 /* Identification number.*/ , .string = "MSP430F5637" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x37FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x63FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5638" /* database IDX A1*/ , .msg28_data= { 0x14, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xA1, 0x99 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x04, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x63 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_DAC12 , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xA1 /* Identification number.*/ , .string = "MSP430F5638" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x47FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x63FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6630" /* database IDX A2*/ , .msg28_data= { 0x46, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xA2, 0x9A /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x02, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x63 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_EMPTY , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_LCDB , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xA2 /* Identification number.*/ , .string = "MSP430F6630" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x27FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x63FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6631" /* database IDX A3*/ , .msg28_data= { 0x48, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xA3, 0x9B /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x03, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x63 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_EMPTY , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_LCDB , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xA3 /* Identification number.*/ , .string = "MSP430F6631" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x37FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x63FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6632" /* database IDX A4*/ , .msg28_data= { 0x4A, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xA4, 0x9C /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x04, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x63 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_EMPTY , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_LCDB , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xA4 /* Identification number.*/ , .string = "MSP430F6632" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x47FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x63FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6633" /* database IDX A5*/ , .msg28_data= { 0x4C, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xA5, 0x9D /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x02, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x63 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_LCDB , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xA5 /* Identification number.*/ , .string = "MSP430F6633" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x27FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x63FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6634" /* database IDX A6*/ , .msg28_data= { 0x4E, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xA6, 0x9E /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x03, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x63 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_LCDB , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xA6 /* Identification number.*/ , .string = "MSP430F6634" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x37FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x63FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6635" /* database IDX A7*/ , .msg28_data= { 0x16, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xA7, 0x9F /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x04, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x63 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_LCDB , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xA7 /* Identification number.*/ , .string = "MSP430F6635" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x47FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x63FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6636" /* database IDX A8*/ , .msg28_data= { 0x18, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xA8, 0xA0 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x02, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x63 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_DAC12 , ETWPID_LCDB , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xA8 /* Identification number.*/ , .string = "MSP430F6636" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x27FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x63FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6637" /* database IDX A9*/ , .msg28_data= { 0x1A, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xA9, 0xA1 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x03, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x63 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_DAC12 , ETWPID_LCDB , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xA9 /* Identification number.*/ , .string = "MSP430F6637" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x37FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x63FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6638" /* database IDX AA*/ , .msg28_data= { 0x1C, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xAA, 0xA2 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x04, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x63 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_DAC12 , ETWPID_LCDB , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xAA /* Identification number.*/ , .string = "MSP430F6638" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x47FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x63FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FR5739" /* database IDX AB*/ , .msg28_data= { 0x03, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xAB, 0xA3 /*, 0x4A */ } , .msg29_data={ 0x00, 0xC2, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x18, 0x00, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x1F /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x00, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x00, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TA3_1 , ETWPID_TA3_0 , ETWPID_TB3_2 , ETWPID_TB3_1 , ETWPID_TB3_0 , ETWPID_USCIA0 , ETWPID_USCIA1 , ETWPID_USCIB0 , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x01, 0x01 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xAB /* Identification number.*/ , .string = "MSP430FR5739" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC200, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x18FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x1FFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 1 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430L092" /* database IDX AC*/ , .msg28_data= { 0x92, 0xC0 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xAC, 0xA4 /*, 0x4A */ } , .msg29_data={ 0x00, 0x1C, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0xFF /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x04, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x17, 0x04 /* off: 26 Id devices */ , 0x90, 0x00, 0xAF, 0x00 /* off: 28 LCD MEM */ , 0x84, 0x03 /* off: 32 Vcc 0 : 900 */ , 0x08, 0x07 /* off: 34 Vcc 1 : 1800 */ , 0x00, 0x00 /* off: 36 Vcc 2 : 0 */ , 0x00, 0x00 /* off: 38 Vcc 3 : 0 */ , 0x00, 0x00 /* off: 40 Vcc 4 : 0 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x00, 0x00, 0x00, 0x00 /* off: 0 info org, len, banks */ , 0x00, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x00, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TA3_1 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_CCS , ETWPID_APOOL , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xAC /* Identification number.*/ , .string = "MSP430L092" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x1C00, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x0000, .infoEnd = 0x0000 /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0xFFFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x00AF /* LCD Memory range.*/ , .bslStart = 0x0000, .bslEnd = 0x0000 /* BSL Memory range.*/ , .vccMinOp = 0x0384, .vccMaxOp= 0x0708 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0004 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6700" /* database IDX AD*/ , .msg28_data= { 0x54, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xAD, 0xA5 /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x1F /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x07, 0x24 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR3_A2 , ETWPID_TMR1_A2, ETWPID_TMR2_A2 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_USCI , ETWPID_USCIA0 , ETWPID_USCIA1 , ETWPID_USCIB0 , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xAD /* Identification number.*/ , .string = "MSP430F6700" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x1FFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6701" /* database IDX AE*/ , .msg28_data= { 0x55, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xAE, 0xA6 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x23 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x07, 0x24 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TMR1_A2, ETWPID_TMR2_A2 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_USCI , ETWPID_USCIA0 , ETWPID_USCIA1 , ETWPID_USCIB0 , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xAE /* Identification number.*/ , .string = "MSP430F6701" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x23FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6702" /* database IDX AF*/ , .msg28_data= { 0x56, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xAF, 0xA7 /*, 0x4A */ } , .msg29_data={ 0x00, 0x40, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x2B /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x07, 0x24 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR3_A2 , ETWPID_TMR1_A2, ETWPID_TMR2_A2 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_USCI , ETWPID_USCIA0 , ETWPID_USCIA1 , ETWPID_USCIB0 , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xAF /* Identification number.*/ , .string = "MSP430F6702" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x2BFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6703" /* database IDX B0*/ , .msg28_data= { 0x57, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xB0, 0xA8 /*, 0x4A */ } , .msg29_data={ 0x00, 0x40, 0xFF, 0x3F, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x2B /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x07, 0x24 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR3_A2 , ETWPID_TMR1_A2, ETWPID_TMR2_A2 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_USCI , ETWPID_USCIA0 , ETWPID_USCIA1 , ETWPID_USCIB0 , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xB0 /* Identification number.*/ , .string = "MSP430F6703" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4000, .mainEnd = 0x13FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x2BFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6720" /* database IDX B1*/ , .msg28_data= { 0x58, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xB1, 0xA9 /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x1F /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x07, 0x24 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TMR1_A2, ETWPID_TMR2_A2 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_USCI , ETWPID_USCIA0 , ETWPID_USCIA1 , ETWPID_USCIB0 , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_SD24B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xB1 /* Identification number.*/ , .string = "MSP430F6720" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x1FFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6721" /* database IDX B2*/ , .msg28_data= { 0x59, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xB2, 0xAA /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x23 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x07, 0x24 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR3_A2 , ETWPID_TMR1_A2, ETWPID_TMR2_A2 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_USCI , ETWPID_USCIA0 , ETWPID_USCIA1 , ETWPID_USCIB0 , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_SD24B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xB2 /* Identification number.*/ , .string = "MSP430F6721" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x23FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6722" /* database IDX B3*/ , .msg28_data= { 0x60, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xB3, 0xAB /*, 0x4A */ } , .msg29_data={ 0x00, 0x40, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x2B /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x07, 0x24 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR3_A2 , ETWPID_TMR1_A2, ETWPID_TMR2_A2 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_USCI , ETWPID_USCIA0 , ETWPID_USCIA1 , ETWPID_USCIB0 , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_SD24B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xB3 /* Identification number.*/ , .string = "MSP430F6722" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x2BFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6723" /* database IDX B4*/ , .msg28_data= { 0x61, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xB4, 0xAC /*, 0x4A */ } , .msg29_data={ 0x00, 0x40, 0xFF, 0x3F, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x23 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x07, 0x24 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR3_A2 , ETWPID_TMR1_A2, ETWPID_TMR2_A2 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_USCI , ETWPID_USCIA0 , ETWPID_USCIA1 , ETWPID_USCIB0 , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_SD24B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xB4 /* Identification number.*/ , .string = "MSP430F6723" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4000, .mainEnd = 0x13FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x23FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6730" /* database IDX B5*/ , .msg28_data= { 0x62, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xB5, 0xAD /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x1F /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x07, 0x24 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR3_A2 , ETWPID_TMR1_A2, ETWPID_TMR2_A2 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_USCI , ETWPID_USCIA0 , ETWPID_USCIA1 , ETWPID_USCIB0 , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_SD24B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xB5 /* Identification number.*/ , .string = "MSP430F6730" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x1FFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6731" /* database IDX B6*/ , .msg28_data= { 0x63, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xB6, 0xAE /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x23 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x07, 0x24 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR3_A2 , ETWPID_TMR1_A2, ETWPID_TMR2_A2 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_USCI , ETWPID_USCIA0 , ETWPID_USCIA1 , ETWPID_USCIB0 , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_SD24B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xB6 /* Identification number.*/ , .string = "MSP430F6731" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x23FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6732" /* database IDX B7*/ , .msg28_data= { 0x64, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xB7, 0xAF /*, 0x4A */ } , .msg29_data={ 0x00, 0x40, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x2B /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x07, 0x24 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR3_A2 , ETWPID_TMR1_A2, ETWPID_TMR2_A2 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_USCI , ETWPID_USCIA0 , ETWPID_USCIA1 , ETWPID_USCIB0 , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_SD24B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xB7 /* Identification number.*/ , .string = "MSP430F6732" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x2BFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6733" /* database IDX B8*/ , .msg28_data= { 0x65, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xB8, 0xB0 /*, 0x4A */ } , .msg29_data={ 0x00, 0x40, 0xFF, 0x3F, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x23 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x07, 0x24 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR3_A2 , ETWPID_TMR1_A2, ETWPID_TMR2_A2 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_USCI , ETWPID_USCIA0 , ETWPID_USCIA1 , ETWPID_USCIB0 , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_SD24B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xB8 /* Identification number.*/ , .string = "MSP430F6733" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4000, .mainEnd = 0x13FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x23FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5509" /* database IDX B9*/ , .msg28_data= { 0x3A, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xB9, 0xB1 /*, 0x4A */ } , .msg29_data={ 0x00, 0xA0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x33 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xB9 /* Identification number.*/ , .string = "MSP430F5509" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xA000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x33FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5508" /* database IDX BA*/ , .msg28_data= { 0x39, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xBA, 0xB2 /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x33 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xBA /* Identification number.*/ , .string = "MSP430F5508" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x33FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5507" /* database IDX BB*/ , .msg28_data= { 0x38, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xBB, 0xB3 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x33 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xBB /* Identification number.*/ , .string = "MSP430F5507" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x33FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5506" /* database IDX BC*/ , .msg28_data= { 0x37, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xBC, 0xB4 /*, 0x4A */ } , .msg29_data={ 0x00, 0xA0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x33 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xBC /* Identification number.*/ , .string = "MSP430F5506" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xA000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x33FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5505" /* database IDX BD*/ , .msg28_data= { 0x36, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xBD, 0xB5 /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x33 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xBD /* Identification number.*/ , .string = "MSP430F5505" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x33FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5504" /* database IDX BE*/ , .msg28_data= { 0x35, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xBE, 0xB6 /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x33 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xBE /* Identification number.*/ , .string = "MSP430F5504" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x33FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5503" /* database IDX BF*/ , .msg28_data= { 0x34, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xBF, 0xB7 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x33 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xBF /* Identification number.*/ , .string = "MSP430F5503" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x33FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5502" /* database IDX C0*/ , .msg28_data= { 0x33, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xC0, 0xB8 /*, 0x4A */ } , .msg29_data={ 0x00, 0xA0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x33 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xC0 /* Identification number.*/ , .string = "MSP430F5502" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xA000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x33FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5501" /* database IDX C1*/ , .msg28_data= { 0x32, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xC1, 0xB9 /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x33 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xC1 /* Identification number.*/ , .string = "MSP430F5501" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x33FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5500" /* database IDX C2*/ , .msg28_data= { 0x3B, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xC2, 0xBA /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x33 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xC2 /* Identification number.*/ , .string = "MSP430F5500" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x33FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F12x2/F11x2" /* database IDX C3*/ , .msg28_data= { 0x12, 0x32 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xC3, 0xBB /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x02 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x00, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x00, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x13, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xC3 /* Identification number.*/ , .string = "MSP430F12x2/F11x2" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x02FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 0 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5310" /* database IDX C4*/ , .msg28_data= { 0x15, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xC4, 0xBC /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x33 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xC4 /* Identification number.*/ , .string = "MSP430F5310" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x33FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5309" /* database IDX C5*/ , .msg28_data= { 0x14, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xC5, 0xBD /*, 0x4A */ } , .msg29_data={ 0x00, 0xA0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x33 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xC5 /* Identification number.*/ , .string = "MSP430F5309" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xA000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x33FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5308" /* database IDX C6*/ , .msg28_data= { 0x13, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xC6, 0xBE /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x33 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xC6 /* Identification number.*/ , .string = "MSP430F5308" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x33FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5304" /* database IDX C7*/ , .msg28_data= { 0x12, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xC7, 0xBF /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x33 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xC7 /* Identification number.*/ , .string = "MSP430F5304" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x33FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430AFE253" /* database IDX C8*/ , .msg28_data= { 0x02, 0x53 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x00 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xC8, 0xC0 /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x03 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xDF, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x00, 0x00, 0x00, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xC8 /* Identification number.*/ , .string = "MSP430AFE253" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x03FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0000, .bslEnd = 0x0000 /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5329" /* database IDX C9*/ , .msg28_data= { 0x1B, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xC9, 0xC1 /*, 0x4A */ } , .msg29_data={ 0x00, 0x44, 0xFF, 0x43, 0x02, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x43 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xC9 /* Identification number.*/ , .string = "MSP430F5329" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4400, .mainEnd = 0x243FF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x43FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5328" /* database IDX CA*/ , .msg28_data= { 0x1A, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xCA, 0xC2 /*, 0x4A */ } , .msg29_data={ 0x00, 0x44, 0xFF, 0x43, 0x02, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x43 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xCA /* Identification number.*/ , .string = "MSP430F5328" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4400, .mainEnd = 0x243FF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x43FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5327" /* database IDX CB*/ , .msg28_data= { 0x19, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xCB, 0xC3 /*, 0x4A */ } , .msg29_data={ 0x00, 0x44, 0xFF, 0xC3, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x3B /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xCB /* Identification number.*/ , .string = "MSP430F5327" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4400, .mainEnd = 0x1C3FF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x3BFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5326" /* database IDX CC*/ , .msg28_data= { 0x18, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xCC, 0xC4 /*, 0x4A */ } , .msg29_data={ 0x00, 0x44, 0xFF, 0xC3, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x3B /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xCC /* Identification number.*/ , .string = "MSP430F5326" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4400, .mainEnd = 0x1C3FF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x3BFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5325" /* database IDX CD*/ , .msg28_data= { 0x17, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xCD, 0xC5 /*, 0x4A */ } , .msg29_data={ 0x00, 0x44, 0xFF, 0x43, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x33 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xCD /* Identification number.*/ , .string = "MSP430F5325" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4400, .mainEnd = 0x143FF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x33FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5324" /* database IDX CE*/ , .msg28_data= { 0x16, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xCE, 0xC6 /*, 0x4A */ } , .msg29_data={ 0x00, 0x44, 0xFF, 0x43, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x33 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xCE /* Identification number.*/ , .string = "MSP430F5324" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4400, .mainEnd = 0x143FF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x33FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430G2xx2" /* database IDX CF*/ , .msg28_data= { 0x24, 0x52 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xCF, 0xC7 /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x02 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x00, 0x00, 0x00, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xCF /* Identification number.*/ , .string = "MSP430G2xx2" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x02FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0000, .bslEnd = 0x0000 /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5342" /* database IDX D0*/ , .msg28_data= { 0x1E, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xD0, 0xC8 /*, 0x4A */ } , .msg29_data={ 0x00, 0x44, 0xFF, 0x43, 0x02, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x43 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xD0 /* Identification number.*/ , .string = "MSP430F5342" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4400, .mainEnd = 0x243FF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x43FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5341" /* database IDX D1*/ , .msg28_data= { 0x1D, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xD1, 0xC9 /*, 0x4A */ } , .msg29_data={ 0x00, 0x44, 0xFF, 0xC3, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x3B /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xD1 /* Identification number.*/ , .string = "MSP430F5341" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4400, .mainEnd = 0x1C3FF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x3BFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5340" /* database IDX D2*/ , .msg28_data= { 0x1C, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xD2, 0xCA /*, 0x4A */ } , .msg29_data={ 0x00, 0x44, 0xFF, 0x43, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x33 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xD2 /* Identification number.*/ , .string = "MSP430F5340" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4400, .mainEnd = 0x143FF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x33FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FW429" /* database IDX D3*/ , .msg28_data= { 0xF4, 0x29 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0x57 /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xD3, 0xCB /*, 0x4A */ } , .msg29_data={ 0x00, 0x11, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x09 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x90, 0x00, 0x9C, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x00, 0x00 /* off: 42 Has test Vpp*/ , 0x01, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x33, 0x00 /* SET */ , 0x13, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x0C, 0xFF, 0x0F, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xD3 /* Identification number.*/ , .string = "MSP430FW429" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x1100, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x09FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0090, .lcdEnd = 0x009C /* LCD Memory range.*/ , .bslStart = 0x0C00, .bslEnd = 0x0FFF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 0 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6659" /* database IDX D4*/ , .msg28_data= { 0x2B, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xD4, 0xCC /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x08, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x63 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0xFF , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_DAC12 , ETWPID_LCDB , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x0F, 0x00 /* SET */ , 0xFF, 0xFF /* SET */ , 0x0F, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xD4 /* Identification number.*/ , .string = "MSP430F6659" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x87FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x63FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0xFFFF /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6658" /* database IDX D5*/ , .msg28_data= { 0x2C, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xD5, 0xCD /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x06, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x63 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x80 , 0x00, 0x00 , 0x00, 0xFF , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_DAC12 , ETWPID_LCDB , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x80 , 0x0F, 0x00 /* SET */ , 0xFF, 0xFF /* SET */ , 0x0F, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xD5 /* Identification number.*/ , .string = "MSP430F6658" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x67FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x63FF /* RAM Memory range.*/ , .ram2Start = 0x8000, .ram2End = 0xFFFF /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6459" /* database IDX D6*/ , .msg28_data= { 0x2D, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xD6, 0xCE /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x08, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x63 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0xFF , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_DAC12 , ETWPID_LCDB , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x0F, 0x00 /* SET */ , 0xFF, 0xFF /* SET */ , 0x0F, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xD6 /* Identification number.*/ , .string = "MSP430F6459" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x87FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x63FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0xFFFF /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6458" /* database IDX D7*/ , .msg28_data= { 0x2E, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xD7, 0xCF /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x06, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x63 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x80 , 0x00, 0x00 , 0x00, 0xFF , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_DAC12 , ETWPID_LCDB , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x80 , 0x0F, 0x00 /* SET */ , 0xFF, 0xFF /* SET */ , 0x0F, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xD7 /* Identification number.*/ , .string = "MSP430F6458" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x67FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x63FF /* RAM Memory range.*/ , .ram2Start = 0x8000, .ram2End = 0xFFFF /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6457" /* database IDX D8*/ , .msg28_data= { 0x2F, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xD8, 0xD0 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x04, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x63 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0xFF , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_DAC12 , ETWPID_LCDB , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x0F, 0x00 /* SET */ , 0xFF, 0xFF /* SET */ , 0x0F, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xD8 /* Identification number.*/ , .string = "MSP430F6457" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x47FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x63FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0xFFFF /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5659" /* database IDX D9*/ , .msg28_data= { 0x30, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xD9, 0xD1 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x08, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x63 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0xFF , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_DAC12 , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x0F, 0x00 /* SET */ , 0xFF, 0xFF /* SET */ , 0x0F, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xD9 /* Identification number.*/ , .string = "MSP430F5659" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x87FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x63FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0xFFFF /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5658" /* database IDX DA*/ , .msg28_data= { 0x31, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xDA, 0xD2 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x06, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x63 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x80 , 0x00, 0x00 , 0x00, 0xFF , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_USB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_DAC12 , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x80 , 0x0F, 0x00 /* SET */ , 0xFF, 0xFF /* SET */ , 0x0F, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xDA /* Identification number.*/ , .string = "MSP430F5658" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x67FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x63FF /* RAM Memory range.*/ , .ram2Start = 0x8000, .ram2End = 0xFFFF /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5359" /* database IDX DB*/ , .msg28_data= { 0x32, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xDB, 0xD3 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x08, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x63 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0xFF , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_DAC12 , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x0F, 0x00 /* SET */ , 0xFF, 0xFF /* SET */ , 0x0F, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xDB /* Identification number.*/ , .string = "MSP430F5359" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x87FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x63FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0xFFFF /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5358" /* database IDX DC*/ , .msg28_data= { 0x33, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xDC, 0xD4 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x06, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x63 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x80 , 0x00, 0x00 , 0x00, 0xFF , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_DAC12 , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x80 , 0x0F, 0x00 /* SET */ , 0xFF, 0xFF /* SET */ , 0x0F, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xDC /* Identification number.*/ , .string = "MSP430F5358" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x67FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x63FF /* RAM Memory range.*/ , .ram2Start = 0x8000, .ram2End = 0xFFFF /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5357" /* database IDX DD*/ , .msg28_data= { 0x34, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xDD, 0xD5 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x04, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x63 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0xFF , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_DAC12 , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x0F, 0x00 /* SET */ , 0xFF, 0xFF /* SET */ , 0x0F, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xDD /* Identification number.*/ , .string = "MSP430F5357" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x47FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x63FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0xFFFF /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430G2xx3" /* database IDX DE*/ , .msg28_data= { 0x25, 0x53 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xDE, 0xD6 /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x03 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x33, 0x00 /* SET */ , 0x1F, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x00, 0x00, 0x00, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xDE /* Identification number.*/ , .string = "MSP430G2xx3" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x03FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0000, .bslEnd = 0x0000 /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430AFE233" /* database IDX DF*/ , .msg28_data= { 0x02, 0x53 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x02 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xDF, 0xD7 /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x03 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xDF, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x00, 0x00, 0x00, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xDF /* Identification number.*/ , .string = "MSP430AFE233" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x03FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0000, .bslEnd = 0x0000 /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430AFE223" /* database IDX E0*/ , .msg28_data= { 0x02, 0x53 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x03 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xE0, 0xD8 /*, 0x4A */ } , .msg29_data={ 0x00, 0xF0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x02 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xDF, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x00, 0x00, 0x00, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xE0 /* Identification number.*/ , .string = "MSP430AFE223" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xF000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x02FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0000, .bslEnd = 0x0000 /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430AFE252" /* database IDX E1*/ , .msg28_data= { 0x02, 0x53 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x04 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xE1, 0xD9 /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x03 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xDF, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x00, 0x00, 0x00, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xE1 /* Identification number.*/ , .string = "MSP430AFE252" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x03FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0000, .bslEnd = 0x0000 /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430AFE232" /* database IDX E2*/ , .msg28_data= { 0x02, 0x53 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x06 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xE2, 0xDA /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x03 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xDF, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x00, 0x00, 0x00, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xE2 /* Identification number.*/ , .string = "MSP430AFE232" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x03FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0000, .bslEnd = 0x0000 /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430AFE222" /* database IDX E3*/ , .msg28_data= { 0x02, 0x53 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x07 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xE3, 0xDB /*, 0x4A */ } , .msg29_data={ 0x00, 0xF0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x02 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xDF, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x00, 0x00, 0x00, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xE3 /* Identification number.*/ , .string = "MSP430AFE222" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xF000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x02FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0000, .bslEnd = 0x0000 /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430AFE251" /* database IDX E4*/ , .msg28_data= { 0x02, 0x53 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x08 /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xE4, 0xDC /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x03 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xDF, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x00, 0x00, 0x00, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xE4 /* Identification number.*/ , .string = "MSP430AFE251" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x03FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0000, .bslEnd = 0x0000 /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430AFE231" /* database IDX E5*/ , .msg28_data= { 0x02, 0x53 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x0A /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xE5, 0xDD /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x03 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xDF, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x00, 0x00, 0x00, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xE5 /* Identification number.*/ , .string = "MSP430AFE231" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x03FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0000, .bslEnd = 0x0000 /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430AFE221" /* database IDX E6*/ , .msg28_data= { 0x02, 0x53 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x0B /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xE6, 0xDE /*, 0x4A */ } , .msg29_data={ 0x00, 0xF0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x02 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xDF, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x00, 0x00, 0x00, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xE6 /* Identification number.*/ , .string = "MSP430AFE221" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xF000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x02FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0000, .bslEnd = 0x0000 /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430AFE250" /* database IDX E7*/ , .msg28_data= { 0x02, 0x53 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x0C /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xE7, 0xDF /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x03 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xDF, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x00, 0x00, 0x00, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xE7 /* Identification number.*/ , .string = "MSP430AFE250" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x03FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0000, .bslEnd = 0x0000 /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430AFE230" /* database IDX E8*/ , .msg28_data= { 0x02, 0x53 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x0E /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xE8, 0xE0 /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x03 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xDF, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x00, 0x00, 0x00, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xE8 /* Identification number.*/ , .string = "MSP430AFE230" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x03FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0000, .bslEnd = 0x0000 /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430AFE220" /* database IDX E9*/ , .msg28_data= { 0x02, 0x53 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0x0F /* FUSES (off: 16)*/ , 0x0F } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xE9, 0xE1 /*, 0x4A */ } , .msg29_data={ 0x00, 0xF0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x10, 0xFF, 0x10, 0x40, 0x00 /* off: 6 INFO */ , 0x00, 0x02, 0xFF, 0x02 /* off: 12 RAM */ , 0x00, 0x00, 0x02, 0x00 /* off: 16 RAM2 */ , 0x02, 0x00 /* off: 20 Breakpoints */ , 0x01, 0x00 /* off: 22 Emulation */ , 0x01, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0xD7, 0x60 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xF3, 0x00 /* SET */ , 0xDF, 0x00 /* SET */ , 0xC0, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x00, 0x00, 0x00, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x00, 0x00, 0x02, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xE9 /* Identification number.*/ , .string = "MSP430AFE220" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xF000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1000, .infoEnd = 0x10FF /* INFO Memory range */ , .ramStart = 0x0200, .ramEnd = 0x02FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x0000, .bslEnd = 0x0000 /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 2 /* Number of breakpoints.*/ , .nRegTrigger = 0 /* Number of CPU Register Trigger.*/ , .nCombinations = 2 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 0 /* Breakpoint Modes*/ , .nBreakRdWr = 0 , .nBreakRdDma = 0 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 0 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 0 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 1 /* Clock control level.*/ , .emulation = 0x0001 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5229" /* database IDX EA*/ , .msg28_data= { 0x51, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xEA, 0xE2 /*, 0x4A */ } , .msg29_data={ 0x00, 0x44, 0xFF, 0x43, 0x02, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x24, 0xFF, 0x43 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xEA /* Identification number.*/ , .string = "MSP430F5229" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4400, .mainEnd = 0x243FF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x2400, .ramEnd = 0x43FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FR5738" /* database IDX EB*/ , .msg28_data= { 0x02, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xEB, 0xE3 /*, 0x4A */ } , .msg29_data={ 0x00, 0xC2, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x18, 0x00, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x1F /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x00, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x00, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TA3_1 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_TB3_0 , ETWPID_USCIA0 , ETWPID_EMPTY , ETWPID_USCIB0 , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x01, 0x01 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xEB /* Identification number.*/ , .string = "MSP430FR5738" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC200, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x18FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x1FFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 1 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FR5735" /* database IDX EC*/ , .msg28_data= { 0x76, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xEC, 0xE4 /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x18, 0x00, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x1F /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x00, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x00, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TA3_1 , ETWPID_TA3_0 , ETWPID_TB3_2 , ETWPID_TB3_1 , ETWPID_TB3_0 , ETWPID_USCIA0 , ETWPID_USCIA1 , ETWPID_USCIB0 , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x01, 0x01 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xEC /* Identification number.*/ , .string = "MSP430FR5735" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x18FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x1FFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 1 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FR5730" /* database IDX ED*/ , .msg28_data= { 0x7C, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xED, 0xE5 /*, 0x4A */ } , .msg29_data={ 0x00, 0xF0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x18, 0x00, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x1D /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x00, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x00, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TA3_1 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_TB3_0 , ETWPID_USCIA0 , ETWPID_EMPTY , ETWPID_USCIB0 , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x01, 0x01 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xED /* Identification number.*/ , .string = "MSP430FR5730" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xF000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x18FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x1DFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 1 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FR5729" /* database IDX EE*/ , .msg28_data= { 0x7B, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xEE, 0xE6 /*, 0x4A */ } , .msg29_data={ 0x00, 0xC2, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x18, 0x00, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x1F /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x00, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x00, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TA3_1 , ETWPID_TA3_0 , ETWPID_TB3_2 , ETWPID_TB3_1 , ETWPID_TB3_0 , ETWPID_USCIA0 , ETWPID_USCIA1 , ETWPID_USCIB0 , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x01, 0x01 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xEE /* Identification number.*/ , .string = "MSP430FR5729" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC200, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x18FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x1FFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 1 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FR5728" /* database IDX EF*/ , .msg28_data= { 0x7A, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xEF, 0xE7 /*, 0x4A */ } , .msg29_data={ 0x00, 0xC2, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x18, 0x00, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x1F /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x00, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x00, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TA3_1 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_TB3_0 , ETWPID_USCIA0 , ETWPID_EMPTY , ETWPID_USCIB0 , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x01, 0x01 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xEF /* Identification number.*/ , .string = "MSP430FR5728" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC200, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x18FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x1FFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 1 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FR5725" /* database IDX F0*/ , .msg28_data= { 0x78, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xF0, 0xE8 /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x18, 0x00, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x1F /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x00, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x00, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TA3_1 , ETWPID_TA3_0 , ETWPID_TB3_2 , ETWPID_TB3_1 , ETWPID_TB3_0 , ETWPID_USCIA0 , ETWPID_USCIA1 , ETWPID_USCIB0 , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x01, 0x01 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xF0 /* Identification number.*/ , .string = "MSP430FR5725" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x18FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x1FFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 1 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FR5720" /* database IDX F1*/ , .msg28_data= { 0x70, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xF1, 0xE9 /*, 0x4A */ } , .msg29_data={ 0x00, 0xF0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x18, 0x00, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x1D /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x00, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x00, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TA3_1 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_TB3_0 , ETWPID_USCIA0 , ETWPID_EMPTY , ETWPID_USCIB0 , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x01, 0x01 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xF1 /* Identification number.*/ , .string = "MSP430FR5720" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xF000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x18FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x1DFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 1 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FR5969" /* database IDX F2*/ , .msg28_data= { 0x69, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xF2, 0xEA /*, 0x4A */ } , .msg29_data={ 0x00, 0x44, 0xFF, 0x3F, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x00, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x23 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x00, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x00, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR3_A2 , ETWPID_TMR1_A2, ETWPID_TA3_1 , ETWPID_TA3_0 , ETWPID_TMR0_B7 , ETWPID_USCIA1 , ETWPID_USCIA0 , ETWPID_USCIB0 , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_AES128 , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x01, 0x01 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xF2 /* Identification number.*/ , .string = "MSP430FR5969" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4400, .mainEnd = 0x13FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x23FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 1 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "CC430F6147" /* database IDX F3*/ , .msg28_data= { 0x35, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xF3, 0xEB /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x2B /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x07, 0x24 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_LCDB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_AES128 , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xF3 /* Identification number.*/ , .string = "CC430F6147" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x2BFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "CC430F6145" /* database IDX F4*/ , .msg28_data= { 0x36, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xF4, 0xEC /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x23 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x07, 0x24 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_LCDB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_AES128 , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xF4 /* Identification number.*/ , .string = "CC430F6145" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x23FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "CC430F6143" /* database IDX F5*/ , .msg28_data= { 0x37, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xF5, 0xED /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x23 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x07, 0x24 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_LCDB , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_AES128 , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xF5 /* Identification number.*/ , .string = "CC430F6143" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x23FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "CC430F5147" /* database IDX F6*/ , .msg28_data= { 0x38, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xF6, 0xEE /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x2B /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x07, 0x24 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_AES128 , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xF6 /* Identification number.*/ , .string = "CC430F5147" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x2BFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "CC430F5145" /* database IDX F7*/ , .msg28_data= { 0x39, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xF7, 0xEF /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x23 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x07, 0x24 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_AES128 , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xF7 /* Identification number.*/ , .string = "CC430F5145" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x23FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "CC430F5143" /* database IDX F8*/ , .msg28_data= { 0x3A, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xF8, 0xF0 /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x23 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x07, 0x24 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_AES128 , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xF8 /* Identification number.*/ , .string = "CC430F5143" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x23FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "CC430F5125" /* database IDX F9*/ , .msg28_data= { 0x3B, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xF9, 0xF1 /*, 0x4A */ } , .msg29_data={ 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x23 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x07, 0x24 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_EMPTY , ETWPID_COMP_B , ETWPID_AES128 , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xF9 /* Identification number.*/ , .string = "CC430F5125" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x23FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "CC430F5123" /* database IDX FA*/ , .msg28_data= { 0x3C, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xFA, 0xF2 /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x23 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x07, 0x24 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_EMPTY , ETWPID_COMP_B , ETWPID_AES128 , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xFA /* Identification number.*/ , .string = "CC430F5123" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x23FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6724" /* database IDX FB*/ , .msg28_data= { 0x6D, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xFB, 0xAC /*, 0x4A */ } , .msg29_data={ 0x00, 0x40, 0xFF, 0x3F, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x23 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x07, 0x24 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR3_A2 , ETWPID_TMR1_A2, ETWPID_TMR2_A2 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_USCI , ETWPID_USCIA0 , ETWPID_USCIA1 , ETWPID_USCIB0 , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_SD24B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xFB /* Identification number.*/ , .string = "MSP430F6724" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4000, .mainEnd = 0x13FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x23FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6725" /* database IDX FC*/ , .msg28_data= { 0x6E, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xFC, 0xAC /*, 0x4A */ } , .msg29_data={ 0x00, 0x40, 0xFF, 0x3F, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x23 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x07, 0x24 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR3_A2 , ETWPID_TMR1_A2, ETWPID_TMR2_A2 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_USCI , ETWPID_USCIA0 , ETWPID_USCIA1 , ETWPID_USCIB0 , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_SD24B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xFC /* Identification number.*/ , .string = "MSP430F6725" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4000, .mainEnd = 0x13FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x23FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6726" /* database IDX FD*/ , .msg28_data= { 0x6F, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xFD, 0xAC /*, 0x4A */ } , .msg29_data={ 0x00, 0x40, 0xFF, 0x3F, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x23 /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x07, 0x24 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR3_A2 , ETWPID_TMR1_A2, ETWPID_TMR2_A2 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_USCI , ETWPID_USCIA0 , ETWPID_USCIA1 , ETWPID_USCIB0 , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_SD24B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xFD /* Identification number.*/ , .string = "MSP430F6726" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4000, .mainEnd = 0x13FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x23FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6734" /* database IDX FE*/ , .msg28_data= { 0x6A, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xFE, 0xF8 /*, 0x4A */ } , .msg29_data={ 0x00, 0x40, 0xFF, 0x3F, 0x02, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x3B /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x07, 0x24 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR3_A2 , ETWPID_TMR1_A2, ETWPID_TMR2_A2 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_USCI , ETWPID_USCIA0 , ETWPID_USCIA1 , ETWPID_USCIB0 , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_SD24B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xFE /* Identification number.*/ , .string = "MSP430F6734" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4000, .mainEnd = 0x23FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x3BFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6735" /* database IDX FF*/ , .msg28_data= { 0x6B, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0xFF, 0xF8 /*, 0x4A */ } , .msg29_data={ 0x00, 0x40, 0xFF, 0x3F, 0x02, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x3B /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x07, 0x24 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR3_A2 , ETWPID_TMR1_A2, ETWPID_TMR2_A2 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_USCI , ETWPID_USCIA0 , ETWPID_USCIA1 , ETWPID_USCIB0 , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_SD24B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0xFF /* Identification number.*/ , .string = "MSP430F6735" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4000, .mainEnd = 0x23FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x3BFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6736" /* database IDX 100*/ , .msg28_data= { 0x6C, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x100, 0xF8 /*, 0x4A */ } , .msg29_data={ 0x00, 0x40, 0xFF, 0x3F, 0x02, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x3B /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x07, 0x24 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR3_A2 , ETWPID_TMR1_A2, ETWPID_TMR2_A2 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_USCI , ETWPID_USCIA0 , ETWPID_USCIA1 , ETWPID_USCIB0 , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_SD24B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x100 /* Identification number.*/ , .string = "MSP430F6736" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4000, .mainEnd = 0x23FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x3BFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 0 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 0 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5333" /* database IDX 101*/ , .msg28_data= { 0x25, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x101, 0xF9 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x02, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x43 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x101 /* Identification number.*/ , .string = "MSP430F5333" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x27FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x43FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5335" /* database IDX 102*/ , .msg28_data= { 0x27, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x102, 0xFA /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x04, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x63 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x102 /* Identification number.*/ , .string = "MSP430F5335" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x47FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x63FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5336" /* database IDX 103*/ , .msg28_data= { 0x28, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x103, 0xFB /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x02, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x63 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_DAC12 , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x103 /* Identification number.*/ , .string = "MSP430F5336" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x27FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x63FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5338" /* database IDX 104*/ , .msg28_data= { 0x2A, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x104, 0xFC /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x04, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x63 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_DAC12 , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x104 /* Identification number.*/ , .string = "MSP430F5338" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x47FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x63FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6433" /* database IDX 105*/ , .msg28_data= { 0x1F, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x105, 0xFD /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x02, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x43 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_LCDB , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x105 /* Identification number.*/ , .string = "MSP430F6433" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x27FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x43FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6435" /* database IDX 106*/ , .msg28_data= { 0x21, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x106, 0xFE /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x04, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x63 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_LCDB , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x106 /* Identification number.*/ , .string = "MSP430F6435" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x47FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x63FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6436" /* database IDX 107*/ , .msg28_data= { 0x22, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x107, 0xFF /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x02, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x63 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_DAC12 , ETWPID_LCDB , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x107 /* Identification number.*/ , .string = "MSP430F6436" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x27FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x63FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F6438" /* database IDX 108*/ , .msg28_data= { 0x24, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x108, 0x100 /*, 0x4A */ } , .msg29_data={ 0x00, 0x80, 0xFF, 0x7F, 0x04, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x63 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x04, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_DAC12 , ETWPID_LCDB , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x1C , 0xFF, 0x23 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x108 /* Identification number.*/ , .string = "MSP430F6438" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x8000, .mainEnd = 0x47FFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x63FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FR5737" /* database IDX 109*/ , .msg28_data= { 0x01, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x109, 0x101 /*, 0x4A */ } , .msg29_data={ 0x00, 0xC2, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x18, 0x00, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x1F /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x00, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x00, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TA3_1 , ETWPID_TA3_0 , ETWPID_TB3_2 , ETWPID_TB3_1 , ETWPID_TB3_0 , ETWPID_USCIA0 , ETWPID_USCIA1 , ETWPID_USCIB0 , ETWPID_EMPTY , ETWPID_RTC , ETWPID_EMPTY , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x01, 0x01 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x109 /* Identification number.*/ , .string = "MSP430FR5737" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC200, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x18FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x1FFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 1 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FR5736" /* database IDX 10A*/ , .msg28_data= { 0x77, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x10A, 0x102 /*, 0x4A */ } , .msg29_data={ 0x00, 0xC2, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x18, 0x00, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x1F /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x00, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x00, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TA3_1 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_TB3_0 , ETWPID_USCIA0 , ETWPID_EMPTY , ETWPID_USCIB0 , ETWPID_EMPTY , ETWPID_RTC , ETWPID_EMPTY , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x01, 0x01 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x10A /* Identification number.*/ , .string = "MSP430FR5736" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC200, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x18FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x1FFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 1 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FR5734" /* database IDX 10B*/ , .msg28_data= { 0x00, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x10B, 0x103 /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x18, 0x00, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x1F /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x00, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x00, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TA3_1 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_TB3_0 , ETWPID_USCIA0 , ETWPID_EMPTY , ETWPID_USCIB0 , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x01, 0x01 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x10B /* Identification number.*/ , .string = "MSP430FR5734" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x18FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x1FFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 1 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FR5733" /* database IDX 10C*/ , .msg28_data= { 0x7F, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x10C, 0x104 /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x18, 0x00, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x1F /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x00, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x00, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TA3_1 , ETWPID_TA3_0 , ETWPID_TB3_2 , ETWPID_TB3_1 , ETWPID_TB3_0 , ETWPID_USCIA0 , ETWPID_USCIA1 , ETWPID_USCIB0 , ETWPID_EMPTY , ETWPID_RTC , ETWPID_EMPTY , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x01, 0x01 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x10C /* Identification number.*/ , .string = "MSP430FR5733" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x18FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x1FFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 1 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FR5732" /* database IDX 10D*/ , .msg28_data= { 0x75, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x10D, 0x105 /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x18, 0x00, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x1F /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x00, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x00, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TA3_1 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_TB3_0 , ETWPID_USCIA0 , ETWPID_EMPTY , ETWPID_USCIB0 , ETWPID_EMPTY , ETWPID_RTC , ETWPID_EMPTY , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x01, 0x01 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x10D /* Identification number.*/ , .string = "MSP430FR5732" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x18FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x1FFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 1 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FR5731" /* database IDX 10E*/ , .msg28_data= { 0x7E, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x10E, 0x106 /*, 0x4A */ } , .msg29_data={ 0x00, 0xF0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x18, 0x00, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x1D /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x00, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x00, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TA3_1 , ETWPID_TA3_0 , ETWPID_TB3_2 , ETWPID_TB3_1 , ETWPID_TB3_0 , ETWPID_USCIA0 , ETWPID_USCIA1 , ETWPID_USCIB0 , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x01, 0x01 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x10E /* Identification number.*/ , .string = "MSP430FR5731" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xF000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x18FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x1DFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 1 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FR5727" /* database IDX 10F*/ , .msg28_data= { 0x79, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x10F, 0x107 /*, 0x4A */ } , .msg29_data={ 0x00, 0xC2, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x18, 0x00, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x1F /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x00, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x00, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TA3_1 , ETWPID_TA3_0 , ETWPID_TB3_2 , ETWPID_TB3_1 , ETWPID_TB3_0 , ETWPID_USCIA0 , ETWPID_USCIA1 , ETWPID_USCIB0 , ETWPID_EMPTY , ETWPID_RTC , ETWPID_EMPTY , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x01, 0x01 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x10F /* Identification number.*/ , .string = "MSP430FR5727" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC200, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x18FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x1FFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 1 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FR5726" /* database IDX 110*/ , .msg28_data= { 0x74, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x110, 0x108 /*, 0x4A */ } , .msg29_data={ 0x00, 0xC2, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x18, 0x00, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x1F /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x00, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x00, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TA3_1 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_TB3_0 , ETWPID_USCIA0 , ETWPID_EMPTY , ETWPID_USCIB0 , ETWPID_EMPTY , ETWPID_RTC , ETWPID_EMPTY , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x01, 0x01 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x110 /* Identification number.*/ , .string = "MSP430FR5726" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xC200, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x18FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x1FFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 1 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FR5724" /* database IDX 111*/ , .msg28_data= { 0x73, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x111, 0x109 /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x18, 0x00, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x1F /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x00, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x00, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TA3_1 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_TB3_0 , ETWPID_USCIA0 , ETWPID_EMPTY , ETWPID_USCIB0 , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x01, 0x01 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x111 /* Identification number.*/ , .string = "MSP430FR5724" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x18FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x1FFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 1 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FR5723" /* database IDX 112*/ , .msg28_data= { 0x72, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x112, 0x10A /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x18, 0x00, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x1F /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x00, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x00, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TA3_1 , ETWPID_TA3_0 , ETWPID_TB3_2 , ETWPID_TB3_1 , ETWPID_TB3_0 , ETWPID_USCIA0 , ETWPID_USCIA1 , ETWPID_USCIB0 , ETWPID_EMPTY , ETWPID_RTC , ETWPID_EMPTY , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x01, 0x01 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x112 /* Identification number.*/ , .string = "MSP430FR5723" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x18FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x1FFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 1 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FR5722" /* database IDX 113*/ , .msg28_data= { 0x71, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x113, 0x10B /*, 0x4A */ } , .msg29_data={ 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x18, 0x00, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x1F /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x00, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x00, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TA3_1 , ETWPID_TA3_0 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_TB3_0 , ETWPID_USCIA0 , ETWPID_EMPTY , ETWPID_USCIB0 , ETWPID_EMPTY , ETWPID_RTC , ETWPID_EMPTY , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x01, 0x01 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x113 /* Identification number.*/ , .string = "MSP430FR5722" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xE000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x18FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x1FFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 1 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430FR5721" /* database IDX 114*/ , .msg28_data= { 0x77, 0x80 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x114, 0x10C /*, 0x4A */ } , .msg29_data={ 0x00, 0xF0, 0xFF, 0xFF, 0x00, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x18, 0x00, 0x00 /* off: 6 INFO */ , 0x00, 0x1C, 0xFF, 0x1D /* off: 12 RAM */ , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x00, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ , 0x00, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TA3_1 , ETWPID_TA3_0 , ETWPID_TB3_2 , ETWPID_TB3_1 , ETWPID_TB3_0 , ETWPID_USCIA0 , ETWPID_USCIA1 , ETWPID_USCIB0 , ETWPID_EMPTY , ETWPID_RTC , ETWPID_ADC10_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x00, 0x01, 0x01 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x114 /* Identification number.*/ , .string = "MSP430FR5721" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xF000, .mainEnd = 0xFFFF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x18FF /* INFO Memory range */ , .ramStart = 0x1C00, .ramEnd = 0x1DFF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 1 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 0 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 0 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5228" /* database IDX 115*/ , .msg28_data= { 0x50, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x115, 0x10D /*, 0x4A */ } , .msg29_data={ 0x00, 0x44, 0xFF, 0xC3, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x24, 0xFF, 0x43 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x115 /* Identification number.*/ , .string = "MSP430F5228" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4400, .mainEnd = 0x1C3FF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x2400, .ramEnd = 0x43FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5227" /* database IDX 116*/ , .msg28_data= { 0x4F, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x116, 0x10E /*, 0x4A */ } , .msg29_data={ 0x00, 0x44, 0xFF, 0x43, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x24, 0xFF, 0x43 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x116 /* Identification number.*/ , .string = "MSP430F5227" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4400, .mainEnd = 0x143FF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x2400, .ramEnd = 0x43FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5224" /* database IDX 117*/ , .msg28_data= { 0x4C, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x117, 0x10F /*, 0x4A */ } , .msg29_data={ 0x00, 0x44, 0xFF, 0x43, 0x02, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x24, 0xFF, 0x43 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x117 /* Identification number.*/ , .string = "MSP430F5224" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4400, .mainEnd = 0x243FF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x2400, .ramEnd = 0x43FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5223" /* database IDX 118*/ , .msg28_data= { 0x4B, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x118, 0x110 /*, 0x4A */ } , .msg29_data={ 0x00, 0x44, 0xFF, 0xC3, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x24, 0xFF, 0x43 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x118 /* Identification number.*/ , .string = "MSP430F5223" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4400, .mainEnd = 0x1C3FF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x2400, .ramEnd = 0x43FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5222" /* database IDX 119*/ , .msg28_data= { 0x4A, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x119, 0x111 /*, 0x4A */ } , .msg29_data={ 0x00, 0x44, 0xFF, 0x43, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x24, 0xFF, 0x43 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x119 /* Identification number.*/ , .string = "MSP430F5222" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4400, .mainEnd = 0x143FF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x2400, .ramEnd = 0x43FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5219" /* database IDX 11A*/ , .msg28_data= { 0x47, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x11A, 0x112 /*, 0x4A */ } , .msg29_data={ 0x00, 0x44, 0xFF, 0x43, 0x02, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x24, 0xFF, 0x43 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_EMPTY , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x11A /* Identification number.*/ , .string = "MSP430F5219" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4400, .mainEnd = 0x243FF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x2400, .ramEnd = 0x43FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5218" /* database IDX 11B*/ , .msg28_data= { 0x46, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x11B, 0x113 /*, 0x4A */ } , .msg29_data={ 0x00, 0x44, 0xFF, 0xC3, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x24, 0xFF, 0x43 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_EMPTY , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x11B /* Identification number.*/ , .string = "MSP430F5218" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4400, .mainEnd = 0x1C3FF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x2400, .ramEnd = 0x43FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5217" /* database IDX 11C*/ , .msg28_data= { 0x45, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x11C, 0x114 /*, 0x4A */ } , .msg29_data={ 0x00, 0x44, 0xFF, 0x43, 0x01, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x24, 0xFF, 0x43 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_EMPTY , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x11C /* Identification number.*/ , .string = "MSP430F5217" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4400, .mainEnd = 0x143FF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x2400, .ramEnd = 0x43FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5214" /* database IDX 11D*/ , .msg28_data= { 0x42, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x11D, 0xE2 /*, 0x4A */ } , .msg29_data={ 0x00, 0x44, 0xFF, 0x43, 0x02, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x24, 0xFF, 0x43 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x11D /* Identification number.*/ , .string = "MSP430F5214" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4400, .mainEnd = 0x243FF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x2400, .ramEnd = 0x43FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5213" /* database IDX 11E*/ , .msg28_data= { 0x41, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x11E, 0xE2 /*, 0x4A */ } , .msg29_data={ 0x00, 0x44, 0xFF, 0x43, 0x02, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x24, 0xFF, 0x43 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x11E /* Identification number.*/ , .string = "MSP430F5213" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4400, .mainEnd = 0x243FF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x2400, .ramEnd = 0x43FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5212" /* database IDX 11F*/ , .msg28_data= { 0x40, 0x81 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x11F, 0xE2 /*, 0x4A */ } , .msg29_data={ 0x00, 0x44, 0xFF, 0x43, 0x02, 0x00 /* off: 0 ROM */ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x24, 0xFF, 0x43 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x08, 0x00 /* off: 20 Breakpoints */ , 0x07, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x1F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x20, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TA3_1 , ETWPID_TMR0_B7, ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_COMP_B , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x00, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x11F /* Identification number.*/ , .string = "MSP430F5212" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0x4400, .mainEnd = 0x243FF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x2400, .ramEnd = 0x43FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 8 /* Number of breakpoints.*/ , .nRegTrigger = 2 /* Number of CPU Register Trigger.*/ , .nCombinations = 10 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 2 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0007 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, { .name= "MSP430F5255" /* database IDX 8F*/ , .msg28_data= { 0x03, 0x82 /* ID (off: 0)*/ , 0xFF /* REV (off: 2)*/ , 0xFF /* FAB (off: 3)*/ , 0x00, 0x00, 0x00, 0x00 , 0xFF /* SELF0 (off: 8)*/ , 0xFF /* SELF1 (off: 9)*/ , 0x00, 0x00, 0x00 , 0xFF /* CONF (off: 13)*/ , 0x00, 0x00 , 0xFF /* FUSES (off: 16)*/ , 0xFF } /* F PATT (off: 17)*/ , .msg29_params={ 0x00, 0x8F, 0x87 /*, 0x4A */ } /* copied from MSP430F5437A - could not find this in datasheet */ , .msg29_data={ 0x00, 0xA4, 0xFF, 0xA3, 0x02, 0x00 /* off: 0 ROM */ /* values entered according to MSP430F5255 datasheet*/ , 0x00, 0x18, 0xFF, 0x19, 0x80, 0x00 /* off: 6 INFO */ , 0x00, 0x24, 0xFF, 0xA3 /* off: 12 RAM */ , 0x00, 0x00, 0x08, 0x00 /* off: 16 RAM2 */ , 0x03, 0x00 /* off: 20 Breakpoints */ , 0x05, 0x00 /* off: 22 Emulation */ , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ , 0x0F, 0x04 /* off: 26 Id devices */ , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ , 0x01, 0x00 /* off: 42 Has test Vpp*/ , 0x03, 0x00 /* off: 44 3-> Default clock control */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */ , 0xFF, 0x00 /* SET */} , .msg2b_len= 0x4A , .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ /* msg2b copied from MSP430F5437A - unmodified - probably wrong */ , 0x02, 0x02, 0x00, 0x0A, 0x00 /* off: 5 ram org, len, banks */ , 0x40, 0x00 /* off: 10 BYTE FLAGS ?? */ , ETWPID_WDT_A , ETWPID_TMR0_A5 , ETWPID_TA3_0 , ETWPID_TMR0_B7 , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_USCI0 , ETWPID_USCI1 , ETWPID_USCI2 , ETWPID_USCI3 , ETWPID_RTC , ETWPID_ADC12_A , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , ETWPID_EMPTY , 0x01, 0x01, 0x00, 0x00 /* off: 28 BYTE FLAGS ?? */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x02, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x01, 0x00 /* SET */ , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 , 0x00, 0x00 } #ifdef MSP430_STORED_INFO , .endian = 0xAA55 /* The value 0xaa55. */ , .id = 0x200 /* Identification number.*/ , .string = "MSP430F5255" , .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ , .coreIpId = 0x0000 /* The CoreIP ID.*/ , .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ , .mainStart = 0xA400, .mainEnd = 0x2A3FF /* MAIN Memory range */ , .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ , .ramStart = 0x2400, .ramEnd = 0xA3FF /* RAM Memory range.*/ , .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ , .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ , .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ , .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ , .hasFramMemory = 0 /* FRAM Memory type */ , .hasTestVpp = 1 /* Device has TEST/VPP.*/ , .nBreakpoints = 3 /* Number of breakpoints.*/ , .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ , .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ , .nBreakOps = 1 /* Breakpoint Modes*/ , .nBreakRdWr = 1 , .nBreakRdDma = 1 , .TrigerMask = 1 /* Trigger Mask for Breakpoint */ , .nRegTriggerMod= 1 /* Register Trigger modes*/ , .nStateStorage = 1 /* MSP430 has Stage Storage*/ , .nCycleCount = 1 /* Number of cycle counters of MSP430*/ , .nCycleCountOps= 1 /* Cycle couter modes*/ , .nSequencer = 1 /* Msp430 has Sequencer*/ , .clockControl = 2 /* Clock control level.*/ , .emulation = 0x0005 /* Emulation level.*/ , .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ , .eemVersion = 0x2800 /* The EEM Version Number.*/ #endif }, }; const struct fet_db_record *fet_db_find_by_msg28(uint8_t *data, int len ) { int i; for (i = 0; i < ARRAY_LEN(fet_db); i++) { const struct fet_db_record *r = &fet_db[i]; if ( r->msg28_data[ 0 ] != data[ 0 ] ) { continue; } /* ID (off: 0), mandatory */ if ( r->msg28_data[ 1 ] != data[ 1 ] ) { continue; } /* ID (off: 1), mandatory */ if (( r->msg28_data[ 2 ] != 0xFF ) && ( r->msg28_data[ 2 ] != data[ 2 ] )) { continue; } /* REV (off: 2), optional */ if (( r->msg28_data[ 3 ] != 0xFF ) && ( r->msg28_data[ 3 ] != data[ 3 ] )) { continue; } /* FAB (off: 3), optional */ if (( r->msg28_data[ 9 ] != 0xFF ) && ( r->msg28_data[ 9 ] != data[ 9 ] )) { continue; } /* SELF 1 (off: 9), optional */ if (( r->msg28_data[ 13 ] != 0xFF ) && ( r->msg28_data[ 13 ] != data[ 13 ] )) { continue; } /* CONF (off: 25), optional */ if (( r->msg28_data[ 16 ] != 0xFF ) && ( r->msg28_data[ 16 ] != data[ 16 ] )) { continue; } /* FUSES (off: 28), optional */ #ifdef MSP430_STORED_INFO r->jtagId = r->msg28_data[ 18 ]; /* The JTAG ID - value returned on an instruction shift.*/ r->coreIpId = (uint16_t)data[ 19 ] | (uint16_t)data[ 20 ] << 8; r->deviceIdPtr= (uint16_t)data[ 21 ] | (uint16_t)data[ 22 ] << 8; r->eemVersion = (uint16_t)data[ 24 ] | (uint16_t)data[ 25 ] << 8; #endif return( r ); } return NULL; } const struct fet_db_record *fet_db_find_by_name(const char *name) { int i; for (i = 0; i < ARRAY_LEN(fet_db); i++) { const struct fet_db_record *r = &fet_db[i]; if (!strcasecmp(r->name, name)) return r; } return NULL; } int fet_db_enum(fet_db_enum_func_t func, void *user_data) { int i; for (i = 0; i < ARRAY_LEN(fet_db); i++) if (func(user_data, &fet_db[i]) < 0) return -1; return 0; } mspdebug-0.25/drivers/fet_db.h000066400000000000000000000035641313531517500163340ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef FET_DB_H_ #define FET_DB_H_ #include #define FET_DB_MSG28_LEN 0x12 #define FET_DB_MSG29_PARAMS 3 #define FET_DB_MSG29_LEN 0x4a #define FET_DB_MSG2B_LEN 0x4a struct fet_db_record { const char *name; uint8_t msg28_data[FET_DB_MSG28_LEN]; int msg29_params[FET_DB_MSG29_PARAMS]; uint8_t msg29_data[FET_DB_MSG29_LEN]; uint8_t msg2b_data[FET_DB_MSG2B_LEN]; int msg2b_len; }; /* Find a record in the database by its response to message 0x28. The * first two bytes _must_ match, and the remaining bytes should match * as much as possible. */ const struct fet_db_record *fet_db_find_by_msg28(uint8_t *data, int len); /* Find a record in the database by name. The search is case-insensitive. */ const struct fet_db_record *fet_db_find_by_name(const char *name); /* Call the given enumeration function for all records in the database. */ typedef int (*fet_db_enum_func_t)(void *user_data, const struct fet_db_record *rec); int fet_db_enum(fet_db_enum_func_t func, void *user_data); #endif mspdebug-0.25/drivers/fet_error.c000066400000000000000000000161541313531517500170720ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * * Various constants and tables come from uif430, written by Robert * Kavaler (kavaler@diva.com). This is available under the same license * as this program, from www.relavak.com. */ #include "util.h" /* These messages come from uif430 and from MSP430.DLL V3. */ static const char *error_strings[] = { /* 0 */ "No error", /* 1 */ "Could not initialize device interface", /* 2 */ "Could not close device interface", /* 3 */ "Invalid parameter(s)", /* 4 */ "Could not find device or device not supported", /* 5 */ "Unknown device", /* 6 */ "Could not read device memory", /* 7 */ "Could not write device memory", /* 8 */ "Could not read device configuration fuses", /* 9 */ "Incorrectly configured device; device derivative not supported", /* 10 */ "Could not set device Vcc", /* 11 */ "Could not reset device", /* 12 */ "Could not preserve/restore device memory", /* 13 */ "Could not set device operating frequency", /* 14 */ "Could not erase device memory", /* 15 */ "Could not set device breakpoint", /* 16 */ "Could not single step device", /* 17 */ "Could not run device (to breakpoint)", /* 18 */ "Could not determine device state", /* 19 */ "Could not open Enhanced Emulation Module", /* 20 */ "Could not read Enhanced Emulation Module register", /* 21 */ "Could not write Enhanced Emulation Module register", /* 22 */ "Could not close Enhanced Emulation Module", /* 23 */ "File open error", /* 24 */ "File type could not be identified", /* 25 */ "File end error", /* 26 */ "File input/output error", /* 27 */ "File data error", /* 28 */ "Verification error", /* 29 */ "Could not blow device security fuse", /* 30 */ "Security fuse has been blown", /* 31 */ "Error within Intel hex file", /* 32 */ "Could not write device register", /* 33 */ "Could not read device register", /* 34 */ "Not supported by selected interface or interface is not initialized", /* 35 */ "Interface communication error", /* 36 */ "No external power supply detected", /* 37 */ "External power too low", /* 38 */ "External power detected", /* 39 */ "External power too high", /* 40 */ "Hardware self test error", /* 41 */ "Fast flash routine experienced a timeout", /* 42 */ "Could not create thread for polling", /* 43 */ "Could not initialize Enhanced Emulation Module", /* 44 */ "Insufficent resources", /* 45 */ "No clock control emulation on connected device", /* 46 */ "No state storage buffer implemented on connected device", /* 47 */ "Could not read trace buffer", /* 48 */ "Enable the variable watch function", /* 49 */ "No trigger sequencer implemented on connected device", /* 50 */ "Could not read sequencer state - sequencer is disabled", /* 51 */ "Could not remove trigger - used in sequencer", /* 52 */ "Could not set combination - trigger is used in sequencer", /* 53 */ "System Protection Module A is enabled - device locked", /* 54 */ "Invalid SPMA key was passed to the target device - device locked", /* 55 */ "Device does not accept any further SPMA keys - device locked", /* 56 */ "MSP-FET430UIF Firmware erased - bootloader active", /* 57 */ "Could not find MSP-FET430UIF on specified COM port", /* 58 */ "MSP-FET430UIF is already in use", /* 59 */ "EEM polling thread is already active", /* 60 */ "Could not terminate EEM polling thread", /* 61 */ "Could not unlock BSL memory segments", /* 62 */ "Could not perform access, BSL memory segments are protected", /* 63 */ "Another device as selected was found", /* 64 */ "Could not enable JTAG wrong password", /* 65 */ "Only one UIF must be connected during update to v3", /* 66 */ "CDC-USB-FET driver was not installed, please install the driver", /* 67 */ "Manual reboot of USB-FET needed! PLEASE unplug and reconnect your USB-FET!", /* 68 */ "Internal error", /* 69 */ "One of the connected eZ-FET debuggers needs recovery", /* Yes, this is actually repeated */ /* 70 */ "One of the connected eZ-FET debuggers needs recovery", /* twice in SLAC460f MSP430.h */ /* 71 */ "Feature not supported", /* 72 */ "Only one eZ-FET must be connected during recovery", /* 73 */ "eZ-FET recovery failed", /* 74 */ "eZ-FET core(communication layer) update failed", /* 75 */ "eZ-FET legacy module update failed", /* 76 */ "Energy Trace is not supported by the selected hardware", /* 77 */ "Hardware State is unknown", /* 78 */ "Device configuration data inconsistent. " "Please discontinue using/replace target device.", /* 79 */ "EEM module not accessible while running in Ultra Low Power Debug Mode - " "Deactivate Ultra Low Power Debug mode to enable this feature", /* 80 */ "Failed to remove software breakpoints, please reprogram target device", /* 81 */ "Trigger configuration conflicts with existing triggers", /* 82 */ "Operation not possible while device is running", /* 83 */ "This function can not be used when software breakpoints are enabled", /* 84 */ "JTAG/SBW speed configuration failed", /* 85 */ "Software breakpoint can't be set (followed by critical value)", /* 86 */ "EnergyTrace is not supported by selected MSP430 device", /* 87 */ "EnergyTrace requires Ultra-Low Power debug / LPMx.5 enabled", /* 88 */ "Legacy version of silicon used, which is no longer supported. " "Please contact TI to obtain a newer version.", /* 89 */ "Secure device via the IDE is not supported. See Device User Guide " "for further information.", /* 90 */ "Cycle counter is in basic mode. Set to advanced mode to use this function.", /* 91 */ "Parallel port FET (MSP-FETP430IF) is no longer supported.", /* 92 */ "Wrong target architecture was selected. " "Valid architectures are MSP430 or MSP432_M4.", /* 93 */ "Mass erase executed. Please power-cycle your device and restart the debug session.", /* 94 */ "Your connected hardware might drain too much power from the debugger. " "This results in an overcurrent.", /* 95 */ "MSP Tool firmware update failed. Please ensure the USB or Backchannel " "UART connection is not in use.", /* 96 */ "MSP432 devices are not supported using the MSPFET430-UIF", /* 97 */ "DAP is locked or wrong debug protocol selected.", /* 98 */ "Device database not loaded.", /* 99 */ "Invalid error number", }; const char *fet_error(int code) { if (code < 0 || code >= ARRAY_LEN(error_strings)) return "Unknown error"; return error_strings[code]; } mspdebug-0.25/drivers/fet_error.h000066400000000000000000000017421313531517500170740ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef FET_ERROR_H_ #define FET_ERROR_H_ /* Translate an error code received from a FET into a string that can * be displayed to the user. */ const char *fet_error(int code); #endif mspdebug-0.25/drivers/fet_olimex_db.c000066400000000000000000011215071313531517500177030ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * Copyright (C) 2012 Stanimir Bonev * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include "fet_olimex_db.h" #include "devicelist.h" #include "util.h" #define ID0_OFFSET 0 #define ID1_OFFSET 1 #define REV_OFFSET 2 #define FAB_ID_OFFSET 3 #define SELF_TEST0_OFFSET 8 #define SELF_TEST1_OFFSET 9 #define EMB_SYS_OFFSET 13 static const struct fet_olimex_db_record fet_olimex_db[] = { [DT_MSP430F11x1] = { .name = "Prototype_MSP430F11x1", .msg29_params = {0x00, 0x01, 0x01}, .msg29_data = { 0x00, 0xf0, 0xff, 0xff, 0x00, 0x00, 0x00, 0xef, 0xff, 0xef, 0x80, 0x00, 0x00, 0x02, 0xff, 0x02, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0xff, 0x13, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F11x1D] = { .name = "MSP430F11x1", .msg29_params = {0x00, 0x02, 0x02}, .msg29_data = { 0x00, 0xf0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x02, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0xff, 0x13, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F133] = { .name = "MSP430F133", .msg29_params = {0x00, 0x03, 0x03}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x02, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x02, 0x00, 0x00, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf3, 0x30, 0xd3, 0x30, 0xc0, 0x30, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F135] = { .name = "MSP430F135", .msg29_params = {0x00, 0x04, 0x04}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x02, 0x00, 0x00, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf3, 0x30, 0xd3, 0x30, 0xc0, 0x30, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F147] = { .name = "MSP430F147", .msg29_params = {0x00, 0x05, 0x05}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x05, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x02, 0x00, 0x00, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf3, 0x30, 0xd3, 0x30, 0xc0, 0x30, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F148] = { .name = "MSP430F148", .msg29_params = {0x00, 0x06, 0x06}, .msg29_data = { 0x00, 0x40, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x02, 0x00, 0x00, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf3, 0x30, 0xd3, 0x30, 0xc0, 0x30, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F149] = { .name = "MSP430F149", .msg29_params = {0x00, 0x07, 0x07}, .msg29_data = { 0x00, 0x11, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x02, 0x00, 0x00, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf3, 0x30, 0xd3, 0x30, 0xc0, 0x30, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F413P] = { .name = "Preliminary_MSP430F413", .msg29_params = {0x00, 0x08, 0x08}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x02, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x90, 0x00, 0x9c, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x33, 0x80, 0x13, 0x80, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F41xC] = { .name = "MSP430F41x", .msg29_params = {0x00, 0x09, 0x09}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x02, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x90, 0x00, 0x9c, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x33, 0x80, 0x13, 0x80, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F11x1A] = { .name = "MSP430F11x1A", .msg29_params = {0x00, 0x0a, 0x0a}, .msg29_data = { 0x00, 0xf0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x02, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0xff, 0x13, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F12x] = { .name = "MSP430F12x", .msg29_params = {0x00, 0x0b, 0x0b}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x02, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x03, 0x13, 0x03, 0xff, 0x03, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F43x] = { .name = "MSP430F43x", .msg29_params = {0x00, 0x0c, 0x0c}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x05, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xa4, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xf3, 0x80, 0xd3, 0x80, 0xc0, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x02, 0x00, 0x08, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F44x] = { .name = "MSP430F44x", .msg29_params = {0x00, 0x0e, 0x0d}, .msg29_data = { 0x00, 0x11, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xa4, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xf3, 0xb0, 0xd3, 0xb0, 0xc0, 0x30, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x02, 0x00, 0x08, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F12x2] = { .name = "Preliminary_MSP430F12x2", .msg29_params = {0x00, 0x0f, 0x0e}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x02, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x03, 0x13, 0x03, 0xff, 0x03, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F11x2] = { .name = "MSP430F11x2", .msg29_params = {0x00, 0x10, 0x0f}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x02, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0xff, 0x13, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F12x2C] = { .name = "MSP430F12x2/F11x2", .msg29_params = {0x00, 0x11, 0x10}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x02, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x03, 0x13, 0x03, 0xff, 0x03, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_PMS430F16x] = { .name = "Preliminary_MSP430F16x", .msg29_params = {0x00, 0x12, 0x11}, .msg29_data = { 0x00, 0x11, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x02, 0x00, 0x00, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf3, 0x30, 0xd3, 0x30, 0xc0, 0x30, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FE423] = { .name = "MSP430FE423", .msg29_params = {0x00, 0x19, 0x12}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x02, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xa4, 0x00, 0x8c, 0x0a, 0x10, 0x0e, 0x8c, 0x0a, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xf3, 0x80, 0xd3, 0x80, 0xc0, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FE425] = { .name = "MSP430FE425", .msg29_params = {0x00, 0x1a, 0x13}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xa4, 0x00, 0x8c, 0x0a, 0x10, 0x0e, 0x8c, 0x0a, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xf3, 0x80, 0xd3, 0x80, 0xc0, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FE427] = { .name = "MSP430FE427", .msg29_params = {0x00, 0x1b, 0x14}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x05, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xa4, 0x00, 0x8c, 0x0a, 0x10, 0x0e, 0x8c, 0x0a, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xf3, 0x80, 0xd3, 0x80, 0xc0, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F423] = { .name = "MSP430F423", .msg29_params = {0x00, 0x1c, 0x15}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x02, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xa4, 0x00, 0x8c, 0x0a, 0x10, 0x0e, 0x8c, 0x0a, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xf3, 0x80, 0xd3, 0x80, 0xc0, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F425] = { .name = "MSP430F425", .msg29_params = {0x00, 0x1d, 0x16}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xa4, 0x00, 0x8c, 0x0a, 0x10, 0x0e, 0x8c, 0x0a, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xf3, 0x80, 0xd3, 0x80, 0xc0, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F427] = { .name = "MSP430F427", .msg29_params = {0x00, 0x1e, 0x17}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x05, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xa4, 0x00, 0x8c, 0x0a, 0x10, 0x0e, 0x8c, 0x0a, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xf3, 0x80, 0xd3, 0x80, 0xc0, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FW42x] = { .name = "MSP430FW42x/F41x", .msg29_params = {0x00, 0x1f, 0x18}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x05, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x90, 0x00, 0x9c, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x33, 0x80, 0x13, 0x80, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F4230] = { .name = "MSP430F4230", .msg29_params = {0x00, 0x20, 0x19}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x02, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xaf, 0x00, 0x08, 0x07, 0x10, 0x0e, 0x8c, 0x0a, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x33, 0x80, 0x1f, 0x80, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F4250] = { .name = "MSP430F4250", .msg29_params = {0x00, 0x21, 0x1a}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x02, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xaf, 0x00, 0x08, 0x07, 0x10, 0x0e, 0x8c, 0x0a, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x33, 0x80, 0x1f, 0x80, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F42x0] = { .name = "MSP430F42x0", .msg29_params = {0x00, 0x22, 0x1b}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x02, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xaf, 0x00, 0x08, 0x07, 0x10, 0x0e, 0x8c, 0x0a, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x33, 0x80, 0x1f, 0x80, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F155] = { .name = "MSP430F155", .msg29_params = {0x00, 0x23, 0x1c}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf3, 0xff, 0xd3, 0xff, 0xc0, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x02, 0x00, 0x08, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F156] = { .name = "MSP430F156", .msg29_params = {0x00, 0x24, 0x1d}, .msg29_data = { 0x00, 0xa0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x05, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf3, 0xff, 0xd3, 0xff, 0xc0, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x02, 0x00, 0x08, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F157] = { .name = "MSP430F157", .msg29_params = {0x00, 0x25, 0x1e}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x05, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf3, 0xff, 0xd3, 0xff, 0xc0, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x02, 0x00, 0x08, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F167] = { .name = "MSP430F167", .msg29_params = {0x00, 0x26, 0x1f}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x05, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf3, 0x30, 0xd3, 0x30, 0xc0, 0x30, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x02, 0x00, 0x08, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F168] = { .name = "MSP430F168", .msg29_params = {0x00, 0x27, 0x20}, .msg29_data = { 0x00, 0x40, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf3, 0x30, 0xd3, 0x30, 0xc0, 0x30, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x02, 0x00, 0x08, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F169] = { .name = "MSP430F169", .msg29_params = {0x00, 0x28, 0x21}, .msg29_data = { 0x00, 0x11, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf3, 0x30, 0xd3, 0x30, 0xc0, 0x30, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x02, 0x00, 0x08, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F1610] = { .name = "MSP430F1610", .msg29_params = {0x00, 0x29, 0x22}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf3, 0x30, 0xd3, 0x30, 0xc0, 0x30, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x02, 0x00, 0x08, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0xff, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F1611] = { .name = "MSP430F1611", .msg29_params = {0x00, 0x2a, 0x23}, .msg29_data = { 0x00, 0x40, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf3, 0x30, 0xd3, 0x30, 0xc0, 0x30, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x02, 0x00, 0x08, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0xff, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F1612] = { .name = "MSP430F1612", .msg29_params = {0x00, 0x2b, 0x24}, .msg29_data = { 0x00, 0x25, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf3, 0x30, 0xd3, 0x30, 0xc0, 0x30, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x02, 0x00, 0x08, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0xff, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FG43x] = { .name = "MSP430FG43x_F43x", .msg29_params = {0x00, 0x2d, 0x25}, .msg29_data = { 0x00, 0x11, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x90, 0x00, 0x9c, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf3, 0x80, 0xd3, 0x80, 0xc0, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FG4619] = { .name = "MSP430FG4619", .msg29_params = {0x00, 0x2e, 0x26}, .msg29_data = { 0x00, 0x21, 0xff, 0xff, 0x01, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x90, 0x00, 0x9c, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0xbf, 0x13, 0xbf, 0xff, 0x30, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x02, 0x00, 0x08, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0xff, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F21x1] = { .name = "MSP430F21x1", .msg29_params = {0x00, 0x2f, 0x27}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x02, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0xff, 0x1f, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_TMS430F1390] = { .name = "TMS430FCAS001", .msg29_params = {0x00, 0x30, 0x28}, .msg29_data = { 0x00, 0x10, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0x7f, 0x10, 0x80, 0x00, 0x00, 0x05, 0xff, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0x00, 0x02, 0x00, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9a, 0x0b, 0x7c, 0x15, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x37, 0x00, 0x17, 0x00, 0x00, 0x00, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_TMS430F1250] = { .name = "TMS430FCAS003", .msg29_params = {0x00, 0x31, 0x29}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0x7f, 0x10, 0x80, 0x00, 0x00, 0x05, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x0c, 0x82, 0x14, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x37, 0x00, 0x17, 0x00, 0x00, 0x00, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_TMS430C1250] = { .name = "TMS430ROMSHUTTLE", .msg29_params = {0x00, 0x32, 0x2a}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0x7f, 0x10, 0x80, 0x00, 0x00, 0x05, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x0c, 0x82, 0x14, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x37, 0x00, 0x17, 0x00, 0x00, 0x00, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_TMS430EMU] = { .name = "TMS430EMU", .msg29_params = {0x00, 0x33, 0x2b}, .msg29_data = { 0x00, 0x10, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0x7f, 0x10, 0x80, 0x00, 0x00, 0x05, 0xff, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0x00, 0x02, 0x00, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9a, 0x0b, 0x7c, 0x15, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x37, 0x00, 0x17, 0x00, 0x00, 0x00, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F20x3] = { .name = "MSP430F20x3", .msg29_params = {0x00, 0x34, 0x2c}, .msg29_data = { 0x00, 0xf8, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0x7f, 0x02, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0xff, 0x1f, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F20x2] = { .name = "F20x2_G2x2x_G2x3x", .msg29_params = {0x00, 0x35, 0x2d}, .msg29_data = { 0x00, 0xf8, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0x7f, 0x02, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0xff, 0x1f, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F20x1] = { .name = "F20x1_G2x0x_G2x1x", .msg29_params = {0x00, 0x36, 0x2e}, .msg29_data = { 0x00, 0xf8, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0x7f, 0x02, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0xff, 0x1f, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F2234] = { .name = "MSP430F2234", .msg29_params = {0x00, 0x37, 0x2f}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x0f, 0x1f, 0x0f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F2254] = { .name = "MSP430F2254", .msg29_params = {0x00, 0x38, 0x30}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x0f, 0x1f, 0x0f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F2274] = { .name = "MSP430F2274", .msg29_params = {0x00, 0x39, 0x31}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x05, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x0f, 0x1f, 0x0f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FG4618] = { .name = "MSP430FG4618", .msg29_params = {0x00, 0x3a, 0x32}, .msg29_data = { 0x00, 0x31, 0xff, 0xff, 0x01, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x90, 0x00, 0x9c, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0xbf, 0x13, 0xbf, 0xff, 0x30, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x02, 0x00, 0x08, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0xff, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F2330] = { .name = "MSP430F2330", .msg29_params = {0x00, 0x3b, 0x33}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x05, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x0f, 0x1f, 0x0f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F2350] = { .name = "MSP430F2350", .msg29_params = {0x00, 0x3c, 0x34}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x0f, 0x1f, 0x0f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F2370] = { .name = "MSP430F2370", .msg29_params = {0x00, 0x3d, 0x35}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x0f, 0x1f, 0x0f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F2232] = { .name = "MSP430F2232", .msg29_params = {0x00, 0x3e, 0x36}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x0f, 0x1f, 0x0f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F2252] = { .name = "MSP430F2252", .msg29_params = {0x00, 0x3f, 0x37}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x0f, 0x1f, 0x0f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F2272] = { .name = "MSP430F2272", .msg29_params = {0x00, 0x40, 0x38}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x05, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x0f, 0x1f, 0x0f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F2619] = { .name = "MSP430F2619", .msg29_params = {0x00, 0x41, 0x39}, .msg29_data = { 0x00, 0x21, 0xff, 0xff, 0x01, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x0f, 0x1f, 0x0f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x02, 0x00, 0x08, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0xff, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F2618] = { .name = "MSP430F2618", .msg29_params = {0x00, 0x42, 0x3a}, .msg29_data = { 0x00, 0x31, 0xff, 0xff, 0x01, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x0f, 0x1f, 0x0f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x02, 0x00, 0x08, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0xff, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F2419] = { .name = "MSP430F2419", .msg29_params = {0x00, 0x43, 0x3b}, .msg29_data = { 0x00, 0x21, 0xff, 0xff, 0x01, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x0f, 0x1f, 0x0f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x02, 0x00, 0x08, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0xff, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F2418] = { .name = "MSP430F2418", .msg29_params = {0x00, 0x44, 0x3c}, .msg29_data = { 0x00, 0x31, 0xff, 0xff, 0x01, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x0f, 0x1f, 0x0f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x02, 0x00, 0x08, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0xff, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FE423A] = { .name = "MSP430FE423A", .msg29_params = {0x00, 0x45, 0x3d}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x02, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xa4, 0x00, 0x8c, 0x0a, 0x10, 0x0e, 0x8c, 0x0a, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xf3, 0x80, 0xd3, 0x80, 0xc0, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FE425A] = { .name = "MSP430FE425A", .msg29_params = {0x00, 0x46, 0x3e}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xa4, 0x00, 0x8c, 0x0a, 0x10, 0x0e, 0x8c, 0x0a, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xf3, 0x80, 0xd3, 0x80, 0xc0, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FE427A] = { .name = "MSP430FE427A", .msg29_params = {0x00, 0x47, 0x3f}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x05, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xa4, 0x00, 0x8c, 0x0a, 0x10, 0x0e, 0x8c, 0x0a, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xf3, 0x80, 0xd3, 0x80, 0xc0, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F423A] = { .name = "MSP430F423A", .msg29_params = {0x00, 0x48, 0x40}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x02, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xa4, 0x00, 0x8c, 0x0a, 0x10, 0x0e, 0x8c, 0x0a, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xf3, 0x80, 0xd3, 0x80, 0xc0, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F425A] = { .name = "MSP430F425A", .msg29_params = {0x00, 0x49, 0x41}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xa4, 0x00, 0x8c, 0x0a, 0x10, 0x0e, 0x8c, 0x0a, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xf3, 0x80, 0xd3, 0x80, 0xc0, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F427A] = { .name = "MSP430F427A", .msg29_params = {0x00, 0x4a, 0x42}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x05, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xa4, 0x00, 0x8c, 0x0a, 0x10, 0x0e, 0x8c, 0x0a, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xf3, 0x80, 0xd3, 0x80, 0xc0, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F4783] = { .name = "MSP430F4783", .msg29_params = {0x00, 0x4b, 0x43}, .msg29_data = { 0x00, 0x40, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xaf, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x33, 0x8f, 0x1f, 0x8f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F4784] = { .name = "MSP430F4784", .msg29_params = {0x00, 0x4c, 0x44}, .msg29_data = { 0x00, 0x40, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xaf, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x33, 0x8f, 0x1f, 0x8f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F4793] = { .name = "MSP430F4793", .msg29_params = {0x00, 0x4d, 0x45}, .msg29_data = { 0x00, 0x11, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x0b, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xaf, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x33, 0x8f, 0x1f, 0x8f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F4794] = { .name = "MSP430F4794", .msg29_params = {0x00, 0x4e, 0x46}, .msg29_data = { 0x00, 0x11, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x0b, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xaf, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x33, 0x8f, 0x1f, 0x8f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F249] = { .name = "MSP430F249", .msg29_params = {0x00, 0x4f, 0x47}, .msg29_data = { 0x00, 0x11, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x03, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x0f, 0x1f, 0x0f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x01, 0x00, 0x01, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F248] = { .name = "MSP430F248", .msg29_params = {0x00, 0x50, 0x48}, .msg29_data = { 0x00, 0x40, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x03, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x0f, 0x1f, 0x0f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x01, 0x00, 0x01, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0xff, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F247] = { .name = "MSP430F247", .msg29_params = {0x00, 0x51, 0x49}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x03, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x0f, 0x1f, 0x0f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x01, 0x00, 0x01, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0xff, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F235] = { .name = "MSP430F235", .msg29_params = {0x00, 0x52, 0x4a}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x03, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x0f, 0x1f, 0x0f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x01, 0x00, 0x01, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F2491] = { .name = "MSP430F2491", .msg29_params = {0x00, 0x53, 0x4b}, .msg29_data = { 0x00, 0x11, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x03, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x0f, 0x1f, 0x0f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x01, 0x00, 0x01, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F2481] = { .name = "MSP430F2481", .msg29_params = {0x00, 0x54, 0x4c}, .msg29_data = { 0x00, 0x40, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x03, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x0f, 0x1f, 0x0f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x01, 0x00, 0x01, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0xff, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F2471] = { .name = "MSP430F2471", .msg29_params = {0x00, 0x55, 0x4d}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x03, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x0f, 0x1f, 0x0f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x01, 0x00, 0x01, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0xff, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F233] = { .name = "MSP430F233", .msg29_params = {0x00, 0x56, 0x4e}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x05, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x03, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x0f, 0x1f, 0x0f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x01, 0x00, 0x01, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F2410] = { .name = "MSP430F2410", .msg29_params = {0x00, 0x57, 0x4f}, .msg29_data = { 0x00, 0x21, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x03, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x0f, 0x1f, 0x0f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x01, 0x00, 0x01, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0xff, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F2132] = { .name = "MSP430F2132", .msg29_params = {0x00, 0x58, 0x50}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x0f, 0x1f, 0x0f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F2122] = { .name = "MSP430F2122", .msg29_params = {0x00, 0x59, 0x51}, .msg29_data = { 0x00, 0xf0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x0f, 0x1f, 0x0f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F2112] = { .name = "MSP430F2112", .msg29_params = {0x00, 0x5a, 0x52}, .msg29_data = { 0x00, 0xf8, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x02, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x0f, 0x1f, 0x0f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_XMS430F5438] = { .name = "XMS430F5438", .msg29_params = {0x00, 0x5b, 0x53}, .msg29_data = { 0x00, 0x5c, 0xff, 0x5b, 0x04, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x5b, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x9d, 0x00, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5438] = { .name = "MSP430F5438", .msg29_params = {0x00, 0x5c, 0x54}, .msg29_data = { 0x00, 0x5c, 0xff, 0x5b, 0x04, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x5b, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x9d, 0x00, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5436] = { .name = "MSP430F5436", .msg29_params = {0x00, 0x5d, 0x55}, .msg29_data = { 0x00, 0x5c, 0xff, 0x5b, 0x03, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x5b, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x9d, 0x00, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5419] = { .name = "MSP430F5419", .msg29_params = {0x00, 0x5e, 0x56}, .msg29_data = { 0x00, 0x5c, 0xff, 0x5b, 0x02, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x5b, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x9d, 0x00, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FE4232] = { .name = "MSP430FE4232", .msg29_params = {0x00, 0x5f, 0x57}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x02, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xa4, 0x00, 0x8c, 0x0a, 0x10, 0x0e, 0x8c, 0x0a, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xf3, 0x80, 0xd3, 0x80, 0xc0, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FE42x2] = { .name = "MSP430FE42x2", .msg29_params = {0x00, 0x60, 0x58}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xa4, 0x00, 0x8c, 0x0a, 0x10, 0x0e, 0x8c, 0x0a, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xf3, 0x80, 0xd3, 0x80, 0xc0, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5437] = { .name = "MSP430F5437", .msg29_params = {0x00, 0x61, 0x59}, .msg29_data = { 0x00, 0x5c, 0xff, 0x5b, 0x04, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x5b, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x9d, 0x00, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5435] = { .name = "MSP430F5435", .msg29_params = {0x00, 0x62, 0x5a}, .msg29_data = { 0x00, 0x5c, 0xff, 0x5b, 0x03, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x5b, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x9d, 0x00, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5418] = { .name = "MSP430F5418", .msg29_params = {0x00, 0x63, 0x5b}, .msg29_data = { 0x00, 0x5c, 0xff, 0x5b, 0x02, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x5b, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x9d, 0x00, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FG4250] = { .name = "MSP430FG4250", .msg29_params = {0x00, 0x64, 0x5c}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x02, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xaf, 0x00, 0x08, 0x07, 0x10, 0x0e, 0x8c, 0x0a, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x33, 0x80, 0x1f, 0x80, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FG42x0] = { .name = "MSP430FG42x0", .msg29_params = {0x00, 0x65, 0x5d}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x02, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xaf, 0x00, 0x08, 0x07, 0x10, 0x0e, 0x8c, 0x0a, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x33, 0x80, 0x1f, 0x80, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FE4272] = { .name = "MSP430FE4272", .msg29_params = {0x00, 0x66, 0x5e}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x05, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xa4, 0x00, 0x8c, 0x0a, 0x10, 0x0e, 0x8c, 0x0a, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xf3, 0x80, 0xd3, 0x80, 0xc0, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FG477] = { .name = "MSP430FG477", .msg29_params = {0x00, 0x67, 0x5f}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xaf, 0x00, 0x08, 0x07, 0x10, 0x0e, 0x8c, 0x0a, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x8f, 0x1f, 0x8f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FG478] = { .name = "MSP430FG478", .msg29_params = {0x00, 0x68, 0x60}, .msg29_data = { 0x00, 0x40, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xaf, 0x00, 0x08, 0x07, 0x10, 0x0e, 0x8c, 0x0a, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x8f, 0x1f, 0x8f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FG479] = { .name = "MSP430FG479", .msg29_params = {0x00, 0x69, 0x61}, .msg29_data = { 0x00, 0x11, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xaf, 0x00, 0x08, 0x07, 0x10, 0x0e, 0x8c, 0x0a, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x8f, 0x1f, 0x8f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F477] = { .name = "MSP430F477", .msg29_params = {0x00, 0x6a, 0x62}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xaf, 0x00, 0x08, 0x07, 0x10, 0x0e, 0x8c, 0x0a, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x8f, 0x1f, 0x8f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F478] = { .name = "MSP430F478", .msg29_params = {0x00, 0x6b, 0x63}, .msg29_data = { 0x00, 0x40, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xaf, 0x00, 0x08, 0x07, 0x10, 0x0e, 0x8c, 0x0a, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x8f, 0x1f, 0x8f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F479] = { .name = "MSP430F479", .msg29_params = {0x00, 0x6c, 0x64}, .msg29_data = { 0x00, 0x11, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xaf, 0x00, 0x08, 0x07, 0x10, 0x0e, 0x8c, 0x0a, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x8f, 0x1f, 0x8f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F47197] = { .name = "MSP430F47197", .msg29_params = {0x00, 0x6d, 0x65}, .msg29_data = { 0x00, 0x21, 0xff, 0xff, 0x01, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xa4, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x8f, 0x1f, 0x1f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x02, 0x00, 0x08, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0xff, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F47187] = { .name = "MSP430F47187", .msg29_params = {0x00, 0x6e, 0x66}, .msg29_data = { 0x00, 0x31, 0xff, 0xff, 0x01, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xa4, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x8f, 0x1f, 0x1f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x02, 0x00, 0x08, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0xff, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F47177] = { .name = "MSP430F47177", .msg29_params = {0x00, 0x6f, 0x67}, .msg29_data = { 0x00, 0x31, 0xff, 0x9f, 0x01, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xa4, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x8f, 0x1f, 0x1f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x02, 0x00, 0x08, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0xff, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F47167] = { .name = "MSP430F47167", .msg29_params = {0x00, 0x70, 0x68}, .msg29_data = { 0x00, 0x21, 0xff, 0x8f, 0x01, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xa4, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x8f, 0x1f, 0x1f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x02, 0x00, 0x08, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0xff, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F47196] = { .name = "MSP430F47196", .msg29_params = {0x00, 0x71, 0x69}, .msg29_data = { 0x00, 0x21, 0xff, 0xff, 0x01, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xa4, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x8f, 0x1f, 0x1f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x02, 0x00, 0x08, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0xff, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F47186] = { .name = "MSP430F47186", .msg29_params = {0x00, 0x72, 0x6a}, .msg29_data = { 0x00, 0x31, 0xff, 0xff, 0x01, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xa4, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x8f, 0x1f, 0x1f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x02, 0x00, 0x08, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0xff, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F47176] = { .name = "MSP430F47176", .msg29_params = {0x00, 0x73, 0x6b}, .msg29_data = { 0x00, 0x31, 0xff, 0x9f, 0x01, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xa4, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x8f, 0x1f, 0x1f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x02, 0x00, 0x08, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0xff, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F47166] = { .name = "MSP430F47166", .msg29_params = {0x00, 0x74, 0x6c}, .msg29_data = { 0x00, 0x21, 0xff, 0x8f, 0x01, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xa4, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x8f, 0x1f, 0x1f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x02, 0x00, 0x08, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0xff, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F4152] = { .name = "MSP430F4152", .msg29_params = {0x00, 0x75, 0x6d}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xaf, 0x00, 0x08, 0x07, 0x10, 0x0e, 0x8c, 0x0a, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x8f, 0x1f, 0x8f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F4132] = { .name = "MSP430F4132", .msg29_params = {0x00, 0x76, 0x6e}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x02, 0x00, 0xd7, 0x60, 0x90, 0x00, 0xaf, 0x00, 0x08, 0x07, 0x10, 0x0e, 0x8c, 0x0a, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x8f, 0x1f, 0x8f, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_CC430F6137] = { .name = "CC430F6137", .msg29_params = {0x00, 0x77, 0x6f}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x2b, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x07, 0x24, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x00, 0x00, 0xb0, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x60, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_CC430F6135] = { .name = "CC430F6135", .msg29_params = {0x00, 0x78, 0x70}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x07, 0x24, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x00, 0x00, 0xb0, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x60, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_CC430F6127] = { .name = "CC430F6127", .msg29_params = {0x00, 0x79, 0x71}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x2b, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x07, 0x24, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x00, 0x00, 0xb0, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x60, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_CC430F6126] = { .name = "CC430F6126", .msg29_params = {0x00, 0x7a, 0x72}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x07, 0x24, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x00, 0x00, 0xb0, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0x00, 0xa8, 0x60, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_CC430F6125] = { .name = "CC430F6125", .msg29_params = {0x00, 0x7b, 0x73}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x07, 0x24, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x00, 0x00, 0xb0, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0x00, 0xa8, 0x60, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_CC430F5137] = { .name = "CC430F5137", .msg29_params = {0x00, 0x7c, 0x74}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x2b, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x07, 0x24, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x00, 0x00, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x60, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_CC430F5135] = { .name = "CC430F5135", .msg29_params = {0x00, 0x7d, 0x75}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x07, 0x24, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x00, 0x00, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x60, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_CC430F5133] = { .name = "CC430F5133", .msg29_params = {0x00, 0x7e, 0x76}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x07, 0x24, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x00, 0x00, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x60, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5513] = { .name = "MSP430F5513", .msg29_params = {0x00, 0x7f, 0x77}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x33, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0x00, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5514] = { .name = "MSP430F5514", .msg29_params = {0x00, 0x80, 0x78}, .msg29_data = { 0x00, 0x44, 0xff, 0x43, 0x01, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x33, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0x00, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5515] = { .name = "MSP430F5515", .msg29_params = {0x00, 0x81, 0x79}, .msg29_data = { 0x00, 0x44, 0xff, 0x43, 0x01, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x33, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0x00, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5517] = { .name = "MSP430F5517", .msg29_params = {0x00, 0x82, 0x7a}, .msg29_data = { 0x00, 0x44, 0xff, 0xc3, 0x01, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x3b, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0x00, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5519] = { .name = "MSP430F5519", .msg29_params = {0x00, 0x83, 0x7b}, .msg29_data = { 0x00, 0x44, 0xff, 0x43, 0x02, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x43, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0x00, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5521] = { .name = "MSP430F5521", .msg29_params = {0x00, 0x84, 0x7c}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x3b, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5522] = { .name = "MSP430F5522", .msg29_params = {0x00, 0x85, 0x7d}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x43, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5524] = { .name = "MSP430F5524", .msg29_params = {0x00, 0x86, 0x7e}, .msg29_data = { 0x00, 0x44, 0xff, 0x43, 0x01, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x33, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5525] = { .name = "MSP430F5525", .msg29_params = {0x00, 0x87, 0x7f}, .msg29_data = { 0x00, 0x44, 0xff, 0x43, 0x01, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x33, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5526] = { .name = "MSP430F5526", .msg29_params = {0x00, 0x88, 0x80}, .msg29_data = { 0x00, 0x44, 0xff, 0xc3, 0x01, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x3b, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5527] = { .name = "MSP430F5527", .msg29_params = {0x00, 0x89, 0x81}, .msg29_data = { 0x00, 0x44, 0xff, 0xc3, 0x01, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x3b, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5528] = { .name = "MSP430F5528", .msg29_params = {0x00, 0x8a, 0x82}, .msg29_data = { 0x00, 0x44, 0xff, 0x43, 0x02, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x43, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5529] = { .name = "MSP430F5529", .msg29_params = {0x00, 0x8b, 0x83}, .msg29_data = { 0x00, 0x44, 0xff, 0x43, 0x02, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x43, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5438A] = { .name = "MSP430F5438A", .msg29_params = {0x00, 0x8c, 0x84}, .msg29_data = { 0x00, 0x5c, 0xff, 0x5b, 0x04, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x5b, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x9d, 0x00, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5436A] = { .name = "MSP430F5436A", .msg29_params = {0x00, 0x8d, 0x85}, .msg29_data = { 0x00, 0x5c, 0xff, 0x5b, 0x03, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x5b, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x9d, 0x00, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5419A] = { .name = "MSP430F5419A", .msg29_params = {0x00, 0x8e, 0x86}, .msg29_data = { 0x00, 0x5c, 0xff, 0x5b, 0x02, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x5b, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x9d, 0x00, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5437A] = { .name = "MSP430F5437A", .msg29_params = {0x00, 0x8f, 0x87}, .msg29_data = { 0x00, 0x5c, 0xff, 0x5b, 0x04, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x5b, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x9d, 0x00, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5435A] = { .name = "MSP430F5435A", .msg29_params = {0x00, 0x90, 0x88}, .msg29_data = { 0x00, 0x5c, 0xff, 0x5b, 0x03, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x5b, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x9d, 0x00, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5418A] = { .name = "MSP430F5418A", .msg29_params = {0x00, 0x91, 0x89}, .msg29_data = { 0x00, 0x5c, 0xff, 0x5b, 0x02, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x5b, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x9d, 0x00, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5510] = { .name = "MSP430F5510", .msg29_params = {0x00, 0x92, 0x8a}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x33, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd6, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5131] = { .name = "MSP430F5131", .msg29_params = {0x00, 0x93, 0x8b}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x0a, 0x00, 0x8e, 0x74, 0x75, 0x00, 0x28, 0x29, 0x00, 0x00, 0x8a, 0x00, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5132] = { .name = "MSP430F5132", .msg29_params = {0x00, 0x94, 0x8c}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x0a, 0x00, 0x8e, 0x74, 0x75, 0x00, 0x28, 0x29, 0x00, 0x00, 0x8a, 0xd6, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5151] = { .name = "MSP430F5151", .msg29_params = {0x00, 0x95, 0x8d}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x0a, 0x00, 0x8e, 0x74, 0x75, 0x00, 0x28, 0x29, 0x00, 0x00, 0x8a, 0x00, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5152] = { .name = "MSP430F5152", .msg29_params = {0x00, 0x96, 0x8e}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x0a, 0x00, 0x8e, 0x74, 0x75, 0x00, 0x28, 0x29, 0x00, 0x00, 0x8a, 0xd6, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5171] = { .name = "MSP430F5171", .msg29_params = {0x00, 0x97, 0x8f}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x0a, 0x00, 0x8e, 0x74, 0x75, 0x00, 0x28, 0x29, 0x00, 0x00, 0x8a, 0x00, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5172] = { .name = "MSP430F5172", .msg29_params = {0x00, 0x98, 0x90}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x0a, 0x00, 0x8e, 0x74, 0x75, 0x00, 0x28, 0x29, 0x00, 0x00, 0x8a, 0xd6, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5630] = { .name = "MSP430F5630", .msg29_params = {0x00, 0x99, 0x91}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x02, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x00, 0x00, 0x8a, 0x00, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5631] = { .name = "MSP430F5631", .msg29_params = {0x00, 0x9a, 0x92}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x03, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x00, 0x00, 0x8a, 0x00, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5632] = { .name = "MSP430F5632", .msg29_params = {0x00, 0x9b, 0x93}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x04, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x00, 0x00, 0x8a, 0x00, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5633] = { .name = "MSP430F5633", .msg29_params = {0x00, 0x9c, 0x94}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x02, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x00, 0x00, 0x8a, 0xd8, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5634] = { .name = "MSP430F5634", .msg29_params = {0x00, 0x9d, 0x95}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x03, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x00, 0x00, 0x8a, 0xd8, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5635] = { .name = "MSP430F5635", .msg29_params = {0x00, 0x9e, 0x96}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x04, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x00, 0x00, 0x8a, 0xd8, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5636] = { .name = "MSP430F5636", .msg29_params = {0x00, 0x9f, 0x97}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x02, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x00, 0x00, 0x8a, 0xd8, 0xa8, 0xc0, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5637] = { .name = "MSP430F5637", .msg29_params = {0x00, 0xa0, 0x98}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x03, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x00, 0x00, 0x8a, 0xd8, 0xa8, 0xc0, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5638] = { .name = "MSP430F5638", .msg29_params = {0x00, 0xa1, 0x99}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x04, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x00, 0x00, 0x8a, 0xd8, 0xa8, 0xc0, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F6630] = { .name = "MSP430F6630", .msg29_params = {0x00, 0xa2, 0x9a}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x02, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x00, 0x00, 0x8a, 0x00, 0xa8, 0x00, 0xb0, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F6631] = { .name = "MSP430F6631", .msg29_params = {0x00, 0xa3, 0x9b}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x03, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x00, 0x00, 0x8a, 0x00, 0xa8, 0x00, 0xb0, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F6632] = { .name = "MSP430F6632", .msg29_params = {0x00, 0xa4, 0x9c}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x04, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x00, 0x00, 0x8a, 0x00, 0xa8, 0x00, 0xb0, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F6633] = { .name = "MSP430F6633", .msg29_params = {0x00, 0xa5, 0x9d}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x02, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x00, 0x00, 0x8a, 0xd8, 0xa8, 0x00, 0xb0, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F6634] = { .name = "MSP430F6634", .msg29_params = {0x00, 0xa6, 0x9e}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x03, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x00, 0x00, 0x8a, 0xd8, 0xa8, 0x00, 0xb0, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F6635] = { .name = "MSP430F6635", .msg29_params = {0x00, 0xa7, 0x9f}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x04, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x00, 0x00, 0x8a, 0xd8, 0xa8, 0x00, 0xb0, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F6636] = { .name = "MSP430F6636", .msg29_params = {0x00, 0xa8, 0xa0}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x02, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x00, 0x00, 0x8a, 0xd8, 0xa8, 0xc0, 0xb0, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F6637] = { .name = "MSP430F6637", .msg29_params = {0x00, 0xa9, 0xa1}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x03, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x00, 0x00, 0x8a, 0xd8, 0xa8, 0xc0, 0xb0, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F6638] = { .name = "MSP430F6638", .msg29_params = {0x00, 0xaa, 0xa2}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x04, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x00, 0x00, 0x8a, 0xd8, 0xa8, 0xc0, 0xb0, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FR5739] = { .name = "MSP430FR5739", .msg29_params = {0x00, 0xab, 0xa3}, .msg29_data = { 0x00, 0x1c, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x18, 0xff, 0x18, 0x00, 0x00, 0x00, 0xc2, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x00, 0x01, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0a, 0x8f, 0x8e, 0x99, 0x98, 0x97, 0x2d, 0x2c, 0x30, 0x00, 0x8a, 0xd6, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430L092] = { .name = "MSP430L092", .msg29_params = {0x00, 0xac, 0xa4}, .msg29_data = { 0x00, 0x1c, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x04, 0x00, 0x02, 0x00, 0x17, 0x04, 0x90, 0x00, 0xaf, 0x00, 0x84, 0x03, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x0a, 0x8f, 0x8e, 0x00, 0xb5, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F6700] = { .name = "MSP430F6700", .msg29_params = {0x00, 0xad, 0xa5}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x07, 0x24, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x0a, 0x88, 0x8d, 0x8c, 0x8e, 0x00, 0x2e, 0x2c, 0x2d, 0x30, 0x8a, 0xd6, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F6701] = { .name = "MSP430F6701", .msg29_params = {0x00, 0xae, 0xa6}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x07, 0x24, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8d, 0x8c, 0x8e, 0x00, 0x2e, 0x2c, 0x2d, 0x30, 0x8a, 0xd6, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F6702] = { .name = "MSP430F6702", .msg29_params = {0x00, 0xaf, 0xa7}, .msg29_data = { 0x00, 0x40, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x2b, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x07, 0x24, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x0a, 0x88, 0x8d, 0x8c, 0x8e, 0x00, 0x2e, 0x2c, 0x2d, 0x30, 0x8a, 0xd6, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F6703] = { .name = "MSP430F6703", .msg29_params = {0x00, 0xb0, 0xa8}, .msg29_data = { 0x00, 0x40, 0xff, 0x3f, 0x01, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x2b, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x07, 0x24, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x0a, 0x88, 0x8d, 0x8c, 0x8e, 0x00, 0x2e, 0x2c, 0x2d, 0x30, 0x8a, 0xd6, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F6720] = { .name = "MSP430F6720", .msg29_params = {0x00, 0xb1, 0xa9}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x07, 0x24, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8d, 0x8c, 0x8e, 0x00, 0x2e, 0x2c, 0x2d, 0x30, 0x8a, 0xd6, 0xd5, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F6721] = { .name = "MSP430F6721", .msg29_params = {0x00, 0xb2, 0xaa}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x07, 0x24, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x0a, 0x88, 0x8d, 0x8c, 0x8e, 0x00, 0x2e, 0x2c, 0x2d, 0x30, 0x8a, 0xd6, 0xd5, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F6722] = { .name = "MSP430F6722", .msg29_params = {0x00, 0xb3, 0xab}, .msg29_data = { 0x00, 0x40, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x2b, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x07, 0x24, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x0a, 0x88, 0x8d, 0x8c, 0x8e, 0x00, 0x2e, 0x2c, 0x2d, 0x30, 0x8a, 0xd6, 0xd5, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F6730] = { .name = "MSP430F6730", .msg29_params = {0x00, 0xb5, 0xad}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x07, 0x24, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x0a, 0x88, 0x8d, 0x8c, 0x8e, 0x00, 0x2e, 0x2c, 0x2d, 0x30, 0x8a, 0xd6, 0xd5, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F6731] = { .name = "MSP430F6731", .msg29_params = {0x00, 0xb6, 0xae}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x07, 0x24, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x0a, 0x88, 0x8d, 0x8c, 0x8e, 0x00, 0x2e, 0x2c, 0x2d, 0x30, 0x8a, 0xd6, 0xd5, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F6732] = { .name = "MSP430F6732", .msg29_params = {0x00, 0xb7, 0xaf}, .msg29_data = { 0x00, 0x40, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x2b, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x07, 0x24, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x0a, 0x88, 0x8d, 0x8c, 0x8e, 0x00, 0x2e, 0x2c, 0x2d, 0x30, 0x8a, 0xd6, 0xd5, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F6733] = { .name = "MSP430F6733", .msg29_params = {0x00, 0xb8, 0xb0}, .msg29_data = { 0x00, 0x40, 0xff, 0x3f, 0x01, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x07, 0x24, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x0a, 0x88, 0x8d, 0x8c, 0x8e, 0x00, 0x2e, 0x2c, 0x2d, 0x30, 0x8a, 0xd6, 0xd5, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5509] = { .name = "MSP430F5509", .msg29_params = {0x00, 0xb9, 0xb1}, .msg29_data = { 0x00, 0xa0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x33, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd6, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5508] = { .name = "MSP430F5508", .msg29_params = {0x00, 0xba, 0xb2}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x33, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd6, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5507] = { .name = "MSP430F5507", .msg29_params = {0x00, 0xbb, 0xb3}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x33, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x00, 0x00, 0x8a, 0xd6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5506] = { .name = "MSP430F5506", .msg29_params = {0x00, 0xbc, 0xb4}, .msg29_data = { 0x00, 0xa0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x33, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x00, 0x00, 0x8a, 0xd6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5505] = { .name = "MSP430F5505", .msg29_params = {0x00, 0xbd, 0xb5}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x33, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x00, 0x00, 0x8a, 0xd6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5504] = { .name = "MSP430F5504", .msg29_params = {0x00, 0xbe, 0xb6}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x33, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x00, 0x00, 0x8a, 0xd6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5503] = { .name = "MSP430F5503", .msg29_params = {0x00, 0xbf, 0xb7}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x33, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x00, 0x00, 0x8a, 0xd6, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5502] = { .name = "MSP430F5502", .msg29_params = {0x00, 0xc0, 0xb8}, .msg29_data = { 0x00, 0xa0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x33, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x00, 0x00, 0x8a, 0xd6, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5501] = { .name = "MSP430F5501", .msg29_params = {0x00, 0xc1, 0xb9}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x33, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x00, 0x00, 0x8a, 0xd6, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5500] = { .name = "MSP430F5500", .msg29_params = {0x00, 0xc2, 0xba}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x33, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x00, 0x00, 0x8a, 0xd6, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F12x2New] = { .name = "MSP430F12x2/F11x2", .msg29_params = {0x00, 0xc3, 0xbb}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x02, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x03, 0x13, 0x03, 0xff, 0x03, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5310] = { .name = "MSP430F5310", .msg29_params = {0x00, 0xc4, 0xbc}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x33, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd6, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5309] = { .name = "MSP430F5309", .msg29_params = {0x00, 0xc5, 0xbd}, .msg29_data = { 0x00, 0xa0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x33, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd6, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5308] = { .name = "MSP430F5308", .msg29_params = {0x00, 0xc6, 0xbe}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x33, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd6, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5304] = { .name = "MSP430F5304", .msg29_params = {0x00, 0xc7, 0xbf}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x33, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x00, 0x00, 0x8a, 0xd6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430AFE253] = { .name = "MSP430AFE253", .msg29_params = {0x00, 0xc8, 0xc0}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf3, 0xff, 0xdf, 0xff, 0xc0, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5329] = { .name = "MSP430F5329", .msg29_params = {0x00, 0xc9, 0xc1}, .msg29_data = { 0x00, 0x44, 0xff, 0x43, 0x02, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x43, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5328] = { .name = "MSP430F5328", .msg29_params = {0x00, 0xca, 0xc2}, .msg29_data = { 0x00, 0x44, 0xff, 0x43, 0x02, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x43, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5327] = { .name = "MSP430F5327", .msg29_params = {0x00, 0xcb, 0xc3}, .msg29_data = { 0x00, 0x44, 0xff, 0xc3, 0x01, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x3b, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5326] = { .name = "MSP430F5326", .msg29_params = {0x00, 0xcc, 0xc4}, .msg29_data = { 0x00, 0x44, 0xff, 0xc3, 0x01, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x3b, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5325] = { .name = "MSP430F5325", .msg29_params = {0x00, 0xcd, 0xc5}, .msg29_data = { 0x00, 0x44, 0xff, 0x43, 0x01, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x33, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5324] = { .name = "MSP430F5324", .msg29_params = {0x00, 0xce, 0xc6}, .msg29_data = { 0x00, 0x44, 0xff, 0x43, 0x01, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x33, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430G2452] = { .name = "MSP430G2xx2", .msg29_params = {0x00, 0xcf, 0xc7}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x02, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0xff, 0x1f, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5342] = { .name = "MSP430F5342", .msg29_params = {0x00, 0xd0, 0xc8}, .msg29_data = { 0x00, 0x44, 0xff, 0x43, 0x02, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x43, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5341] = { .name = "MSP430F5341", .msg29_params = {0x00, 0xd1, 0xc9}, .msg29_data = { 0x00, 0x44, 0xff, 0xc3, 0x01, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x3b, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5340] = { .name = "MSP430F5340", .msg29_params = {0x00, 0xd2, 0xca}, .msg29_data = { 0x00, 0x44, 0xff, 0x43, 0x01, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x33, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FW429] = { .name = "MSP430FW429", .msg29_params = {0x00, 0xd3, 0xcb}, .msg29_data = { 0x00, 0x11, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x80, 0x00, 0x00, 0x02, 0xff, 0x09, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x90, 0x00, 0x9c, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x33, 0x80, 0x13, 0x80, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F6659] = { .name = "MSP430F6659", .msg29_params = {0x00, 0xd4, 0xcc}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x08, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x00, 0x00, 0x8a, 0xd8, 0xa8, 0xc0, 0xb0, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F6658] = { .name = "MSP430F6658", .msg29_params = {0x00, 0xd5, 0xcd}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x06, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x00, 0x00, 0x8a, 0xd8, 0xa8, 0xc0, 0xb0, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0f, 0x00, 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F6459] = { .name = "MSP430F6459", .msg29_params = {0x00, 0xd6, 0xce}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x08, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x00, 0x00, 0x8a, 0xd8, 0xa8, 0xc0, 0xb0, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F6458] = { .name = "MSP430F6458", .msg29_params = {0x00, 0xd7, 0xcf}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x06, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x00, 0x00, 0x8a, 0xd8, 0xa8, 0xc0, 0xb0, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0f, 0x00, 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F6457] = { .name = "MSP430F6457", .msg29_params = {0x00, 0xd8, 0xd0}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x04, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x00, 0x00, 0x8a, 0xd8, 0xa8, 0xc0, 0xb0, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5659] = { .name = "MSP430F5659", .msg29_params = {0x00, 0xd9, 0xd1}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x08, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x00, 0x00, 0x8a, 0xd8, 0xa8, 0xc0, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5658] = { .name = "MSP430F5658", .msg29_params = {0x00, 0xda, 0xd2}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x06, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x40, 0x28, 0x29, 0x00, 0x00, 0x8a, 0xd8, 0xa8, 0xc0, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0f, 0x00, 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5359] = { .name = "MSP430F5359", .msg29_params = {0x00, 0xdb, 0xd3}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x08, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x00, 0x00, 0x8a, 0xd8, 0xa8, 0xc0, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5358] = { .name = "MSP430F5358", .msg29_params = {0x00, 0xdc, 0xd4}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x06, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x00, 0x00, 0x8a, 0xd8, 0xa8, 0xc0, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0f, 0x00, 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5357] = { .name = "MSP430F5357", .msg29_params = {0x00, 0xdd, 0xd5}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x04, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x00, 0x00, 0x8a, 0xd8, 0xa8, 0xc0, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430G2553] = { .name = "MSP430G2xx3", .msg29_params = {0x00, 0xde, 0xd6}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0xff, 0x1f, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430AFE233] = { .name = "MSP430AFE233", .msg29_params = {0x00, 0xdf, 0xd7}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf3, 0xff, 0xdf, 0xff, 0xc0, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430AFE223] = { .name = "MSP430AFE223", .msg29_params = {0x00, 0xe0, 0xd8}, .msg29_data = { 0x00, 0xf0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x02, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf3, 0xff, 0xdf, 0xff, 0xc0, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430AFE252] = { .name = "MSP430AFE252", .msg29_params = {0x00, 0xe1, 0xd9}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf3, 0xff, 0xdf, 0xff, 0xc0, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430AFE232] = { .name = "MSP430AFE232", .msg29_params = {0x00, 0xe2, 0xda}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf3, 0xff, 0xdf, 0xff, 0xc0, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430AFE222] = { .name = "MSP430AFE222", .msg29_params = {0x00, 0xe3, 0xdb}, .msg29_data = { 0x00, 0xf0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x02, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf3, 0xff, 0xdf, 0xff, 0xc0, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430AFE251] = { .name = "MSP430AFE251", .msg29_params = {0x00, 0xe4, 0xdc}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf3, 0xff, 0xdf, 0xff, 0xc0, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430AFE231] = { .name = "MSP430AFE231", .msg29_params = {0x00, 0xe5, 0xdd}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf3, 0xff, 0xdf, 0xff, 0xc0, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430AFE221] = { .name = "MSP430AFE221", .msg29_params = {0x00, 0xe6, 0xde}, .msg29_data = { 0x00, 0xf0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x02, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf3, 0xff, 0xdf, 0xff, 0xc0, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430AFE250] = { .name = "MSP430AFE250", .msg29_params = {0x00, 0xe7, 0xdf}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf3, 0xff, 0xdf, 0xff, 0xc0, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430AFE230] = { .name = "MSP430AFE230", .msg29_params = {0x00, 0xe8, 0xe0}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf3, 0xff, 0xdf, 0xff, 0xc0, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430AFE220] = { .name = "MSP430AFE220", .msg29_params = {0x00, 0xe9, 0xe1}, .msg29_data = { 0x00, 0xf0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x40, 0x00, 0x00, 0x02, 0xff, 0x02, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf3, 0xff, 0xdf, 0xff, 0xc0, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FR5738] = { .name = "MSP430FR5738", .msg29_params = {0x00, 0xeb, 0xe3}, .msg29_data = { 0x00, 0xc2, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x18, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x00, 0x01, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0a, 0x8f, 0x8e, 0x00, 0x00, 0x97, 0x2c, 0x00, 0x30, 0x00, 0x8a, 0xd6, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FR5735] = { .name = "MSP430FR5735", .msg29_params = {0x00, 0xec, 0xe4}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x18, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x00, 0x01, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0a, 0x8f, 0x8e, 0x99, 0x98, 0x97, 0x2c, 0x2d, 0x30, 0x00, 0x8a, 0xd6, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FR5730] = { .name = "MSP430FR5730", .msg29_params = {0x00, 0xed, 0xe5}, .msg29_data = { 0x00, 0xf0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x18, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x1d, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x00, 0x01, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0a, 0x8f, 0x8e, 0x00, 0x00, 0x97, 0x2c, 0x00, 0x30, 0x00, 0x8a, 0xd6, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FR5729] = { .name = "MSP430FR5729", .msg29_params = {0x00, 0xee, 0xe6}, .msg29_data = { 0x00, 0xc2, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x18, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x00, 0x01, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0a, 0x8f, 0x8e, 0x99, 0x98, 0x97, 0x2c, 0x2d, 0x30, 0x00, 0x8a, 0xd6, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FR5728] = { .name = "MSP430FR5728", .msg29_params = {0x00, 0xef, 0xe7}, .msg29_data = { 0x00, 0xc2, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x18, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x00, 0x01, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0a, 0x8f, 0x8e, 0x00, 0x00, 0x97, 0x2c, 0x00, 0x30, 0x00, 0x8a, 0xd6, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FR5725] = { .name = "MSP430FR5725", .msg29_params = {0x00, 0xf0, 0xe8}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x18, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x00, 0x01, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0a, 0x8f, 0x8e, 0x99, 0x98, 0x97, 0x2c, 0x2d, 0x30, 0x00, 0x8a, 0xd6, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FR5720] = { .name = "MSP430FR5720", .msg29_params = {0x00, 0xf1, 0xe9}, .msg29_data = { 0x00, 0xf0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x18, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x1d, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x00, 0x01, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0a, 0x8f, 0x8e, 0x00, 0x00, 0x97, 0x2c, 0x00, 0x30, 0x00, 0x8a, 0xd6, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FR5969] = { .name = "MSP430FR5969", .msg29_params = {0x00, 0xf2, 0xea}, .msg29_data = { 0x00, 0x44, 0xff, 0x3f, 0x01, 0x00, 0x00, 0x18, 0xff, 0x19, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x00, 0x01, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0a, 0x88, 0x8d, 0x8f, 0x8e, 0x9d, 0x2d, 0x2c, 0x30, 0x00, 0x8a, 0xd8, 0xa8, 0x60, 0x00, 0x00, 0x01, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_CC430F6147] = { .name = "CC430F6147", .msg29_params = {0x00, 0xf3, 0xeb}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x2b, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x07, 0x24, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x00, 0x00, 0xb0, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x60, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_CC430F6145] = { .name = "CC430F6145", .msg29_params = {0x00, 0xf4, 0xec}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x07, 0x24, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x00, 0x00, 0xb0, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x60, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_CC430F6143] = { .name = "CC430F6143", .msg29_params = {0x00, 0xf5, 0xed}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x07, 0x24, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x00, 0x00, 0xb0, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x60, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_CC430F5147] = { .name = "CC430F5147", .msg29_params = {0x00, 0xf6, 0xee}, .msg29_data = { 0x00, 0x80, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x2b, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x07, 0x24, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x00, 0x00, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x60, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_CC430F5145] = { .name = "CC430F5145", .msg29_params = {0x00, 0xf7, 0xef}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x07, 0x24, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x00, 0x00, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x60, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_CC430F5143] = { .name = "CC430F5143", .msg29_params = {0x00, 0xf8, 0xf0}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x07, 0x24, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x00, 0x00, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x60, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_CC430F5125] = { .name = "CC430F5125", .msg29_params = {0x00, 0xf9, 0xf1}, .msg29_data = { 0x00, 0xc0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x07, 0x24, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x00, 0x00, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0x00, 0xa8, 0x60, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_CC430F5123] = { .name = "CC430F5123", .msg29_params = {0x00, 0xfa, 0xf2}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x07, 0x24, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x00, 0x00, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0x00, 0xa8, 0x60, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F6723] = { .name = "MSP430F672x", .msg29_params = {0x00, 0xfb, 0xac}, .msg29_data = { 0x00, 0x40, 0xff, 0x3f, 0x01, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x07, 0x24, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x0a, 0x88, 0x8d, 0x8c, 0x8e, 0x00, 0x2e, 0x2c, 0x2d, 0x30, 0x8a, 0xd6, 0xd5, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F6736] = { .name = "MSP430F673x", .msg29_params = {0x00, 0xfe, 0xf8}, .msg29_data = { 0x00, 0x40, 0xff, 0x3f, 0x02, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x3b, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x07, 0x24, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x0a, 0x88, 0x8d, 0x8c, 0x8e, 0x00, 0x2e, 0x2c, 0x2d, 0x30, 0x8a, 0xd6, 0xd5, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5333] = { .name = "MSP430F5333", .msg29_params = {0x00, 0x101, 0xf9}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x02, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x43, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5335] = { .name = "MSP430F5335", .msg29_params = {0x00, 0x102, 0xfa}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x04, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5336] = { .name = "MSP430F5336", .msg29_params = {0x00, 0x103, 0xfb}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x02, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0xc0, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5338] = { .name = "MSP430F5338", .msg29_params = {0x00, 0x104, 0xfc}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x04, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0xc0, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F6433] = { .name = "MSP430F6433", .msg29_params = {0x00, 0x105, 0xfd}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x02, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x43, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x00, 0xb0, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F6435] = { .name = "MSP430F6435", .msg29_params = {0x00, 0x106, 0xfe}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x04, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x00, 0xb0, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F6436] = { .name = "MSP430F6436", .msg29_params = {0x00, 0x107, 0xff}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x02, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0xc0, 0xb0, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F6438] = { .name = "MSP430F6438", .msg29_params = {0x00, 0x108, 0x100}, .msg29_data = { 0x00, 0x80, 0xff, 0x7f, 0x04, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x1c, 0xff, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x04, 0x02, 0x00, 0x0a, 0x00, 0x40, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0xc0, 0xb0, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x23, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FR5737] = { .name = "MSP430FR5737", .msg29_params = {0x00, 0x109, 0x101}, .msg29_data = { 0x00, 0xc2, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x18, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x00, 0x01, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0a, 0x8f, 0x8e, 0x99, 0x98, 0x97, 0x2c, 0x2d, 0x30, 0x00, 0x8a, 0x00, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FR5736] = { .name = "MSP430FR5736", .msg29_params = {0x00, 0x10a, 0x102}, .msg29_data = { 0x00, 0xc2, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x18, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x00, 0x01, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0a, 0x8f, 0x8e, 0x00, 0x00, 0x97, 0x2c, 0x00, 0x30, 0x00, 0x8a, 0x00, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FR5734] = { .name = "MSP430FR5734", .msg29_params = {0x00, 0x10b, 0x103}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x18, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x00, 0x01, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0a, 0x8f, 0x8e, 0x00, 0x00, 0x97, 0x2c, 0x00, 0x30, 0x00, 0x8a, 0xd6, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FR5733] = { .name = "MSP430FR5733", .msg29_params = {0x00, 0x10c, 0x104}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x18, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x00, 0x01, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0a, 0x8f, 0x8e, 0x99, 0x98, 0x97, 0x2c, 0x2d, 0x30, 0x00, 0x8a, 0x00, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FR5732] = { .name = "MSP430FR5732", .msg29_params = {0x00, 0x10d, 0x105}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x18, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x00, 0x01, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0a, 0x8f, 0x8e, 0x00, 0x00, 0x97, 0x2c, 0x00, 0x30, 0x00, 0x8a, 0x00, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FR5731] = { .name = "MSP430FR5731", .msg29_params = {0x00, 0x10e, 0x106}, .msg29_data = { 0x00, 0xf0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x18, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x1d, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x00, 0x01, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0a, 0x8f, 0x8e, 0x99, 0x98, 0x97, 0x2c, 0x2d, 0x30, 0x00, 0x8a, 0xd6, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FR5727] = { .name = "MSP430FR5727", .msg29_params = {0x00, 0x10f, 0x107}, .msg29_data = { 0x00, 0xc2, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x18, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x00, 0x01, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0a, 0x8f, 0x8e, 0x99, 0x98, 0x97, 0x2c, 0x2d, 0x30, 0x00, 0x8a, 0x00, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FR5726] = { .name = "MSP430FR5726", .msg29_params = {0x00, 0x110, 0x108}, .msg29_data = { 0x00, 0xc2, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x18, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x00, 0x01, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0a, 0x8f, 0x8e, 0x00, 0x00, 0x97, 0x2c, 0x00, 0x30, 0x00, 0x8a, 0x00, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FR5724] = { .name = "MSP430FR5724", .msg29_params = {0x00, 0x111, 0x109}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x18, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x00, 0x01, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0a, 0x8f, 0x8e, 0x00, 0x00, 0x97, 0x2c, 0x00, 0x30, 0x00, 0x8a, 0xd6, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FR5723] = { .name = "MSP430FR5723", .msg29_params = {0x00, 0x112, 0x10a}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x18, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x00, 0x01, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0a, 0x8f, 0x8e, 0x99, 0x98, 0x97, 0x2c, 0x2d, 0x30, 0x00, 0x8a, 0x00, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FR5722] = { .name = "MSP430FR5722", .msg29_params = {0x00, 0x113, 0x10b}, .msg29_data = { 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x18, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x00, 0x01, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0a, 0x8f, 0x8e, 0x00, 0x00, 0x97, 0x2c, 0x00, 0x30, 0x00, 0x8a, 0x00, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430FR5721] = { .name = "MSP430FR5721", .msg29_params = {0x00, 0x114, 0x10c}, .msg29_data = { 0x00, 0xf0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x18, 0xff, 0x18, 0x00, 0x00, 0x00, 0x1c, 0xff, 0x1d, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x02, 0x00, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x00, 0x01, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0a, 0x8f, 0x8e, 0x99, 0x98, 0x97, 0x2c, 0x2d, 0x30, 0x00, 0x8a, 0xd6, 0xa8, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5228] = { .name = "MSP430F5228", .msg29_params = {0x00, 0x115, 0x10d}, .msg29_data = { 0x00, 0x44, 0xff, 0xc3, 0x01, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x24, 0xff, 0x43, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5227] = { .name = "MSP430F5227", .msg29_params = {0x00, 0x116, 0x10e}, .msg29_data = { 0x00, 0x44, 0xff, 0x43, 0x01, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x24, 0xff, 0x43, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5224] = { .name = "MSP430F5224", .msg29_params = {0x00, 0x117, 0x10f}, .msg29_data = { 0x00, 0x44, 0xff, 0x43, 0x02, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x24, 0xff, 0x43, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5223] = { .name = "MSP430F5223", .msg29_params = {0x00, 0x118, 0x110}, .msg29_data = { 0x00, 0x44, 0xff, 0xc3, 0x01, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x24, 0xff, 0x43, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5222] = { .name = "MSP430F5222", .msg29_params = {0x00, 0x119, 0x111}, .msg29_data = { 0x00, 0x44, 0xff, 0x43, 0x01, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x24, 0xff, 0x43, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5219] = { .name = "MSP430F5219", .msg29_params = {0x00, 0x11a, 0x112}, .msg29_data = { 0x00, 0x44, 0xff, 0x43, 0x02, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x24, 0xff, 0x43, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0x00, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5218] = { .name = "MSP430F5218", .msg29_params = {0x00, 0x11b, 0x113}, .msg29_data = { 0x00, 0x44, 0xff, 0xc3, 0x01, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x24, 0xff, 0x43, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0x00, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5217] = { .name = "MSP430F5217", .msg29_params = {0x00, 0x11c, 0x114}, .msg29_data = { 0x00, 0x44, 0xff, 0x43, 0x01, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x24, 0xff, 0x43, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0x00, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430F5229] = { .name = "MSP430F5212/3/4", .msg29_params = {0x00, 0x11d, 0xe2}, .msg29_data = { 0x00, 0x44, 0xff, 0x43, 0x02, 0x00, 0x00, 0x18, 0xff, 0x19, 0x80, 0x00, 0x00, 0x24, 0xff, 0x43, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x02, 0x00, 0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }, .msg2b_len = 0x4a, .msg2b_data = { 0x00, 0x10, 0xff, 0x17, 0x00, 0x02, 0x02, 0x00, 0x0a, 0x00, 0x20, 0x00, 0x0a, 0x91, 0x8e, 0x8f, 0x9d, 0x00, 0x28, 0x29, 0x2a, 0x2b, 0x8a, 0xd8, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, }, [DT_MSP430G2955] = { /* Copied from MSP430G2453, with modifications */ .name = "MSP430G2955", .msg29_params = {0x00, 0x39, 0x31}, .msg29_data = { /* Copied from MSP430G2453, with changes */ 0x00, 0x21, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0xff, 0x10, 0x00, 0x01, 0x00, 0x11, 0xff, 0x20, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07, 0x10, 0x0e, 0xc4, 0x09, 0x70, 0x17, 0x58, 0x1b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x0f, 0x1f, 0x0f, 0xff, 0xff }, .msg2b_len = 0x4a, .msg2b_data = { /* Copied from MSP430G2452 */ 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x02, 0x02, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }; int fet_olimex_db_find_by_name(const char *name) { int i; for (i = 1; sdeviceID[i].name; i++) { const struct device_table *r = &sdeviceID[i]; if (!strcasecmp(r->name, name)) return i; } return -1; } int fet_olimex_db_enum(fet_olimex_db_enum_func_t func, void *user_data) { int i; for (i = 1; sdeviceID[i].name; i++) if (func(user_data, sdeviceID[i].name) < 0) return -1; return 0; } int fet_olimex_db_identify(const uint8_t *data) { uint16_t fuse = LE_WORD(data, 16); int i; for (i = 1; sdeviceID[i].name; i++) { if (((0xFF == sdeviceID[i].device_id_param[0]) || (sdeviceID[i].device_id_param[0] == data[ID0_OFFSET])) && ((0xFF == sdeviceID[i].device_id_param[1]) || (sdeviceID[i].device_id_param[1] == data[ID1_OFFSET])) && ((0xFF == sdeviceID[i].device_id_param[2]) || (sdeviceID[i].device_id_param[2] == data[REV_OFFSET])) && ((0xFF == sdeviceID[i].device_id_param[3]) || (sdeviceID[i].device_id_param[3] == data[FAB_ID_OFFSET])) && ((0xFF == sdeviceID[i].device_id_param[4]) || (sdeviceID[i].device_id_param[4] == data[SELF_TEST0_OFFSET])) && ((0xFF == sdeviceID[i].device_id_param[5]) || (sdeviceID[i].device_id_param[5] == data[SELF_TEST1_OFFSET])) && ((0xFF == sdeviceID[i].device_id_param[6]) || (sdeviceID[i].device_id_param[6] == data[EMB_SYS_OFFSET]))) { if (0xFF != sdeviceID[i].device_id_param[7]) { if ((sdeviceID[i].device_id_param[7] & sdeviceID[i].device_id_param[8]) == (fuse & sdeviceID[i].device_id_param[8])) return i; } else { return i; } } } return -1; } devicetype_t fet_olimex_db_index_to_type(int indx) { if (indx < 1) return DT_UNKNOWN_DEVICE; return sdeviceID[indx].device_type_id; } const struct fet_olimex_db_record *fet_db_get_record(devicetype_t type) { const struct fet_olimex_db_record *rec = &fet_olimex_db[type]; if (type <= 0) return NULL; if (!rec->name) return NULL; return rec; } mspdebug-0.25/drivers/fet_olimex_db.h000066400000000000000000000044751313531517500177130ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * Copyright (C) 2012 Stanimir Bonev * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef FET_OLIMEX_DB_H_ #define FET_OLIMEX_DB_H_ #include #include "devicelist.h" #define FET_OLIMEX_DB_MSG28_LEN 0x12 #define FET_OLIMEX_DB_MSG29_PARAMS 3 #define FET_OLIMEX_DB_MSG29_LEN 0x4a #define FET_OLIMEX_DB_MSG2B_LEN 0x4a struct fet_olimex_db_record { const char *name; int msg29_params[FET_OLIMEX_DB_MSG29_PARAMS]; uint8_t msg29_data[FET_OLIMEX_DB_MSG29_LEN]; uint8_t msg2b_data[FET_OLIMEX_DB_MSG2B_LEN]; int msg2b_len; }; /* Find a record in the database by name. The search is case-insensitive. * * Returns a device index on success or -1 if the device could not be * found. */ int fet_olimex_db_find_by_name(const char *name); /* Call the given enumeration function for all records in the database. * * If the callback returns -1, enumeration is aborted and the enumerator * function returns -1. Otherwise, 0 is returned. */ typedef int (*fet_olimex_db_enum_func_t)(void *user_data, const char *name); int fet_olimex_db_enum(fet_olimex_db_enum_func_t func, void *user_data); /* Find suitable device index. Given 9 bytes of identification data, return * the device index, or -1 if the device can't be identified. */ int fet_olimex_db_identify(const uint8_t *data); /* Convert a device index to a device type. */ devicetype_t fet_olimex_db_index_to_type(int index); /* Return configuration data for a given device type. */ const struct fet_olimex_db_record *fet_db_get_record(devicetype_t type); #endif mspdebug-0.25/drivers/fet_proto.c000066400000000000000000000236261313531517500171060ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009-2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include "util.h" #include "fet_proto.h" #include "fet_error.h" #include "output.h" /********************************************************************* * Checksum calculation * * This code table is also derived from uif430. */ static const uint16_t fcstab[256] = { 0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf, 0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7, 0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e, 0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876, 0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd, 0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5, 0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c, 0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974, 0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb, 0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3, 0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a, 0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72, 0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9, 0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1, 0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738, 0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70, 0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7, 0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff, 0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036, 0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e, 0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5, 0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd, 0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134, 0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c, 0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3, 0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb, 0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232, 0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a, 0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1, 0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9, 0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330, 0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78 }; static uint16_t calc_checksum(uint8_t *cp, int len) { uint16_t fcs = 0xffff; while (len--) { fcs = (fcs >> 8) ^ fcstab[(fcs ^ *cp++) & 0xff]; } return fcs ^ 0xffff; } /********************************************************************* * FET packet transfer. This level of the interface deals in packets * send to/from the device. */ /* This is a type of data transfer which appears to be unique to * the RF2500. Blocks of data are sent to an internal buffer. Each * block is prefixed with a buffer offset and a payload length. * * No checksums are included. */ static int send_rf2500_data(struct fet_proto *dev, const uint8_t *data, int len) { int offset = 0; while (len) { uint8_t pbuf[63]; int plen = len > 59 ? 59 : len; pbuf[0] = 0x83; pbuf[1] = offset & 0xff; pbuf[2] = offset >> 8; pbuf[3] = plen; memcpy(pbuf + 4, data, plen); if (dev->transport->ops->send(dev->transport, pbuf, plen + 4) < 0) return -1; data += plen; len -= plen; offset += plen; } return 0; } #define PTYPE_ACK 0 #define PTYPE_CMD 1 #define PTYPE_PARAM 2 #define PTYPE_DATA 3 #define PTYPE_MIXED 4 #define PTYPE_NAK 5 #define PTYPE_FLASH_ACK 6 static int parse_packet(struct fet_proto *dev, int plen) { uint16_t c = calc_checksum(dev->fet_buf + 2, plen - 2); uint16_t r = LE_WORD(dev->fet_buf, plen); int i = 2; int type; if (c != r) { printc_err("fet: checksum error (calc %04x," " recv %04x)\n", c, r); return -1; } if (plen < 6) goto too_short; dev->command_code = dev->fet_buf[i++]; type = dev->fet_buf[i++]; dev->state = dev->fet_buf[i++]; dev->error = dev->fet_buf[i++]; if (dev->error) { printc_err("fet: FET returned error code %d (%s)\n", dev->error, fet_error(dev->error)); return -1; } if (type == PTYPE_NAK) { printc_err("fet: FET returned NAK\n"); return -1; } /* Parse packet parameters */ if (type == PTYPE_PARAM || type == PTYPE_MIXED) { int j; if (i + 2 > plen) goto too_short; dev->argc = LE_WORD(dev->fet_buf, i); i += 2; if (dev->argc >= FET_PROTO_MAX_PARAMS) { printc_err("fet: too many params: %d\n", dev->argc); return -1; } for (j = 0; j < dev->argc; j++) { if (i + 4 > plen) goto too_short; dev->argv[j] = LE_LONG(dev->fet_buf, i); i += 4; } } else { dev->argc = 0; } /* Extract a pointer to the data */ if (type == PTYPE_DATA || type == PTYPE_MIXED) { if (i + 4 > plen) goto too_short; dev->datalen = LE_LONG(dev->fet_buf, i); i += 4; if (i + dev->datalen > plen) goto too_short; dev->data = dev->fet_buf + i; } else { dev->data = NULL; dev->datalen = 0; } return 0; too_short: printc_err("fet: too short (%d bytes)\n", plen); return -1; } static void do_chomp_ff(struct fet_proto *dev) { int chomp_len = 0; while ((chomp_len < dev->fet_len) && dev->fet_buf[chomp_len] == 0xff) chomp_len++; if (chomp_len) memmove(dev->fet_buf, dev->fet_buf + chomp_len, dev->fet_len - chomp_len); dev->fet_len -= chomp_len; } /* Receive a packet from the FET. The usual format is: * * * The length is that of the data + checksum. Olimex JTAG adapters follow * all packets with a trailing 0x7e byte, which must be discarded. */ static int recv_packet(struct fet_proto *dev, int chomp_ff) { int pkt_extra = (dev->proto_flags & FET_PROTO_EXTRA_RECV) ? 3 : 2; int plen = LE_WORD(dev->fet_buf, 0); /* If there's a packet still here from last time, get rid of it */ if (dev->fet_len >= plen + pkt_extra) { memmove(dev->fet_buf, dev->fet_buf + plen + pkt_extra, dev->fet_len - plen - pkt_extra); dev->fet_len -= plen + pkt_extra; } /* Keep adding data to the buffer until we have a complete packet */ for (;;) { int len; plen = LE_WORD(dev->fet_buf, 0); if (dev->fet_len >= plen + pkt_extra) return parse_packet(dev, plen); len = dev->transport->ops->recv(dev->transport, dev->fet_buf + dev->fet_len, sizeof(dev->fet_buf) - dev->fet_len); if (len < 0) return -1; dev->fet_len += len; if (chomp_ff) do_chomp_ff(dev); } return -1; } static int send_command(struct fet_proto *dev, int command_code, const uint32_t *params, int nparams, const uint8_t *extra, int exlen) { uint8_t datapkt[FET_PROTO_MAX_BLOCK * 2]; int len = 0; uint8_t buf[FET_PROTO_MAX_BLOCK * 3]; uint16_t cksum; int i = 0; int j; assert (len + exlen + 2 <= sizeof(datapkt)); /* Command code and packet type */ datapkt[len++] = command_code; datapkt[len++] = ((nparams > 0) ? 1 : 0) + ((exlen > 0) ? 2 : 0) + 1; /* Optional parameters */ if (nparams > 0) { datapkt[len++] = nparams & 0xff; datapkt[len++] = nparams >> 8; for (j = 0; j < nparams; j++) { uint32_t p = params[j]; datapkt[len++] = p & 0xff; p >>= 8; datapkt[len++] = p & 0xff; p >>= 8; datapkt[len++] = p & 0xff; p >>= 8; datapkt[len++] = p & 0xff; } } /* Extra data */ if (extra) { int x = exlen; datapkt[len++] = x & 0xff; x >>= 8; datapkt[len++] = x & 0xff; x >>= 8; datapkt[len++] = x & 0xff; x >>= 8; datapkt[len++] = x & 0xff; memcpy(datapkt + len, extra, exlen); len += exlen; } /* Checksum */ cksum = calc_checksum(datapkt, len); datapkt[len++] = cksum & 0xff; datapkt[len++] = cksum >> 8; /* Copy into buf, escaping special characters and adding * delimeters. */ if (!(dev->proto_flags & FET_PROTO_NOLEAD_SEND)) buf[i++] = 0x7e; for (j = 0; j < len; j++) { char c = datapkt[j]; if (c == 0x7e || c == 0x7d) { buf[i++] = 0x7d; c ^= 0x20; } buf[i++] = c; } buf[i++] = 0x7e; assert (i < sizeof(buf)); return dev->transport->ops->send(dev->transport, buf, i); } void fet_proto_init(struct fet_proto *dev, transport_t transport, int proto_flags) { dev->transport = transport; dev->proto_flags = proto_flags; dev->fet_len = 0; } int fet_proto_xfer(struct fet_proto *dev, int command_code, const uint8_t *data, int datalen, int nparams, ...) { uint32_t params[FET_PROTO_MAX_PARAMS]; int i; va_list ap; assert (nparams <= FET_PROTO_MAX_PARAMS); va_start(ap, nparams); for (i = 0; i < nparams; i++) params[i] = va_arg(ap, uint32_t); va_end(ap); if (data && (dev->proto_flags & FET_PROTO_SEPARATE_DATA)) { assert (nparams + 1 <= FET_PROTO_MAX_PARAMS); params[nparams++] = datalen; if (send_rf2500_data(dev, data, datalen) < 0) return -1; if (send_command(dev, command_code, params, nparams, NULL, 0) < 0) return -1; } else if (send_command(dev, command_code, params, nparams, data, datalen) < 0) return -1; /* Olimex devices sometimes return a spurious 0xff before their * response to C_INITIALIZE. */ if (recv_packet(dev, (command_code == 0x01)) < 0) return -1; if (dev->command_code != command_code) { printc_err("fet: reply type mismatch\n"); return -1; } return 0; } mspdebug-0.25/drivers/fet_proto.h000066400000000000000000000036371313531517500171130ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009-2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef FET_PROTO_H_ #define FET_PROTO_H_ #include #include "transport.h" /* Send data in separate packets, as in the RF2500 */ #define FET_PROTO_SEPARATE_DATA 0x01 /* Received packets have an extra trailing byte */ #define FET_PROTO_EXTRA_RECV 0x02 /* Command packets have no leading \x7e */ #define FET_PROTO_NOLEAD_SEND 0x04 /* Data transfer limits */ #define FET_PROTO_MAX_PARAMS 16 #define FET_PROTO_MAX_BLOCK 4096 /* Protocol parser structure */ struct fet_proto { transport_t transport; int proto_flags; /* Raw packet buffer */ uint8_t fet_buf[65538]; int fet_len; /* Received packet is parsed into these fields */ int command_code; int state; int error; int argc; uint32_t argv[FET_PROTO_MAX_PARAMS]; uint8_t *data; int datalen; }; /* Initialize a FET protocol parser */ void fet_proto_init(struct fet_proto *p, transport_t trans, int proto_flags); /* Perform a command-response transfer */ int fet_proto_xfer(struct fet_proto *p, int command_code, const uint8_t *data, int datalen, int nparams, ...); #endif mspdebug-0.25/drivers/flash_bsl.c000066400000000000000000000372221313531517500170370ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009, 2010 Daniel Beer * Copyright (C) 2010 Andrew Armenia * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include #include #include #include "flash_bsl.h" #include "util.h" #include "output.h" #include "fet_error.h" #include "sport.h" #include "bsllib.h" struct flash_bsl_device { struct device base; sport_t serial_fd; int long_password; const struct device_args *args; const char *seq; }; #define MAX_BLOCK 256 /* This should be at least MAX_BLOCK + 4 */ #define MAX_PACKET 512 /* adapted from TI's published BSL source code */ #define CRC_INIT 0xffff static uint16_t crc_ccitt(const uint8_t *data, int len) { uint16_t crc = CRC_INIT; uint16_t temp; int i; for (i = 0; i < len; ++i) { temp = ((crc >> 8) ^ data[i]) & 0xff; temp ^= (temp >> 4); crc = (crc << 8) ^ (temp << 12) ^ (temp << 5) ^ temp; } return crc; } static void crc_selftest(void) { /* These test vectors are from page 30 of TI doc SLAU319A */ uint16_t crc_expected = 0x5590; uint16_t crc_actual = crc_ccitt((uint8_t *)"\x52\x02", 2); if (crc_expected != crc_actual) { printc_err("flash_bsl: CRC malfunction " "(expected 0x%04x got 0x%04x)\n", crc_expected, crc_actual); } crc_expected = 0x121d; crc_actual = crc_ccitt((uint8_t *)"\x3a\x04\x01", 3); if (crc_expected != crc_actual) { printc_err("flash_bsl: CRC malfunction " "(expected 0x%04x got 0x%04x)\n", crc_expected, crc_actual); } crc_expected = 0x528b; crc_actual = crc_ccitt((uint8_t *)"\x1a", 1); if (crc_expected != crc_actual) { printc_err("flash_bsl: CRC malfunction " "(expected 0x%04x got 0x%04x)\n", crc_expected, crc_actual); } } #define RX_DATA_BLOCK 0x10 #define RX_DATA_BLOCK_FAST 0x1b #define RX_PASSWORD 0x11 #define ERASE_SEGMENT 0x12 #define UNLOCK_LOCK_INFO 0x13 #define MASS_ERASE 0x15 #define CRC_CHECK 0x16 #define LOAD_PC 0x17 #define TX_DATA_BLOCK 0x18 #define TX_BSL_VERSION 0x19 #define TX_BUFFER_SIZE 0x1a static int flash_bsl_send(struct flash_bsl_device *dev, const uint8_t *data, int len) { uint16_t crc; uint8_t cmd_buf[MAX_PACKET + 5]; uint8_t response; #if defined(FLASH_BSL_VERBOSE) debug_hexdump("flash_bsl: sending", data, len); #endif crc = crc_ccitt(data, len); if (len > MAX_PACKET) { printc_err("flash_bsl: attempted to transmit " "long packet (len=%d)\n", len); return -1; } cmd_buf[0] = 0x80; cmd_buf[1] = (len & 0xff); cmd_buf[2] = (len >> 8) & 0xff; memcpy(cmd_buf + 3, data, len); cmd_buf[len + 3] = (crc & 0xff); cmd_buf[len + 4] = (crc >> 8) & 0xff; if (sport_write_all(dev->serial_fd, cmd_buf, len + 5) < 0) { printc_err("flash_bsl: serial write failed: %s\n", last_error()); return -1; } if (sport_read_all(dev->serial_fd, &response, 1) < 0) { printc_err("flash_bsl: serial read failed: %s\n", last_error()); return -1; } if (response != 0) { switch (response) { case 0x51: printc_err("flash_bsl: BSL reports incorrect " "packet header\n"); break; case 0x52: printc_err("flash_bsl: BSL reports checksum " "incorrect\n"); break; case 0x53: printc_err("flash_bsl: BSL got zero-size packet\n"); break; case 0x54: printc_err("flash_bsl: BSL receive buffer " "overflowed\n"); break; case 0x55: printc_err("flash_bsl: (known-)unknown error\n"); break; case 0x56: printc_err("flash_bsl: unknown baud rate\n"); break; default: printc_err("flash_bsl: unknown unknown error\n"); break; } return -1; } return 0; } static int flash_bsl_recv(struct flash_bsl_device *dev, uint8_t *recv_buf, int buf_len) { uint8_t header[3]; uint8_t crc_bytes[2]; uint16_t recv_len; uint16_t crc_value; if (sport_read_all(dev->serial_fd, header, 3) < 0) { printc_err("flash_bsl: read response failed: %s\n", last_error()); return -1; } if (header[0] != 0x80) { printc_err("flash_bsl: incorrect response header received\n"); return -1; } recv_len = header[2]; recv_len <<= 8; recv_len |= header[1]; #if defined(FLASH_BSL_VERBOSE) printc_dbg("flash_bsl: incoming message length %d\n", recv_len); #endif if (recv_len > buf_len) { printc_err("flash_bsl: insufficient buffer to receive data\n"); return -1; } if (sport_read_all(dev->serial_fd, recv_buf, recv_len) < 0) { perror("receive message"); printc_err("flash_bsl: error receiving message\n"); return -1; } if (sport_read_all(dev->serial_fd, crc_bytes, 2) < 0) { perror("receive message CRC"); printc_err("flash_bsl: error receiving message CRC\n"); return -1; } crc_value = crc_bytes[1]; crc_value <<= 8; crc_value |= crc_bytes[0]; if (crc_ccitt(recv_buf, recv_len) != crc_value) { printc_err("flash_bsl: received message with bad CRC\n"); return -1; } #if defined(FLASH_BSL_VERBOSE) debug_hexdump("received message", recv_buf, recv_len); #endif delay_ms(10); return recv_len; } static void flash_bsl_perror(uint8_t code) { switch (code) { case 0x00: printc_err("flash_bsl: success\n"); break; case 0x01: printc_err("flash_bsl: FLASH verify failed\n"); break; case 0x02: printc_err("flash_bsl: FLASH operation failed\n"); break; case 0x03: printc_err("flash_bsl: voltage not constant during program\n"); break; case 0x04: printc_err("flash_bsl: BSL is locked\n"); break; case 0x05: printc_err("flash_bsl: incorrect password\n"); break; case 0x06: printc_err("flash_bsl: attempted byte write to FLASH\n"); break; case 0x07: printc_err("flash_bsl: unrecognized command\n"); break; case 0x08: printc_err("flash_bsl: command was too long\n"); break; default: printc_err("flash_bsl: unknown status message\n"); break; } } static int flash_bsl_readmem(device_t dev_base, address_t addr, uint8_t *mem, address_t len) { struct flash_bsl_device *dev = (struct flash_bsl_device *)dev_base; uint8_t recv_buf[MAX_BLOCK*2]; uint8_t send_buf[64]; uint16_t read_size; int ret; if (addr > 0xfffff || addr + len > 0x100000) { printc_err("flash_bsl: read exceeds possible range\n"); return -1; } while (len > 0) { if (len > MAX_BLOCK) { read_size = MAX_BLOCK; } else { read_size = len; } /* build command */ send_buf[0] = TX_DATA_BLOCK; /* command: transmit data block */ send_buf[1] = addr & 0xff; send_buf[2] = (addr >> 8) & 0xff; send_buf[3] = (addr >> 16) & 0xff; send_buf[4] = read_size & 0xff; send_buf[5] = (read_size >> 8) & 0xff; if (flash_bsl_send(dev, send_buf, 6) < 0) { printc_err("flash_bsl readmem: send failed\n"); return -1; } ret = flash_bsl_recv(dev, recv_buf, read_size + 1); if (ret < 0) { printc_err("flash_bsl readmem: receive failed\n"); return -1; } else if (ret < read_size) { printc_err("flash_bsl readmem: warning: not all requested data received\n"); } if (recv_buf[0] == 0x3a) { memcpy(mem, recv_buf + 1, ret - 1); addr += ret - 1; len -= ret - 1; mem += ret - 1; } else if (recv_buf[0] == 0x3b) { flash_bsl_perror(recv_buf[1]); } else { printc_err("flash_bsl readmem: invalid response\n"); return -1; } } return 0; } static int flash_bsl_erase(device_t dev_base, device_erase_type_t type, address_t addr) { struct flash_bsl_device *dev = (struct flash_bsl_device *)dev_base; uint8_t erase_cmd[4]; uint8_t response_buffer[16]; int ret; if (type == DEVICE_ERASE_ALL) { printc_err("flash_bsl_erase: simultaneous code/info erase not supported\n"); return -1; } else if (type == DEVICE_ERASE_MAIN) { erase_cmd[0] = MASS_ERASE; if (flash_bsl_send(dev, erase_cmd, 1) < 0) { printc_err("flash_bsl_erase: failed to send erase command\n"); return -1; } } else if (type == DEVICE_ERASE_SEGMENT) { erase_cmd[0] = ERASE_SEGMENT; erase_cmd[1] = addr & 0xff; erase_cmd[2] = (addr >> 8) & 0xff; erase_cmd[3] = (addr >> 16) & 0xff; if (flash_bsl_send(dev, erase_cmd, 4) < 0) { printc_err("flash_bsl_erase: failed to send erase command\n"); return -1; } } else { printc_err("flash_bsl_erase: unsupported erase type\n"); return -1; } ret = flash_bsl_recv(dev, response_buffer, sizeof(response_buffer)); if (ret < 2) { printc_err("flash_bsl_erase: no response\n"); return -1; } if (response_buffer[0] != 0x3b) { printc_err("flash_bsl_erase: incorrect response\n"); return -1; } if (response_buffer[1] != 0) { flash_bsl_perror(response_buffer[1]); printc_err("flash_bsl_erase: erase failed\n"); return -1; } else { #if defined(FLASH_BSL_VERBOSE) printc_dbg("flash_bsl_erase: success\n"); #endif } return 0; } static int flash_bsl_unlock(struct flash_bsl_device *dev) { /* * after erase, the password will be 0xff * (16 or 32) * (an empty interrupt vector table) */ uint8_t rx_password_cmd[33] = "\x11" "\xff\xff\xff\xff\xff\xff\xff\xff" "\xff\xff\xff\xff\xff\xff\xff\xff" "\xff\xff\xff\xff\xff\xff\xff\xff" "\xff\xff\xff\xff\xff\xff\xff\xff"; uint8_t response_buffer[16]; int ret; /* mass erase - this might wipe Information Memory on some devices */ /* (according to the documentation it should not) */ if (flash_bsl_erase((device_t)dev, DEVICE_ERASE_MAIN, 0) < 0) { printc_err("flash_bsl_unlock: warning: erase failed\n"); } /* send password (which is now erased FLASH) */ if (dev->long_password) { #if defined(FLASH_BSL_VERBOSE) printc_dbg("flash_bsl_unlock: using long password\n"); #endif } if (flash_bsl_send(dev, rx_password_cmd, dev->long_password ? 33 : 17) < 0) { printc_err("flash_bsl_unlock: send password failed\n"); return -1; } ret = flash_bsl_recv(dev, response_buffer, sizeof(response_buffer)); if (ret < 2) { printc_err("flash_bsl_unlock: error receiving password response\n"); return -1; } if (response_buffer[0] != 0x3b) { printc_err("flash_bsl_unlock: received invalid password response\n"); return -1; } if (response_buffer[1] != 0x00) { flash_bsl_perror(response_buffer[1]); printc_err("flash_bsl_unlock: password error\n"); return -1; } return 0; } static int flash_bsl_ctl(device_t dev_base, device_ctl_t type) { (void)dev_base; switch (type) { case DEVICE_CTL_HALT: /* Ignore halt requests */ return 0; case DEVICE_CTL_RESET: /* Ignore reset requests */ return 0; default: printc_err("flash_bsl: CPU control is not possible\n"); } return -1; } static device_status_t flash_bsl_poll(device_t dev_base) { (void)dev_base; return DEVICE_STATUS_HALTED; } static int flash_bsl_getregs(device_t dev_base, address_t *regs) { (void)dev_base; (void)regs; printc_err("flash_bsl: register fetch is not implemented\n"); return -1; } static int flash_bsl_setregs(device_t dev_base, const address_t *regs) { (void)dev_base; (void)regs; printc_err("flash_bsl: register store is not implemented\n"); return -1; } static int flash_bsl_writemem(device_t dev_base, address_t addr, const uint8_t *mem, address_t len) { struct flash_bsl_device *dev = (struct flash_bsl_device *)dev_base; uint8_t send_buf[2*MAX_BLOCK]; uint8_t recv_buf[16]; uint16_t write_size; int n_recv; if (addr > 0xfffff || addr + len > 0x100000) { printc_err("flash_bsl: write exceeds possible range\n"); return -1; } while (len > 0) { /* compute size of this write operation */ if (len > MAX_BLOCK) { write_size = MAX_BLOCK; } else { write_size = len; } /* build write command */ /* command */ send_buf[0] = RX_DATA_BLOCK; /* address */ send_buf[1] = addr & 0xff; send_buf[2] = (addr >> 8) & 0xff; send_buf[3] = (addr >> 16) & 0xff; /* data */ memcpy(&send_buf[4], mem, write_size); addr += write_size; mem += write_size; len -= write_size; /* send command */ if (flash_bsl_send(dev, send_buf, write_size + 4) < 0) { printc_err("flash_bsl: send failed\n"); return -1; } /* receive and check response */ n_recv = flash_bsl_recv(dev, recv_buf, sizeof(recv_buf)); if (n_recv < 0) { printc_err("flash_bsl write: error occurred receiving response\n"); return -1; } else if (n_recv < 2) { printc_err("flash_bsl write: response too short\n"); return -1; } else if (recv_buf[0] != 0x3b) { printc_err("flash_bsl write: invalid response received\n"); return -1; } else if (recv_buf[1] != 0x00) { printc_err("flash_bsl write: BSL reported write error: "); flash_bsl_perror(recv_buf[1]); return -1; } /* else success! */ } return 0; } static void flash_bsl_destroy(device_t dev_base) { struct flash_bsl_device *dev = (struct flash_bsl_device *)dev_base; if ( dev->args->bsl_gpio_used ) { bsllib_seq_do_gpio(dev->args->bsl_gpio_rts, dev->args->bsl_gpio_dtr, bsllib_seq_next(dev->seq)); } else { bsllib_seq_do(dev->serial_fd, bsllib_seq_next(dev->seq)); } sport_close(dev->serial_fd); free(dev); } static device_t flash_bsl_open(const struct device_args *args) { struct flash_bsl_device *dev; uint8_t tx_bsl_version_command[] = { TX_BSL_VERSION }; uint8_t tx_bsl_version_response[5]; if (!(args->flags & DEVICE_FLAG_TTY)) { printc_err("This driver does not support raw USB access.\n"); return NULL; } dev = malloc(sizeof(*dev)); if (!dev) { pr_error("flash_bsl: can't allocate memory"); return NULL; } crc_selftest( ); memset(dev, 0, sizeof(*dev)); dev->base.type = &device_flash_bsl; dev->args = args; dev->serial_fd = sport_open(args->path, 9600, SPORT_EVEN_PARITY); if (SPORT_ISERR(dev->serial_fd)) { printc_err("flash_bsl: can't open %s: %s\n", args->path, last_error()); free(dev); return NULL; } dev->seq = args->bsl_entry_seq; if (!dev->seq) dev->seq = "dR,r,R,r,R,D:dR,DR"; dev->long_password = args->flags & DEVICE_FLAG_LONG_PW; /* enter bootloader */ if ( args->bsl_gpio_used ) { if (bsllib_seq_do_gpio(args->bsl_gpio_rts, args->bsl_gpio_dtr, dev->seq) < 0) { printc_err("BSL entry sequence failed\n"); goto fail; } } else { if (bsllib_seq_do(dev->serial_fd, dev->seq) < 0) { printc_err("BSL entry sequence failed\n"); goto fail; } } delay_ms(500); /* unlock device (erase then send password) */ if (flash_bsl_unlock(dev) < 0) { goto fail; } if (flash_bsl_send(dev, tx_bsl_version_command, sizeof(tx_bsl_version_command)) < 0) { printc_err("flash_bsl: failed to read BSL version"); goto fail; } if (flash_bsl_recv(dev, tx_bsl_version_response, sizeof(tx_bsl_version_response)) < sizeof(tx_bsl_version_response)) { printc_err("flash_bsl: BSL responded with invalid version"); goto fail; } debug_hexdump("BSL version", tx_bsl_version_response, sizeof(tx_bsl_version_response)); return (device_t)dev; fail: sport_close(dev->serial_fd); free(dev); return NULL; } const struct device_class device_flash_bsl = { .name = "flash-bsl", .help = "TI generic flash-based bootloader via RS-232", .open = flash_bsl_open, .destroy = flash_bsl_destroy, .readmem = flash_bsl_readmem, .writemem = flash_bsl_writemem, .getregs = flash_bsl_getregs, .setregs = flash_bsl_setregs, .ctl = flash_bsl_ctl, .poll = flash_bsl_poll, .erase = flash_bsl_erase, .getconfigfuses = NULL }; mspdebug-0.25/drivers/flash_bsl.h000066400000000000000000000017651313531517500170470ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * Copyright (C) 2010 Andrew Armenia * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef FLASH_BSL_H_ #define FLASH_BSL_H_ #include "device.h" /* MSP430 Flash bootloader implementation. */ extern const struct device_class device_flash_bsl; #endif mspdebug-0.25/drivers/gdbc.c000066400000000000000000000230601313531517500157740ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2011 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include "sockets.h" #include "output.h" #include "gdbc.h" #include "gdb_proto.h" #include "opdb.h" #include "util.h" #include "ctrlc.h" struct gdb_client { struct device base; struct gdb_data gdb; int is_running; struct device_breakpoint last_bps[DEVICE_MAX_BREAKPOINTS]; }; static int get_xfer_size(void) { int x = opdb_get_numeric("gdbc_xfer_size"); if (x < 2) return 2; if (x > GDB_MAX_XFER) return GDB_MAX_XFER; return x; } static int check_ok(struct gdb_data *gdb) { char buf[GDB_BUF_SIZE]; int len; len = gdb_read_packet(gdb, buf); if (len < 0) return -1; if (len < 1 || buf[0] == 'E') { printc_err("gdbc: bad response: %s\n", buf); return -1; } return 0; } static void gdbc_destroy(device_t dev_base) { struct gdb_client *c = (struct gdb_client *)dev_base; shutdown(c->gdb.sock, 2); closesocket(c->gdb.sock); free(c); } static int gdbc_readmem(device_t dev_base, address_t addr, uint8_t *mem, address_t len) { struct gdb_client *dev = (struct gdb_client *)dev_base; int xfer_size = get_xfer_size(); char buf[GDB_BUF_SIZE]; while (len) { int plen = len > xfer_size ? xfer_size : len; int r; int i; gdb_packet_start(&dev->gdb); gdb_printf(&dev->gdb, "m%04x,%x", addr, plen); gdb_packet_end(&dev->gdb); if (gdb_flush_ack(&dev->gdb) < 0) return -1; r = gdb_read_packet(&dev->gdb, buf); if (r < 0) return -1; if (r < plen * 2) { printc_err("gdbc: short read at 0x%04x: expected %d " "bytes, got %d\n", addr, plen, r / 2); return -1; } for (i = 0; i * 2 < r; i++) mem[i] = (hexval(buf[i * 2]) << 4) | hexval(buf[i * 2 + 1]); mem += plen; len -= plen; addr += plen; } return 0; } static int gdbc_writemem(device_t dev_base, address_t addr, const uint8_t *mem, address_t len) { struct gdb_client *dev = (struct gdb_client *)dev_base; int xfer_size = get_xfer_size(); while (len) { int plen = len > xfer_size ? xfer_size : len; int i; gdb_packet_start(&dev->gdb); gdb_printf(&dev->gdb, "M%04x,%x:", addr, plen); for (i = 0; i < plen; i++) gdb_printf(&dev->gdb, "%02x", mem[i]); gdb_packet_end(&dev->gdb); if (gdb_flush_ack(&dev->gdb) < 0) return -1; if (check_ok(&dev->gdb) < 0) return -1; mem += plen; len -= plen; addr += plen; } return 0; } static int gdbc_getregs(device_t dev_base, address_t *regs) { struct gdb_client *dev = (struct gdb_client *)dev_base; char buf[GDB_BUF_SIZE]; int len; int i; if (gdb_send(&dev->gdb, "g") < 0) return -1; len = gdb_read_packet(&dev->gdb, buf); if (len < 0) return -1; if (len < DEVICE_NUM_REGS * 4) { printc_err("gdbc: short read: expected %d chars, got %d\n", DEVICE_NUM_REGS * 4, len); return -1; } for (i = 0; i < DEVICE_NUM_REGS; i++) { char *text = buf + i * 4; regs[i] = (hexval(text[0]) << 4) | (hexval(text[1])) | (hexval(text[2]) << 12) | (hexval(text[3]) << 8); } return 0; } static int gdbc_setregs(device_t dev_base, const address_t *regs) { struct gdb_client *dev = (struct gdb_client *)dev_base; int i; gdb_packet_start(&dev->gdb); gdb_printf(&dev->gdb, "G"); for (i = 0; i < DEVICE_NUM_REGS; i++) gdb_printf(&dev->gdb, "%02x%02x", regs[i] & 0xff, (regs[i] >> 8) & 0xff); gdb_packet_end(&dev->gdb); if (gdb_flush_ack(&dev->gdb) < 0) return -1; return check_ok(&dev->gdb); } static int do_reset(struct gdb_client *dev) { char buf[GDB_BUF_SIZE]; int len; if (gdb_send(&dev->gdb, "R00") < 0) return -1; len = gdb_read_packet(&dev->gdb, buf); if (!len) { if (gdb_send(&dev->gdb, "r") < 0) return -1; len = gdb_read_packet(&dev->gdb, buf); } if (len < 0) return -1; if (len < 2 || buf[0] != 'O' || buf[1] != 'K') { printc_err("gdbc: reset: bad response: %s\n", buf); return -1; } return 0; } static int bp_send(struct gdb_data *gdb, int c, address_t addr, device_bptype_t type) { int type_code = 0; switch (type) { case DEVICE_BPTYPE_BREAK: type_code = 1; break; case DEVICE_BPTYPE_WRITE: type_code = 2; break; case DEVICE_BPTYPE_READ: type_code = 3; break; case DEVICE_BPTYPE_WATCH: type_code = 4; break; } gdb_packet_start(gdb); gdb_printf(gdb, "%c%d,%04x,2", c, type_code, addr); gdb_packet_end(gdb); if (gdb_flush_ack(gdb) < 0) return -1; return check_ok(gdb); } static int refresh_bps(struct gdb_client *dev) { int i; for (i = 0; i < dev->base.max_breakpoints; i++) { struct device_breakpoint *bp = &dev->base.breakpoints[i]; struct device_breakpoint *old = &dev->last_bps[i]; if (!(bp->flags & DEVICE_BP_DIRTY)) continue; if ((old->flags & DEVICE_BP_ENABLED) && (bp_send(&dev->gdb, 'z', old->addr, old->type) < 0)) return -1; if ((bp->flags & DEVICE_BP_ENABLED) && (bp_send(&dev->gdb, 'Z', bp->addr, bp->type) < 0)) return -1; bp->flags &= ~DEVICE_BP_DIRTY; } memcpy(dev->last_bps, dev->base.breakpoints, sizeof(dev->last_bps)); return 0; } static int gdbc_ctl(device_t dev_base, device_ctl_t op) { struct gdb_client *dev = (struct gdb_client *)dev_base; switch (op) { case DEVICE_CTL_STEP: if (gdb_send(&dev->gdb, "s") < 0) return -1; return check_ok(&dev->gdb); case DEVICE_CTL_RUN: if (refresh_bps(dev) < 0) return -1; if (gdb_send(&dev->gdb, "c") < 0) return -1; dev->is_running = 1; return 0; case DEVICE_CTL_HALT: if (dev->is_running) { if (sockets_send(dev->gdb.sock, "\003", 1, 0) < 1) { pr_error("gdbc: write"); return -1; } dev->is_running = 0; return check_ok(&dev->gdb); } return 0; case DEVICE_CTL_RESET: return do_reset(dev); default: printc_err("gdbc: unsupported operation\n"); return -1; } return 0; } static int gdbc_erase(device_t dev_base, device_erase_type_t type, address_t addr) { struct gdb_client *dev = (struct gdb_client *)dev_base; const char *cmd = "erase"; char buf[GDB_BUF_SIZE]; int len; (void)type; (void)addr; gdb_packet_start(&dev->gdb); gdb_printf(&dev->gdb, "qRcmd,"); while (*cmd) gdb_printf(&dev->gdb, "%02x", *(cmd++)); gdb_packet_end(&dev->gdb); if (gdb_flush_ack(&dev->gdb) < 0) return -1; len = gdb_read_packet(&dev->gdb, buf); if (len < 0) return -1; return 0; } static device_status_t gdbc_poll(device_t dev_base) { struct gdb_client *dev = (struct gdb_client *)dev_base; char buf[GDB_BUF_SIZE]; int len; if (!dev->is_running) return DEVICE_STATUS_HALTED; len = gdb_peek(&dev->gdb, 50); if (ctrlc_check()) return DEVICE_STATUS_INTR; if (len < 0) { dev->is_running = 0; return DEVICE_STATUS_ERROR; } if (!len) return DEVICE_STATUS_RUNNING; len = gdb_read_packet(&dev->gdb, buf); if (len < 0) { dev->is_running = 0; return DEVICE_STATUS_ERROR; } dev->is_running = 0; return DEVICE_STATUS_HALTED; } static int connect_to(const char *spec) { const char *port_text; int hn_len; int port = 2000; char hostname[128]; struct hostent *ent; struct sockaddr_in addr; int sock; if (!spec) { printc_err("gdbc: no remote target specified\n"); return -1; } port_text = strchr(spec, ':'); if (port_text) { port = atoi(port_text + 1); hn_len = port_text - spec; } else { hn_len = strlen(spec); } if (hn_len + 1 > sizeof(hostname)) hn_len = sizeof(hostname) - 1; memcpy(hostname, spec, hn_len); hostname[hn_len] = 0; printc_dbg("Looking up %s...\n", hostname); ent = gethostbyname(hostname); if (!ent) { #ifdef __Windows__ printc_err("No such host: %s: %s\n", hostname, last_error()); #else printc_err("No such host: %s: %s\n", hostname, hstrerror(h_errno)); #endif return -1; } sock = socket(PF_INET, SOCK_STREAM, 0); if (SOCKET_ISERR(sock)) { printc_err("socket: %s\n", last_error()); return -1; } addr.sin_family = AF_INET; addr.sin_port = htons(port); addr.sin_addr = *(struct in_addr *)ent->h_addr; printc_dbg("Connecting to %s:%d...\n", inet_ntoa(addr.sin_addr), port); if (sockets_connect(sock, (struct sockaddr *)&addr, sizeof(addr)) < 0) { printc_err("connect: %s\n", last_error()); closesocket(sock); return -1; } return sock; } static device_t gdbc_open(const struct device_args *args) { int sock = connect_to(args->path); struct gdb_client *dev; if (sock < 0) return NULL; dev = malloc(sizeof(struct gdb_client)); if (!dev) { printc_err("gdbc: can't allocate memory: %s\n", last_error()); return NULL; } memset(dev, 0, sizeof(*dev)); dev->base.type = &device_gdbc; dev->base.max_breakpoints = DEVICE_MAX_BREAKPOINTS; gdb_init(&dev->gdb, sock); return (device_t)dev; } const struct device_class device_gdbc = { .name = "gdbc", .help = "GDB client mode", .open = gdbc_open, .destroy = gdbc_destroy, .readmem = gdbc_readmem, .writemem = gdbc_writemem, .erase = gdbc_erase, .getregs = gdbc_getregs, .setregs = gdbc_setregs, .ctl = gdbc_ctl, .poll = gdbc_poll, .getconfigfuses = NULL }; mspdebug-0.25/drivers/gdbc.h000066400000000000000000000016621313531517500160050ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2011 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef GDBC_H_ #define GDBC_H_ #include "device.h" /* GDB client implementation */ extern const struct device_class device_gdbc; #endif mspdebug-0.25/drivers/goodfet.c000066400000000000000000000311321313531517500165230ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include "util.h" #include "sport.h" #include "output.h" #include "goodfet.h" #include "ctrlc.h" /* GoodFET protocol definitions */ #define APP_JTAG430 0x11 #define APP_DEBUG 0xFF #define GLOBAL_READ 0x00 #define GLOBAL_WRITE 0x01 #define GLOBAL_PEEK 0x02 #define GLOBAL_POKE 0x03 #define GLOBAL_SETUP 0x10 #define GLOBAL_START 0x20 #define GLOBAL_STOP 0x21 #define GLOBAL_CALL 0x30 #define GLOBAL_EXEC 0x31 #define GLOBAL_LIMIT 0x7B #define GLOBAL_EXIST 0x7C #define GLOBAL_NMEM 0x7D #define GLOBAL_NOK 0x7E #define GLOBAL_OK 0x7F #define GLOBAL_DEBUG 0xFF #define JTAG430_HALTCPU 0xA0 #define JTAG430_RELEASECPU 0xA1 #define JTAG430_SETINSTRFETCH 0xC1 #define JTAG430_SETPC 0xC2 #define JTAG430_SETREG 0xD2 #define JTAG430_GETREG 0xD3 #define JTAG430_WRITEMEM 0xE0 #define JTAG430_WRITEFLASH 0xE1 #define JTAG430_READMEM 0xE2 #define JTAG430_ERASEFLASH 0xE3 #define JTAG430_ERASECHECK 0xE4 #define JTAG430_VERIFYMEM 0xE5 #define JTAG430_BLOWFUSE 0xE6 #define JTAG430_ISFUSEBLOWN 0xE7 #define JTAG430_ERASEINFO 0xE8 #define JTAG430_COREIP_ID 0xF0 #define JTAG430_DEVICE_ID 0xF1 /* GoodFET packet transfer */ #define MAX_LEN 1024 #define MAX_MEM_BLOCK 128 struct goodfet { struct device base; sport_t serial_fd; }; /************************************************************************ * GoodFET protocol handling */ struct packet { uint8_t app; uint8_t verb; uint16_t len; uint8_t data[MAX_LEN]; }; static int reset_sequence(sport_t fd) { static const int states[] = { SPORT_MC_RTS, SPORT_MC_RTS | SPORT_MC_DTR, SPORT_MC_DTR }; int i; printc_dbg("Resetting GoodFET...\n"); for (i = 0; i < 3; i++) { if (sport_set_modem(fd, states[i]) < 0) { printc_err("goodfet: failed at step %d: %s\n", i, last_error()); return -1; } delay_ms(20); } return 0; } static int send_packet(sport_t fd, uint8_t app, uint8_t verb, uint16_t len, const uint8_t *data) { uint8_t raw[MAX_LEN + 4]; if (len > MAX_LEN) { printc_err("goodfet: send_packet: maximum length " "exceeded (%d)\n", len); return -1; } #ifdef DEBUG_GOODFET printc_dbg("SEND: %02x/%02x\n", app, verb); if (len) debug_hexdump("Data", data, len); #endif raw[0] = app; raw[1] = verb; raw[2] = len & 0xff; raw[3] = len >> 8; memcpy(raw + 4, data, len); if (sport_write_all(fd, raw, len + 4) < 0) { printc_err("goodfet: send_packet: %s\n", last_error()); return -1; } return 0; } static int recv_packet(sport_t fd, struct packet *pkt) { uint8_t header[4]; if (sport_read_all(fd, header, 4) < 0) { printc_err("goodfet: recv_packet (header): %s\n", last_error()); return -1; } pkt->app = header[0]; pkt->verb = header[1]; pkt->len = ((uint16_t)header[2]) | (((uint16_t)header[3]) << 8); if (pkt->len > MAX_LEN) { printc_err("goodfet: recv_packet: maximum length " "exceeded (%d)\n", pkt->len); return -1; } if (sport_read_all(fd, pkt->data, pkt->len) < 0) { printc_err("goodfet: recv_packet (data): %s\n", last_error()); return -1; } #ifdef DEBUG_GOODFET printc_dbg("RECV: %02x/%02x\n", pkt->app, pkt->verb); if (pkt->len) debug_hexdump("Data", pkt->data, pkt->len); #endif return 0; } static int xfer(sport_t fd, uint8_t app, uint8_t verb, uint16_t len, const uint8_t *data, struct packet *pkt) { if (send_packet(fd, app, verb, len, data) < 0) goto fail; while (recv_packet(fd, pkt) >= 0) { if (pkt->app == APP_DEBUG && pkt->verb == GLOBAL_DEBUG) { char text[MAX_LEN + 1]; memcpy(text, pkt->data, pkt->len); text[pkt->len] = 0; printc_dbg("[GoodFET debug] %s\n", text); } if (pkt->app == app && pkt->verb == verb) return 0; } fail: printc_err("goodfet: command 0x%02x/0x%02x " "failed\n", app, verb); return -1; } /************************************************************************ * GoodFET MSP430 JTAG operations */ /* Read a word-aligned block from any kind of memory. * returns the number of bytes read or -1 on failure */ static int read_words(device_t dev, const struct chipinfo_memory *m, address_t addr, address_t len, uint8_t *data) { struct goodfet *gc = (struct goodfet *)dev; sport_t fd = gc->serial_fd; struct packet pkt; uint8_t req[6]; if (len > MAX_MEM_BLOCK) len = MAX_MEM_BLOCK; req[0] = addr; req[1] = addr >> 8; req[2] = addr >> 16; req[3] = addr >> 24; req[4] = len; req[5] = len >> 8; if (xfer(fd, APP_JTAG430, GLOBAL_PEEK, sizeof(req), req, &pkt) < 0) { printc_err("goodfet: read %d bytes from 0x%x failed\n", len, addr); return -1; } if (pkt.len != len) { printc_err("goodfet: short memory read (got %d, " "expected %d)\n", pkt.len, len); return -1; } memcpy(data, pkt.data, pkt.len); return len; } /* Write a word to RAM. */ static int write_ram_word(sport_t fd, address_t addr, uint16_t value) { uint8_t req[6]; struct packet pkt; req[0] = addr; req[1] = addr >> 8; req[2] = 0; req[3] = 0; req[4] = value; req[5] = value >> 8; if (xfer(fd, APP_JTAG430, GLOBAL_POKE, sizeof(req), req, &pkt) < 0) { printc_err("goodfet: failed to write word at 0x%x\n", addr); return -1; } return 0; } /* Write a word-aligned flash block. The starting address must be within * the flash memory range. */ static int write_flash_block(sport_t fd, address_t addr, address_t len, const uint8_t *data) { uint8_t req[MAX_MEM_BLOCK + 4]; struct packet pkt; req[0] = addr >> 0; req[1] = addr >> 8; req[2] = addr >> 16; req[3] = addr >> 24; memcpy(req + 4, data, len); if (xfer(fd, APP_JTAG430, JTAG430_WRITEFLASH, len + 4, req, &pkt) < 0) { printc_err("goodfet: failed to write " "flash block of size %d at 0x%x\n", len, addr); return -1; } return 0; } /* Write a word-aligned block to any kind of memory. * returns the number of bytes written or -1 on failure */ static int write_words(device_t dev, const struct chipinfo_memory *m, address_t addr, address_t len, const uint8_t *data) { struct goodfet *gc = (struct goodfet *)dev; sport_t fd = gc->serial_fd; int r; if (len > MAX_MEM_BLOCK) len = MAX_MEM_BLOCK; if (m->type != CHIPINFO_MEMTYPE_FLASH) { len = 2; r = write_ram_word(fd, addr, r16le(data)); } else { r = write_flash_block(fd, addr, len, data); } if (r < 0) { printc_err("goodfet: write_words at address 0x%x failed\n", addr); return -1; } return len; } static int init_device(sport_t fd) { struct packet pkt; printc_dbg("Initializing...\n"); if (xfer(fd, APP_JTAG430, GLOBAL_NOK, 0, NULL, &pkt) < 0) { printc_err("goodfet: comms test failed\n"); return -1; } printc_dbg("Setting up JTAG pins\n"); if (xfer(fd, APP_JTAG430, GLOBAL_SETUP, 0, NULL, &pkt) < 0) { printc_err("goodfet: SETUP command failed\n"); return -1; } printc_dbg("Starting JTAG\n"); if (xfer(fd, APP_JTAG430, GLOBAL_START, 0, NULL, &pkt) < 0) { printc_err("goodfet: START command failed\n"); return -1; } if (pkt.len < 1) { printc_err("goodfet: bad response to JTAG START\n"); return -1; } printc("JTAG ID: 0x%02x\n", pkt.data[0]); if (pkt.data[0] != 0x89 && pkt.data[0] != 0x91) { printc_err("goodfet: unexpected JTAG ID: 0x%02x\n", pkt.data[0]); xfer(fd, APP_JTAG430, GLOBAL_STOP, 0, NULL, &pkt); return -1; } printc_dbg("Halting CPU\n"); if (xfer(fd, APP_JTAG430, JTAG430_HALTCPU, 0, NULL, &pkt) < 0) { printc_err("goodfet: HALTCPU command failed\n"); xfer(fd, APP_JTAG430, GLOBAL_STOP, 0, NULL, &pkt); return -1; } return 0; } /************************************************************************ * MSPDebug Device interface */ static int goodfet_readmem(device_t dev_base, address_t addr, uint8_t *mem, address_t len) { return readmem(dev_base, addr, mem, len, read_words); } static int goodfet_writemem(device_t dev_base, address_t addr, const uint8_t *mem, address_t len) { return writemem(dev_base, addr, mem, len, write_words, read_words); } static int goodfet_setregs(device_t dev_base, const address_t *regs) { (void)dev_base; (void)regs; printc_err("goodfet: register write not implemented\n"); return -1; } static int goodfet_getregs(device_t dev_base, address_t *regs) { (void)dev_base; (void)regs; printc_err("goodfet: register read not implemented\n"); return -1; } static int goodfet_reset(struct goodfet *gc) { static const uint8_t cmd_seq[] = { JTAG430_RELEASECPU, GLOBAL_STOP, GLOBAL_START, JTAG430_HALTCPU }; int i; /* We don't have a POR request, so just restart JTAG */ for (i = 0; i < 4; i++) { struct packet pkt; if (xfer(gc->serial_fd, APP_JTAG430, cmd_seq[i], 0, NULL, &pkt) < 0) { printc_err("goodfet: reset: command 0x%02x failed\n", cmd_seq[i]); return -1; } } return 0; } static int goodfet_run(struct goodfet *gc) { struct packet pkt; if (xfer(gc->serial_fd, APP_JTAG430, JTAG430_RELEASECPU, 0, NULL, &pkt) < 0) { printc_err("goodfet: failed to release CPU\n"); return -1; } return 0; } static int goodfet_halt(struct goodfet *gc) { struct packet pkt; if (xfer(gc->serial_fd, APP_JTAG430, JTAG430_HALTCPU, 0, NULL, &pkt) < 0) { printc_err("goodfet: failed to release CPU\n"); return -1; } return 0; } static int goodfet_ctl(device_t dev_base, device_ctl_t type) { struct goodfet *gc = (struct goodfet *)dev_base; switch (type) { case DEVICE_CTL_RESET: return goodfet_reset(gc); case DEVICE_CTL_RUN: return goodfet_run(gc); case DEVICE_CTL_HALT: return goodfet_halt(gc); default: printc_err("goodfet: unsupported operation\n"); return -1; } return 0; } static device_status_t goodfet_poll(device_t dev_base) { (void)dev_base; if (delay_ms(100) < 0) return DEVICE_STATUS_INTR; return DEVICE_STATUS_RUNNING; } static int goodfet_erase(device_t dev_base, device_erase_type_t type, address_t addr) { struct goodfet *gc = (struct goodfet *)dev_base; struct packet pkt; if (type != DEVICE_ERASE_MAIN) { printc_err("goodfet: only main memory erase is supported\n"); return -1; } if (xfer(gc->serial_fd, APP_JTAG430, JTAG430_ERASEFLASH, 0, NULL, &pkt) < 0) { printc_err("goodfet: erase failed\n"); return -1; } return 0; } static device_t goodfet_open(const struct device_args *args) { struct goodfet *gc; if (!(args->flags & DEVICE_FLAG_TTY)) { printc_err("goodfet: this driver does not support raw " "USB access\n"); return NULL; } if (!(args->flags & DEVICE_FLAG_JTAG)) { printc_err("goodfet: this driver does not support " "Spy-Bi-Wire\n"); return NULL; } gc = malloc(sizeof(*gc)); if (!gc) { printc_err("goodfet: malloc: %s\n", last_error()); return NULL; } memset(gc, 0, sizeof(*gc)); gc->base.type = &device_goodfet; gc->base.max_breakpoints = 0; gc->base.need_probe = 1; gc->serial_fd = sport_open(args->path, 115200, 0); if (SPORT_ISERR(gc->serial_fd)) { printc_err("goodfet: sport_open: %s: %s\n", args->path, last_error()); free(gc); return NULL; } if ((args->flags & DEVICE_FLAG_FORCE_RESET) && reset_sequence(gc->serial_fd) < 0) printc_err("warning: goodfet: reset failed\n"); if (sport_flush(gc->serial_fd) < 0) printc_err("warning: goodfet: sport_flush: %s\n", last_error()); if (init_device(gc->serial_fd) < 0) { printc_err("goodfet: initialization failed\n"); free(gc); return NULL; } return &gc->base; } static void goodfet_destroy(device_t dev_base) { struct goodfet *gc = (struct goodfet *)dev_base; struct packet pkt; xfer(gc->serial_fd, APP_JTAG430, JTAG430_RELEASECPU, 0, NULL, &pkt); xfer(gc->serial_fd, APP_JTAG430, GLOBAL_STOP, 0, NULL, &pkt); sport_close(gc->serial_fd); free(gc); } const struct device_class device_goodfet = { .name = "goodfet", .help = "GoodFET MSP430 JTAG", .open = goodfet_open, .destroy = goodfet_destroy, .readmem = goodfet_readmem, .writemem = goodfet_writemem, .getregs = goodfet_getregs, .setregs = goodfet_setregs, .ctl = goodfet_ctl, .poll = goodfet_poll, .erase = goodfet_erase, .getconfigfuses = NULL }; mspdebug-0.25/drivers/goodfet.h000066400000000000000000000016701313531517500165340ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef GOODFET_H_ #define GOODFET_H_ #include "device.h" /* GoodFET implementation */ extern const struct device_class device_goodfet; #endif mspdebug-0.25/drivers/hal_proto.c000066400000000000000000000100601313531517500170600ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2013 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include "util.h" #include "output.h" #include "hal_proto.h" void hal_proto_init(struct hal_proto *p, transport_t trans, hal_proto_flags_t flags) { memset(p, 0, sizeof(*p)); p->trans = trans; p->flags = flags; p->ref_id = 0; } int hal_proto_send(struct hal_proto *p, hal_proto_type_t type, const uint8_t *data, int length) { uint8_t buf[512]; size_t len = 0; if (length > HAL_MAX_PAYLOAD) { printc_err("hal_proto_send: payload too long: %d\n", length); return -1; } buf[len++] = length + 3; buf[len++] = type; buf[len++] = p->ref_id; buf[len++] = 0; p->ref_id = (p->ref_id + 1) & 0x7f; memcpy(buf + len, data, length); len += length; if (len & 1) buf[len++] = 0; if (p->flags & HAL_PROTO_CHECKSUM) { size_t i; uint8_t sum_l = 0xff; uint8_t sum_h = 0xff; for (i = 0; i < len; i += 2) { sum_l ^= buf[i]; sum_h ^= buf[i + 1]; } buf[len++] = sum_l; buf[len++] = sum_h; } if (p->trans->ops->send(p->trans, buf, len) < 0) { printc_err("hal_proto_send: type: 0x%02x\n", type); return -1; } return 0; } int hal_proto_receive(struct hal_proto *p, uint8_t *buf, int max_len) { uint8_t rx_buf[512]; uint8_t sum_h = 0xff; uint8_t sum_l = 0xff; int rx_len = 0; int len; int i; for (;;) { int r = p->trans->ops->recv(p->trans, rx_buf + rx_len, sizeof(rx_buf) - rx_len); if (r <= 0) { printc_err("hal_proto_recv: read error\n"); return -1; } rx_len += r; if (rx_len) { const size_t expect_len = rx_buf[0] + 4 - (rx_buf[0] & 1); if (rx_len == expect_len) break; if (rx_len > expect_len) { printc_err("hal_proto_recv: length " "mismatch\n"); return -1; } } } if (rx_len < 6) { printc_err("hal_proto_recv: short read: %d\n", rx_len); return -1; } for (i = 0; i < rx_len; i += 2) { sum_h ^= rx_buf[i]; sum_l ^= rx_buf[i + 1]; } if (sum_h || sum_l) { printc_err("hal_proto_recv: bad checksum\n"); return -1; } len = rx_buf[0] - 3; p->type = rx_buf[1]; p->ref = rx_buf[2]; p->seq = rx_buf[3]; if (len > max_len) { printc_err("hal_proto_recv: reply too long\n"); return -1; } memcpy(buf, rx_buf + 4, len); return len; } int hal_proto_execute(struct hal_proto *p, uint8_t fid, const uint8_t *data, int len) { uint8_t fdata[HAL_MAX_PAYLOAD]; if (len + 2 > HAL_MAX_PAYLOAD) { printc_err("hal_proto_execute: payload too big: %d\n", len); return -1; } fdata[0] = fid; fdata[1] = 0; memcpy(fdata + 2, data, len); if (hal_proto_send(p, HAL_PROTO_TYPE_CMD_EXECUTE, fdata, len + 2) < 0) goto fail; p->length = 0; do { int r = hal_proto_receive(p, p->payload + p->length, sizeof(p->payload) - p->length); if (r < 0) goto fail; if ((p->type == HAL_PROTO_TYPE_EXCEPTION) && (r >= 2)) { printc_err("hal_proto_execute: HAL exception: 0x%04x\n", LE_WORD(p->payload, p->length)); goto fail; } if (p->type == HAL_PROTO_TYPE_ACKNOWLEDGE) break; if (p->type != HAL_PROTO_TYPE_DATA) { printc_err("hal_proto_execute: no data " "(got type 0x%02x)\n", p->type); goto fail; } if (hal_proto_send(p, HAL_PROTO_TYPE_ACKNOWLEDGE, NULL, 0) < 0) goto fail; p->length += r; } while (p->ref & 0x80); return 0; fail: printc_err("hal_proto_execute: fid: 0x%02x\n", fid); return -1; } mspdebug-0.25/drivers/hal_proto.h000066400000000000000000000060241313531517500170720ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2013 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef HAL_PROTO_H_ #define HAL_PROTO_H_ #include #include #include "transport.h" /* Low-level HAL message types */ typedef enum { HAL_PROTO_TYPE_UP_INIT = 0x51, HAL_PROTO_TYPE_UP_ERASE = 0x52, HAL_PROTO_TYPE_UP_WRITE = 0x53, HAL_PROTO_TYPE_UP_READ = 0x54, HAL_PROTO_TYPE_UP_CORE = 0x55, HAL_PROTO_TYPE_DCDC_CALIBRATE = 0x56, HAL_PROTO_TYPE_DCDC_INIT_INTERFACE = 0x57, HAL_PROTO_TYPE_DCDC_SUB_MCU_VERSION = 0x58, HAL_PROTO_TYPE_DCDC_LAYER_VERSION = 0x59, HAL_PROTO_TYPE_DCDC_POWER_DOWN = 0x60, HAL_PROTO_TYPE_DCDC_SET_VCC = 0x61, HAL_PROTO_TYPE_DCDC_RESTART = 0x62, HAL_PROTO_TYPE_CMD_LEGACY = 0x7e, HAL_PROTO_TYPE_CMD_SYNC = 0x80, HAL_PROTO_TYPE_CMD_EXECUTE = 0x81, HAL_PROTO_TYPE_CMD_EXECUTE_LOOP = 0x82, HAL_PROTO_TYPE_CMD_LOAD = 0x83, HAL_PROTO_TYPE_CMD_LOAD_CONTINUED = 0x84, HAL_PROTO_TYPE_CMD_DATA = 0x85, HAL_PROTO_TYPE_CMD_KILL = 0x86, HAL_PROTO_TYPE_CMD_MOVE = 0x87, HAL_PROTO_TYPE_CMD_UNLOAD = 0x88, HAL_PROTO_TYPE_CMD_BYPASS = 0x89, HAL_PROTO_TYPE_CMD_EXECUTE_LOOP_CONT = 0x8a, HAL_PROTO_TYPE_CMD_COM_RESET = 0x8b, HAL_PROTO_TYPE_CMD_PAUSE_LOOP = 0x8c, HAL_PROTO_TYPE_CMD_RESUME_LOOP = 0x8d, HAL_PROTO_TYPE_ACKNOWLEDGE = 0x91, HAL_PROTO_TYPE_EXCEPTION = 0x92, HAL_PROTO_TYPE_DATA = 0x93, HAL_PROTO_TYPE_DATA_REQUEST = 0x94, HAL_PROTO_TYPE_STATUS = 0x95 } hal_proto_type_t; typedef enum { HAL_PROTO_CHECKSUM = 0x01 } hal_proto_flags_t; #define HAL_MAX_PAYLOAD 253 struct hal_proto { transport_t trans; hal_proto_flags_t flags; uint8_t ref_id; /* Receive parameters */ hal_proto_type_t type; uint8_t ref; uint8_t seq; /* Execute data */ int length; uint8_t payload[4096]; }; /* Initialize a HAL protocol interpreter */ void hal_proto_init(struct hal_proto *p, transport_t trans, hal_proto_flags_t flags); /* Send a low-level HAL command */ int hal_proto_send(struct hal_proto *p, hal_proto_type_t type, const uint8_t *data, int length); /* Receive a low-level HAL response */ int hal_proto_receive(struct hal_proto *p, uint8_t *buf, int max_len); /* Execute a high-level function. The reply data is kept in the payload * buffer. */ int hal_proto_execute(struct hal_proto *p, uint8_t fid, const uint8_t *data, int len); #endif mspdebug-0.25/drivers/jtaglib.c000066400000000000000000000706421313531517500165210ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * Copyright (C) 2012-2015 Peter Bägel * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ /* jtag functions are taken from TIs SLAA149–September 2002 * * breakpoint implementation influenced by a posting of Ruisheng Lin * to Travis Goodspeed at 2012-09-20 found at: * http://sourceforge.net/p/goodfet/mailman/message/29860790/ * * 2012-10-03 Peter Bägel (DF5EQ) * 2012-10-03 initial release Peter Bägel (DF5EQ) * 2014-12-26 jtag_single_step added Peter Bägel (DF5EQ) * jtag_read_reg corrected * jtag_write_reg corrected * 2015-02-21 jtag_set_breakpoint added Peter Bägel (DF5EQ) * jtag_cpu_state added */ #include #include "jtaglib.h" #include "output.h" #include "eem_defs.h" /* JTAG identification value for all existing Flash-based MSP430 devices */ #define JTAG_ID 0x89 /* Instructions for the JTAG control signal register in reverse bit order */ #define IR_CNTRL_SIG_16BIT 0xC8 /* 0x13 */ #define IR_CNTRL_SIG_CAPTURE 0x28 /* 0x14 */ #define IR_CNTRL_SIG_RELEASE 0xA8 /* 0x15 */ /* Instructions for the JTAG data register */ #define IR_DATA_16BIT 0x82 /* 0x41 */ #define IR_DATA_CAPTURE 0x42 /* 0x42 */ #define IR_DATA_QUICK 0xC2 /* 0x43 */ /* Instructions for the JTAG address register */ #define IR_ADDR_16BIT 0xC1 /* 0x83 */ #define IR_ADDR_CAPTURE 0x21 /* 0x84 */ #define IR_DATA_TO_ADDR 0xA1 /* 0x85 */ /* Instructions for the JTAG PSA mode */ #define IR_DATA_PSA 0x22 /* 0x44 */ #define IR_SHIFT_OUT_PSA 0x62 /* 0x46 */ /* Instructions for the JTAG Fuse */ #define IR_PREPARE_BLOW 0x44 /* 0x22 */ #define IR_EX_BLOW 0x24 /* 0x24 */ /* Instructions for the Configuration Fuse */ #define IR_CONFIG_FUSES 0x94 /* Bypass instruction */ #define IR_BYPASS 0xFF /* 0xFF */ /* Instructions for the EEM */ #define IR_EMEX_DATA_EXCHANGE 0x90 /* 0x09 */ #define IR_EMEX_WRITE_CONTROL 0x30 /* 0x0C */ #define IR_EMEX_READ_CONTROL 0xD0 /* 0x0B */ #define jtag_tms_set(p) p->f->jtdev_tms(p, 1) #define jtag_tms_clr(p) p->f->jtdev_tms(p, 0) #define jtag_tck_set(p) p->f->jtdev_tck(p, 1) #define jtag_tck_clr(p) p->f->jtdev_tck(p, 0) #define jtag_tdi_set(p) p->f->jtdev_tdi(p, 1) #define jtag_tdi_clr(p) p->f->jtdev_tdi(p, 0) #define jtag_tclk_set(p) p->f->jtdev_tclk(p, 1) #define jtag_tclk_clr(p) p->f->jtdev_tclk(p, 0) #define jtag_rst_set(p) p->f->jtdev_rst(p, 1) #define jtag_rst_clr(p) p->f->jtdev_rst(p, 0) #define jtag_tst_set(p) p->f->jtdev_tst(p, 1) #define jtag_tst_clr(p) p->f->jtdev_tst(p, 0) #define jtag_led_green_on(p) p->f->jtdev_led_green(p, 1) #define jtag_led_green_off(p) p->f->jtdev_led_green(p, 0) #define jtag_led_red_on(p) p->f->jtdev_led_red(p, 1) #define jtag_led_red_off(p) p->f->jtdev_led_red(p, 0) /* Reset target JTAG interface and perform fuse-HW check */ static void jtag_reset_tap(struct jtdev *p) { int loop_counter; jtag_tms_set(p); jtag_tck_set(p); /* Perform fuse check */ jtag_tms_clr(p); jtag_tms_set(p); jtag_tms_clr(p); jtag_tms_set(p); /* Reset JTAG state machine */ for (loop_counter = 6; loop_counter > 0; loop_counter--) { jtag_tck_clr(p); jtag_tck_set(p); if (p->failed) return; } /* Set JTAG state machine to Run-Test/IDLE */ jtag_tck_clr(p); jtag_tms_clr(p); jtag_tck_set(p); } /* This function sets the target JTAG state machine * back into the Run-Test/Idle state after a shift access */ static void jtag_tclk_prep (struct jtdev *p) { /* JTAG state = Exit-DR */ jtag_tck_clr(p); jtag_tck_set(p); /* JTAG state = Update-DR */ jtag_tms_clr(p); jtag_tck_clr(p); jtag_tck_set(p); /* JTAG state = Run-Test/Idle */ } /* Shift a value into TDI (MSB first) and simultaneously * shift out a value from TDO (MSB first) * num_bits: number of bits to shift * data_out: data to be shifted out * return : scanned TDO value */ static unsigned int jtag_shift( struct jtdev *p, unsigned char num_bits, unsigned int data_out ) { unsigned int data_in; unsigned int mask; unsigned int tclk_save; tclk_save = p->f->jtdev_tclk_get(p); data_in = 0; for (mask = 0x0001U << (num_bits - 1); mask != 0; mask >>= 1) { if ((data_out & mask) != 0) jtag_tdi_set(p); else jtag_tdi_clr(p); if (mask == 1) jtag_tms_set(p); jtag_tck_clr(p); jtag_tck_set(p); if (p->f->jtdev_tdo_get(p) == 1) data_in |= mask; } p->f->jtdev_tclk(p, tclk_save); /* Set JTAG state back to Run-Test/Idle */ jtag_tclk_prep(p); return data_in; } /* Shifts a new instruction into the JTAG instruction register through TDI * MSB first, with interchanged MSB/LSB, to use the shifting function * instruction: 8 bit instruction * return : scanned TDO value */ static unsigned int jtag_ir_shift(struct jtdev *p, unsigned int instruction) { /* JTAG state = Run-Test/Idle */ jtag_tms_set(p); jtag_tck_clr(p); jtag_tck_set(p); /* JTAG state = Select DR-Scan */ jtag_tck_clr(p); jtag_tck_set(p); /* JTAG state = Select IR-Scan */ jtag_tms_clr(p); jtag_tck_clr(p); jtag_tck_set(p); /* JTAG state = Capture-IR */ jtag_tck_clr(p); jtag_tck_set(p); /* JTAG state = Shift-IR, Shift in TDI (8-bit) */ return jtag_shift(p, 8, instruction); /* JTAG state = Run-Test/Idle */ } /* Shifts a given 8-bit byte into the JTAG data register through TDI. * data : 8 bit data * return: scanned TDO value */ static unsigned int jtag_dr_shift_8(struct jtdev *p, unsigned int data) { /* JTAG state = Run-Test/Idle */ jtag_tms_set(p); jtag_tck_clr(p); jtag_tck_set(p); /* JTAG state = Select DR-Scan */ jtag_tms_clr(p); jtag_tck_clr(p); jtag_tck_set(p); /* JTAG state = Capture-DR */ jtag_tck_clr(p); jtag_tck_set(p); /* JTAG state = Shift-DR, Shift in TDI (16-bit) */ return jtag_shift(p, 8, data); /* JTAG state = Run-Test/Idle */ } /* Shifts a given 16-bit word into the JTAG data register through TDI. * data : 16 bit data * return: scanned TDO value */ static unsigned int jtag_dr_shift_16(struct jtdev *p, unsigned int data) { /* JTAG state = Run-Test/Idle */ jtag_tms_set(p); jtag_tck_clr(p); jtag_tck_set(p); /* JTAG state = Select DR-Scan */ jtag_tms_clr(p); jtag_tck_clr(p); jtag_tck_set(p); /* JTAG state = Capture-DR */ jtag_tck_clr(p); jtag_tck_set(p); /* JTAG state = Shift-DR, Shift in TDI (16-bit) */ return jtag_shift(p, 16, data); /* JTAG state = Run-Test/Idle */ } /* Set target CPU JTAG state machine into the instruction fetch state * return: 1 - instruction fetch was set * 0 - otherwise */ static int jtag_set_instruction_fetch(struct jtdev *p) { unsigned int loop_counter; jtag_ir_shift(p, IR_CNTRL_SIG_CAPTURE); /* Wait until CPU is in instruction fetch state * timeout after limited attempts */ for (loop_counter = 50; loop_counter > 0; loop_counter--) { if ((jtag_dr_shift_16(p, 0x0000) & 0x0080) == 0x0080) return 1; jtag_tclk_clr(p); /* The TCLK pulse befor jtag_dr_shift_16 leads to */ jtag_tclk_set(p); /* problems at MEM_QUICK_READ, it's from SLAU265 */ } printc_err("jtag_set_instruction_fetch: failed\n"); p->failed = 1; return 0; } /* Set the CPU into a controlled stop state */ static void jtag_halt_cpu(struct jtdev *p) { /* Set CPU into instruction fetch mode */ jtag_set_instruction_fetch(p); /* Set device into JTAG mode + read */ jtag_ir_shift(p, IR_CNTRL_SIG_16BIT); jtag_dr_shift_16(p, 0x2401); /* Send JMP $ instruction to keep CPU from changing the state */ jtag_ir_shift(p, IR_DATA_16BIT); jtag_dr_shift_16(p, 0x3FFF); jtag_tclk_set(p); jtag_tclk_clr(p); /* Set JTAG_HALT bit */ jtag_ir_shift(p, IR_CNTRL_SIG_16BIT); jtag_dr_shift_16(p, 0x2409); jtag_tclk_set(p); } /* Release the target CPU from the controlled stop state */ static void jtag_release_cpu(struct jtdev *p) { jtag_tclk_clr(p); /* clear the HALT_JTAG bit */ jtag_ir_shift(p, IR_CNTRL_SIG_16BIT); jtag_dr_shift_16(p, 0x2401); jtag_ir_shift(p, IR_ADDR_CAPTURE); jtag_tclk_set(p); } /* Compares the computed PSA (Pseudo Signature Analysis) value to the PSA * value shifted out from the target device. It is used for very fast data * block write or erasure verification. * start_address: start of data * length : number of data * data : pointer to data, 0 for erase check * RETURN : 1 - comparison was successful * 0 - otherwise */ static int jtag_verify_psa(struct jtdev *p, unsigned int start_address, unsigned int length, const uint16_t *data) { unsigned int psa_value; unsigned int index; /* Polynom value for PSA calculation */ unsigned int polynom = 0x0805; /* Start value for PSA calculation */ unsigned int psa_crc = start_address-2; jtag_execute_puc(p); jtag_ir_shift(p, IR_CNTRL_SIG_16BIT); jtag_dr_shift_16(p, 0x2401); jtag_set_instruction_fetch(p); jtag_ir_shift(p, IR_DATA_16BIT); jtag_dr_shift_16(p, 0x4030); jtag_tclk_set(p); jtag_tclk_clr(p); jtag_dr_shift_16(p, start_address-2); jtag_tclk_set(p); jtag_tclk_clr(p); jtag_tclk_set(p); jtag_tclk_clr(p); jtag_tclk_set(p); jtag_tclk_clr(p); jtag_ir_shift(p, IR_ADDR_CAPTURE); jtag_dr_shift_16(p, 0x0000); jtag_ir_shift(p, IR_DATA_PSA); for (index = 0; index < length; index++) { /* Calculate the PSA value */ if ((psa_crc & 0x8000) == 0x8000) { psa_crc ^= polynom; psa_crc <<= 1; psa_crc |= 0x0001; } else psa_crc <<= 1; if (data == 0) /* use erase check mask */ psa_crc ^= 0xFFFF; else /* use data */ psa_crc ^= data[index]; /* Clock through the PSA */ jtag_tclk_set(p); jtag_tck_clr(p); jtag_tms_set(p); jtag_tck_set(p); /* Select DR scan */ jtag_tck_clr(p); jtag_tms_clr(p); jtag_tck_set(p); /* Capture DR */ jtag_tck_clr(p); jtag_tck_set(p); /* Shift DR */ jtag_tck_clr(p); jtag_tms_set(p); jtag_tck_set(p); /* Exit DR */ jtag_tck_clr(p); jtag_tck_set(p); jtag_tms_clr(p); jtag_tck_clr(p); jtag_tck_set(p); jtag_tclk_clr(p); } /* Read out the PSA value */ jtag_ir_shift(p, IR_SHIFT_OUT_PSA); psa_value = jtag_dr_shift_16(p, 0x0000); jtag_tclk_set(p); return (psa_value == psa_crc) ? 1 : 0; } /* Take target device under JTAG control. * Disable the target watchdog. * return: 0 - fuse is blown * >0 - jtag id */ unsigned int jtag_init(struct jtdev *p) { unsigned int jtag_id; jtag_rst_clr(p); p->f->jtdev_power_on(p); jtag_tdi_set(p); jtag_tms_set(p); jtag_tck_set(p); jtag_tclk_set(p); jtag_rst_set(p); jtag_tst_clr(p); jtag_tst_set(p); jtag_rst_clr(p); jtag_tst_clr(p); jtag_tst_set(p); p->f->jtdev_connect(p); jtag_rst_set(p); jtag_reset_tap(p); /* Check fuse */ if (jtag_is_fuse_blown(p)) { printc_err("jtag_init: fuse is blown\n"); p->failed = 1; return 0; } /* Set device into JTAG mode */ jtag_id = jtag_get_device(p); if (jtag_id == 0) { printc_err("jtag_init: invalid jtag_id: 0x%02x\n", jtag_id); p->failed = 1; return 0; } /* Perform PUC, includes target watchdog disable */ if (jtag_execute_puc(p) != jtag_id) { printc_err("jtag_init: PUC failed\n"); p->failed = 1; return 0; } return jtag_id; } unsigned int jtag_get_device(struct jtdev *p) { unsigned int jtag_id = 0; unsigned int loop_counter; /* Set device into JTAG mode + read */ jtag_ir_shift(p, IR_CNTRL_SIG_16BIT); jtag_dr_shift_16(p, 0x2401); /* Wait until CPU is synchronized, * timeout after a limited number of attempts */ jtag_id = jtag_ir_shift(p, IR_CNTRL_SIG_CAPTURE); for ( loop_counter = 50; loop_counter > 0; loop_counter--) { if ( (jtag_dr_shift_16(p, 0x0000) & 0x0200) == 0x0200 ) { break; } } if (loop_counter == 0) { printc_err("jtag_get_device: timed out\n"); p->failed = 1; /* timeout reached */ return 0; } jtag_led_green_on(p); return jtag_id; } /* Read the target chip id. * return: chip id */ unsigned int jtag_chip_id(struct jtdev *p) { unsigned short chip_id; /* Read id from address 0x0ff0 */ chip_id = jtag_read_mem(p, 16, 0x0FF0); /* High / low byte are stored in reverse order */ chip_id = (chip_id << 8) + (chip_id >> 8); return chip_id; } /* Reads one byte/word from a given address * format : 8-byte, 16-word * address: address of memory * return : content of memory */ uint16_t jtag_read_mem(struct jtdev *p, unsigned int format, address_t address) { uint16_t content; jtag_halt_cpu(p); jtag_tclk_clr(p); jtag_ir_shift(p, IR_CNTRL_SIG_16BIT); if (format == 16) { /* set word read */ jtag_dr_shift_16(p, 0x2409); } else { /* set byte read */ jtag_dr_shift_16(p, 0x2419); } /* set address */ jtag_ir_shift(p, IR_ADDR_16BIT); jtag_dr_shift_16(p, address); jtag_ir_shift(p, IR_DATA_TO_ADDR); jtag_tclk_set(p); jtag_tclk_clr(p); /* shift out 16 bits */ content = jtag_dr_shift_16(p, 0x0000); jtag_tclk_set(p); /* is also the first instruction in jtag_release_cpu() */ jtag_release_cpu(p); if (format == 8) content &= 0x00ff; return content; } /* Reads an array of words from target memory * address: address to read from * length : number of word to read * data : memory to write to */ void jtag_read_mem_quick(struct jtdev *p, address_t address, unsigned int length, uint16_t *data) { unsigned int index; /* Initialize reading: */ jtag_write_reg(p, 0,address-4); jtag_halt_cpu(p); jtag_tclk_clr(p); /* set RW to read */ jtag_ir_shift(p, IR_CNTRL_SIG_16BIT); jtag_dr_shift_16(p, 0x2409); jtag_ir_shift(p, IR_DATA_QUICK); for (index = 0; index < length; index++) { jtag_tclk_set(p); jtag_tclk_clr(p); /* shift out the data from the target */ data[index] = jtag_dr_shift_16(p, 0x0000); } jtag_tclk_set(p); jtag_release_cpu(p); } /* Writes one byte/word at a given address * format : 8-byte, 16-word * address: address to be written * data : data to write */ void jtag_write_mem(struct jtdev *p, unsigned int format, address_t address, uint16_t data) { jtag_halt_cpu(p); jtag_tclk_clr(p); jtag_ir_shift(p, IR_CNTRL_SIG_16BIT); if (format == 16) /* Set word write */ jtag_dr_shift_16(p, 0x2408); else /* Set byte write */ jtag_dr_shift_16(p, 0x2418); jtag_ir_shift(p, IR_ADDR_16BIT); /* Set addr */ jtag_dr_shift_16(p, address); jtag_ir_shift(p, IR_DATA_TO_ADDR); /* Shift in 16 bits */ jtag_dr_shift_16(p, data); jtag_tclk_set(p); jtag_release_cpu(p); } /* Writes an array of words into target memory * address: address to write to * length : number of word to write * data : data to write */ void jtag_write_mem_quick(struct jtdev *p, address_t address, unsigned int length, const uint16_t *data) { unsigned int index; /* Initialize writing */ jtag_write_reg(p, 0, address-4); jtag_halt_cpu(p); jtag_tclk_clr(p); jtag_ir_shift(p, IR_CNTRL_SIG_16BIT); /* Set RW to write */ jtag_dr_shift_16(p, 0x2408); jtag_ir_shift(p, IR_DATA_QUICK); for (index = 0; index < length; index++) { /* Write data */ jtag_dr_shift_16(p, data[index]); /* Increment PC by 2 */ jtag_tclk_set(p); jtag_tclk_clr(p); } jtag_tclk_set(p); jtag_release_cpu(p); } /* This function checks if the JTAG access security fuse is blown * return: 1 - fuse is blown * 0 - otherwise */ int jtag_is_fuse_blown (struct jtdev *p) { unsigned int loop_counter; /* First trial could be wrong */ for (loop_counter = 3; loop_counter > 0; loop_counter--) { jtag_ir_shift(p, IR_CNTRL_SIG_CAPTURE); if (jtag_dr_shift_16(p, 0xAAAA) == 0x5555) /* Fuse is blown */ return 1; } /* Fuse is not blown */ return 0; } /* Execute a Power-Up Clear (PUC) using JTAG CNTRL SIG register * return: JTAG ID */ unsigned int jtag_execute_puc(struct jtdev *p) { unsigned int jtag_id; jtag_ir_shift(p, IR_CNTRL_SIG_16BIT); /* Apply and remove reset */ jtag_dr_shift_16(p, 0x2C01); jtag_dr_shift_16(p, 0x2401); jtag_tclk_clr(p); jtag_tclk_set(p); jtag_tclk_clr(p); jtag_tclk_set(p); jtag_tclk_clr(p); jtag_tclk_set(p); /* Read jtag id */ jtag_id = jtag_ir_shift(p, IR_ADDR_CAPTURE); /* Disable watchdog on target device */ jtag_write_mem(p, 16, 0x0120, 0x5A80); return jtag_id; } /* Release the target device from JTAG control * address: 0xFFFE - perform Reset, * load Reset Vector into PC * 0xFFFF - start execution at current * PC position * other - load Address into PC */ void jtag_release_device(struct jtdev *p, address_t address) { jtag_led_green_off(p); switch (address) { case 0xffff: /* Nothing to do */ break; case 0xfffe: /* Perform reset */ /* delete all breakpoints */ jtag_set_breakpoint(p,-1,0); /* issue reset */ jtag_ir_shift(p, IR_CNTRL_SIG_16BIT); jtag_dr_shift_16(p, 0x2C01); jtag_dr_shift_16(p, 0x2401); break; default: /* Set target CPU's PC */ jtag_write_reg(p, 0, address); break; } jtag_set_instruction_fetch(p); jtag_ir_shift(p, IR_EMEX_DATA_EXCHANGE); jtag_dr_shift_16(p, BREAKREACT + READ); jtag_dr_shift_16(p, 0x0000); jtag_ir_shift(p, IR_EMEX_WRITE_CONTROL); jtag_dr_shift_16(p, 0x000f); jtag_ir_shift(p, IR_CNTRL_SIG_RELEASE); } /* Performs a verification over the given memory range * return: 1 - verification was successful * 0 - otherwise */ int jtag_verify_mem(struct jtdev *p, address_t start_address, unsigned int length, const uint16_t *data) { return jtag_verify_psa(p, start_address, length, data); } /* Performs an erase check over the given memory range * return: 1 - erase check was successful * 0 - otherwise */ int jtag_erase_check(struct jtdev *p, address_t start_address, unsigned int length) { return jtag_verify_psa(p, start_address, length, NULL); } /* Programs/verifies an array of words into a FLASH by using the * FLASH controller. The JTAG FLASH register isn't needed. * start_address: start in FLASH * length : number of words * data : pointer to data */ void jtag_write_flash(struct jtdev *p, address_t start_address, unsigned int length, const uint16_t *data) { unsigned int index; unsigned int address; jtag_led_red_on(p); address = start_address; jtag_halt_cpu(p); jtag_tclk_clr(p); /* Set RW to write */ jtag_ir_shift(p, IR_CNTRL_SIG_16BIT); jtag_dr_shift_16(p, 0x2408); /* FCTL1 register */ jtag_ir_shift(p, IR_ADDR_16BIT); jtag_dr_shift_16(p, 0x0128); /* Enable FLASH write */ jtag_ir_shift(p, IR_DATA_TO_ADDR); jtag_dr_shift_16(p, 0xA540); jtag_tclk_set(p); jtag_tclk_clr(p); /* FCTL2 register */ jtag_ir_shift(p, IR_ADDR_16BIT); jtag_dr_shift_16(p, 0x012A); /* Select MCLK as source, DIV=1 */ jtag_ir_shift(p, IR_DATA_TO_ADDR); jtag_dr_shift_16(p, 0xA540); jtag_tclk_set(p); jtag_tclk_clr(p); /* FCTL3 register */ jtag_ir_shift(p, IR_ADDR_16BIT); jtag_dr_shift_16(p, 0x012C); /* Clear FCTL3 register */ jtag_ir_shift(p, IR_DATA_TO_ADDR); jtag_dr_shift_16(p, 0xA500); jtag_tclk_set(p); jtag_tclk_clr(p); for (index = 0; index < length; index++) { /* Set RW to write */ jtag_ir_shift(p, IR_CNTRL_SIG_16BIT); jtag_dr_shift_16(p, 0x2408); /* Set address */ jtag_ir_shift(p, IR_ADDR_16BIT); jtag_dr_shift_16(p, address); /* Set data */ jtag_ir_shift(p, IR_DATA_TO_ADDR); jtag_dr_shift_16(p, data[index]); jtag_tclk_set(p); jtag_tclk_clr(p); /* Set RW to read */ jtag_ir_shift(p, IR_CNTRL_SIG_16BIT); jtag_dr_shift_16(p, 0x2409); /* provide TCLKs * min. 33 for F149 and F449 */ p->f->jtdev_tclk_strobe(p, 35); address += 2; if (p->failed) break; } /* Set RW to write */ jtag_ir_shift(p, IR_CNTRL_SIG_16BIT); jtag_dr_shift_16(p, 0x2408); /* FCTL1 register */ jtag_ir_shift(p, IR_ADDR_16BIT); jtag_dr_shift_16(p, 0x0128); /* Disable FLASH write */ jtag_ir_shift(p, IR_DATA_TO_ADDR); jtag_dr_shift_16(p, 0xA500); jtag_tclk_set(p); jtag_release_cpu(p); jtag_led_red_off(p); } /* Performs a mass erase (with and w/o info memory) or a segment erase of a * FLASH module specified by the given mode and address. Large memory devices * get additional mass erase operations to meet the spec. * erase_mode : ERASE_MASS, ERASE_MAIN, ERASE_SGMT * erase_address: address within the selected segment */ void jtag_erase_flash(struct jtdev *p, unsigned int erase_mode, address_t erase_address) { unsigned int number_of_strobes = 4820; /* default for segment erase */ unsigned int loop_counter; unsigned int max_loop_count = 1; /* erase cycle repeating for mass erase */ jtag_led_red_on(p); if ((erase_mode == JTAG_ERASE_MASS) || (erase_mode == JTAG_ERASE_MAIN)) { number_of_strobes = 5300; /* Larger Flash memories require */ max_loop_count = 19; /* additional cycles for erase. */ erase_address = 0xfffe; /* overwrite given address */ } for (loop_counter = max_loop_count; loop_counter > 0; loop_counter--) { jtag_halt_cpu(p); jtag_tclk_clr(p); /* Set RW to write */ jtag_ir_shift(p, IR_CNTRL_SIG_16BIT); jtag_dr_shift_16(p, 0x2408); /* FCTL1 address */ jtag_ir_shift(p, IR_ADDR_16BIT); jtag_dr_shift_16(p, 0x0128); /* Enable erase mode */ jtag_ir_shift(p, IR_DATA_TO_ADDR); jtag_dr_shift_16(p, erase_mode); jtag_tclk_set(p); jtag_tclk_clr(p); /* FCTL2 address */ jtag_ir_shift(p, IR_ADDR_16BIT); jtag_dr_shift_16(p, 0x012A); /* MCLK is source, DIV=1 */ jtag_ir_shift(p, IR_DATA_TO_ADDR); jtag_dr_shift_16(p, 0xA540); jtag_tclk_set(p); jtag_tclk_clr(p); /* FCTL3 address */ jtag_ir_shift(p, IR_ADDR_16BIT); jtag_dr_shift_16(p, 0x012C); /* Clear FCTL3 */ jtag_ir_shift(p, IR_DATA_TO_ADDR); jtag_dr_shift_16(p, 0xA500); jtag_tclk_set(p); jtag_tclk_clr(p); /* Set erase address */ jtag_ir_shift(p, IR_ADDR_16BIT); jtag_dr_shift_16(p, erase_address); /* Dummy write to start erase */ jtag_ir_shift(p, IR_DATA_TO_ADDR); jtag_dr_shift_16(p, 0x55AA); jtag_tclk_set(p); jtag_tclk_clr(p); /* Set RW to read */ jtag_ir_shift(p, IR_CNTRL_SIG_16BIT); jtag_dr_shift_16(p, 0x2409); /* provide TCLKs */ p->f->jtdev_tclk_strobe(p, number_of_strobes); /* Set RW to write */ jtag_ir_shift(p, IR_CNTRL_SIG_16BIT); jtag_dr_shift_16(p, 0x2408); /* FCTL1 address */ jtag_ir_shift(p, IR_ADDR_16BIT); jtag_dr_shift_16(p, 0x0128); /* Disable erase */ jtag_ir_shift(p, IR_DATA_TO_ADDR); jtag_dr_shift_16(p, 0xA500); jtag_tclk_set(p); jtag_release_cpu(p); } jtag_led_red_off(p); } /* Reads a register from the target CPU */ address_t jtag_read_reg(struct jtdev *p, int reg) { unsigned int value; /* CPU controls RW & BYTE */ jtag_ir_shift(p, IR_CNTRL_SIG_16BIT); jtag_dr_shift_16(p, 0x3401); /* Set CPU into instruction fetch mode */ jtag_set_instruction_fetch(p); jtag_ir_shift(p, IR_DATA_16BIT); /* "jmp $-4" instruction */ /* PC - 4 -> PC */ /* needs 2 clock cycles */ jtag_dr_shift_16(p, 0x3ffd); jtag_tclk_set(p); jtag_tclk_clr(p); jtag_tclk_set(p); jtag_tclk_clr(p); /* "mov Rn,&0x01fe" instruction * Rn -> &0x01fe * PC is advanced 4 bytes by this instruction * needs 4 clock cycles * it's a ROM address, write has no effect, but * the registers value is placed on the databus */ jtag_dr_shift_16(p, 0x4082 | (((unsigned int)reg << 8) & 0x0f00) ); jtag_tclk_set(p); jtag_tclk_clr(p); jtag_dr_shift_16(p, 0x01fe); jtag_tclk_set(p); jtag_tclk_clr(p); jtag_tclk_set(p); jtag_tclk_clr(p); jtag_tclk_set(p); jtag_tclk_clr(p); /* Read databus which contains the registers value */ jtag_ir_shift(p, IR_DATA_CAPTURE); value = jtag_dr_shift_16(p, 0x0000); /* JTAG controls RW & BYTE */ jtag_ir_shift(p, IR_CNTRL_SIG_16BIT); jtag_dr_shift_16(p, 0x2401); jtag_tclk_set(p); /* Return value read from register */ return value; } /* Writes a value into a register of the target CPU */ void jtag_write_reg(struct jtdev *p, int reg, address_t value) { /* CPU controls RW & BYTE */ jtag_ir_shift(p, IR_CNTRL_SIG_16BIT); jtag_dr_shift_16(p, 0x3401); /* Set CPU into instruction fetch mode */ jtag_set_instruction_fetch(p); jtag_ir_shift(p, IR_DATA_16BIT); /* "jmp $-4" instruction */ /* PC - 4 -> PC */ /* needs 4 clock cycles */ jtag_dr_shift_16(p, 0x3ffd); jtag_tclk_set(p); jtag_tclk_clr(p); jtag_tclk_set(p); jtag_tclk_clr(p); /* "mov #value,Rn" instruction * value -> Rn * PC is advanced 4 bytes by this instruction * needs 2 clock cycles */ jtag_dr_shift_16(p, 0x4030 | (reg & 0x000f) ); jtag_tclk_set(p); jtag_tclk_clr(p); jtag_dr_shift_16(p, value); jtag_tclk_set(p); jtag_tclk_clr(p); /* JTAG controls RW & BYTE */ jtag_ir_shift(p, IR_CNTRL_SIG_16BIT); jtag_dr_shift_16(p, 0x2401); jtag_tclk_set(p); } /*----------------------------------------------------------------------------*/ void jtag_single_step( struct jtdev *p ) { unsigned int loop_counter; /* CPU controls RW & BYTE */ jtag_ir_shift(p, IR_CNTRL_SIG_16BIT); jtag_dr_shift_16(p, 0x3401); /* clock CPU until next instruction fetch cycle */ /* failure after 10 clock cycles */ /* this is more than for the longest instruction */ jtag_ir_shift(p, IR_CNTRL_SIG_CAPTURE); for (loop_counter = 10; loop_counter > 0; loop_counter--) { jtag_tclk_clr(p); jtag_tclk_set(p); if ((jtag_dr_shift_16(p, 0x0000) & 0x0080) == 0x0080) { break; } } /* JTAG controls RW & BYTE */ jtag_ir_shift(p, IR_CNTRL_SIG_16BIT); jtag_dr_shift_16(p, 0x2401); if (loop_counter == 0) { /* timeout reached */ printc_err("pif: single step failed\n"); p->failed = 1; } } /*----------------------------------------------------------------------------*/ unsigned int jtag_set_breakpoint( struct jtdev *p,int bp_num, address_t bp_addr ) { /* The breakpoint logic is explained in 'SLAU414c EEM.pdf' */ /* A good overview is given with Figure 1-1 */ /* MBx is TBx in EEM_defs.h */ /* CPU Stop is BREAKREACT in EEM_defs.h */ /* State Storage is STOR_REACT in EEM_defs.h */ /* Cycle Counter is EVENT_REACT in EEM_defs.h */ unsigned int breakreact; if (bp_num >= 8) { /* there are no more than 8 breakpoints in EEM */ printc_err("jtag_set_breakpoint: failed setting " "breakpoint %d at %04x\n", bp_num, bp_addr); p->failed = 1; return 0; } if (bp_num < 0) { /* disable all breakpoints by deleting the BREAKREACT * register */ jtag_ir_shift(p, IR_EMEX_DATA_EXCHANGE); jtag_dr_shift_16(p, BREAKREACT + WRITE); jtag_dr_shift_16(p, 0x0000); return 1; } /* set breakpoint */ jtag_ir_shift(p, IR_EMEX_DATA_EXCHANGE); jtag_dr_shift_16(p, GENCTRL + WRITE); jtag_dr_shift_16(p, EEM_EN + CLEAR_STOP + EMU_CLK_EN + EMU_FEAT_EN); jtag_ir_shift(p, IR_EMEX_DATA_EXCHANGE); //repeating may not needed jtag_dr_shift_16(p, 8*bp_num + MBTRIGxVAL + WRITE); jtag_dr_shift_16(p, bp_addr); jtag_ir_shift(p, IR_EMEX_DATA_EXCHANGE); //repeating may not needed jtag_dr_shift_16(p, 8*bp_num + MBTRIGxCTL + WRITE); jtag_dr_shift_16(p, MAB + TRIG_0 + CMP_EQUAL); jtag_ir_shift(p, IR_EMEX_DATA_EXCHANGE); //repeating may not needed jtag_dr_shift_16(p, 8*bp_num + MBTRIGxMSK + WRITE); jtag_dr_shift_16(p, NO_MASK); jtag_ir_shift(p, IR_EMEX_DATA_EXCHANGE); //repeating may not needed jtag_dr_shift_16(p, 8*bp_num + MBTRIGxCMB + WRITE); jtag_dr_shift_16(p, 1<> 1) | (1 << bp_num); jtag_dr_shift_16(p, BREAKREACT + WRITE); jtag_dr_shift_16(p, breakreact); return 1; } /*----------------------------------------------------------------------------*/ unsigned int jtag_cpu_state( struct jtdev *p ) { jtag_ir_shift(p, IR_EMEX_READ_CONTROL); if ((jtag_dr_shift_16(p, 0x0000) & 0x0080) == 0x0080) { return 1; /* halted */ } else { return 0; /* running */ } } /*----------------------------------------------------------------------------*/ int jtag_get_config_fuses( struct jtdev *p ) { jtag_ir_shift(p, IR_CONFIG_FUSES); return jtag_dr_shift_8(p, 0); } mspdebug-0.25/drivers/jtaglib.h000066400000000000000000000075511313531517500165250ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * Copyright (C) 2012-2015 Peter Bägel * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ /* jtag functions are taken from TIs SLAA149–September 2002 * * breakpoint implementation influenced by a posting of Ruisheng Lin * to Travis Goodspeed at 2012-09-20 found at: * http://sourceforge.net/p/goodfet/mailman/message/29860790/ * * * 2012-10-03 Peter Bägel (DF5EQ) * 2012-10-03 initial release Peter Bägel (DF5EQ) * 2014-12-26 jtag_single_step added Peter Bägel (DF5EQ) * 2015-02-21 jtag_set_breakpoint added Peter Bägel (DF5EQ) * jtag_cpu_state added */ #ifndef JTAGLIB_H_ #define JTAGLIB_H_ #include #include "jtdev.h" #include "util.h" /* Flash erasing modes */ #define JTAG_ERASE_MASS 0xA506 #define JTAG_ERASE_MAIN 0xA504 #define JTAG_ERASE_SGMT 0xA502 /* Take target device under JTAG control. */ unsigned int jtag_init(struct jtdev *p); unsigned int jtag_get_device(struct jtdev *p); /* Read the target chip id. */ unsigned int jtag_chip_id(struct jtdev *p); /* Reads one byte/word from a given address */ uint16_t jtag_read_mem(struct jtdev *p, unsigned int format, address_t address); /* Reads an array of words from target memory */ void jtag_read_mem_quick(struct jtdev *p, address_t start_address, unsigned int word_count, uint16_t *data); /* Writes one byte/word at a given address */ void jtag_write_mem(struct jtdev *p, unsigned int format, address_t address, uint16_t data); /* Writes an array of words into target memory */ void jtag_write_mem_quick(struct jtdev *p, address_t start_address, unsigned int word_count, const uint16_t *data); /* This function checks if the JTAG access security fuse is blown */ int jtag_is_fuse_blown(struct jtdev *p); /* Execute a Power-Up Clear (PUC) using JTAG CNTRL SIG register */ unsigned int jtag_execute_puc(struct jtdev *p); /* Release the target device from JTAG control */ void jtag_release_device(struct jtdev *p, address_t address); /* Performs a verification over the given memory range */ int jtag_verify_mem(struct jtdev *p, address_t start_address, unsigned int word_count, const uint16_t *data); /* Performs an erase check over the given memory range */ int jtag_erase_check(struct jtdev *p, address_t start_address, unsigned int word_count); /* Programs/verifies an array of words into a FLASH */ void jtag_write_flash(struct jtdev *p, address_t start_address, unsigned int word_count, const uint16_t *data); /* Performs a mass erase or a segment erase of a FLASH module */ void jtag_erase_flash(struct jtdev *p, unsigned int erase_mode, address_t erase_address); /* Reads a register from the target CPU */ address_t jtag_read_reg(struct jtdev *p, int reg); /* Writes a value into a register of the target CPU */ void jtag_write_reg(struct jtdev *p, int reg, address_t value); void jtag_single_step(struct jtdev *p); unsigned int jtag_set_breakpoint(struct jtdev *p, int bp_num, address_t bp_addr); unsigned int jtag_cpu_state(struct jtdev *p); int jtag_get_config_fuses(struct jtdev *p); #endif mspdebug-0.25/drivers/jtdev.c000066400000000000000000000204651313531517500162170ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * Copyright (C) 2012 Peter Bägel * * ppdev/ppi abstraction inspired by uisp src/DARPA.C * originally written by Sergey Larin; * corrected by Denis Chertykov, Uros Platise and Marek Michalkiewicz. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include "jtdev.h" #include "output.h" #if defined(__linux__) || \ ( defined(__FreeBSD__) || defined(__DragonFly__) ) /*===== includes =============================================================*/ #include #include #if defined(__linux__) #include #define par_claim(fd) ioctl(fd, PPCLAIM, NULL) #define par_write_data(fd, ptr) ioctl(fd, PPWDATA, ptr) #define par_write_control(fd, ptr) ioctl(fd, PPWCONTROL, ptr) #define par_release(fd) ioctl(fd, PPRELEASE, NULL) #define par_read_status(fd, ptr) ioctl(fd, PPRSTATUS, ptr) #elif defined(__FreeBSD__) || defined(__DragonFly__) #if defined(__FreeBSD__) #include #include #else /* __DragonFly__ */ #include #include #endif #define par_claim(fd) (0) #define par_write_data(fd, ptr) ioctl(fd, PPISDATA, ptr) #define par_write_control(fd, ptr) ioctl(fd, PPISCTRL, ptr) #define par_release(fd) (0) #define par_read_status(fd, ptr) ioctl(fd, PPIGSTATUS, ptr) #endif /* __linux__ || (__FreeBSD__ || __DragonFly__) */ #include #include "util.h" /*===== private symbols ======================================================*/ /*--- port data (out) ---*/ #define DATA0 ((unsigned char)0x01) #define DATA1 ((unsigned char)0x02) #define DATA2 ((unsigned char)0x04) #define DATA3 ((unsigned char)0x08) #define DATA4 ((unsigned char)0x10) #define DATA5 ((unsigned char)0x20) #define DATA6 ((unsigned char)0x40) #define DATA7 ((unsigned char)0x80) /*--- port status (in) ---*/ #define ERR ((unsigned char)0x08) #define SEL ((unsigned char)0x10) #define PE ((unsigned char)0x20) #define ACK ((unsigned char)0x40) #define BUSY ((unsigned char)0x80) /*--- port control (out) ---*/ #ifndef STROBE #define STROBE ((unsigned char)0x01) /* inverted by PC-hardware */ #endif #ifndef AUTOFEED #define AUTOFEED ((unsigned char)0x02) #endif #ifndef INIT #define INIT ((unsigned char)0x04) #endif #ifndef SELECTIN #define SELECTIN ((unsigned char)0x08) #endif #define IRQEN ((unsigned char)0x10) /*--- JTAG signal mapping ---*/ #define TEST INIT #define TDO PE #define TDI DATA0 #define TMS DATA1 #define TCK DATA2 #define XOUT DATA3 #define POWER (DATA4 | DATA7) #define RESET STROBE #define ENABLE (SELECTIN | AUTOFEED) #define LED_GREEN DATA5 #define LED_RED DATA6 #define TCLK TDI /*===== public functions =====================================================*/ static void do_ppwdata(struct jtdev *p) { if (par_write_data(p->port, &p->data_register) < 0) { pr_error("jtdev: par_write_data"); p->failed = 1; } } static void do_ppwcontrol(struct jtdev *p) { if (par_write_control(p->port, &p->control_register) < 0) { pr_error("jtdev: par_write_control"); p->failed = 1; } } static int jtpif_open(struct jtdev *p, const char *device) { p->port = open(device, O_RDWR); if (p->port < 0) { printc_err("jtdev: can't open %s: %s\n", device, last_error()); return -1; } if (par_claim(p->port) < 0) { printc_err("jtdev: par_claim: %s: %s\n", device, last_error()); close(p->port); return -1; } p->data_register = 0; p->control_register = 0; p->failed = 0; do_ppwdata(p); do_ppwcontrol(p); return 0; } static void jtpif_close(struct jtdev *p) { if (par_release(p->port) < 0) pr_error("warning: jtdev: failed to release port"); close(p->port); } static void jtpif_power_on(struct jtdev *p) { /* power supply on */ p->data_register |= POWER; do_ppwdata(p); } static void jtpif_power_off(struct jtdev *p) { /* power supply off */ p->data_register &= ~POWER; do_ppwdata(p); /* a high, inactive reset also powers the target */ /* reset pin is inverted by PC hardware */ p->control_register |= RESET; do_ppwcontrol(p); } static void jtpif_connect(struct jtdev *p) { p->control_register |= (TEST | ENABLE); do_ppwcontrol(p); } static void jtpif_release(struct jtdev *p) { p->control_register &= ~(TEST | ENABLE); do_ppwcontrol(p); } static void jtpif_tck(struct jtdev *p, int out) { if (out) p->data_register |= TCK; else p->data_register &= ~TCK; do_ppwdata(p); } static void jtpif_tms(struct jtdev *p, int out) { if (out) p->data_register |= TMS; else p->data_register &= ~TMS; do_ppwdata(p); } static void jtpif_tdi(struct jtdev *p, int out) { if (out) p->data_register |= TDI; else p->data_register &= ~TDI; do_ppwdata(p); } static void jtpif_rst(struct jtdev *p, int out) { /* reset pin is inverted by PC hardware */ if (out) p->control_register &= ~RESET; else p->control_register |= RESET; do_ppwcontrol(p); } static void jtpif_tst(struct jtdev *p, int out) { if (out) p->control_register |= TEST; else p->control_register &= ~TEST; do_ppwcontrol(p); } static int jtpif_tdo_get(struct jtdev *p) { uint8_t input; if (par_read_status(p->port, &input) < 0) { pr_error("jtdev: par_read_status:"); p->failed = 1; return 0; } return (input & TDO) ? 1 : 0; } static void jtpif_tclk(struct jtdev *p, int out) { if (out) p->data_register |= TCLK; else p->data_register &= ~TCLK; do_ppwdata(p); } static int jtpif_tclk_get(struct jtdev *p) { return (p->data_register & TCLK) ? 1 : 0; } static void jtpif_tclk_strobe(struct jtdev *p, unsigned int count) { int i; for (i = 0; i < count; i++) { jtpif_tclk(p, 1); jtpif_tclk(p, 0); if (p->failed) return; } } static void jtpif_led_green(struct jtdev *p, int out) { if (out) p->data_register |= LED_GREEN; else p->data_register &= ~LED_GREEN; do_ppwdata(p); } static void jtpif_led_red(struct jtdev *p, int out) { if (out) p->data_register |= LED_RED; else p->data_register &= ~LED_RED; do_ppwdata(p); } #else /* __linux__ */ static int jtpif_open(struct jtdev *p, const char *device) { printc_err("jtdev: driver is not supported on this platform\n"); p->failed = 1; return -1; } static void jtpif_close(struct jtdev *p) { } static void jtpif_power_on(struct jtdev *p) { } static void jtpif_power_off(struct jtdev *p) { } static void jtpif_connect(struct jtdev *p) { } static void jtpif_release(struct jtdev *p) { } static void jtpif_tck(struct jtdev *p, int out) { } static void jtpif_tms(struct jtdev *p, int out) { } static void jtpif_tdi(struct jtdev *p, int out) { } static void jtpif_rst(struct jtdev *p, int out) { } static void jtpif_tst(struct jtdev *p, int out) { } static int jtpif_tdo_get(struct jtdev *p) { return 0; } static void jtpif_tclk(struct jtdev *p, int out) { } static int jtpif_tclk_get(struct jtdev *p) { return 0; } static void jtpif_tclk_strobe(struct jtdev *p, unsigned int count) { } static void jtpif_led_green(struct jtdev *p, int out) { } static void jtpif_led_red(struct jtdev *p, int out) { } #endif const struct jtdev_func jtdev_func_pif = { .jtdev_open = jtpif_open, .jtdev_close = jtpif_close, .jtdev_power_on = jtpif_power_on, .jtdev_power_off = jtpif_power_off, .jtdev_connect = jtpif_connect, .jtdev_release = jtpif_release, .jtdev_tck = jtpif_tck, .jtdev_tms = jtpif_tms, .jtdev_tdi = jtpif_tdi, .jtdev_rst = jtpif_rst, .jtdev_tst = jtpif_tst, .jtdev_tdo_get = jtpif_tdo_get, .jtdev_tclk = jtpif_tclk, .jtdev_tclk_get = jtpif_tclk_get, .jtdev_tclk_strobe = jtpif_tclk_strobe, .jtdev_led_green = jtpif_led_green, .jtdev_led_red = jtpif_led_red }; mspdebug-0.25/drivers/jtdev.h000066400000000000000000000044241313531517500162210ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * Copyright (C) 2012 Peter Bägel * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef JTDEV_H_ #define JTDEV_H_ #include struct jtdev_func; struct jtdev { int port; uint8_t data_register; uint8_t control_register; int failed; const struct jtdev_func * f; }; struct jtdev_func{ /* Initialize/destroy a parallel-port JTAG interface. jtdev_open() * returns 0 on success or -1 if an error occurs. * * All other JTAG IO functions indicate errors by setting the failed * field in the jtdev structure. */ int (*jtdev_open)(struct jtdev *p, const char *device); void (*jtdev_close)(struct jtdev *p); /* Connect/release JTAG */ void (*jtdev_power_on)(struct jtdev *p); void (*jtdev_power_off)(struct jtdev *p); void (*jtdev_connect)(struct jtdev *p); void (*jtdev_release)(struct jtdev *p); /* Low-level IO */ void (*jtdev_tck)(struct jtdev *p, int out); void (*jtdev_tms)(struct jtdev *p, int out); void (*jtdev_tdi)(struct jtdev *p, int out); void (*jtdev_rst)(struct jtdev *p, int out); void (*jtdev_tst)(struct jtdev *p, int out); int (*jtdev_tdo_get)(struct jtdev *p); /* TCLK management */ void (*jtdev_tclk)(struct jtdev *p, int out); int (*jtdev_tclk_get)(struct jtdev *p); void (*jtdev_tclk_strobe)(struct jtdev *p, unsigned int count); /* LED indicators */ void (*jtdev_led_green)(struct jtdev *p, int out); void (*jtdev_led_red)(struct jtdev *p, int out); }; extern const struct jtdev_func jtdev_func_pif; extern const struct jtdev_func jtdev_func_gpio; extern const struct jtdev_func jtdev_func_bp; #endif mspdebug-0.25/drivers/jtdev_bus_pirate.c000066400000000000000000000207161313531517500204330ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * Copyright (C) 2012 Peter Bägel * * ppdev/ppi abstraction inspired by uisp src/DARPA.C * originally written by Sergey Larin; * corrected by Denis Chertykov, Uros Platise and Marek Michalkiewicz. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include "jtdev.h" #include "output.h" #if defined(__linux__) /*===== includes =============================================================*/ #include #include #include #include #include #include "util.h" /*===== private symbols ======================================================*/ /*--- bus pirate pins ---*/ #define BP_CS ((unsigned char)0x01) #define BP_MISO ((unsigned char)0x02) #define BP_CLK ((unsigned char)0x04) #define BP_MOSI ((unsigned char)0x08) #define BP_AUX ((unsigned char)0x10) #define BP_PULLUP ((unsigned char)0x20) #define BP_POWER ((unsigned char)0x40) /*--- bus pirate binary commands ---*/ #define CMD_ENTER_BB ((unsigned char)0x00) #define CMD_LEAVE_BB ((unsigned char)0x0f) #define CMD_CONFIG_PIN_DIR(x) ((unsigned char)0x40 | (x & 0x1f)) #define CMD_WRITE_PINS(x) ((unsigned char)0x80 | (x & 0x7f)) /*--- JTAG signal mapping ---*/ #define TDO BP_MISO #define TDI BP_MOSI #define TMS BP_CS #define POWER BP_POWER #define RESET BP_AUX #define TCK BP_CLK /*===== public functions =====================================================*/ #include static void do_bus_pirate_data(struct jtdev *p) { char res; char out_buff, in_buff; int buffered; out_buff = CMD_WRITE_PINS(p->data_register); ioctl(p->port, TIOCINQ, &buffered); if(buffered != 0) { pr_error("jtdev: extraneous bytes available on serial port, flushing it"); tcflush(p->port, TCIFLUSH); } if(write(p->port, &out_buff, 1) < 1) { pr_error("jtdev: failed writing to serial port"); p->failed = 1; } res = read(p->port, &in_buff, 1); p->data_register &= ~TDO; p->data_register |= in_buff & TDO; // TODO: Handle failure, try again if we don't receive if (res < 1) { pr_error("jtdev: no response with in data"); p->failed = 1; } } static int jtbp_open(struct jtdev *p, const char *device) { int i; char in_buff, out_buff; struct termios tio; const char* response = "BBIO1"; p->port = open(device, O_RDWR | O_NOCTTY); if (p->port < 0) { printc_err("jtdev: can't open %s: %s\n", device, last_error()); return -1; } memset(&tio, 0, sizeof(tio)); tio.c_cflag = B115200 | CS8 | CLOCAL | CREAD; tio.c_iflag = IGNPAR; tio.c_oflag = 0; tio.c_lflag = 0; tio.c_cc[VTIME] = 1; tio.c_cc[VMIN] = 0; tcflush(p->port, TCIFLUSH); tcsetattr(p->port, TCSANOW, &tio); // If it's in the middle of spewing something, let it finish while(read(p->port, &in_buff, 1) != 0); out_buff = 0; for(i=0; i<20; ++i) { if(write(p->port, &out_buff, 1) < 1) { pr_error("jtdev: failed writing to serial port"); p->failed = 1; } if(read(p->port, &in_buff, 1) > 0) { break; } } if (i == 20) { printc_err("jtdev: bus pirate failed to enter bit bang mode\n"); return -1; } if(in_buff != *response) { printc_err("jtdev: bus pirate: got bad response %c\n", in_buff); return -1; } ++response; for(i=0; i<4; ++i, ++response) { if(read(p->port, &in_buff, 1) <= 0) { printc_err("jtdev: bus pirate: got no response\n"); } if(in_buff != *response) { printc_err("jtdev: bus pirate: got bad response %c\n", in_buff); return -1; } } out_buff = CMD_CONFIG_PIN_DIR(TDO); if(write(p->port, &out_buff, 1) < 1) { pr_error("jtdev: failed writing to serial port"); p->failed = 1; } if(read(p->port, &in_buff, 1) <= 0) { printc_err("jtdev: bus pirate: got no response\n"); } p->data_register = 0; p->control_register = 0; p->failed = 0; do_bus_pirate_data(p); return 0; } static void jtbp_close(struct jtdev *p) { char out_buff; out_buff = 0x0f; // Don't care if this fails, user can just power cycle the bus pirate if(write(p->port, &out_buff, 1)); close(p->port); } static void jtbp_power_on(struct jtdev *p) { /* power supply on */ p->data_register |= POWER; do_bus_pirate_data(p); sleep(1); } static void jtbp_power_off(struct jtdev *p) { /* power supply off */ p->data_register &= ~(POWER | RESET); do_bus_pirate_data(p); } static void jtbp_connect(struct jtdev *p) { // unsure what this function does, I presume my setup w/ bus pirate is // "always enabled" } static void jtbp_release(struct jtdev *p) { // unsure what this function does, I presume my setup w/ bus pirate is // "always enabled" } static void jtbp_tck(struct jtdev *p, int out) { if (out) p->data_register |= TCK; else p->data_register &= ~TCK; do_bus_pirate_data(p); } static void jtbp_tms(struct jtdev *p, int out) { if (out) p->data_register |= TMS; else p->data_register &= ~TMS; do_bus_pirate_data(p); } static void jtbp_tdi(struct jtdev *p, int out) { if (out) p->data_register |= TDI; else p->data_register &= ~TDI; do_bus_pirate_data(p); } static void jtbp_rst(struct jtdev *p, int out) { if (out) p->data_register |= RESET; else p->data_register &= ~RESET; do_bus_pirate_data(p); } static void jtbp_tst(struct jtdev *p, int out) { // Test not supported on bus pirate } static int jtbp_tdo_get(struct jtdev *p) { do_bus_pirate_data(p); return (p->data_register & TDO) ? 1 : 0; } static void jtbp_tclk(struct jtdev *p, int out) { jtbp_tdi(p, out); } static int jtbp_tclk_get(struct jtdev *p) { do_bus_pirate_data(p); return (p->data_register & TDI) ? 1 : 0; } static void jtbp_tclk_strobe(struct jtdev *p, unsigned int count) { int i; for (i = 0; i < count; i++) { jtbp_tclk(p, 1); jtbp_tclk(p, 0); if (p->failed) return; } } static void jtbp_led_green(struct jtdev *p, int out) { // TCLK not supported by bus pirate } static void jtbp_led_red(struct jtdev *p, int out) { // TCLK not supported by bus pirate } #else /* __linux__ */ static int jtbp_open(struct jtdev *p, const char *device) { printc_err("jtdev: driver is not supported on this platform\n"); p->failed = 1; return -1; } static void jtbp_close(struct jtdev *p) { } static void jtbp_power_on(struct jtdev *p) { } static void jtbp_power_off(struct jtdev *p) { } static void jtbp_connect(struct jtdev *p) { } static void jtbp_release(struct jtdev *p) { } static void jtbp_tck(struct jtdev *p, int out) { } static void jtbp_tms(struct jtdev *p, int out) { } static void jtbp_tdi(struct jtdev *p, int out) { } static void jtbp_rst(struct jtdev *p, int out) { } static void jtbp_tst(struct jtdev *p, int out) { } static int jtbp_tdo_get(struct jtdev *p) { return 0; } static void jtbp_tclk(struct jtdev *p, int out) { } static int jtbp_tclk_get(struct jtdev *p) { return 0; } static void jtbp_tclk_strobe(struct jtdev *p, unsigned int count) { } static void jtbp_led_green(struct jtdev *p, int out) { } static void jtbp_led_red(struct jtdev *p, int out) { } #endif const struct jtdev_func jtdev_func_bp = { .jtdev_open = jtbp_open, .jtdev_close = jtbp_close, .jtdev_power_on = jtbp_power_on, .jtdev_power_off = jtbp_power_off, .jtdev_connect = jtbp_connect, .jtdev_release = jtbp_release, .jtdev_tck = jtbp_tck, .jtdev_tms = jtbp_tms, .jtdev_tdi = jtbp_tdi, .jtdev_rst = jtbp_rst, .jtdev_tst = jtbp_tst, .jtdev_tdo_get = jtbp_tdo_get, .jtdev_tclk = jtbp_tclk, .jtdev_tclk_get = jtbp_tclk_get, .jtdev_tclk_strobe = jtbp_tclk_strobe, .jtdev_led_green = jtbp_led_green, .jtdev_led_red = jtbp_led_red }; mspdebug-0.25/drivers/jtdev_gpio.c000066400000000000000000000142411313531517500172300ustar00rootroot00000000000000/* MSPDebug - gpio device interface * Copyright (C) 2014 TTI GmbH - TGU Smartmote * Author(s): Jan Willeke (willeke@smartmote.de) * * Linux /sys/class/gpio interface to msp430 jtag * inspired by urjtag and jtdev.c * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include "jtdev.h" #include "output.h" #if defined(__linux__) || \ ( defined(__FreeBSD__) || defined(__DragonFly__) ) /*===== includes =============================================================*/ #include #include #include #include #include #include "gpio.h" /* pin mapping */ enum { GPIO_TDI = 0, GPIO_TCK, GPIO_TMS, GPIO_TDO, GPIO_RST, GPIO_TST, GPIO_REQUIRED }; unsigned int jtag_gpios[6]; int fd_gpios[6]; static int gpio_open () { int i, ret; /* Export all gpios */ for (i = 0; i < GPIO_REQUIRED; i++) { unsigned int gpio = jtag_gpios[i]; ret = gpio_export (gpio); if (ret) { printf("gpio[%d] %u cannot be exported\n", i, gpio); return -1; } gpio_set_dir (gpio, (i == GPIO_TDO) ? 0 : 1); fd_gpios[i] = gpio_open_fd(gpio); if (fd_gpios[i] < 0) { printf("gpio: cannot open gpio[%d] %u\n", i, gpio); return -1; } } return 0; } static int gpio_parse_config (const char *params) { struct option{ char* name; int num; }; static const struct option ops[] = { {"tms=",GPIO_TMS}, {"tdi=",GPIO_TDI}, {"tdo=",GPIO_TDO}, {"tck=",GPIO_TCK}, {"rst=",GPIO_RST}, {"tst=",GPIO_TST} }; int i; for( i = 0;i < 6; i++) { char* help; help = strstr(params,ops[i].name); if (help) jtag_gpios[ops[i].num] = atoi(help+4); else return -1; printf("gpio %s %d\n", ops[i].name,jtag_gpios[ops[i].num]); } return 0; } static int jtgpio_open(struct jtdev *p, const char *device) { if (gpio_parse_config(device)){ printf("gpio: failed parsing parameters\n"); return -1; } return gpio_open(); } static void jtgpio_close(struct jtdev *p) { int i; printf("JTAG_CLOSE\n"); for (i = 0; i < GPIO_REQUIRED; i++) { if (fd_gpios[i]) close (fd_gpios[i]); gpio_unexport (jtag_gpios[i]); } } static void jtgpio_power_on(struct jtdev *p) { printf("JTAG_power on\n"); } static void jtgpio_power_off(struct jtdev *p) { printf("JTAG_power off\n"); } static void jtgpio_connect(struct jtdev *p) { printf("JTAG_connct \n"); } static void jtgpio_release(struct jtdev *p) { printf("JTAG_release\n"); } static void jtgpio_tck(struct jtdev *p, int out) { gpio_set_value_fd (fd_gpios[GPIO_TCK], out); } static void jtgpio_tms(struct jtdev *p, int out) { gpio_set_value_fd (fd_gpios[GPIO_TMS], out); } static void jtgpio_tdi(struct jtdev *p, int out) { gpio_set_value_fd (fd_gpios[GPIO_TDI], out); } static void jtgpio_rst(struct jtdev *p, int out) { gpio_set_value_fd (fd_gpios[GPIO_RST], out); } static void jtgpio_tst(struct jtdev *p, int out) { gpio_set_value_fd (fd_gpios[GPIO_TST], out); } static int jtgpio_tdo_get(struct jtdev *p) { return gpio_get_value_fd (fd_gpios[GPIO_TDO], jtag_gpios[GPIO_TDO]); } static void jtgpio_tclk(struct jtdev *p, int out) { gpio_set_value_fd (fd_gpios[GPIO_TDI], out); } static int jtgpio_tclk_get(struct jtdev *p) { return gpio_get_value_fd (fd_gpios[GPIO_TDI], jtag_gpios[GPIO_TDI]); } static void jtgpio_tclk_strobe(struct jtdev *p, unsigned int count) { int i; for (i=0;ifailed = 1; return -1; } static void jtgpio_close(struct jtdev *p) { } static void jtgpio_power_on(struct jtdev *p) { } static void jtgpio_power_off(struct jtdev *p) { } static void jtgpio_connect(struct jtdev *p) { } static void jtgpio_release(struct jtdev *p) { } static void jtgpio_tck(struct jtdev *p, int out) { } static void jtgpio_tms(struct jtdev *p, int out) { } static void jtgpio_tdi(struct jtdev *p, int out) { } static void jtgpio_rst(struct jtdev *p, int out) { } static void jtgpio_tst(struct jtdev *p, int out) { } static int jtgpio_tdo_get(struct jtdev *p) { return 0; } static void jtgpio_tclk(struct jtdev *p, int out) { } static int jtgpio_tclk_get(struct jtdev *p) { return 0; } static void jtgpio_tclk_strobe(struct jtdev *p, unsigned int count) { } static void jtgpio_led_green(struct jtdev *p, int out) { } static void jtgpio_led_red(struct jtdev *p, int out) { } #endif const struct jtdev_func jtdev_func_gpio = { .jtdev_open = jtgpio_open, .jtdev_close = jtgpio_close, .jtdev_power_on = jtgpio_power_on, .jtdev_power_off = jtgpio_power_off, .jtdev_connect = jtgpio_connect, .jtdev_release = jtgpio_release, .jtdev_tck = jtgpio_tck, .jtdev_tms = jtgpio_tms, .jtdev_tdi = jtgpio_tdi, .jtdev_rst = jtgpio_rst, .jtdev_tst = jtgpio_tst, .jtdev_tdo_get = jtgpio_tdo_get, .jtdev_tclk = jtgpio_tclk, .jtdev_tclk_get = jtgpio_tclk_get, .jtdev_tclk_strobe = jtgpio_tclk_strobe, .jtdev_led_green = jtgpio_led_green, .jtdev_led_red = jtgpio_led_red }; mspdebug-0.25/drivers/loadbsl.c000066400000000000000000000245361313531517500165260ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2013 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include "output.h" #include "util.h" #include "loadbsl.h" #include "loadbsl_fw.h" #include "bslhid.h" #define BSL_MAX_CORE 62 #define BSL_MAX_BLOCK 52 #define BSL_CMD_RX_BLOCK 0x10 #define BSL_CMD_RX_BLOCK_FAST 0x1B #define BSL_CMD_RX_PASSWORD 0x11 #define BSL_CMD_ERASE_SEGMENT 0x12 #define BSL_CMD_UNLOCK_LOCK_INFO 0x13 #define BSL_CMD_MASS_ERASE 0x15 #define BSL_CMD_CRC_CHECK 0x16 #define BSL_CMD_LOAD_PC 0x17 #define BSL_CMD_TX_BLOCK 0x18 #define BSL_CMD_TX_VERSION 0x19 #define BSL_CMD_TX_BUFSIZE 0x1A #define BSL_PACKET_HEADER 0x80 #define BSL_PACKET_ACK 0x90 /* BSL error codes: from SLAU319C ("MSP430 Programming via the Bootstrap * Loader"). */ static const char *const bsl_error_table[9] = { [0x00] = "Success", [0x01] = "Flash write check failed", [0x02] = "Flash fail bit set", [0x03] = "Voltage change during program", [0x04] = "BSL locked", [0x05] = "BSL password error", [0x06] = "Byte write forbidden", [0x07] = "Unknown command", [0x08] = "Packet length exceeds buffer size" }; static const char *bsl_error_message(int code) { const char *text = NULL; if (code >= 0 && code < ARRAY_LEN(bsl_error_table)) text = bsl_error_table[code]; if (text) return text; return "Unknown error code"; } struct loadbsl_device { struct device base; transport_t trans; }; static int send_command(transport_t trans, uint8_t cmd, address_t addr, const uint8_t *data, int datalen) { uint8_t outbuf[BSL_MAX_CORE]; const int addrlen = (addr != ADDRESS_NONE) ? 3 : 0; const int corelen = datalen + addrlen + 1; if (datalen > BSL_MAX_BLOCK) { printc_err("loadbsl: send_command: MAX_BLOCK exceeded: %d\n", datalen); return -1; } outbuf[0] = cmd; if (addrlen > 0) { outbuf[1] = addr & 0xff; outbuf[2] = (addr >> 8) & 0xff; outbuf[3] = (addr >> 16) & 0xff; } memcpy(outbuf + 1 + addrlen, data, datalen); if (trans->ops->send(trans, outbuf, corelen) < 0) { printc_err("loadbsl: send_command failed\n"); return -1; } return 0; } static int recv_packet(transport_t trans, uint8_t *data, int max_len) { uint8_t inbuf[BSL_MAX_CORE]; int len = trans->ops->recv(trans, inbuf, sizeof(inbuf)); int type; int code; if (len < 0) { printc_err("loadbsl: recv_packet: transport error\n"); return -1; } if (len < 1) { printc_err("loadbsl: recv_packet: zero-length packet\n"); return -1; } type = inbuf[0]; if (type == 0x3a) { const int data_len = len - 1; if (!data) return 0; if (data_len > max_len) { printc_err("loadbsl: recv_packet: packet too " "long for buffer (%d bytes)\n", data_len); return -1; } memcpy(data, inbuf + 1, data_len); return data_len; } if (type != 0x3b) { printc_err("loadbsl: recv_packet: unknown packet type: " "0x%02x\n", type); return -1; } if (len < 2) { printc_err("loadbsl: recv_packet: missing response code\n"); return -1; } code = inbuf[1]; if (code) { printc_err("loadbsl: recv_packet: BSL error code: %d (%s)\n", code, bsl_error_message(code)); return -1; } return 0; } /* Retrieve and display BSL version info. Returns API version byte. */ static int version_check(transport_t trans) { uint8_t data[4]; int r; if (send_command(trans, BSL_CMD_TX_VERSION, ADDRESS_NONE, NULL, 0) < 0) { printc_err("loadbsl: failed to send TX_VERSION command\n"); return -1; } r = recv_packet(trans, data, 4); if (r < 0) { printc_err("loadbsl: failed to receive version\n"); return -1; } if (r < 4) { printc_err("loadbsl: short version response\n"); return -1; } printc_dbg("BSL version: [vendor: %02x, int: %02x, " "API: %02x, per: %02x]\n", data[0], data[1], data[2], data[3]); return data[2]; } static int do_writemem(transport_t trans, address_t addr, const uint8_t *mem, address_t len) { while (len) { int plen = len; if (plen > BSL_MAX_BLOCK) plen = BSL_MAX_BLOCK; if (send_command(trans, BSL_CMD_RX_BLOCK_FAST, addr, mem, plen) < 0) { printc_err("loadbsl: failed to write block " "to 0x%04x\n", addr); return -1; } addr += plen; mem += plen; len -= plen; } return 0; } static int rx_password(transport_t trans) { uint8_t password[32]; memset(password, 0xff, sizeof(password)); if (send_command(trans, BSL_CMD_RX_PASSWORD, ADDRESS_NONE, password, sizeof(password)) < 0 || recv_packet(trans, NULL, 0) < 0) { printc_err("loadbsl: rx_password failed\n"); return -1; } return 0; } static int check_and_load(transport_t trans) { const struct loadbsl_fw *fw = &loadbsl_fw_usb5xx; int api_version = version_check(trans); if ((api_version >= 0) && (api_version != 0x80)) return 0; printc_dbg("Uploading BSL firmware (%d bytes at address 0x%04x)...\n", fw->size, fw->prog_addr); if (do_writemem(trans, fw->prog_addr, fw->data, fw->size) < 0) { printc_err("loadbsl: firmware upload failed\n"); return -1; } printc_dbg("Starting new firmware (PC: 0x%04x)...\n", fw->entry_point); if (send_command(trans, BSL_CMD_LOAD_PC, fw->entry_point, NULL, 0) < 0) { printc_err("loadbsl: PC load failed\n"); return -1; } if (trans->ops->suspend && trans->ops->resume && trans->ops->suspend(trans) < 0) { printc_err("loadbsl: transport suspend failed\n"); return -1; } printc_dbg("Done, waiting for startup\n"); delay_ms(1000); if (trans->ops->suspend && trans->ops->resume && trans->ops->resume(trans) < 0) { printc_err("loadbsl: transport resume failed\n"); return -1; } if (rx_password(trans) < 0) { printc_err("loadbsl: failed to unlock new firmware\n"); return -1; } return version_check(trans); } static void loadbsl_destroy(device_t base) { struct loadbsl_device *dev = (struct loadbsl_device *)base; static const uint8_t puc_word[] = {0, 0}; /* Write 0x0000 to WDTCTL, triggering a PUC */ if (send_command(dev->trans, BSL_CMD_RX_BLOCK_FAST, 0x15c, puc_word, sizeof(puc_word)) < 0) printc_err("warning: loadbsl: failed to trigger PUC\n"); dev->trans->ops->destroy(dev->trans); free(dev); } static int loadbsl_readmem(device_t base, address_t addr, uint8_t *mem, address_t len) { struct loadbsl_device *dev = (struct loadbsl_device *)base; while (len) { int plen = len; uint8_t len_param[2]; int r; if (plen > BSL_MAX_BLOCK) plen = BSL_MAX_BLOCK; len_param[0] = plen & 0xff; len_param[1] = plen >> 8; if (send_command(dev->trans, BSL_CMD_TX_BLOCK, addr, len_param, 2) < 0) goto fail; r = recv_packet(dev->trans, mem, plen); if (r < 0) goto fail; if (r < plen) { printc_err("loadbsl: short response to " "memory read\n"); return -1; } addr += plen; mem += plen; len -= plen; } return 0; fail: printc_err("loadbsl: failed to read block from 0x%04x\n", addr); return -1; } static int loadbsl_writemem(device_t base, address_t addr, const uint8_t *mem, address_t len) { struct loadbsl_device *dev = (struct loadbsl_device *)base; return do_writemem(dev->trans, addr, mem, len); } static int loadbsl_getregs(device_t base, address_t *regs) { (void)base; (void)regs; printc_err("loadbsl: register fetch is not implemented\n"); return -1; } static int loadbsl_setregs(device_t base, const address_t *regs) { (void)base; (void)regs; printc_err("loadbsl: register store is not implemented\n"); return -1; } static int loadbsl_erase(device_t base, device_erase_type_t type, address_t addr) { struct loadbsl_device *dev = (struct loadbsl_device *)base; switch (type) { case DEVICE_ERASE_ALL: printc_err("loadbsl: ERASE_ALL not supported\n"); return -1; case DEVICE_ERASE_MAIN: if (send_command(dev->trans, BSL_CMD_MASS_ERASE, ADDRESS_NONE, NULL, 0) < 0 || recv_packet(dev->trans, NULL, 0) < 0) { printc_err("loadbsl: ERASE_MAIN failed\n"); return -1; } break; case DEVICE_ERASE_SEGMENT: if (send_command(dev->trans, BSL_CMD_ERASE_SEGMENT, addr, NULL, 0) < 0 || recv_packet(dev->trans, NULL, 0) < 0) { printc_err("loadbsl: ERASE_SEGMENT failed\n"); return -1; } break; } return 0; } static int loadbsl_ctl(device_t base, device_ctl_t type) { (void)base; switch (type) { case DEVICE_CTL_HALT: case DEVICE_CTL_RESET: return 0; default: printc_err("loadbsl: CPU control is not possible\n"); return -1; } return 0; } static device_status_t loadbsl_poll(device_t base) { (void)base; return DEVICE_STATUS_HALTED; } static device_t loadbsl_open(const struct device_args *args) { struct loadbsl_device *dev; if (args->flags & DEVICE_FLAG_TTY) { printc_err("loadbsl: this driver does not support " "tty access\n"); return NULL; } dev = malloc(sizeof(*dev)); memset(dev, 0, sizeof(*dev)); dev->base.type = &device_loadbsl; dev->base.max_breakpoints = 0; #if defined(__APPLE__) dev->trans = bslosx_open(args->path, args->requested_serial); #else dev->trans = bslhid_open(args->path, args->requested_serial); #endif if (!dev->trans) { free(dev); return NULL; } if (rx_password(dev->trans) < 0) { printc_dbg("loadbsl: retrying password...\n"); if (rx_password(dev->trans) < 0) { dev->trans->ops->destroy(dev->trans); free(dev); return NULL; } } if (check_and_load(dev->trans) < 0) { dev->trans->ops->destroy(dev->trans); free(dev); return NULL; } return &dev->base; } const struct device_class device_loadbsl = { .name = "load-bsl", .help = "Loadable USB BSL driver (USB 5xx/6xx).", .open = loadbsl_open, .destroy = loadbsl_destroy, .readmem = loadbsl_readmem, .writemem = loadbsl_writemem, .erase = loadbsl_erase, .getregs = loadbsl_getregs, .setregs = loadbsl_setregs, .ctl = loadbsl_ctl, .poll = loadbsl_poll, .getconfigfuses = NULL }; mspdebug-0.25/drivers/loadbsl.h000066400000000000000000000017041313531517500165230ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2013 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef LOADBSL_H_ #define LOADBSL_H_ #include "device.h" /* MSP430 loadable BSL implementation */ extern const struct device_class device_loadbsl; #endif mspdebug-0.25/drivers/loadbsl_fw.c000066400000000000000000000407501313531517500172160ustar00rootroot00000000000000/* * MSPBLS_RAM_BSL.00.05.04.34 * * An array holding the bytes to be programmed into device RAM for full USB BSL cabability * * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ #include "loadbsl_fw.h" /* program start addr 0x2504 * first mem addr 0x2500 */ static const uint8_t RAM_BSL_00_05_04_34[] = { 0x00, 0x05, 0x04, 0x34, 0x31, 0x40, 0x90, 0x33, 0xB0, 0x13, 0x5E, 0x2E, 0x0C, 0x93, 0x00, 0x24, 0xB0, 0x13, 0xF4, 0x2D, 0xFF, 0x3F, 0x12, 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x08, 0x47, 0x20, 0x00, 0x02, 0x04, 0x01, 0x00, 0x00, 0x00, 0x01, 0x06, 0x00, 0xFF, 0x09, 0x01, 0xA1, 0x01, 0x85, 0x3F, 0x95, 0x3F, 0x75, 0x08, 0x25, 0x01, 0x15, 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0x3F, 0x40, 0xDE, 0x2E, 0x3F, 0x53, 0xFE, 0x2F, 0x10, 0x01, 0x92, 0xB3, 0x44, 0x01, 0xFD, 0x2F, 0x10, 0x01, 0xB2, 0x40, 0x80, 0x5A, 0x5C, 0x01, 0x10, 0x01, 0xB2, 0x90, 0xA5, 0xA5, 0x56, 0x24, 0x10, 0x01, 0x1D, 0x15, 0x10, 0x01 }; const struct loadbsl_fw loadbsl_fw_usb5xx = { .data = RAM_BSL_00_05_04_34, .size = sizeof(RAM_BSL_00_05_04_34), .prog_addr = 0x2500, .entry_point = 0x2504 }; mspdebug-0.25/drivers/loadbsl_fw.h000066400000000000000000000020751313531517500172210ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009-2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef LOADBSL_FW_H_ #define LOADBSL_FW_H_ #include /* USB BSL firmware image */ struct loadbsl_fw { const uint8_t *data; const uint32_t size; const uint32_t prog_addr; const uint32_t entry_point; }; extern const struct loadbsl_fw loadbsl_fw_usb5xx; #endif mspdebug-0.25/drivers/obl.c000066400000000000000000000214141313531517500156520ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include "util.h" #include "output.h" #include "obl.h" #define IMAGE_MAGIC 0xd1261176 #define FLASH_PAGE_SIZE 1024 #define COPY_OFFSET 0x38000 #define COPY_VALID_ADDR 0x7dff0 typedef enum { OBL_CMD_READ_RAM = 0x01, OBL_CMD_WRITE_RAM = 0x02, OBL_CMD_READ_FLASH = 0x03, OBL_CMD_WRITE_FLASH = 0x04, OBL_CMD_RF_SELF_TEST = 0x05, OBL_CMD_SET_PROTECTION = 0x06, OBL_CMD_DEV_RESET = 0x07, OBL_CMD_DEV_VERSION = 0x08, OBL_CMD_PROD_TEST = 0x09 } obl_cmd_t; typedef enum { OBL_RESULT_OK = 0x00, OBL_RESULT_NRF_SPI_FAULT = 0x01, OBL_RESULT_NRF_LINK_FAULT = 0x02, OBL_RESULT_COMMAND_FAULT = 0xff } obl_result_t; struct progress_meter { uint32_t total; uint32_t last; int interval_shift; }; static void progress_init(struct progress_meter *m, uint32_t size) { m->total = size; m->last = 0; m->interval_shift = 0; while (size > 30) { size >>= 1; m->interval_shift++; } } static void progress_update(struct progress_meter *m, const char *label, uint32_t cur) { if (!((m->last ^ cur) >> m->interval_shift)) return; m->last = cur; printc("%s: %8d/%8d [%3d%%]\n", label, cur, m->total, cur * 100 / m->total); } static int transport_read_all(transport_t tr, uint8_t *data, int len) { while (len > 0) { int r = tr->ops->recv(tr, data, len); if (r <= 0) return -1; data += r; len -= r; } return 0; } static int obl_xfer(transport_t tr, const uint8_t *command, int cmd_len, uint8_t *recv_data, int recv_len) { uint8_t result; if (tr->ops->set_modem(tr, TRANSPORT_MODEM_DTR) < 0) { printc_err("obl_xfer: failed to activate DTR\n"); return -1; } if (tr->ops->send(tr, command, cmd_len) < 0) { printc_err("obl_xfer: failed to send command\n"); goto fail; } if (tr->ops->recv(tr, &result, 1) < 0) { printc_err("obl_xfer: failed to read status byte\n"); goto fail; } if (result != OBL_RESULT_OK) { printc_err("obl_xfer: device error code: 0x%02x\n", result); goto fail; } if (recv_len && transport_read_all(tr, recv_data, recv_len) < 0) { printc_err("obl_xfer: failed to read data\n"); goto fail; } tr->ops->set_modem(tr, 0); return 0; fail: tr->ops->set_modem(tr, 0); return -1; } static uint8_t *read_file(const char *filename, unsigned int *len_ret) { FILE *in = fopen(filename, "rb"); unsigned int len; uint8_t *buf; if (!in) { printc_err("Can't open %s for reading: %s\n", filename, last_error()); return NULL; } if (fseek(in, 0, SEEK_END) < 0) { printc_err("Can't determine file size: %s: %s\n", filename, last_error()); fclose(in); return NULL; } len = ftell(in); rewind(in); buf = malloc(len); if (!buf) { printc_err("Can't allocate memory for " "firmware image: %s: %s\n", filename, last_error()); fclose(in); return NULL; } if (fread(buf, len, 1, in) != 1) { printc_err("Failed to read %s: %s\n", filename, last_error()); free(buf); fclose(in); return NULL; } fclose(in); *len_ret = len; return buf; } static int obl_read_mem(transport_t tr, uint32_t addr, uint8_t *data, uint32_t size) { uint8_t cmd[9]; cmd[0] = OBL_CMD_READ_RAM; cmd[1] = addr & 0xff; cmd[2] = (addr >> 8) & 0xff; cmd[3] = (addr >> 16) & 0xff; cmd[4] = (addr >> 24) & 0xff; cmd[5] = size & 0xff; cmd[6] = (size >> 8) & 0xff; cmd[7] = (size >> 16) & 0xff; cmd[8] = (size >> 24) & 0xff; if (obl_xfer(tr, cmd, sizeof(cmd), data, size) < 0) { printc_err("obl_read_mem: failed to read %d bytes from " "0x%x\n", size, addr); return -1; } return 0; } static int obl_write_flash(transport_t tr, uint32_t addr, const uint8_t *data, uint32_t size) { uint8_t cmd[size + 9]; cmd[0] = OBL_CMD_WRITE_FLASH; cmd[1] = addr & 0xff; cmd[2] = (addr >> 8) & 0xff; cmd[3] = (addr >> 16) & 0xff; cmd[4] = (addr >> 24) & 0xff; cmd[5] = size & 0xff; cmd[6] = (size >> 8) & 0xff; cmd[7] = (size >> 16) & 0xff; cmd[8] = (size >> 24) & 0xff; memcpy(cmd + 9, data, size); if (obl_xfer(tr, cmd, size + 9, NULL, 0) < 0) { printc_err("obl_write_flash: failed to write %d bytes to " "0x%x\n", size, addr); return -1; } return 0; } static int write_image(transport_t tr, uint32_t addr, uint32_t size, const uint8_t *data) { struct progress_meter pm; uint32_t i; progress_init(&pm, size); for (i = 0; i < size; i += FLASH_PAGE_SIZE) { const uint32_t offset = i + addr + COPY_OFFSET; int r; if (i + FLASH_PAGE_SIZE < size) { r = obl_write_flash(tr, offset, data + i, FLASH_PAGE_SIZE); } else { uint8_t partial[FLASH_PAGE_SIZE]; memset(partial, 0xff, sizeof(partial)); memcpy(partial, data + i, size - i); r = obl_write_flash(tr, offset, partial, FLASH_PAGE_SIZE); } if (r < 0) { printc_err("Write failed at offset 0x%x\n", i); return -1; } progress_update(&pm, "Writing", i); } return 0; } static int verify_image(transport_t tr, uint32_t addr, uint32_t size, const uint8_t *data) { struct progress_meter pm; uint32_t i; progress_init(&pm, size); for (i = 0; i < size; i += FLASH_PAGE_SIZE) { const uint32_t offset = i + addr + COPY_OFFSET; uint8_t buf[FLASH_PAGE_SIZE]; int is_ok = 1; if (obl_read_mem(tr, offset, buf, FLASH_PAGE_SIZE) < 0) { printc_err("Read error at offset 0x%x\n", i); return -1; } if (i + FLASH_PAGE_SIZE < size) { if (memcmp(buf, data + i, FLASH_PAGE_SIZE)) is_ok = 0; } else { int j; if (memcmp(buf, data + i, size - i)) is_ok = 0; for (j = size - i; j < FLASH_PAGE_SIZE; j++) if (buf[j] != 0xff) is_ok = 0; } if (!is_ok) { printc_err("Verification failed at flash " "page offset 0x%x\n", i); return -1; } progress_update(&pm, "Verifying", i); } return 0; } static int write_valid_size(transport_t tr, uint32_t size) { uint8_t buf[FLASH_PAGE_SIZE]; const int page = COPY_VALID_ADDR & ~(FLASH_PAGE_SIZE - 1); const int offset = COPY_VALID_ADDR & (FLASH_PAGE_SIZE - 1); memset(buf, 0xff, sizeof(buf)); buf[offset] = size & 0xff; buf[offset + 1] = (size >> 8) & 0xff; buf[offset + 2] = (size >> 16) & 0xff; buf[offset + 3] = (size >> 24) & 0xff; if (obl_write_flash(tr, page, buf, FLASH_PAGE_SIZE) < 0) { printc_err("Failed to write image-valid marker\n"); return -1; } return 0; } int obl_get_version(transport_t tr, uint32_t *ver_ret) { static const uint8_t cmd = OBL_CMD_DEV_VERSION; uint8_t buf[4]; uint32_t version; if (obl_xfer(tr, &cmd, 1, buf, 4) < 0) { printc_err("warning: obl_get_version: unable to retrieve " "Olimex firmware version\n"); return -1; } version = LE_LONG(buf, 0); if (ver_ret) *ver_ret = version; return 0; } static int load_image(transport_t trans, const uint8_t *file_data, unsigned int file_len, const char *image_filename) { uint32_t image_offset; uint32_t image_size; if (file_len < 16 || LE_LONG(file_data, 0) != IMAGE_MAGIC) { printc_err("Invalid firmware image: %s\n", image_filename); return -1; } image_offset = LE_LONG(file_data, 8); image_size = LE_LONG(file_data, 12); printc_dbg("Firmware image version: %x: %d bytes at offset 0x%x\n", LE_LONG(file_data, 4), image_size, image_offset); if (image_size + 16 != file_len) { printc_err("Image length mismatch: %s\n", image_filename); return -1; } if (write_image(trans, image_offset, image_size, file_data + 16) < 0) return -1; if (verify_image(trans, image_offset, image_size, file_data + 16) < 0) return -1; if (write_valid_size(trans, image_size) < 0) return -1; printc("Firmware update successful\n"); return 0; } int obl_update(transport_t trans, const char *image_filename) { uint8_t *file_data; unsigned int file_len; file_data = read_file(image_filename, &file_len); if (!file_data) return -1; if (load_image(trans, file_data, file_len, image_filename) < 0) { free(file_data); return -1; } free(file_data); return 0; } int obl_reset(transport_t trans) { const uint8_t cmd = OBL_CMD_DEV_RESET; if (obl_xfer(trans, &cmd, 1, NULL, 0) < 0) { printc_err("Device reset failed\n"); return -1; } return 0; } mspdebug-0.25/drivers/obl.h000066400000000000000000000026111313531517500156550ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef OBL_H_ #define OBL_H_ #include "transport.h" /* Fetch the version of installed Olimex firmware. Returns 0 on success * or -1 if an error occurs. */ int obl_get_version(transport_t trans, uint32_t *ver_ret); /* Perform a firmware update using the given image file. */ int obl_update(transport_t trans, const char *image_filename); /* Perform a device reset. This will return almost immediately, but it * will take 15 seconds for the reset to complete. During this time, the * underlying device will disappear and reappear, so it must be * reopened. */ int obl_reset(transport_t trans); #endif mspdebug-0.25/drivers/pif.c000066400000000000000000000316731313531517500156640ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * Copyright (C) 2012-2015 Peter Bägel * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ /* Driver for parallel port interface like the Olimex MSP430-JTAG * Starting point was the goodfet driver * * 2012-10-03 initial release Peter Bägel (DF5EQ) * 2014-12-26 single step implemented Peter Bägel (DF5EQ) * 2015-02-21 breakpoints implemented Peter Bägel (DF5EQ) */ #include #include #include "util.h" #include "output.h" #include "pif.h" #include "jtaglib.h" #include "ctrlc.h" struct pif_device { struct device base; struct jtdev jtag; }; /*============================================================================*/ /* pif MSP430 JTAG operations */ /*----------------------------------------------------------------------------*/ /* Read a word-aligned block from any kind of memory * returns the number of bytes read or -1 on failure */ static int read_words(device_t dev, const struct chipinfo_memory *m, address_t addr, address_t len, uint8_t *data) { struct pif_device *pif = (struct pif_device *)dev; struct jtdev *p = &pif->jtag; unsigned int index; unsigned int word; for ( index = 0; index < len; index += 2 ) { word = jtag_read_mem( p, 16, addr+index ); data[index] = word & 0x00ff; data[index+1] = (word >> 8) & 0x00ff; } return p->failed ? -1 : len; } /*----------------------------------------------------------------------------*/ /* Write a word to RAM */ static int write_ram_word( struct jtdev *p, address_t addr, uint16_t value ) { jtag_write_mem( p, 16, addr, value ); return p->failed ? -1 : 0; } /*----------------------------------------------------------------------------*/ /* Write a word-aligned flash block. */ /* The starting address must be within the flash memory range. */ static int write_flash_block( struct jtdev *p, address_t addr, address_t len, const uint8_t *data) { unsigned int i; uint16_t *word; word = malloc( len / 2 * sizeof(*word) ); if (!word) { pr_error("pif: failed to allocate memory"); return -1; } for(i = 0; i < len/2; i++) { word[i]=data[2*i] + (((uint16_t)data[2*i+1]) << 8); } jtag_write_flash( p, addr, len/2, word ); free(word); return p->failed ? -1 : 0; } /* Write a word-aligned block to any kind of memory. * returns the number of bytes written or -1 on failure */ static int write_words(device_t dev, const struct chipinfo_memory *m, address_t addr, address_t len, const uint8_t *data) { struct pif_device *pif = (struct pif_device *)dev; struct jtdev *p = &pif->jtag; int r; if (m->type != CHIPINFO_MEMTYPE_FLASH) { len = 2; r = write_ram_word(p, addr, r16le(data)); } else { r = write_flash_block(p, addr, len, data); } if (r < 0) { printc_err("pif: write_words at address 0x%x failed\n", addr); return -1; } return len; } /*----------------------------------------------------------------------------*/ static int init_device(struct jtdev *p) { unsigned int jtag_id; printc_dbg("Starting JTAG\n"); jtag_id = jtag_init(p); printc("JTAG ID: 0x%02x\n", jtag_id); if (jtag_id != 0x89 && jtag_id != 0x91) { printc_err("pif: unexpected JTAG ID: 0x%02x\n", jtag_id); jtag_release_device(p, 0xfffe); return -1; } return 0; } /*===== MSPDebug Device interface ============================================*/ /*----------------------------------------------------------------------------*/ static int refresh_bps(struct pif_device *dev) { int i; int ret; struct device_breakpoint *bp; address_t addr; ret = 0; for (i = 0; i < dev->base.max_breakpoints; i++) { bp = &dev->base.breakpoints[i]; printc_dbg("refresh breakpoint %d: type=%d " "addr=%04x flags=%04x\n", i, bp->type, bp->addr, bp->flags); if ( (bp->flags & DEVICE_BP_DIRTY) && (bp->type == DEVICE_BPTYPE_BREAK) ) { addr = bp->addr; if ( !(bp->flags & DEVICE_BP_ENABLED) ) { addr = 0; } if ( jtag_set_breakpoint (&dev->jtag, i, addr) == 0) { printc_err("pif: failed to refresh " "breakpoint #%d\n", i); ret = -1; } else { bp->flags &= ~DEVICE_BP_DIRTY; } } } return ret; } /*----------------------------------------------------------------------------*/ static int pif_readmem( device_t dev_base, address_t addr, uint8_t* mem, address_t len ) { struct pif_device *dev = (struct pif_device *)dev_base; dev->jtag.failed = 0; return readmem(dev_base, addr, mem, len, read_words); } /*----------------------------------------------------------------------------*/ static int pif_writemem( device_t dev_base, address_t addr, const uint8_t* mem, address_t len ) { struct pif_device *dev = (struct pif_device *)dev_base; dev->jtag.failed = 0; return writemem(dev_base, addr, mem, len, write_words, read_words); } /*----------------------------------------------------------------------------*/ static int pif_getregs(device_t dev_base, address_t *regs) { struct pif_device *dev = (struct pif_device *)dev_base; int i; dev->jtag.failed = 0; for (i = 0; i < DEVICE_NUM_REGS; i++) regs[i] = jtag_read_reg(&dev->jtag, i); return dev->jtag.failed ? -1 : 0; } /*----------------------------------------------------------------------------*/ static int pif_setregs( device_t dev_base, const address_t* regs ) { struct pif_device *dev = (struct pif_device *)dev_base; int i; dev->jtag.failed = 0; for (i = 0; i < DEVICE_NUM_REGS; i++) { jtag_write_reg( &dev->jtag, i, regs[i] ); } return dev->jtag.failed ? -1 : 0; } /*----------------------------------------------------------------------------*/ static int pif_ctl(device_t dev_base, device_ctl_t type) { struct pif_device *dev = (struct pif_device *)dev_base; dev->jtag.failed = 0; switch (type) { case DEVICE_CTL_RESET: /* perform soft reset */ jtag_execute_puc(&dev->jtag); break; case DEVICE_CTL_RUN: /* transfer changed breakpoints to device */ if (refresh_bps(dev) < 0) { return -1; } /* start program execution at current PC */ jtag_release_device(&dev->jtag, 0xffff); break; case DEVICE_CTL_HALT: /* take device under JTAG control */ jtag_get_device(&dev->jtag); break; case DEVICE_CTL_STEP: /* execute next instruction at current PC */ jtag_single_step(&dev->jtag); break; default: printc_err("pif: unsupported operation\n"); return -1; } return dev->jtag.failed ? -1 : 0; } /*----------------------------------------------------------------------------*/ static device_status_t pif_poll(device_t dev_base) { struct pif_device *dev = (struct pif_device *)dev_base; if (delay_ms(100) < 0 || ctrlc_check()) return DEVICE_STATUS_INTR; if (jtag_cpu_state(&dev->jtag) == 1) { return DEVICE_STATUS_HALTED; } return DEVICE_STATUS_RUNNING; } /*----------------------------------------------------------------------------*/ static int pif_erase( device_t dev_base, device_erase_type_t type, address_t addr ) { struct pif_device *dev = (struct pif_device *)dev_base; dev->jtag.failed = 0; switch(type) { case DEVICE_ERASE_MAIN: jtag_erase_flash ( &dev->jtag, JTAG_ERASE_MAIN, addr ); break; case DEVICE_ERASE_ALL: jtag_erase_flash ( &dev->jtag, JTAG_ERASE_MASS, addr ); break; case DEVICE_ERASE_SEGMENT: jtag_erase_flash ( &dev->jtag, JTAG_ERASE_SGMT, addr ); break; default: return -1; } return dev->jtag.failed ? -1 : 0; } /*----------------------------------------------------------------------------*/ static int pif_getconfigfuses(device_t dev_base) { struct pif_device *dev = (struct pif_device *)dev_base; return jtag_get_config_fuses(&dev->jtag); } /*----------------------------------------------------------------------------*/ static device_t pif_open(const struct device_args *args) { struct pif_device *dev; if (!(args->flags & DEVICE_FLAG_TTY)) { printc_err("pif: this driver does not support raw USB access\n"); return NULL; } if (!(args->flags & DEVICE_FLAG_JTAG)) { printc_err("pif: this driver does not support Spy-Bi-Wire\n"); return NULL; } dev = malloc(sizeof(*dev)); if (!dev) { printc_err("pif: malloc: %s\n", last_error()); return NULL; } memset(dev, 0, sizeof(*dev)); dev->base.type = &device_pif; dev->base.max_breakpoints = 2; //supported by all devices dev->base.need_probe = 1; (&dev->jtag)->f = &jtdev_func_pif; if ((&dev->jtag)->f->jtdev_open(&dev->jtag, args->path) < 0) { printc_err("pif: can't open port\n"); free(dev); return NULL; } if (init_device(&dev->jtag) < 0) { printc_err("pif: initialization failed\n"); free(dev); return NULL; } return &dev->base; } /*----------------------------------------------------------------------------*/ static device_t gpio_open(const struct device_args *args) { struct pif_device *dev; if (!(args->flags & DEVICE_FLAG_TTY)) { printc_err("gpio: this driver does not support raw USB access\n"); return NULL; } if (!(args->flags & DEVICE_FLAG_JTAG)) { printc_err("gpio: this driver does not support Spy-Bi-Wire\n"); return NULL; } dev = malloc(sizeof(*dev)); if (!dev) { printc_err("gpio: malloc: %s\n", last_error()); return NULL; } memset(dev, 0, sizeof(*dev)); dev->base.type = &device_pif; dev->base.max_breakpoints = 0; (&dev->jtag)->f = &jtdev_func_gpio; if ((&dev->jtag)->f->jtdev_open(&dev->jtag, args->path) < 0) { printc_err("gpio: can't open port\n"); free(dev); return NULL; } if (init_device(&dev->jtag) < 0) { printc_err("gpio: initialization failed\n"); free(dev); return NULL; } return &dev->base; } /*----------------------------------------------------------------------------*/ static device_t bp_open(const struct device_args *args) { struct pif_device *dev; if (!(args->flags & DEVICE_FLAG_TTY)) { printc_err("bp: this driver does not support raw USB access\n"); return NULL; } if (!(args->flags & DEVICE_FLAG_JTAG)) { printc_err("bp: this driver does not support Spy-Bi-Wire\n"); return NULL; } dev = malloc(sizeof(*dev)); if (!dev) { printc_err("bp: malloc: %s\n", last_error()); return NULL; } memset(dev, 0, sizeof(*dev)); dev->base.type = &device_pif; dev->base.max_breakpoints = 2; //supported by all devices dev->base.need_probe = 1; (&dev->jtag)->f = &jtdev_func_bp; if ((&dev->jtag)->f->jtdev_open(&dev->jtag, args->path) < 0) { printc_err("bp: can't open port\n"); free(dev); return NULL; } if (init_device(&dev->jtag) < 0) { printc_err("bp: initialization failed\n"); free(dev); return NULL; } return &dev->base; } /*----------------------------------------------------------------------------*/ static void pif_destroy(device_t dev_base) { struct pif_device *dev = (struct pif_device *)dev_base; dev->jtag.failed = 0; jtag_release_device(&dev->jtag, 0xfffe); (&dev->jtag)->f->jtdev_close(&dev->jtag); free(dev); } /*----------------------------------------------------------------------------*/ const struct device_class device_pif = { .name = "pif", .help = "Parallel Port JTAG", .open = pif_open, .destroy = pif_destroy, .readmem = pif_readmem, .writemem = pif_writemem, .getregs = pif_getregs, .setregs = pif_setregs, .ctl = pif_ctl, .poll = pif_poll, .erase = pif_erase, .getconfigfuses = pif_getconfigfuses }; const struct device_class device_gpio = { .name = "gpio", .help = "/sys/class/gpio direct connect", .open = gpio_open, .destroy = pif_destroy, .readmem = pif_readmem, .writemem = pif_writemem, .getregs = pif_getregs, .setregs = pif_setregs, .ctl = pif_ctl, .poll = pif_poll, .erase = pif_erase, .getconfigfuses = pif_getconfigfuses }; const struct device_class device_bp = { .name = "bus-pirate", .help = "Bus Pirate JTAG, MISO-TDO, MOSI-TDI, CS-TMS, AUX-RESET, CLK-TCK", .open = bp_open, .destroy = pif_destroy, .readmem = pif_readmem, .writemem = pif_writemem, .getregs = pif_getregs, .setregs = pif_setregs, .ctl = pif_ctl, .poll = pif_poll, .erase = pif_erase, .getconfigfuses = pif_getconfigfuses }; mspdebug-0.25/drivers/pif.h000066400000000000000000000023401313531517500156560ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * Copyright (C) 2012 Peter Bägel * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ /* Driver for parallel port interface like the Olimex MSP430-JTAG * Starting point was the goodfet driver * * 2012-10-03 Peter Bägel (DF5EQ) */ #ifndef PIF_H_ #define PIF_H_ #include "device.h" /* pif implementation */ extern const struct device_class device_pif; /* share wiht gpio implementation */ extern const struct device_class device_gpio; extern const struct device_class device_bp; #endif mspdebug-0.25/drivers/rom_bsl.c000066400000000000000000000252271313531517500165410ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009-2014 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include #include #include #include "rom_bsl.h" #include "util.h" #include "output.h" #include "bsllib.h" #include "util/sport.h" struct rom_bsl_device { struct device base; sport_t fd; const char *seq; uint8_t reply_buf[256]; int reply_len; }; #define DATA_HDR 0x80 #define DATA_ACK 0x90 #define DATA_NAK 0xA0 static int rom_bsl_ack(struct rom_bsl_device *dev) { uint8_t reply; if (sport_read_all(dev->fd, &reply, 1) < 0) { pr_error("rom_bsl: failed to receive reply"); return -1; } if (reply == DATA_NAK) { printc_err("rom_bsl: received NAK\n"); return -1; } if (reply != DATA_ACK) { printc_err("rom_bsl: bad ack character: %x\n", reply); return -1; } return 0; } static int rom_bsl_sync(struct rom_bsl_device *dev) { static const uint8_t c = DATA_HDR; int tries = 2; if (sport_flush(dev->fd) < 0) { pr_error("rom_bsl: tcflush"); return -1; } while (tries--) { if (sport_write_all(dev->fd, &c, 1) < 0) { pr_error("rom_bsl: write error"); continue; } if (!rom_bsl_ack(dev)) return 0; } printc_err("rom_bsl: sync failed\n"); return -1; } static int send_command(struct rom_bsl_device *dev, int code, uint16_t addr, const uint8_t *data, int len) { uint8_t pktbuf[256]; uint8_t cklow = 0xff; uint8_t ckhigh = 0xff; int pktlen; int evenlen = len; int i; if (len % 2 != 0) { printc_dbg("Making length even\n"); evenlen = len + 1; } pktlen = data ? evenlen + 4 : 4; if (pktlen + 6 > sizeof(pktbuf)) { printc_err("rom_bsl: payload too large: %d\n", len); return -1; } pktbuf[0] = DATA_HDR; pktbuf[1] = code; pktbuf[2] = pktlen; pktbuf[3] = pktlen; pktbuf[4] = addr & 0xff; pktbuf[5] = addr >> 8; pktbuf[6] = evenlen & 0xff; pktbuf[7] = evenlen >> 8; if (data) { memcpy(pktbuf + 8, data, len); if (len != evenlen) pktbuf[8 + len] = 0xff; } for (i = 0; i < pktlen + 4; i += 2) cklow ^= pktbuf[i]; for (i = 1; i < pktlen + 4; i += 2) ckhigh ^= pktbuf[i]; pktbuf[pktlen + 4] = cklow; pktbuf[pktlen + 5] = ckhigh; #ifdef DEBUG_ROM_BSL debug_hexdump("Send", pktbuf, pktlen + 6); #endif if (sport_write_all(dev->fd, pktbuf, pktlen + 6) < 0) { pr_error("rom_bsl: write error"); return -1; } return 0; } static int verify_checksum(struct rom_bsl_device *dev) { uint8_t cklow = 0xff; uint8_t ckhigh = 0xff; int i; for (i = 0; i < dev->reply_len; i += 2) cklow ^= dev->reply_buf[i]; for (i = 1; i < dev->reply_len; i += 2) ckhigh ^= dev->reply_buf[i]; if (cklow || ckhigh) { printc_err("rom_bsl: checksum invalid (%02x %02x)\n", cklow, ckhigh); return -1; } return 0; } static int fetch_reply(struct rom_bsl_device *dev) { dev->reply_len = 0; for (;;) { int r = sport_read(dev->fd, dev->reply_buf + dev->reply_len, sizeof(dev->reply_buf) - dev->reply_len); if (!r) { printc_err("rom_bsl: read timeout\n"); return -1; } if (r < 0) { pr_error("rom_bsl: read error"); return -1; } #ifdef DEBUG_ROM_BSL debug_hexdump("Receive", dev->reply_buf + dev->reply_len, r); #endif dev->reply_len += r; if (dev->reply_buf[0] == DATA_ACK) { return 0; } else if (dev->reply_buf[0] == DATA_HDR) { if (dev->reply_len >= 6 && dev->reply_len == dev->reply_buf[2] + 6) return verify_checksum(dev); } else if (dev->reply_buf[0] == DATA_NAK) { printc_err("rom_bsl: received NAK\n"); return -1; } else { printc_err("rom_bsl: unknown reply type: %02x\n", dev->reply_buf[0]); return -1; } if (dev->reply_len >= sizeof(dev->reply_buf)) { printc_err("rom_bsl: reply buffer overflow\n"); return -1; } } } static int rom_bsl_xfer(struct rom_bsl_device *dev, int command_code, uint16_t addr, const uint8_t *txdata, int len) { if (rom_bsl_sync(dev) < 0 || send_command(dev, command_code, addr, txdata, len) < 0 || fetch_reply(dev) < 0) { printc_err("rom_bsl: failed on command 0x%02x " "(addr = 0x%04x, len = 0x%04x)\n", command_code, addr, len); return -1; } return 0; } #define CMD_MASS_ERASE 0x18 #define CMD_ERASE_SEGMENT 0x16 #define CMD_TX_DATA 0x14 #define CMD_RX_DATA 0x12 #define CMD_TX_VERSION 0x1e #define CMD_RX_PASSWORD 0x10 static void rom_bsl_destroy(device_t dev_base) { struct rom_bsl_device *dev = (struct rom_bsl_device *)dev_base; if (bsllib_seq_do(dev->fd, bsllib_seq_next(dev->seq)) < 0) pr_error("warning: rom_bsl: exit sequence failed"); sport_close(dev->fd); free(dev); } static int rom_bsl_ctl(device_t dev_base, device_ctl_t type) { (void)dev_base; switch (type) { case DEVICE_CTL_HALT: /* Ignore halt requests */ return 0; case DEVICE_CTL_RESET: /* Ignore reset requests */ return 0; default: printc_err("rom_bsl: CPU control is not possible\n"); } return -1; } static device_status_t rom_bsl_poll(device_t dev_base) { (void)dev_base; return DEVICE_STATUS_HALTED; } static int rom_bsl_getregs(device_t dev_base, address_t *regs) { (void)dev_base; (void)regs; printc_err("rom_bsl: register fetch is not implemented\n"); return -1; } static int rom_bsl_setregs(device_t dev_base, const address_t *regs) { (void)dev_base; (void)regs; printc_err("rom_bsl: register store is not implemented\n"); return -1; } static int rom_bsl_writemem(device_t dev_base, address_t addr, const uint8_t *mem, address_t len) { struct rom_bsl_device *dev = (struct rom_bsl_device *)dev_base; if (addr >= 0x10000 || len > 0x10000 || addr + len > 0x10000) { printc_err("rom_bsl: memory write out of range\n"); return -1; } while (len) { int wlen = len > 100 ? 100 : len; int r; uint8_t memtmp[256]; const uint8_t *memptr; if (addr % 2) { printc_dbg("Memory aligning\n"); memcpy(memtmp + 1, mem, wlen); memtmp[0] = 0xff; memptr = memtmp; wlen++; len++; addr--; mem--; } else { memptr = mem; } r = rom_bsl_xfer(dev, CMD_RX_DATA, addr, memptr, wlen); if (r < 0) { printc_err("rom_bsl: failed to write to 0x%04x\n", addr); return -1; } mem += wlen; len -= wlen; addr += wlen; } return 0; } static int rom_bsl_readmem(device_t dev_base, address_t addr, uint8_t *mem, address_t len) { struct rom_bsl_device *dev = (struct rom_bsl_device *)dev_base; if (addr >= 0x10000 || len > 0x10000 || addr + len > 0x10000) { printc_err("rom_bsl: memory read out of range\n"); return -1; } while (len) { address_t count = len; int align = 0; if (addr % 2 != 0) { printc_dbg("Memory aligning\n"); count++; addr--; align = 1; } if (count > 220) count = 220; if (rom_bsl_xfer(dev, CMD_TX_DATA, addr, NULL, count) < 0) { printc_err("rom_bsl: failed to read memory\n"); return -1; } if (count > dev->reply_buf[2]) count = dev->reply_buf[2]; memcpy(mem, dev->reply_buf + 4 + align, count - align); mem += (count - align); len -= (count - align); addr += (count - align); } return 0; } static int rom_bsl_erase(device_t dev_base, device_erase_type_t type, address_t addr) { struct rom_bsl_device *dev = (struct rom_bsl_device *)dev_base; (void)addr; switch (type) { case DEVICE_ERASE_MAIN: return rom_bsl_xfer(dev, CMD_ERASE_SEGMENT, 0xfffe, NULL, 0xa504); case DEVICE_ERASE_SEGMENT: return rom_bsl_xfer(dev, CMD_ERASE_SEGMENT, addr, NULL, 0xa502); case DEVICE_ERASE_ALL: return rom_bsl_xfer(dev, CMD_MASS_ERASE, 0xfffe, NULL, 0xa506); } return 0; } static int unlock_device(struct rom_bsl_device *dev) { const static uint8_t password[32] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, }; printc_dbg("Performing mass erase...\n"); if (rom_bsl_xfer(dev, CMD_MASS_ERASE, 0xfffe, NULL, 0xa506) < 0) { printc_err("rom_bsl: initial mass erase failed\n"); return -1; } printc_dbg("Sending password...\n"); if (rom_bsl_xfer(dev, CMD_RX_PASSWORD, 0, password, sizeof(password)) < 0) { printc_err("rom_bsl: RX password failed\n"); return -1; } return 0; } static device_t rom_bsl_open(const struct device_args *args) { struct rom_bsl_device *dev; if (!(args->flags & DEVICE_FLAG_TTY)) { printc_err("rom_bsl: raw USB access is not supported"); return NULL; } dev = malloc(sizeof(*dev)); if (!dev) { pr_error("rom_bsl: can't allocate memory"); return NULL; } memset(dev, 0, sizeof(*dev)); dev->base.type = &device_rom_bsl; dev->fd = sport_open(args->path, 9600, SPORT_EVEN_PARITY); if (SPORT_ISERR(dev->fd)) { pr_error("sport_open"); free(dev); return NULL; } dev->seq = args->bsl_entry_seq; if (!dev->seq) dev->seq = "DR,r,R,r,d,R:DR,r"; if ( args->bsl_gpio_used ) { if (bsllib_seq_do_gpio(args->bsl_gpio_rts, args->bsl_gpio_dtr, dev->seq) < 0) { pr_error("rom_bsl: entry sequence failed"); goto fail; } } else { if (bsllib_seq_do(dev->fd, dev->seq) < 0) { pr_error("rom_bsl: entry sequence failed"); goto fail; } } delay_ms(500); /* Show BSL version */ if (rom_bsl_xfer(dev, CMD_TX_VERSION, 0, NULL, 0) < 0) printc_err("warning: rom_bsl: failed to read version\n"); else if (dev->reply_len < 19) printc_err("warning: rom_bsl: short reply\n"); else printc_dbg("BSL version is %x.%02x\n", dev->reply_buf[15], dev->reply_buf[16]); if (unlock_device(dev) < 0) { printc_err("rom_bsl: failed to unlock\n"); goto fail; } return (device_t)dev; fail: sport_close(dev->fd); free(dev); return NULL; } const struct device_class device_rom_bsl = { .name = "rom-bsl", .help = "ROM bootstrap loader", .open = rom_bsl_open, .destroy = rom_bsl_destroy, .readmem = rom_bsl_readmem, .writemem = rom_bsl_writemem, .erase = rom_bsl_erase, .getregs = rom_bsl_getregs, .setregs = rom_bsl_setregs, .ctl = rom_bsl_ctl, .poll = rom_bsl_poll, .getconfigfuses = NULL }; mspdebug-0.25/drivers/rom_bsl.h000066400000000000000000000017071313531517500165430ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2014 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef ROM_BSL_H_ #define ROM_BSL_H_ #include "device.h" /* MSP430 FET Bootloader implementation. */ extern const struct device_class device_rom_bsl; #endif mspdebug-0.25/drivers/sim.c000066400000000000000000000434051313531517500156720ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include #include "device.h" #include "dis.h" #include "util.h" #include "output.h" #include "sim.h" #include "simio_cpu.h" #include "ctrlc.h" #define MEM_SIZE 65536 #define MEM_IO_END 0x200 struct sim_device { struct device base; uint8_t memory[MEM_SIZE]; uint16_t regs[DEVICE_NUM_REGS]; int running; uint16_t current_insn; int watchpoint_hit; }; #define MEM_GETB(dev, offset) ((dev)->memory[offset]) #define MEM_SETB(dev, offset, value) ((dev)->memory[offset] = (value)) #define MEM_GETW(dev, offset) \ ((dev)->memory[offset] | \ ((dev)->memory[(offset + 1) & 0xffff] << 8)) #define MEM_SETW(dev, offset, value) \ do { \ (dev)->memory[offset & ~1] = (value) & 0xff; \ (dev)->memory[offset | 1] = (value) >> 8; \ } while (0); static void watchpoint_check(struct sim_device *dev, uint16_t addr, int is_write) { int i; for (i = 0; i < DEVICE_MAX_BREAKPOINTS; i++) { const struct device_breakpoint *bp = &dev->base.breakpoints[i]; if ((bp->flags & DEVICE_BP_ENABLED) && (bp->addr == addr) && ((bp->type == DEVICE_BPTYPE_WATCH || (bp->type == DEVICE_BPTYPE_READ && !is_write) || (bp->type == DEVICE_BPTYPE_WRITE && is_write)))) { printc_dbg("Watchpoint %d triggered (0x%04x, %s)\n", i, addr, is_write ? "WRITE" : "READ"); dev->watchpoint_hit = 1; return; } } } static int fetch_operand(struct sim_device *dev, int amode, int reg, int is_byte, uint16_t *addr_ret, uint32_t *data_ret) { uint16_t addr = 0; uint32_t mask = is_byte ? 0xff : 0xffff; switch (amode) { case MSP430_AMODE_REGISTER: if (reg == MSP430_REG_R3) { if (data_ret) *data_ret = 0; return 0; } if (data_ret) *data_ret = dev->regs[reg] & mask; return 0; case MSP430_AMODE_INDEXED: if (reg == MSP430_REG_R3) { if (data_ret) *data_ret = 1; return 0; } addr = MEM_GETW(dev, dev->regs[MSP430_REG_PC]); if (reg != MSP430_REG_SR) addr += dev->regs[reg]; dev->regs[MSP430_REG_PC] += 2; break; case MSP430_AMODE_INDIRECT: if (reg == MSP430_REG_SR) { if (data_ret) *data_ret = 4; return 0; } if (reg == MSP430_REG_R3) { if (data_ret) *data_ret = 2; return 0; } addr = dev->regs[reg]; break; case MSP430_AMODE_INDIRECT_INC: if (reg == MSP430_REG_SR) { if (data_ret) *data_ret = 8; return 0; } if (reg == MSP430_REG_R3) { if (data_ret) *data_ret = mask; return 0; } addr = dev->regs[reg]; dev->regs[reg] += (is_byte && reg != MSP430_REG_PC && reg != MSP430_REG_SP) ? 1 : 2; break; } if (addr_ret) *addr_ret = addr; if (data_ret) { watchpoint_check(dev, addr, 0); *data_ret = MEM_GETW(dev, addr) & mask; if (addr < MEM_IO_END) { int ret; if (is_byte) { uint8_t x = *data_ret; ret = simio_read_b(addr, &x); *data_ret = x; } else { uint16_t x = *data_ret; ret = simio_read(addr, &x); *data_ret = x; } return ret; } } return 0; } static int store_operand(struct sim_device *dev, int amode, int reg, int is_byte, uint16_t addr, uint16_t data) { if (amode == MSP430_AMODE_REGISTER) { dev->regs[reg] = is_byte ? data & 0xFF : data; return 0; } watchpoint_check(dev, addr, 1); if (is_byte) MEM_SETB(dev, addr, data); else MEM_SETW(dev, addr, data); if (addr < MEM_IO_END) { if (is_byte) return simio_write_b(addr, data); return simio_write(addr, data); } return 0; } #define ARITH_BITS (MSP430_SR_V | MSP430_SR_N | MSP430_SR_Z | MSP430_SR_C) static int step_double(struct sim_device *dev, uint16_t ins) { uint16_t opcode = ins & 0xf000; int sreg = (ins >> 8) & 0xf; int amode_dst = (ins >> 7) & 1; int is_byte = ins & 0x0040; int amode_src = (ins >> 4) & 0x3; int dreg = ins & 0x000f; uint32_t src_data; uint16_t dst_addr = 0; uint32_t dst_data; uint32_t res_data; uint32_t msb = is_byte ? 0x80 : 0x8000; uint32_t mask = is_byte ? 0xff : 0xffff; uint32_t shiftMask = 0x000f; uint32_t i = 0; int cycles; if (amode_dst == MSP430_AMODE_REGISTER && dreg == MSP430_REG_PC) { if (amode_src == MSP430_AMODE_REGISTER || amode_src == MSP430_AMODE_INDIRECT) cycles = 2; else cycles = 3; } else if (sreg == MSP430_REG_SR || sreg == MSP430_REG_R3) { if (amode_dst == MSP430_AMODE_REGISTER) cycles = 1; else cycles = 4; } else { if (amode_src == MSP430_AMODE_INDIRECT || amode_src == MSP430_AMODE_INDIRECT_INC) cycles = 2; else if (amode_src == MSP430_AMODE_INDEXED) cycles = 3; else cycles = 1; if (amode_dst == MSP430_AMODE_INDEXED) cycles += 3; } if (fetch_operand(dev, amode_src, sreg, is_byte, NULL, &src_data) < 0) return -1; if (fetch_operand(dev, amode_dst, dreg, is_byte, &dst_addr, opcode == MSP430_OP_MOV ? NULL : &dst_data) < 0) return -1; switch (opcode) { case MSP430_OP_MOV: res_data = src_data; break; case MSP430_OP_SUB: case MSP430_OP_SUBC: case MSP430_OP_CMP: src_data = (~src_data) & mask; case MSP430_OP_ADD: case MSP430_OP_ADDC: if (opcode == MSP430_OP_ADDC || opcode == MSP430_OP_SUBC) res_data = (dev->regs[MSP430_REG_SR] & MSP430_SR_C) ? 1 : 0; else if (opcode == MSP430_OP_SUB || opcode == MSP430_OP_CMP) res_data = 1; else res_data = 0; res_data += src_data; res_data += dst_data; dev->regs[MSP430_REG_SR] &= ~ARITH_BITS; if (!(res_data & mask)) dev->regs[MSP430_REG_SR] |= MSP430_SR_Z; if (res_data & msb) dev->regs[MSP430_REG_SR] |= MSP430_SR_N; if (res_data & (msb << 1)) dev->regs[MSP430_REG_SR] |= MSP430_SR_C; if (!((src_data ^ dst_data) & msb) && (src_data ^ res_data) & msb) dev->regs[MSP430_REG_SR] |= MSP430_SR_V; break; case MSP430_OP_DADD: res_data = 0; if (dev->regs[MSP430_REG_SR] & MSP430_SR_C) res_data++; shiftMask = 0x000f; for(i = 0; i < 4; ++i) { res_data += (src_data & shiftMask) + (dst_data & shiftMask); if( (res_data & (0x1f << (i*4))) > (9 << (i*4))) res_data += 6 << (i*4); shiftMask = shiftMask << 4; } dev->regs[MSP430_REG_SR] &= ~ARITH_BITS; if (!(res_data & mask)) dev->regs[MSP430_REG_SR] |= MSP430_SR_Z; if (res_data & msb) dev->regs[MSP430_REG_SR] |= MSP430_SR_N; if (res_data & (msb << 1)) dev->regs[MSP430_REG_SR] |= MSP430_SR_C; break; case MSP430_OP_BIT: case MSP430_OP_AND: res_data = src_data & dst_data; dev->regs[MSP430_REG_SR] &= ~ARITH_BITS; dev->regs[MSP430_REG_SR] |= (res_data & mask) ? MSP430_SR_C : MSP430_SR_Z; if (res_data & msb) dev->regs[MSP430_REG_SR] |= MSP430_SR_N; break; case MSP430_OP_BIC: res_data = dst_data & ~src_data; break; case MSP430_OP_BIS: res_data = dst_data | src_data; break; case MSP430_OP_XOR: res_data = dst_data ^ src_data; dev->regs[MSP430_REG_SR] &= ~ARITH_BITS; dev->regs[MSP430_REG_SR] |= (res_data & mask) ? MSP430_SR_C : MSP430_SR_Z; if (res_data & msb) dev->regs[MSP430_REG_SR] |= MSP430_SR_N; if (src_data & dst_data & msb) dev->regs[MSP430_REG_SR] |= MSP430_SR_V; break; default: printc_err("sim: invalid double-operand opcode: " "0x%04x (PC = 0x%04x)\n", opcode, dev->current_insn); return -1; } if (opcode != MSP430_OP_CMP && opcode != MSP430_OP_BIT && store_operand(dev, amode_dst, dreg, is_byte, dst_addr, res_data) < 0) return -1; return cycles; } static int step_single(struct sim_device *dev, uint16_t ins) { uint16_t opcode = ins & 0xff80; int is_byte = ins & 0x0040; int amode = (ins >> 4) & 0x3; int reg = ins & 0x000f; uint16_t msb = is_byte ? 0x80 : 0x8000; uint32_t mask = is_byte ? 0xff : 0xffff; uint16_t src_addr = 0; uint32_t src_data; uint32_t res_data = 0; int cycles = 1; if (fetch_operand(dev, amode, reg, is_byte, &src_addr, &src_data) < 0) return -1; if (amode == MSP430_AMODE_INDEXED) cycles = 4; else if (amode == MSP430_AMODE_REGISTER) cycles = 1; else cycles = 3; switch (opcode) { case MSP430_OP_RRC: case MSP430_OP_RRA: res_data = (src_data >> 1) & ~msb; if (opcode == MSP430_OP_RRC) { if (dev->regs[MSP430_REG_SR] & MSP430_SR_C) res_data |= msb; } else { res_data |= src_data & msb; } dev->regs[MSP430_REG_SR] &= ~ARITH_BITS; if (!(res_data & mask)) dev->regs[MSP430_REG_SR] |= MSP430_SR_Z; if (res_data & msb) dev->regs[MSP430_REG_SR] |= MSP430_SR_N; if (src_data & 1) dev->regs[MSP430_REG_SR] |= MSP430_SR_C; break; case MSP430_OP_SWPB: res_data = ((src_data & 0xff) << 8) | ((src_data >> 8) & 0xff); break; case MSP430_OP_SXT: res_data = src_data & 0xff; dev->regs[MSP430_REG_SR] &= ~ARITH_BITS; if (src_data & 0x80) { res_data |= 0xff00; dev->regs[MSP430_REG_SR] |= MSP430_SR_N; } dev->regs[MSP430_REG_SR] |= (res_data & mask) ? MSP430_SR_C : MSP430_SR_Z; break; case MSP430_OP_PUSH: dev->regs[MSP430_REG_SP] -= 2; MEM_SETW(dev, dev->regs[MSP430_REG_SP], src_data); if (amode == MSP430_AMODE_REGISTER) cycles = 3; else if (amode == MSP430_AMODE_INDIRECT || (amode == MSP430_AMODE_INDIRECT_INC && reg == MSP430_REG_PC)) cycles = 4; else cycles = 5; break; case MSP430_OP_CALL: dev->regs[MSP430_REG_SP] -= 2; MEM_SETW(dev, dev->regs[MSP430_REG_SP], dev->regs[MSP430_REG_PC]); dev->regs[MSP430_REG_PC] = src_data; if (amode == MSP430_AMODE_REGISTER || amode == MSP430_AMODE_INDIRECT) cycles = 4; else cycles = 5; break; case MSP430_OP_RETI: dev->regs[MSP430_REG_SR] = MEM_GETW(dev, dev->regs[MSP430_REG_SP]); dev->regs[MSP430_REG_SP] += 2; dev->regs[MSP430_REG_PC] = MEM_GETW(dev, dev->regs[MSP430_REG_SP]); dev->regs[MSP430_REG_SP] += 2; cycles = 5; break; default: printc_err("sim: unknown single-operand opcode: 0x%04x " "(PC = 0x%04x)\n", opcode, dev->current_insn); return -1; } if (opcode != MSP430_OP_PUSH && opcode != MSP430_OP_CALL && opcode != MSP430_OP_RETI && store_operand(dev, amode, reg, is_byte, src_addr, res_data) < 0) return -1; return cycles; } static int step_jump(struct sim_device *dev, uint16_t ins) { uint16_t opcode = ins & 0xfc00; uint16_t pc_offset = (ins & 0x03ff) << 1; uint16_t sr = dev->regs[MSP430_REG_SR]; if (pc_offset & 0x0400) pc_offset |= 0xff800; switch (opcode) { case MSP430_OP_JNZ: sr = !(sr & MSP430_SR_Z); break; case MSP430_OP_JZ: sr &= MSP430_SR_Z; break; case MSP430_OP_JNC: sr = !(sr & MSP430_SR_C); break; case MSP430_OP_JC: sr &= MSP430_SR_C; break; case MSP430_OP_JN: sr &= MSP430_SR_N; break; case MSP430_OP_JGE: sr = ((sr & MSP430_SR_N) ? 1 : 0) == ((sr & MSP430_SR_V) ? 1 : 0); break; case MSP430_OP_JL: sr = ((sr & MSP430_SR_N) ? 1 : 0) != ((sr & MSP430_SR_V) ? 1 : 0); break; case MSP430_OP_JMP: sr = 1; break; } if (sr) dev->regs[MSP430_REG_PC] += pc_offset; return 2; } /* Fetch and execute one instruction. Return the number of CPU cycles * it would have taken, or -1 if an error occurs. */ static int step_cpu(struct sim_device *dev) { uint16_t ins; int ret; /* Fetch the instruction */ dev->current_insn = dev->regs[MSP430_REG_PC]; ins = MEM_GETW(dev, dev->current_insn); dev->regs[MSP430_REG_PC] += 2; /* Handle different instruction types */ if ((ins & 0xf000) >= 0x4000) ret = step_double(dev, ins); else if ((ins & 0xf000) >= 0x2000) ret = step_jump(dev, ins); else ret = step_single(dev, ins); /* If things went wrong, restart at the current instruction */ if (ret < 0) dev->regs[MSP430_REG_PC] = dev->current_insn; return ret; } static void do_reset(struct sim_device *dev) { simio_step(dev->regs[MSP430_REG_SR], 4); memset(dev->regs, 0, sizeof(dev->regs)); dev->regs[MSP430_REG_PC] = MEM_GETW(dev, 0xfffe); dev->regs[MSP430_REG_SR] = 0; simio_reset(); } static int step_system(struct sim_device *dev) { int count = 1; int irq; uint16_t status = dev->regs[MSP430_REG_SR]; irq = simio_check_interrupt(); if (irq == 15) { do_reset(dev); return 0; } else if (((status & MSP430_SR_GIE) && irq >= 0) || irq >= 14) { if (irq >= 16) { printc_err("sim: invalid interrupt number: %d\n", irq); return -1; } dev->regs[MSP430_REG_SP] -= 2; MEM_SETW(dev, dev->regs[MSP430_REG_SP], dev->regs[MSP430_REG_PC]); dev->regs[MSP430_REG_SP] -= 2; MEM_SETW(dev, dev->regs[MSP430_REG_SP], dev->regs[MSP430_REG_SR]); dev->regs[MSP430_REG_SR] &= ~(MSP430_SR_GIE | MSP430_SR_CPUOFF); dev->regs[MSP430_REG_PC] = MEM_GETW(dev, 0xffe0 + irq * 2); simio_ack_interrupt(irq); count = 6; } else if (!(status & MSP430_SR_CPUOFF)) { count = step_cpu(dev); if (count < 0) return -1; } simio_step(status, count); return 0; } /************************************************************************ * Device interface */ static void sim_destroy(device_t dev_base) { free(dev_base); } static int sim_readmem(device_t dev_base, address_t addr, uint8_t *mem, address_t len) { struct sim_device *dev = (struct sim_device *)dev_base; if (addr > MEM_SIZE || (addr + len) < addr || (addr + len) > MEM_SIZE) { printc_err("sim: memory read out of range\n"); return -1; } if (addr + len > MEM_SIZE) len = MEM_SIZE - addr; /* Read byte IO addresses */ while (len && (addr < 0x100)) { simio_read_b(addr, mem); mem++; len--; addr++; } /* Read word IO addresses */ while (len > 2 && (addr < 0x200)) { uint16_t data = 0; simio_read(addr, &data); mem[0] = data & 0xff; mem[1] = data >> 8; mem += 2; len -= 2; addr += 2; } memcpy(mem, dev->memory + addr, len); return 0; } static int sim_writemem(device_t dev_base, address_t addr, const uint8_t *mem, address_t len) { struct sim_device *dev = (struct sim_device *)dev_base; if (addr > MEM_SIZE || (addr + len) < addr || (addr + len) > MEM_SIZE) { printc_err("sim: memory write out of range\n"); return -1; } /* Write byte IO addresses */ while (len && (addr < 0x100)) { simio_write_b(addr, *mem); mem++; len--; addr++; } /* Write word IO addresses */ while (len > 2 && (addr < 0x200)) { simio_write(addr, ((uint16_t)mem[1] << 8) | mem[0]); mem += 2; len -= 2; addr += 2; } memcpy(dev->memory + addr, mem, len); return 0; } static int sim_getregs(device_t dev_base, address_t *regs) { struct sim_device *dev = (struct sim_device *)dev_base; int i; for (i = 0; i < DEVICE_NUM_REGS; i++) regs[i] = dev->regs[i]; return 0; } static int sim_setregs(device_t dev_base, const address_t *regs) { struct sim_device *dev = (struct sim_device *)dev_base; int i; for (i = 0; i < DEVICE_NUM_REGS; i++) dev->regs[i] = regs[i]; return 0; } static int sim_ctl(device_t dev_base, device_ctl_t op) { struct sim_device *dev = (struct sim_device *)dev_base; switch (op) { case DEVICE_CTL_RESET: do_reset(dev); return 0; case DEVICE_CTL_HALT: dev->running = 0; return 0; case DEVICE_CTL_STEP: return step_system(dev); case DEVICE_CTL_RUN: dev->running = 1; return 0; default: printc_err("sim: unsupported operation\n"); return -1; } return 0; } static int sim_erase(device_t dev_base, device_erase_type_t type, address_t addr) { struct sim_device *dev = (struct sim_device *)dev_base; switch (type) { case DEVICE_ERASE_MAIN: memset(dev->memory + 0x2000, 0xff, MEM_SIZE - 0x2000); break; case DEVICE_ERASE_ALL: memset(dev->memory, 0xff, MEM_SIZE); break; case DEVICE_ERASE_SEGMENT: addr &= ~0x3f; addr &= (MEM_SIZE - 1); memset(dev->memory + addr, 0xff, 64); break; } return 0; } static device_status_t sim_poll(device_t dev_base) { struct sim_device *dev = (struct sim_device *)dev_base; int count = 1000000; if (!dev->running) return DEVICE_STATUS_HALTED; dev->watchpoint_hit = 0; while (count > 0) { int i; for (i = 0; i < dev->base.max_breakpoints; i++) { struct device_breakpoint *bp = &dev->base.breakpoints[i]; if ((bp->flags & DEVICE_BP_ENABLED) && (bp->type == DEVICE_BPTYPE_BREAK) && dev->regs[MSP430_REG_PC] == bp->addr) { dev->running = 0; return DEVICE_STATUS_HALTED; } } if (step_system(dev) < 0) { dev->running = 0; return DEVICE_STATUS_ERROR; } if (dev->watchpoint_hit) { dev->running = 0; return DEVICE_STATUS_HALTED; } if (ctrlc_check()) return DEVICE_STATUS_INTR; count--; } return DEVICE_STATUS_RUNNING; } static device_t sim_open(const struct device_args *args) { struct sim_device *dev = malloc(sizeof(*dev)); (void)args; if (!dev) { pr_error("can't allocate memory for simulation"); return NULL; } memset(dev, 0, sizeof(*dev)); dev->base.type = &device_sim; dev->base.max_breakpoints = DEVICE_MAX_BREAKPOINTS; memset(dev->memory, 0xff, sizeof(dev->memory)); memset(dev->regs, 0xff, sizeof(dev->regs)); dev->running = 0; dev->current_insn = 0; printc_dbg("Simulation started, 0x%x bytes of RAM\n", MEM_SIZE); return (device_t)dev; } const struct device_class device_sim = { .name = "sim", .help = "Simulation mode.", .open = sim_open, .destroy = sim_destroy, .readmem = sim_readmem, .writemem = sim_writemem, .erase = sim_erase, .getregs = sim_getregs, .setregs = sim_setregs, .ctl = sim_ctl, .poll = sim_poll, .getconfigfuses = NULL }; mspdebug-0.25/drivers/sim.h000066400000000000000000000016671313531517500157030ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef SIM_H_ #define SIM_H_ #include "device.h" /* Dummy/simulation implementation. */ extern const struct device_class device_sim; #endif mspdebug-0.25/drivers/tilib.c000066400000000000000000000353141313531517500162050ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2011 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include "output.h" #include "tilib.h" #include "tilib_api.h" #include "thread.h" #include "ctrlc.h" #include "opdb.h" struct tilib_device { struct device base; thread_lock_t mb_lock; uint32_t mailbox; uint16_t bp_handles[DEVICE_MAX_BREAKPOINTS]; char uifPath[1024]; fperm_t active_fperm; }; static struct tilib_device *client_handle; #define MID_SINGLE_STEP 0x01 #define MID_BREAKPOINT 0x02 #define MID_STORAGE 0x04 #define MID_STATE 0x08 #define MID_WARNING 0x10 #define MID_CPU_STOPPED 0x20 #define MID_HALT_ANY (MID_BREAKPOINT | MID_CPU_STOPPED) static const MessageID_t my_message_ids = { .uiMsgIdSingleStep = MID_SINGLE_STEP, .uiMsgIdBreakpoint = MID_BREAKPOINT, .uiMsgIdStorage = MID_STORAGE, .uiMsgIdState = MID_STATE, .uiMsgIdWarning = MID_WARNING, .uiMsgIdCPUStopped = MID_CPU_STOPPED }; static void event_notify(unsigned int msg_id, unsigned int w_param, long l_param, long client_handle_unused) { (void)w_param; (void)l_param; (void)client_handle_unused; thread_lock_acquire(&client_handle->mb_lock); client_handle->mailbox |= msg_id; thread_lock_release(&client_handle->mb_lock); } static uint32_t event_fetch(struct tilib_device *dev) { uint32_t ret; thread_lock_acquire(&dev->mb_lock); ret = dev->mailbox; dev->mailbox = 0; thread_lock_release(&dev->mb_lock); return ret; } static void report_error(struct tilib_device *dev, const char *what) { long err = tilib_api->MSP430_Error_Number(); const char *desc = tilib_api->MSP430_Error_String(err); printc_err("tilib: %s: %s (error = %ld)\n", what, desc, err); } static int refresh_fperm(struct tilib_device *dev) { fperm_t fp = opdb_read_fperm(); fperm_t delta = dev->active_fperm ^ fp; if (delta & FPERM_LOCKED_FLASH) { int opt = (fp & FPERM_LOCKED_FLASH) ? 1 : 0; printc_dbg("%s locked flash access\n", opt ? "Enabling" : "Disabling"); if (tilib_api->MSP430_Configure (LOCKED_FLASH_ACCESS, opt) < 0) { report_error(dev, "MSP430_Configure " "(LOCKED_FLASH_ACCESS)\n"); return -1; } } if (delta & FPERM_BSL) { int opt = (fp & FPERM_BSL) ? 1 : 0; printc_dbg("%s BSL access\n", opt ? "Enabling" : "Disabling"); if (tilib_api->MSP430_Configure (UNLOCK_BSL_MODE, opt) < 0) { report_error(dev, "MSP430_Configure " "(UNLOCK_BSL_MODE)\n"); return -1; } } dev->active_fperm = fp; return 0; } static int tilib_readmem(device_t dev_base, address_t addr, uint8_t *mem, address_t len) { struct tilib_device *dev = (struct tilib_device *)dev_base; if (tilib_api->MSP430_Memory(addr, (char *)mem, len, READ) < 0) { report_error(dev, "MSP430_Memory"); return -1; } return 0; } static int tilib_writemem(device_t dev_base, address_t addr, const uint8_t *mem, address_t len) { struct tilib_device *dev = (struct tilib_device *)dev_base; refresh_fperm(dev); if (tilib_api->MSP430_Memory(addr, (char *)mem, len, WRITE) < 0) { report_error(dev, "MSP430_Memory"); return -1; } return 0; } static long ti_erase_type(device_erase_type_t e) { switch (e) { case DEVICE_ERASE_ALL: return ERASE_ALL; case DEVICE_ERASE_MAIN: return ERASE_MAIN; case DEVICE_ERASE_SEGMENT: return ERASE_SEGMENT; } return 0; } static int tilib_erase(device_t dev_base, device_erase_type_t type, address_t address) { struct tilib_device *dev = (struct tilib_device *)dev_base; if (type == DEVICE_ERASE_MAIN) address = 0xfffe; refresh_fperm(dev); /* We need to pass a non-zero length if we've selected segment * erase. */ if (tilib_api->MSP430_Erase(ti_erase_type(type), address, 1) < 0) { report_error(dev, "MSP430_Erase"); return -1; } return 0; } static int tilib_getregs(device_t dev_base, address_t *regs) { struct tilib_device *dev = (struct tilib_device *)dev_base; long regbuf[DEVICE_NUM_REGS]; int i; if (tilib_api->MSP430_Registers(regbuf, 0xffff, READ) < 0) { report_error(dev, "MSP430_Registers"); return -1; } for (i = 0; i < DEVICE_NUM_REGS; i++) regs[i] = regbuf[i]; return 0; } static int tilib_setregs(device_t dev_base, const address_t *regs) { struct tilib_device *dev = (struct tilib_device *)dev_base; long regbuf[DEVICE_NUM_REGS]; int i; for (i = 0; i < DEVICE_NUM_REGS; i++) regbuf[i] = regs[i]; if (tilib_api->MSP430_Registers(regbuf, 0xffff, WRITE) < 0) { report_error(dev, "MSP430_Registers"); return -1; } return 0; } static void load_break(BpParameter_t *param, address_t addr) { param->bpMode = BP_CODE; param->lAddrVal = addr; param->bpType = BP_MAB; param->lReg = 0; /* not used */ param->bpAccess = BP_FETCH; param->bpAction = BP_BRK; param->bpOperat = BP_EQUAL; param->lMask = 0; /* what's this? */ param->lRangeEndAdVa = 0; /* not used */ param->bpRangeAction = 0; /* not used */ param->bpCondition = BP_NO_COND; param->lCondMdbVal = 0; param->bpCondAccess = BP_FETCH; param->lCondMask = 0; /* what's this? */ param->bpCondOperat = BP_EQUAL; param->wExtCombine = 0; /* not used? */ } static void load_complex(BpParameter_t *param, address_t addr, BpAccess_t acc) { param->bpMode = BP_COMPLEX; param->lAddrVal = addr; param->bpType = BP_MAB; param->lReg = 0; /* not used (only for register-write) */ param->bpAccess = acc; param->bpAction = BP_BRK; param->bpOperat = BP_EQUAL; param->lMask = 0xffffff; param->lRangeEndAdVa = 0; /* not used */ param->bpRangeAction = 0; /* not used */ param->bpCondition = BP_NO_COND; param->lCondMdbVal = 0; param->bpCondAccess = acc; param->lCondMask = 0; /* what's this? */ param->bpCondOperat = BP_EQUAL; param->wExtCombine = 0; /* not used? */ } static int refresh_bps(struct tilib_device *dev) { int i; for (i = 0; i < dev->base.max_breakpoints; i++) { struct device_breakpoint *bp = &dev->base.breakpoints[i]; BpParameter_t param = {0}; if (!(bp->flags & DEVICE_BP_DIRTY)) continue; if (bp->flags & DEVICE_BP_ENABLED) { switch (bp->type) { case DEVICE_BPTYPE_BREAK: load_break(¶m, bp->addr); break; case DEVICE_BPTYPE_WATCH: load_complex(¶m, bp->addr, BP_NO_FETCH); break; case DEVICE_BPTYPE_READ: load_complex(¶m, bp->addr, BP_READ_DMA); break; case DEVICE_BPTYPE_WRITE: load_complex(¶m, bp->addr, BP_WRITE_DMA); break; } } else if (!dev->bp_handles[i]) { bp->flags &= ~DEVICE_BP_DIRTY; continue; } else { param.bpMode = BP_CLEAR; } if (tilib_api->MSP430_EEM_SetBreakpoint (&dev->bp_handles[i], ¶m) < 0) { report_error(dev, "MSP430_EEM_SetBreakpoint"); return -1; } bp->flags &= ~DEVICE_BP_DIRTY; } return 0; } static int do_halt(struct tilib_device *dev) { long state; long cycles; if (tilib_api->MSP430_State(&state, 1, &cycles) < 0) { report_error(dev, "MSP430_State"); return -1; } /* Is this a blocking call? */ return 0; } static int do_step(struct tilib_device *dev) { if (tilib_api->MSP430_Run(SINGLE_STEP, 0) < 0) { report_error(dev, "MSP430_Run"); return -1; } return 0; } static int tilib_ctl(device_t dev_base, device_ctl_t op) { struct tilib_device *dev = (struct tilib_device *)dev_base; switch (op) { case DEVICE_CTL_RESET: if (tilib_api->MSP430_Reset(RST_RESET, 0, 0) < 0) { report_error(dev, "MSP430_Reset"); return -1; } return 0; case DEVICE_CTL_RUN: if (refresh_bps(dev) < 0) return -1; if (tilib_api->MSP430_Run(RUN_TO_BREAKPOINT, 0) < 0) { report_error(dev, "MSP430_Run"); return -1; } break; case DEVICE_CTL_HALT: return do_halt(dev); case DEVICE_CTL_STEP: return do_step(dev); case DEVICE_CTL_SECURE: if (tilib_api->MSP430_Secure() < 0) { report_error(dev, "MSP430_Secure"); return -1; } return 0; } return 0; } static device_status_t tilib_poll(device_t dev_base) { struct tilib_device *dev = (struct tilib_device *)dev_base; if (delay_ms(50) < 0) return DEVICE_STATUS_INTR; if (event_fetch(dev) & MID_HALT_ANY) return DEVICE_STATUS_HALTED; return DEVICE_STATUS_RUNNING; } static void tilib_destroy(device_t dev_base) { struct tilib_device *dev = (struct tilib_device *)dev_base; printc_dbg("MSP430_Run\n"); if (tilib_api->MSP430_Run(FREE_RUN, 1) < 0) report_error(dev, "MSP430_Run"); printc_dbg("MSP430_Close\n"); tilib_api->MSP430_Close(0); tilib_api_exit(); thread_lock_destroy(&dev->mb_lock); free(dev); } static void fw_progress(unsigned int msg_id, unsigned long w_param, unsigned long l_param, long client_handle_unused) { (void)l_param; (void)client_handle_unused; switch (msg_id) { case BL_DATA_BLOCK_PROGRAMMED: if (w_param > 100) w_param = 100; printc(" %3lu percent done\n", w_param); break; case BL_UPDATE_ERROR: report_error(client_handle, "BL_UPDATE_ERROR"); break; case BL_WAIT_FOR_TIMEOUT: printc("Waiting for bootloader to timeout...\n"); break; case BL_INIT: printc("Initializing bootloader...\n"); break; case BL_ERASE_INT_VECTORS: printc("Erasing interrupt vectors...\n"); break; case BL_ERASE_FIRMWARE: printc("Erasing firmware...\n"); break; case BL_PROGRAM_FIRMWARE: printc("Programming new firmware...\n"); break; case BL_EXIT: printc("Done, finishing...\n"); break; case BL_UPDATE_DONE: printc("Update complete\n"); break; } } static int do_fw_update(struct tilib_device *dev, const char *filename) { printc("Starting firmware update (this may take some time)...\n"); if (tilib_api->MSP430_FET_FwUpdate((char *)filename, fw_progress, (long)dev) < 0) { report_error(dev, "MSP430_FET_FwUpdate"); return -1; } return 0; } static int do_init(struct tilib_device *dev, const struct device_args *args) { long version; union DEVICE_T device; printc_dbg("MSP430_Initialize: %s\n", dev->uifPath); if (tilib_api->MSP430_Initialize(dev->uifPath, &version) < 0) { report_error(dev, "MSP430_Initialize"); return -1; } if (args->require_fwupdate) { printc("Updating firmware using %s\n", args->require_fwupdate); if (do_fw_update(dev, args->require_fwupdate) < 0) { tilib_api->MSP430_Close(0); return -1; } } else if (version < 0) { printc("FET firmware update is required.\n"); if (args->flags & DEVICE_FLAG_DO_FWUPDATE) { if (do_fw_update(dev, NULL) < 0) { tilib_api->MSP430_Close(0); return -1; } } else { printc("Re-run with --allow-fw-update to perform " "a firmware update.\n"); tilib_api->MSP430_Close(0); return -1; } } else { printc_dbg("Firmware version is %ld\n", version); } printc_dbg("MSP430_VCC: %d mV\n", args->vcc_mv); if (tilib_api->MSP430_VCC(args->vcc_mv) < 0) { report_error(dev, "MSP430_VCC"); tilib_api->MSP430_Close(0); return -1; } /* Without this delay, MSP430_OpenDevice will often hang. */ delay_s(1); printc_dbg("MSP430_OpenDevice\n"); if (tilib_api->MSP430_OpenDevice("DEVICE_UNKNOWN", "", 0, 0, 0) < 0) { report_error(dev, "MSP430_OpenDevice"); tilib_api->MSP430_Close(0); return -1; } printc_dbg("MSP430_GetFoundDevice\n"); if (tilib_api->MSP430_GetFoundDevice(device.buffer, sizeof(device.buffer)) < 0) { report_error(dev, "MSP430_GetFoundDevice"); tilib_api->MSP430_Close(0); return -1; } printc_dbg("Device: %s (id = 0x%04x)\n", device.string, device.id); printc_dbg("%d breakpoints available\n", device.nBreakpoints); dev->base.max_breakpoints = device.nBreakpoints; if (dev->base.max_breakpoints > DEVICE_MAX_BREAKPOINTS) dev->base.max_breakpoints = DEVICE_MAX_BREAKPOINTS; printc_dbg("MSP430_EEM_Init\n"); thread_lock_init(&dev->mb_lock); if (tilib_api->MSP430_EEM_Init(event_notify, (long)dev, (MessageID_t *)&my_message_ids) < 0) { report_error(dev, "MSP430_EEM_Init"); tilib_api->MSP430_Close(0); thread_lock_destroy(&dev->mb_lock); return -1; } return 0; } static int do_findUif(struct tilib_device *dev) { // Find the first uif and store the path name into dev->uifPath long attachedUifCount = 0; long uifIndex = 0; printc_dbg("MSP430_GetNumberOfUsbIfs\n"); if (tilib_api->MSP430_GetNumberOfUsbIfs(&attachedUifCount) < 0) { report_error(dev, "MSP430_GetNumberOfUsbIfs"); return -1; } for (uifIndex = 0; uifIndex < attachedUifCount; uifIndex++) { char *name = NULL; long status = 0; printc_dbg("MSP430_GetNameOfUsbIf\n"); if (tilib_api->MSP430_GetNameOfUsbIf(uifIndex, &name, &status) < 0) { report_error(dev, "MSP430_GetNameOfUsbIf"); return -1; } if (status == 0) /* status == 1 when fet is in use */ { // This fet is unused strncpy(dev->uifPath, name, sizeof(dev->uifPath)); printc_dbg("Found FET: %s\n", dev->uifPath); return 0; } } printc_err("No unused FET found.\n"); return -1; } static device_t tilib_open(const struct device_args *args) { struct tilib_device *dev; dev = malloc(sizeof(*dev)); if (!dev) { printc_err("tilib: can't allocate memory: %s\n", last_error()); return NULL; } memset(dev, 0, sizeof(*dev)); dev->base.type = &device_tilib; if (tilib_api_init() < 0) { free(dev); return NULL; } client_handle = dev; /* Copy the args->path to the dev->uifPath buffer * we may need to change it for automatic detection, and * not sure if the path is actually modified by MSP430_Initialize, * but the argument isn't const, so probably safest to copy it. */ if ((args->flags & DEVICE_FLAG_TTY)) { strncpy(dev->uifPath, args->path, sizeof(dev->uifPath)); dev->uifPath[sizeof(dev->uifPath) - 1] = 0; } else { // No path was supplied, use the first UIF we can find if (do_findUif(dev) < 0) { tilib_api_exit(); free(dev); return NULL; } } if (do_init(dev, args) < 0) { printc_err("tilib: device initialization failed\n"); tilib_api_exit(); free(dev); return NULL; } return (device_t)dev; } const struct device_class device_tilib = { .name = "tilib", .help = "TI MSP430 library", .open = tilib_open, .destroy = tilib_destroy, .readmem = tilib_readmem, .writemem = tilib_writemem, .erase = tilib_erase, .getregs = tilib_getregs, .setregs = tilib_setregs, .ctl = tilib_ctl, .poll = tilib_poll, .getconfigfuses = NULL }; mspdebug-0.25/drivers/tilib.h000066400000000000000000000017051313531517500162070ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2011 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef TILIB_H_ #define TILIB_H_ #include "device.h" /* TI MSP430.DLL/libmsp430.so implementation */ extern const struct device_class device_tilib; #endif mspdebug-0.25/drivers/tilib_api.c000066400000000000000000000516141313531517500170370ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2015 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include "util/output.h" #include "tilib_api.h" #include "dynload.h" static dynload_handle_t lib_handle; const struct tilib_api_table *tilib_api; #if defined(__Windows__) || defined(__CYGWIN__) static const char tilib_filename[] = "MSP430.DLL"; #define TIDLL __stdcall #else static const char tilib_filename[] = "libmsp430.so"; #define TIDLL #endif static void *get_func(const char *name) { void *ret = dynload_sym(lib_handle, name); if (!ret) { printc_err("tilib_api: can't find symbol \"%s\": %s\n", name, dynload_error()); return NULL; } return ret; } /************************************************************************ * New API (post-SLAC460L) */ struct new_messageid { uint32_t uiMsgIdSingleStep; uint32_t uiMsgIdBreakpoint; uint32_t uiMsgIdStorage; uint32_t uiMsgIdState; uint32_t uiMsgIdWarning; uint32_t uiMsgIdCPUStopped; }; static void o2n_messageid(struct new_messageid *dst, const MessageID_t *src) { dst->uiMsgIdSingleStep = src->uiMsgIdSingleStep; dst->uiMsgIdBreakpoint = src->uiMsgIdBreakpoint; dst->uiMsgIdStorage = src->uiMsgIdStorage; dst->uiMsgIdState = src->uiMsgIdState; dst->uiMsgIdWarning = src->uiMsgIdWarning; dst->uiMsgIdCPUStopped = src->uiMsgIdCPUStopped; } struct new_breakpoint { BpMode_t bpMode; int32_t lAddrVal; BpType_t bpType; int32_t lReg; BpAccess_t bpAccess; BpAction_t bpAction; BpOperat_t bpOperat; int32_t lMask; int32_t lRangeEndAdVa; BpRangeAction_t bpRangeAction; BpCondition_t bpCondition; uint32_t lCondMdbVal; BpAccess_t bpCondAccess; int32_t lCondMask; BpOperat_t bpCondOperat; uint16_t wExtCombine; }; static void o2n_breakpoint(struct new_breakpoint *dst, const BpParameter_t *src) { dst->bpMode = src->bpMode; dst->lAddrVal = src->lAddrVal; dst->bpType = src->bpType; dst->lReg = src->lReg; dst->bpAccess = src->bpAccess; dst->bpAction = src->bpAction; dst->bpOperat = src->bpOperat; dst->lMask = src->lMask; dst->lRangeEndAdVa = src->lRangeEndAdVa; dst->bpRangeAction = src->bpRangeAction; dst->bpCondition = src->bpCondition; dst->lCondMdbVal = src->lCondMdbVal; dst->bpCondAccess = src->bpCondAccess; dst->lCondMask = src->lCondMask; dst->bpCondOperat = src->bpCondOperat; dst->wExtCombine = src->wExtCombine; } union new_device { uint8_t buffer[112]; struct { uint16_t endian; uint16_t id; uint8_t string[32]; uint16_t mainStart; uint16_t infoStart; uint16_t ramEnd; uint16_t nBreakpoints; uint16_t emulation; uint16_t clockControl; uint16_t lcdStart; uint16_t lcdEnd; uint16_t vccMinOp; uint16_t vccMaxOp; uint16_t hasTestVpp; uint16_t ramStart; uint16_t ram2Start; uint16_t ram2End; uint16_t infoEnd; uint32_t mainEnd; uint16_t bslStart; uint16_t bslEnd; uint16_t nRegTrigger; uint16_t nCombinations; uint8_t cpuArch; uint8_t jtagId; uint16_t coreIpId; uint32_t deviceIdPtr; uint16_t eemVersion; uint16_t nBreakpointsOptions; uint16_t nBreakpointsReadWrite; uint16_t nBreakpointsDma; uint16_t TrigerMask; uint16_t nRegTriggerOperations; uint16_t nStateStorage; uint16_t nCycleCounter; uint16_t nCycleCounterOperations; uint16_t nSequencer; uint16_t HasFramMemroy; uint16_t mainSegmentSize; } __attribute__((packed)); }; static void n2o_device(union DEVICE_T *dst, const union new_device *src) { dst->endian = src->endian; dst->id = src->id; memcpy(dst->string, src->string, sizeof(dst->string)); dst->mainStart = src->mainStart; dst->infoStart = src->infoStart; dst->ramEnd = src->ramEnd; dst->nBreakpoints = src->nBreakpoints; dst->emulation = src->emulation; dst->clockControl = src->clockControl; dst->lcdStart = src->lcdStart; dst->lcdEnd = src->lcdEnd; dst->vccMinOp = src->vccMinOp; dst->vccMaxOp = src->vccMaxOp; dst->hasTestVpp = src->hasTestVpp; dst->ramStart = src->ramStart; dst->ram2Start = src->ram2Start; dst->ram2End = src->ram2End; dst->infoEnd = src->infoEnd; dst->mainEnd = src->mainEnd; dst->bslStart = src->bslStart; dst->bslEnd = src->bslEnd; dst->nRegTrigger = src->nRegTrigger; dst->nCombinations = src->nCombinations; dst->cpuArch = src->cpuArch; dst->jtagId = src->jtagId; dst->coreIpId = src->coreIpId; dst->deviceIdPtr = src->deviceIdPtr; dst->eemVersion = src->eemVersion; dst->nBreakpointsOptions = src->nBreakpointsOptions; dst->nBreakpointsReadWrite = src->nBreakpointsReadWrite; dst->nBreakpointsDma = src->nBreakpointsDma; dst->TrigerMask = src->TrigerMask; dst->nRegTriggerOperations = src->nRegTriggerOperations; dst->nStateStorage = src->nStateStorage; dst->nCycleCounter = src->nCycleCounter; dst->nCycleCounterOperations = src->nCycleCounterOperations; dst->nSequencer = src->nSequencer; dst->HasFramMemroy = src->HasFramMemroy; /* dst->mainSegmentSize = src->mainSegmentSize; */ } typedef void (*new_notify_func_t) (uint32_t MsgId, uint32_t wParam, uint32_t lParam, int32_t clientHandle); struct tilib_new_api { /* MSP430.h */ int32_t TIDLL (*MSP430_Initialize)(char *port, int32_t *version); int32_t TIDLL (*MSP430_VCC)(int32_t voltage); int32_t TIDLL (*MSP430_Configure)(int32_t mode, int32_t value); int32_t TIDLL (*MSP430_OpenDevice)(char *Device, char *Password, int32_t PwLength, int32_t DeviceCode, int32_t setId); int32_t TIDLL (*MSP430_GetFoundDevice)(uint8_t *FoundDevice, int32_t count); int32_t TIDLL (*MSP430_Close)(int32_t vccOff); int32_t TIDLL (*MSP430_Memory)(int32_t address, char *buffer, int32_t count, int32_t rw); int32_t TIDLL (*MSP430_Reset)(int32_t method, int32_t execute, int32_t releaseJTAG); int32_t TIDLL (*MSP430_Erase)(int32_t type, int32_t address, int32_t length); int32_t TIDLL (*MSP430_Secure)(void); int32_t TIDLL (*MSP430_Error_Number)(void); const char *TIDLL (*MSP430_Error_String)(int32_t errNumber); int32_t TIDLL (*MSP430_GetNumberOfUsbIfs)(int32_t* number); int32_t TIDLL (*MSP430_GetNameOfUsbIf)(int32_t idx, char **name, int32_t *status); int32_t TIDLL (*MSP430_LoadDeviceDb)(const char *f); // needed for slac460s /* MSP430_Debug.h */ int32_t TIDLL (*MSP430_Registers)(int32_t *registers, int32_t mask, int32_t rw); int32_t TIDLL (*MSP430_Run)(int32_t mode, int32_t releaseJTAG); int32_t TIDLL (*MSP430_State)(int32_t *state, int32_t stop, int32_t *pCPUCycles); /* MSP430_EEM.h */ int32_t TIDLL (*MSP430_EEM_Init)(new_notify_func_t callback, int32_t clientHandle, struct new_messageid *pMsgIdBuffer); int32_t TIDLL (*MSP430_EEM_SetBreakpoint)(uint16_t *pwBpHandle, struct new_breakpoint *pBpBuffer); /* MSP430_FET.h */ int32_t TIDLL (*MSP430_FET_FwUpdate)(char* lpszFileName, new_notify_func_t callback, int32_t clientHandle); /* Callback thunk data */ DLL430_EVENTNOTIFY_FUNC cb_event; DLL430_FET_NOTIFY_FUNC cb_fw; }; static struct tilib_new_api napi; static STATUS_T new_Initialize(char *port, long *version) { int32_t nv; int r; r = napi.MSP430_Initialize(port, &nv); if (r < 0) return r; if (napi.MSP430_LoadDeviceDb) napi.MSP430_LoadDeviceDb(NULL); *version = nv; return 0; } static STATUS_T new_VCC(long voltage) { return napi.MSP430_VCC(voltage); } static STATUS_T new_Configure(long mode, long value) { return napi.MSP430_Configure(mode, value); } static STATUS_T new_OpenDevice(char *Device, char *Password, long PwLength, long DeviceCode, long setId) { return napi.MSP430_OpenDevice(Device, Password, PwLength, DeviceCode, setId); } static STATUS_T new_GetFoundDevice(char *FoundDevice, long count) { union new_device ndev; union DEVICE_T odev; int r; r = napi.MSP430_GetFoundDevice(ndev.buffer, sizeof(ndev.buffer)); if (r < 0) return r; memset(&odev, 0, sizeof(odev)); n2o_device(&odev, &ndev); if (count > sizeof(odev.buffer)) count = sizeof(odev.buffer); memcpy(FoundDevice, odev.buffer, count); return 0; } static STATUS_T new_Close(long vccOff) { return napi.MSP430_Close(vccOff); } static STATUS_T new_Memory(long address, char *buffer, long count, long rw) { return napi.MSP430_Memory(address, buffer, count, rw); } static STATUS_T new_Reset(long method, long execute, long releaseJTAG) { return napi.MSP430_Reset(method, execute, releaseJTAG); } static STATUS_T new_Erase(long type, long address, long length) { return napi.MSP430_Erase(type, address, length); } static STATUS_T new_Secure(void) { return napi.MSP430_Secure(); } static STATUS_T new_Error_Number(void) { return napi.MSP430_Error_Number(); } static const char *new_Error_String(long errNumber) { return napi.MSP430_Error_String(errNumber); } static STATUS_T new_GetNumberOfUsbIfs(long* number) { int32_t nn; int r; r = napi.MSP430_GetNumberOfUsbIfs(&nn); if (r < 0) return r; *number = nn; return 0; } static STATUS_T new_GetNameOfUsbIf(long idx, char **name, long *status) { int32_t ns; int r; r = napi.MSP430_GetNameOfUsbIf(idx, name, &ns); if (r < 0) return r; *status = ns; return 0; } static STATUS_T new_Registers(long *registers, long mask, long rw) { int32_t nr[16]; int i; for (i = 0; i < 16; i++) if (mask & (1 << i)) nr[i] = registers[i]; i = napi.MSP430_Registers(nr, mask, rw); if (i < 0) return i; for (i = 0; i < 16; i++) if (mask & (1 << i)) registers[i] = nr[i]; return 0; } static STATUS_T new_Run(long mode, long releaseJTAG) { return napi.MSP430_Run(mode, releaseJTAG); } static STATUS_T new_State(long *state, long stop, long *pCPUCycles) { int32_t ns; int32_t nc; int r; r = napi.MSP430_State(&ns, stop, &nc); if (r < 0) return r; *state = ns; *pCPUCycles = nc; return 0; } static void new_event(uint32_t MsgId, uint32_t wParam, uint32_t lParam, int32_t clientHandle) { napi.cb_event(MsgId, wParam, lParam, clientHandle); } static STATUS_T new_EEM_Init(DLL430_EVENTNOTIFY_FUNC callback, long clientHandle, MessageID_t *pMsgIdBuffer) { struct new_messageid nm; napi.cb_event = callback; o2n_messageid(&nm, pMsgIdBuffer); return napi.MSP430_EEM_Init(new_event, clientHandle, &nm); } static STATUS_T new_EEM_SetBreakpoint(uint16_t *pwBpHandle, BpParameter_t *pBpBuffer) { struct new_breakpoint np; o2n_breakpoint(&np, pBpBuffer); return napi.MSP430_EEM_SetBreakpoint(pwBpHandle, &np); } static void new_fw(uint32_t MsgId, uint32_t wParam, uint32_t lParam, int32_t clientHandle) { napi.cb_fw(MsgId, wParam, lParam, clientHandle); } static STATUS_T new_FET_FwUpdate(char* lpszFileName, DLL430_FET_NOTIFY_FUNC callback, long clientHandle) { napi.cb_fw = callback; return napi.MSP430_FET_FwUpdate(lpszFileName, new_fw, clientHandle); } static const struct tilib_api_table new_tab = { .MSP430_Initialize = new_Initialize, .MSP430_VCC = new_VCC, .MSP430_Configure = new_Configure, .MSP430_OpenDevice = new_OpenDevice, .MSP430_GetFoundDevice = new_GetFoundDevice, .MSP430_Close = new_Close, .MSP430_Memory = new_Memory, .MSP430_Reset = new_Reset, .MSP430_Erase = new_Erase, .MSP430_Secure = new_Secure, .MSP430_Error_Number = new_Error_Number, .MSP430_Error_String = new_Error_String, .MSP430_GetNumberOfUsbIfs = new_GetNumberOfUsbIfs, .MSP430_GetNameOfUsbIf = new_GetNameOfUsbIf, .MSP430_Registers = new_Registers, .MSP430_Run = new_Run, .MSP430_State = new_State, .MSP430_EEM_Init = new_EEM_Init, .MSP430_EEM_SetBreakpoint = new_EEM_SetBreakpoint, .MSP430_FET_FwUpdate = new_FET_FwUpdate, }; static int init_new_api(void) { if (!(napi.MSP430_Initialize = get_func("MSP430_Initialize"))) return -1; if (!(napi.MSP430_VCC = get_func("MSP430_VCC"))) return -1; if (!(napi.MSP430_Configure = get_func("MSP430_Configure"))) return -1; if (!(napi.MSP430_OpenDevice = get_func("MSP430_OpenDevice"))) return -1; if (!(napi.MSP430_GetFoundDevice = get_func("MSP430_GetFoundDevice"))) return -1; if (!(napi.MSP430_Close = get_func("MSP430_Close"))) return -1; if (!(napi.MSP430_Memory = get_func("MSP430_Memory"))) return -1; if (!(napi.MSP430_Reset = get_func("MSP430_Reset"))) return -1; if (!(napi.MSP430_Erase = get_func("MSP430_Erase"))) return -1; if (!(napi.MSP430_Secure = get_func("MSP430_Secure"))) return -1; if (!(napi.MSP430_Error_Number = get_func("MSP430_Error_Number"))) return -1; if (!(napi.MSP430_Error_String = get_func("MSP430_Error_String"))) return -1; if (!(napi.MSP430_GetNumberOfUsbIfs = get_func("MSP430_GetNumberOfUsbIfs"))) return -1; napi.MSP430_LoadDeviceDb = dynload_sym(lib_handle, "MSP430_LoadDeviceDb"); if (!(napi.MSP430_GetNameOfUsbIf = get_func("MSP430_GetNameOfUsbIf"))) return -1; if (!(napi.MSP430_Registers = get_func("MSP430_Registers"))) return -1; if (!(napi.MSP430_Run = get_func("MSP430_Run"))) return -1; if (!(napi.MSP430_State = get_func("MSP430_State"))) return -1; if (!(napi.MSP430_EEM_Init = get_func("MSP430_EEM_Init"))) return -1; if (!(napi.MSP430_EEM_SetBreakpoint = get_func("MSP430_EEM_SetBreakpoint"))) return -1; if (!(napi.MSP430_FET_FwUpdate = get_func("MSP430_FET_FwUpdate"))) return -1; tilib_api = &new_tab; return 0; } /************************************************************************ * Old API (pre-SLAC460L) */ struct tilib_old_api { /* MSP430.h */ STATUS_T TIDLL (*MSP430_Initialize)(char *port, long *version); STATUS_T TIDLL (*MSP430_VCC)(long voltage); STATUS_T TIDLL (*MSP430_Configure)(long mode, long value); STATUS_T TIDLL (*MSP430_OpenDevice)(char *Device, char *Password, long PwLength, long DeviceCode, long setId); STATUS_T TIDLL (*MSP430_GetFoundDevice)(char *FoundDevice, long count); STATUS_T TIDLL (*MSP430_Close)(long vccOff); STATUS_T TIDLL (*MSP430_Memory)(long address, char *buffer, long count, long rw); STATUS_T TIDLL (*MSP430_Reset)(long method, long execute, long releaseJTAG); STATUS_T TIDLL (*MSP430_Erase)(long type, long address, long length); STATUS_T TIDLL (*MSP430_Secure)(void); STATUS_T TIDLL (*MSP430_Error_Number)(void); const char *TIDLL (*MSP430_Error_String)(long errNumber); STATUS_T TIDLL (*MSP430_GetNumberOfUsbIfs)(long* number); STATUS_T TIDLL (*MSP430_GetNameOfUsbIf)(long idx, char **name, long *status); /* MSP430_Debug.h */ STATUS_T TIDLL (*MSP430_Registers)(long *registers, long mask, long rw); STATUS_T TIDLL (*MSP430_Run)(long mode, long releaseJTAG); STATUS_T TIDLL (*MSP430_State)(long *state, long stop, long *pCPUCycles); /* MSP430_EEM.h */ STATUS_T TIDLL (*MSP430_EEM_Init)(DLL430_EVENTNOTIFY_FUNC callback, long clientHandle, MessageID_t *pMsgIdBuffer); STATUS_T TIDLL (*MSP430_EEM_SetBreakpoint)(uint16_t *pwBpHandle, BpParameter_t *pBpBuffer); /* MSP430_FET.h */ STATUS_T TIDLL (*MSP430_FET_FwUpdate)(char* lpszFileName, DLL430_FET_NOTIFY_FUNC callback, long clientHandle); }; static struct tilib_old_api old; static STATUS_T old_Initialize(char *port, long *version) { return old.MSP430_Initialize(port, version); } static STATUS_T old_VCC(long voltage) { return old.MSP430_VCC(voltage); } static STATUS_T old_Configure(long mode, long value) { return old.MSP430_Configure(mode, value); } static STATUS_T old_OpenDevice(char *Device, char *Password, long PwLength, long DeviceCode, long setId) { return old.MSP430_OpenDevice(Device, Password, PwLength, DeviceCode, setId); } static STATUS_T old_GetFoundDevice(char *FoundDevice, long count) { return old.MSP430_GetFoundDevice(FoundDevice, count); } static STATUS_T old_Close(long vccOff) { return old.MSP430_Close(vccOff); } static STATUS_T old_Memory(long address, char *buffer, long count, long rw) { return old.MSP430_Memory(address, buffer, count, rw); } static STATUS_T old_Reset(long method, long execute, long releaseJTAG) { return old.MSP430_Reset(method, execute, releaseJTAG); } static STATUS_T old_Erase(long type, long address, long length) { return old.MSP430_Erase(type, address, length); } static STATUS_T old_Secure(void) { return old.MSP430_Secure(); } static STATUS_T old_Error_Number(void) { return old.MSP430_Error_Number(); } static const char *old_Error_String(long errNumber) { return old.MSP430_Error_String(errNumber); } static STATUS_T old_GetNumberOfUsbIfs(long* number) { return old.MSP430_GetNumberOfUsbIfs(number); } static STATUS_T old_GetNameOfUsbIf(long idx, char **name, long *status) { return old.MSP430_GetNameOfUsbIf(idx, name, status); } static STATUS_T old_Registers(long *registers, long mask, long rw) { return old.MSP430_Registers(registers, mask, rw); } static STATUS_T old_Run(long mode, long releaseJTAG) { return old.MSP430_Run(mode, releaseJTAG); } static STATUS_T old_State(long *state, long stop, long *pCPUCycles) { return old.MSP430_State(state, stop, pCPUCycles); } static STATUS_T old_EEM_Init(DLL430_EVENTNOTIFY_FUNC callback, long clientHandle, MessageID_t *pMsgIdBuffer) { return old.MSP430_EEM_Init(callback, clientHandle, pMsgIdBuffer); } static STATUS_T old_EEM_SetBreakpoint(uint16_t *pwBpHandle, BpParameter_t *pBpBuffer) { return old.MSP430_EEM_SetBreakpoint(pwBpHandle, pBpBuffer); } static STATUS_T old_FET_FwUpdate(char* lpszFileName, DLL430_FET_NOTIFY_FUNC callback, long clientHandle) { return old.MSP430_FET_FwUpdate(lpszFileName, callback, clientHandle); } static const struct tilib_api_table old_tab = { .MSP430_Initialize = old_Initialize, .MSP430_VCC = old_VCC, .MSP430_Configure = old_Configure, .MSP430_OpenDevice = old_OpenDevice, .MSP430_GetFoundDevice = old_GetFoundDevice, .MSP430_Close = old_Close, .MSP430_Memory = old_Memory, .MSP430_Reset = old_Reset, .MSP430_Erase = old_Erase, .MSP430_Secure = old_Secure, .MSP430_Error_Number = old_Error_Number, .MSP430_Error_String = old_Error_String, .MSP430_GetNumberOfUsbIfs = old_GetNumberOfUsbIfs, .MSP430_GetNameOfUsbIf = old_GetNameOfUsbIf, .MSP430_Registers = old_Registers, .MSP430_Run = old_Run, .MSP430_State = old_State, .MSP430_EEM_Init = old_EEM_Init, .MSP430_EEM_SetBreakpoint = old_EEM_SetBreakpoint, .MSP430_FET_FwUpdate = old_FET_FwUpdate, }; static int init_old_api(void) { if (!(old.MSP430_Initialize = get_func("MSP430_Initialize"))) return -1; if (!(old.MSP430_VCC = get_func("MSP430_VCC"))) return -1; if (!(old.MSP430_Configure = get_func("MSP430_Configure"))) return -1; if (!(old.MSP430_OpenDevice = get_func("MSP430_OpenDevice"))) return -1; if (!(old.MSP430_GetFoundDevice = get_func("MSP430_GetFoundDevice"))) return -1; if (!(old.MSP430_Close = get_func("MSP430_Close"))) return -1; if (!(old.MSP430_Memory = get_func("MSP430_Memory"))) return -1; if (!(old.MSP430_Reset = get_func("MSP430_Reset"))) return -1; if (!(old.MSP430_Erase = get_func("MSP430_Erase"))) return -1; if (!(old.MSP430_Secure = get_func("MSP430_Secure"))) return -1; if (!(old.MSP430_Error_Number = get_func("MSP430_Error_Number"))) return -1; if (!(old.MSP430_Error_String = get_func("MSP430_Error_String"))) return -1; if (!(old.MSP430_GetNumberOfUsbIfs = get_func("MSP430_GetNumberOfUsbIfs"))) return -1; if (!(old.MSP430_GetNameOfUsbIf = get_func("MSP430_GetNameOfUsbIf"))) return -1; if (!(old.MSP430_Registers = get_func("MSP430_Registers"))) return -1; if (!(old.MSP430_Run = get_func("MSP430_Run"))) return -1; if (!(old.MSP430_State = get_func("MSP430_State"))) return -1; if (!(old.MSP430_EEM_Init = get_func("MSP430_EEM_Init"))) return -1; if (!(old.MSP430_EEM_SetBreakpoint = get_func("MSP430_EEM_SetBreakpoint"))) return -1; if (!(old.MSP430_FET_FwUpdate = get_func("MSP430_FET_FwUpdate"))) return -1; tilib_api = &old_tab; return 0; } /************************************************************************ * Top-level init */ int tilib_api_init(void) { int ret; lib_handle = dynload_open(tilib_filename); if (!lib_handle) { printc_err("tilib_api: can't find %s: %s\n", tilib_filename, dynload_error()); return -1; } if (dynload_sym(lib_handle, "MSP430_HIL_MEMAP")) { printc_dbg("Using new (SLAC460L+) API\n"); ret = init_new_api(); } else { printc_dbg("Using old API\n"); ret = init_old_api(); } if (ret < 0) { dynload_close(lib_handle); return -1; } return 0; } void tilib_api_exit(void) { dynload_close(lib_handle); } mspdebug-0.25/drivers/tilib_api.h000066400000000000000000000047321313531517500170430ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2015 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef TILIB_API_H_ #define TILIB_API_H_ #include "tilib_defs.h" struct tilib_api_table { /* MSP430.h */ STATUS_T (*MSP430_Initialize)(char *port, long *version); STATUS_T (*MSP430_VCC)(long voltage); STATUS_T (*MSP430_Configure)(long mode, long value); STATUS_T (*MSP430_OpenDevice)(char *Device, char *Password, long PwLength, long DeviceCode, long setId); STATUS_T (*MSP430_GetFoundDevice)(char *FoundDevice, long count); STATUS_T (*MSP430_Close)(long vccOff); STATUS_T (*MSP430_Memory)(long address, char *buffer, long count, long rw); STATUS_T (*MSP430_Reset)(long method, long execute, long releaseJTAG); STATUS_T (*MSP430_Erase)(long type, long address, long length); STATUS_T (*MSP430_Secure)(void); STATUS_T (*MSP430_Error_Number)(void); const char *(*MSP430_Error_String)(long errNumber); STATUS_T (*MSP430_GetNumberOfUsbIfs)(long* number); STATUS_T (*MSP430_GetNameOfUsbIf)(long idx, char **name, long *status); /* MSP430_Debug.h */ STATUS_T (*MSP430_Registers)(long *registers, long mask, long rw); STATUS_T (*MSP430_Run)(long mode, long releaseJTAG); STATUS_T (*MSP430_State)(long *state, long stop, long *pCPUCycles); /* MSP430_EEM.h */ STATUS_T (*MSP430_EEM_Init)(DLL430_EVENTNOTIFY_FUNC callback, long clientHandle, MessageID_t *pMsgIdBuffer); STATUS_T (*MSP430_EEM_SetBreakpoint)(uint16_t *pwBpHandle, BpParameter_t *pBpBuffer); /* MSP430_FET.h */ STATUS_T (*MSP430_FET_FwUpdate)(char* lpszFileName, DLL430_FET_NOTIFY_FUNC callback, long clientHandle); }; extern const struct tilib_api_table *tilib_api; int tilib_api_init(void); void tilib_api_exit(void); #endif mspdebug-0.25/drivers/tilib_defs.h000066400000000000000000000276001313531517500172120ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2011 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef TILIB_DEFS_H_ #define TILIB_DEFS_H_ /* This header file contains various constants used by the TI MSP430 * library. The original copyright notice is: * * Copyright (C) 2004 - 2011 Texas Instruments Incorporated - * http://www.ti.com/ * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include /* this is the definition for the DLL functions return value */ typedef long STATUS_T; typedef long LONG; typedef unsigned long ULONG; typedef char CHAR; typedef uint16_t WORD; typedef uint8_t BYTE; enum READ_WRITE { WRITE = 0, READ = 1, }; enum RESET_METHOD { PUC_RESET = (1 << 0), /**< Power up clear (i.e., a "soft") reset */ RST_RESET = (1 << 1), /**< RST/NMI (i.e., "hard") reset */ VCC_RESET = (1 << 2), /**< Cycle Vcc (i.e., a "power on") reset */ FORCE_RESET = (1 << 3) }; /* FLASH erase type. */ enum ERASE_TYPE { ERASE_SEGMENT = 0, /**< Erase a segment */ ERASE_MAIN = 1, /**< Erase all MAIN memory */ ERASE_ALL = 2, /**< Erase all MAIN and INFORMATION memory */ }; /* Run modes. */ enum RUN_MODES { /* Run the device. Set breakpoints (if any) are disabled */ FREE_RUN = 1, /* A single device instruction is executed. Interrupt * processing is supported */ SINGLE_STEP = 2, /* Run the device. Set breakpoints (if any) are enabled */ RUN_TO_BREAKPOINT = 3 }; /* State modes. */ enum STATE_MODES { /* The device is stopped */ STOPPED = 0, /* The device is running or is being single stepped */ RUNNING = 1, /* The device is stopped after the single step operation is * complete */ SINGLE_STEP_COMPLETE = 2, /* The device is stopped as a result of hitting an enabled * breakpoint */ BREAKPOINT_HIT = 3, /* The device is in LPMx.5 low power mode */ LPMX5_MODE = 4, /* The device woke up from LPMx.5 low power mode */ LPMX5_WAKEUP = 5 }; /* Configurations to set with MSP430_Configure. */ enum CONFIG_MODE { /* Verify data downloaded to FLASH memories */ VERIFICATION_MODE = 0, /* 4xx emulation mode */ EMULATION_MODE = 1, /* Clock control mode (on emulation stop) */ CLK_CNTRL_MODE = 2, /* Module Clock control mode (on emulation stop) */ MCLK_CNTRL_MODE = 3, /* Flash test mode for Automotive Devices - Marginal Read */ FLASH_TEST_MODE = 4, /* Allows Locked Info Mem Segment A access (if set to '1') */ LOCKED_FLASH_ACCESS = 5, /* Flash Swop mode for Automotive Devices */ FLASH_SWOP = 6, /* Trace mode in EDT file format */ EDT_TRACE_MODE = 7, /* Configure interface protocol: JTAG or Spy-bi-Wire * (see enum INTERFACE_TYPE) */ INTERFACE_MODE = 8, /* Configure a value that will be placed on the devices' * MemoryDataBus right before the device gets released from JTAG. * Useful fro supporting Emulated Hardware Breakpoints. */ SET_MDB_BEFORE_RUN = 9, /* * Configure whether RAM content should be preserved/restored * in MSP430_Erase() and MSP430_Memory() or not. * RAM_PRESERVE_MODE is set to ENABLE by default. * Usage Example for initial flash programming: * (1) MSP430_Configure(RAM_PRESERVE_MODE, DISABLE); * (2) MSP430_Erase(ERASE_ALL,..,..); * (3) MSP430_Memory(..., ..., ..., WRITE ); * (4) MSP430_Memory(..., ..., ..., READ ); * ..... Flash Programming/Download finished * (n) MSP430_Configure(RAM_PRESERVE_MODE, ENABLE); */ RAM_PRESERVE_MODE = 10, /* Configure the DLL to allow read/write/erase access to the 5xx * Bootstrap Loader (BSL) memory segments. */ UNLOCK_BSL_MODE =11, /* just used internal for the device code of L092 and C092 */ DEVICE_CODE = 12, /* set true to write the external SPI image of the L092 */ WRITE_EXTERNAL_MEMORY = 13, /* set DEBUG_LPM_X true to start debugging of LPMx.5 */ DEBUG_LPM_X = 14 }; typedef void (*DLL430_EVENTNOTIFY_FUNC) (unsigned int MsgId, unsigned int wParam, long lParam, long clientHandle); typedef struct MESSAGE_ID { ULONG uiMsgIdSingleStep; ULONG uiMsgIdBreakpoint; ULONG uiMsgIdStorage; ULONG uiMsgIdState; ULONG uiMsgIdWarning; ULONG uiMsgIdCPUStopped; } MessageID_t; typedef enum BpMode { BP_CLEAR = 0, BP_CODE = 1, BP_RANGE = 2, BP_COMPLEX = 3 } BpMode_t; typedef enum BpType { BP_MAB = 0, BP_MDB = 1, BP_REGISTER = 2 } BpType_t; typedef enum BpAccess { BP_FETCH = 0, BP_FETCH_HOLD = 1, BP_NO_FETCH = 2, BP_DONT_CARE = 3, BP_NO_FETCH_READ = 4, BP_NO_FETCH_WRITE = 5, BP_READ = 6, BP_WRITE = 7, BP_NO_FETCH_NO_DMA = 8, BP_DMA = 9, BP_NO_DMA = 10, BP_WRITE_NO_DMA = 11, BP_NO_FETCH_READ_NO_DMA = 12, BP_READ_NO_DMA = 13, BP_READ_DMA = 14, BP_WRITE_DMA = 15 } BpAccess_t; typedef enum BpOperat { BP_EQUAL = 0, BP_GREATER = 1, BP_LOWER = 2, BP_UNEQUAL = 3 } BpOperat_t; typedef enum BpRangeAction { BP_INSIDE = 0, BP_OUTSIDE = 1 } BpRangeAction_t; typedef enum BpCondition { BP_NO_COND = 0, BP_COND = 1 } BpCondition_t; typedef enum BpAction { BP_NONE = 0, BP_BRK = 1, BP_STO = 2, BP_BRK_STO = 3 } BpAction_t; typedef struct BREAKPOINT { /* Breakpoint modes */ BpMode_t bpMode; /* Breakpoint address/value (ignored for clear breakpoint) */ LONG lAddrVal; /* Breakpoint type (used for range and complex breakpoints) */ BpType_t bpType; /* Breakpoint register (used for complex breakpoints with * register-write trigger) */ LONG lReg; /* Breakpoint access (used only for range and complex * breakpoints) */ BpAccess_t bpAccess; /* Breakpoint action (break/storage) (used for range and complex * breakpoints) */ BpAction_t bpAction; /* Breakpoint operator (used for complex breakpoints) */ BpOperat_t bpOperat; /* Breakpoint mask (used for complex breakpoints) */ LONG lMask; /* Range breakpoint end address (used for range breakpoints) */ LONG lRangeEndAdVa; /* Range breakpoint action (inside/outside) (used for range * breakpoints) */ BpRangeAction_t bpRangeAction; /* Complex breakpoint: Condition available */ BpCondition_t bpCondition; /* Complex breakpoint: MDB value (used for complex breakpoints) */ ULONG lCondMdbVal; /* Complex breakpoint: Access (used for complex breakpoints) */ BpAccess_t bpCondAccess; /* Complex breakpoint: Mask Value(used for complex breakpoints) */ LONG lCondMask; /* Complex breakpoint: Operator (used for complex breakpoints) */ BpOperat_t bpCondOperat; /* Combine breakpoint: Reference of a combination handle */ WORD wExtCombine; } BpParameter_t; typedef void (*DLL430_FET_NOTIFY_FUNC) (unsigned int MsgId, unsigned long wParam, unsigned long lParam, long clientHandle); typedef enum UPDATE_STATUS_MESSAGES { /* Initializing Update Bootloader */ BL_INIT = 0, /* Erasing mapped interrupt vectors */ BL_ERASE_INT_VECTORS = 1, /* Erasing firmware memory section */ BL_ERASE_FIRMWARE = 2, /* Program new firmware */ BL_PROGRAM_FIRMWARE = 3, /* One data block of the new firmware was successfully programmed */ BL_DATA_BLOCK_PROGRAMMED = 4, /* Exit Update Bootlader and reboot firmware */ BL_EXIT = 5, /* Update was successfully finished */ BL_UPDATE_DONE = 6, /* An error occured during firmware update */ BL_UPDATE_ERROR = 7, /* An error occured during firmware update */ BL_WAIT_FOR_TIMEOUT = 8 } UPDATE_STATUS_MESSAGES_t; union DEVICE_T { /* this buffer holds the complete device information */ /* and is overlayed by the following information structure */ CHAR buffer[110]; struct { /* actually 106 Bytes */ /* The value 0xaa55. */ WORD endian; /* Identification number. */ WORD id; /* Identification string. */ BYTE string[32]; /* MAIN MEMORY (FLASH) starting address. */ WORD mainStart; /* INFORMATION MEMORY (FLASH) starting address. */ WORD infoStart; /* RAM ending address. */ WORD ramEnd; /* Number of breakpoints. */ WORD nBreakpoints; /* Emulation level. */ WORD emulation; /* Clock control level. */ WORD clockControl; /* LCD starting address. */ WORD lcdStart; /* LCD ending address. */ WORD lcdEnd; /* Vcc minimum during operation [mVolts]. */ WORD vccMinOp; /* Vcc maximum during operation [mVolts]. */ WORD vccMaxOp; /* Device has TEST/VPP. */ WORD hasTestVpp; /* RAM starting address. */ WORD ramStart; /* RAM2 starting address. */ WORD ram2Start; /* RAM2 ending address. */ WORD ram2End; /* INFO ending address. */ WORD infoEnd; /* MAIN ending address. */ ULONG mainEnd; /* BSL starting address. */ WORD bslStart; /* BSL ending address. */ WORD bslEnd; /* Number of CPU Register Trigger. */ WORD nRegTrigger; /* Number of EEM Trigger Combinations. */ WORD nCombinations; /* The MSP430 architecture (non-X, X or Xv2). */ BYTE cpuArch; /* The JTAG ID - value returned on an instruction shift. */ BYTE jtagId; /* The CoreIP ID. */ WORD coreIpId; /* The Device-ID Pointer. */ ULONG deviceIdPtr; /* The EEM Version Number. */ WORD eemVersion; /* Breakpoint Modes */ WORD nBreakpointsOptions; WORD nBreakpointsReadWrite; WORD nBreakpointsDma; /* Trigger Mask for Breakpoint */ WORD TrigerMask; /* Register Trigger modes */ WORD nRegTriggerOperations; /* MSP430 has Stage Storage */ WORD nStateStorage ; /* Numbr of cycle counters of MSP430 */ WORD nCycleCounter; /* Cycle couter modes */ WORD nCycleCounterOperations; /* Msp430 has Sqeuncer */ WORD nSequencer; /* Msp430 has FRAM Memroy */ WORD HasFramMemroy; } __attribute__((packed)); }; #endif mspdebug-0.25/drivers/v3hil.c000066400000000000000000000645461313531517500161400ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include "bytes.h" #include "v3hil.h" #include "dis.h" #include "output.h" #include "opdb.h" /* HAL function IDs */ typedef enum { HAL_PROTO_FID_INIT = 0x01, HAL_PROTO_FID_SET_VCC = 0x02, HAL_PROTO_FID_GET_VCC = 0x03, HAL_PROTO_FID_START_JTAG = 0x04, HAL_PROTO_FID_START_JTAG_ACT_CODE = 0x05, HAL_PROTO_FID_STOP_JTAG = 0x06, HAL_PROTO_FID_CONFIGURE = 0x07, HAL_PROTO_FID_GET_FUSES = 0x08, HAL_PROTO_FID_BLOW_FUSE = 0x09, HAL_PROTO_FID_WAIT_FOR_EEM = 0x0a, HAL_PROTO_FID_BIT_SEQUENCE = 0x0b, HAL_PROTO_FID_GET_JTAG_ID = 0x0c, HAL_PROTO_FID_SET_DEVICE_CHAIN_INFO = 0x0d, HAL_PROTO_FID_SET_CHAIN_CONFIGURATION = 0x0e, HAL_PROTO_FID_GET_NUM_DEVICES = 0x0f, HAL_PROTO_FID_GET_INTERFACE_MODE = 0x10, HAL_PROTO_FID_SJ_ASSERT_POR_SC = 0x11, HAL_PROTO_FID_SJ_CONDITIONAL_SC = 0x12, HAL_PROTO_FID_RC_RELEASE_JTAG = 0x13, HAL_PROTO_FID_READ_MEM_BYTES = 0x14, HAL_PROTO_FID_READ_MEM_WORDS = 0x15, HAL_PROTO_FID_READ_MEM_QUICK = 0x16, HAL_PROTO_FID_WRITE_MEM_BYTES = 0x17, HAL_PROTO_FID_WRITE_MEM_WORDS = 0x18, HAL_PROTO_FID_EEM_DX = 0x19, HAL_PROTO_FID_EEM_DX_AFE2XX = 0x1a, HAL_PROTO_FID_SINGLE_STEP = 0x1b, HAL_PROTO_FID_READ_ALL_CPU_REGS = 0x1c, HAL_PROTO_FID_WRITE_ALL_CPU_REGS = 0x1d, HAL_PROTO_FID_PSA = 0x1e, HAL_PROTO_FID_EXECUTE_FUNCLET = 0x1f, HAL_PROTO_FID_EXECUTE_FUNCLET_JTAG = 0x20, HAL_PROTO_FID_GET_DCO_FREQUENCY = 0x21, HAL_PROTO_FID_GET_DCO_FREQUENCY_JTAG = 0x22, HAL_PROTO_FID_GET_FLL_FREQUENCY = 0x23, HAL_PROTO_FID_GET_FLL_FREQUENCY_JTAG = 0x24, HAL_PROTO_FID_WAIT_FOR_STORAGE = 0x25, HAL_PROTO_FID_SJ_ASSERT_POR_SC_X = 0x26, HAL_PROTO_FID_SJ_CONDITIONAL_SC_X = 0x27, HAL_PROTO_FID_RC_RELEASE_JTAG_X = 0x28, HAL_PROTO_FID_READ_MEM_BYTES_X = 0x29, HAL_PROTO_FID_READ_MEM_WORDS_X = 0x2a, HAL_PROTO_FID_READ_MEM_QUICK_X = 0x2b, HAL_PROTO_FID_WRITE_MEM_BYTES_X = 0x2c, HAL_PROTO_FID_WRITE_MEM_WORDS_X = 0x2d, HAL_PROTO_FID_EEM_DX_X = 0x2e, HAL_PROTO_FID_SINGLE_STEP_X = 0x2f, HAL_PROTO_FID_READ_ALL_CPU_REGS_X = 0x30, HAL_PROTO_FID_WRITE_ALL_CPU_REGS_X = 0x31, HAL_PROTO_FID_PSA_X = 0x32, HAL_PROTO_FID_EXECUTE_FUNCLET_X = 0x33, HAL_PROTO_FID_GET_DCO_FREQUENCY_X = 0x34, HAL_PROTO_FID_GET_FLL_FREQUENCY_X = 0x35, HAL_PROTO_FID_WAIT_FOR_STORAGE_X = 0x36, HAL_PROTO_FID_BLOW_FUSE_XV2 = 0x37, HAL_PROTO_FID_BLOW_FUSE_FRAM = 0x38, HAL_PROTO_FID_SJ_ASSERT_POR_SC_XV2 = 0x39, HAL_PROTO_FID_SJ_CONDITIONAL_SC_XV2 = 0x3a, HAL_PROTO_FID_RC_RELEASE_JTAG_XV2 = 0x3b, HAL_PROTO_FID_READ_MEM_WORDS_XV2 = 0x3c, HAL_PROTO_FID_READ_MEM_QUICK_XV2 = 0x3d, HAL_PROTO_FID_WRITE_MEM_WORDS_XV2 = 0x3e, HAL_PROTO_FID_EEM_DX_XV2 = 0x3f, HAL_PROTO_FID_SINGLE_STEP_XV2 = 0x40, HAL_PROTO_FID_READ_ALL_CPU_REGS_XV2 = 0x41, HAL_PROTO_FID_WRITE_ALL_CPU_REGS_XV2 = 0x42, HAL_PROTO_FID_PSA_XV2 = 0x43, HAL_PROTO_FID_EXECUTE_FUNCLET_XV2 = 0x44, HAL_PROTO_FID_UNLOCK_DEVICE_XV2 = 0x45, HAL_PROTO_FID_MAGIC_PATTERN = 0x46, HAL_PROTO_FID_UNLOCK_C092 = 0x47, HAL_PROTO_FID_HIL_COMMAND = 0x48, HAL_PROTO_FID_POLL_JSTATE_REG = 0x49, HAL_PROTO_FID_POLL_JSTATE_REG_FR57XX = 0x4a, HAL_PROTO_FID_IS_JTAG_FUSE_BLOWN = 0x4b, HAL_PROTO_FID_RESET_XV2 = 0x4c, HAL_PROTO_FID_WRITE_FRAM_QUICK_XV2 = 0x4d, HAL_PROTO_FID_SEND_JTAG_MAILBOX_XV2 = 0x4e, HAL_PROTO_FID_SINGLE_STEP_JSTATE_XV2 = 0x4f, HAL_PROTO_FID_POLL_JSTATE_REG_ET8 = 0x50, HAL_PROTO_FID_RESET_STATIC_GLOBAL_VARS = 0x51, HAL_PROTO_FID_RESET_430I = 0x52, HAL_PROTO_FID_POLL_JSTATE_REG_430I = 0x53 } hal_proto_fid_t; /* Argument types for HAL_PROTO_FID_CONFIGURE */ typedef enum { HAL_PROTO_CONFIG_ENHANCED_PSA = 0x01, HAL_PROTO_CONFIG_PSA_TCKL_HIGH = 0x02, HAL_PROTO_CONFIG_DEFAULT_CLK_CONTROL = 0x03, HAL_PROTO_CONFIG_POWER_TESTREG_MASK = 0x04, HAL_PROTO_CONFIG_TESTREG_ENABLE_LPMX5 = 0x05, HAL_PROTO_CONFIG_TESTREG_DISABLE_LPMX5 = 0x06, HAL_PROTO_CONFIG_POWER_TESTREG3V_MASK = 0x07, HAL_PROTO_CONFIG_TESTREG3V_ENABLE_LPMX5 = 0x08, HAL_PROTO_CONFIG_TESTREG3V_DISABLE_LPMX5 = 0x09, HAL_PROTO_CONFIG_CLK_CONTROL_TYPE = 0x0a, HAL_PROTO_CONFIG_JTAG_SPEED = 0x0b, HAL_PROTO_CONFIG_SFLLDEH = 0x0c, HAL_PROTO_CONFIG_NO_BSL = 0x0d, HAL_PROTO_CONFIG_ALT_ROM_ADDR_FOR_CPU_READ = 0x0e, HAL_PROTO_CONFIG_ASSERT_BSL_VALID_BIT = 0x0f } hal_proto_config_t; static hal_proto_fid_t map_fid(const struct v3hil *h, hal_proto_fid_t src) { hal_proto_fid_t dst = h->chip->v3_functions[src]; return dst ? dst : src; } void v3hil_init(struct v3hil *h, transport_t trans, hal_proto_flags_t flags) { memset(h, 0, sizeof(*h)); hal_proto_init(&h->hal, trans, flags); } int v3hil_set_vcc(struct v3hil *h, int vcc_mv) { uint8_t data[2]; w16le(data, vcc_mv); return hal_proto_execute(&h->hal, HAL_PROTO_FID_SET_VCC, data, 2); } int v3hil_comm_init(struct v3hil *h) { const uint8_t ver_payload = 0; printc_dbg("Reset communications...\n"); if (hal_proto_send(&h->hal, HAL_PROTO_TYPE_EXCEPTION, NULL, 0) < 0) return -1; if (hal_proto_execute(&h->hal, 0, &ver_payload, 1) < 0) return -1; if (h->hal.length < 8) { printc_err("warning: v3hil: short reply to version request\n"); } else { const uint8_t major = h->hal.payload[1] >> 6; const uint8_t minor = h->hal.payload[1] & 0x3f; const uint8_t patch = h->hal.payload[0]; const uint16_t flavour = r16le(h->hal.payload + 2); printc_dbg("Version: %d.%d.%d.%d, HW: 0x%04x\n", major, minor, patch, flavour, r32le(h->hal.payload + 4)); } printc_dbg("Reset firmware...\n"); if (hal_proto_execute(&h->hal, HAL_PROTO_FID_RESET_STATIC_GLOBAL_VARS, NULL, 0) < 0) return -1; return 0; } int v3hil_start_jtag(struct v3hil *h, v3hil_jtag_type_t type) { uint8_t data = type; uint8_t chain_id[2] = {0, 0}; if (hal_proto_execute(&h->hal, HAL_PROTO_FID_START_JTAG, &data, 1) < 0) return -1; if (!h->hal.length) { printc_err("v3hil: short reply\n"); return -1; } if (!h->hal.payload[0]) { printc_err("v3hil: no devices present\n"); return -1; } printc_dbg("Device count: %d\n", h->hal.payload[0]); return hal_proto_execute(&h->hal, HAL_PROTO_FID_SET_DEVICE_CHAIN_INFO, chain_id, 2); } int v3hil_stop_jtag(struct v3hil *h) { return hal_proto_execute(&h->hal, HAL_PROTO_FID_STOP_JTAG, NULL, 0); } int v3hil_sync(struct v3hil *h) { uint8_t data[32]; h->cal.is_cal = 0; memset(data, 0, sizeof(data)); data[0] = (h->jtag_id == 0x89) ? 0x20 : 0x5c; /* WDTCTL */ data[1] = 0x01; data[2] = 0x80; /* WDTHOLD */ data[3] = 0x5a; /* WDTPW */ data[4] = h->jtag_id; /* ETW codes (?) */ if (h->chip) { int i; for (i = 0; i < 16; i++) data[i + 20 - i] = h->chip->clock_map[i].value; } else { data[5] = 1; data[15] = 40; } /* We can't use map_fid() because h->chip might be NULL -- this * function will be called before identification is complete. */ if (hal_proto_execute(&h->hal, (h->jtag_id == 0x89) ? HAL_PROTO_FID_SJ_ASSERT_POR_SC : HAL_PROTO_FID_SJ_ASSERT_POR_SC_XV2, data, 21) < 0) return -1; if (h->hal.length < 8) { printc_err("v3hil: short reply: %d\n", h->hal.length); return -1; } h->wdtctl = h->hal.payload[0]; h->regs[MSP430_REG_PC] = r32le(h->hal.payload + 2); h->regs[MSP430_REG_SR] = r16le(h->hal.payload + 6); return 0; } int v3hil_read(struct v3hil *h, address_t addr, uint8_t *mem, address_t size) { const struct chipinfo_memory *m = NULL; uint8_t req[12]; if (h->chip) { size = check_range(h->chip, addr, size, &m); if (!m) { memset(mem, 0x55, size); return size; } } w32le(req, addr); w32le(req + 4, (m->bits == 8) ? size : (size >> 1)); w32le(req + 8, h->regs[MSP430_REG_PC]); if (hal_proto_execute(&h->hal, map_fid(h, (m->bits == 8) ? HAL_PROTO_FID_READ_MEM_BYTES : HAL_PROTO_FID_READ_MEM_WORDS), req, 8) < 0) goto fail; if (h->hal.length < size) { printc_err("v3hil: short reply: %d\n", h->hal.length); goto fail; } memcpy(mem, h->hal.payload, size); return size; fail: printc_err("v3hil: failed reading %d bytes from 0x%05x\n", size, addr); return -1; } const struct chipinfo_memory *find_ram(const struct chipinfo *c) { const struct chipinfo_memory *m; const struct chipinfo_memory *best = NULL; if (!c) goto fail; for (m = c->memory; m->name; m++) { if (m->type != CHIPINFO_MEMTYPE_RAM) continue; if (!best || m->size > best->size) best = m; } if (!best) goto fail; return best; fail: printc_err("v3hil: can't find RAM region in chip database\n"); return NULL; } static int calibrate_dco(struct v3hil *h, uint8_t max_bcs) { const struct chipinfo_memory *ram = find_ram(h->chip); uint8_t data[6]; uint8_t mem_write[16]; if (!ram) goto fail; printc_dbg("Calibrate DCO...\n"); w16le(data, ram->offset); w16le(data + 2, max_bcs); if (hal_proto_execute(&h->hal, map_fid(h, HAL_PROTO_FID_GET_DCO_FREQUENCY), data, 6) < 0) goto fail; if (h->hal.length < 6) { printc_err("v3hil: short reply: %d\n", h->hal.length); goto fail; } h->cal.cal0 = r16le(data); h->cal.cal1 = r16le(data + 2); w32le(mem_write, 0x56); /* addr of DCO */ w32le(mem_write + 4, 3); mem_write[8] = data[0]; /* DCO */ mem_write[9] = data[2]; /* BCS1 */ mem_write[10] = data[4]; /* BCS2 */ mem_write[11] = 0; /* pad */ if (hal_proto_execute(&h->hal, map_fid(h, HAL_PROTO_FID_WRITE_MEM_BYTES), mem_write, 12) < 0) { printc_err("v3hil: failed to load DCO settings\n"); goto fail; } return 0; fail: printc_err("v3hil: DCO calibration failed\n"); return -1; } static int calibrate_fll(struct v3hil *h) { const struct chipinfo_memory *ram = find_ram(h->chip); uint8_t data[10]; uint8_t mem_write[16]; if (!ram) goto fail; printc_dbg("Calibrate FLL...\n"); w16le(data, ram->offset); w16le(data + 2, 0); if (hal_proto_execute(&h->hal, map_fid(h, HAL_PROTO_FID_GET_DCO_FREQUENCY), data, 10) < 0) goto fail; if (h->hal.length < 10) { printc_err("v3hil: short reply: %d\n", h->hal.length); goto fail; } h->cal.cal0 = 0; h->cal.cal1 = r16le(data + 2); w32le(mem_write, 0x50); /* addr of SCFI0 */ w32le(mem_write + 4, 5); mem_write[8] = data[0]; /* SCFI0 */ mem_write[9] = data[2]; /* SCFI1 */ mem_write[10] = data[4]; /* SCFQCTL */ mem_write[11] = data[6]; /* FLLCTL0 */ mem_write[12] = data[8]; /* FLLCTL1 */ mem_write[13] = 0; /* pad */ if (hal_proto_execute(&h->hal, map_fid(h, HAL_PROTO_FID_WRITE_MEM_BYTES), mem_write, 14) < 0) { printc_err("v3hil: failed to load FLL settings\n"); goto fail; } return 0; fail: printc_err("v3hil: FLL calibration failed\n"); return -1; } static int calibrate(struct v3hil *h) { int r; if (h->cal.is_cal) return 0; switch (h->chip->clock_sys) { case CHIPINFO_CLOCK_SYS_BC_1XX: r = calibrate_dco(h, 0x7); break; case CHIPINFO_CLOCK_SYS_BC_2XX: r = calibrate_dco(h, 0xf); break; case CHIPINFO_CLOCK_SYS_FLL_PLUS: r = calibrate_fll(h); break; default: r = 0; h->cal.cal0 = 0; h->cal.cal1 = 0; break; } if (r < 0) return -1; h->cal.is_cal = 1; return 0; } static int upload_funclet(struct v3hil *h, const struct chipinfo_memory *ram, const struct chipinfo_funclet *f) { uint32_t addr = ram->offset; const uint16_t *code = f->code; uint16_t num_words = f->code_size; if (num_words * 2 > ram->size) { printc_err("v3hil: funclet too big for RAM\n"); return -1; } while (num_words) { uint8_t data[512]; uint16_t n = num_words > 112 ? 112 : num_words; int i; w32le(data, addr); w32le(data + 4, n); for (i = 0; i < n; i++) w16le(data + 8 + i * 2, code[i]); if (hal_proto_execute(&h->hal, map_fid(h, HAL_PROTO_FID_WRITE_MEM_WORDS), data, n * 2 + 8) < 0) { printc_err("v3hil: funclet upload " "failed at 0x%04x (%d words)\n", addr, n); return -1; } addr += n * 2; code += n; num_words -= n; } return 0; } static int write_flash(struct v3hil *h, address_t addr, const uint8_t *mem, address_t size) { const struct chipinfo_memory *ram = find_ram(h->chip); const struct chipinfo_funclet *f = h->chip->v3_write; uint8_t data[256]; uint16_t avail; if (!ram) return -1; if (!f) { printc_err("v3hil: no funclet defined for flash write\n"); return -1; } if (calibrate(h) < 0) return -1; if (upload_funclet(h, ram, f) < 0) return -1; if (size > 128) size = 128; avail = ram->size - f->code_size * 2; if (avail > f->max_payload) avail = f->max_payload; w16le(data, ram->offset); w16le(data + 2, avail); w16le(data + 4, ram->offset + f->entry_point); w32le(data + 6, addr); w32le(data + 10, size >> 1); w32le(data + 14, 0); /* If FPERM_LOCKED_FLASH is set, info A is UNLOCKED */ w16le(data + 16, (opdb_read_fperm() & FPERM_LOCKED_FLASH) ? 0xa548 : 0xa508); w16le(data + 18, h->cal.cal0); w16le(data + 20, h->cal.cal1); memcpy(data + 22, mem, size); if (hal_proto_execute(&h->hal, map_fid(h, HAL_PROTO_FID_EXECUTE_FUNCLET), data, size + 22) < 0) { printc_err("v3hil: failed to program %d bytes at 0x%04x\n", size, addr); return -1; } return size; } static int write_ram(struct v3hil *h, const struct chipinfo_memory *m, address_t addr, const uint8_t *mem, address_t size) { uint8_t data[256]; w32le(data, addr); w32le(data + 4, (m->bits == 8) ? size : (size >> 1)); memcpy(data + 8, mem, size); if (hal_proto_execute(&h->hal, map_fid(h, (m->bits == 8) ? HAL_PROTO_FID_WRITE_MEM_BYTES : HAL_PROTO_FID_WRITE_MEM_WORDS), data, size + 8) < 0) { printc_err("v3hil: failed writing %d bytes to 0x%05x\n", size, addr); return -1; } return size; } int v3hil_write(struct v3hil *h, address_t addr, const uint8_t *mem, address_t size) { const struct chipinfo_memory *m = NULL; if (h->chip) { size = check_range(h->chip, addr, size, &m); if (!m) return size; } if (size > 128) size = 128; if (m->type == CHIPINFO_MEMTYPE_FLASH) return write_flash(h, addr, mem, size); return write_ram(h, m, addr, mem, size); } static int call_erase(struct v3hil *h, const struct chipinfo_memory *ram, const struct chipinfo_funclet *f, address_t addr, uint16_t type) { uint8_t data[32]; printc_dbg("Erase segment @ 0x%04x\n", addr); w16le(data, ram->offset); w16le(data + 2, 0); w16le(data + 4, ram->offset + f->entry_point); w32le(data + 6, addr); w32le(data + 10, 2); w16le(data + 14, type); w16le(data + 16, (opdb_read_fperm() & FPERM_LOCKED_FLASH) ? 0xa548 : 0xa508); w16le(data + 18, h->cal.cal0); w16le(data + 20, h->cal.cal1); w32le(data + 22, 0xdeadbeef); if (hal_proto_execute(&h->hal, map_fid(h, HAL_PROTO_FID_EXECUTE_FUNCLET), data, 26) < 0) { printc_err("v3hil: failed to erase at 0x%04x\n", addr); return -1; } return 0; } int v3hil_erase(struct v3hil *h, address_t segment) { const struct chipinfo_memory *ram = find_ram(h->chip); const struct chipinfo_funclet *f = h->chip->v3_erase; const struct chipinfo_memory *flash; if (!ram) return -1; if (!f) { printc_err("v3hil: no funclet defined for flash erase\n"); return -1; } if (segment == ADDRESS_NONE) flash = chipinfo_find_mem_by_name(h->chip, "main"); else flash = chipinfo_find_mem_by_addr(h->chip, segment); if (!flash) printc_err("v3hil: can't find appropriate flash region\n"); if (calibrate(h) < 0) return -1; if (upload_funclet(h, ram, f) < 0) return -1; if (segment == ADDRESS_NONE) { int bank_size = flash->size; int i; if (flash->banks) bank_size /= flash->banks; for (i = flash->banks; i >= 0; i--) if (call_erase(h, ram, f, flash->offset + i * bank_size - 2, 0xa502) < 0) return -1; } else { segment &= ~(flash->seg_size - 1); segment |= flash->seg_size - 2; if (call_erase(h, ram, f, segment, 0xa502) < 0) return -1; } return 0; } int v3hil_update_regs(struct v3hil *h) { const hal_proto_fid_t fid = map_fid(h, HAL_PROTO_FID_READ_ALL_CPU_REGS); const int reg_size = (fid == HAL_PROTO_FID_READ_ALL_CPU_REGS) ? 2 : 3; int i; int sptr = 0; if (hal_proto_execute(&h->hal, fid, NULL, 0) < 0) { printc_err("v3hil: can't read CPU registers\n"); return -1; } if (h->hal.length < reg_size * 13) { printc_err("v3hil: short read: %d\n", h->hal.length); return -1; } for (i = 0; i < DEVICE_NUM_REGS; i++){ address_t r = 0; int j; if ((i == MSP430_REG_PC) || (i == MSP430_REG_SR) || (i == MSP430_REG_R3)) continue; for (j = 0; j < reg_size; j++) r |= ((address_t)(h->hal.payload[sptr++])) << (j << 3); h->regs[i] = r; } return 0; } int v3hil_flush_regs(struct v3hil *h) { const hal_proto_fid_t fid = map_fid(h, HAL_PROTO_FID_WRITE_ALL_CPU_REGS); const int reg_size = (fid == HAL_PROTO_FID_WRITE_ALL_CPU_REGS) ? 2 : 3; int i; int dptr = 0; uint8_t data[64]; for (i = 0; i < DEVICE_NUM_REGS; i++){ address_t r = h->regs[i]; int j; if ((i == MSP430_REG_PC) || (i == MSP430_REG_SR) || (i == MSP430_REG_R3)) continue; for (j = 0; j < reg_size; j++) { data[dptr++] = r; r >>= 8; } } if (hal_proto_execute(&h->hal, fid, data, reg_size * 13) < 0) { printc_err("v3hil: can't write CPU registers\n"); return -1; } return 0; } int v3hil_context_restore(struct v3hil *h, int free) { uint8_t data[32]; memset(data, 0, sizeof(data)); data[0] = (h->jtag_id == 0x89) ? 0x20 : 0x5c; /* WDTCTL */ data[1] = 0x01; data[2] = h->wdtctl; data[3] = 0x5a; /* WDTPW */ w32le(data + 4, h->regs[MSP430_REG_PC]); data[8] = h->regs[MSP430_REG_SR]; data[9] = h->regs[MSP430_REG_SR] >> 8; data[10] = free ? 7 : 6; data[14] = free ? 1 : 0; if (hal_proto_execute(&h->hal, map_fid(h, HAL_PROTO_FID_RC_RELEASE_JTAG), data, 18) < 0) { printc_err("v3hil: failed to restore context\n"); return -1; } return 0; } int v3hil_context_save(struct v3hil *h) { uint8_t data[32]; h->cal.is_cal = 0; memset(data, 0, sizeof(data)); data[0] = (h->jtag_id == 0x89) ? 0x20 : 0x5c; /* WDTCTL */ data[1] = 0x01; data[2] = h->wdtctl | 0x80; data[3] = 0x5a; /* WDTPW */ if (hal_proto_execute(&h->hal, map_fid(h, HAL_PROTO_FID_SJ_CONDITIONAL_SC), data, 8) < 0) return -1; if (h->hal.length < 8) { printc_err("v3hil: short reply: %d\n", h->hal.length); return -1; } h->wdtctl = r16le(h->hal.payload); h->regs[MSP430_REG_PC] = r32le(h->hal.payload + 2); h->regs[MSP430_REG_SR] = r16le(h->hal.payload + 6); return 0; } int v3hil_single_step(struct v3hil *h) { uint8_t data[32]; h->cal.is_cal = 0; memset(data, 0, sizeof(data)); data[0] = (h->jtag_id == 0x89) ? 0x20 : 0x5c; /* WDTCTL */ data[1] = 0x01; data[2] = h->wdtctl; data[3] = 0x5a; /* WDTPW */ w32le(data + 4, h->regs[MSP430_REG_PC]); data[8] = h->regs[MSP430_REG_SR]; data[9] = h->regs[MSP430_REG_SR] >> 8; data[10] = 7; if (hal_proto_execute(&h->hal, map_fid(h, HAL_PROTO_FID_SINGLE_STEP), data, 18) < 0) { printc_err("do_step: single-step failed\n"); return -1; } if (h->hal.length < 8) { printc_err("do_step: short reply: %d\n", h->hal.length); return -1; } h->wdtctl = r16le(h->hal.payload); h->regs[MSP430_REG_PC] = r32le(h->hal.payload + 2); h->regs[MSP430_REG_SR] = r16le(h->hal.payload + 6); return 0; } /************************************************************************ * Identification/config */ static int set_param(struct v3hil *fet, hal_proto_config_t cfg, uint32_t value) { uint8_t data[8] = {0}; int i; for (i = 0; i < 4; i++) { data[i + 4] = value; value >>= 8; } data[0] = cfg; if (hal_proto_execute(&fet->hal, HAL_PROTO_FID_CONFIGURE, data, 8) < 0) { printc_err("v3hil: can't set param 0x%02x to 0x%08x\n", cfg, value); return -1; } return 0; } static int idproc_89(struct v3hil *fet, uint32_t id_data_addr, struct chipinfo_id *id) { uint8_t data[32]; printc_dbg("Identify (89)...\n"); printc_dbg("Read device ID bytes at 0x%05x...\n", id_data_addr); memset(data, 0, 8); w32le(data, id_data_addr); data[4] = 8; if (hal_proto_execute(&fet->hal, HAL_PROTO_FID_READ_MEM_WORDS, data, 8) < 0) return -1; if (fet->hal.length < 16) { printc_err("v3hil: short reply: %d\n", fet->hal.length); return -1; } id->ver_id = r16le(fet->hal.payload); id->ver_sub_id = 0; id->revision = r16le(fet->hal.payload + 2); id->fab = fet->hal.payload[3]; id->self = r16le(fet->hal.payload + 4); id->config = fet->hal.payload[13] & 0x7f; printc_dbg("Read fuses...\n"); if (hal_proto_execute(&fet->hal, HAL_PROTO_FID_GET_FUSES, NULL, 0) < 0) return -1; if (!fet->hal.length) { printc_err("v3hil: short reply: %d\n", fet->hal.length); return -1; } id->fuses = fet->hal.payload[0]; return 0; } static int idproc_9x(struct v3hil *fet, uint32_t dev_id_ptr, struct chipinfo_id *id) { uint8_t data[32]; uint8_t info_len; int i; int tlv_size; printc_dbg("Identify (9x)...\n"); printc_dbg("Read device ID bytes at 0x%05x...\n", dev_id_ptr); memset(data, 0, 8); w32le(data, dev_id_ptr); data[4] = 4; if (hal_proto_execute(&fet->hal, HAL_PROTO_FID_READ_MEM_QUICK_XV2, data, 8) < 0) return -1; if (fet->hal.length < 8) { printc_err("v3hil: short reply: %d\n", fet->hal.length); return -1; } info_len = fet->hal.payload[0]; id->ver_id = r16le(fet->hal.payload + 4); id->revision = fet->hal.payload[6]; id->config = fet->hal.payload[7]; id->fab = 0x55; id->self = 0x5555; id->fuses = 0x55; if ((info_len < 1) || (info_len > 11)) return 0; printc_dbg("Read TLV...\n"); tlv_size = ((1 << info_len) - 2) << 2; w32le(data, dev_id_ptr); w32le(data + 4, tlv_size >> 1); w32le(data + 8, fet->regs[MSP430_REG_PC]); if (hal_proto_execute(&fet->hal, HAL_PROTO_FID_READ_MEM_QUICK_XV2, data, 8) < 0) return -1; if (fet->hal.length < tlv_size) { printc_err("v3hil: short reply: %d\n", fet->hal.length); return -1; } /* Search TLV for sub-ID */ i = 8; while (i + 3 < tlv_size) { uint8_t tag = fet->hal.payload[i++]; uint8_t len = fet->hal.payload[i++]; if (tag == 0xff) break; if ((tag == 0x14) && (len >= 2)) id->ver_sub_id = r16le(fet->hal.payload); i += len; } return 0; } int v3hil_identify(struct v3hil *fet) { struct chipinfo_id id; uint32_t dev_id_ptr; uint32_t id_data_addr; int i; printc_dbg("Fetching JTAG ID...\n"); if (hal_proto_execute(&fet->hal, HAL_PROTO_FID_GET_JTAG_ID, NULL, 0) < 0) return -1; if (fet->hal.length < 12) { printc_err("v3hil: short reply: %d\n", fet->hal.length); return -1; } printc_dbg("ID:"); for (i = 0; i < fet->hal.length; i++) printc_dbg(" %02x", fet->hal.payload[i]); printc_dbg("\n"); /* Byte at 0 is JTAG ID. 0x91, 0x95, 0x99 means CPUxV2. 0x89 * means old CPU. */ fet->jtag_id = fet->hal.payload[0]; dev_id_ptr = r32le(fet->hal.payload + 4); id_data_addr = r32le(fet->hal.payload + 8); /* Pick fail-safe configuration */ printc_dbg("Reset parameters...\n"); if (set_param(fet, HAL_PROTO_CONFIG_CLK_CONTROL_TYPE, 0) < 0 || set_param(fet, HAL_PROTO_CONFIG_SFLLDEH, 0) < 0 || set_param(fet, HAL_PROTO_CONFIG_DEFAULT_CLK_CONTROL, 0x040f) || set_param(fet, HAL_PROTO_CONFIG_ENHANCED_PSA, 0) < 0 || set_param(fet, HAL_PROTO_CONFIG_PSA_TCKL_HIGH, 0) < 0 || set_param(fet, HAL_PROTO_CONFIG_POWER_TESTREG_MASK, 0) < 0 || set_param(fet, HAL_PROTO_CONFIG_POWER_TESTREG3V_MASK, 0) < 0 || set_param(fet, HAL_PROTO_CONFIG_NO_BSL, 0) < 0 || set_param(fet, HAL_PROTO_CONFIG_ALT_ROM_ADDR_FOR_CPU_READ, 0) < 0) return -1; printc_dbg("Check JTAG fuse...\n"); if (hal_proto_execute(&fet->hal, HAL_PROTO_FID_IS_JTAG_FUSE_BLOWN, NULL, 0) < 0) return -1; if ((fet->hal.length >= 2) && (fet->hal.payload[0] == 0x55) && (fet->hal.payload[1] == 0x55)) { printc_err("v3hil: JTAG fuse is blown!\n"); return -1; } memset(&id, 0, sizeof(id)); printc_dbg("Sync JTAG...\n"); if (v3hil_sync(fet) < 0) return -1; if (fet->jtag_id == 0x89) { if (idproc_89(fet, id_data_addr, &id) < 0) return -1; } else { if (idproc_9x(fet, dev_id_ptr, &id) < 0) return -1; } printc_dbg(" ver_id: %04x\n", id.ver_id); printc_dbg(" ver_sub_id: %04x\n", id.ver_sub_id); printc_dbg(" revision: %02x\n", id.revision); printc_dbg(" fab: %02x\n", id.fab); printc_dbg(" self: %04x\n", id.self); printc_dbg(" config: %02x\n", id.config); printc_dbg(" fuses: %02x\n", id.fuses); printc_dbg(" activation_key: %08x\n", id.activation_key); fet->chip = chipinfo_find_by_id(&id); if (!fet->chip) { printc_err("v3hil: unknown chip ID\n"); return -1; } return 0; } int v3hil_configure(struct v3hil *fet) { printc_dbg("Configuring for %s...\n", fet->chip->name); if (set_param(fet, HAL_PROTO_CONFIG_CLK_CONTROL_TYPE, fet->chip->clock_control) < 0 || set_param(fet, HAL_PROTO_CONFIG_SFLLDEH, (fet->chip->features & CHIPINFO_FEATURE_SFLLDH) ? 1 : 0) < 0 || set_param(fet, HAL_PROTO_CONFIG_DEFAULT_CLK_CONTROL, fet->chip->mclk_control) < 0 || set_param(fet, HAL_PROTO_CONFIG_ENHANCED_PSA, (fet->chip->psa == CHIPINFO_PSA_ENHANCED) ? 1 : 0) < 0 || set_param(fet, HAL_PROTO_CONFIG_PSA_TCKL_HIGH, (fet->chip->features & CHIPINFO_FEATURE_PSACH) ? 1 : 0) < 0 || set_param(fet, HAL_PROTO_CONFIG_POWER_TESTREG_MASK, fet->chip->power.reg_mask) < 0 || set_param(fet, HAL_PROTO_CONFIG_TESTREG_ENABLE_LPMX5, fet->chip->power.enable_lpm5) < 0 || set_param(fet, HAL_PROTO_CONFIG_TESTREG_DISABLE_LPMX5, fet->chip->power.disable_lpm5) < 0 || set_param(fet, HAL_PROTO_CONFIG_POWER_TESTREG3V_MASK, fet->chip->power.reg_mask_3v) < 0 || set_param(fet, HAL_PROTO_CONFIG_TESTREG3V_ENABLE_LPMX5, fet->chip->power.enable_lpm5_3v) < 0 || set_param(fet, HAL_PROTO_CONFIG_TESTREG3V_DISABLE_LPMX5, fet->chip->power.disable_lpm5_3v) < 0 || set_param(fet, HAL_PROTO_CONFIG_NO_BSL, (fet->chip->features & CHIPINFO_FEATURE_NO_BSL) ? 1 : 0) < 0 || set_param(fet, HAL_PROTO_CONFIG_ALT_ROM_ADDR_FOR_CPU_READ, (fet->chip->features & CHIPINFO_FEATURE_1337) ? 1 : 0) < 0) return -1; return 0; } mspdebug-0.25/drivers/v3hil.h000066400000000000000000000063211313531517500161300ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef V3HIL_H_ #define V3HIL_H_ #include "hal_proto.h" #include "chipinfo.h" #include "util.h" #include "device.h" #include "transport.h" /* Clock calibration data */ struct v3hil_calibrate { uint8_t is_cal; /* Calibration parameters for write/erase funclets */ uint16_t cal0; uint16_t cal1; }; struct v3hil { struct hal_proto hal; const struct chipinfo *chip; /* 0x89 is old-style CPU */ uint8_t jtag_id; /* Lower 8 bits of saved WDTCTL */ uint8_t wdtctl; /* Register cache: this must be flushed before restoring context * and updated after saving context. */ address_t regs[DEVICE_NUM_REGS]; struct v3hil_calibrate cal; }; /* Initialize data, associate transport */ void v3hil_init(struct v3hil *h, transport_t trans, hal_proto_flags_t flags); /* Reset communications and probe HAL. */ int v3hil_comm_init(struct v3hil *h); /* Set voltage */ int v3hil_set_vcc(struct v3hil *h, int vcc_mv); /* Start/stop JTAG controller */ typedef enum { V3HIL_JTAG_JTAG = 0, V3HIL_JTAG_SPYBIWIRE = 1 } v3hil_jtag_type_t; int v3hil_start_jtag(struct v3hil *h, v3hil_jtag_type_t); int v3hil_stop_jtag(struct v3hil *h); /* Synchronize JTAG and reset the chip. This is the only operation which * can be done pre-configuration. */ int v3hil_sync(struct v3hil *h); /* Run the chip identification procedure. chip will be filled out if * this is successful. This calls v3hil_sync(). */ int v3hil_identify(struct v3hil *h); /* Configure for the current chip */ int v3hil_configure(struct v3hil *h); /* Read/write memory. LSB of address and size are ignored. Number of * bytes read is returned, which may be less than requested if a memory * map boundary is crossed. */ int v3hil_read(struct v3hil *h, address_t addr, uint8_t *mem, address_t size); int v3hil_write(struct v3hil *h, address_t addr, const uint8_t *mem, address_t size); /* Erase flash. If address is specified, a segment erase is performed. * Otherwise, ADDRESS_NONE indicates that a main memory erase should be * performed. */ int v3hil_erase(struct v3hil *h, address_t segment); /* Read/write register cache. */ int v3hil_update_regs(struct v3hil *h); int v3hil_flush_regs(struct v3hil *h); /* Restore context (run) and save context (halt). */ int v3hil_context_restore(struct v3hil *h, int free); int v3hil_context_save(struct v3hil *h); /* Single-step the CPU. You must handle the register cache yourself. */ int v3hil_single_step(struct v3hil *h); #endif mspdebug-0.25/formats/000077500000000000000000000000001313531517500147255ustar00rootroot00000000000000mspdebug-0.25/formats/binfile.c000066400000000000000000000050441313531517500165040ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include "util.h" #include "binfile.h" #include "ihex.h" #include "elf32.h" #include "symmap.h" #include "titext.h" #include "srec.h" #include "coff.h" #include "output.h" struct file_format { int (*check)(FILE *in); int (*extract)(FILE *in, binfile_imgcb_t cb, void *user_data); int (*syms)(FILE *in); }; static const struct file_format formats[] = { { .check = elf32_check, .extract = elf32_extract, .syms = elf32_syms }, { .check = ihex_check, .extract = ihex_extract }, { .check = symmap_check, .syms = symmap_syms }, { .check = titext_check, .extract = titext_extract }, { .check = srec_check, .extract = srec_extract }, { .check = coff_check, .extract = coff_extract, .syms = coff_syms } }; static const struct file_format *identify(FILE *in) { int i; for (i = 0; i < ARRAY_LEN(formats); i++) { const struct file_format *f = &formats[i]; if (f->check(in) > 0) return f; } return NULL; } int binfile_info(FILE *in) { const struct file_format *fmt = identify(in); int flags = 0; if (fmt) { if (fmt->extract) flags |= BINFILE_HAS_TEXT; if (fmt->syms) flags |= BINFILE_HAS_SYMS; } return flags; } int binfile_extract(FILE *in, binfile_imgcb_t cb, void *user_data) { const struct file_format *fmt = identify(in); if (!fmt) { printc_err("binfile: unknown file format\n"); return -1; } if (!fmt->extract) { printc_err("binfile: this format contains no code\n"); return -1; } return fmt->extract(in, cb, user_data); } int binfile_syms(FILE *in) { const struct file_format *fmt = identify(in); if (!fmt) { printc_err("binfile: unknown file format\n"); return -1; } if (!fmt->syms) { printc_err("binfile: this format contains no symbols\n"); return -1; } return fmt->syms(in); } mspdebug-0.25/formats/binfile.h000066400000000000000000000035161313531517500165130ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef BINFILE_H_ #define BINFILE_H_ #include #include #include "stab.h" struct binfile_chunk { const char *name; address_t addr; const uint8_t *data; int len; }; /* Callback for binary image data */ typedef int (*binfile_imgcb_t)(void *user_data, const struct binfile_chunk *ch); #define BINFILE_HAS_SYMS 0x01 #define BINFILE_HAS_TEXT 0x02 /* Examine the given file and figure out what it contains. If the file * type is unknown, 0 is returned. If an IO error occurs, -1 is * returned. Otherwise, the return value is a positive integer * bitmask. */ int binfile_info(FILE *in); /* If possible, extract the text from this file, feeding it in chunks * of an indeterminate size to the callback given. * * Returns 0 if successful, -1 if an error occurs. */ int binfile_extract(FILE *in, binfile_imgcb_t cb, void *user_data); /* Attempt to load symbols from the file and store them in the given * symbol table. Returns 0 on success or -1 if an error occurs. */ int binfile_syms(FILE *in); #endif mspdebug-0.25/formats/coff.c000066400000000000000000000213141313531517500160070ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include "coff.h" #include "util.h" #include "output.h" struct coff_header { uint16_t version; int sec_count; uint32_t timestamp; int stab_start; int stab_count; int opt_bytes; uint16_t flags; uint16_t target_id; }; /* Header sizes */ #define FILE_HEADER_SIZE 22 #define OPT_HEADER_SIZE 28 #define SHDR_SIZE 48 #define STAB_ENTRY_SIZE 18 /* Bits in the flags field */ #define F_RELFLG 0x0001 #define F_EXEC 0x0002 #define F_LSYMS 0x0008 #define F_LITTLE 0x0100 #define F_BIG 0x0200 #define F_SYMMERGE 0x1000 /* Section header flags */ #define STYP_REG 0x00000000 #define STYP_DSECT 0x00000001 #define STYP_NOLOAD 0x00000002 #define STYP_GROUP 0x00000004 #define STYP_PAD 0x00000008 #define STYP_COPY 0x00000010 #define STYP_TEXT 0x00000020 #define STYP_DATA 0x00000040 #define STYP_BSS 0x00000080 #define STYP_BLOCK 0x00001000 #define STYP_PASS 0x00002000 #define STYP_CLINK 0x00004000 #define STYP_VECTOR 0x00008000 #define STYP_PADDED 0x00010000 /* Symbol storage classes */ #define C_NULL 0 #define C_AUTO 1 #define C_EXT 2 #define C_STAT 3 #define C_REG 4 #define C_EXTREF 5 #define C_LABEL 6 #define C_ULABEL 7 #define C_MOS 8 #define C_ARG 9 #define C_STRTAG 10 #define C_MOU 11 #define C_UNTAG 12 #define C_TPDEF 13 #define C_USTATIC 14 #define C_ENTAG 15 #define C_MOE 16 #define C_REGPARM 17 #define C_FIELD 18 #define C_UEXT 19 #define C_STATLAB 20 #define C_EXTLAB 21 #define C_VARARG 22 #define C_BLOCK 100 #define C_FCN 101 #define C_EOS 102 #define C_FILE 103 #define C_LINE 104 /* MSP430 magic number */ #define MSP430_MAGIC 0x00a0 static int read_block(FILE *in, int offset, int size, void *buf) { int len; if (size < 0) { printc_err("coff: invalid size: %d\n", size); return -1; } if (fseek(in, offset, SEEK_SET) < 0) { printc_err("coff: can't seek to offset %d: %s\n", offset, last_error()); return -1; } len = fread(buf, 1, size, in); if (len < 0) { printc_err("coff: can't read %d bytes from " "offset %d: %s\n", size, offset, last_error()); return -1; } if (len < size) { printc_err("coff: can't read %d bytes from " "offset %d: short read\n", size, offset); return -1; } return 0; } static void parse_header(const uint8_t *data, struct coff_header *hdr) { hdr->version = LE_WORD(data, 0); hdr->sec_count = LE_WORD(data, 2); hdr->timestamp = LE_LONG(data, 4); hdr->stab_start = LE_LONG(data, 8); hdr->stab_count = LE_LONG(data, 12); hdr->opt_bytes = LE_WORD(data, 16); hdr->flags = LE_WORD(data, 18); hdr->target_id = LE_WORD(data, 20); } static int read_header(FILE *in, struct coff_header *hdr) { uint8_t hdr_data[FILE_HEADER_SIZE]; if (read_block(in, 0, FILE_HEADER_SIZE, hdr_data) < 0) { printc_err("coff: failed to extract COFF header\n"); return -1; } parse_header(hdr_data, hdr); return 0; } int coff_check(FILE *in) { uint8_t data[FILE_HEADER_SIZE]; rewind(in); if (fread(data, 1, FILE_HEADER_SIZE, in) != FILE_HEADER_SIZE) return 0; return data[20] == 0xa0 && !data[21]; } static int read_sechdrs(FILE *in, const struct coff_header *hdr, uint8_t **ret_tab) { uint8_t *table; int alloc_size = SHDR_SIZE * hdr->sec_count; if (!hdr->sec_count) { *ret_tab = NULL; return 0; } table = malloc(alloc_size); if (!table) { pr_error("coff: can't allocate memory for section headers"); return -1; } if (read_block(in, hdr->opt_bytes + FILE_HEADER_SIZE, SHDR_SIZE * hdr->sec_count, table) < 0) { printc_err("coff: can't read section headers\n"); free(table); return -1; } *ret_tab = table; return hdr->sec_count; } static int load_section(FILE *in, uint32_t addr, uint32_t offset, uint32_t size, binfile_imgcb_t cb, void *user_data) { struct binfile_chunk ch = {0}; uint8_t *section; if (!size) return 0; section = malloc(size); if (!section) { printc_err("coff: couldn't allocate memory for " "section at 0x%x: %s\n", offset, last_error()); return -1; } if (read_block(in, offset, size, section) < 0) { printc_err("coff: couldn't read section at 0x%x\n", offset); free(section); return -1; } ch.addr = addr; ch.len = size; ch.data = section; if (cb(user_data, &ch) < 0) { free(section); return -1; } free(section); return 0; } int coff_extract(FILE *in, binfile_imgcb_t cb, void *user_data) { struct coff_header hdr; uint8_t *shdrs; int ret = 0; int i; if (read_header(in, &hdr) < 0) return -1; if (read_sechdrs(in, &hdr, &shdrs) < 0) return -1; for (i = 0; i < hdr.sec_count; i++) { uint8_t *header = shdrs + SHDR_SIZE * i; uint32_t flags = LE_LONG(header, 40); if (((flags & STYP_TEXT) || (flags & STYP_DATA)) && !(flags & STYP_NOLOAD)) { uint32_t addr = LE_LONG(header, 8); uint32_t offset = LE_LONG(header, 20); uint32_t size = LE_LONG(header, 16); if (load_section(in, addr, offset, size, cb, user_data) < 0) { printc_err("coff: error while loading " "section %d\n", i); ret = -1; break; } } } if (shdrs) free(shdrs); return ret; } static int read_strtab(FILE *in, const struct coff_header *hdr, char **ret_tab) { char *strtab; int file_size; int alloc_size; int strtab_len; int strtab_start = hdr->stab_count * STAB_ENTRY_SIZE + hdr->stab_start; if (fseek(in, 0, SEEK_END) < 0) { printc_err("coff: can't seek to end\n"); return -1; } file_size = ftell(in); strtab_len = file_size - strtab_start; if (strtab_len < 0) { printc_err("coff: invalid string table size\n"); return -1; } if (!strtab_len) { *ret_tab = NULL; return 0; } alloc_size = strtab_len + 1; strtab = malloc(alloc_size); if (!strtab) { pr_error("coff: can't allocate memory for string table"); return -1; } if (read_block(in, strtab_start, strtab_len, strtab) < 0) { printc_err("coff: failed to read string table\n"); free(strtab); return -1; } strtab[strtab_len] = 0; *ret_tab = strtab; return strtab_len; } static int read_symtab(FILE *in, const struct coff_header *hdr, uint8_t **ret_tab) { uint8_t *table; int alloc_size = STAB_ENTRY_SIZE * hdr->stab_count; if (!hdr->stab_count) { *ret_tab = NULL; return 0; } table = malloc(alloc_size); if (!table) { pr_error("coff: failed to allocate memory for symbol table"); return -1; } if (read_block(in, hdr->stab_start, STAB_ENTRY_SIZE * hdr->stab_count, table) < 0) { printc_err("coff: failed to read symbol table\n"); free(table); return -1; } *ret_tab = table; return hdr->stab_count; } int coff_syms(FILE *in) { struct coff_header hdr; char *strtab; uint8_t *symtab; int strtab_len; int i; int ret = 0; if (read_header(in, &hdr) < 0) return -1; strtab_len = read_strtab(in, &hdr, &strtab); if (strtab_len < 0) return -1; if (read_symtab(in, &hdr, &symtab) < 0) { if (strtab) free(strtab); return -1; } for (i = 0; i < hdr.stab_count; i++) { uint8_t *entry = symtab + i * STAB_ENTRY_SIZE; uint32_t value = LE_LONG(entry, 8); int storage_class = entry[16]; char namebuf[9]; const char *name = NULL; if (LE_LONG(entry, 0)) { memcpy(namebuf, entry, 8); namebuf[8] = 0; name = namebuf; } else { uint32_t offset = LE_LONG(entry, 4); if (offset >= 4 && offset < strtab_len) name = strtab + offset; } if (name && (storage_class == C_EXT || storage_class == C_LABEL) && stab_set(name, value) < 0) { printc_err("coff: failed to insert symbol\n"); ret = -1; break; } /* Skip auxiliary entries */ i += entry[17]; } if (symtab) free(symtab); if (strtab) free(strtab); return ret; } mspdebug-0.25/formats/coff.h000066400000000000000000000017321313531517500160160ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef COFF_H_ #define COFF_H_ #include "binfile.h" int coff_check(FILE *in); int coff_extract(FILE *in, binfile_imgcb_t cb, void *user_data); int coff_syms(FILE *in); #endif mspdebug-0.25/formats/elf32.c000066400000000000000000000222101313531517500160010ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include "elf32.h" #include "elf_format.h" #include "output.h" #include "util.h" #ifndef EM_MSP430 #define EM_MSP430 0x69 #endif static const uint8_t elf32_id[] = { ELFMAG0, ELFMAG1, ELFMAG2, ELFMAG3, ELFCLASS32 }; #define MAX_PHDRS 32 #define MAX_SHDRS 128 struct elf32_info { Elf32_Ehdr file_ehdr; Elf32_Phdr file_phdrs[MAX_PHDRS]; Elf32_Shdr file_shdrs[MAX_SHDRS]; char *string_tab; int string_len; }; static int parse_ehdr(Elf32_Ehdr *e, FILE *in) { uint8_t data[52]; if (fread(data, sizeof(data), 1, in) != 1) return -1; memcpy(e->e_ident, data, EI_NIDENT); e->e_type = LE_WORD(data, 16); e->e_machine = LE_WORD(data, 18); e->e_version = LE_LONG(data, 20); e->e_entry = LE_LONG(data, 24); e->e_phoff = LE_LONG(data, 28); e->e_shoff = LE_LONG(data, 32); e->e_flags = LE_LONG(data, 36); e->e_ehsize = LE_WORD(data, 40); e->e_phentsize = LE_WORD(data, 42); e->e_phnum = LE_WORD(data, 44); e->e_shentsize = LE_WORD(data, 46); e->e_shnum = LE_WORD(data, 48); e->e_shstrndx = LE_WORD(data, 50); return 0; } static int parse_phdr(Elf32_Phdr *p, FILE *in) { uint8_t data[32]; if (fread(data, sizeof(data), 1, in) != 1) return -1; p->p_type = LE_LONG(data, 0); p->p_offset = LE_LONG(data, 4); p->p_vaddr = LE_LONG(data, 8); p->p_paddr = LE_LONG(data, 12); p->p_filesz = LE_LONG(data, 16); p->p_memsz = LE_LONG(data, 20); p->p_flags = LE_LONG(data, 24); p->p_align = LE_LONG(data, 28); return 0; } static int parse_shdr(Elf32_Shdr *s, FILE *in) { uint8_t data[40]; if (fread(data, sizeof(data), 1, in) != 1) return -1; s->sh_name = LE_LONG(data, 0); s->sh_type = LE_LONG(data, 4); s->sh_flags = LE_LONG(data, 8); s->sh_addr = LE_LONG(data, 12); s->sh_offset = LE_LONG(data, 16); s->sh_size = LE_LONG(data, 20); s->sh_link = LE_LONG(data, 24); s->sh_info = LE_LONG(data, 28); s->sh_addralign = LE_LONG(data, 32); s->sh_entsize = LE_LONG(data, 36); return 0; } static int parse_sym(Elf32_Sym *s, FILE *in) { uint8_t data[16]; if (fread(data, sizeof(data), 1, in) != 1) return -1; s->st_name = LE_LONG(data, 0); s->st_value = LE_LONG(data, 4); s->st_size = LE_LONG(data, 8); s->st_info = data[12]; s->st_other = data[13]; s->st_shndx = LE_WORD(data, 14); return 0; } static int read_ehdr(struct elf32_info *info, FILE *in) { /* Read and check the ELF header */ rewind(in); if (parse_ehdr(&info->file_ehdr, in) < 0) { pr_error("elf32: couldn't read ELF header"); return -1; } if (memcmp(info->file_ehdr.e_ident, elf32_id, sizeof(elf32_id))) { printc_err("elf32: not an ELF32 file\n"); return -1; } return 0; } static int read_phdr(struct elf32_info *info, FILE *in) { int i; if (info->file_ehdr.e_phnum > MAX_PHDRS) { printc_err("elf32: too many program headers: %d\n", info->file_ehdr.e_phnum); return -1; } for (i = 0; i < info->file_ehdr.e_phnum; i++) { if (fseek(in, i * info->file_ehdr.e_phentsize + info->file_ehdr.e_phoff, SEEK_SET) < 0) { printc_err("elf32: can't seek to phdr %d\n", i); return -1; } if (parse_phdr(&info->file_phdrs[i], in) < 0) { printc_err("elf32: can't read phdr %d: %s\n", i, last_error()); return -1; } } return 0; } static int read_shdr(struct elf32_info *info, FILE *in) { int i; if (info->file_ehdr.e_shnum > MAX_SHDRS) { printc_err("elf32: too many section headers: %d\n", info->file_ehdr.e_shnum); return -1; } for (i = 0; i < info->file_ehdr.e_shnum; i++) { if (fseek(in, i * info->file_ehdr.e_shentsize + info->file_ehdr.e_shoff, SEEK_SET) < 0) { printc_err("elf32: can't seek to shdr %d\n", i); return -1; } if (parse_shdr(&info->file_shdrs[i], in) < 0) { printc_err("elf32: can't read shdr %d: %s\n", i, last_error()); return -1; } } return 0; } static uint32_t file_to_phys(struct elf32_info *info, uint32_t v) { int i; for (i = 0; i < info->file_ehdr.e_phnum; i++) { Elf32_Phdr *p = &info->file_phdrs[i]; if (v >= p->p_offset && v - p->p_offset < p->p_filesz) return v - p->p_offset + p->p_paddr; } return v; } static int feed_section(struct elf32_info *info, FILE *in, const Elf32_Shdr *sh, binfile_imgcb_t cb, void *user_data) { uint32_t offset = sh->sh_offset; uint32_t size = sh->sh_size; uint8_t buf[1024]; uint32_t addr = file_to_phys(info, offset); const char *name = NULL; if (fseek(in, offset, SEEK_SET) < 0) { pr_error("elf32: can't seek to section"); return -1; } if (info->string_tab && sh->sh_name < info->string_len) name = info->string_tab + sh->sh_name; while (size) { int ask = size > sizeof(buf) ? sizeof(buf) : size; int len = fread(buf, 1, ask, in); struct binfile_chunk ch = {0}; if (len < 0) { pr_error("elf32: can't read section"); return -1; } ch.name = name; ch.addr = addr; ch.data = buf; ch.len = len; if (cb(user_data, &ch) < 0) return -1; size -= len; offset += len; addr += len; } return 0; } static int read_all(struct elf32_info *info, FILE *in) { memset(info, 0, sizeof(*info)); if (read_ehdr(info, in) < 0) return -1; if (info->file_ehdr.e_machine != EM_MSP430) printc_err("elf32: warning: unknown machine type: 0x%x\n", info->file_ehdr.e_machine); if (read_phdr(info, in) < 0) return -1; if (read_shdr(info, in) < 0) return -1; return 0; } static int load_strings(struct elf32_info *info, FILE *in, Elf32_Shdr *s) { int len = s->sh_size; if (!len) return 0; if (fseek(in, s->sh_offset, SEEK_SET) < 0) { pr_error("elf32: can't seek to strings"); return -1; } info->string_len = len; info->string_tab = malloc(len + 1); if (!info->string_tab) { pr_error("elf32: can't allocate string table memory"); return -1; } if (!fread(info->string_tab, info->string_len, 1, in)) { if (ferror(in)) { pr_error("elf32: error reading strings"); return -1; } printc_err("elf32: eof reading strings\n"); return -1; } info->string_tab[info->string_len] = 0; return 0; } int elf32_extract(FILE *in, binfile_imgcb_t cb, void *user_data) { struct elf32_info info; int i; int ret = 0; if (read_all(&info, in) < 0) return -1; if (load_strings(&info, in, &info.file_shdrs[info.file_ehdr.e_shstrndx]) < 0) { printc_err("elf32: warning: can't load section string " "table\n"); info.string_tab = NULL; } for (i = 0; i < info.file_ehdr.e_shnum; i++) { Elf32_Shdr *s = &info.file_shdrs[i]; if (s->sh_type == SHT_PROGBITS && s->sh_flags & SHF_ALLOC && feed_section(&info, in, s, cb, user_data) < 0) { ret = -1; break; } } if (info.string_tab) free(info.string_tab); return ret; } int elf32_check(FILE *in) { int i; rewind(in); for (i = 0; i < sizeof(elf32_id); i++) if (fgetc(in) != elf32_id[i]) return 0; return 1; } static Elf32_Shdr *find_shdr(struct elf32_info *info, Elf32_Word type) { int i; for (i = 0; i < info->file_ehdr.e_shnum; i++) { Elf32_Shdr *s = &info->file_shdrs[i]; if (s->sh_type == type) return s; } return NULL; } #define N_SYMS 128 #ifndef STT_COMMON #define STT_COMMON 5 #endif static int syms_load_syms(struct elf32_info *info, FILE *in, Elf32_Shdr *s) { int len = s->sh_size / 16; int i; if (fseek(in, s->sh_offset, SEEK_SET) < 0) { pr_error("elf32: can't seek to symbols"); return -1; } for (i = 0; i < len; i++) { Elf32_Sym y; int st; const char *name; if (parse_sym(&y, in) < 0) { pr_error("elf32: error reading symbols"); return -1; } st = ELF32_ST_TYPE(y.st_info); name = info->string_tab + y.st_name; if (y.st_name > info->string_len) { printc_err("elf32: symbol out of bounds\n"); return -1; } if (name[0] && (st == STT_OBJECT || st == STT_FUNC || st == STT_SECTION || st == STT_COMMON || st == STT_TLS) && stab_set(info->string_tab + y.st_name, y.st_value) < 0) return -1; } return 0; } int elf32_syms(FILE *in) { struct elf32_info info; Elf32_Shdr *s; int ret = 0; if (read_all(&info, in) < 0) return -1; s = find_shdr(&info, SHT_SYMTAB); if (!s) { printc_err("elf32: no symbol table\n"); return -1; } if (s->sh_link <= 0 || s->sh_link >= info.file_ehdr.e_shnum) { printc_err("elf32: no string table\n"); return -1; } if (load_strings(&info, in, &info.file_shdrs[s->sh_link]) < 0 || syms_load_syms(&info, in, s) < 0) ret = -1; if (info.string_tab) free(info.string_tab); return ret; } mspdebug-0.25/formats/elf32.h000066400000000000000000000017351313531517500160170ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef ELF32_H_ #define ELF32_H_ #include "binfile.h" int elf32_check(FILE *in); int elf32_extract(FILE *in, binfile_imgcb_t cb, void *user_data); int elf32_syms(FILE *in); #endif mspdebug-0.25/formats/elf_format.h000066400000000000000000003421601313531517500172220ustar00rootroot00000000000000/* This file defines standard ELF types, structures, and macros. Copyright (C) 1995-2003,2004,2005,2006,2007,2008,2009 Free Software Foundation, Inc. This file is part of the GNU C Library. The GNU C Library is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) any later version. The GNU C Library is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details. You should have received a copy of the GNU Lesser General Public License along with the GNU C Library; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. */ #ifndef _ELF_H #define _ELF_H 1 /* Standard ELF types. */ #include /* Type for a 16-bit quantity. */ typedef uint16_t Elf32_Half; typedef uint16_t Elf64_Half; /* Types for signed and unsigned 32-bit quantities. */ typedef uint32_t Elf32_Word; typedef int32_t Elf32_Sword; typedef uint32_t Elf64_Word; typedef int32_t Elf64_Sword; /* Types for signed and unsigned 64-bit quantities. */ typedef uint64_t Elf32_Xword; typedef int64_t Elf32_Sxword; typedef uint64_t Elf64_Xword; typedef int64_t Elf64_Sxword; /* Type of addresses. */ typedef uint32_t Elf32_Addr; typedef uint64_t Elf64_Addr; /* Type of file offsets. */ typedef uint32_t Elf32_Off; typedef uint64_t Elf64_Off; /* Type for section indices, which are 16-bit quantities. */ typedef uint16_t Elf32_Section; typedef uint16_t Elf64_Section; /* Type for version symbol information. */ typedef Elf32_Half Elf32_Versym; typedef Elf64_Half Elf64_Versym; /* The ELF file header. This appears at the start of every ELF file. */ #define EI_NIDENT (16) typedef struct { unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ Elf32_Half e_type; /* Object file type */ Elf32_Half e_machine; /* Architecture */ Elf32_Word e_version; /* Object file version */ Elf32_Addr e_entry; /* Entry point virtual address */ Elf32_Off e_phoff; /* Program header table file offset */ Elf32_Off e_shoff; /* Section header table file offset */ Elf32_Word e_flags; /* Processor-specific flags */ Elf32_Half e_ehsize; /* ELF header size in bytes */ Elf32_Half e_phentsize; /* Program header table entry size */ Elf32_Half e_phnum; /* Program header table entry count */ Elf32_Half e_shentsize; /* Section header table entry size */ Elf32_Half e_shnum; /* Section header table entry count */ Elf32_Half e_shstrndx; /* Section header string table index */ } Elf32_Ehdr; typedef struct { unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ Elf64_Half e_type; /* Object file type */ Elf64_Half e_machine; /* Architecture */ Elf64_Word e_version; /* Object file version */ Elf64_Addr e_entry; /* Entry point virtual address */ Elf64_Off e_phoff; /* Program header table file offset */ Elf64_Off e_shoff; /* Section header table file offset */ Elf64_Word e_flags; /* Processor-specific flags */ Elf64_Half e_ehsize; /* ELF header size in bytes */ Elf64_Half e_phentsize; /* Program header table entry size */ Elf64_Half e_phnum; /* Program header table entry count */ Elf64_Half e_shentsize; /* Section header table entry size */ Elf64_Half e_shnum; /* Section header table entry count */ Elf64_Half e_shstrndx; /* Section header string table index */ } Elf64_Ehdr; /* Fields in the e_ident array. The EI_* macros are indices into the array. The macros under each EI_* macro are the values the byte may have. */ #define EI_MAG0 0 /* File identification byte 0 index */ #define ELFMAG0 0x7f /* Magic number byte 0 */ #define EI_MAG1 1 /* File identification byte 1 index */ #define ELFMAG1 'E' /* Magic number byte 1 */ #define EI_MAG2 2 /* File identification byte 2 index */ #define ELFMAG2 'L' /* Magic number byte 2 */ #define EI_MAG3 3 /* File identification byte 3 index */ #define ELFMAG3 'F' /* Magic number byte 3 */ /* Conglomeration of the identification bytes, for easy testing as a word. */ #define ELFMAG "\177ELF" #define SELFMAG 4 #define EI_CLASS 4 /* File class byte index */ #define ELFCLASSNONE 0 /* Invalid class */ #define ELFCLASS32 1 /* 32-bit objects */ #define ELFCLASS64 2 /* 64-bit objects */ #define ELFCLASSNUM 3 #define EI_DATA 5 /* Data encoding byte index */ #define ELFDATANONE 0 /* Invalid data encoding */ #define ELFDATA2LSB 1 /* 2's complement, little endian */ #define ELFDATA2MSB 2 /* 2's complement, big endian */ #define ELFDATANUM 3 #define EI_VERSION 6 /* File version byte index */ /* Value must be EV_CURRENT */ #define EI_OSABI 7 /* OS ABI identification */ #define ELFOSABI_NONE 0 /* UNIX System V ABI */ #define ELFOSABI_SYSV 0 /* Alias. */ #define ELFOSABI_HPUX 1 /* HP-UX */ #define ELFOSABI_NETBSD 2 /* NetBSD. */ #define ELFOSABI_LINUX 3 /* Linux. */ #define ELFOSABI_SOLARIS 6 /* Sun Solaris. */ #define ELFOSABI_AIX 7 /* IBM AIX. */ #define ELFOSABI_IRIX 8 /* SGI Irix. */ #define ELFOSABI_FREEBSD 9 /* FreeBSD. */ #define ELFOSABI_TRU64 10 /* Compaq TRU64 UNIX. */ #define ELFOSABI_MODESTO 11 /* Novell Modesto. */ #define ELFOSABI_OPENBSD 12 /* OpenBSD. */ #define ELFOSABI_ARM 97 /* ARM */ #define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */ #define EI_ABIVERSION 8 /* ABI version */ #define EI_PAD 9 /* Byte index of padding bytes */ /* Legal values for e_type (object file type). */ #define ET_NONE 0 /* No file type */ #define ET_REL 1 /* Relocatable file */ #define ET_EXEC 2 /* Executable file */ #define ET_DYN 3 /* Shared object file */ #define ET_CORE 4 /* Core file */ #define ET_NUM 5 /* Number of defined types */ #define ET_LOOS 0xfe00 /* OS-specific range start */ #define ET_HIOS 0xfeff /* OS-specific range end */ #define ET_LOPROC 0xff00 /* Processor-specific range start */ #define ET_HIPROC 0xffff /* Processor-specific range end */ /* Legal values for e_machine (architecture). */ #define EM_NONE 0 /* No machine */ #define EM_M32 1 /* AT&T WE 32100 */ #define EM_SPARC 2 /* SUN SPARC */ #define EM_386 3 /* Intel 80386 */ #define EM_68K 4 /* Motorola m68k family */ #define EM_88K 5 /* Motorola m88k family */ #define EM_860 7 /* Intel 80860 */ #define EM_MIPS 8 /* MIPS R3000 big-endian */ #define EM_S370 9 /* IBM System/370 */ #define EM_MIPS_RS3_LE 10 /* MIPS R3000 little-endian */ #define EM_PARISC 15 /* HPPA */ #define EM_VPP500 17 /* Fujitsu VPP500 */ #define EM_SPARC32PLUS 18 /* Sun's "v8plus" */ #define EM_960 19 /* Intel 80960 */ #define EM_PPC 20 /* PowerPC */ #define EM_PPC64 21 /* PowerPC 64-bit */ #define EM_S390 22 /* IBM S390 */ #define EM_V800 36 /* NEC V800 series */ #define EM_FR20 37 /* Fujitsu FR20 */ #define EM_RH32 38 /* TRW RH-32 */ #define EM_RCE 39 /* Motorola RCE */ #define EM_ARM 40 /* ARM */ #define EM_FAKE_ALPHA 41 /* Digital Alpha */ #define EM_SH 42 /* Hitachi SH */ #define EM_SPARCV9 43 /* SPARC v9 64-bit */ #define EM_TRICORE 44 /* Siemens Tricore */ #define EM_ARC 45 /* Argonaut RISC Core */ #define EM_H8_300 46 /* Hitachi H8/300 */ #define EM_H8_300H 47 /* Hitachi H8/300H */ #define EM_H8S 48 /* Hitachi H8S */ #define EM_H8_500 49 /* Hitachi H8/500 */ #define EM_IA_64 50 /* Intel Merced */ #define EM_MIPS_X 51 /* Stanford MIPS-X */ #define EM_COLDFIRE 52 /* Motorola Coldfire */ #define EM_68HC12 53 /* Motorola M68HC12 */ #define EM_MMA 54 /* Fujitsu MMA Multimedia Accelerator*/ #define EM_PCP 55 /* Siemens PCP */ #define EM_NCPU 56 /* Sony nCPU embeeded RISC */ #define EM_NDR1 57 /* Denso NDR1 microprocessor */ #define EM_STARCORE 58 /* Motorola Start*Core processor */ #define EM_ME16 59 /* Toyota ME16 processor */ #define EM_ST100 60 /* STMicroelectronic ST100 processor */ #define EM_TINYJ 61 /* Advanced Logic Corp. Tinyj emb.fam*/ #define EM_X86_64 62 /* AMD x86-64 architecture */ #define EM_PDSP 63 /* Sony DSP Processor */ #define EM_FX66 66 /* Siemens FX66 microcontroller */ #define EM_ST9PLUS 67 /* STMicroelectronics ST9+ 8/16 mc */ #define EM_ST7 68 /* STmicroelectronics ST7 8 bit mc */ #define EM_68HC16 69 /* Motorola MC68HC16 microcontroller */ #define EM_68HC11 70 /* Motorola MC68HC11 microcontroller */ #define EM_68HC08 71 /* Motorola MC68HC08 microcontroller */ #define EM_68HC05 72 /* Motorola MC68HC05 microcontroller */ #define EM_SVX 73 /* Silicon Graphics SVx */ #define EM_ST19 74 /* STMicroelectronics ST19 8 bit mc */ #define EM_VAX 75 /* Digital VAX */ #define EM_CRIS 76 /* Axis Communications 32-bit embedded processor */ #define EM_JAVELIN 77 /* Infineon Technologies 32-bit embedded processor */ #define EM_FIREPATH 78 /* Element 14 64-bit DSP Processor */ #define EM_ZSP 79 /* LSI Logic 16-bit DSP Processor */ #define EM_MMIX 80 /* Donald Knuth's educational 64-bit processor */ #define EM_HUANY 81 /* Harvard University machine-independent object files */ #define EM_PRISM 82 /* SiTera Prism */ #define EM_AVR 83 /* Atmel AVR 8-bit microcontroller */ #define EM_FR30 84 /* Fujitsu FR30 */ #define EM_D10V 85 /* Mitsubishi D10V */ #define EM_D30V 86 /* Mitsubishi D30V */ #define EM_V850 87 /* NEC v850 */ #define EM_M32R 88 /* Mitsubishi M32R */ #define EM_MN10300 89 /* Matsushita MN10300 */ #define EM_MN10200 90 /* Matsushita MN10200 */ #define EM_PJ 91 /* picoJava */ #define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */ #define EM_ARC_A5 93 /* ARC Cores Tangent-A5 */ #define EM_XTENSA 94 /* Tensilica Xtensa Architecture */ #define EM_NUM 95 /* If it is necessary to assign new unofficial EM_* values, please pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the chances of collision with official or non-GNU unofficial values. */ #define EM_ALPHA 0x9026 /* Legal values for e_version (version). */ #define EV_NONE 0 /* Invalid ELF version */ #define EV_CURRENT 1 /* Current version */ #define EV_NUM 2 /* Section header. */ typedef struct { Elf32_Word sh_name; /* Section name (string tbl index) */ Elf32_Word sh_type; /* Section type */ Elf32_Word sh_flags; /* Section flags */ Elf32_Addr sh_addr; /* Section virtual addr at execution */ Elf32_Off sh_offset; /* Section file offset */ Elf32_Word sh_size; /* Section size in bytes */ Elf32_Word sh_link; /* Link to another section */ Elf32_Word sh_info; /* Additional section information */ Elf32_Word sh_addralign; /* Section alignment */ Elf32_Word sh_entsize; /* Entry size if section holds table */ } Elf32_Shdr; typedef struct { Elf64_Word sh_name; /* Section name (string tbl index) */ Elf64_Word sh_type; /* Section type */ Elf64_Xword sh_flags; /* Section flags */ Elf64_Addr sh_addr; /* Section virtual addr at execution */ Elf64_Off sh_offset; /* Section file offset */ Elf64_Xword sh_size; /* Section size in bytes */ Elf64_Word sh_link; /* Link to another section */ Elf64_Word sh_info; /* Additional section information */ Elf64_Xword sh_addralign; /* Section alignment */ Elf64_Xword sh_entsize; /* Entry size if section holds table */ } Elf64_Shdr; /* Special section indices. */ #define SHN_UNDEF 0 /* Undefined section */ #define SHN_LORESERVE 0xff00 /* Start of reserved indices */ #define SHN_LOPROC 0xff00 /* Start of processor-specific */ #define SHN_BEFORE 0xff00 /* Order section before all others (Solaris). */ #define SHN_AFTER 0xff01 /* Order section after all others (Solaris). */ #define SHN_HIPROC 0xff1f /* End of processor-specific */ #define SHN_LOOS 0xff20 /* Start of OS-specific */ #define SHN_HIOS 0xff3f /* End of OS-specific */ #define SHN_ABS 0xfff1 /* Associated symbol is absolute */ #define SHN_COMMON 0xfff2 /* Associated symbol is common */ #define SHN_XINDEX 0xffff /* Index is in extra table. */ #define SHN_HIRESERVE 0xffff /* End of reserved indices */ /* Legal values for sh_type (section type). */ #define SHT_NULL 0 /* Section header table entry unused */ #define SHT_PROGBITS 1 /* Program data */ #define SHT_SYMTAB 2 /* Symbol table */ #define SHT_STRTAB 3 /* String table */ #define SHT_RELA 4 /* Relocation entries with addends */ #define SHT_HASH 5 /* Symbol hash table */ #define SHT_DYNAMIC 6 /* Dynamic linking information */ #define SHT_NOTE 7 /* Notes */ #define SHT_NOBITS 8 /* Program space with no data (bss) */ #define SHT_REL 9 /* Relocation entries, no addends */ #define SHT_SHLIB 10 /* Reserved */ #define SHT_DYNSYM 11 /* Dynamic linker symbol table */ #define SHT_INIT_ARRAY 14 /* Array of constructors */ #define SHT_FINI_ARRAY 15 /* Array of destructors */ #define SHT_PREINIT_ARRAY 16 /* Array of pre-constructors */ #define SHT_GROUP 17 /* Section group */ #define SHT_SYMTAB_SHNDX 18 /* Extended section indeces */ #define SHT_NUM 19 /* Number of defined types. */ #define SHT_LOOS 0x60000000 /* Start OS-specific. */ #define SHT_GNU_ATTRIBUTES 0x6ffffff5 /* Object attributes. */ #define SHT_GNU_HASH 0x6ffffff6 /* GNU-style hash table. */ #define SHT_GNU_LIBLIST 0x6ffffff7 /* Prelink library list */ #define SHT_CHECKSUM 0x6ffffff8 /* Checksum for DSO content. */ #define SHT_LOSUNW 0x6ffffffa /* Sun-specific low bound. */ #define SHT_SUNW_move 0x6ffffffa #define SHT_SUNW_COMDAT 0x6ffffffb #define SHT_SUNW_syminfo 0x6ffffffc #define SHT_GNU_verdef 0x6ffffffd /* Version definition section. */ #define SHT_GNU_verneed 0x6ffffffe /* Version needs section. */ #define SHT_GNU_versym 0x6fffffff /* Version symbol table. */ #define SHT_HISUNW 0x6fffffff /* Sun-specific high bound. */ #define SHT_HIOS 0x6fffffff /* End OS-specific type */ #define SHT_LOPROC 0x70000000 /* Start of processor-specific */ #define SHT_HIPROC 0x7fffffff /* End of processor-specific */ #define SHT_LOUSER 0x80000000 /* Start of application-specific */ #define SHT_HIUSER 0x8fffffff /* End of application-specific */ /* Legal values for sh_flags (section flags). */ #define SHF_WRITE (1 << 0) /* Writable */ #define SHF_ALLOC (1 << 1) /* Occupies memory during execution */ #define SHF_EXECINSTR (1 << 2) /* Executable */ #define SHF_MERGE (1 << 4) /* Might be merged */ #define SHF_STRINGS (1 << 5) /* Contains nul-terminated strings */ #define SHF_INFO_LINK (1 << 6) /* `sh_info' contains SHT index */ #define SHF_LINK_ORDER (1 << 7) /* Preserve order after combining */ #define SHF_OS_NONCONFORMING (1 << 8) /* Non-standard OS specific handling required */ #define SHF_GROUP (1 << 9) /* Section is member of a group. */ #define SHF_TLS (1 << 10) /* Section hold thread-local data. */ #define SHF_MASKOS 0x0ff00000 /* OS-specific. */ #define SHF_MASKPROC 0xf0000000 /* Processor-specific */ #define SHF_ORDERED (1 << 30) /* Special ordering requirement (Solaris). */ #define SHF_EXCLUDE (1 << 31) /* Section is excluded unless referenced or allocated (Solaris).*/ /* Section group handling. */ #define GRP_COMDAT 0x1 /* Mark group as COMDAT. */ /* Symbol table entry. */ typedef struct { Elf32_Word st_name; /* Symbol name (string tbl index) */ Elf32_Addr st_value; /* Symbol value */ Elf32_Word st_size; /* Symbol size */ unsigned char st_info; /* Symbol type and binding */ unsigned char st_other; /* Symbol visibility */ Elf32_Section st_shndx; /* Section index */ } Elf32_Sym; typedef struct { Elf64_Word st_name; /* Symbol name (string tbl index) */ unsigned char st_info; /* Symbol type and binding */ unsigned char st_other; /* Symbol visibility */ Elf64_Section st_shndx; /* Section index */ Elf64_Addr st_value; /* Symbol value */ Elf64_Xword st_size; /* Symbol size */ } Elf64_Sym; /* The syminfo section if available contains additional information about every dynamic symbol. */ typedef struct { Elf32_Half si_boundto; /* Direct bindings, symbol bound to */ Elf32_Half si_flags; /* Per symbol flags */ } Elf32_Syminfo; typedef struct { Elf64_Half si_boundto; /* Direct bindings, symbol bound to */ Elf64_Half si_flags; /* Per symbol flags */ } Elf64_Syminfo; /* Possible values for si_boundto. */ #define SYMINFO_BT_SELF 0xffff /* Symbol bound to self */ #define SYMINFO_BT_PARENT 0xfffe /* Symbol bound to parent */ #define SYMINFO_BT_LOWRESERVE 0xff00 /* Beginning of reserved entries */ /* Possible bitmasks for si_flags. */ #define SYMINFO_FLG_DIRECT 0x0001 /* Direct bound symbol */ #define SYMINFO_FLG_PASSTHRU 0x0002 /* Pass-thru symbol for translator */ #define SYMINFO_FLG_COPY 0x0004 /* Symbol is a copy-reloc */ #define SYMINFO_FLG_LAZYLOAD 0x0008 /* Symbol bound to object to be lazy loaded */ /* Syminfo version values. */ #define SYMINFO_NONE 0 #define SYMINFO_CURRENT 1 #define SYMINFO_NUM 2 /* How to extract and insert information held in the st_info field. */ #define ELF32_ST_BIND(val) (((unsigned char) (val)) >> 4) #define ELF32_ST_TYPE(val) ((val) & 0xf) #define ELF32_ST_INFO(bind, type) (((bind) << 4) + ((type) & 0xf)) /* Both Elf32_Sym and Elf64_Sym use the same one-byte st_info field. */ #define ELF64_ST_BIND(val) ELF32_ST_BIND (val) #define ELF64_ST_TYPE(val) ELF32_ST_TYPE (val) #define ELF64_ST_INFO(bind, type) ELF32_ST_INFO ((bind), (type)) /* Legal values for ST_BIND subfield of st_info (symbol binding). */ #define STB_LOCAL 0 /* Local symbol */ #define STB_GLOBAL 1 /* Global symbol */ #define STB_WEAK 2 /* Weak symbol */ #define STB_NUM 3 /* Number of defined types. */ #define STB_LOOS 10 /* Start of OS-specific */ #define STB_GNU_UNIQUE 10 /* Unique symbol. */ #define STB_HIOS 12 /* End of OS-specific */ #define STB_LOPROC 13 /* Start of processor-specific */ #define STB_HIPROC 15 /* End of processor-specific */ /* Legal values for ST_TYPE subfield of st_info (symbol type). */ #define STT_NOTYPE 0 /* Symbol type is unspecified */ #define STT_OBJECT 1 /* Symbol is a data object */ #define STT_FUNC 2 /* Symbol is a code object */ #define STT_SECTION 3 /* Symbol associated with a section */ #define STT_FILE 4 /* Symbol's name is file name */ #define STT_COMMON 5 /* Symbol is a common data object */ #define STT_TLS 6 /* Symbol is thread-local data object*/ #define STT_NUM 7 /* Number of defined types. */ #define STT_LOOS 10 /* Start of OS-specific */ #define STT_GNU_IFUNC 10 /* Symbol is indirect code object */ #define STT_HIOS 12 /* End of OS-specific */ #define STT_LOPROC 13 /* Start of processor-specific */ #define STT_HIPROC 15 /* End of processor-specific */ /* Symbol table indices are found in the hash buckets and chain table of a symbol hash table section. This special index value indicates the end of a chain, meaning no further symbols are found in that bucket. */ #define STN_UNDEF 0 /* End of a chain. */ /* How to extract and insert information held in the st_other field. */ #define ELF32_ST_VISIBILITY(o) ((o) & 0x03) /* For ELF64 the definitions are the same. */ #define ELF64_ST_VISIBILITY(o) ELF32_ST_VISIBILITY (o) /* Symbol visibility specification encoded in the st_other field. */ #define STV_DEFAULT 0 /* Default symbol visibility rules */ #define STV_INTERNAL 1 /* Processor specific hidden class */ #define STV_HIDDEN 2 /* Sym unavailable in other modules */ #define STV_PROTECTED 3 /* Not preemptible, not exported */ /* Relocation table entry without addend (in section of type SHT_REL). */ typedef struct { Elf32_Addr r_offset; /* Address */ Elf32_Word r_info; /* Relocation type and symbol index */ } Elf32_Rel; /* I have seen two different definitions of the Elf64_Rel and Elf64_Rela structures, so we'll leave them out until Novell (or whoever) gets their act together. */ /* The following, at least, is used on Sparc v9, MIPS, and Alpha. */ typedef struct { Elf64_Addr r_offset; /* Address */ Elf64_Xword r_info; /* Relocation type and symbol index */ } Elf64_Rel; /* Relocation table entry with addend (in section of type SHT_RELA). */ typedef struct { Elf32_Addr r_offset; /* Address */ Elf32_Word r_info; /* Relocation type and symbol index */ Elf32_Sword r_addend; /* Addend */ } Elf32_Rela; typedef struct { Elf64_Addr r_offset; /* Address */ Elf64_Xword r_info; /* Relocation type and symbol index */ Elf64_Sxword r_addend; /* Addend */ } Elf64_Rela; /* How to extract and insert information held in the r_info field. */ #define ELF32_R_SYM(val) ((val) >> 8) #define ELF32_R_TYPE(val) ((val) & 0xff) #define ELF32_R_INFO(sym, type) (((sym) << 8) + ((type) & 0xff)) #define ELF64_R_SYM(i) ((i) >> 32) #define ELF64_R_TYPE(i) ((i) & 0xffffffff) #define ELF64_R_INFO(sym,type) ((((Elf64_Xword) (sym)) << 32) + (type)) /* Program segment header. */ typedef struct { Elf32_Word p_type; /* Segment type */ Elf32_Off p_offset; /* Segment file offset */ Elf32_Addr p_vaddr; /* Segment virtual address */ Elf32_Addr p_paddr; /* Segment physical address */ Elf32_Word p_filesz; /* Segment size in file */ Elf32_Word p_memsz; /* Segment size in memory */ Elf32_Word p_flags; /* Segment flags */ Elf32_Word p_align; /* Segment alignment */ } Elf32_Phdr; typedef struct { Elf64_Word p_type; /* Segment type */ Elf64_Word p_flags; /* Segment flags */ Elf64_Off p_offset; /* Segment file offset */ Elf64_Addr p_vaddr; /* Segment virtual address */ Elf64_Addr p_paddr; /* Segment physical address */ Elf64_Xword p_filesz; /* Segment size in file */ Elf64_Xword p_memsz; /* Segment size in memory */ Elf64_Xword p_align; /* Segment alignment */ } Elf64_Phdr; /* Legal values for p_type (segment type). */ #define PT_NULL 0 /* Program header table entry unused */ #define PT_LOAD 1 /* Loadable program segment */ #define PT_DYNAMIC 2 /* Dynamic linking information */ #define PT_INTERP 3 /* Program interpreter */ #define PT_NOTE 4 /* Auxiliary information */ #define PT_SHLIB 5 /* Reserved */ #define PT_PHDR 6 /* Entry for header table itself */ #define PT_TLS 7 /* Thread-local storage segment */ #define PT_NUM 8 /* Number of defined types */ #define PT_LOOS 0x60000000 /* Start of OS-specific */ #define PT_GNU_EH_FRAME 0x6474e550 /* GCC .eh_frame_hdr segment */ #define PT_GNU_STACK 0x6474e551 /* Indicates stack executability */ #define PT_GNU_RELRO 0x6474e552 /* Read-only after relocation */ #define PT_LOSUNW 0x6ffffffa #define PT_SUNWBSS 0x6ffffffa /* Sun Specific segment */ #define PT_SUNWSTACK 0x6ffffffb /* Stack segment */ #define PT_HISUNW 0x6fffffff #define PT_HIOS 0x6fffffff /* End of OS-specific */ #define PT_LOPROC 0x70000000 /* Start of processor-specific */ #define PT_HIPROC 0x7fffffff /* End of processor-specific */ /* Legal values for p_flags (segment flags). */ #define PF_X (1 << 0) /* Segment is executable */ #define PF_W (1 << 1) /* Segment is writable */ #define PF_R (1 << 2) /* Segment is readable */ #define PF_MASKOS 0x0ff00000 /* OS-specific */ #define PF_MASKPROC 0xf0000000 /* Processor-specific */ /* Legal values for note segment descriptor types for core files. */ #define NT_PRSTATUS 1 /* Contains copy of prstatus struct */ #define NT_FPREGSET 2 /* Contains copy of fpregset struct */ #define NT_PRPSINFO 3 /* Contains copy of prpsinfo struct */ #define NT_PRXREG 4 /* Contains copy of prxregset struct */ #define NT_TASKSTRUCT 4 /* Contains copy of task structure */ #define NT_PLATFORM 5 /* String from sysinfo(SI_PLATFORM) */ #define NT_AUXV 6 /* Contains copy of auxv array */ #define NT_GWINDOWS 7 /* Contains copy of gwindows struct */ #define NT_ASRS 8 /* Contains copy of asrset struct */ #define NT_PSTATUS 10 /* Contains copy of pstatus struct */ #define NT_PSINFO 13 /* Contains copy of psinfo struct */ #define NT_PRCRED 14 /* Contains copy of prcred struct */ #define NT_UTSNAME 15 /* Contains copy of utsname struct */ #define NT_LWPSTATUS 16 /* Contains copy of lwpstatus struct */ #define NT_LWPSINFO 17 /* Contains copy of lwpinfo struct */ #define NT_PRFPXREG 20 /* Contains copy of fprxregset struct */ #define NT_PRXFPREG 0x46e62b7f /* Contains copy of user_fxsr_struct */ #define NT_PPC_VMX 0x100 /* PowerPC Altivec/VMX registers */ #define NT_PPC_SPE 0x101 /* PowerPC SPE/EVR registers */ #define NT_PPC_VSX 0x102 /* PowerPC VSX registers */ #define NT_386_TLS 0x200 /* i386 TLS slots (struct user_desc) */ #define NT_386_IOPERM 0x201 /* x86 io permission bitmap (1=deny) */ /* Legal values for the note segment descriptor types for object files. */ #define NT_VERSION 1 /* Contains a version string. */ /* Dynamic section entry. */ typedef struct { Elf32_Sword d_tag; /* Dynamic entry type */ union { Elf32_Word d_val; /* Integer value */ Elf32_Addr d_ptr; /* Address value */ } d_un; } Elf32_Dyn; typedef struct { Elf64_Sxword d_tag; /* Dynamic entry type */ union { Elf64_Xword d_val; /* Integer value */ Elf64_Addr d_ptr; /* Address value */ } d_un; } Elf64_Dyn; /* Legal values for d_tag (dynamic entry type). */ #define DT_NULL 0 /* Marks end of dynamic section */ #define DT_NEEDED 1 /* Name of needed library */ #define DT_PLTRELSZ 2 /* Size in bytes of PLT relocs */ #define DT_PLTGOT 3 /* Processor defined value */ #define DT_HASH 4 /* Address of symbol hash table */ #define DT_STRTAB 5 /* Address of string table */ #define DT_SYMTAB 6 /* Address of symbol table */ #define DT_RELA 7 /* Address of Rela relocs */ #define DT_RELASZ 8 /* Total size of Rela relocs */ #define DT_RELAENT 9 /* Size of one Rela reloc */ #define DT_STRSZ 10 /* Size of string table */ #define DT_SYMENT 11 /* Size of one symbol table entry */ #define DT_INIT 12 /* Address of init function */ #define DT_FINI 13 /* Address of termination function */ #define DT_SONAME 14 /* Name of shared object */ #define DT_RPATH 15 /* Library search path (deprecated) */ #define DT_SYMBOLIC 16 /* Start symbol search here */ #define DT_REL 17 /* Address of Rel relocs */ #define DT_RELSZ 18 /* Total size of Rel relocs */ #define DT_RELENT 19 /* Size of one Rel reloc */ #define DT_PLTREL 20 /* Type of reloc in PLT */ #define DT_DEBUG 21 /* For debugging; unspecified */ #define DT_TEXTREL 22 /* Reloc might modify .text */ #define DT_JMPREL 23 /* Address of PLT relocs */ #define DT_BIND_NOW 24 /* Process relocations of object */ #define DT_INIT_ARRAY 25 /* Array with addresses of init fct */ #define DT_FINI_ARRAY 26 /* Array with addresses of fini fct */ #define DT_INIT_ARRAYSZ 27 /* Size in bytes of DT_INIT_ARRAY */ #define DT_FINI_ARRAYSZ 28 /* Size in bytes of DT_FINI_ARRAY */ #define DT_RUNPATH 29 /* Library search path */ #define DT_FLAGS 30 /* Flags for the object being loaded */ #define DT_ENCODING 32 /* Start of encoded range */ #define DT_PREINIT_ARRAY 32 /* Array with addresses of preinit fct*/ #define DT_PREINIT_ARRAYSZ 33 /* size in bytes of DT_PREINIT_ARRAY */ #define DT_NUM 34 /* Number used */ #define DT_LOOS 0x6000000d /* Start of OS-specific */ #define DT_HIOS 0x6ffff000 /* End of OS-specific */ #define DT_LOPROC 0x70000000 /* Start of processor-specific */ #define DT_HIPROC 0x7fffffff /* End of processor-specific */ #define DT_PROCNUM DT_MIPS_NUM /* Most used by any processor */ /* DT_* entries which fall between DT_VALRNGHI & DT_VALRNGLO use the Dyn.d_un.d_val field of the Elf*_Dyn structure. This follows Sun's approach. */ #define DT_VALRNGLO 0x6ffffd00 #define DT_GNU_PRELINKED 0x6ffffdf5 /* Prelinking timestamp */ #define DT_GNU_CONFLICTSZ 0x6ffffdf6 /* Size of conflict section */ #define DT_GNU_LIBLISTSZ 0x6ffffdf7 /* Size of library list */ #define DT_CHECKSUM 0x6ffffdf8 #define DT_PLTPADSZ 0x6ffffdf9 #define DT_MOVEENT 0x6ffffdfa #define DT_MOVESZ 0x6ffffdfb #define DT_FEATURE_1 0x6ffffdfc /* Feature selection (DTF_*). */ #define DT_POSFLAG_1 0x6ffffdfd /* Flags for DT_* entries, effecting the following DT_* entry. */ #define DT_SYMINSZ 0x6ffffdfe /* Size of syminfo table (in bytes) */ #define DT_SYMINENT 0x6ffffdff /* Entry size of syminfo */ #define DT_VALRNGHI 0x6ffffdff #define DT_VALTAGIDX(tag) (DT_VALRNGHI - (tag)) /* Reverse order! */ #define DT_VALNUM 12 /* DT_* entries which fall between DT_ADDRRNGHI & DT_ADDRRNGLO use the Dyn.d_un.d_ptr field of the Elf*_Dyn structure. If any adjustment is made to the ELF object after it has been built these entries will need to be adjusted. */ #define DT_ADDRRNGLO 0x6ffffe00 #define DT_GNU_HASH 0x6ffffef5 /* GNU-style hash table. */ #define DT_TLSDESC_PLT 0x6ffffef6 #define DT_TLSDESC_GOT 0x6ffffef7 #define DT_GNU_CONFLICT 0x6ffffef8 /* Start of conflict section */ #define DT_GNU_LIBLIST 0x6ffffef9 /* Library list */ #define DT_CONFIG 0x6ffffefa /* Configuration information. */ #define DT_DEPAUDIT 0x6ffffefb /* Dependency auditing. */ #define DT_AUDIT 0x6ffffefc /* Object auditing. */ #define DT_PLTPAD 0x6ffffefd /* PLT padding. */ #define DT_MOVETAB 0x6ffffefe /* Move table. */ #define DT_SYMINFO 0x6ffffeff /* Syminfo table. */ #define DT_ADDRRNGHI 0x6ffffeff #define DT_ADDRTAGIDX(tag) (DT_ADDRRNGHI - (tag)) /* Reverse order! */ #define DT_ADDRNUM 11 /* The versioning entry types. The next are defined as part of the GNU extension. */ #define DT_VERSYM 0x6ffffff0 #define DT_RELACOUNT 0x6ffffff9 #define DT_RELCOUNT 0x6ffffffa /* These were chosen by Sun. */ #define DT_FLAGS_1 0x6ffffffb /* State flags, see DF_1_* below. */ #define DT_VERDEF 0x6ffffffc /* Address of version definition table */ #define DT_VERDEFNUM 0x6ffffffd /* Number of version definitions */ #define DT_VERNEED 0x6ffffffe /* Address of table with needed versions */ #define DT_VERNEEDNUM 0x6fffffff /* Number of needed versions */ #define DT_VERSIONTAGIDX(tag) (DT_VERNEEDNUM - (tag)) /* Reverse order! */ #define DT_VERSIONTAGNUM 16 /* Sun added these machine-independent extensions in the "processor-specific" range. Be compatible. */ #define DT_AUXILIARY 0x7ffffffd /* Shared object to load before self */ #define DT_FILTER 0x7fffffff /* Shared object to get values from */ #define DT_EXTRATAGIDX(tag) ((Elf32_Word)-((Elf32_Sword) (tag) <<1>>1)-1) #define DT_EXTRANUM 3 /* Values of `d_un.d_val' in the DT_FLAGS entry. */ #define DF_ORIGIN 0x00000001 /* Object may use DF_ORIGIN */ #define DF_SYMBOLIC 0x00000002 /* Symbol resolutions starts here */ #define DF_TEXTREL 0x00000004 /* Object contains text relocations */ #define DF_BIND_NOW 0x00000008 /* No lazy binding for this object */ #define DF_STATIC_TLS 0x00000010 /* Module uses the static TLS model */ /* State flags selectable in the `d_un.d_val' element of the DT_FLAGS_1 entry in the dynamic section. */ #define DF_1_NOW 0x00000001 /* Set RTLD_NOW for this object. */ #define DF_1_GLOBAL 0x00000002 /* Set RTLD_GLOBAL for this object. */ #define DF_1_GROUP 0x00000004 /* Set RTLD_GROUP for this object. */ #define DF_1_NODELETE 0x00000008 /* Set RTLD_NODELETE for this object.*/ #define DF_1_LOADFLTR 0x00000010 /* Trigger filtee loading at runtime.*/ #define DF_1_INITFIRST 0x00000020 /* Set RTLD_INITFIRST for this object*/ #define DF_1_NOOPEN 0x00000040 /* Set RTLD_NOOPEN for this object. */ #define DF_1_ORIGIN 0x00000080 /* $ORIGIN must be handled. */ #define DF_1_DIRECT 0x00000100 /* Direct binding enabled. */ #define DF_1_TRANS 0x00000200 #define DF_1_INTERPOSE 0x00000400 /* Object is used to interpose. */ #define DF_1_NODEFLIB 0x00000800 /* Ignore default lib search path. */ #define DF_1_NODUMP 0x00001000 /* Object can't be dldump'ed. */ #define DF_1_CONFALT 0x00002000 /* Configuration alternative created.*/ #define DF_1_ENDFILTEE 0x00004000 /* Filtee terminates filters search. */ #define DF_1_DISPRELDNE 0x00008000 /* Disp reloc applied at build time. */ #define DF_1_DISPRELPND 0x00010000 /* Disp reloc applied at run-time. */ /* Flags for the feature selection in DT_FEATURE_1. */ #define DTF_1_PARINIT 0x00000001 #define DTF_1_CONFEXP 0x00000002 /* Flags in the DT_POSFLAG_1 entry effecting only the next DT_* entry. */ #define DF_P1_LAZYLOAD 0x00000001 /* Lazyload following object. */ #define DF_P1_GROUPPERM 0x00000002 /* Symbols from next object are not generally available. */ /* Version definition sections. */ typedef struct { Elf32_Half vd_version; /* Version revision */ Elf32_Half vd_flags; /* Version information */ Elf32_Half vd_ndx; /* Version Index */ Elf32_Half vd_cnt; /* Number of associated aux entries */ Elf32_Word vd_hash; /* Version name hash value */ Elf32_Word vd_aux; /* Offset in bytes to verdaux array */ Elf32_Word vd_next; /* Offset in bytes to next verdef entry */ } Elf32_Verdef; typedef struct { Elf64_Half vd_version; /* Version revision */ Elf64_Half vd_flags; /* Version information */ Elf64_Half vd_ndx; /* Version Index */ Elf64_Half vd_cnt; /* Number of associated aux entries */ Elf64_Word vd_hash; /* Version name hash value */ Elf64_Word vd_aux; /* Offset in bytes to verdaux array */ Elf64_Word vd_next; /* Offset in bytes to next verdef entry */ } Elf64_Verdef; /* Legal values for vd_version (version revision). */ #define VER_DEF_NONE 0 /* No version */ #define VER_DEF_CURRENT 1 /* Current version */ #define VER_DEF_NUM 2 /* Given version number */ /* Legal values for vd_flags (version information flags). */ #define VER_FLG_BASE 0x1 /* Version definition of file itself */ #define VER_FLG_WEAK 0x2 /* Weak version identifier */ /* Versym symbol index values. */ #define VER_NDX_LOCAL 0 /* Symbol is local. */ #define VER_NDX_GLOBAL 1 /* Symbol is global. */ #define VER_NDX_LORESERVE 0xff00 /* Beginning of reserved entries. */ #define VER_NDX_ELIMINATE 0xff01 /* Symbol is to be eliminated. */ /* Auxialiary version information. */ typedef struct { Elf32_Word vda_name; /* Version or dependency names */ Elf32_Word vda_next; /* Offset in bytes to next verdaux entry */ } Elf32_Verdaux; typedef struct { Elf64_Word vda_name; /* Version or dependency names */ Elf64_Word vda_next; /* Offset in bytes to next verdaux entry */ } Elf64_Verdaux; /* Version dependency section. */ typedef struct { Elf32_Half vn_version; /* Version of structure */ Elf32_Half vn_cnt; /* Number of associated aux entries */ Elf32_Word vn_file; /* Offset of filename for this dependency */ Elf32_Word vn_aux; /* Offset in bytes to vernaux array */ Elf32_Word vn_next; /* Offset in bytes to next verneed entry */ } Elf32_Verneed; typedef struct { Elf64_Half vn_version; /* Version of structure */ Elf64_Half vn_cnt; /* Number of associated aux entries */ Elf64_Word vn_file; /* Offset of filename for this dependency */ Elf64_Word vn_aux; /* Offset in bytes to vernaux array */ Elf64_Word vn_next; /* Offset in bytes to next verneed entry */ } Elf64_Verneed; /* Legal values for vn_version (version revision). */ #define VER_NEED_NONE 0 /* No version */ #define VER_NEED_CURRENT 1 /* Current version */ #define VER_NEED_NUM 2 /* Given version number */ /* Auxiliary needed version information. */ typedef struct { Elf32_Word vna_hash; /* Hash value of dependency name */ Elf32_Half vna_flags; /* Dependency specific information */ Elf32_Half vna_other; /* Unused */ Elf32_Word vna_name; /* Dependency name string offset */ Elf32_Word vna_next; /* Offset in bytes to next vernaux entry */ } Elf32_Vernaux; typedef struct { Elf64_Word vna_hash; /* Hash value of dependency name */ Elf64_Half vna_flags; /* Dependency specific information */ Elf64_Half vna_other; /* Unused */ Elf64_Word vna_name; /* Dependency name string offset */ Elf64_Word vna_next; /* Offset in bytes to next vernaux entry */ } Elf64_Vernaux; /* Legal values for vna_flags. */ #define VER_FLG_WEAK 0x2 /* Weak version identifier */ /* Auxiliary vector. */ /* This vector is normally only used by the program interpreter. The usual definition in an ABI supplement uses the name auxv_t. The vector is not usually defined in a standard file, but it can't hurt. We rename it to avoid conflicts. The sizes of these types are an arrangement between the exec server and the program interpreter, so we don't fully specify them here. */ typedef struct { uint32_t a_type; /* Entry type */ union { uint32_t a_val; /* Integer value */ /* We use to have pointer elements added here. We cannot do that, though, since it does not work when using 32-bit definitions on 64-bit platforms and vice versa. */ } a_un; } Elf32_auxv_t; typedef struct { uint64_t a_type; /* Entry type */ union { uint64_t a_val; /* Integer value */ /* We use to have pointer elements added here. We cannot do that, though, since it does not work when using 32-bit definitions on 64-bit platforms and vice versa. */ } a_un; } Elf64_auxv_t; /* Legal values for a_type (entry type). */ #define AT_NULL 0 /* End of vector */ #define AT_IGNORE 1 /* Entry should be ignored */ #define AT_EXECFD 2 /* File descriptor of program */ #define AT_PHDR 3 /* Program headers for program */ #define AT_PHENT 4 /* Size of program header entry */ #define AT_PHNUM 5 /* Number of program headers */ #define AT_PAGESZ 6 /* System page size */ #define AT_BASE 7 /* Base address of interpreter */ #define AT_FLAGS 8 /* Flags */ #define AT_ENTRY 9 /* Entry point of program */ #define AT_NOTELF 10 /* Program is not ELF */ #define AT_UID 11 /* Real uid */ #define AT_EUID 12 /* Effective uid */ #define AT_GID 13 /* Real gid */ #define AT_EGID 14 /* Effective gid */ #define AT_CLKTCK 17 /* Frequency of times() */ /* Some more special a_type values describing the hardware. */ #define AT_PLATFORM 15 /* String identifying platform. */ #define AT_HWCAP 16 /* Machine dependent hints about processor capabilities. */ /* This entry gives some information about the FPU initialization performed by the kernel. */ #define AT_FPUCW 18 /* Used FPU control word. */ /* Cache block sizes. */ #define AT_DCACHEBSIZE 19 /* Data cache block size. */ #define AT_ICACHEBSIZE 20 /* Instruction cache block size. */ #define AT_UCACHEBSIZE 21 /* Unified cache block size. */ /* A special ignored value for PPC, used by the kernel to control the interpretation of the AUXV. Must be > 16. */ #define AT_IGNOREPPC 22 /* Entry should be ignored. */ #define AT_SECURE 23 /* Boolean, was exec setuid-like? */ #define AT_BASE_PLATFORM 24 /* String identifying real platforms.*/ #define AT_RANDOM 25 /* Address of 16 random bytes. */ #define AT_EXECFN 31 /* Filename of executable. */ /* Pointer to the global system page used for system calls and other nice things. */ #define AT_SYSINFO 32 #define AT_SYSINFO_EHDR 33 /* Shapes of the caches. Bits 0-3 contains associativity; bits 4-7 contains log2 of line size; mask those to get cache size. */ #define AT_L1I_CACHESHAPE 34 #define AT_L1D_CACHESHAPE 35 #define AT_L2_CACHESHAPE 36 #define AT_L3_CACHESHAPE 37 /* Note section contents. Each entry in the note section begins with a header of a fixed form. */ typedef struct { Elf32_Word n_namesz; /* Length of the note's name. */ Elf32_Word n_descsz; /* Length of the note's descriptor. */ Elf32_Word n_type; /* Type of the note. */ } Elf32_Nhdr; typedef struct { Elf64_Word n_namesz; /* Length of the note's name. */ Elf64_Word n_descsz; /* Length of the note's descriptor. */ Elf64_Word n_type; /* Type of the note. */ } Elf64_Nhdr; /* Known names of notes. */ /* Solaris entries in the note section have this name. */ #define ELF_NOTE_SOLARIS "SUNW Solaris" /* Note entries for GNU systems have this name. */ #define ELF_NOTE_GNU "GNU" /* Defined types of notes for Solaris. */ /* Value of descriptor (one word) is desired pagesize for the binary. */ #define ELF_NOTE_PAGESIZE_HINT 1 /* Defined note types for GNU systems. */ /* ABI information. The descriptor consists of words: word 0: OS descriptor word 1: major version of the ABI word 2: minor version of the ABI word 3: subminor version of the ABI */ #define NT_GNU_ABI_TAG 1 #define ELF_NOTE_ABI NT_GNU_ABI_TAG /* Old name. */ /* Known OSes. These values can appear in word 0 of an NT_GNU_ABI_TAG note section entry. */ #define ELF_NOTE_OS_LINUX 0 #define ELF_NOTE_OS_GNU 1 #define ELF_NOTE_OS_SOLARIS2 2 #define ELF_NOTE_OS_FREEBSD 3 /* Synthetic hwcap information. The descriptor begins with two words: word 0: number of entries word 1: bitmask of enabled entries Then follow variable-length entries, one byte followed by a '\0'-terminated hwcap name string. The byte gives the bit number to test if enabled, (1U << bit) & bitmask. */ #define NT_GNU_HWCAP 2 /* Build ID bits as generated by ld --build-id. The descriptor consists of any nonzero number of bytes. */ #define NT_GNU_BUILD_ID 3 /* Version note generated by GNU gold containing a version string. */ #define NT_GNU_GOLD_VERSION 4 /* Move records. */ typedef struct { Elf32_Xword m_value; /* Symbol value. */ Elf32_Word m_info; /* Size and index. */ Elf32_Word m_poffset; /* Symbol offset. */ Elf32_Half m_repeat; /* Repeat count. */ Elf32_Half m_stride; /* Stride info. */ } Elf32_Move; typedef struct { Elf64_Xword m_value; /* Symbol value. */ Elf64_Xword m_info; /* Size and index. */ Elf64_Xword m_poffset; /* Symbol offset. */ Elf64_Half m_repeat; /* Repeat count. */ Elf64_Half m_stride; /* Stride info. */ } Elf64_Move; /* Macro to construct move records. */ #define ELF32_M_SYM(info) ((info) >> 8) #define ELF32_M_SIZE(info) ((unsigned char) (info)) #define ELF32_M_INFO(sym, size) (((sym) << 8) + (unsigned char) (size)) #define ELF64_M_SYM(info) ELF32_M_SYM (info) #define ELF64_M_SIZE(info) ELF32_M_SIZE (info) #define ELF64_M_INFO(sym, size) ELF32_M_INFO (sym, size) /* Motorola 68k specific definitions. */ /* Values for Elf32_Ehdr.e_flags. */ #define EF_CPU32 0x00810000 /* m68k relocs. */ #define R_68K_NONE 0 /* No reloc */ #define R_68K_32 1 /* Direct 32 bit */ #define R_68K_16 2 /* Direct 16 bit */ #define R_68K_8 3 /* Direct 8 bit */ #define R_68K_PC32 4 /* PC relative 32 bit */ #define R_68K_PC16 5 /* PC relative 16 bit */ #define R_68K_PC8 6 /* PC relative 8 bit */ #define R_68K_GOT32 7 /* 32 bit PC relative GOT entry */ #define R_68K_GOT16 8 /* 16 bit PC relative GOT entry */ #define R_68K_GOT8 9 /* 8 bit PC relative GOT entry */ #define R_68K_GOT32O 10 /* 32 bit GOT offset */ #define R_68K_GOT16O 11 /* 16 bit GOT offset */ #define R_68K_GOT8O 12 /* 8 bit GOT offset */ #define R_68K_PLT32 13 /* 32 bit PC relative PLT address */ #define R_68K_PLT16 14 /* 16 bit PC relative PLT address */ #define R_68K_PLT8 15 /* 8 bit PC relative PLT address */ #define R_68K_PLT32O 16 /* 32 bit PLT offset */ #define R_68K_PLT16O 17 /* 16 bit PLT offset */ #define R_68K_PLT8O 18 /* 8 bit PLT offset */ #define R_68K_COPY 19 /* Copy symbol at runtime */ #define R_68K_GLOB_DAT 20 /* Create GOT entry */ #define R_68K_JMP_SLOT 21 /* Create PLT entry */ #define R_68K_RELATIVE 22 /* Adjust by program base */ #define R_68K_TLS_GD32 25 /* 32 bit GOT offset for GD */ #define R_68K_TLS_GD16 26 /* 16 bit GOT offset for GD */ #define R_68K_TLS_GD8 27 /* 8 bit GOT offset for GD */ #define R_68K_TLS_LDM32 28 /* 32 bit GOT offset for LDM */ #define R_68K_TLS_LDM16 29 /* 16 bit GOT offset for LDM */ #define R_68K_TLS_LDM8 30 /* 8 bit GOT offset for LDM */ #define R_68K_TLS_LDO32 31 /* 32 bit module-relative offset */ #define R_68K_TLS_LDO16 32 /* 16 bit module-relative offset */ #define R_68K_TLS_LDO8 33 /* 8 bit module-relative offset */ #define R_68K_TLS_IE32 34 /* 32 bit GOT offset for IE */ #define R_68K_TLS_IE16 35 /* 16 bit GOT offset for IE */ #define R_68K_TLS_IE8 36 /* 8 bit GOT offset for IE */ #define R_68K_TLS_LE32 37 /* 32 bit offset relative to static TLS block */ #define R_68K_TLS_LE16 38 /* 16 bit offset relative to static TLS block */ #define R_68K_TLS_LE8 39 /* 8 bit offset relative to static TLS block */ #define R_68K_TLS_DTPMOD32 40 /* 32 bit module number */ #define R_68K_TLS_DTPREL32 41 /* 32 bit module-relative offset */ #define R_68K_TLS_TPREL32 42 /* 32 bit TP-relative offset */ /* Keep this the last entry. */ #define R_68K_NUM 43 /* Intel 80386 specific definitions. */ /* i386 relocs. */ #define R_386_NONE 0 /* No reloc */ #define R_386_32 1 /* Direct 32 bit */ #define R_386_PC32 2 /* PC relative 32 bit */ #define R_386_GOT32 3 /* 32 bit GOT entry */ #define R_386_PLT32 4 /* 32 bit PLT address */ #define R_386_COPY 5 /* Copy symbol at runtime */ #define R_386_GLOB_DAT 6 /* Create GOT entry */ #define R_386_JMP_SLOT 7 /* Create PLT entry */ #define R_386_RELATIVE 8 /* Adjust by program base */ #define R_386_GOTOFF 9 /* 32 bit offset to GOT */ #define R_386_GOTPC 10 /* 32 bit PC relative offset to GOT */ #define R_386_32PLT 11 #define R_386_TLS_TPOFF 14 /* Offset in static TLS block */ #define R_386_TLS_IE 15 /* Address of GOT entry for static TLS block offset */ #define R_386_TLS_GOTIE 16 /* GOT entry for static TLS block offset */ #define R_386_TLS_LE 17 /* Offset relative to static TLS block */ #define R_386_TLS_GD 18 /* Direct 32 bit for GNU version of general dynamic thread local data */ #define R_386_TLS_LDM 19 /* Direct 32 bit for GNU version of local dynamic thread local data in LE code */ #define R_386_16 20 #define R_386_PC16 21 #define R_386_8 22 #define R_386_PC8 23 #define R_386_TLS_GD_32 24 /* Direct 32 bit for general dynamic thread local data */ #define R_386_TLS_GD_PUSH 25 /* Tag for pushl in GD TLS code */ #define R_386_TLS_GD_CALL 26 /* Relocation for call to __tls_get_addr() */ #define R_386_TLS_GD_POP 27 /* Tag for popl in GD TLS code */ #define R_386_TLS_LDM_32 28 /* Direct 32 bit for local dynamic thread local data in LE code */ #define R_386_TLS_LDM_PUSH 29 /* Tag for pushl in LDM TLS code */ #define R_386_TLS_LDM_CALL 30 /* Relocation for call to __tls_get_addr() in LDM code */ #define R_386_TLS_LDM_POP 31 /* Tag for popl in LDM TLS code */ #define R_386_TLS_LDO_32 32 /* Offset relative to TLS block */ #define R_386_TLS_IE_32 33 /* GOT entry for negated static TLS block offset */ #define R_386_TLS_LE_32 34 /* Negated offset relative to static TLS block */ #define R_386_TLS_DTPMOD32 35 /* ID of module containing symbol */ #define R_386_TLS_DTPOFF32 36 /* Offset in TLS block */ #define R_386_TLS_TPOFF32 37 /* Negated offset in static TLS block */ /* 38? */ #define R_386_TLS_GOTDESC 39 /* GOT offset for TLS descriptor. */ #define R_386_TLS_DESC_CALL 40 /* Marker of call through TLS descriptor for relaxation. */ #define R_386_TLS_DESC 41 /* TLS descriptor containing pointer to code and to argument, returning the TLS offset for the symbol. */ #define R_386_IRELATIVE 42 /* Adjust indirectly by program base */ /* Keep this the last entry. */ #define R_386_NUM 43 /* SUN SPARC specific definitions. */ /* Legal values for ST_TYPE subfield of st_info (symbol type). */ #define STT_SPARC_REGISTER 13 /* Global register reserved to app. */ /* Values for Elf64_Ehdr.e_flags. */ #define EF_SPARCV9_MM 3 #define EF_SPARCV9_TSO 0 #define EF_SPARCV9_PSO 1 #define EF_SPARCV9_RMO 2 #define EF_SPARC_LEDATA 0x800000 /* little endian data */ #define EF_SPARC_EXT_MASK 0xFFFF00 #define EF_SPARC_32PLUS 0x000100 /* generic V8+ features */ #define EF_SPARC_SUN_US1 0x000200 /* Sun UltraSPARC1 extensions */ #define EF_SPARC_HAL_R1 0x000400 /* HAL R1 extensions */ #define EF_SPARC_SUN_US3 0x000800 /* Sun UltraSPARCIII extensions */ /* SPARC relocs. */ #define R_SPARC_NONE 0 /* No reloc */ #define R_SPARC_8 1 /* Direct 8 bit */ #define R_SPARC_16 2 /* Direct 16 bit */ #define R_SPARC_32 3 /* Direct 32 bit */ #define R_SPARC_DISP8 4 /* PC relative 8 bit */ #define R_SPARC_DISP16 5 /* PC relative 16 bit */ #define R_SPARC_DISP32 6 /* PC relative 32 bit */ #define R_SPARC_WDISP30 7 /* PC relative 30 bit shifted */ #define R_SPARC_WDISP22 8 /* PC relative 22 bit shifted */ #define R_SPARC_HI22 9 /* High 22 bit */ #define R_SPARC_22 10 /* Direct 22 bit */ #define R_SPARC_13 11 /* Direct 13 bit */ #define R_SPARC_LO10 12 /* Truncated 10 bit */ #define R_SPARC_GOT10 13 /* Truncated 10 bit GOT entry */ #define R_SPARC_GOT13 14 /* 13 bit GOT entry */ #define R_SPARC_GOT22 15 /* 22 bit GOT entry shifted */ #define R_SPARC_PC10 16 /* PC relative 10 bit truncated */ #define R_SPARC_PC22 17 /* PC relative 22 bit shifted */ #define R_SPARC_WPLT30 18 /* 30 bit PC relative PLT address */ #define R_SPARC_COPY 19 /* Copy symbol at runtime */ #define R_SPARC_GLOB_DAT 20 /* Create GOT entry */ #define R_SPARC_JMP_SLOT 21 /* Create PLT entry */ #define R_SPARC_RELATIVE 22 /* Adjust by program base */ #define R_SPARC_UA32 23 /* Direct 32 bit unaligned */ /* Additional Sparc64 relocs. */ #define R_SPARC_PLT32 24 /* Direct 32 bit ref to PLT entry */ #define R_SPARC_HIPLT22 25 /* High 22 bit PLT entry */ #define R_SPARC_LOPLT10 26 /* Truncated 10 bit PLT entry */ #define R_SPARC_PCPLT32 27 /* PC rel 32 bit ref to PLT entry */ #define R_SPARC_PCPLT22 28 /* PC rel high 22 bit PLT entry */ #define R_SPARC_PCPLT10 29 /* PC rel trunc 10 bit PLT entry */ #define R_SPARC_10 30 /* Direct 10 bit */ #define R_SPARC_11 31 /* Direct 11 bit */ #define R_SPARC_64 32 /* Direct 64 bit */ #define R_SPARC_OLO10 33 /* 10bit with secondary 13bit addend */ #define R_SPARC_HH22 34 /* Top 22 bits of direct 64 bit */ #define R_SPARC_HM10 35 /* High middle 10 bits of ... */ #define R_SPARC_LM22 36 /* Low middle 22 bits of ... */ #define R_SPARC_PC_HH22 37 /* Top 22 bits of pc rel 64 bit */ #define R_SPARC_PC_HM10 38 /* High middle 10 bit of ... */ #define R_SPARC_PC_LM22 39 /* Low miggle 22 bits of ... */ #define R_SPARC_WDISP16 40 /* PC relative 16 bit shifted */ #define R_SPARC_WDISP19 41 /* PC relative 19 bit shifted */ #define R_SPARC_GLOB_JMP 42 /* was part of v9 ABI but was removed */ #define R_SPARC_7 43 /* Direct 7 bit */ #define R_SPARC_5 44 /* Direct 5 bit */ #define R_SPARC_6 45 /* Direct 6 bit */ #define R_SPARC_DISP64 46 /* PC relative 64 bit */ #define R_SPARC_PLT64 47 /* Direct 64 bit ref to PLT entry */ #define R_SPARC_HIX22 48 /* High 22 bit complemented */ #define R_SPARC_LOX10 49 /* Truncated 11 bit complemented */ #define R_SPARC_H44 50 /* Direct high 12 of 44 bit */ #define R_SPARC_M44 51 /* Direct mid 22 of 44 bit */ #define R_SPARC_L44 52 /* Direct low 10 of 44 bit */ #define R_SPARC_REGISTER 53 /* Global register usage */ #define R_SPARC_UA64 54 /* Direct 64 bit unaligned */ #define R_SPARC_UA16 55 /* Direct 16 bit unaligned */ #define R_SPARC_TLS_GD_HI22 56 #define R_SPARC_TLS_GD_LO10 57 #define R_SPARC_TLS_GD_ADD 58 #define R_SPARC_TLS_GD_CALL 59 #define R_SPARC_TLS_LDM_HI22 60 #define R_SPARC_TLS_LDM_LO10 61 #define R_SPARC_TLS_LDM_ADD 62 #define R_SPARC_TLS_LDM_CALL 63 #define R_SPARC_TLS_LDO_HIX22 64 #define R_SPARC_TLS_LDO_LOX10 65 #define R_SPARC_TLS_LDO_ADD 66 #define R_SPARC_TLS_IE_HI22 67 #define R_SPARC_TLS_IE_LO10 68 #define R_SPARC_TLS_IE_LD 69 #define R_SPARC_TLS_IE_LDX 70 #define R_SPARC_TLS_IE_ADD 71 #define R_SPARC_TLS_LE_HIX22 72 #define R_SPARC_TLS_LE_LOX10 73 #define R_SPARC_TLS_DTPMOD32 74 #define R_SPARC_TLS_DTPMOD64 75 #define R_SPARC_TLS_DTPOFF32 76 #define R_SPARC_TLS_DTPOFF64 77 #define R_SPARC_TLS_TPOFF32 78 #define R_SPARC_TLS_TPOFF64 79 #define R_SPARC_GOTDATA_HIX22 80 #define R_SPARC_GOTDATA_LOX10 81 #define R_SPARC_GOTDATA_OP_HIX22 82 #define R_SPARC_GOTDATA_OP_LOX10 83 #define R_SPARC_GOTDATA_OP 84 #define R_SPARC_H34 85 #define R_SPARC_SIZE32 86 #define R_SPARC_SIZE64 87 #define R_SPARC_GNU_VTINHERIT 250 #define R_SPARC_GNU_VTENTRY 251 #define R_SPARC_REV32 252 /* Keep this the last entry. */ #define R_SPARC_NUM 253 /* For Sparc64, legal values for d_tag of Elf64_Dyn. */ #define DT_SPARC_REGISTER 0x70000001 #define DT_SPARC_NUM 2 /* Bits present in AT_HWCAP on SPARC. */ #define HWCAP_SPARC_FLUSH 1 /* The CPU supports flush insn. */ #define HWCAP_SPARC_STBAR 2 #define HWCAP_SPARC_SWAP 4 #define HWCAP_SPARC_MULDIV 8 #define HWCAP_SPARC_V9 16 /* The CPU is v9, so v8plus is ok. */ #define HWCAP_SPARC_ULTRA3 32 #define HWCAP_SPARC_BLKINIT 64 /* Sun4v with block-init/load-twin. */ #define HWCAP_SPARC_N2 128 /* MIPS R3000 specific definitions. */ /* Legal values for e_flags field of Elf32_Ehdr. */ #define EF_MIPS_NOREORDER 1 /* A .noreorder directive was used */ #define EF_MIPS_PIC 2 /* Contains PIC code */ #define EF_MIPS_CPIC 4 /* Uses PIC calling sequence */ #define EF_MIPS_XGOT 8 #define EF_MIPS_64BIT_WHIRL 16 #define EF_MIPS_ABI2 32 #define EF_MIPS_ABI_ON32 64 #define EF_MIPS_ARCH 0xf0000000 /* MIPS architecture level */ /* Legal values for MIPS architecture level. */ #define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ #define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ #define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ #define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ #define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ #define EF_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ #define EF_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ /* The following are non-official names and should not be used. */ #define E_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ #define E_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ #define E_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ #define E_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ #define E_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ #define E_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ #define E_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ /* Special section indices. */ #define SHN_MIPS_ACOMMON 0xff00 /* Allocated common symbols */ #define SHN_MIPS_TEXT 0xff01 /* Allocated test symbols. */ #define SHN_MIPS_DATA 0xff02 /* Allocated data symbols. */ #define SHN_MIPS_SCOMMON 0xff03 /* Small common symbols */ #define SHN_MIPS_SUNDEFINED 0xff04 /* Small undefined symbols */ /* Legal values for sh_type field of Elf32_Shdr. */ #define SHT_MIPS_LIBLIST 0x70000000 /* Shared objects used in link */ #define SHT_MIPS_MSYM 0x70000001 #define SHT_MIPS_CONFLICT 0x70000002 /* Conflicting symbols */ #define SHT_MIPS_GPTAB 0x70000003 /* Global data area sizes */ #define SHT_MIPS_UCODE 0x70000004 /* Reserved for SGI/MIPS compilers */ #define SHT_MIPS_DEBUG 0x70000005 /* MIPS ECOFF debugging information*/ #define SHT_MIPS_REGINFO 0x70000006 /* Register usage information */ #define SHT_MIPS_PACKAGE 0x70000007 #define SHT_MIPS_PACKSYM 0x70000008 #define SHT_MIPS_RELD 0x70000009 #define SHT_MIPS_IFACE 0x7000000b #define SHT_MIPS_CONTENT 0x7000000c #define SHT_MIPS_OPTIONS 0x7000000d /* Miscellaneous options. */ #define SHT_MIPS_SHDR 0x70000010 #define SHT_MIPS_FDESC 0x70000011 #define SHT_MIPS_EXTSYM 0x70000012 #define SHT_MIPS_DENSE 0x70000013 #define SHT_MIPS_PDESC 0x70000014 #define SHT_MIPS_LOCSYM 0x70000015 #define SHT_MIPS_AUXSYM 0x70000016 #define SHT_MIPS_OPTSYM 0x70000017 #define SHT_MIPS_LOCSTR 0x70000018 #define SHT_MIPS_LINE 0x70000019 #define SHT_MIPS_RFDESC 0x7000001a #define SHT_MIPS_DELTASYM 0x7000001b #define SHT_MIPS_DELTAINST 0x7000001c #define SHT_MIPS_DELTACLASS 0x7000001d #define SHT_MIPS_DWARF 0x7000001e /* DWARF debugging information. */ #define SHT_MIPS_DELTADECL 0x7000001f #define SHT_MIPS_SYMBOL_LIB 0x70000020 #define SHT_MIPS_EVENTS 0x70000021 /* Event section. */ #define SHT_MIPS_TRANSLATE 0x70000022 #define SHT_MIPS_PIXIE 0x70000023 #define SHT_MIPS_XLATE 0x70000024 #define SHT_MIPS_XLATE_DEBUG 0x70000025 #define SHT_MIPS_WHIRL 0x70000026 #define SHT_MIPS_EH_REGION 0x70000027 #define SHT_MIPS_XLATE_OLD 0x70000028 #define SHT_MIPS_PDR_EXCEPTION 0x70000029 /* Legal values for sh_flags field of Elf32_Shdr. */ #define SHF_MIPS_GPREL 0x10000000 /* Must be part of global data area */ #define SHF_MIPS_MERGE 0x20000000 #define SHF_MIPS_ADDR 0x40000000 #define SHF_MIPS_STRINGS 0x80000000 #define SHF_MIPS_NOSTRIP 0x08000000 #define SHF_MIPS_LOCAL 0x04000000 #define SHF_MIPS_NAMES 0x02000000 #define SHF_MIPS_NODUPE 0x01000000 /* Symbol tables. */ /* MIPS specific values for `st_other'. */ #define STO_MIPS_DEFAULT 0x0 #define STO_MIPS_INTERNAL 0x1 #define STO_MIPS_HIDDEN 0x2 #define STO_MIPS_PROTECTED 0x3 #define STO_MIPS_PLT 0x8 #define STO_MIPS_SC_ALIGN_UNUSED 0xff /* MIPS specific values for `st_info'. */ #define STB_MIPS_SPLIT_COMMON 13 /* Entries found in sections of type SHT_MIPS_GPTAB. */ typedef union { struct { Elf32_Word gt_current_g_value; /* -G value used for compilation */ Elf32_Word gt_unused; /* Not used */ } gt_header; /* First entry in section */ struct { Elf32_Word gt_g_value; /* If this value were used for -G */ Elf32_Word gt_bytes; /* This many bytes would be used */ } gt_entry; /* Subsequent entries in section */ } Elf32_gptab; /* Entry found in sections of type SHT_MIPS_REGINFO. */ typedef struct { Elf32_Word ri_gprmask; /* General registers used */ Elf32_Word ri_cprmask[4]; /* Coprocessor registers used */ Elf32_Sword ri_gp_value; /* $gp register value */ } Elf32_RegInfo; /* Entries found in sections of type SHT_MIPS_OPTIONS. */ typedef struct { unsigned char kind; /* Determines interpretation of the variable part of descriptor. */ unsigned char size; /* Size of descriptor, including header. */ Elf32_Section section; /* Section header index of section affected, 0 for global options. */ Elf32_Word info; /* Kind-specific information. */ } Elf_Options; /* Values for `kind' field in Elf_Options. */ #define ODK_NULL 0 /* Undefined. */ #define ODK_REGINFO 1 /* Register usage information. */ #define ODK_EXCEPTIONS 2 /* Exception processing options. */ #define ODK_PAD 3 /* Section padding options. */ #define ODK_HWPATCH 4 /* Hardware workarounds performed */ #define ODK_FILL 5 /* record the fill value used by the linker. */ #define ODK_TAGS 6 /* reserve space for desktop tools to write. */ #define ODK_HWAND 7 /* HW workarounds. 'AND' bits when merging. */ #define ODK_HWOR 8 /* HW workarounds. 'OR' bits when merging. */ /* Values for `info' in Elf_Options for ODK_EXCEPTIONS entries. */ #define OEX_FPU_MIN 0x1f /* FPE's which MUST be enabled. */ #define OEX_FPU_MAX 0x1f00 /* FPE's which MAY be enabled. */ #define OEX_PAGE0 0x10000 /* page zero must be mapped. */ #define OEX_SMM 0x20000 /* Force sequential memory mode? */ #define OEX_FPDBUG 0x40000 /* Force floating point debug mode? */ #define OEX_PRECISEFP OEX_FPDBUG #define OEX_DISMISS 0x80000 /* Dismiss invalid address faults? */ #define OEX_FPU_INVAL 0x10 #define OEX_FPU_DIV0 0x08 #define OEX_FPU_OFLO 0x04 #define OEX_FPU_UFLO 0x02 #define OEX_FPU_INEX 0x01 /* Masks for `info' in Elf_Options for an ODK_HWPATCH entry. */ #define OHW_R4KEOP 0x1 /* R4000 end-of-page patch. */ #define OHW_R8KPFETCH 0x2 /* may need R8000 prefetch patch. */ #define OHW_R5KEOP 0x4 /* R5000 end-of-page patch. */ #define OHW_R5KCVTL 0x8 /* R5000 cvt.[ds].l bug. clean=1. */ #define OPAD_PREFIX 0x1 #define OPAD_POSTFIX 0x2 #define OPAD_SYMBOL 0x4 /* Entry found in `.options' section. */ typedef struct { Elf32_Word hwp_flags1; /* Extra flags. */ Elf32_Word hwp_flags2; /* Extra flags. */ } Elf_Options_Hw; /* Masks for `info' in ElfOptions for ODK_HWAND and ODK_HWOR entries. */ #define OHWA0_R4KEOP_CHECKED 0x00000001 #define OHWA1_R4KEOP_CLEAN 0x00000002 /* MIPS relocs. */ #define R_MIPS_NONE 0 /* No reloc */ #define R_MIPS_16 1 /* Direct 16 bit */ #define R_MIPS_32 2 /* Direct 32 bit */ #define R_MIPS_REL32 3 /* PC relative 32 bit */ #define R_MIPS_26 4 /* Direct 26 bit shifted */ #define R_MIPS_HI16 5 /* High 16 bit */ #define R_MIPS_LO16 6 /* Low 16 bit */ #define R_MIPS_GPREL16 7 /* GP relative 16 bit */ #define R_MIPS_LITERAL 8 /* 16 bit literal entry */ #define R_MIPS_GOT16 9 /* 16 bit GOT entry */ #define R_MIPS_PC16 10 /* PC relative 16 bit */ #define R_MIPS_CALL16 11 /* 16 bit GOT entry for function */ #define R_MIPS_GPREL32 12 /* GP relative 32 bit */ #define R_MIPS_SHIFT5 16 #define R_MIPS_SHIFT6 17 #define R_MIPS_64 18 #define R_MIPS_GOT_DISP 19 #define R_MIPS_GOT_PAGE 20 #define R_MIPS_GOT_OFST 21 #define R_MIPS_GOT_HI16 22 #define R_MIPS_GOT_LO16 23 #define R_MIPS_SUB 24 #define R_MIPS_INSERT_A 25 #define R_MIPS_INSERT_B 26 #define R_MIPS_DELETE 27 #define R_MIPS_HIGHER 28 #define R_MIPS_HIGHEST 29 #define R_MIPS_CALL_HI16 30 #define R_MIPS_CALL_LO16 31 #define R_MIPS_SCN_DISP 32 #define R_MIPS_REL16 33 #define R_MIPS_ADD_IMMEDIATE 34 #define R_MIPS_PJUMP 35 #define R_MIPS_RELGOT 36 #define R_MIPS_JALR 37 #define R_MIPS_TLS_DTPMOD32 38 /* Module number 32 bit */ #define R_MIPS_TLS_DTPREL32 39 /* Module-relative offset 32 bit */ #define R_MIPS_TLS_DTPMOD64 40 /* Module number 64 bit */ #define R_MIPS_TLS_DTPREL64 41 /* Module-relative offset 64 bit */ #define R_MIPS_TLS_GD 42 /* 16 bit GOT offset for GD */ #define R_MIPS_TLS_LDM 43 /* 16 bit GOT offset for LDM */ #define R_MIPS_TLS_DTPREL_HI16 44 /* Module-relative offset, high 16 bits */ #define R_MIPS_TLS_DTPREL_LO16 45 /* Module-relative offset, low 16 bits */ #define R_MIPS_TLS_GOTTPREL 46 /* 16 bit GOT offset for IE */ #define R_MIPS_TLS_TPREL32 47 /* TP-relative offset, 32 bit */ #define R_MIPS_TLS_TPREL64 48 /* TP-relative offset, 64 bit */ #define R_MIPS_TLS_TPREL_HI16 49 /* TP-relative offset, high 16 bits */ #define R_MIPS_TLS_TPREL_LO16 50 /* TP-relative offset, low 16 bits */ #define R_MIPS_GLOB_DAT 51 #define R_MIPS_COPY 126 #define R_MIPS_JUMP_SLOT 127 /* Keep this the last entry. */ #define R_MIPS_NUM 128 /* Legal values for p_type field of Elf32_Phdr. */ #define PT_MIPS_REGINFO 0x70000000 /* Register usage information */ #define PT_MIPS_RTPROC 0x70000001 /* Runtime procedure table. */ #define PT_MIPS_OPTIONS 0x70000002 /* Special program header types. */ #define PF_MIPS_LOCAL 0x10000000 /* Legal values for d_tag field of Elf32_Dyn. */ #define DT_MIPS_RLD_VERSION 0x70000001 /* Runtime linker interface version */ #define DT_MIPS_TIME_STAMP 0x70000002 /* Timestamp */ #define DT_MIPS_ICHECKSUM 0x70000003 /* Checksum */ #define DT_MIPS_IVERSION 0x70000004 /* Version string (string tbl index) */ #define DT_MIPS_FLAGS 0x70000005 /* Flags */ #define DT_MIPS_BASE_ADDRESS 0x70000006 /* Base address */ #define DT_MIPS_MSYM 0x70000007 #define DT_MIPS_CONFLICT 0x70000008 /* Address of CONFLICT section */ #define DT_MIPS_LIBLIST 0x70000009 /* Address of LIBLIST section */ #define DT_MIPS_LOCAL_GOTNO 0x7000000a /* Number of local GOT entries */ #define DT_MIPS_CONFLICTNO 0x7000000b /* Number of CONFLICT entries */ #define DT_MIPS_LIBLISTNO 0x70000010 /* Number of LIBLIST entries */ #define DT_MIPS_SYMTABNO 0x70000011 /* Number of DYNSYM entries */ #define DT_MIPS_UNREFEXTNO 0x70000012 /* First external DYNSYM */ #define DT_MIPS_GOTSYM 0x70000013 /* First GOT entry in DYNSYM */ #define DT_MIPS_HIPAGENO 0x70000014 /* Number of GOT page table entries */ #define DT_MIPS_RLD_MAP 0x70000016 /* Address of run time loader map. */ #define DT_MIPS_DELTA_CLASS 0x70000017 /* Delta C++ class definition. */ #define DT_MIPS_DELTA_CLASS_NO 0x70000018 /* Number of entries in DT_MIPS_DELTA_CLASS. */ #define DT_MIPS_DELTA_INSTANCE 0x70000019 /* Delta C++ class instances. */ #define DT_MIPS_DELTA_INSTANCE_NO 0x7000001a /* Number of entries in DT_MIPS_DELTA_INSTANCE. */ #define DT_MIPS_DELTA_RELOC 0x7000001b /* Delta relocations. */ #define DT_MIPS_DELTA_RELOC_NO 0x7000001c /* Number of entries in DT_MIPS_DELTA_RELOC. */ #define DT_MIPS_DELTA_SYM 0x7000001d /* Delta symbols that Delta relocations refer to. */ #define DT_MIPS_DELTA_SYM_NO 0x7000001e /* Number of entries in DT_MIPS_DELTA_SYM. */ #define DT_MIPS_DELTA_CLASSSYM 0x70000020 /* Delta symbols that hold the class declaration. */ #define DT_MIPS_DELTA_CLASSSYM_NO 0x70000021 /* Number of entries in DT_MIPS_DELTA_CLASSSYM. */ #define DT_MIPS_CXX_FLAGS 0x70000022 /* Flags indicating for C++ flavor. */ #define DT_MIPS_PIXIE_INIT 0x70000023 #define DT_MIPS_SYMBOL_LIB 0x70000024 #define DT_MIPS_LOCALPAGE_GOTIDX 0x70000025 #define DT_MIPS_LOCAL_GOTIDX 0x70000026 #define DT_MIPS_HIDDEN_GOTIDX 0x70000027 #define DT_MIPS_PROTECTED_GOTIDX 0x70000028 #define DT_MIPS_OPTIONS 0x70000029 /* Address of .options. */ #define DT_MIPS_INTERFACE 0x7000002a /* Address of .interface. */ #define DT_MIPS_DYNSTR_ALIGN 0x7000002b #define DT_MIPS_INTERFACE_SIZE 0x7000002c /* Size of the .interface section. */ #define DT_MIPS_RLD_TEXT_RESOLVE_ADDR 0x7000002d /* Address of rld_text_rsolve function stored in GOT. */ #define DT_MIPS_PERF_SUFFIX 0x7000002e /* Default suffix of dso to be added by rld on dlopen() calls. */ #define DT_MIPS_COMPACT_SIZE 0x7000002f /* (O32)Size of compact rel section. */ #define DT_MIPS_GP_VALUE 0x70000030 /* GP value for aux GOTs. */ #define DT_MIPS_AUX_DYNAMIC 0x70000031 /* Address of aux .dynamic. */ /* The address of .got.plt in an executable using the new non-PIC ABI. */ #define DT_MIPS_PLTGOT 0x70000032 /* The base of the PLT in an executable using the new non-PIC ABI if that PLT is writable. For a non-writable PLT, this is omitted or has a zero value. */ #define DT_MIPS_RWPLT 0x70000034 #define DT_MIPS_NUM 0x35 /* Legal values for DT_MIPS_FLAGS Elf32_Dyn entry. */ #define RHF_NONE 0 /* No flags */ #define RHF_QUICKSTART (1 << 0) /* Use quickstart */ #define RHF_NOTPOT (1 << 1) /* Hash size not power of 2 */ #define RHF_NO_LIBRARY_REPLACEMENT (1 << 2) /* Ignore LD_LIBRARY_PATH */ #define RHF_NO_MOVE (1 << 3) #define RHF_SGI_ONLY (1 << 4) #define RHF_GUARANTEE_INIT (1 << 5) #define RHF_DELTA_C_PLUS_PLUS (1 << 6) #define RHF_GUARANTEE_START_INIT (1 << 7) #define RHF_PIXIE (1 << 8) #define RHF_DEFAULT_DELAY_LOAD (1 << 9) #define RHF_REQUICKSTART (1 << 10) #define RHF_REQUICKSTARTED (1 << 11) #define RHF_CORD (1 << 12) #define RHF_NO_UNRES_UNDEF (1 << 13) #define RHF_RLD_ORDER_SAFE (1 << 14) /* Entries found in sections of type SHT_MIPS_LIBLIST. */ typedef struct { Elf32_Word l_name; /* Name (string table index) */ Elf32_Word l_time_stamp; /* Timestamp */ Elf32_Word l_checksum; /* Checksum */ Elf32_Word l_version; /* Interface version */ Elf32_Word l_flags; /* Flags */ } Elf32_Lib; typedef struct { Elf64_Word l_name; /* Name (string table index) */ Elf64_Word l_time_stamp; /* Timestamp */ Elf64_Word l_checksum; /* Checksum */ Elf64_Word l_version; /* Interface version */ Elf64_Word l_flags; /* Flags */ } Elf64_Lib; /* Legal values for l_flags. */ #define LL_NONE 0 #define LL_EXACT_MATCH (1 << 0) /* Require exact match */ #define LL_IGNORE_INT_VER (1 << 1) /* Ignore interface version */ #define LL_REQUIRE_MINOR (1 << 2) #define LL_EXPORTS (1 << 3) #define LL_DELAY_LOAD (1 << 4) #define LL_DELTA (1 << 5) /* Entries found in sections of type SHT_MIPS_CONFLICT. */ typedef Elf32_Addr Elf32_Conflict; /* HPPA specific definitions. */ /* Legal values for e_flags field of Elf32_Ehdr. */ #define EF_PARISC_TRAPNIL 0x00010000 /* Trap nil pointer dereference. */ #define EF_PARISC_EXT 0x00020000 /* Program uses arch. extensions. */ #define EF_PARISC_LSB 0x00040000 /* Program expects little endian. */ #define EF_PARISC_WIDE 0x00080000 /* Program expects wide mode. */ #define EF_PARISC_NO_KABP 0x00100000 /* No kernel assisted branch prediction. */ #define EF_PARISC_LAZYSWAP 0x00400000 /* Allow lazy swapping. */ #define EF_PARISC_ARCH 0x0000ffff /* Architecture version. */ /* Defined values for `e_flags & EF_PARISC_ARCH' are: */ #define EFA_PARISC_1_0 0x020b /* PA-RISC 1.0 big-endian. */ #define EFA_PARISC_1_1 0x0210 /* PA-RISC 1.1 big-endian. */ #define EFA_PARISC_2_0 0x0214 /* PA-RISC 2.0 big-endian. */ /* Additional section indeces. */ #define SHN_PARISC_ANSI_COMMON 0xff00 /* Section for tenatively declared symbols in ANSI C. */ #define SHN_PARISC_HUGE_COMMON 0xff01 /* Common blocks in huge model. */ /* Legal values for sh_type field of Elf32_Shdr. */ #define SHT_PARISC_EXT 0x70000000 /* Contains product specific ext. */ #define SHT_PARISC_UNWIND 0x70000001 /* Unwind information. */ #define SHT_PARISC_DOC 0x70000002 /* Debug info for optimized code. */ /* Legal values for sh_flags field of Elf32_Shdr. */ #define SHF_PARISC_SHORT 0x20000000 /* Section with short addressing. */ #define SHF_PARISC_HUGE 0x40000000 /* Section far from gp. */ #define SHF_PARISC_SBP 0x80000000 /* Static branch prediction code. */ /* Legal values for ST_TYPE subfield of st_info (symbol type). */ #define STT_PARISC_MILLICODE 13 /* Millicode function entry point. */ #define STT_HP_OPAQUE (STT_LOOS + 0x1) #define STT_HP_STUB (STT_LOOS + 0x2) /* HPPA relocs. */ #define R_PARISC_NONE 0 /* No reloc. */ #define R_PARISC_DIR32 1 /* Direct 32-bit reference. */ #define R_PARISC_DIR21L 2 /* Left 21 bits of eff. address. */ #define R_PARISC_DIR17R 3 /* Right 17 bits of eff. address. */ #define R_PARISC_DIR17F 4 /* 17 bits of eff. address. */ #define R_PARISC_DIR14R 6 /* Right 14 bits of eff. address. */ #define R_PARISC_PCREL32 9 /* 32-bit rel. address. */ #define R_PARISC_PCREL21L 10 /* Left 21 bits of rel. address. */ #define R_PARISC_PCREL17R 11 /* Right 17 bits of rel. address. */ #define R_PARISC_PCREL17F 12 /* 17 bits of rel. address. */ #define R_PARISC_PCREL14R 14 /* Right 14 bits of rel. address. */ #define R_PARISC_DPREL21L 18 /* Left 21 bits of rel. address. */ #define R_PARISC_DPREL14R 22 /* Right 14 bits of rel. address. */ #define R_PARISC_GPREL21L 26 /* GP-relative, left 21 bits. */ #define R_PARISC_GPREL14R 30 /* GP-relative, right 14 bits. */ #define R_PARISC_LTOFF21L 34 /* LT-relative, left 21 bits. */ #define R_PARISC_LTOFF14R 38 /* LT-relative, right 14 bits. */ #define R_PARISC_SECREL32 41 /* 32 bits section rel. address. */ #define R_PARISC_SEGBASE 48 /* No relocation, set segment base. */ #define R_PARISC_SEGREL32 49 /* 32 bits segment rel. address. */ #define R_PARISC_PLTOFF21L 50 /* PLT rel. address, left 21 bits. */ #define R_PARISC_PLTOFF14R 54 /* PLT rel. address, right 14 bits. */ #define R_PARISC_LTOFF_FPTR32 57 /* 32 bits LT-rel. function pointer. */ #define R_PARISC_LTOFF_FPTR21L 58 /* LT-rel. fct ptr, left 21 bits. */ #define R_PARISC_LTOFF_FPTR14R 62 /* LT-rel. fct ptr, right 14 bits. */ #define R_PARISC_FPTR64 64 /* 64 bits function address. */ #define R_PARISC_PLABEL32 65 /* 32 bits function address. */ #define R_PARISC_PLABEL21L 66 /* Left 21 bits of fdesc address. */ #define R_PARISC_PLABEL14R 70 /* Right 14 bits of fdesc address. */ #define R_PARISC_PCREL64 72 /* 64 bits PC-rel. address. */ #define R_PARISC_PCREL22F 74 /* 22 bits PC-rel. address. */ #define R_PARISC_PCREL14WR 75 /* PC-rel. address, right 14 bits. */ #define R_PARISC_PCREL14DR 76 /* PC rel. address, right 14 bits. */ #define R_PARISC_PCREL16F 77 /* 16 bits PC-rel. address. */ #define R_PARISC_PCREL16WF 78 /* 16 bits PC-rel. address. */ #define R_PARISC_PCREL16DF 79 /* 16 bits PC-rel. address. */ #define R_PARISC_DIR64 80 /* 64 bits of eff. address. */ #define R_PARISC_DIR14WR 83 /* 14 bits of eff. address. */ #define R_PARISC_DIR14DR 84 /* 14 bits of eff. address. */ #define R_PARISC_DIR16F 85 /* 16 bits of eff. address. */ #define R_PARISC_DIR16WF 86 /* 16 bits of eff. address. */ #define R_PARISC_DIR16DF 87 /* 16 bits of eff. address. */ #define R_PARISC_GPREL64 88 /* 64 bits of GP-rel. address. */ #define R_PARISC_GPREL14WR 91 /* GP-rel. address, right 14 bits. */ #define R_PARISC_GPREL14DR 92 /* GP-rel. address, right 14 bits. */ #define R_PARISC_GPREL16F 93 /* 16 bits GP-rel. address. */ #define R_PARISC_GPREL16WF 94 /* 16 bits GP-rel. address. */ #define R_PARISC_GPREL16DF 95 /* 16 bits GP-rel. address. */ #define R_PARISC_LTOFF64 96 /* 64 bits LT-rel. address. */ #define R_PARISC_LTOFF14WR 99 /* LT-rel. address, right 14 bits. */ #define R_PARISC_LTOFF14DR 100 /* LT-rel. address, right 14 bits. */ #define R_PARISC_LTOFF16F 101 /* 16 bits LT-rel. address. */ #define R_PARISC_LTOFF16WF 102 /* 16 bits LT-rel. address. */ #define R_PARISC_LTOFF16DF 103 /* 16 bits LT-rel. address. */ #define R_PARISC_SECREL64 104 /* 64 bits section rel. address. */ #define R_PARISC_SEGREL64 112 /* 64 bits segment rel. address. */ #define R_PARISC_PLTOFF14WR 115 /* PLT-rel. address, right 14 bits. */ #define R_PARISC_PLTOFF14DR 116 /* PLT-rel. address, right 14 bits. */ #define R_PARISC_PLTOFF16F 117 /* 16 bits LT-rel. address. */ #define R_PARISC_PLTOFF16WF 118 /* 16 bits PLT-rel. address. */ #define R_PARISC_PLTOFF16DF 119 /* 16 bits PLT-rel. address. */ #define R_PARISC_LTOFF_FPTR64 120 /* 64 bits LT-rel. function ptr. */ #define R_PARISC_LTOFF_FPTR14WR 123 /* LT-rel. fct. ptr., right 14 bits. */ #define R_PARISC_LTOFF_FPTR14DR 124 /* LT-rel. fct. ptr., right 14 bits. */ #define R_PARISC_LTOFF_FPTR16F 125 /* 16 bits LT-rel. function ptr. */ #define R_PARISC_LTOFF_FPTR16WF 126 /* 16 bits LT-rel. function ptr. */ #define R_PARISC_LTOFF_FPTR16DF 127 /* 16 bits LT-rel. function ptr. */ #define R_PARISC_LORESERVE 128 #define R_PARISC_COPY 128 /* Copy relocation. */ #define R_PARISC_IPLT 129 /* Dynamic reloc, imported PLT */ #define R_PARISC_EPLT 130 /* Dynamic reloc, exported PLT */ #define R_PARISC_TPREL32 153 /* 32 bits TP-rel. address. */ #define R_PARISC_TPREL21L 154 /* TP-rel. address, left 21 bits. */ #define R_PARISC_TPREL14R 158 /* TP-rel. address, right 14 bits. */ #define R_PARISC_LTOFF_TP21L 162 /* LT-TP-rel. address, left 21 bits. */ #define R_PARISC_LTOFF_TP14R 166 /* LT-TP-rel. address, right 14 bits.*/ #define R_PARISC_LTOFF_TP14F 167 /* 14 bits LT-TP-rel. address. */ #define R_PARISC_TPREL64 216 /* 64 bits TP-rel. address. */ #define R_PARISC_TPREL14WR 219 /* TP-rel. address, right 14 bits. */ #define R_PARISC_TPREL14DR 220 /* TP-rel. address, right 14 bits. */ #define R_PARISC_TPREL16F 221 /* 16 bits TP-rel. address. */ #define R_PARISC_TPREL16WF 222 /* 16 bits TP-rel. address. */ #define R_PARISC_TPREL16DF 223 /* 16 bits TP-rel. address. */ #define R_PARISC_LTOFF_TP64 224 /* 64 bits LT-TP-rel. address. */ #define R_PARISC_LTOFF_TP14WR 227 /* LT-TP-rel. address, right 14 bits.*/ #define R_PARISC_LTOFF_TP14DR 228 /* LT-TP-rel. address, right 14 bits.*/ #define R_PARISC_LTOFF_TP16F 229 /* 16 bits LT-TP-rel. address. */ #define R_PARISC_LTOFF_TP16WF 230 /* 16 bits LT-TP-rel. address. */ #define R_PARISC_LTOFF_TP16DF 231 /* 16 bits LT-TP-rel. address. */ #define R_PARISC_GNU_VTENTRY 232 #define R_PARISC_GNU_VTINHERIT 233 #define R_PARISC_TLS_GD21L 234 /* GD 21-bit left. */ #define R_PARISC_TLS_GD14R 235 /* GD 14-bit right. */ #define R_PARISC_TLS_GDCALL 236 /* GD call to __t_g_a. */ #define R_PARISC_TLS_LDM21L 237 /* LD module 21-bit left. */ #define R_PARISC_TLS_LDM14R 238 /* LD module 14-bit right. */ #define R_PARISC_TLS_LDMCALL 239 /* LD module call to __t_g_a. */ #define R_PARISC_TLS_LDO21L 240 /* LD offset 21-bit left. */ #define R_PARISC_TLS_LDO14R 241 /* LD offset 14-bit right. */ #define R_PARISC_TLS_DTPMOD32 242 /* DTP module 32-bit. */ #define R_PARISC_TLS_DTPMOD64 243 /* DTP module 64-bit. */ #define R_PARISC_TLS_DTPOFF32 244 /* DTP offset 32-bit. */ #define R_PARISC_TLS_DTPOFF64 245 /* DTP offset 32-bit. */ #define R_PARISC_TLS_LE21L R_PARISC_TPREL21L #define R_PARISC_TLS_LE14R R_PARISC_TPREL14R #define R_PARISC_TLS_IE21L R_PARISC_LTOFF_TP21L #define R_PARISC_TLS_IE14R R_PARISC_LTOFF_TP14R #define R_PARISC_TLS_TPREL32 R_PARISC_TPREL32 #define R_PARISC_TLS_TPREL64 R_PARISC_TPREL64 #define R_PARISC_HIRESERVE 255 /* Legal values for p_type field of Elf32_Phdr/Elf64_Phdr. */ #define PT_HP_TLS (PT_LOOS + 0x0) #define PT_HP_CORE_NONE (PT_LOOS + 0x1) #define PT_HP_CORE_VERSION (PT_LOOS + 0x2) #define PT_HP_CORE_KERNEL (PT_LOOS + 0x3) #define PT_HP_CORE_COMM (PT_LOOS + 0x4) #define PT_HP_CORE_PROC (PT_LOOS + 0x5) #define PT_HP_CORE_LOADABLE (PT_LOOS + 0x6) #define PT_HP_CORE_STACK (PT_LOOS + 0x7) #define PT_HP_CORE_SHM (PT_LOOS + 0x8) #define PT_HP_CORE_MMF (PT_LOOS + 0x9) #define PT_HP_PARALLEL (PT_LOOS + 0x10) #define PT_HP_FASTBIND (PT_LOOS + 0x11) #define PT_HP_OPT_ANNOT (PT_LOOS + 0x12) #define PT_HP_HSL_ANNOT (PT_LOOS + 0x13) #define PT_HP_STACK (PT_LOOS + 0x14) #define PT_PARISC_ARCHEXT 0x70000000 #define PT_PARISC_UNWIND 0x70000001 /* Legal values for p_flags field of Elf32_Phdr/Elf64_Phdr. */ #define PF_PARISC_SBP 0x08000000 #define PF_HP_PAGE_SIZE 0x00100000 #define PF_HP_FAR_SHARED 0x00200000 #define PF_HP_NEAR_SHARED 0x00400000 #define PF_HP_CODE 0x01000000 #define PF_HP_MODIFY 0x02000000 #define PF_HP_LAZYSWAP 0x04000000 #define PF_HP_SBP 0x08000000 /* Alpha specific definitions. */ /* Legal values for e_flags field of Elf64_Ehdr. */ #define EF_ALPHA_32BIT 1 /* All addresses must be < 2GB. */ #define EF_ALPHA_CANRELAX 2 /* Relocations for relaxing exist. */ /* Legal values for sh_type field of Elf64_Shdr. */ /* These two are primerily concerned with ECOFF debugging info. */ #define SHT_ALPHA_DEBUG 0x70000001 #define SHT_ALPHA_REGINFO 0x70000002 /* Legal values for sh_flags field of Elf64_Shdr. */ #define SHF_ALPHA_GPREL 0x10000000 /* Legal values for st_other field of Elf64_Sym. */ #define STO_ALPHA_NOPV 0x80 /* No PV required. */ #define STO_ALPHA_STD_GPLOAD 0x88 /* PV only used for initial ldgp. */ /* Alpha relocs. */ #define R_ALPHA_NONE 0 /* No reloc */ #define R_ALPHA_REFLONG 1 /* Direct 32 bit */ #define R_ALPHA_REFQUAD 2 /* Direct 64 bit */ #define R_ALPHA_GPREL32 3 /* GP relative 32 bit */ #define R_ALPHA_LITERAL 4 /* GP relative 16 bit w/optimization */ #define R_ALPHA_LITUSE 5 /* Optimization hint for LITERAL */ #define R_ALPHA_GPDISP 6 /* Add displacement to GP */ #define R_ALPHA_BRADDR 7 /* PC+4 relative 23 bit shifted */ #define R_ALPHA_HINT 8 /* PC+4 relative 16 bit shifted */ #define R_ALPHA_SREL16 9 /* PC relative 16 bit */ #define R_ALPHA_SREL32 10 /* PC relative 32 bit */ #define R_ALPHA_SREL64 11 /* PC relative 64 bit */ #define R_ALPHA_GPRELHIGH 17 /* GP relative 32 bit, high 16 bits */ #define R_ALPHA_GPRELLOW 18 /* GP relative 32 bit, low 16 bits */ #define R_ALPHA_GPREL16 19 /* GP relative 16 bit */ #define R_ALPHA_COPY 24 /* Copy symbol at runtime */ #define R_ALPHA_GLOB_DAT 25 /* Create GOT entry */ #define R_ALPHA_JMP_SLOT 26 /* Create PLT entry */ #define R_ALPHA_RELATIVE 27 /* Adjust by program base */ #define R_ALPHA_TLS_GD_HI 28 #define R_ALPHA_TLSGD 29 #define R_ALPHA_TLS_LDM 30 #define R_ALPHA_DTPMOD64 31 #define R_ALPHA_GOTDTPREL 32 #define R_ALPHA_DTPREL64 33 #define R_ALPHA_DTPRELHI 34 #define R_ALPHA_DTPRELLO 35 #define R_ALPHA_DTPREL16 36 #define R_ALPHA_GOTTPREL 37 #define R_ALPHA_TPREL64 38 #define R_ALPHA_TPRELHI 39 #define R_ALPHA_TPRELLO 40 #define R_ALPHA_TPREL16 41 /* Keep this the last entry. */ #define R_ALPHA_NUM 46 /* Magic values of the LITUSE relocation addend. */ #define LITUSE_ALPHA_ADDR 0 #define LITUSE_ALPHA_BASE 1 #define LITUSE_ALPHA_BYTOFF 2 #define LITUSE_ALPHA_JSR 3 #define LITUSE_ALPHA_TLS_GD 4 #define LITUSE_ALPHA_TLS_LDM 5 /* Legal values for d_tag of Elf64_Dyn. */ #define DT_ALPHA_PLTRO (DT_LOPROC + 0) #define DT_ALPHA_NUM 1 /* PowerPC specific declarations */ /* Values for Elf32/64_Ehdr.e_flags. */ #define EF_PPC_EMB 0x80000000 /* PowerPC embedded flag */ /* Cygnus local bits below */ #define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag*/ #define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib flag */ /* PowerPC relocations defined by the ABIs */ #define R_PPC_NONE 0 #define R_PPC_ADDR32 1 /* 32bit absolute address */ #define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */ #define R_PPC_ADDR16 3 /* 16bit absolute address */ #define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */ #define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */ #define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */ #define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */ #define R_PPC_ADDR14_BRTAKEN 8 #define R_PPC_ADDR14_BRNTAKEN 9 #define R_PPC_REL24 10 /* PC relative 26 bit */ #define R_PPC_REL14 11 /* PC relative 16 bit */ #define R_PPC_REL14_BRTAKEN 12 #define R_PPC_REL14_BRNTAKEN 13 #define R_PPC_GOT16 14 #define R_PPC_GOT16_LO 15 #define R_PPC_GOT16_HI 16 #define R_PPC_GOT16_HA 17 #define R_PPC_PLTREL24 18 #define R_PPC_COPY 19 #define R_PPC_GLOB_DAT 20 #define R_PPC_JMP_SLOT 21 #define R_PPC_RELATIVE 22 #define R_PPC_LOCAL24PC 23 #define R_PPC_UADDR32 24 #define R_PPC_UADDR16 25 #define R_PPC_REL32 26 #define R_PPC_PLT32 27 #define R_PPC_PLTREL32 28 #define R_PPC_PLT16_LO 29 #define R_PPC_PLT16_HI 30 #define R_PPC_PLT16_HA 31 #define R_PPC_SDAREL16 32 #define R_PPC_SECTOFF 33 #define R_PPC_SECTOFF_LO 34 #define R_PPC_SECTOFF_HI 35 #define R_PPC_SECTOFF_HA 36 /* PowerPC relocations defined for the TLS access ABI. */ #define R_PPC_TLS 67 /* none (sym+add)@tls */ #define R_PPC_DTPMOD32 68 /* word32 (sym+add)@dtpmod */ #define R_PPC_TPREL16 69 /* half16* (sym+add)@tprel */ #define R_PPC_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ #define R_PPC_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ #define R_PPC_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ #define R_PPC_TPREL32 73 /* word32 (sym+add)@tprel */ #define R_PPC_DTPREL16 74 /* half16* (sym+add)@dtprel */ #define R_PPC_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ #define R_PPC_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ #define R_PPC_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ #define R_PPC_DTPREL32 78 /* word32 (sym+add)@dtprel */ #define R_PPC_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ #define R_PPC_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ #define R_PPC_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ #define R_PPC_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ #define R_PPC_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ #define R_PPC_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ #define R_PPC_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ #define R_PPC_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ #define R_PPC_GOT_TPREL16 87 /* half16* (sym+add)@got@tprel */ #define R_PPC_GOT_TPREL16_LO 88 /* half16 (sym+add)@got@tprel@l */ #define R_PPC_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ #define R_PPC_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ #define R_PPC_GOT_DTPREL16 91 /* half16* (sym+add)@got@dtprel */ #define R_PPC_GOT_DTPREL16_LO 92 /* half16* (sym+add)@got@dtprel@l */ #define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */ #define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */ /* The remaining relocs are from the Embedded ELF ABI, and are not in the SVR4 ELF ABI. */ #define R_PPC_EMB_NADDR32 101 #define R_PPC_EMB_NADDR16 102 #define R_PPC_EMB_NADDR16_LO 103 #define R_PPC_EMB_NADDR16_HI 104 #define R_PPC_EMB_NADDR16_HA 105 #define R_PPC_EMB_SDAI16 106 #define R_PPC_EMB_SDA2I16 107 #define R_PPC_EMB_SDA2REL 108 #define R_PPC_EMB_SDA21 109 /* 16 bit offset in SDA */ #define R_PPC_EMB_MRKREF 110 #define R_PPC_EMB_RELSEC16 111 #define R_PPC_EMB_RELST_LO 112 #define R_PPC_EMB_RELST_HI 113 #define R_PPC_EMB_RELST_HA 114 #define R_PPC_EMB_BIT_FLD 115 #define R_PPC_EMB_RELSDA 116 /* 16 bit relative offset in SDA */ /* Diab tool relocations. */ #define R_PPC_DIAB_SDA21_LO 180 /* like EMB_SDA21, but lower 16 bit */ #define R_PPC_DIAB_SDA21_HI 181 /* like EMB_SDA21, but high 16 bit */ #define R_PPC_DIAB_SDA21_HA 182 /* like EMB_SDA21, adjusted high 16 */ #define R_PPC_DIAB_RELSDA_LO 183 /* like EMB_RELSDA, but lower 16 bit */ #define R_PPC_DIAB_RELSDA_HI 184 /* like EMB_RELSDA, but high 16 bit */ #define R_PPC_DIAB_RELSDA_HA 185 /* like EMB_RELSDA, adjusted high 16 */ /* GNU extension to support local ifunc. */ #define R_PPC_IRELATIVE 248 /* GNU relocs used in PIC code sequences. */ #define R_PPC_REL16 249 /* half16 (sym+add-.) */ #define R_PPC_REL16_LO 250 /* half16 (sym+add-.)@l */ #define R_PPC_REL16_HI 251 /* half16 (sym+add-.)@h */ #define R_PPC_REL16_HA 252 /* half16 (sym+add-.)@ha */ /* This is a phony reloc to handle any old fashioned TOC16 references that may still be in object files. */ #define R_PPC_TOC16 255 /* PowerPC specific values for the Dyn d_tag field. */ #define DT_PPC_GOT (DT_LOPROC + 0) #define DT_PPC_NUM 1 /* PowerPC64 relocations defined by the ABIs */ #define R_PPC64_NONE R_PPC_NONE #define R_PPC64_ADDR32 R_PPC_ADDR32 /* 32bit absolute address */ #define R_PPC64_ADDR24 R_PPC_ADDR24 /* 26bit address, word aligned */ #define R_PPC64_ADDR16 R_PPC_ADDR16 /* 16bit absolute address */ #define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of address */ #define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of address. */ #define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits. */ #define R_PPC64_ADDR14 R_PPC_ADDR14 /* 16bit address, word aligned */ #define R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN #define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN #define R_PPC64_REL24 R_PPC_REL24 /* PC-rel. 26 bit, word aligned */ #define R_PPC64_REL14 R_PPC_REL14 /* PC relative 16 bit */ #define R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN #define R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN #define R_PPC64_GOT16 R_PPC_GOT16 #define R_PPC64_GOT16_LO R_PPC_GOT16_LO #define R_PPC64_GOT16_HI R_PPC_GOT16_HI #define R_PPC64_GOT16_HA R_PPC_GOT16_HA #define R_PPC64_COPY R_PPC_COPY #define R_PPC64_GLOB_DAT R_PPC_GLOB_DAT #define R_PPC64_JMP_SLOT R_PPC_JMP_SLOT #define R_PPC64_RELATIVE R_PPC_RELATIVE #define R_PPC64_UADDR32 R_PPC_UADDR32 #define R_PPC64_UADDR16 R_PPC_UADDR16 #define R_PPC64_REL32 R_PPC_REL32 #define R_PPC64_PLT32 R_PPC_PLT32 #define R_PPC64_PLTREL32 R_PPC_PLTREL32 #define R_PPC64_PLT16_LO R_PPC_PLT16_LO #define R_PPC64_PLT16_HI R_PPC_PLT16_HI #define R_PPC64_PLT16_HA R_PPC_PLT16_HA #define R_PPC64_SECTOFF R_PPC_SECTOFF #define R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO #define R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI #define R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA #define R_PPC64_ADDR30 37 /* word30 (S + A - P) >> 2 */ #define R_PPC64_ADDR64 38 /* doubleword64 S + A */ #define R_PPC64_ADDR16_HIGHER 39 /* half16 #higher(S + A) */ #define R_PPC64_ADDR16_HIGHERA 40 /* half16 #highera(S + A) */ #define R_PPC64_ADDR16_HIGHEST 41 /* half16 #highest(S + A) */ #define R_PPC64_ADDR16_HIGHESTA 42 /* half16 #highesta(S + A) */ #define R_PPC64_UADDR64 43 /* doubleword64 S + A */ #define R_PPC64_REL64 44 /* doubleword64 S + A - P */ #define R_PPC64_PLT64 45 /* doubleword64 L + A */ #define R_PPC64_PLTREL64 46 /* doubleword64 L + A - P */ #define R_PPC64_TOC16 47 /* half16* S + A - .TOC */ #define R_PPC64_TOC16_LO 48 /* half16 #lo(S + A - .TOC.) */ #define R_PPC64_TOC16_HI 49 /* half16 #hi(S + A - .TOC.) */ #define R_PPC64_TOC16_HA 50 /* half16 #ha(S + A - .TOC.) */ #define R_PPC64_TOC 51 /* doubleword64 .TOC */ #define R_PPC64_PLTGOT16 52 /* half16* M + A */ #define R_PPC64_PLTGOT16_LO 53 /* half16 #lo(M + A) */ #define R_PPC64_PLTGOT16_HI 54 /* half16 #hi(M + A) */ #define R_PPC64_PLTGOT16_HA 55 /* half16 #ha(M + A) */ #define R_PPC64_ADDR16_DS 56 /* half16ds* (S + A) >> 2 */ #define R_PPC64_ADDR16_LO_DS 57 /* half16ds #lo(S + A) >> 2 */ #define R_PPC64_GOT16_DS 58 /* half16ds* (G + A) >> 2 */ #define R_PPC64_GOT16_LO_DS 59 /* half16ds #lo(G + A) >> 2 */ #define R_PPC64_PLT16_LO_DS 60 /* half16ds #lo(L + A) >> 2 */ #define R_PPC64_SECTOFF_DS 61 /* half16ds* (R + A) >> 2 */ #define R_PPC64_SECTOFF_LO_DS 62 /* half16ds #lo(R + A) >> 2 */ #define R_PPC64_TOC16_DS 63 /* half16ds* (S + A - .TOC.) >> 2 */ #define R_PPC64_TOC16_LO_DS 64 /* half16ds #lo(S + A - .TOC.) >> 2 */ #define R_PPC64_PLTGOT16_DS 65 /* half16ds* (M + A) >> 2 */ #define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds #lo(M + A) >> 2 */ /* PowerPC64 relocations defined for the TLS access ABI. */ #define R_PPC64_TLS 67 /* none (sym+add)@tls */ #define R_PPC64_DTPMOD64 68 /* doubleword64 (sym+add)@dtpmod */ #define R_PPC64_TPREL16 69 /* half16* (sym+add)@tprel */ #define R_PPC64_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ #define R_PPC64_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ #define R_PPC64_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ #define R_PPC64_TPREL64 73 /* doubleword64 (sym+add)@tprel */ #define R_PPC64_DTPREL16 74 /* half16* (sym+add)@dtprel */ #define R_PPC64_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ #define R_PPC64_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ #define R_PPC64_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ #define R_PPC64_DTPREL64 78 /* doubleword64 (sym+add)@dtprel */ #define R_PPC64_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ #define R_PPC64_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ #define R_PPC64_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ #define R_PPC64_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ #define R_PPC64_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ #define R_PPC64_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ #define R_PPC64_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ #define R_PPC64_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ #define R_PPC64_GOT_TPREL16_DS 87 /* half16ds* (sym+add)@got@tprel */ #define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */ #define R_PPC64_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ #define R_PPC64_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ #define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */ #define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */ #define R_PPC64_GOT_DTPREL16_HI 93 /* half16 (sym+add)@got@dtprel@h */ #define R_PPC64_GOT_DTPREL16_HA 94 /* half16 (sym+add)@got@dtprel@ha */ #define R_PPC64_TPREL16_DS 95 /* half16ds* (sym+add)@tprel */ #define R_PPC64_TPREL16_LO_DS 96 /* half16ds (sym+add)@tprel@l */ #define R_PPC64_TPREL16_HIGHER 97 /* half16 (sym+add)@tprel@higher */ #define R_PPC64_TPREL16_HIGHERA 98 /* half16 (sym+add)@tprel@highera */ #define R_PPC64_TPREL16_HIGHEST 99 /* half16 (sym+add)@tprel@highest */ #define R_PPC64_TPREL16_HIGHESTA 100 /* half16 (sym+add)@tprel@highesta */ #define R_PPC64_DTPREL16_DS 101 /* half16ds* (sym+add)@dtprel */ #define R_PPC64_DTPREL16_LO_DS 102 /* half16ds (sym+add)@dtprel@l */ #define R_PPC64_DTPREL16_HIGHER 103 /* half16 (sym+add)@dtprel@higher */ #define R_PPC64_DTPREL16_HIGHERA 104 /* half16 (sym+add)@dtprel@highera */ #define R_PPC64_DTPREL16_HIGHEST 105 /* half16 (sym+add)@dtprel@highest */ #define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */ /* GNU extension to support local ifunc. */ #define R_PPC64_JMP_IREL 247 #define R_PPC64_IRELATIVE 248 #define R_PPC64_REL16 249 /* half16 (sym+add-.) */ #define R_PPC64_REL16_LO 250 /* half16 (sym+add-.)@l */ #define R_PPC64_REL16_HI 251 /* half16 (sym+add-.)@h */ #define R_PPC64_REL16_HA 252 /* half16 (sym+add-.)@ha */ /* PowerPC64 specific values for the Dyn d_tag field. */ #define DT_PPC64_GLINK (DT_LOPROC + 0) #define DT_PPC64_OPD (DT_LOPROC + 1) #define DT_PPC64_OPDSZ (DT_LOPROC + 2) #define DT_PPC64_NUM 3 /* ARM specific declarations */ /* Processor specific flags for the ELF header e_flags field. */ #define EF_ARM_RELEXEC 0x01 #define EF_ARM_HASENTRY 0x02 #define EF_ARM_INTERWORK 0x04 #define EF_ARM_APCS_26 0x08 #define EF_ARM_APCS_FLOAT 0x10 #define EF_ARM_PIC 0x20 #define EF_ARM_ALIGN8 0x40 /* 8-bit structure alignment is in use */ #define EF_ARM_NEW_ABI 0x80 #define EF_ARM_OLD_ABI 0x100 #define EF_ARM_SOFT_FLOAT 0x200 #define EF_ARM_VFP_FLOAT 0x400 #define EF_ARM_MAVERICK_FLOAT 0x800 /* Other constants defined in the ARM ELF spec. version B-01. */ /* NB. These conflict with values defined above. */ #define EF_ARM_SYMSARESORTED 0x04 #define EF_ARM_DYNSYMSUSESEGIDX 0x08 #define EF_ARM_MAPSYMSFIRST 0x10 #define EF_ARM_EABIMASK 0XFF000000 /* Constants defined in AAELF. */ #define EF_ARM_BE8 0x00800000 #define EF_ARM_LE8 0x00400000 #define EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK) #define EF_ARM_EABI_UNKNOWN 0x00000000 #define EF_ARM_EABI_VER1 0x01000000 #define EF_ARM_EABI_VER2 0x02000000 #define EF_ARM_EABI_VER3 0x03000000 #define EF_ARM_EABI_VER4 0x04000000 #define EF_ARM_EABI_VER5 0x05000000 /* Additional symbol types for Thumb. */ #define STT_ARM_TFUNC STT_LOPROC /* A Thumb function. */ #define STT_ARM_16BIT STT_HIPROC /* A Thumb label. */ /* ARM-specific values for sh_flags */ #define SHF_ARM_ENTRYSECT 0x10000000 /* Section contains an entry point */ #define SHF_ARM_COMDEF 0x80000000 /* Section may be multiply defined in the input to a link step. */ /* ARM-specific program header flags */ #define PF_ARM_SB 0x10000000 /* Segment contains the location addressed by the static base. */ #define PF_ARM_PI 0x20000000 /* Position-independent segment. */ #define PF_ARM_ABS 0x40000000 /* Absolute segment. */ /* Processor specific values for the Phdr p_type field. */ #define PT_ARM_EXIDX (PT_LOPROC + 1) /* ARM unwind segment. */ /* Processor specific values for the Shdr sh_type field. */ #define SHT_ARM_EXIDX (SHT_LOPROC + 1) /* ARM unwind section. */ #define SHT_ARM_PREEMPTMAP (SHT_LOPROC + 2) /* Preemption details. */ #define SHT_ARM_ATTRIBUTES (SHT_LOPROC + 3) /* ARM attributes section. */ /* ARM relocs. */ #define R_ARM_NONE 0 /* No reloc */ #define R_ARM_PC24 1 /* PC relative 26 bit branch */ #define R_ARM_ABS32 2 /* Direct 32 bit */ #define R_ARM_REL32 3 /* PC relative 32 bit */ #define R_ARM_PC13 4 #define R_ARM_ABS16 5 /* Direct 16 bit */ #define R_ARM_ABS12 6 /* Direct 12 bit */ #define R_ARM_THM_ABS5 7 #define R_ARM_ABS8 8 /* Direct 8 bit */ #define R_ARM_SBREL32 9 #define R_ARM_THM_PC22 10 #define R_ARM_THM_PC8 11 #define R_ARM_AMP_VCALL9 12 #define R_ARM_SWI24 13 #define R_ARM_THM_SWI8 14 #define R_ARM_XPC25 15 #define R_ARM_THM_XPC22 16 #define R_ARM_TLS_DTPMOD32 17 /* ID of module containing symbol */ #define R_ARM_TLS_DTPOFF32 18 /* Offset in TLS block */ #define R_ARM_TLS_TPOFF32 19 /* Offset in static TLS block */ #define R_ARM_COPY 20 /* Copy symbol at runtime */ #define R_ARM_GLOB_DAT 21 /* Create GOT entry */ #define R_ARM_JUMP_SLOT 22 /* Create PLT entry */ #define R_ARM_RELATIVE 23 /* Adjust by program base */ #define R_ARM_GOTOFF 24 /* 32 bit offset to GOT */ #define R_ARM_GOTPC 25 /* 32 bit PC relative offset to GOT */ #define R_ARM_GOT32 26 /* 32 bit GOT entry */ #define R_ARM_PLT32 27 /* 32 bit PLT address */ #define R_ARM_ALU_PCREL_7_0 32 #define R_ARM_ALU_PCREL_15_8 33 #define R_ARM_ALU_PCREL_23_15 34 #define R_ARM_LDR_SBREL_11_0 35 #define R_ARM_ALU_SBREL_19_12 36 #define R_ARM_ALU_SBREL_27_20 37 #define R_ARM_GNU_VTENTRY 100 #define R_ARM_GNU_VTINHERIT 101 #define R_ARM_THM_PC11 102 /* thumb unconditional branch */ #define R_ARM_THM_PC9 103 /* thumb conditional branch */ #define R_ARM_TLS_GD32 104 /* PC-rel 32 bit for global dynamic thread local data */ #define R_ARM_TLS_LDM32 105 /* PC-rel 32 bit for local dynamic thread local data */ #define R_ARM_TLS_LDO32 106 /* 32 bit offset relative to TLS block */ #define R_ARM_TLS_IE32 107 /* PC-rel 32 bit for GOT entry of static TLS block offset */ #define R_ARM_TLS_LE32 108 /* 32 bit offset relative to static TLS block */ #define R_ARM_RXPC25 249 #define R_ARM_RSBREL32 250 #define R_ARM_THM_RPC22 251 #define R_ARM_RREL32 252 #define R_ARM_RABS22 253 #define R_ARM_RPC24 254 #define R_ARM_RBASE 255 /* Keep this the last entry. */ #define R_ARM_NUM 256 /* IA-64 specific declarations. */ /* Processor specific flags for the Ehdr e_flags field. */ #define EF_IA_64_MASKOS 0x0000000f /* os-specific flags */ #define EF_IA_64_ABI64 0x00000010 /* 64-bit ABI */ #define EF_IA_64_ARCH 0xff000000 /* arch. version mask */ /* Processor specific values for the Phdr p_type field. */ #define PT_IA_64_ARCHEXT (PT_LOPROC + 0) /* arch extension bits */ #define PT_IA_64_UNWIND (PT_LOPROC + 1) /* ia64 unwind bits */ #define PT_IA_64_HP_OPT_ANOT (PT_LOOS + 0x12) #define PT_IA_64_HP_HSL_ANOT (PT_LOOS + 0x13) #define PT_IA_64_HP_STACK (PT_LOOS + 0x14) /* Processor specific flags for the Phdr p_flags field. */ #define PF_IA_64_NORECOV 0x80000000 /* spec insns w/o recovery */ /* Processor specific values for the Shdr sh_type field. */ #define SHT_IA_64_EXT (SHT_LOPROC + 0) /* extension bits */ #define SHT_IA_64_UNWIND (SHT_LOPROC + 1) /* unwind bits */ /* Processor specific flags for the Shdr sh_flags field. */ #define SHF_IA_64_SHORT 0x10000000 /* section near gp */ #define SHF_IA_64_NORECOV 0x20000000 /* spec insns w/o recovery */ /* Processor specific values for the Dyn d_tag field. */ #define DT_IA_64_PLT_RESERVE (DT_LOPROC + 0) #define DT_IA_64_NUM 1 /* IA-64 relocations. */ #define R_IA64_NONE 0x00 /* none */ #define R_IA64_IMM14 0x21 /* symbol + addend, add imm14 */ #define R_IA64_IMM22 0x22 /* symbol + addend, add imm22 */ #define R_IA64_IMM64 0x23 /* symbol + addend, mov imm64 */ #define R_IA64_DIR32MSB 0x24 /* symbol + addend, data4 MSB */ #define R_IA64_DIR32LSB 0x25 /* symbol + addend, data4 LSB */ #define R_IA64_DIR64MSB 0x26 /* symbol + addend, data8 MSB */ #define R_IA64_DIR64LSB 0x27 /* symbol + addend, data8 LSB */ #define R_IA64_GPREL22 0x2a /* @gprel(sym + add), add imm22 */ #define R_IA64_GPREL64I 0x2b /* @gprel(sym + add), mov imm64 */ #define R_IA64_GPREL32MSB 0x2c /* @gprel(sym + add), data4 MSB */ #define R_IA64_GPREL32LSB 0x2d /* @gprel(sym + add), data4 LSB */ #define R_IA64_GPREL64MSB 0x2e /* @gprel(sym + add), data8 MSB */ #define R_IA64_GPREL64LSB 0x2f /* @gprel(sym + add), data8 LSB */ #define R_IA64_LTOFF22 0x32 /* @ltoff(sym + add), add imm22 */ #define R_IA64_LTOFF64I 0x33 /* @ltoff(sym + add), mov imm64 */ #define R_IA64_PLTOFF22 0x3a /* @pltoff(sym + add), add imm22 */ #define R_IA64_PLTOFF64I 0x3b /* @pltoff(sym + add), mov imm64 */ #define R_IA64_PLTOFF64MSB 0x3e /* @pltoff(sym + add), data8 MSB */ #define R_IA64_PLTOFF64LSB 0x3f /* @pltoff(sym + add), data8 LSB */ #define R_IA64_FPTR64I 0x43 /* @fptr(sym + add), mov imm64 */ #define R_IA64_FPTR32MSB 0x44 /* @fptr(sym + add), data4 MSB */ #define R_IA64_FPTR32LSB 0x45 /* @fptr(sym + add), data4 LSB */ #define R_IA64_FPTR64MSB 0x46 /* @fptr(sym + add), data8 MSB */ #define R_IA64_FPTR64LSB 0x47 /* @fptr(sym + add), data8 LSB */ #define R_IA64_PCREL60B 0x48 /* @pcrel(sym + add), brl */ #define R_IA64_PCREL21B 0x49 /* @pcrel(sym + add), ptb, call */ #define R_IA64_PCREL21M 0x4a /* @pcrel(sym + add), chk.s */ #define R_IA64_PCREL21F 0x4b /* @pcrel(sym + add), fchkf */ #define R_IA64_PCREL32MSB 0x4c /* @pcrel(sym + add), data4 MSB */ #define R_IA64_PCREL32LSB 0x4d /* @pcrel(sym + add), data4 LSB */ #define R_IA64_PCREL64MSB 0x4e /* @pcrel(sym + add), data8 MSB */ #define R_IA64_PCREL64LSB 0x4f /* @pcrel(sym + add), data8 LSB */ #define R_IA64_LTOFF_FPTR22 0x52 /* @ltoff(@fptr(s+a)), imm22 */ #define R_IA64_LTOFF_FPTR64I 0x53 /* @ltoff(@fptr(s+a)), imm64 */ #define R_IA64_LTOFF_FPTR32MSB 0x54 /* @ltoff(@fptr(s+a)), data4 MSB */ #define R_IA64_LTOFF_FPTR32LSB 0x55 /* @ltoff(@fptr(s+a)), data4 LSB */ #define R_IA64_LTOFF_FPTR64MSB 0x56 /* @ltoff(@fptr(s+a)), data8 MSB */ #define R_IA64_LTOFF_FPTR64LSB 0x57 /* @ltoff(@fptr(s+a)), data8 LSB */ #define R_IA64_SEGREL32MSB 0x5c /* @segrel(sym + add), data4 MSB */ #define R_IA64_SEGREL32LSB 0x5d /* @segrel(sym + add), data4 LSB */ #define R_IA64_SEGREL64MSB 0x5e /* @segrel(sym + add), data8 MSB */ #define R_IA64_SEGREL64LSB 0x5f /* @segrel(sym + add), data8 LSB */ #define R_IA64_SECREL32MSB 0x64 /* @secrel(sym + add), data4 MSB */ #define R_IA64_SECREL32LSB 0x65 /* @secrel(sym + add), data4 LSB */ #define R_IA64_SECREL64MSB 0x66 /* @secrel(sym + add), data8 MSB */ #define R_IA64_SECREL64LSB 0x67 /* @secrel(sym + add), data8 LSB */ #define R_IA64_REL32MSB 0x6c /* data 4 + REL */ #define R_IA64_REL32LSB 0x6d /* data 4 + REL */ #define R_IA64_REL64MSB 0x6e /* data 8 + REL */ #define R_IA64_REL64LSB 0x6f /* data 8 + REL */ #define R_IA64_LTV32MSB 0x74 /* symbol + addend, data4 MSB */ #define R_IA64_LTV32LSB 0x75 /* symbol + addend, data4 LSB */ #define R_IA64_LTV64MSB 0x76 /* symbol + addend, data8 MSB */ #define R_IA64_LTV64LSB 0x77 /* symbol + addend, data8 LSB */ #define R_IA64_PCREL21BI 0x79 /* @pcrel(sym + add), 21bit inst */ #define R_IA64_PCREL22 0x7a /* @pcrel(sym + add), 22bit inst */ #define R_IA64_PCREL64I 0x7b /* @pcrel(sym + add), 64bit inst */ #define R_IA64_IPLTMSB 0x80 /* dynamic reloc, imported PLT, MSB */ #define R_IA64_IPLTLSB 0x81 /* dynamic reloc, imported PLT, LSB */ #define R_IA64_COPY 0x84 /* copy relocation */ #define R_IA64_SUB 0x85 /* Addend and symbol difference */ #define R_IA64_LTOFF22X 0x86 /* LTOFF22, relaxable. */ #define R_IA64_LDXMOV 0x87 /* Use of LTOFF22X. */ #define R_IA64_TPREL14 0x91 /* @tprel(sym + add), imm14 */ #define R_IA64_TPREL22 0x92 /* @tprel(sym + add), imm22 */ #define R_IA64_TPREL64I 0x93 /* @tprel(sym + add), imm64 */ #define R_IA64_TPREL64MSB 0x96 /* @tprel(sym + add), data8 MSB */ #define R_IA64_TPREL64LSB 0x97 /* @tprel(sym + add), data8 LSB */ #define R_IA64_LTOFF_TPREL22 0x9a /* @ltoff(@tprel(s+a)), imm2 */ #define R_IA64_DTPMOD64MSB 0xa6 /* @dtpmod(sym + add), data8 MSB */ #define R_IA64_DTPMOD64LSB 0xa7 /* @dtpmod(sym + add), data8 LSB */ #define R_IA64_LTOFF_DTPMOD22 0xaa /* @ltoff(@dtpmod(sym + add)), imm22 */ #define R_IA64_DTPREL14 0xb1 /* @dtprel(sym + add), imm14 */ #define R_IA64_DTPREL22 0xb2 /* @dtprel(sym + add), imm22 */ #define R_IA64_DTPREL64I 0xb3 /* @dtprel(sym + add), imm64 */ #define R_IA64_DTPREL32MSB 0xb4 /* @dtprel(sym + add), data4 MSB */ #define R_IA64_DTPREL32LSB 0xb5 /* @dtprel(sym + add), data4 LSB */ #define R_IA64_DTPREL64MSB 0xb6 /* @dtprel(sym + add), data8 MSB */ #define R_IA64_DTPREL64LSB 0xb7 /* @dtprel(sym + add), data8 LSB */ #define R_IA64_LTOFF_DTPREL22 0xba /* @ltoff(@dtprel(s+a)), imm22 */ /* SH specific declarations */ /* SH relocs. */ #define R_SH_NONE 0 #define R_SH_DIR32 1 #define R_SH_REL32 2 #define R_SH_DIR8WPN 3 #define R_SH_IND12W 4 #define R_SH_DIR8WPL 5 #define R_SH_DIR8WPZ 6 #define R_SH_DIR8BP 7 #define R_SH_DIR8W 8 #define R_SH_DIR8L 9 #define R_SH_SWITCH16 25 #define R_SH_SWITCH32 26 #define R_SH_USES 27 #define R_SH_COUNT 28 #define R_SH_ALIGN 29 #define R_SH_CODE 30 #define R_SH_DATA 31 #define R_SH_LABEL 32 #define R_SH_SWITCH8 33 #define R_SH_GNU_VTINHERIT 34 #define R_SH_GNU_VTENTRY 35 #define R_SH_TLS_GD_32 144 #define R_SH_TLS_LD_32 145 #define R_SH_TLS_LDO_32 146 #define R_SH_TLS_IE_32 147 #define R_SH_TLS_LE_32 148 #define R_SH_TLS_DTPMOD32 149 #define R_SH_TLS_DTPOFF32 150 #define R_SH_TLS_TPOFF32 151 #define R_SH_GOT32 160 #define R_SH_PLT32 161 #define R_SH_COPY 162 #define R_SH_GLOB_DAT 163 #define R_SH_JMP_SLOT 164 #define R_SH_RELATIVE 165 #define R_SH_GOTOFF 166 #define R_SH_GOTPC 167 /* Keep this the last entry. */ #define R_SH_NUM 256 /* Additional s390 relocs */ #define R_390_NONE 0 /* No reloc. */ #define R_390_8 1 /* Direct 8 bit. */ #define R_390_12 2 /* Direct 12 bit. */ #define R_390_16 3 /* Direct 16 bit. */ #define R_390_32 4 /* Direct 32 bit. */ #define R_390_PC32 5 /* PC relative 32 bit. */ #define R_390_GOT12 6 /* 12 bit GOT offset. */ #define R_390_GOT32 7 /* 32 bit GOT offset. */ #define R_390_PLT32 8 /* 32 bit PC relative PLT address. */ #define R_390_COPY 9 /* Copy symbol at runtime. */ #define R_390_GLOB_DAT 10 /* Create GOT entry. */ #define R_390_JMP_SLOT 11 /* Create PLT entry. */ #define R_390_RELATIVE 12 /* Adjust by program base. */ #define R_390_GOTOFF32 13 /* 32 bit offset to GOT. */ #define R_390_GOTPC 14 /* 32 bit PC relative offset to GOT. */ #define R_390_GOT16 15 /* 16 bit GOT offset. */ #define R_390_PC16 16 /* PC relative 16 bit. */ #define R_390_PC16DBL 17 /* PC relative 16 bit shifted by 1. */ #define R_390_PLT16DBL 18 /* 16 bit PC rel. PLT shifted by 1. */ #define R_390_PC32DBL 19 /* PC relative 32 bit shifted by 1. */ #define R_390_PLT32DBL 20 /* 32 bit PC rel. PLT shifted by 1. */ #define R_390_GOTPCDBL 21 /* 32 bit PC rel. GOT shifted by 1. */ #define R_390_64 22 /* Direct 64 bit. */ #define R_390_PC64 23 /* PC relative 64 bit. */ #define R_390_GOT64 24 /* 64 bit GOT offset. */ #define R_390_PLT64 25 /* 64 bit PC relative PLT address. */ #define R_390_GOTENT 26 /* 32 bit PC rel. to GOT entry >> 1. */ #define R_390_GOTOFF16 27 /* 16 bit offset to GOT. */ #define R_390_GOTOFF64 28 /* 64 bit offset to GOT. */ #define R_390_GOTPLT12 29 /* 12 bit offset to jump slot. */ #define R_390_GOTPLT16 30 /* 16 bit offset to jump slot. */ #define R_390_GOTPLT32 31 /* 32 bit offset to jump slot. */ #define R_390_GOTPLT64 32 /* 64 bit offset to jump slot. */ #define R_390_GOTPLTENT 33 /* 32 bit rel. offset to jump slot. */ #define R_390_PLTOFF16 34 /* 16 bit offset from GOT to PLT. */ #define R_390_PLTOFF32 35 /* 32 bit offset from GOT to PLT. */ #define R_390_PLTOFF64 36 /* 16 bit offset from GOT to PLT. */ #define R_390_TLS_LOAD 37 /* Tag for load insn in TLS code. */ #define R_390_TLS_GDCALL 38 /* Tag for function call in general dynamic TLS code. */ #define R_390_TLS_LDCALL 39 /* Tag for function call in local dynamic TLS code. */ #define R_390_TLS_GD32 40 /* Direct 32 bit for general dynamic thread local data. */ #define R_390_TLS_GD64 41 /* Direct 64 bit for general dynamic thread local data. */ #define R_390_TLS_GOTIE12 42 /* 12 bit GOT offset for static TLS block offset. */ #define R_390_TLS_GOTIE32 43 /* 32 bit GOT offset for static TLS block offset. */ #define R_390_TLS_GOTIE64 44 /* 64 bit GOT offset for static TLS block offset. */ #define R_390_TLS_LDM32 45 /* Direct 32 bit for local dynamic thread local data in LE code. */ #define R_390_TLS_LDM64 46 /* Direct 64 bit for local dynamic thread local data in LE code. */ #define R_390_TLS_IE32 47 /* 32 bit address of GOT entry for negated static TLS block offset. */ #define R_390_TLS_IE64 48 /* 64 bit address of GOT entry for negated static TLS block offset. */ #define R_390_TLS_IEENT 49 /* 32 bit rel. offset to GOT entry for negated static TLS block offset. */ #define R_390_TLS_LE32 50 /* 32 bit negated offset relative to static TLS block. */ #define R_390_TLS_LE64 51 /* 64 bit negated offset relative to static TLS block. */ #define R_390_TLS_LDO32 52 /* 32 bit offset relative to TLS block. */ #define R_390_TLS_LDO64 53 /* 64 bit offset relative to TLS block. */ #define R_390_TLS_DTPMOD 54 /* ID of module containing symbol. */ #define R_390_TLS_DTPOFF 55 /* Offset in TLS block. */ #define R_390_TLS_TPOFF 56 /* Negated offset in static TLS block. */ #define R_390_20 57 /* Direct 20 bit. */ #define R_390_GOT20 58 /* 20 bit GOT offset. */ #define R_390_GOTPLT20 59 /* 20 bit offset to jump slot. */ #define R_390_TLS_GOTIE20 60 /* 20 bit GOT offset for static TLS block offset. */ /* Keep this the last entry. */ #define R_390_NUM 61 /* CRIS relocations. */ #define R_CRIS_NONE 0 #define R_CRIS_8 1 #define R_CRIS_16 2 #define R_CRIS_32 3 #define R_CRIS_8_PCREL 4 #define R_CRIS_16_PCREL 5 #define R_CRIS_32_PCREL 6 #define R_CRIS_GNU_VTINHERIT 7 #define R_CRIS_GNU_VTENTRY 8 #define R_CRIS_COPY 9 #define R_CRIS_GLOB_DAT 10 #define R_CRIS_JUMP_SLOT 11 #define R_CRIS_RELATIVE 12 #define R_CRIS_16_GOT 13 #define R_CRIS_32_GOT 14 #define R_CRIS_16_GOTPLT 15 #define R_CRIS_32_GOTPLT 16 #define R_CRIS_32_GOTREL 17 #define R_CRIS_32_PLT_GOTREL 18 #define R_CRIS_32_PLT_PCREL 19 #define R_CRIS_NUM 20 /* AMD x86-64 relocations. */ #define R_X86_64_NONE 0 /* No reloc */ #define R_X86_64_64 1 /* Direct 64 bit */ #define R_X86_64_PC32 2 /* PC relative 32 bit signed */ #define R_X86_64_GOT32 3 /* 32 bit GOT entry */ #define R_X86_64_PLT32 4 /* 32 bit PLT address */ #define R_X86_64_COPY 5 /* Copy symbol at runtime */ #define R_X86_64_GLOB_DAT 6 /* Create GOT entry */ #define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */ #define R_X86_64_RELATIVE 8 /* Adjust by program base */ #define R_X86_64_GOTPCREL 9 /* 32 bit signed PC relative offset to GOT */ #define R_X86_64_32 10 /* Direct 32 bit zero extended */ #define R_X86_64_32S 11 /* Direct 32 bit sign extended */ #define R_X86_64_16 12 /* Direct 16 bit zero extended */ #define R_X86_64_PC16 13 /* 16 bit sign extended pc relative */ #define R_X86_64_8 14 /* Direct 8 bit sign extended */ #define R_X86_64_PC8 15 /* 8 bit sign extended pc relative */ #define R_X86_64_DTPMOD64 16 /* ID of module containing symbol */ #define R_X86_64_DTPOFF64 17 /* Offset in module's TLS block */ #define R_X86_64_TPOFF64 18 /* Offset in initial TLS block */ #define R_X86_64_TLSGD 19 /* 32 bit signed PC relative offset to two GOT entries for GD symbol */ #define R_X86_64_TLSLD 20 /* 32 bit signed PC relative offset to two GOT entries for LD symbol */ #define R_X86_64_DTPOFF32 21 /* Offset in TLS block */ #define R_X86_64_GOTTPOFF 22 /* 32 bit signed PC relative offset to GOT entry for IE symbol */ #define R_X86_64_TPOFF32 23 /* Offset in initial TLS block */ #define R_X86_64_PC64 24 /* PC relative 64 bit */ #define R_X86_64_GOTOFF64 25 /* 64 bit offset to GOT */ #define R_X86_64_GOTPC32 26 /* 32 bit signed pc relative offset to GOT */ /* 27 .. 33 */ #define R_X86_64_GOTPC32_TLSDESC 34 /* GOT offset for TLS descriptor. */ #define R_X86_64_TLSDESC_CALL 35 /* Marker for call through TLS descriptor. */ #define R_X86_64_TLSDESC 36 /* TLS descriptor. */ #define R_X86_64_IRELATIVE 37 /* Adjust indirectly by program base */ #define R_X86_64_NUM 38 /* AM33 relocations. */ #define R_MN10300_NONE 0 /* No reloc. */ #define R_MN10300_32 1 /* Direct 32 bit. */ #define R_MN10300_16 2 /* Direct 16 bit. */ #define R_MN10300_8 3 /* Direct 8 bit. */ #define R_MN10300_PCREL32 4 /* PC-relative 32-bit. */ #define R_MN10300_PCREL16 5 /* PC-relative 16-bit signed. */ #define R_MN10300_PCREL8 6 /* PC-relative 8-bit signed. */ #define R_MN10300_GNU_VTINHERIT 7 /* Ancient C++ vtable garbage... */ #define R_MN10300_GNU_VTENTRY 8 /* ... collection annotation. */ #define R_MN10300_24 9 /* Direct 24 bit. */ #define R_MN10300_GOTPC32 10 /* 32-bit PCrel offset to GOT. */ #define R_MN10300_GOTPC16 11 /* 16-bit PCrel offset to GOT. */ #define R_MN10300_GOTOFF32 12 /* 32-bit offset from GOT. */ #define R_MN10300_GOTOFF24 13 /* 24-bit offset from GOT. */ #define R_MN10300_GOTOFF16 14 /* 16-bit offset from GOT. */ #define R_MN10300_PLT32 15 /* 32-bit PCrel to PLT entry. */ #define R_MN10300_PLT16 16 /* 16-bit PCrel to PLT entry. */ #define R_MN10300_GOT32 17 /* 32-bit offset to GOT entry. */ #define R_MN10300_GOT24 18 /* 24-bit offset to GOT entry. */ #define R_MN10300_GOT16 19 /* 16-bit offset to GOT entry. */ #define R_MN10300_COPY 20 /* Copy symbol at runtime. */ #define R_MN10300_GLOB_DAT 21 /* Create GOT entry. */ #define R_MN10300_JMP_SLOT 22 /* Create PLT entry. */ #define R_MN10300_RELATIVE 23 /* Adjust by program base. */ #define R_MN10300_NUM 24 /* M32R relocs. */ #define R_M32R_NONE 0 /* No reloc. */ #define R_M32R_16 1 /* Direct 16 bit. */ #define R_M32R_32 2 /* Direct 32 bit. */ #define R_M32R_24 3 /* Direct 24 bit. */ #define R_M32R_10_PCREL 4 /* PC relative 10 bit shifted. */ #define R_M32R_18_PCREL 5 /* PC relative 18 bit shifted. */ #define R_M32R_26_PCREL 6 /* PC relative 26 bit shifted. */ #define R_M32R_HI16_ULO 7 /* High 16 bit with unsigned low. */ #define R_M32R_HI16_SLO 8 /* High 16 bit with signed low. */ #define R_M32R_LO16 9 /* Low 16 bit. */ #define R_M32R_SDA16 10 /* 16 bit offset in SDA. */ #define R_M32R_GNU_VTINHERIT 11 #define R_M32R_GNU_VTENTRY 12 /* M32R relocs use SHT_RELA. */ #define R_M32R_16_RELA 33 /* Direct 16 bit. */ #define R_M32R_32_RELA 34 /* Direct 32 bit. */ #define R_M32R_24_RELA 35 /* Direct 24 bit. */ #define R_M32R_10_PCREL_RELA 36 /* PC relative 10 bit shifted. */ #define R_M32R_18_PCREL_RELA 37 /* PC relative 18 bit shifted. */ #define R_M32R_26_PCREL_RELA 38 /* PC relative 26 bit shifted. */ #define R_M32R_HI16_ULO_RELA 39 /* High 16 bit with unsigned low */ #define R_M32R_HI16_SLO_RELA 40 /* High 16 bit with signed low */ #define R_M32R_LO16_RELA 41 /* Low 16 bit */ #define R_M32R_SDA16_RELA 42 /* 16 bit offset in SDA */ #define R_M32R_RELA_GNU_VTINHERIT 43 #define R_M32R_RELA_GNU_VTENTRY 44 #define R_M32R_REL32 45 /* PC relative 32 bit. */ #define R_M32R_GOT24 48 /* 24 bit GOT entry */ #define R_M32R_26_PLTREL 49 /* 26 bit PC relative to PLT shifted */ #define R_M32R_COPY 50 /* Copy symbol at runtime */ #define R_M32R_GLOB_DAT 51 /* Create GOT entry */ #define R_M32R_JMP_SLOT 52 /* Create PLT entry */ #define R_M32R_RELATIVE 53 /* Adjust by program base */ #define R_M32R_GOTOFF 54 /* 24 bit offset to GOT */ #define R_M32R_GOTPC24 55 /* 24 bit PC relative offset to GOT */ #define R_M32R_GOT16_HI_ULO 56 /* High 16 bit GOT entry with unsigned low */ #define R_M32R_GOT16_HI_SLO 57 /* High 16 bit GOT entry with signed low */ #define R_M32R_GOT16_LO 58 /* Low 16 bit GOT entry */ #define R_M32R_GOTPC_HI_ULO 59 /* High 16 bit PC relative offset to GOT with unsigned low */ #define R_M32R_GOTPC_HI_SLO 60 /* High 16 bit PC relative offset to GOT with signed low */ #define R_M32R_GOTPC_LO 61 /* Low 16 bit PC relative offset to GOT */ #define R_M32R_GOTOFF_HI_ULO 62 /* High 16 bit offset to GOT with unsigned low */ #define R_M32R_GOTOFF_HI_SLO 63 /* High 16 bit offset to GOT with signed low */ #define R_M32R_GOTOFF_LO 64 /* Low 16 bit offset to GOT */ #define R_M32R_NUM 256 /* Keep this the last entry. */ #endif /* elf.h */ mspdebug-0.25/formats/ihex.c000066400000000000000000000061021313531517500160250ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include "ihex.h" #include "output.h" int ihex_check(FILE *in) { rewind(in); return fgetc(in) == ':'; } static int feed_line(uint8_t *data, int nbytes, binfile_imgcb_t cb, void *user_data, address_t *segment_offset) { uint8_t cksum = 0; address_t address; uint8_t type; uint8_t *payload; int data_len; int i; struct binfile_chunk ch = {0}; if (nbytes < 5) return 0; /* Verify checksum */ for (i = 0; i + 1 < nbytes; i++) cksum += data[i]; cksum = ~(cksum - 1) & 0xff; if (data[nbytes - 1] != cksum) { printc_err("ihex: invalid checksum: %02x " "(calculated %02x)\n", data[nbytes - 1], cksum); return -1; } /* Extract other bits */ type = data[3]; address = (data[1] << 8) | data[2]; payload = data + 4; data_len = nbytes - 5; switch (type) { case 0: ch.addr = address + *segment_offset; ch.data = payload; ch.len = data_len; return cb(user_data, &ch); case 1: case 3: /* These can be safely ignored */ break; case 2: if (data_len != 2) { printc_err("ihex: invalid 02 record\n"); return -1; } *segment_offset = (address_t)((payload[0] << 8) | payload[1]) << 4; break; case 4: if (data_len != 2) { printc_err("ihex: invalid 04 record\n"); return -1; } *segment_offset = (address_t)((payload[0] << 8) | payload[1]) << 16; break; default: printc_err("warning: ihex: unknown record type: " "0x%02x\n", type); break; } return 0; } int ihex_extract(FILE *in, binfile_imgcb_t cb, void *user_data) { char buf[128]; int lno = 0; address_t segment_offset = 0; rewind(in); while (fgets(buf, sizeof(buf), in)) { int len = strlen(buf); int i; uint8_t data[64]; int nbytes; lno++; if (buf[0] != ':') { printc_err("ihex: line %d: invalid start " "marker\n", lno); continue; } /* Trim trailing whitespace */ while (len && isspace(buf[len - 1])) len--; buf[len] = 0; /* Decode hex digits */ nbytes = (len - 1) / 2; for (i = 0; i < nbytes; i++) { char d[] = {buf[i * 2 + 1], buf[i * 2 + 2], 0}; data[i] = strtoul(d, NULL, 16); } /* Handle the line */ if (feed_line(data, nbytes, cb, user_data, &segment_offset) < 0) { printc_err("ihex: error on line %d\n", lno); return -1; } } return 0; } mspdebug-0.25/formats/ihex.h000066400000000000000000000016771313531517500160460ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef IHEX_H_ #define IHEX_H_ #include "binfile.h" int ihex_check(FILE *in); int ihex_extract(FILE *in, binfile_imgcb_t cb, void *user_data); #endif mspdebug-0.25/formats/srec.c000066400000000000000000000056011313531517500160270ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include "srec.h" #include "util.h" #include "output.h" int srec_check(FILE *in) { char buf[128]; int i; rewind(in); if (!fgets(buf, sizeof(buf), in)) return 0; if (buf[0] != 'S') return 0; for (i = 1; buf[i] && !isspace(buf[i]); i++) if (!ishex(buf[i])) return 0; for (; buf[i]; i++) if (!isspace(buf[i])) return 0; return 1; } int srec_extract(FILE *in, binfile_imgcb_t cb, void *user_data) { char buf[128]; int lno = 0; rewind(in); while (fgets(buf, sizeof(buf), in)) { uint8_t bytes[128]; uint8_t cksum = 0; int count = 0; int i; lno++; if (buf[0] != 'S') { printc_err("srec: garbage on line %d\n", lno); return -1; } for (i = 2; ishex(buf[i]) && ishex(buf[i + 1]); i += 2) { if (count >= sizeof(bytes)) { printc_err("srec: too many bytes on " "line %d\n", lno); return -1; } bytes[count++] = (hexval(buf[i]) << 4) | hexval(buf[i + 1]); } while (buf[i]) { if (!isspace(buf[i])) { printc_err("srec: trailing garbage on " "line %d\n", lno); return -1; } i++; } if (count < 2) { printc_err("srec: too few bytes on line %d\n", lno); return -1; } if (bytes[0] + 1 != count) { printc_err("srec: byte count mismatch on " "line %d\n", lno); return -1; } for (i = 0; i + 1 < count; i++) cksum += bytes[i]; cksum = ~cksum; if (cksum != bytes[count - 1]) { printc_err("srec: checksum error on line %d " "(calc = 0x%02x, read = 0x%02x)\n", lno, cksum, bytes[count - 1]); return -1; } if (buf[1] >= '1' && buf[1] <= '3') { int addrbytes = buf[1] - '1' + 2; address_t addr = 0; struct binfile_chunk ch = {0}; for (i = 0; i < addrbytes; i++) addr = (addr << 8) | bytes[i + 1]; if (count < addrbytes + 2) { printc_err("srec: too few address bytes " "on line %d\n", lno); return -1; } ch.addr = addr; ch.data = bytes + addrbytes + 1; ch.len = count - 2 - addrbytes; if (cb(user_data, &ch) < 0) { printc_err("srec: error on line %d\n", lno); return -1; } } } return 0; } mspdebug-0.25/formats/srec.h000066400000000000000000000016771313531517500160450ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef SREC_H_ #define SREC_H_ #include "binfile.h" int srec_check(FILE *in); int srec_extract(FILE *in, binfile_imgcb_t cb, void *user_data); #endif mspdebug-0.25/formats/symmap.c000066400000000000000000000030501313531517500163750ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include "symmap.h" int symmap_check(FILE *in) { char buf[128]; int i; int spc_count = 0; rewind(in); if (!fgets(buf, sizeof(buf), in)) return 0; for (i = 0; buf[i]; i++) { if (buf[i] == '\r' || buf[i] == '\n') break; if (buf[i] < 32 || buf[i] > 126) return 0; if (isspace(buf[i])) spc_count++; } return spc_count >= 2; } int symmap_syms(FILE *in) { rewind(in); char buf[128]; while (fgets(buf, sizeof(buf), in)) { char *addr = strtok(buf, " \t\r\n"); char *name; strtok(NULL, " \t\r\n"); name = strtok(NULL, " \t\r\n"); if (addr && name) { address_t addr_val = strtoul(addr, NULL, 16); if (stab_set(name, addr_val) < 0) return -1; } } return 0; } mspdebug-0.25/formats/symmap.h000066400000000000000000000016371313531517500164130ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef SYMMAP_H_ #define SYMMAP_H_ #include "binfile.h" int symmap_check(FILE *in); int symmap_syms(FILE *in); #endif mspdebug-0.25/formats/titext.c000066400000000000000000000060231313531517500164130ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include "titext.h" #include "util.h" #include "output.h" static int is_address_line(const char *text) { if (*text != '@') return 0; text++; if (!*text || isspace(*text)) return 0; while (*text && !isspace(*text)) { if (!ishex(*text)) return 0; text++; } while (*text) { if (!isspace(*text)) return 0; text++; } return 1; } static int is_data_line(const char *text) { while (*text) { if (!(ishex(*text) || isspace(*text))) return 0; text++; } return 1; } int titext_check(FILE *in) { char buf[64]; rewind(in); if (!fgets(buf, sizeof(buf), in)) return 0; return is_address_line(buf); } static int process_data_line(address_t address, const char *buf, binfile_imgcb_t cb, void *user_data) { uint8_t data[64]; int data_len = 0; int value = 0; int vc = 0; struct binfile_chunk ch = {0}; while (*buf) { int c = *(buf++); int x; if (isspace(c)) { if (vc) { if (data_len >= sizeof(data)) goto too_long; data[data_len++] = value; } vc = 0; } else { if (isdigit(c)) { x = c - '0'; } else if (c >= 'A' && c <= 'F') { x = c - 'A' + 10; } else if (c >= 'a' && c <= 'f') { x = c - 'a' + 10; } else { printc_err("titext: unexpected " "character: %c\n", c); return -1; } if (vc >= 2) { printc_err("titext: too many digits " "in hex value\n"); return -1; } value = (value << 4) | x; vc++; } } if (vc) { if (data_len >= sizeof(data)) goto too_long; data[data_len++] = value; } ch.addr = address; ch.data = data; ch.len = data_len; if (cb(user_data, &ch) < 0) return -1; return data_len; too_long: printc_err("titext: too many data bytes\n"); return -1; } int titext_extract(FILE *in, binfile_imgcb_t cb, void *user_data) { address_t address = 0; int lno = 0; char buf[128]; rewind(in); while (fgets(buf, sizeof(buf), in)) { lno++; if (is_address_line(buf)) { address = strtoul(buf + 1, NULL, 16); } else if (is_data_line(buf)) { int count = process_data_line(address, buf, cb, user_data); if (count < 0) { printc_err("titext: data error on line " "%d\n", lno); return -1; } address += count; } } return 0; } mspdebug-0.25/formats/titext.h000066400000000000000000000017111313531517500164170ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef TITEXT_H_ #define TITEXT_H_ #include "binfile.h" int titext_check(FILE *in); int titext_extract(FILE *in, binfile_imgcb_t cb, void *user_data); #endif mspdebug-0.25/mspdebug.man000066400000000000000000001131331313531517500155570ustar00rootroot00000000000000.TH mspdebug 1 "24 Jul 2017" "Version 0.25" .SH NAME MSPDebug - debugging tool for MSP430 MCUs .SH SYNOPSIS \fBmspdebug\fR [options] \fIdriver\fR [\fIcommand\fR ...] .SH DESCRIPTION MSPDebug is a command-line tool designed for debugging and programming the MSP430 family of MCUs. It supports the eZ430-F2013, eZ430-RF2500, Launchpad, Chronos, FET430UIF, GoodFET, Olimex MSP430-JTAG-TINY and MSP430-JTAG-ISO programming tools, as well as a simulation mode. When started with appropriate options, MSPDebug will attempt to connect to the debugging tool specified and identify the device under test. Once connected, the user is presented with a command prompt which can be used to reflash the device memory, inspect memory and registers, set registers, and control the CPU (single step, run and run to breakpoint). It supports a variety of file formats, described in the section \fBBINARY FORMATS\fR below. It can also be used as a remote stub for \fBgdb\fR(1). On startup, MSPDebug will look for a file called .mspdebug first in the current directory, and then in the user's home directory. If either file exists, commands will be read and executed from this file before executing any other commands or starting the interactive reader. Alternatively, a configuration file can be explicitly specified with the \fB-C\fR option. .SH COMMAND-LINE OPTIONS Command-line options accepted by MSPDebug are described below. If commands are specified on the end of the command-line, then they are executed after connecting to the device, and the interactive prompt is not started. Please be aware that commands consisting of multiple words need to be enclosed in quotation marks, otherwise they are treated as single commands. Thus the common prog command would be used as "prog main.elf". See the section labelled \fBCOMMANDS\fR for more information. .IP "\-q" Start in quiet mode. See the "quiet" option described below. .IP "\-v \fIvoltage\fR" Set the programming voltage. The voltage should be specified as an integer in millivolts. It defaults to 3000 (3.0 V). .IP "\-j" Use JTAG instead of Spy-Bi-Wire to communicate with the MSP430. This option doesn't work with eZ430 or eZ430-RF2500 devices, which support Spy-Bi-Wire only. .IP "\-d \fIdevice\fR" Specify that the driver should connect via a tty device rather than USB. The supported connection methods vary depending on the driver. See the section \fBDRIVERS\fR below for details. .IP "\-U \fIbus\fR:\fIdevice\fR" Specify a particular USB device to connect to. Without this option, the first device of the appropriate type is opened. .IP "\-s \fIserial\fR" Specify a particular USB device serial number to connect to. Use this option to distinguish between multiple devices of the same type. .IP "\-n" Do not process the startup file (~/.mspdebug). .IP "\-C \fIfile\fR" Specify an alternative configuration file (default is ~/.mspdebug). If -n is specified as well, no file will be read. .IP "\--long-password" When using the flash-bsl driver, send a 32-byte BSL password instead of the standard 16-byte password. .IP "\-\-help" Display a brief help message and exit. .IP "\-\-fet\-list" Display a list of chips supported by the FET driver (the driver used for UIF, RF2500 and Olimex devices). .IP "\-\-fet\-force\-id \fIstring\fR" When using a FET device, force the connected chip to be recognised by MSPDebug as one of the given type during initialization. This overrides the device ID returned by the FET. The given string should be a chip name in long form, for example "MSP430F2274". .IP "\-\-fet\-skip\-close" When using a FET device, skip the JTAG close procedure when disconnecting. With some boards, this removes the need to replug the debugger after use. .IP "\-\-usb\-list" List available USB devices and exit. .IP "\-\-force-reset" When using a FET device, always send a reset during initialization. By default, an initialization without reset will be tried first. .IP "\-\-allow-fw-update" When using a V3 FET device via the TI library, allow the library to perform a firmware update if the FET firmware is incompatible with the library. .IP "\-\-require-fw-update \fIimage.txt\fR" When using a V3 FET device, or certain Olimex devices, force a firmware update using the given firmware image. The firmware format depends on the driver. .IP "\-\-version" Show program version and copyright information. .IP "\-\-embedded" Start mspdebug as an embedded subprocess. See the documentation accompanying the source release for more information on embedded mode. .IP "\-\-bsl\-entry\-sequence \fIseq\fR" Specify a BSL entry sequence. Each character specifies a modem control line transition (R: RTS on, r: RTS off, D: DTR on, d: DTR off). A comma indicates a delay. The entry and exit sequences are separated by a colon. The default value is \fBdR,r,R,r,R,D:dR,DR\fR, for the \fBflash-bsl\fR driver. .SH DRIVERS For drivers supporting both USB and tty access, USB is the default, unless specified otherwise (see \fB-d\fR above). On Linux, if USB access is used, the kernel driver (if any) is detached from the tty device. If further access to the tty device is needed, unloading and re-loading of the driver (e.g. cdc-acm.ko) is required. A driver name must be specified on the command line for MSPDebug to connect to. Valid driver names are listed here. .IP "\fBrf2500\fR" Connect to an eZ430-RF2500, Launchpad or Chronos device. Only USB connection is supported. .IP "\fBolimex\fR" Connect to an Olimex MSP430-JTAG-TINY device. Both USB and tty access are supported. .IP "\fBolimex-v1\fR" Connect to an Olimex MSP430-JTAG-TINY (V1) device. Both USB and tty access are supported. This driver must be used instead of \fBolimex\fR if connecting to a V1 device via a tty interface. .IP "\fBolimex-iso\fR" Connect to an Olimex MSP430-JTAG-ISO device. Both USB and tty access are supported. .IP "\fBolimex-iso-mk2\fR" Connect to an Olimex MSP430-JTAG-ISO-MK2 device. Both USB and tty access are supported. .IP "\fBsim\fR" Do not connect to any hardware device, but instead start in simulation mode. A 64k buffer is allocated to simulate the device memory. During simulation, addresses below 0x0200 are assumed to be IO memory. Programmed IO writes to and from IO memory are handled by the IO simulator, which can be configured and controlled with the \fBsimio\fR command, described below. This mode is intended for testing of changes to MSPDebug, and for aiding the disassembly of MSP430 binaries (as all binary and symbol table formats are still usable in this mode). .IP "\fBuif\fR" Connect to an eZ430-F2013 or a FET430UIF device. The device argument should be the filename of the appropriate tty device. The TI serial converter chips on these devices are supported by newer versions of the Linux kernel, and should appear as /dev/tty\fIXX\fR when attached. USB connection is supported for this driver. The USB interface chip in these devices is a TI3410, which requires a firmware download on startup. MSPDebug will search for a file called ti_3410.fw.ihex in the configured library directory and the current directory. You can specify an alternate location for the file via the \fBMSPDEBUG_TI3410_FW\fR environment variable. .IP "\fBuif-bsl\fR" Connect to the bootloader on a FET430UIF device. These devices contain MSP430F1612 chips. By sending a special command sequence, you can obtain access to the bootloader and inspect memory on the MSP430F1612 in the programming device itself. Currently, only memory read/write and erase are supported. CPU control via the bootloader is not possible. .IP "\fBflash-bsl\fR" Connect to the built-in bootloader in MSP430 devices with flash bootloader memory. Devices with ROM bootloaders require another driver. Currently, this driver must mass-erase the device in order to gain access. Read, write, and erase operations are supported. USB connection is not supported for this driver. Connection is via serial port, and bootloader entry is accomplished via the RTS and DTR lines. Connect RTS to the device's TEST pin and DTR to the device's RST pin. Use an appropriate serial level-shifter to make the connection, if necessary. If connecting to a device with non-multiplexed JTAG pins, connect RTS to the device's TCK pin via an inverter. .IP "\fBgdbc\fR" GDB client mode. Connect to a server which implements the GDB remote protocol and provide an interface to it. To use this driver, specify the remote address in \fIhostname:port\fR format using the \fB-d\fR option. .IP "\fBtilib\fR" Use the Texas Instruments MSP430.DLL to access the device. The library file (MSP430.DLL for Windows, libmsp430.so for Unix-like systems) must be present in the dynamic loader search path. USB connection is not supported for this driver. This driver supports watchpoints. Note that the \fB-d\fR option for this driver passes its argument straight through to the library's \fBMSP430_Initialize\fR function. Any special argument supported by that function is therefore accessible via the \fB-d\fR option. Automatic device discovery works only on Linux and Windows. On other systems, the appropriate ACM serial node must be explicitly specified. .IP "\fBgoodfet\fR" Connect to a GoodFET device. JTAG mode must be used, and only tty access is supported. This device can be used for memory access (read, erase and program), but CPU control is limited. The CPU may be halted, run and reset, but register access and breakpoints aren't supported. .IP "\fBpif\fR" Connect to a parallel-port JTAG controller. JTAG mode must be used, and only tty access is supported. Currently, this driver is only supported on Linux, FreeBSD and DragonFly BSD. A parallel port device (ppdev on Linux, ppi on FreeBSD and DragonFly BSD) must be specified via the \fB-d\fR option. .IP "\fBgpio\fR" Connect to system gpios. JTAG mode must be used, and only tty access is supported. Currently, this driver is only supported on Linux, FreeBSD and DragonFly BSD. The gpios to used must defined using a string like "tdi=7 tdo=8 tms=9 tck=4 rst=10 tst=11" via the \fB-d\fR option. (dont forget the quotes) .IP "\fBload-bsl\fR" Connect to a USB bootloader. The stub bootloader will be used to load a fuller-featured bootloader into RAM for execution. .IP "\fBezfet\fR" This driver is for Texas Instruments' eZ-FET devices. It supports USB and tty access. It does not support breakpoint control. .IP "\fBrom-bsl\fR" This driver is for the old-style (ROM) bootstrap loader. It supports tty access only. Entry is attempted via the RTS/DTR signals. The default sequence is \fBDR,r,R,r,d,R:DR,r\fR, but you can override this with the \fB\-\-bsl\-entry\-sequence\fR option. \fBWARNING:\fR this driver unlocks the BSL by performing a mass erase. There are reports of this operation causing an erase of info A in some devices. Use at your own risk. .IP "\fBbus-pirate\fR" Raw JTAG using Bus Pirate devices. .SH COMMANDS MSPDebug can accept commands either through an interactive prompt, or non-interactively when specified on the command line. The supported commands are listed below. Commands take arguments separated by spaces. Any text string enclosed in double-quotation marks is considered to be a single argument, even if it contains space characters. Within a quoted string, the usual C-style backslash substitutions can be used. Commands can be specified by giving the first few characters of the command name, provided that the prefix is unambiguous. Some commands support automatic repeat. For these commands, pressing enter at the reader prompt without typing anything will cause repeat execution. .IP "\fB!\fR [\fIcommand\fR [\fIargs ...\fR]]" Invoke an interactive operating system shell. If any arguments are specified, the first one is taken as a command to execute, with the rest of the arguments as the arguments to the command. This command is not yet available on non-POSIX systems. .IP "\fB=\fR \fIexpression\fR" Evaluate an address expression and show both its value, and the result when the value is looked up in reverse in the current symbol table. This result is of the form \fIsymbol\fR+\fIoffset\fR, where \fIsymbol\fR is the name of the nearest symbol not past the address in question. See the section marked \fBADDRESS EXPRESSIONS\fR for more information on the syntax of expressions. .IP "\fBalias\fR" Show a list of defined command aliases. .IP "\fBalias\fR \fIname\fR" Remove a previously defined command alias. .IP "\fBalias\fR \fIname\fR \fIcommand\fR" Define a command alias. The text \fIcommand\fR will be substituted for \fIname\fR when looking up commands. The given command text may contain a command plus arguments, if the entire text is wrapped in quotes when defining the alias. To avoid alias substitution when interpreting commands, prefix the command with \\ (a backslash character). .IP "\fBblow_jtag_fuse\fR" Blow the device's JTAG fuse. .B WARNING: this is an irreversible operation! .IP "\fBbreak\fR" Show a list of active breakpoints. Breakpoints can be added and removed with the \fBsetbreak\fR and \fBdelbreak\fR commands. Each breakpoint is numbered with an integer index starting at 0. .IP "\fBcgraph\fR \fIaddress\fR \fIlength\fR [\fIaddress\fR]" Construct the call graph of all functions contained or referenced in the given range of memory. If a particular function is specified, then details for that node of the graph are displayed. Otherwise, a summary of all nodes is displayed. Information from the symbol table is used for hinting at the possible locations of function starts. Any symbol which does not contain a "." is considered a possible function start. Callers and callee names are shown prefixed by a "*" where the transition is a tail-call type transition. .IP "\fBdelbreak\fR [\fIindex\fR]" Delete one or all breakpoints. If an index is given, the selected breakpoint is deleted. Otherwise, all breakpoints are cleared. .IP "\fBdis\fR \fIaddress\fR [\fIlength\fR]" Dissassemble a section of memory. Both arguments may be address expressions. If no length is specified, a section of the default length (64 bytes) is disassembled and shown. If symbols are available, then all addresses used as operands are translated into \fIsymbol\fR+\fIoffset\fR form. This command supports repeat execution. If repeated, it continues to disassemble another block of memory following that last printed. .IP "\fBerase\fR [\fBall\fR|\fBsegment\fR|\fBsegrange\fR] [\fIaddress\fR] [\fIsize\fR] [\fIsegrange\fR]" Erase the device under test. With no arguments, all code memory is erased (but not information or boot memory). With the argument "all", a mass erase is performed (the results may depend on the state of the LOCKA bit in the flash memory controller). Specify "segment" and a memory address to erase an individual flash segment. Specify "segrange", an address, size and segment size to erase an arbitrary set of contiguous segments. .IP "\fBexit\fR" Exit from MSPDebug. .IP "\fBfill\fR \fIaddress\fR \fIlength\fR \fIb0\fR [\fIb1\fR \fIb2\fR ...] Fill the memory region of size \fIlength\fR starting at \fIaddress\fR with the pattern of bytes given (specified in hexadecimal). The pattern will be repeated without padding as many times as necessary without exceeding the bounds of the specified region. .IP "\fBgdb\fR [\fIport\fR]" Start a GDB remote stub, optionally specifying a TCP port to listen on. If no port is given, the default port is controlled by the option \fBgdb_default_port\fR. MSPDebug will wait for a connection on this port, and then act as a GDB remote stub until GDB disconnects. GDB's "monitor" command can be used to issue MSPDebug commands via the GDB interface. Supplied commands are executed non-interactively, and the output is sent back to be displayed in GDB. .IP "\fBhelp\fR [\fIcommand\fR]" Show a brief listing of available commands. If an argument is specified, show the syntax for the given command. The help text shown when no argument is given is also shown when MSPDebug starts up. .IP "\fBhexout\fR \fIaddress\fR \fIlength\fR \fIfilename\fR" Read the specified section of the device memory and save it to an Intel HEX file. The address and length arguments may both be address expressions. If the specified file already exists, then it will be overwritten. If you need to dump memory from several disjoint memory regions, you can do this by saving each section to a separate file. The resulting files can then be concatenated together to form a single valid HEX file. .IP "\fBisearch\fR \fIaddress\fR \fIlength\fR [\fIoptions\fR ...]" Search over the given range for an instruction which matches the specified search criteria. The search may be narrowed by specifying one or more of the following terms: .RS .IP "\fBopcode\fR \fIopcode\fR" Match the specified opcode. Byte/word specifiers are not recognised, as they are specified with other options. .IP "\fBbyte\fR" Match only byte operations. .IP "\fBword\fR" Match only word operations. .IP "\fBaword\fR" Match only address-word (20-bit) operations. .IP "\fBjump\fR" Match only jump instructions (conditional and unconditional jumps, but not instructions such as BR which load the program counter explicitly). .IP "\fBsingle\fR" Match only single-operand instructions. .IP "\fBdouble\fR" Match only double-operand instructions. .IP "\fBnoarg\fR" Match only instructions with no arguments. .IP "\fBsrc\fR \fIaddress\fR" Match instructions with the specified value in the source operand. The value may be given as an address expression. Specifying this option implies matching of only double-operand instructions. .IP "\fBdst\fR \fIaddress\fR" Match instructions with the specified value in the destination operand. This option implies that no-argument instructions are not matched. .IP "\fBsrcreg\fR \fIregister\fR" Match instructions using the specified register in the source operand. This option implies matching of only double-operand instructions. .IP "\fBdstreg\fR \fIregister\fR" Match instructions using the specified register in the destination operand. This option implies that no-argument instructions are not matched. .IP "\fBsrcmode\fR \fImode\fR" Match instructions using the specified mode in the source operand. See below for a list of modes recognised. This option implies matching of only double-operand instructions. .IP "\fBdstmode\fR \fImode\fR" Match instructions using the specified mode in the destination operand. See below for a list of modes. This option implies that no-argument instructions are not matched. .RE .IP For single-operand instructions, the operand is considered to be the destination operand. The seven addressing modes used by the MSP430 are represented by single characters, and are listed here: .RS .IP "\fBR\fR" Register mode. .IP "\fBI\fR" Indexed mode. .IP "\fBS\fR" Symbolic mode. .IP "\fB&\fR" Absolute mode. .IP "\fB@\fR" Register-indirect mode. .IP "\fB+\fR" Register-indirect mode with auto-increment. .IP "\fB#\fR" Immediate mode. .RE .IP "\fBload\fR \fIfilename\fR" Program the device under test using the binary file supplied. This command is like \fBprog\fR, but it does not load symbols or erase the device before programming. The CPU is reset and halted before and after programming. .IP "\fBload_raw\fR \fIfilename\fR \fIaddress\fR" Write the data contained in a raw binary file to the given memory address. The CPU is reset and halted before and after programming. .IP "\fBmd\fR \fIaddress\fR [\fIlength\fR]" Read the specified section of device memory and display it as a canonical\-style hexdump. Both arguments may be address expressions. If no length is specified, a section of the default length (64 bytes) is shown. The output is split into three columns. The first column shows the starting address for the line. The second column lists the hexadecimal values of the bytes. The final column shows the ASCII characters corresponding to printable bytes, and . for non-printing characters. This command supports repeat execution. If repeated, it continues to print another block of memory following that last printed. .IP "\fBmw\fR \fIaddress\fR \fIbytes\fR ..." Write a sequence of bytes at the given memory address. The address given may be an address expression. Bytes values are two-digit hexadecimal numbers separated by spaces. .IP "\fBopt\fR [\fIname\fR] [\fIvalue\fR]" Query, set or list option variables. MSPDebug's behaviour can be configured using option variables, described below in the section \fBOPTIONS\fR. Option variables may be of three types: boolean, numeric or text. Numeric values may be specified as address expressions. With no arguments, this command displays all available option variables. With just an option name as its argument, it displays the current value of that option. .IP "\fBpower info\fR" Show basic power statistics gathered over the last few sessions. This includes total charge consumption, run time and average current. .IP "\fBpower clear\fR" Clear all recorded power statistics. .IP "\fBpower all\fR [\fIgranularity\fR]" Show sample data gathered over all sessions. An optional granularity can be specified, in microseconds. For each time slice, relative session time, charge consumption, current consumption and approximate code location are shown. .IP "\fBpower session\fR \fIN\fR [\fIgranularity\fR]" Same as \fBpower all\fR, except that data is shown only for the \fIN\fRth session. .IP "\fBpower export-csv\fR \fIN\fR \fIfilename\fR" Export raw sample data for the \fIN\fRth session to the given file in CSV format. For each line, the columns are, in order: relative time in microseconds, current consumption in microamps, memory address. .IP "\fBpower profile\fR" If a symbol table is loaded, compile and correlate all gathered power data against the symbol table. A single table is then shown listing, per function, charge consumption, run time and average current. The functions are listed in order of charge consumption (biggest consumers first). .IP "\fBprog\fR \fIfilename\fR" Erase and reprogram the device under test using the binary file supplied. The file format will be auto-detected and may be any of the supported file formats. In the case of a file containing symbols, symbols will be automatically loaded from the file into the symbol table (discarding any existing symbols), if they are present. The CPU is reset and halted before and after programming. .IP "\fBread\fR \fIfilename\fR" Read commands from the given file, line by line and process each one. Any lines whose first non-space character is \fB#\fR are ignored. If an error occurs while processing a command, the rest of the file is not processed. .IP "\fBregs\fR" Show the current value of all CPU registers in the device under test. .IP "\fBreset\fR" Reset (and halt) the CPU of the device under test. .IP "\fBrun\fR" Start running the CPU. The interactive command prompt is blocked when the CPU is started and the prompt will not appear again until the CPU halts. The CPU will halt if it encounters a breakpoint, or if Ctrl\-C is pressed by the user. After the CPU halts, the current register values are shown as well as a disassembly of the first few instructions at the address selected by the program counter. .IP "\fBsave_raw\fR \fIaddress\fR \fIlength\fR \fIfilename\fR" Save a region of memory to a raw binary file. The address and length arguments may both be address expressions. If the specified file already exists, then it will be overwritten. .IP "\fBset\fR \fIregister\fR \fIvalue\fR" Alter the value of a register. Registers are specified as numbers from 0 through 15. Any leading non-numeric characters are ignored (so a register may be specified as, for example, "R12"). The value argument is an address expression. .IP "\fBsetbreak\fR \fIaddress\fR [\fIindex\fR]" Add a new breakpoint. The breakpoint location is an address expression. An optional index may be specified, indicating that this new breakpoint should overwrite an existing slot. If no index is specified, then the breakpoint will be stored in the next unused slot. .IP "\fBsetwatch\fR \fIaddress\fR [\fIindex\fR]" Add a new watchpoint. The watchpoint location is an address expression, and an optional index may be specified. Watchpoints are considered to be a type of breakpoint and can be inspected or removed using the \fBbreak\fR and \fBdelbreak\fR commands. Note that not all drivers support watchpoints. .IP "\fBsetwatch_r\fR \fIaddress\fR [\fIindex\fR]" Add a watchpoint which is triggered only on read access. .IP "\fBsetwatch_w\fR \fIaddress\fR [\fIindex\fR]" Add a watchpoint which is triggered only on write access. .IP "\fBsimio add\fR \fIclass\fR \fIname\fR [\fIargs ...\fR]" Add a new peripheral to the IO simulator. The \fIclass\fR parameter may be any of the peripheral types named in the output of the \fBsimio classes\fR command. The \fIname\fR parameter is a unique name assigned by the user to this peripheral instance, and is used with other commands to refer to this instance of the peripheral. Some peripheral classes take arguments upon creation. These are documented in the output to the \fBsimio help\fR command. .IP "\fBsimio classes\fR" List the names of the different types of peripherals which may be added to the simulator. You can use the \fBsimio help\fR command to obtain more information about each peripheral type. .IP "\fBsimio config\fR \fIname\fR \fIparam\fR [\fIargs ...\fR]" Configure or perform some action on a peripheral instance. The \fIparam\fR argument is specific to the peripheral type. A list of valid configuration commands can be obtained by using the \fBsimio help\fR command. .IP "\fBsimio del\fR \fIname\fR" Remove a previously added peripheral instance. The \fIname\fR argument should be the name of the peripheral that was assigned with the \fBsimio add\fR command. .IP "\fBsimio devices\fR" List all peripheral instances currently attached to the simulator, along with their types and interrupt status. You can obtain more detailed information for each instance with the \fBsimio info\fR command. .IP "\fBsimio help\fR \fIclass\fR" Obtain more information about a peripheral class. The documentation given will list constructor arguments and configuration parameters for the device type. .IP "\fBsimio info\fR \fIname\fR" Display detailed status information for a particular peripheral. The type of information displayed is specific to each type of peripheral. .IP "\fBstep\fR [\fIcount\fR]" Step the CPU through one or more instructions. After stepping, the new register values are displayed, as well as a disassembly of the instructions at the address selected by the program counter. An optional count can be specified to step multiple times. If no argument is given, the CPU steps once. This command supports repeat execution. .IP "\fBsym clear\fR" Clear the symbol table, deleting all symbols. .IP "\fBsym set\fR \fIname\fR \fIvalue\fR" Set or alter the value of a symbol. The value given may be an address expression. .IP "\fBsym del\fR \fIname\fR" Delete the given symbol from the symbol table. .IP "\fBsym import\fR \fIfilename\fR" Load symbols from the specified file and add them to the symbol table. The file format will be auto-detected and may be either ELF32 or a BSD-style symbol listing (like the output from \fBnm\fR(1)). Symbols can be combined from many sources, as the syms command adds to the existing symbol table without discarding existing symbols. .IP "\fBsym import+\fR \fIfilename\fR" This command is similar to \fBsym import\fR, except that the symbol table is not cleared first. By using this command, symbols from multiple sources can be combined. .IP "\fBsym export\fR \fIfilename\fR" Save all symbols currently defined to the given file. The symbols are saved as a BSD-style symbol table. Note that symbol types are not stored by MSPDebug, and all symbols are saved as type \fBt\fR. .IP "\fBsym find\fR [\fIregex\fR]" Search for symbols. If a regular expression is given, then all symbols matching the expression are printed. If no expression is specified, then the entire symbol table is listed. .IP "\fBsym rename\fR \fIregex\fR \fIstring\fR" Rename symbols by searching for those matching the given regular expression and substituting the given string for the matched portion. The symbols renamed are displayed, as well as a total count of all symbols renamed. .IP "\fBverify \fIfilename\fR" Compare the contents of the given binary file to the chip memory. If any differences are found, a message is printed for the first mismatched byte. .IP "\fBverify_raw \fIfilename\fR \fIaddress\fR" Compare the contents of a raw binary file to the device memory at the given address. If any differences are found, a message is printed for the first mismatched byte. .SH BINARY FORMATS The following binary/symbol formats are supported by MSPDebug: .RS ELF32 .br COFF .br Intel HEX (program only) .br BSD symbol table (symbols only) .br TI Text (program only) .br SREC (program only) .RE .SH IO SIMULATOR The IO simulator subsystem consists of a database of device classes, and a list of instances of those classes. Each device class has a different set of constructor arguments, configuration parameters and information which may be displayed. This section describes the operation of the available device classes in detail. In the list below, each device class is listed, followed by its constructor arguments. .IP "\fBgpio\fR" Digital IO port simulator. This device simulates any of the digital ports with or without interrupt capability. It has the following configuration parameters: .RS .IP "\fBbase\fR \fIaddress\fR" Set the base address for this port. Note that for ports without interrupt capability, the resistor enable port has a special address which is computable from the base address. .IP "\fBirq\fR \fIvector\fR" Enable interrupt functionality for this port by specifying an interrupt vector number. .IP "\fBnoirq\fR" Disable interrupt functionality for this port. .IP "\fBverbose\fR" Print a state change message every time the port output changes. .IP "\fBquiet\fR" Don't print anything when the port state changes (the default). .IP "\fBset\fR \fIpin\fR \fIvalue\fR" Set the input pin state for the given pin on this port. The \fIpin\fR parameter should be an index between 0 and 7. The \fIvalue\fR should be either zero (for a low state) or non-zero (for a high state). .RE .IP "\fBhwmult\fR" This peripheral simulates the hardware multiplier. It has no constructor or configuration parameters, and does not provide any extended information. .IP "\fBtimer\fR [\fIsize\fR]" This peripheral simulators Timer_A modules, and can be used to simulate Timer_B modules, provided that the extended features aren't required. The constructor takes a size argument specifying the number of capture/compare registers in this peripheral instance. The number of such registers may not be less than 2, or greater than 7. The IO addresses and IRQs used are configurable. The default IO addresses used are those specified for Timer_A in the MSP430 hardware documentation. .RS .IP "\fBbase\fR \fIaddress\fR" Alter the base IO address. By default, this is 0x0160. By setting this to 0x0180, a Timer_B module may be simulated. .IP "\fBirq0\fR \fInumber\fR" Set the TACCR0 interrupt vector number. By default, this is interrupt vector 9. This interrupt is self-clearing, and higher priority than the TACCR1/TAIFG vector. .IP "\fBirq1\fR \fInumber\fR" Set the TACCR1/TAIFG interrupt vector. By default, this is interrupt vector 8. .IP "\fBiv\fR \fIaddress\fR" Alter the address of the interrupt vector register. By default, this is 0x012E. By setting this to 0x011E, a Timer_B module may be simulated. .IP "\fBset\fR \fIchannel\fR \fIvalue\fR" When Timer_A is used in capture mode, the CCI bit in each capture register reflects the state of the corresponding input pin, and can't be altered in software. This configuration command can be used to simulate changes in input pin state, and will trigger the corresponding interrupts if the peripheral is so configured. .RE .IP "\fBtracer\fR [\fIhistory-size\fR]" The tracer peripheral is a debugging device. It can be used to investigate and record the IO activity of a running program, to benchmark execution time, and to simulate interrupts. The information displayed by the tracer gives a running count of clock cycles from each of the system clocks, and an instruction count. A list of the \fIN\fR most recent IO events is also displayed (this is configurable via the \fIhistory-size\fR argument of the constructor). Each IO event is timestamped by the number of MCLK cycles that have elapsed since the last reset of the device's counter. The IO events that it records consist of programmed IO reads and writes, interrupt acceptance, and system resets. As well as keeping the IO events in a rotating buffer, the tracer can be configured to display the events as they occur. Note that since clock cycles don't advance while the CPU isn't running, this peripheral can be used to calculate execution times for blocks of code. This can be achieved by setting a breakpoint at the end of the code block, setting the program counter to the start of the code block, clearing the tracer and running the code. After the breakpoint is reached, the information displayed by the tracer will contain a count of MCLK cycles elapsed during the last run. The configuration parameters for this device class are: .RS .IP "\fBverbose\fR" Start displaying IO events as they occur, as well as recording them in the rotating buffer. .IP "\fBquiet\fR" Stop displaying IO events as they occur, and just record them in the buffer. .IP "\fBtrigger\fR \fIirq\fR" Signal an interrupt request to the CPU. This request will remain raised until accepted by the CPU or cleared by the user. .IP "\fBuntrigger\fR" Clear a signalled interrupt request. .IP "\fBclear\fR" Reset the clock cycle and instruction counts to 0, and clear the IO event history. .RE .IP "\fBwdt\fR" This peripheral simulates the Watchdog Timer+, which can be used in software either as a watchdog or as an interval timer. It has no constructor arguments. The simulated state of the NMI/RST# pin can be controlled through a configuration parameter. Note that if this pin state is held low with the pin mode selected as a reset (the default), the CPU will not run. The extended information for this peripheral shows all register states, including the hidden counter register. Configuration parameters are: .RS .IP "\fBnmi\fR \fIstate\fR" Set the NMI/RST# pin state. The argument should be zero to indicate a low state or non-zero for a high state. .IP "\fBirq\fR \fIirq\fR" Select the interrupt vector for interval timer mode. The default is to use interrupt vector 10. .SH ADDRESS EXPRESSIONS Any command which accepts a memory address, length or register value as an argument may be given an address expression. An address expression consists of an algebraic combination of values. An address value can be one of the following: .RS A symbol name .br A CPU register name preceded with "@" .br A hex value preceded with the specifier "0x" .br A decimal value preceded with the specifier "0d" .br A number in the default input radix (without a specifier). See the option \fBiradix\fR for more information. .RE The operators recognised are the usual algebraic operators: \fB+\fR, \fB-\fR, \fB*\fR, \fB/\fR, \fB%\fR, \fB(\fR and \fB)\fR. Operator precedence is the same as in C-like languages, and the \fB-\fR operator may be used as a unary negation operator. The following are all valid examples of address expressions: .B 2+2 .br .B table_start + (elem_size + elem_pad)*4 .br .B main+0x3f .br .B __bss_end-__bss_start .br .B @sp .SH OPTIONS MSPDebug's behaviour can be configured via the following variables: .IP "\fBcolor\fR (boolean)" If true, MSPDebug will colorize debugging output. .IP "\fBfet_block_size\fR (numeric)" Change the size of the buffer used to transfer memory to and from the FET. Increasing the value from the default of 64 will improve transfer speed, but may cause problems with some chips. .IP "\fBenable_bsl_access\fR (boolean)" If set, some drivers will allow erase/program access to flash BSL memory. If in doubt, do not enable this. .IP "\fBenable_locked_flash_access\fR (boolean)" If set, some drivers will allow erase/program access to the info A segment. If in doubt, do not enable this. Currently, the tilib and uif drivers are affected by this option. .IP "\fBenable_fuse_blow\fR" If set, some drivers will allow the JTAG security fuse to be blown. .B WARNING: this is an irreversible operation! If in doubt, do not enable this option. .IP "\fBgdb_default_port\fR (numeric)" This option controls the default TCP port for the GDB server, if no argument is given to the "\fBgdb\fR" command. .IP "\fBgdb_loop\fR (boolean)" Automatically restart the GDB server after disconnection. If this option is set, then the GDB server keeps running until an error occurs, or the user interrupts with Ctrl+C. .IP "\fBgdbc_xfer_size\fR (numeric)" Maximum size of memory transfers for the GDB client. Increasing this value will result in faster transfers, but may cause problems with some servers. .IP "\fBiradix\fR (numeric)" Default input radix for address expressions. For address values with no radix specifier, this value gives the input radix, which is 10 (decimal) by default. .IP "\fBquiet\fR (boolean)" If set, MSPDebug will supress most of its debug-related output. This option defaults to false, but can be set true on start-up using the \fB-q\fR command-line option. .SH ENVIRONMENT .IP "\fBMSPDEBUG_TI3410_FW\fI" Specifies the location of TI3410 firmware, for raw USB access to FET430UIF or eZ430 devices. This variable should contain the path to an Intel HEX file containing suitable firmware for the TI3410. .SH FILES .IP "~/.mspdebug" File containing commands to be executed on startup. .IP "ti_3410.fw.ihex" Firmware image for the TI3410 USB interface chip. This file is only required for raw USB access to FET430UIF or eZ430 devices. .SH SEE ALSO \fBnm\fR(1), \fBgdb\fR(1), \fBobjcopy\fR(1) .SH BUGS If you find any bugs, you should report them to the author at dlbeer@gmail.com. It would help if you could include a transcript of an MSPDebug session illustrating the program, as well as any relevant binaries or other files. .SH COPYRIGHT Copyright (C) 2009-2013 Daniel Beer MSPDebug is free software, distributed under the terms of the GNU General Public license (version 2 or later). See the file COPYING included with the source code for more details. mspdebug-0.25/simio/000077500000000000000000000000001313531517500143725ustar00rootroot00000000000000mspdebug-0.25/simio/simio.c000066400000000000000000000227221313531517500156630ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include "output.h" #include "output_util.h" #include "dis.h" #include "simio.h" #include "simio_cpu.h" #include "simio_device.h" #include "simio_tracer.h" #include "simio_timer.h" #include "simio_wdt.h" #include "simio_hwmult.h" #include "simio_gpio.h" #include "simio_console.h" static const struct simio_class *const class_db[] = { &simio_tracer, &simio_timer, &simio_wdt, &simio_hwmult, &simio_gpio, &simio_console }; /* Simulator data. We keep a list of devices on the bus, and the special * function registers. * * Currently, MCLK and SMCLK are tied together, and ACLK runs at a fixed * ratio of 1:256 with MCLK. aclk_counter counts fractional cycles. */ static struct list_node device_list; static uint8_t sfr_data[16]; static int aclk_counter; static void destroy_device(struct simio_device *dev) { list_remove(&dev->node); dev->type->destroy(dev); } void simio_init(void) { list_init(&device_list); simio_reset(); } void simio_exit(void) { while (!LIST_EMPTY(&device_list)) destroy_device((struct simio_device *)device_list.next); } static const struct simio_class *find_class(const char *name) { int i; for (i = 0; i < ARRAY_LEN(class_db); i++) { const struct simio_class *t = class_db[i]; if (!strcasecmp(t->name, name)) return t; } return NULL; } static struct simio_device *find_device(const char *name) { struct list_node *n; for (n = device_list.next; n != &device_list; n = n->next) { struct simio_device *dev = (struct simio_device *)n; if (!strcasecmp(dev->name, name)) return dev; } return NULL; } static int cmd_add(char **arg_text) { const char *type_text = get_arg(arg_text); const char *name_text = get_arg(arg_text); const struct simio_class *type; struct simio_device *dev; if (!(name_text && type_text)) { printc_err("simio add: device class and name must be " "specified.\n"); return -1; } if (find_device(name_text)) { printc_err("simio add: device name is not unique: %s\n", name_text); return -1; } type = find_class(type_text); if (!type) { printc_err("simio add: unknown type.\n"); return -1; } dev = type->create(arg_text); if (!dev) { printc_err("simio add: failed to create device.\n"); return -1; } list_insert(&dev->node, &device_list); strncpy(dev->name, name_text, sizeof(dev->name)); dev->name[sizeof(dev->name) - 1] = 0; printc_dbg("Added new device \"%s\" of type \"%s\".\n", dev->name, dev->type->name); return 0; } static int cmd_del(char **arg_text) { const char *name_text = get_arg(arg_text); struct simio_device *dev; if (!name_text) { printc_err("simio del: device name must be specified.\n"); return -1; } dev = find_device(name_text); if (!dev) { printc_err("simio del: no such device: %s\n", name_text); return -1; } destroy_device(dev); printc_dbg("Destroyed device \"%s\".\n", name_text); return 0; } static int cmd_devices(char **arg_text) { struct list_node *n; (void)arg_text; for (n = device_list.next; n != &device_list; n = n->next) { struct simio_device *dev = (struct simio_device *)n; int irq = -1; if (dev->type->check_interrupt) irq = dev->type->check_interrupt(dev); printc(" %-10s (type %s", dev->name, dev->type->name); if (irq < 0) printc(")\n"); else printc(", IRQ pending: %d)\n", irq); } return 0; } static int cmd_classes(char **arg_text) { struct vector v; int i; (void)arg_text; vector_init(&v, sizeof(const char *)); for (i = 0; i < ARRAY_LEN(class_db); i++) { if (vector_push(&v, &class_db[i]->name, 1) < 0) { printc_err("simio classes: can't allocate memory\n"); vector_destroy(&v); return -1; } } printc("Available device classes:\n"); namelist_print(&v); vector_destroy(&v); return 0; } static int cmd_help(char **arg_text) { const char *name = get_arg(arg_text); const struct simio_class *type; if (!name) { printc_err("simio help: you must specify a device class\n"); return -1; } type = find_class(name); if (!type) { printc_err("simio help: unknown device class: %s\n", name); return -1; } printc("\x1b[1mDEVICE CLASS: %s\x1b[0m\n\n%s\n", type->name, type->help); return 0; } static int cmd_config(char **arg_text) { const char *name = get_arg(arg_text); const char *param = get_arg(arg_text); struct simio_device *dev; if (!(name && param)) { printc_err("simio config: you must specify a device name and " "a parameter\n"); return -1; } dev = find_device(name); if (!dev) { printc_err("simio config: no such device: %s\n", name); return -1; } if (!dev->type->config) { printc_err("simio config: no configuration parameters are " "defined for this device\n"); return -1; } return dev->type->config(dev, param, arg_text); } static int cmd_info(char **arg_text) { const char *name = get_arg(arg_text); struct simio_device *dev; if (!name) { printc_err("simio info: you must specify a device name\n"); return -1; } dev = find_device(name); if (!dev) { printc_err("simio info: no such device: %s\n", name); return -1; } if (!dev->type->info) { printc_err("simio config: no information available\n"); return -1; } return dev->type->info(dev); } int cmd_simio(char **arg_text) { const char *subcmd = get_arg(arg_text); static const struct { const char *name; int (*func)(char **arg_text); } cmd_table[] = { {"add", cmd_add}, {"del", cmd_del}, {"devices", cmd_devices}, {"classes", cmd_classes}, {"help", cmd_help}, {"config", cmd_config}, {"info", cmd_info} }; int i; if (!subcmd) { printc_err("simio: a subcommand is required\n"); return -1; } for (i = 0; i < ARRAY_LEN(cmd_table); i++) if (!strcasecmp(cmd_table[i].name, subcmd)) return cmd_table[i].func(arg_text); printc_err("simio: unknown subcommand: %s\n", subcmd); return -1; } void simio_reset(void) { struct list_node *n; memset(sfr_data, 0, sizeof(sfr_data)); aclk_counter = 0; for (n = device_list.next; n != &device_list; n = n->next) { struct simio_device *dev = (struct simio_device *)n; const struct simio_class *type = dev->type; if (type->reset) type->reset(dev); } } #define IO_REQUEST_FUNC(name, method, datatype) \ int name(address_t addr, datatype data) { \ struct list_node *n; \ int ret = 1; \ \ for (n = device_list.next; n != &device_list; n = n->next) { \ struct simio_device *dev = (struct simio_device *)n; \ const struct simio_class *type = dev->type; \ \ if (type->method) { \ int r = type->method(dev, addr, data); \ \ if (r < ret) \ ret = r; \ } \ } \ \ return ret; \ } #define IO_REQUEST_FUNC_S(name, method, datatype) \ static IO_REQUEST_FUNC(name, method, datatype) IO_REQUEST_FUNC(simio_write, write, uint16_t) IO_REQUEST_FUNC(simio_read, read, uint16_t *) IO_REQUEST_FUNC_S(simio_write_b_device, write_b, uint8_t) IO_REQUEST_FUNC_S(simio_read_b_device, read_b, uint8_t *) int simio_write_b(address_t addr, uint8_t data) { if (addr < 16) { sfr_data[addr] = data; return 0; } return simio_write_b_device(addr, data); } int simio_read_b(address_t addr, uint8_t *data) { if (addr < 16) { *data = sfr_data[addr]; return 0; } return simio_read_b_device(addr, data); } int simio_check_interrupt(void) { int irq = -1; struct list_node *n; for (n = device_list.next; n != &device_list; n = n->next) { struct simio_device *dev = (struct simio_device *)n; const struct simio_class *type = dev->type; if (type->check_interrupt) { int i = type->check_interrupt(dev); if (i > irq) irq = i; } } return irq; } void simio_ack_interrupt(int irq) { struct list_node *n; for (n = device_list.next; n != &device_list; n = n->next) { struct simio_device *dev = (struct simio_device *)n; const struct simio_class *type = dev->type; if (type->ack_interrupt) type->ack_interrupt(dev, irq); } } void simio_step(uint16_t status_register, int cycles) { int clocks[SIMIO_NUM_CLOCKS] = {0}; struct list_node *n; aclk_counter += cycles; clocks[SIMIO_MCLK] = cycles; clocks[SIMIO_SMCLK] = cycles; clocks[SIMIO_ACLK] = aclk_counter >> 8; aclk_counter &= 0xff; if (status_register & MSP430_SR_CPUOFF) clocks[SIMIO_MCLK] = 0; if (status_register & MSP430_SR_SCG1) clocks[SIMIO_SMCLK] = 0; if (status_register & MSP430_SR_OSCOFF) clocks[SIMIO_ACLK] = 0; for (n = device_list.next; n != &device_list; n = n->next) { struct simio_device *dev = (struct simio_device *)n; const struct simio_class *type = dev->type; if (type->step) type->step(dev, status_register, clocks); } } uint8_t simio_sfr_get(address_t which) { if (which > sizeof(sfr_data)) return 0; return sfr_data[which]; } void simio_sfr_modify(address_t which, uint8_t mask, uint8_t bits) { if (which > sizeof(sfr_data)) return; sfr_data[which] = (sfr_data[which] & ~mask) | bits; } mspdebug-0.25/simio/simio.h000066400000000000000000000020571313531517500156670ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef SIMIO_H_ #define SIMIO_H_ /* Initialize the IO simulator. */ void simio_init(void); /* Clean up allocated resources. */ void simio_exit(void); /* This file gives the prototype for the "simio" command function. */ int cmd_simio(char **arg_text); #endif mspdebug-0.25/simio/simio_console.c000066400000000000000000000063371313531517500174110ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2012 Unai Uribarri Rodriguez * * This program is free software; you can redisgibute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is disgibuted in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include "simio_device.h" #include "simio_console.h" #include "expr.h" #include "output.h" struct console { struct simio_device base; /* Base address */ address_t base_addr; char buffer[256]; unsigned buffer_offset; }; static struct simio_device *console_create(char **arg_text) { struct console *c; (void)arg_text; c = malloc(sizeof(*c)); if (!c) { pr_error("console: can't allocate memory"); return NULL; } memset(c, 0, sizeof(*c)); c->base.type = &simio_console; c->base_addr = 0xFF; c->buffer_offset = 0; return (struct simio_device *)c; } static void console_destroy(struct simio_device *dev) { struct console *c = (struct console *)dev; free(c); } static void console_reset(struct simio_device *dev) { struct console *c = (struct console *)dev; c->buffer_offset = 0; } static int config_addr(address_t *addr, char **arg_text) { char *text = get_arg(arg_text); if (!text) { printc_err("console: config: expected address\n"); return -1; } if (expr_eval(text, addr) < 0) { printc_err("console: can't parse address: %s\n", text); return -1; } return 0; } static int console_config(struct simio_device *dev, const char *param, char **arg_text) { struct console *c = (struct console *)dev; if (!strcasecmp(param, "base")) { return config_addr(&c->base_addr, arg_text); } printc_err("console: config: unknown parameter: %s\n", param); return -1; } static int console_info(struct simio_device *dev) { struct console *c = (struct console *)dev; printc("Base address: 0x%04x\n", c->base_addr); printc("Buffer: %.*s\n", c->buffer_offset, c->buffer); return 0; } static int console_write_b(struct simio_device *dev, address_t addr, uint8_t data) { struct console *c = (struct console *)dev; if (addr == c->base_addr) { c->buffer[c->buffer_offset++] = data; if (data == '\n' || c->buffer_offset == sizeof c->buffer) { printc("%.*s", c->buffer_offset, c->buffer); c->buffer_offset = 0; } } return 1; } const struct simio_class simio_console = { .name = "console", .help = "This peripheral prints to stdout every byte written to base address\n" "\n" "Config arguments are:\n" " base
\n" " Set the peripheral base address. Defaults to 0x00FF\n" "\n", .create = console_create, .destroy = console_destroy, .reset = console_reset, .config = console_config, .info = console_info, .write_b = console_write_b, }; mspdebug-0.25/simio/simio_console.h000066400000000000000000000016151313531517500174100ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2012 Unai Uribarri * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef SIMIO_CONSOLE_H_ #define SIMIO_CONSOLE_H_ extern const struct simio_class simio_console; #endif mspdebug-0.25/simio/simio_cpu.h000066400000000000000000000043131313531517500165330ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef SIMIO_CPU_H_ #define SIMIO_CPU_H_ /* This file describes the interface between the CPU simulator and the IO * simulator. It gives prototypes for functions which should be periodically * called by the CPU simulator. */ #include #include "util.h" /* This function should be called when the CPU is reset, to also reset * the IO simulator. */ void simio_reset(void); /* These functions should be called to perform programmed IO requests. A * return value of 0 indicates success, 1 is an unhandled request, and -1 * is an error which should cause execution to stop. */ int simio_write(address_t addr, uint16_t data); int simio_read(address_t addr, uint16_t *data); int simio_write_b(address_t addr, uint8_t data); int simio_read_b(address_t addr, uint8_t *data); /* Check for an interrupt before executing an instruction. It returns -1 if * no interrupt is pending, otherwise the number of the highest priority * pending interrupt. */ int simio_check_interrupt(void); /* When the CPU begins to handle an interrupt, it needs to notify the IO * simulation. Some interrupt flags are cleared automatically when handled. */ void simio_ack_interrupt(int irq); /* This should be called after executing an instruction to advance the system * clocks. * * The status_register value should be the value of SR _before_ the * instruction was executed. */ void simio_step(uint16_t status_register, int cycles); #endif mspdebug-0.25/simio/simio_device.h000066400000000000000000000064261313531517500172120ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef SIMIO_DEVICE_H_ #define SIMIO_DEVICE_H_ #include #include "util.h" #include "list.h" /* Each system clock has a unique index. After each instruction, step() * is invoked on each device with an array of clock transition counts. */ typedef enum { SIMIO_MCLK = 0, SIMIO_SMCLK, SIMIO_ACLK, SIMIO_NUM_CLOCKS } simio_clock_t; /* Access to special function registers is provided by these functions. The * modify function does: * * SFR = (SFR & ~mask) | bits */ #define SIMIO_IE1 0x00 #define SIMIO_IFG1 0x01 #define SIMIO_IE2 0x02 #define SIMIO_IFG2 0x03 uint8_t simio_sfr_get(address_t which); void simio_sfr_modify(address_t which, uint8_t mask, uint8_t bits); struct simio_class; /* Device base class. * * The node and name fields will be filled out by the IO simulator - they're * used for keeping track of the device list. The node member MUST be the * first in the struct. */ struct simio_device { struct list_node node; char name[64]; const struct simio_class *type; }; struct simio_class { const char *name; const char *help; /* Instantiate a new device, with the given arguments. This may * fail, in which case NULL should be returned. */ struct simio_device *(*create)(char **arg_text); void (*destroy)(struct simio_device *dev); /* These methods are invoked via the command interface to modify * device data and show status. */ int (*config)(struct simio_device *dev, const char *param, char **arg_text); int (*info)(struct simio_device *dev); /* System reset hook. */ void (*reset)(struct simio_device *dev); /* Programmed IO functions return 1 to indicate an unhandled * request. This scheme allows stacking. */ int (*write)(struct simio_device *dev, address_t addr, uint16_t data); int (*read)(struct simio_device *dev, address_t addr, uint16_t *data); int (*write_b)(struct simio_device *dev, address_t addr, uint8_t data); int (*read_b)(struct simio_device *dev, address_t addr, uint8_t *data); /* Check and acknowledge interrupts. Each device may produce * a single interrupt request at any time. */ int (*check_interrupt)(struct simio_device *dev); void (*ack_interrupt)(struct simio_device *dev, int irq); /* Run the clocks for this device. The counters array has one * array per clock, and gives the number of cycles elapsed since * the last call to this method. */ void (*step)(struct simio_device *dev, uint16_t status_register, const int *clocks); }; #endif mspdebug-0.25/simio/simio_gpio.c000066400000000000000000000171661313531517500167070ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redisgibute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is disgibuted in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include "simio_device.h" #include "simio_gpio.h" #include "expr.h" #include "output.h" #define REG_IN 0 #define REG_OUT 1 #define REG_DIR 2 #define REG_IFG 3 #define REG_IES 4 #define REG_IE 5 #define REG_SEL 6 #define REG_REN 7 struct gpio { struct simio_device base; /* Print when output changes? */ int verbose; /* Base address */ address_t base_addr; /* IRQ, or -1 if disabled */ int irq; /* Congol registers */ uint8_t regs[8]; }; static struct simio_device *gpio_create(char **arg_text) { struct gpio *g; (void)arg_text; g = malloc(sizeof(*g)); if (!g) { pr_error("gpio: can't allocate memory"); return NULL; } memset(g, 0, sizeof(*g)); g->base.type = &simio_gpio; g->base_addr = 0x20; g->irq = -1; return (struct simio_device *)g; } static void gpio_destroy(struct simio_device *dev) { struct gpio *g = (struct gpio *)dev; free(g); } static void gpio_reset(struct simio_device *dev) { struct gpio *g = (struct gpio *)dev; g->regs[REG_DIR] = 0; g->regs[REG_IFG] = 0; g->regs[REG_IE] = 0; g->regs[REG_SEL] = 0; g->regs[REG_REN] = 0; } static int config_addr(address_t *addr, char **arg_text) { char *text = get_arg(arg_text); if (!text) { printc_err("gpio: config: expected address\n"); return -1; } if (expr_eval(text, addr) < 0) { printc_err("gpio: can't parse address: %s\n", text); return -1; } return 0; } static int config_irq(int *irq, char **arg_text) { char *text = get_arg(arg_text); address_t value; if (!text) { printc_err("gpio: config: expected interrupt number\n"); return -1; } if (expr_eval(text, &value) < 0) { printc_err("gpio: can't parse interrupt number: %s\n", text); return -1; } *irq = value; return 0; } static int config_channel(struct gpio *g, char **arg_text) { char *which_text = get_arg(arg_text); char *value_text = get_arg(arg_text); address_t which; address_t value; uint8_t mask; if (!(which_text && value_text)) { printc_err("gpio: config: expected pin and value\n"); return -1; } if (expr_eval(which_text, &which) < 0) { printc_err("gpio: can't parse pin number: %s\n", which_text); return -1; } if (expr_eval(value_text, &value) < 0) { printc_err("gpio: can't parse pin value: %s\n", value_text); return -1; } if (which > 7) { printc_err("gpio: invalid pin number: %d\n", which); return -1; } mask = 1 << which; if (g->regs[REG_IE] & mask) { if (((g->regs[REG_IES] & mask) && !value && (g->regs[REG_IN] & mask)) || (!(g->regs[REG_IES] & mask) && value && !(g->regs[REG_IN] & mask))) g->regs[REG_IFG] |= mask; } if (value) g->regs[REG_IN] |= mask; else g->regs[REG_IN] &= ~mask; return 0; } static int gpio_config(struct simio_device *dev, const char *param, char **arg_text) { struct gpio *g = (struct gpio *)dev; if (!strcasecmp(param, "base")) return config_addr(&g->base_addr, arg_text); if (!strcasecmp(param, "irq")) return config_irq(&g->irq, arg_text); if (!strcasecmp(param, "set")) return config_channel(g, arg_text); if (!strcasecmp(param, "noirq")) { g->irq = -1; return 0; } if (!strcasecmp(param, "verbose")) { g->verbose = 1; return 0; } if (!strcasecmp(param, "quiet")) { g->verbose = 0; return 0; } printc_err("gpio: config: unknown parameter: %s\n", param); return -1; } static void print_tristate(uint8_t mask, uint8_t value) { int i; for (i = 0; i < 8; i++) { if (!(mask & 0x80)) printc("-"); else if (value & 0x80) printc("H"); else printc("l"); if (i == 3) printc(" "); value <<= 1; mask <<= 1; } } static int port_map(struct gpio *g, address_t addr) { int ren_addr; if (g->irq >= 0) { if (addr < g->base_addr) return -1; if (addr >= g->base_addr + 8) return -1; return addr - g->base_addr; } if (addr >= g->base_addr && addr <= g->base_addr + 2) return addr - g->base_addr; if (addr == g->base_addr + 3) return REG_SEL; ren_addr = ((g->base_addr >> 2) & 1) | ((g->base_addr >> 4) & 2) | 0x10; if (addr == ren_addr) return REG_REN; return -1; } static int gpio_info(struct simio_device *dev) { struct gpio *g = (struct gpio *)dev; printc("Base address: 0x%04x\n", g->base_addr); printc("Input state: "); print_tristate(~g->regs[REG_DIR] & ~g->regs[REG_SEL], g->regs[REG_IN]); printc("\n"); printc("Output state: "); print_tristate(g->regs[REG_DIR] & ~g->regs[REG_SEL], g->regs[REG_OUT]); printc("\n"); printc("Direction: "); print_tristate(~g->regs[REG_SEL], g->regs[REG_DIR]); printc("\n"); if (g->irq >= 0) { printc("IRQ: %d\n", g->irq); printc("Interrupt: "); print_tristate(g->regs[REG_IE], g->regs[REG_IFG]); printc("\n"); printc("Interrupt edge select: "); print_tristate(g->regs[REG_IE], g->regs[REG_IES]); printc("\n"); printc("Interrupt enable: "); print_tristate(0xff, g->regs[REG_IE]); printc("\n"); } printc("Port select: "); print_tristate(0xff, g->regs[REG_SEL]); printc("\n"); printc("Resistor enable: "); print_tristate(0xff, g->regs[REG_REN]); printc("\n"); return 0; } static int gpio_write_b(struct simio_device *dev, address_t addr, uint8_t data) { struct gpio *g = (struct gpio *)dev; int index = port_map(g, addr); if (index < 0) return 1; if (g->verbose && index == REG_OUT) { uint8_t delta = (g->regs[REG_OUT] ^ data) & g->regs[REG_DIR] & ~g->regs[REG_SEL]; if (delta) { printc("gpio: state change on %s: ", g->base.name); print_tristate(delta, data); printc("\n"); } } g->regs[index] = data; return 1; } static int gpio_read_b(struct simio_device *dev, address_t addr, uint8_t *data) { struct gpio *g = (struct gpio *)dev; int index = port_map(g, addr); if (index < 0) return 1; if (addr < g->base_addr || index >= 8) return 1; *data = g->regs[index]; return 0; } static int gpio_check_interrupt(struct simio_device *dev) { struct gpio *g = (struct gpio *)dev; if (g->regs[REG_IFG] & g->regs[REG_IE]) return g->irq; return -1; } const struct simio_class simio_gpio = { .name = "gpio", .help = "This peripheral implements a digital IO port, with optional interrupt\n" "functionality.\n" "\n" "Config arguments are:\n" " base
\n" " Set the peripheral base address.\n" " irq \n" " Set the interrupt vector for input pin state changes.\n" " noirq\n" " Disable interrupt functionality.\n" " verbose\n" " Print a message when output states change.\n" " quiet\n" " Don't print messages as output state changes.\n" " set <0|1>\n" " Set input pin state.\n", .create = gpio_create, .destroy = gpio_destroy, .reset = gpio_reset, .config = gpio_config, .info = gpio_info, .write_b = gpio_write_b, .read_b = gpio_read_b, .check_interrupt = gpio_check_interrupt }; mspdebug-0.25/simio/simio_gpio.h000066400000000000000000000016101313531517500166770ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef SIMIO_GPIO_H_ #define SIMIO_GPIO_H_ extern const struct simio_class simio_gpio; #endif mspdebug-0.25/simio/simio_hwmult.c000066400000000000000000000070551313531517500172650ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include "simio_device.h" #include "simio_hwmult.h" #include "output.h" #include "expr.h" /* Multiplier register addresses - taken from mspgcc */ #define MPY 0x0130 /* Multiply Unsigned/Operand 1 */ #define MPYS 0x0132 /* Multiply Signed/Operand 1 */ #define MAC 0x0134 /* Multiply Unsigned and Accumulate/Operand 1 */ #define MACS 0x0136 /* Multiply Signed and Accumulate/Operand 1 */ #define OP2 0x0138 /* Operand 2 */ #define RESLO 0x013A /* Result Low Word */ #define RESHI 0x013C /* Result High Word */ #define SUMEXT 0x013E /* Sum Extend */ struct hwmult { struct simio_device base; int mode; uint16_t op1; uint16_t op2; uint32_t result; uint16_t sumext; }; struct simio_device *hwmult_create(char **arg_text) { struct hwmult *h = malloc(sizeof(*h)); (void)arg_text; if (!h) { pr_error("hwmult: can't allocate memory"); return NULL; } memset(h, 0, sizeof(*h)); h->base.type = &simio_hwmult; return (struct simio_device *)h; } static void hwmult_destroy(struct simio_device *dev) { free(dev); } static void do_multiply(struct hwmult *h) { uint32_t im; uint64_t temp = 0; /* Multiply */ if (h->mode & 2) im = (int16_t)h->op1 * (int16_t)h->op2; else im = h->op1 * h->op2; /* Accumulate or store */ if (h->mode & 4) { temp = (uint64_t)h->result + im; h->result = temp; } else h->result = im; /* Set SUMEXT */ if (h->mode & 2) /* MPYS and MACS */ h->sumext = (h->result & 0x80000000) ? 0xffff : 0; else if(h->mode == MAC) h->sumext = temp >> 32; else /* MPY */ h->sumext = 0; } static int hwmult_write(struct simio_device *dev, address_t addr, uint16_t data) { struct hwmult *h = (struct hwmult *)dev; switch (addr) { case RESHI: h->result = (h->result & 0xffff) | ((uint32_t)data << 16); return 0; case RESLO: h->result = (h->result & 0xffff0000) | data; return 0; case OP2: h->op2 = data; do_multiply(h); return 0; case MPY: case MPYS: case MAC: case MACS: h->op1 = data; h->mode = addr; return 0; } return 1; } static int hwmult_read(struct simio_device *dev, address_t addr, uint16_t *data) { struct hwmult *h = (struct hwmult *)dev; switch (addr) { case MPY: case MPYS: case MAC: case MACS: *data = h->op1; return 0; case OP2: *data = h->op2; return 0; case RESLO: *data = h->result & 0xffff; return 0; case RESHI: *data = h->result >> 16; return 0; case SUMEXT: *data = h->sumext; return 0; } return 1; } const struct simio_class simio_hwmult = { .name = "hwmult", .help = "This module simulates the hardware multiplier.\n", .create = hwmult_create, .destroy = hwmult_destroy, .write = hwmult_write, .read = hwmult_read }; mspdebug-0.25/simio/simio_hwmult.h000066400000000000000000000016161313531517500172670ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef SIMIO_HWMULT_H_ #define SIMIO_HWMULT_H_ extern const struct simio_class simio_hwmult; #endif mspdebug-0.25/simio/simio_timer.c000066400000000000000000000272241313531517500170650ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include "simio_device.h" #include "simio_timer.h" #include "expr.h" #include "output.h" /* TACTL bits (taken from mspgcc headers) */ #define TASSEL2 0x0400 /* unused */ #define TASSEL1 0x0200 /* Timer A clock source select 1 */ #define TASSEL0 0x0100 /* Timer A clock source select 0 */ #define ID1 0x0080 /* Timer A clock input divider 1 */ #define ID0 0x0040 /* Timer A clock input divider 0 */ #define MC1 0x0020 /* Timer A mode control 1 */ #define MC0 0x0010 /* Timer A mode control 0 */ #define TACLR 0x0004 /* Timer A counter clear */ #define TAIE 0x0002 /* Timer A counter interrupt enable */ #define TAIFG 0x0001 /* Timer A counter interrupt flag */ /* TACCTLx flags (taken from mspgcc) */ #define CM1 0x8000 /* Capture mode 1 */ #define CM0 0x4000 /* Capture mode 0 */ #define CCIS1 0x2000 /* Capture input select 1 */ #define CCIS0 0x1000 /* Capture input select 0 */ #define SCS 0x0800 /* Capture sychronize */ #define SCCI 0x0400 /* Latched capture signal (read) */ #define CAP 0x0100 /* Capture mode: 1 /Compare mode : 0 */ #define OUTMOD2 0x0080 /* Output mode 2 */ #define OUTMOD1 0x0040 /* Output mode 1 */ #define OUTMOD0 0x0020 /* Output mode 0 */ #define CCIE 0x0010 /* Capture/compare interrupt enable */ #define CCI 0x0008 /* Capture input signal (read) */ /* #define OUT 0x0004 PWM Output signal if output mode 0 */ #define COV 0x0002 /* Capture/compare overflow flag */ #define CCIFG 0x0001 /* Capture/compare interrupt flag */ #define MAX_CCRS 7 struct timer { struct simio_device base; int size; int clock_input; int go_down; address_t base_addr; address_t iv_addr; int irq0; int irq1; /* IO registers */ uint16_t tactl; uint16_t tar; uint16_t ctls[MAX_CCRS]; uint16_t ccrs[MAX_CCRS]; }; static struct simio_device *timer_create(char **arg_text) { char *size_text = get_arg(arg_text); struct timer *tr; int size = 3; if (size_text) { address_t value; if (expr_eval(size_text, &value) < 0) { printc_err("timer: can't parse size: %s\n", size_text); return NULL; } if (size < 2 || size > MAX_CCRS) { printc_err("timer: invalid size: %d\n", size); return NULL; } } tr = malloc(sizeof(*tr)); if (!tr) { pr_error("timer: can't allocate memory"); return NULL; } memset(tr, 0, sizeof(*tr)); tr->base.type = &simio_timer; tr->size = size; tr->base_addr = 0x160; tr->iv_addr = 0x12e; tr->irq0 = 9; tr->irq1 = 8; return (struct simio_device *)tr; } static void timer_destroy(struct simio_device *dev) { struct timer *tr = (struct timer *)dev; free(tr); } static void timer_reset(struct simio_device *dev) { struct timer *tr = (struct timer *)dev; tr->tactl = 0; tr->tar = 0; tr->go_down = 0; memset(tr->ccrs, 0, sizeof(tr->ccrs)); memset(tr->ctls, 0, sizeof(tr->ctls)); } static int config_addr(address_t *addr, char **arg_text) { char *text = get_arg(arg_text); if (!text) { printc_err("timer: config: expected address\n"); return -1; } if (expr_eval(text, addr) < 0) { printc_err("timer: can't parse address: %s\n", text); return -1; } return 0; } static int config_irq(int *irq, char **arg_text) { char *text = get_arg(arg_text); address_t value; if (!text) { printc_err("timer: config: expected interrupt number\n"); return -1; } if (expr_eval(text, &value) < 0) { printc_err("timer: can't parse interrupt number: %s\n", text); return -1; } *irq = value; return 0; } static int config_channel(struct timer *tr, char **arg_text) { char *which_text = get_arg(arg_text); char *value_text = get_arg(arg_text); address_t which; address_t value; int oldval; uint16_t edge_flags = 0; if (!(which_text && value_text)) { printc_err("timer: config: expected channel and value\n"); return -1; } if (expr_eval(which_text, &which) < 0) { printc_err("timer: can't parse channel number: %s\n", which_text); return -1; } if (expr_eval(value_text, &value) < 0) { printc_err("timer: can't parse channel value: %s\n", value_text); return -1; } if (which > tr->size) { printc_err("timer: invalid channel number: %d\n", which); return -1; } oldval = tr->ctls[which] & CCI; tr->ctls[which] &= ~CCI; if (value) tr->ctls[which] |= CCI; if (oldval && !value) edge_flags |= CM1; if (!oldval && value) edge_flags |= CM0; printc_dbg("Timer channel %d: %s => %s\n", which, oldval ? "H" : "L", value ? "H" : "L"); if ((tr->ctls[which] & edge_flags) && (tr->ctls[which] & CAP)) { if (tr->ctls[which] & CCIFG) { printc_dbg("Timer capture overflow\n"); tr->ctls[which] |= COV; } else { printc_dbg("Timer capture interrupt triggered\n"); tr->ccrs[which] = tr->tar; tr->ctls[which] |= CCIFG; } } return 0; } static int timer_config(struct simio_device *dev, const char *param, char **arg_text) { struct timer *tr = (struct timer *)dev; if (!strcasecmp(param, "base")) return config_addr(&tr->base_addr, arg_text); if (!strcasecmp(param, "iv")) return config_addr(&tr->iv_addr, arg_text); if (!strcasecmp(param, "irq0")) return config_irq(&tr->irq0, arg_text); if (!strcasecmp(param, "irq1")) return config_irq(&tr->irq1, arg_text); if (!strcasecmp(param, "set")) return config_channel(tr, arg_text); printc_err("timer: config: unknown parameter: %s\n", param); return -1; } static uint16_t calc_iv(struct timer *tr, int update) { int i; for (i = 0; i < tr->size; i++) if ((tr->ctls[i] & (CCIE | CCIFG)) == (CCIE | CCIFG)) { /* Reading or writing TAIV clears the highest flag. TACCR0 is cleared in timer_ack_interrupt(). */ if (update && (i > 0)) tr->ctls[i] &= ~CCIFG; return i * 2; } if ((tr->tactl & (TAIFG | TAIE)) == (TAIFG | TAIE)) { if (update) tr->tactl &= ~TAIFG; return 0xa; } return 0; } static int timer_info(struct simio_device *dev) { struct timer *tr = (struct timer *)dev; int i; printc("Base address: 0x%04x\n", tr->base_addr); printc("IV address: 0x%04x\n", tr->iv_addr); printc("IRQ0: %d\n", tr->irq0); printc("IRQ1: %d\n", tr->irq1); printc("\n"); printc("TACTL: 0x%04x\n", tr->tactl); printc("TAR: 0x%04x\n", tr->tar); printc("TAIV: 0x%02x\n", calc_iv(tr, 0)); printc("\n"); for (i = 0; i < tr->size; i++) printc("Channel %2d, TACTL = 0x%04x, TACCR = 0x%04x\n", i, tr->ctls[i], tr->ccrs[i]); return 0; } static int timer_write(struct simio_device *dev, address_t addr, uint16_t data) { struct timer *tr = (struct timer *)dev; if (addr == tr->base_addr) { tr->tactl = data & ~(TACLR | 0x08); if (data & TACLR) tr->tar = 0; return 0; } if (addr == tr->base_addr + 0x10) { tr->tar = data; return 0; } if (addr >= tr->base_addr + 2 && addr < tr->base_addr + tr->size + 2) { int index = ((addr & 0xf) - 2) >> 1; tr->ctls[index] = (data & 0xf9f7) | (tr->ctls[index] & 0x0608); return 0; } if (addr >= tr->base_addr + 0x12 && addr < tr->base_addr + tr->size + 0x12) { int index = ((addr & 0xf) - 2) >> 1; tr->ccrs[index] = data; return 0; } if (addr == tr->iv_addr) { /* Writing to TAIV clears the highest priority bit. */ calc_iv(tr, 1); return 0; } return 1; } static int timer_read(struct simio_device *dev, address_t addr, uint16_t *data) { struct timer *tr = (struct timer *)dev; if (addr == tr->base_addr) { *data = tr->tactl; return 0; } if (addr == tr->base_addr + 0x10) { *data = tr->tar; return 0; } if (addr >= tr->base_addr + 2 && addr < tr->base_addr + tr->size + 2) { *data = tr->ctls[((addr & 0xf) - 2) >> 1]; return 0; } if (addr >= tr->base_addr + 0x12 && addr < tr->base_addr + tr->size + 0x12) { *data = tr->ccrs[((addr & 0xf) - 2) >> 1]; return 0; } if (addr == tr->iv_addr) { *data = calc_iv(tr, 1); return 0; } return 1; } static int timer_check_interrupt(struct simio_device *dev) { struct timer *tr = (struct timer *)dev; int i; if ((tr->ctls[0] & (CCIE | CCIFG)) == (CCIE | CCIFG)) return tr->irq0; if ((tr->tactl & (TAIFG | TAIE)) == (TAIFG | TAIE)) return tr->irq1; for (i = 1; i < tr->size; i++) if ((tr->ctls[i] & (CCIE | CCIFG)) == (CCIE | CCIFG)) return tr->irq1; return -1; } static void timer_ack_interrupt(struct simio_device *dev, int irq) { struct timer *tr = (struct timer *)dev; if (irq == tr->irq0) tr->ctls[0] &= ~CCIFG; /* By design irq1 does not clear CCIFG or TAIFG automatically */ } static void tar_step(struct timer *tr) { switch ((tr->tactl >> 4) & 3) { case 0: break; case 1: if (tr->tar == tr->ccrs[0]) { tr->tar = 0; tr->tactl |= TAIFG; } else { tr->tar++; } break; case 2: tr->tar++; if (!tr->tar) tr->tactl |= TAIFG; break; case 3: if (tr->tar >= tr->ccrs[0]) tr->go_down = 1; if (!tr->tar) tr->go_down = 0; if (tr->go_down) { tr->tar--; if (!tr->tar) tr->tactl |= TAIFG; } else { tr->tar++; } break; } } static void timer_step(struct simio_device *dev, uint16_t status, const int *clocks) { struct timer *tr = (struct timer *)dev; int pulse_count; int i; (void)status; /* Count input clock pulses */ i = (tr->tactl >> 8) & 3; if (i == 2) tr->clock_input += clocks[SIMIO_SMCLK]; else if (i == 1) tr->clock_input += clocks[SIMIO_ACLK]; /* Figure out our clock input divide ratio */ i = (tr->tactl >> 6) & 3; pulse_count = tr->clock_input >> i; tr->clock_input &= ((1 << i) - 1); /* Run the timer for however many pulses */ for (i = 0; i < pulse_count; i++) { int j; for (j = 0; j < tr->size; j++) if (!(tr->ctls[j] & CAP) && (tr->tar == tr->ccrs[j])) { if (tr->ctls[j] & CCI) tr->ctls[j] |= SCCI; else tr->ctls[j] &= ~SCCI; tr->ctls[j] |= CCIFG; } tar_step(tr); } } const struct simio_class simio_timer = { .name = "timer", .help = "This peripheral implements the Timer_A module.\n" "\n" "Constructor arguments: [size]\n" " Specify the number of capture/compare registers.\n" "\n" "Config arguments are:\n" " base
\n" " Set the peripheral base address.\n" " irq0 \n" " Set the interrupt vector for CCR0.\n" " irq1 \n" " Set the interrupt vector for CCR1.\n" " iv
\n" " Set the interrupt vector register address.\n" " set <0|1>\n" " Set the capture input value on the given channel.\n", .create = timer_create, .destroy = timer_destroy, .reset = timer_reset, .config = timer_config, .info = timer_info, .write = timer_write, .read = timer_read, .check_interrupt = timer_check_interrupt, .ack_interrupt = timer_ack_interrupt, .step = timer_step }; mspdebug-0.25/simio/simio_timer.h000066400000000000000000000016131313531517500170640ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef SIMIO_TIMER_H_ #define SIMIO_TIMER_H_ extern const struct simio_class simio_timer; #endif mspdebug-0.25/simio/simio_tracer.c000066400000000000000000000175141313531517500172260ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include "simio_device.h" #include "simio_tracer.h" #include "expr.h" #include "output.h" #include "output_util.h" #include "dis.h" #define DEFAULT_HISTORY 16 typedef enum { EVENT_WRITE_16, EVENT_READ_16, EVENT_WRITE_8, EVENT_READ_8, EVENT_IRQ_HANDLE, EVENT_RESET } event_type_t; typedef unsigned long long counter_t; struct event { counter_t when; event_type_t what; address_t addr; uint16_t data; }; struct tracer { struct simio_device base; /* IO event history ring buffer. */ struct event *history; int size; int head; int tail; /* Clock and instruction counters. */ counter_t cycles[SIMIO_NUM_CLOCKS]; counter_t inscount; /* Outstanding interrupt request. */ int irq_request; /* Verbose mode. */ int verbose; }; static void event_print(const struct event *e) { char name[128]; print_address(e->addr, name, sizeof(name), 0); printc(" %10" LLFMT ": ", e->when); switch (e->what) { case EVENT_WRITE_16: printc("write.w => %s 0x%04x\n", name, e->data); break; case EVENT_READ_16: printc("read.w => %s\n", name); break; case EVENT_WRITE_8: printc("write.b => %s 0x%02x\n", name, e->data); break; case EVENT_READ_8: printc("read.b => %s\n", name); break; case EVENT_IRQ_HANDLE: printc("irq handle %d\n", e->addr); break; case EVENT_RESET: printc("system reset\n"); break; default: printc("unknown 0x%04x 0x%04x\n", e->addr, e->data); break; } } static void event_rec(struct tracer *tr, event_type_t what, address_t addr, uint16_t data) { struct event *e = &tr->history[tr->head]; e->when = tr->cycles[SIMIO_MCLK]; e->what = what; e->addr = addr; e->data = data; if (tr->verbose) event_print(e); tr->head = (tr->head + 1) % tr->size; if (tr->head == tr->tail) tr->tail = (tr->tail + 1) % tr->size; } static struct simio_device *tracer_create(char **arg_text) { const char *size_text = get_arg(arg_text); int size = DEFAULT_HISTORY; struct event *history; struct tracer *tr; if (size_text) { address_t value; if (expr_eval(size_text, &value) < 0) { printc_err("tracer: can't parse history size: %s\n", size_text); return NULL; } size = value; if (size < 2) { printc_err("tracer: invalid size: %d\n", size); return NULL; } } history = malloc(sizeof(history[0]) * size); if (!history) { pr_error("tracer: couldn't allocate memory for history"); return NULL; } tr = malloc(sizeof(*tr)); if (!tr) { pr_error("tracer: couldn't allocate memory"); free(history); return NULL; } memset(tr, 0, sizeof(*tr)); tr->base.type = &simio_tracer; tr->history = history; tr->size = size; tr->irq_request = -1; return (struct simio_device *)tr; } static void tracer_destroy(struct simio_device *dev) { struct tracer *tr = (struct tracer *)dev; free(tr->history); free(tr); } static void tracer_reset(struct simio_device *dev) { struct tracer *tr = (struct tracer *)dev; event_rec(tr, EVENT_RESET, 0, 0); } static int tracer_config(struct simio_device *dev, const char *param, char **arg_text) { struct tracer *tr = (struct tracer *)dev; if (!strcasecmp(param, "verbose")) tr->verbose = 1; else if (!strcasecmp(param, "quiet")) tr->verbose = 0; else if (!strcasecmp(param, "untrigger")) tr->irq_request = -1; else if (!strcasecmp(param, "clear")) { tr->head = 0; tr->tail = 0; memset(tr->cycles, 0, sizeof(tr->cycles)); tr->inscount = 0; } else if (!strcasecmp(param, "trigger")) { const char *irq_text = get_arg(arg_text); address_t value; if (!irq_text) { printc_err("tracer: trigger: must specify an IRQ " "number\n"); return -1; } if (expr_eval(irq_text, &value) < 0) { printc_err("tracer: trigger: can't parse IRQ " "number: %s\n", irq_text); return -1; } if (value >= 16) { printc_err("tracer: trigger: invalid IRQ: %d\n", value); return -1; } tr->irq_request = value; } else { printc_err("tracer: unknown config parameter: %s\n", param); return -1; } return 0; } static int tracer_info(struct simio_device *dev) { struct tracer *tr = (struct tracer *)dev; int i; printc("Instruction count: %" LLFMT "\n", tr->inscount); printc("MCLK: %" LLFMT "\n", tr->cycles[SIMIO_MCLK]); printc("SMCLK %" LLFMT "\n", tr->cycles[SIMIO_SMCLK]); printc("ACLK: %" LLFMT "\n", tr->cycles[SIMIO_ACLK]); if (tr->irq_request >= 0) printc("IRQ pending: %d\n", tr->irq_request); else printc("No IRQ is pending\n"); printc("\nIO event history (oldest first):\n"); for (i = tr->tail; i != tr->head; i = (i + 1) % tr->size) event_print(&tr->history[i]); return 0; } static int tracer_write(struct simio_device *dev, address_t addr, uint16_t data) { struct tracer *tr = (struct tracer *)dev; event_rec(tr, EVENT_WRITE_16, addr, data); return 1; } static int tracer_read(struct simio_device *dev, address_t addr, uint16_t *data) { struct tracer *tr = (struct tracer *)dev; (void)data; event_rec(tr, EVENT_READ_16, addr, 0); return 1; } static int tracer_write_b(struct simio_device *dev, address_t addr, uint8_t data) { struct tracer *tr = (struct tracer *)dev; event_rec(tr, EVENT_WRITE_8, addr, data); return 1; } static int tracer_read_b(struct simio_device *dev, address_t addr, uint8_t *data) { struct tracer *tr = (struct tracer *)dev; (void)data; event_rec(tr, EVENT_READ_8, addr, 0); return 1; } static int tracer_check_interrupt(struct simio_device *dev) { struct tracer *tr = (struct tracer *)dev; return tr->irq_request; } static void tracer_ack_interrupt(struct simio_device *dev, int irq) { struct tracer *tr = (struct tracer *)dev; if (tr->irq_request == irq) tr->irq_request = -1; event_rec(tr, EVENT_IRQ_HANDLE, irq, 0); } static void tracer_step(struct simio_device *dev, uint16_t status, const int *clocks) { struct tracer *tr = (struct tracer *)dev; int i; for (i = 0; i < SIMIO_NUM_CLOCKS; i++) tr->cycles[i] += clocks[i]; if (!(status & MSP430_SR_CPUOFF)) tr->inscount++; } const struct simio_class simio_tracer = { .name = "tracer", .help = "A debug peripheral to implement IO tracing. This will keep a record of\n" "IO activity which can be checked at any time. It can also be used to\n" "manually trigger interrupts.\n" "\n" "Constructor arguments: [history-size]\n" " If specified, enlarge the IO event history from its default size.\n" "\n" "Config arguments are:\n" " verbose\n" " Show IO events as they occur.\n" " quiet\n" " Only show IO events when requested (default).\n" " trigger \n" " Trigger an specific IRQ vector.\n" " untrigger\n" " Cancel an interrupt request.\n" " clear\n" " Clear the IO history and counter so far.\n", .create = tracer_create, .destroy = tracer_destroy, .reset = tracer_reset, .config = tracer_config, .info = tracer_info, .write = tracer_write, .read = tracer_read, .write_b = tracer_write_b, .read_b = tracer_read_b, .check_interrupt = tracer_check_interrupt, .ack_interrupt = tracer_ack_interrupt, .step = tracer_step }; mspdebug-0.25/simio/simio_tracer.h000066400000000000000000000016161313531517500172270ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef SIMIO_TRACER_H_ #define SIMIO_TRACER_H_ extern const struct simio_class simio_tracer; #endif mspdebug-0.25/simio/simio_wdt.c000066400000000000000000000137241313531517500165430ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include "simio_device.h" #include "simio_wdt.h" #include "output.h" #include "expr.h" /* WDTCTL flags, taken from mspgcc. * * Watchdog timer password. Always read as 069h. Must be written as 05Ah, * or a PUC will be generated. */ #define WDTIS0 0x0001 #define WDTIS1 0x0002 #define WDTSSEL 0x0004 #define WDTCNTCL 0x0008 #define WDTTMSEL 0x0010 #define WDTNMI 0x0020 #define WDTNMIES 0x0040 #define WDTHOLD 0x0080 #define WDTPW 0x5A00 /* Flags in IE1 */ #define WDTIE 0x01 #define NMIIE 0x10 /* Flags in IFG1 */ #define WDTIFG 0x01 #define NMIIFG 0x10 struct wdt { struct simio_device base; int pin_state; int wdt_irq; int count_reg; int reset_triggered; uint8_t wdtctl; }; struct simio_device *wdt_create(char **arg_text) { struct wdt *w = malloc(sizeof(*w)); (void)arg_text; if (!w) { pr_error("wdt: can't allocate memory"); return NULL; } memset(w, 0, sizeof(*w)); w->base.type = &simio_wdt; w->pin_state = 1; w->wdt_irq = 10; w->reset_triggered = 0; w->wdtctl = 0; w->count_reg = 0; return (struct simio_device *)w; } static void wdt_destroy(struct simio_device *dev) { free(dev); } static void wdt_reset(struct simio_device *dev) { struct wdt *w = (struct wdt *)dev; w->reset_triggered = 0; w->wdtctl = 0; w->count_reg = 0; } static int parse_int(int *val, char **arg_text) { const char *text = get_arg(arg_text); address_t value; if (!text) { printc_err("wdt: expected integer argument\n"); return -1; } if (expr_eval(text, &value) < 0) { printc_err("wdt: couldn't parse argument: %s\n", text); return -1; } *val = value; return 0; } static int wdt_config(struct simio_device *dev, const char *param, char **arg_text) { struct wdt *w = (struct wdt *)dev; if (!strcasecmp(param, "nmi")) { int old = w->pin_state; if (parse_int(&w->pin_state, arg_text) < 0) return -1; if (w->wdtctl & WDTNMI) { if (((w->wdtctl & WDTNMIES) && old && !w->pin_state) || (!(w->wdtctl & WDTNMIES) && !old && w->pin_state)) simio_sfr_modify(SIMIO_IFG1, NMIIFG, NMIIFG); } return 0; } if (!strcasecmp(param, "irq")) return parse_int(&w->wdt_irq, arg_text); printc_err("wdt: unknown configuration parameter: %s\n", param); return -1; } static int wdt_info(struct simio_device *dev) { struct wdt *w = (struct wdt *)dev; printc("Configured WDT IRQ: %d\n", w->wdt_irq); printc("WDTCTL: 0x__%02x\n", w->wdtctl); printc("NMI/RST# pin: %s\n", w->pin_state ? "HIGH" : "low"); printc("Counter: 0x%04x\n", w->count_reg); printc("Reset: %s\n", w->reset_triggered ? "TRIGGERED" : "not triggered"); return 0; } static int wdt_write(struct simio_device *dev, address_t addr, uint16_t data) { struct wdt *w = (struct wdt *)dev; if (addr != 0x120) return 1; if (data >> 8 != 0x5a) w->reset_triggered = 1; w->wdtctl = data & 0xf7; if (w->wdtctl & WDTCNTCL) w->count_reg = 0; return 0; } static int wdt_read(struct simio_device *dev, address_t addr, uint16_t *data) { struct wdt *w = (struct wdt *)dev; if (addr != 0x120) return 1; *data = 0x6900 | w->wdtctl; return 0; } static int wdt_check_interrupt(struct simio_device *dev) { struct wdt *w = (struct wdt *)dev; uint8_t flags; if (!(w->wdtctl & WDTNMI) && !w->pin_state) return 15; if (w->reset_triggered) return 15; flags = simio_sfr_get(SIMIO_IFG1) & simio_sfr_get(SIMIO_IE1); if (flags & NMIIFG) return 14; if (flags & WDTIFG) return w->wdt_irq; return -1; } static void wdt_ack_interrupt(struct simio_device *dev, int irq) { struct wdt *w = (struct wdt *)dev; if (irq == 14) simio_sfr_modify(SIMIO_IFG1, NMIIFG, 0); else if (irq == w->wdt_irq) simio_sfr_modify(SIMIO_IFG1, WDTIFG, 0); } static void wdt_step(struct simio_device *dev, uint16_t status_register, const int *clocks) { struct wdt *w = (struct wdt *)dev; int max = 1; (void)status_register; /* If on hold, nothing happens */ if (w->wdtctl & WDTHOLD) return; /* Count input clock cycles */ if (w->wdtctl & WDTSSEL) w->count_reg += clocks[SIMIO_ACLK]; else w->count_reg += clocks[SIMIO_SMCLK]; /* Figure out the divisor */ switch (w->wdtctl & 3) { case 0: max = 32768; break; case 1: max = 8192; break; case 2: max = 512; break; case 3: max = 64; break; } /* Check for overflow */ if (w->count_reg >= max) { if (w->wdtctl & WDTTMSEL) simio_sfr_modify(SIMIO_IFG1, WDTIFG, WDTIFG); else w->reset_triggered = 1; } w->count_reg &= (max - 1); } const struct simio_class simio_wdt = { .name = "wdt", .help = "This module simulates the Watchdog Timer+ peripheral. There are no\n" "constructor arguments. Configuration parameters are:\n" " irq \n" " Set the interrupt vector for the WDT interrupt.\n" " nmi <0|1>\n" " Set the state of the NMI/RST# pin.\n", .create = wdt_create, .destroy = wdt_destroy, .reset = wdt_reset, .config = wdt_config, .info = wdt_info, .write = wdt_write, .read = wdt_read, .check_interrupt = wdt_check_interrupt, .ack_interrupt = wdt_ack_interrupt, .step = wdt_step }; mspdebug-0.25/simio/simio_wdt.h000066400000000000000000000016051313531517500165430ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef SIMIO_WDT_H_ #define SIMIO_WDT_H_ extern const struct simio_class simio_wdt; #endif mspdebug-0.25/ti_3410.fw.ihex000066400000000000000000001117621313531517500156370ustar00rootroot00000000000000:10000000C2350002001E021ADBFFFFFFFFFF0232B3 :10001000CBFFFFFFFFFFFFFFFFFFFFFFFFFF0233ED :10002000767581CE90FDE88583A01234EAEC4D60B0 :100030006A78AB8003760018B89CFA787F800376E4 :100040000018B865FA78208003760018B820FA9076 :10005000FDDDAE83AF8290FBF81200A16005E4F0F5 :10006000A380F690FDE8A88290FDE8A982E8C399F4 :10007000500576000880F69000FF1200AA90010358 :100080001200AA9001071200AA90010B1200C8905A :1000900001111200C89001171200C875D000123368 :1000A000C802011DEF65827003EE658322E493F8B8 :1000B000740193F9740293FE740393F5828E83E8BE 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:1035000004F1049D04A104CD04D104990499049903 :1035100004D504B504AD04B104A904C104BD04B9C3 :1035200004C504C904A5190103002200480200488B :103530000E301420C81AD0180A0C05060203010226 :103540000001CE0181010000C00080006000300059 :1035500018001000080004000200010008183828B4 :103560000C05100A0200000000000301100A02000E :1035700000000000FBE0FBF209022700010200A0AE :10358000320904000003FF0000000705810240002B :103590000007050102400000070583030200012225 :1035A0000354005500530042003300340031003012 :1035B000002000200020002000200020002000200B :0535C000000000000006 :00000001FF mspdebug-0.25/ti_3410.fw.txt000066400000000000000000000013201313531517500155050ustar00rootroot00000000000000The file in this directory, ti_3410.fw.ihex, contains a firmware image for the TI3410 interface chip. It was obtained from sources for the Linux kernel (version 2.6.38.5). The original notes accompanying this file (found in firmware/WHENCE) read: -------------------------------------------------------------------------- Driver: ti_usb_3410_5052 -- USB TI 3410/5052 serial device File: ti_3410.fw Info: firmware 9/10/04 FW3410_Special_StartWdogOnStartPort File: ti_5052.fw Info: firmware 9/18/04 Licence: Allegedly GPLv2+, but no source visible. Marked: Copyright (C) 2004 Texas Instruments Found in hex form in kernel source. -------------------------------------------------------------------------- mspdebug-0.25/transport/000077500000000000000000000000001313531517500153065ustar00rootroot00000000000000mspdebug-0.25/transport/bslhid.c000066400000000000000000000203401313531517500167160ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2013 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef __Windows__ #include #else #include #endif #include #include #include #include "usbutil.h" #include "output.h" #include "output_util.h" #include "bslhid.h" #define BSLHID_VID 0x2047 #define BSLHID_PID 0x0200 #define BSLHID_CLASS USB_CLASS_HID #define BSLHID_XFER_SIZE 64 #define BSLHID_MTU (BSLHID_XFER_SIZE - 2) #define BSLHID_HEADER 0x3F #define BSLHID_TIMEOUT 5000 struct bslhid_transport { struct transport base; int cfg_number; int int_number; struct usb_dev_handle *handle; int in_ep; int out_ep; char bus_name[PATH_MAX + 1]; }; static int find_interface(struct bslhid_transport *tr, const struct usb_device *dev) { int c; for (c = 0; c < dev->descriptor.bNumConfigurations; c++) { const struct usb_config_descriptor *cfg = &dev->config[c]; int i; for (i = 0; i < cfg->bNumInterfaces; i++) { const struct usb_interface *intf = &cfg->interface[i]; const struct usb_interface_descriptor *desc = &intf->altsetting[0]; if (desc->bInterfaceClass == BSLHID_CLASS) { tr->cfg_number = c; tr->int_number = i; return 0; } } } printc_err("bslhid: can't find a matching interface\n"); return -1; } static int find_endpoints(struct bslhid_transport *tr, const struct usb_device *dev) { const struct usb_interface_descriptor *desc = &dev->config[tr->cfg_number].interface[tr->int_number]. altsetting[0]; int i; tr->in_ep = -1; tr->out_ep = -1; for (i = 0; i < desc->bNumEndpoints; i++) { int addr = desc->endpoint[i].bEndpointAddress; if (addr & USB_ENDPOINT_DIR_MASK) tr->in_ep = addr; else tr->out_ep = addr; } if (tr->in_ep < 0 || tr->out_ep < 0) { printc_err("bslhid: can't find suitable endpoints\n"); return -1; } return 0; } static int open_device(struct bslhid_transport *tr, struct usb_device *dev) { if (find_interface(tr, dev) < 0) return -1; printc_dbg("Opening interface %d (config %d)...\n", tr->int_number, tr->cfg_number); if (find_endpoints(tr, dev) < 0) return -1; printc_dbg("Found endpoints: IN: 0x%02x, OUT: 0x%02x\n", tr->in_ep, tr->out_ep); tr->handle = usb_open(dev); if (!tr->handle) { pr_error("bslhid: can't open device"); return -1; } #ifdef __Windows__ if (usb_set_configuration(tr->handle, tr->cfg_number) < 0) pr_error("warning: bslhid: can't set configuration"); #endif #ifdef __linux__ if (usb_detach_kernel_driver_np(tr->handle, tr->int_number) < 0) pr_error("warning: bslhid: can't detach kernel driver"); #endif if (usb_claim_interface(tr->handle, tr->int_number) < 0) { pr_error("bslhid: can't claim interface"); usb_close(tr->handle); return -1; } /* Save the bus path for a future suspend/resume */ strncpy(tr->bus_name, dev->bus->dirname, sizeof(tr->bus_name)); tr->bus_name[sizeof(tr->bus_name) - 1] = 0; return 0; } static void bslhid_destroy(transport_t base) { struct bslhid_transport *tr = (struct bslhid_transport *)base; if (tr->handle) { usb_release_interface(tr->handle, tr->int_number); usb_close(tr->handle); } free(tr); } static int bslhid_flush(transport_t base) { #ifndef __APPLE__ struct bslhid_transport *tr = (struct bslhid_transport *)base; uint8_t inbuf[BSLHID_XFER_SIZE]; if (!tr->handle) return 0; while (usb_bulk_read(tr->handle, tr->in_ep, (char *)inbuf, sizeof(inbuf), 100) > 0); #endif return 0; } static int bslhid_send(transport_t base, const uint8_t *data, int len) { struct bslhid_transport *tr = (struct bslhid_transport *)base; uint8_t outbuf[BSLHID_XFER_SIZE]; if (!tr->handle) { printc_err("bslhid: send on suspended device\n"); return -1; } memset(outbuf, 0xac, sizeof(outbuf)); if (len > BSLHID_MTU) { printc_err("bslhid: send in excess of MTU: %d\n", len); return -1; } outbuf[0] = BSLHID_HEADER; outbuf[1] = len; memcpy(outbuf + 2, data, len); #ifdef DEBUG_BSLHID debug_hexdump("bslhid_send", outbuf, sizeof(outbuf)); #endif if (usb_bulk_write(tr->handle, tr->out_ep, (char *)outbuf, sizeof(outbuf), BSLHID_TIMEOUT) < 0) { printc_err("bslhid: usb_bulk_write: %s\n", usb_strerror()); return -1; } return 0; } static int bslhid_recv(transport_t base, uint8_t *data, int max_len) { struct bslhid_transport *tr = (struct bslhid_transport *)base; uint8_t inbuf[BSLHID_XFER_SIZE]; int r; int len; if (!tr->handle) { printc_err("bslhid: recv on suspended device\n"); return -1; } r = usb_bulk_read(tr->handle, tr->in_ep, (char *)inbuf, sizeof(inbuf), BSLHID_TIMEOUT); if (r <= 0) { printc_err("bslhid_recv: usb_bulk_read: %s\n", usb_strerror()); return -1; } #ifdef DEBUG_BSLHID debug_hexdump("bslhid_recv", inbuf, r); #endif if (r < 2) { printc_err("bslhid_recv: short transfer\n"); return -1; } if (inbuf[0] != BSLHID_HEADER) { printc_err("bslhid_recv: missing transfer header\n"); return -1; } len = inbuf[1]; if ((len > max_len) || (len + 2 > r)) { printc_err("bslhid_recv: bad length: %d (%d byte transfer)\n", len, r); return -1; } memcpy(data, inbuf + 2, len); return len; } static int bslhid_set_modem(transport_t base, transport_modem_t state) { printc_err("bslhid: unsupported operation: set_modem\n"); return -1; } static int bslhid_suspend(transport_t base) { struct bslhid_transport *tr = (struct bslhid_transport *)base; if (tr->handle) { usb_release_interface(tr->handle, tr->int_number); usb_close(tr->handle); tr->handle = NULL; } return 0; } static struct usb_bus *find_by_name(const char *name) { struct usb_bus *b; for (b = usb_get_busses(); b; b = b->next) if (!strcmp(name, b->dirname)) return b; return NULL; } static struct usb_device *find_first_bsl(struct usb_bus *bus) { struct usb_device *d; for (d = bus->devices; d; d = d->next) if ((d->descriptor.idVendor == BSLHID_VID) && (d->descriptor.idProduct == BSLHID_PID)) return d; return NULL; } static int bslhid_resume(transport_t base) { struct bslhid_transport *tr = (struct bslhid_transport *)base; struct usb_bus *bus; struct usb_device *dev; if (tr->handle) return 0; usb_init(); usb_find_busses(); usb_find_devices(); bus = find_by_name(tr->bus_name); if (!bus) { printc_err("bslhid: can't find bus to resume from\n"); return -1; } /* We can't portably distinguish physical locations, so this * will have to do. */ dev = find_first_bsl(bus); if (!dev) { printc_err("bslhid: can't find a BSL HID on this bus\n"); return -1; } if (open_device(tr, dev) < 0) { printc_err("bslhid: failed to resume BSL HID device\n"); return -1; } return 0; } static const struct transport_class bslhid_transport_class = { .destroy = bslhid_destroy, .send = bslhid_send, .recv = bslhid_recv, .flush = bslhid_flush, .set_modem = bslhid_set_modem, .suspend = bslhid_suspend, .resume = bslhid_resume }; transport_t bslhid_open(const char *dev_path, const char *requested_serial) { struct bslhid_transport *tr = malloc(sizeof(*tr)); struct usb_device *dev; if (!tr) { pr_error("bslhid: can't allocate memory"); return NULL; } memset(tr, 0, sizeof(*tr)); tr->base.ops = &bslhid_transport_class; usb_init(); usb_find_busses(); usb_find_devices(); if (dev_path) dev = usbutil_find_by_loc(dev_path); else dev = usbutil_find_by_id(BSLHID_VID, BSLHID_PID, requested_serial); if (!dev) { free(tr); return NULL; } if (open_device(tr, dev) < 0) { printc_err("bslhid: failed to open BSL HID device\n"); free(tr); return NULL; } bslhid_flush(&tr->base); return &tr->base; } mspdebug-0.25/transport/bslhid.h000066400000000000000000000023321313531517500167240ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2013 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef BSLHID_H_ #define BSLHID_H_ #include "transport.h" /* Open a USB HID device used to wrap the USB bootstrap loader serial * protocol. The interface is described in SLAU319C: "MSP430 Programming * via the Bootstrap Loader". */ #if defined(__APPLE__) transport_t bslosx_open(const char *dev_path, const char *requested_serial); #else transport_t bslhid_open(const char *dev_path, const char *requested_serial); #endif #endif mspdebug-0.25/transport/bslosx.c000066400000000000000000000151341313531517500167700ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2013 Daniel Beer * Copyright (C) 2016 Hiroki Mori * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include #include #include #include #include "usbutil.h" #include "output.h" #include "output_util.h" #include "bslhid.h" #define BSLHID_VID 0x2047 #define BSLHID_PID 0x0200 #define BSLHID_CLASS USB_CLASS_HID #define BSLHID_XFER_SIZE 64 #define BSLHID_MTU (BSLHID_XFER_SIZE - 2) #define BSLHID_HEADER 0x3F #define BSLHID_TIMEOUT 5000 struct bslosx_transport { struct transport base; int cfg_number; int int_number; IOHIDDeviceRef refDevice; char bus_name[PATH_MAX + 1]; }; static void bslosx_destroy(transport_t base) { struct bslosx_transport *tr = (struct bslosx_transport *)base; if (tr->refDevice) { IOHIDDeviceClose(tr->refDevice, kIOHIDOptionsTypeNone); } free(tr); } static int bslosx_flush(transport_t base) { return 0; } static int bslosx_send(transport_t base, const uint8_t *data, int len) { struct bslosx_transport *tr = (struct bslosx_transport *)base; uint8_t outbuf[BSLHID_XFER_SIZE]; if (!tr->refDevice) { printc_err("bslosx: send on suspended device\n"); return -1; } memset(outbuf, 0xac, sizeof(outbuf)); if (len > BSLHID_MTU) { printc_err("bslosx: send in excess of MTU: %d\n", len); return -1; } outbuf[0] = BSLHID_HEADER; outbuf[1] = len; memcpy(outbuf + 2, data, len); #ifdef DEBUG_BSLHID debug_hexdump("bslosx_send", outbuf, sizeof(outbuf)); #endif IOReturn ret = IOHIDDeviceSetReport(tr->refDevice, kIOHIDReportTypeOutput, 0, outbuf, BSLHID_XFER_SIZE); return 0; } static int g_readBytes; static void reportCallback(void *inContext, IOReturn inResult, void *inSender, IOHIDReportType inType, uint32_t inReportID, uint8_t *inReport, CFIndex InReportLength) { g_readBytes = InReportLength; } static int bslosx_recv(transport_t base, uint8_t *data, int max_len) { struct bslosx_transport *tr = (struct bslosx_transport *)base; uint8_t inbuf[BSLHID_XFER_SIZE]; int r; int len; if (!tr->refDevice) { printc_err("bslosx: recv on suspended device\n"); return -1; } IOHIDDeviceRegisterInputReportCallback(tr->refDevice, &inbuf, BSLHID_XFER_SIZE, reportCallback, NULL); g_readBytes = -1; CFRunLoopRunInMode(kCFRunLoopDefaultMode, 1, false); r = g_readBytes; if (r <= 0) { printc_err("bslosx_recv: usb_bulk_read no data\n"); return -1; } #ifdef DEBUG_BSLHID debug_hexdump("bslosx_recv", inbuf, r); #endif if (r < 2) { printc_err("bslosx_recv: short transfer\n"); return -1; } if (inbuf[0] != BSLHID_HEADER) { printc_err("bslosx_recv: missing transfer header\n"); return -1; } len = inbuf[1]; if ((len > max_len) || (len + 2 > r)) { printc_err("bslosx_recv: bad length: %d (%d byte transfer)\n", len, r); return -1; } memcpy(data, inbuf + 2, len); return len; } static int bslosx_set_modem(transport_t base, transport_modem_t state) { printc_err("bslosx: unsupported operation: set_modem\n"); return -1; } static int bslosx_suspend(transport_t base) { struct bslosx_transport *tr = (struct bslosx_transport *)base; if (tr->refDevice) { IOHIDDeviceClose(tr->refDevice, kIOHIDOptionsTypeNone); tr->refDevice = NULL; } return 0; } static struct usb_bus *find_by_name(const char *name) { struct usb_bus *b; for (b = usb_get_busses(); b; b = b->next) if (!strcmp(name, b->dirname)) return b; return NULL; } static struct usb_device *find_first_bsl(struct usb_bus *bus) { struct usb_device *d; for (d = bus->devices; d; d = d->next) if ((d->descriptor.idVendor == BSLHID_VID) && (d->descriptor.idProduct == BSLHID_PID)) return d; return NULL; } static int bslosx_resume(transport_t base) { return 0; } static const struct transport_class bslosx_transport_class = { .destroy = bslosx_destroy, .send = bslosx_send, .recv = bslosx_recv, .flush = bslosx_flush, .set_modem = bslosx_set_modem, .suspend = bslosx_suspend, .resume = bslosx_resume }; int getIntProperty(IOHIDDeviceRef inIOHIDDeviceRef, CFStringRef inKey) { int val; if (inIOHIDDeviceRef) { CFTypeRef tCFTypeRef = IOHIDDeviceGetProperty(inIOHIDDeviceRef, inKey); if (tCFTypeRef) { if (CFNumberGetTypeID() == CFGetTypeID(tCFTypeRef)) { if (!CFNumberGetValue( (CFNumberRef) tCFTypeRef, kCFNumberSInt32Type, &val)) { val = -1; } } } } return val; } transport_t bslosx_open(const char *dev_path, const char *requested_serial) { struct bslosx_transport *tr = malloc(sizeof(*tr)); if (!tr) { pr_error("bslosx: can't allocate memory"); return NULL; } memset(tr, 0, sizeof(*tr)); IOHIDDeviceRef refDevice; IOHIDManagerRef refHidMgr = NULL; CFSetRef refDevSet = NULL; IOHIDDeviceRef *prefDevs = NULL; int i; int vid, pid; CFIndex numDevices; IOReturn ret; refHidMgr = IOHIDManagerCreate(kCFAllocatorDefault, kIOHIDOptionsTypeNone); IOHIDManagerSetDeviceMatching(refHidMgr, NULL); IOHIDManagerScheduleWithRunLoop(refHidMgr, CFRunLoopGetCurrent(), kCFRunLoopDefaultMode); IOHIDManagerOpen(refHidMgr, kIOHIDOptionsTypeNone); refDevSet = IOHIDManagerCopyDevices(refHidMgr); numDevices = CFSetGetCount(refDevSet); prefDevs = malloc(numDevices * sizeof(IOHIDDeviceRef)); CFSetGetValues(refDevSet, (const void **)prefDevs); for (i = 0; i < numDevices; i++) { refDevice = prefDevs[i]; vid = getIntProperty(refDevice, CFSTR(kIOHIDVendorIDKey)); pid = getIntProperty(refDevice, CFSTR(kIOHIDProductIDKey)); if (vid == BSLHID_VID && pid == BSLHID_PID) { break; } } if (!refDevice) { free(tr); return NULL; } ret = IOHIDDeviceOpen(refDevice, kIOHIDOptionsTypeNone); if (ret != kIOReturnSuccess) { printc_err("bslosx: failed to open BSL HID device\n"); free(tr); return NULL; } tr->base.ops = &bslosx_transport_class; tr->refDevice = refDevice; strcpy(tr->bus_name, "macosxhid"); bslosx_flush(&tr->base); return &tr->base; } mspdebug-0.25/transport/cdc_acm.c000066400000000000000000000166501313531517500170330ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009-2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #ifndef __Windows__ #include #else #include #endif #include "cdc_acm.h" #include "util.h" #include "usbutil.h" #include "output.h" #define READ_BUFFER_SIZE 1024 struct cdc_acm_transport { struct transport base; int int_number; struct usb_dev_handle *handle; int in_ep; int out_ep; /* We have to implement an intermediate read buffer, because * some interfaces are buggy and don't like single-byte reads. */ int rbuf_len; int rbuf_ptr; char rbuf[READ_BUFFER_SIZE]; }; #define CDC_INTERFACE_CLASS 10 #define TIMEOUT 30000 /* CDC requests */ #define CDC_REQTYPE_HOST_TO_DEVICE 0x21 #define CDC_SET_CONTROL 0x22 #define CDC_SET_LINE_CODING 0x20 /* Modem control line bitmask */ #define CDC_CTRL_DTR 0x01 #define CDC_CTRL_RTS 0x02 static int usbtr_send(transport_t tr_base, const uint8_t *data, int len) { struct cdc_acm_transport *tr = (struct cdc_acm_transport *)tr_base; int sent; #ifdef DEBUG_CDC_ACM debug_hexdump(__FILE__ ": USB transfer out", data, len); #endif while (len) { sent = usb_bulk_write(tr->handle, tr->out_ep, (char *)data, len, TIMEOUT); if (sent <= 0) { pr_error(__FILE__": can't send data"); return -1; } data += sent; len -= sent; } return 0; } static int usbtr_recv(transport_t tr_base, uint8_t *databuf, int len) { struct cdc_acm_transport *tr = (struct cdc_acm_transport *)tr_base; if (tr->rbuf_ptr >= tr->rbuf_len) { tr->rbuf_ptr = 0; tr->rbuf_len = usb_bulk_read(tr->handle, tr->in_ep, tr->rbuf, sizeof(tr->rbuf), TIMEOUT); if (tr->rbuf_len <= 0) { pr_error(__FILE__": can't receive data"); return -1; } #ifdef DEBUG_CDC_ACM debug_hexdump(__FILE__": USB transfer in", (uint8_t *)tr->rbuf, tr->rbuf_len); #endif } if (tr->rbuf_ptr + len > tr->rbuf_len) len = tr->rbuf_len - tr->rbuf_ptr; memcpy(databuf, tr->rbuf + tr->rbuf_ptr, len); tr->rbuf_ptr += len; return len; } static void usbtr_destroy(transport_t tr_base) { struct cdc_acm_transport *tr = (struct cdc_acm_transport *)tr_base; usb_release_interface(tr->handle, tr->int_number); usb_close(tr->handle); free(tr); } static int usbtr_flush(transport_t tr_base) { struct cdc_acm_transport *tr = (struct cdc_acm_transport *)tr_base; char buf[64]; /* Flush out lingering data */ while (usb_bulk_read(tr->handle, tr->in_ep, buf, sizeof(buf), 100) > 0); tr->rbuf_len = 0; tr->rbuf_ptr = 0; return 0; } static int usbtr_set_modem(transport_t tr_base, transport_modem_t state) { struct cdc_acm_transport *tr = (struct cdc_acm_transport *)tr_base; int value = 0; if (state & TRANSPORT_MODEM_DTR) value |= CDC_CTRL_DTR; if (state & TRANSPORT_MODEM_RTS) value |= CDC_CTRL_RTS; #ifdef DEBUG_CDC_ACM printc(__FILE__": modem ctrl = 0x%x\n", value); #endif if (usb_control_msg(tr->handle, CDC_REQTYPE_HOST_TO_DEVICE, CDC_SET_CONTROL, value, 0, NULL, 0, 300) < 0) { pr_error("cdc_acm: failed to set modem control lines\n"); return -1; } return 0; } static const struct transport_class cdc_acm_class = { .destroy = usbtr_destroy, .send = usbtr_send, .recv = usbtr_recv, .flush = usbtr_flush, .set_modem = usbtr_set_modem }; static int find_interface(struct cdc_acm_transport *tr, struct usb_device *dev) { struct usb_config_descriptor *c = &dev->config[0]; int i; for (i = 0; i < c->bNumInterfaces; i++) { struct usb_interface *intf = &c->interface[i]; struct usb_interface_descriptor *desc = &intf->altsetting[0]; int j; if (desc->bInterfaceClass != CDC_INTERFACE_CLASS) continue; /* Look for bulk in/out endpoints */ tr->in_ep = -1; tr->out_ep = -1; for (j = 0; j < desc->bNumEndpoints; j++) { struct usb_endpoint_descriptor *ep = &desc->endpoint[j]; const int type = ep->bmAttributes & USB_ENDPOINT_TYPE_MASK; const int addr = ep->bEndpointAddress; if (type != USB_ENDPOINT_TYPE_BULK) continue; if (addr & USB_ENDPOINT_DIR_MASK) tr->in_ep = addr; else tr->out_ep = addr; } if (tr->in_ep >= 0 && tr->out_ep >= 0) { tr->int_number = i; return 0; } } return -1; } static int open_interface(struct cdc_acm_transport *tr, struct usb_device *dev) { #if defined(__linux__) int drv; char drName[256]; #endif tr->handle = usb_open(dev); if (!tr->handle) { pr_error(__FILE__": can't open device"); return -1; } #if defined(__linux__) drv = usb_get_driver_np(tr->handle, tr->int_number, drName, sizeof(drName)); if (drv >= 0) { if (usb_detach_kernel_driver_np(tr->handle, tr->int_number) < 0) pr_error(__FILE__": warning: can't detach " "kernel driver"); } #endif if (usb_claim_interface(tr->handle, tr->int_number) < 0) { pr_error(__FILE__": can't claim interface"); usb_close(tr->handle); return -1; } return 0; } static int configure_port(struct cdc_acm_transport *tr, int baud_rate) { uint8_t line_coding[7]; line_coding[0] = baud_rate & 0xff; line_coding[1] = (baud_rate >> 8) & 0xff; line_coding[2] = (baud_rate >> 16) & 0xff; line_coding[3] = (baud_rate >> 24) & 0xff; line_coding[4] = 0; /* 1 stop bit */ line_coding[5] = 0; /* no parity */ line_coding[6] = 8; /* 8 data bits */ if (usb_control_msg(tr->handle, CDC_REQTYPE_HOST_TO_DEVICE, CDC_SET_LINE_CODING, 0, 0, (char *)line_coding, 7, 300) < 0) { pr_error("cdc_acm: failed to set line coding\n"); return -1; } if (usb_control_msg(tr->handle, CDC_REQTYPE_HOST_TO_DEVICE, CDC_SET_CONTROL, 0, 0, NULL, 0, 300) < 0) { pr_error("cdc_acm: failed to set modem control lines\n"); return -1; } return 0; } transport_t cdc_acm_open(const char *devpath, const char *requested_serial, int baud_rate, uint16_t vendor, uint16_t product) { struct cdc_acm_transport *tr = malloc(sizeof(*tr)); struct usb_device *dev; if (!tr) { pr_error(__FILE__": can't allocate memory"); return NULL; } memset(tr, 0, sizeof(*tr)); tr->base.ops = &cdc_acm_class; usb_init(); usb_find_busses(); usb_find_devices(); if (devpath) dev = usbutil_find_by_loc(devpath); else dev = usbutil_find_by_id(vendor, product, requested_serial); if (!dev) { free(tr); return NULL; } if (find_interface(tr, dev) < 0) { printc_err(__FILE__ ": failed to locate CDC-ACM interface\n"); free(tr); return NULL; } if (open_interface(tr, dev) < 0) { printc_err(__FILE__": failed to open interface\n"); free(tr); return NULL; } if (configure_port(tr, baud_rate) < 0) { usb_release_interface(tr->handle, tr->int_number); usb_close(tr->handle); free(tr); return NULL; } usbtr_flush(&tr->base); return (transport_t)tr; } mspdebug-0.25/transport/cdc_acm.h000066400000000000000000000023241313531517500170310ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * Copyright (C) 2010 Peter Jansen * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef CDC_ACM_H_ #define CDC_ACM_H_ #include "transport.h" /* Search the USB bus for the first CDC-ACM device, and initialize it. * If successful, return a valid transport object. * * A particular USB device may be specified in bus:dev form. */ transport_t cdc_acm_open(const char *usb_device, const char *requested_serial, int baud_rate, uint16_t product, uint16_t vendor); #endif mspdebug-0.25/transport/comport.c000066400000000000000000000065741313531517500171510ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009-2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include #include #include #include "comport.h" #include "util.h" #include "output.h" #include "sport.h" struct comport_transport { struct transport base; sport_t serial_fd; }; static int serial_send(transport_t tr_base, const uint8_t *data, int len) { struct comport_transport *tr = (struct comport_transport *)tr_base; #ifdef DEBUG_SERIAL debug_hexdump("Serial transfer out:", data, len); #endif if (sport_write_all(tr->serial_fd, data, len) < 0) { pr_error("comport: write error"); return -1; } return 0; } static int serial_recv(transport_t tr_base, uint8_t *data, int max_len) { struct comport_transport *tr = (struct comport_transport *)tr_base; int r; r = sport_read(tr->serial_fd, data, max_len); if (r < 0) { pr_error("comport: read error"); return -1; } #ifdef DEBUG_SERIAL debug_hexdump("Serial transfer in", data, r); #endif return r; } static void serial_destroy(transport_t tr_base) { struct comport_transport *tr = (struct comport_transport *)tr_base; sport_close(tr->serial_fd); free(tr); } static int serial_flush(transport_t tr_base) { struct comport_transport *tr = (struct comport_transport *)tr_base; if (sport_flush(tr->serial_fd) < 0) { pr_error("comport: flush failed"); return -1; } return 0; } static int serial_set_modem(transport_t tr_base, transport_modem_t state) { struct comport_transport *tr = (struct comport_transport *)tr_base; int bits = 0; if (state & TRANSPORT_MODEM_DTR) bits |= SPORT_MC_DTR; if (state & TRANSPORT_MODEM_RTS) bits |= SPORT_MC_RTS; if (sport_set_modem(tr->serial_fd, bits) < 0) { pr_error("comport: failed to set modem control lines\n"); return -1; } return 0; } static const struct transport_class comport_transport = { .destroy = serial_destroy, .send = serial_send, .recv = serial_recv, .flush = serial_flush, .set_modem = serial_set_modem }; transport_t comport_open(const char *device, int baud_rate) { struct comport_transport *tr = malloc(sizeof(*tr)); if (!tr) { pr_error("comport: couldn't allocate memory"); return NULL; } tr->base.ops = &comport_transport; printc_dbg("Trying to open %s at %d bps...\n", device, baud_rate); tr->serial_fd = sport_open(device, baud_rate, 0); if (SPORT_ISERR(tr->serial_fd)) { printc_err("comport: can't open serial device: %s: %s\n", device, last_error()); free(tr); return NULL; } if (sport_set_modem(tr->serial_fd, 0) < 0) pr_error("warning: comport: failed to set " "modem control lines"); return (transport_t)tr; } mspdebug-0.25/transport/comport.h000066400000000000000000000021301313531517500171360ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef COMPORT_H_ #define COMPORT_H_ #include "transport.h" /* This function is for opening a system serial device. The argument * given should be the filename of the relevant tty device (POSIX) or a * COM port name (Windows). */ transport_t comport_open(const char *device, int baud_rate); #endif mspdebug-0.25/transport/cp210x.c000066400000000000000000000201751313531517500164740ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009-2012 Daniel Beer * Copyright (C) 2010 Peter Jansen * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #ifndef __Windows__ #include #else #include #endif #include #include "cp210x.h" #include "util.h" #include "usbutil.h" #include "output.h" struct cp210x_transport { struct transport base; struct usb_dev_handle *handle; int int_number; }; /********************************************************************* * USB transport * * These functions handle the details of slicing data over USB * transfers. The interface presented is a continuous byte stream with * no slicing codes. * * Writes are unbuffered -- a single write translates to at least * one transfer. */ #define CP210X_CLOCK 3500000 #define V1_INTERFACE_CLASS 255 #define V1_IN_EP 0x81 #define V1_OUT_EP 0x01 #define CP210x_REQTYPE_HOST_TO_DEVICE 0x41 #define CP210X_IFC_ENABLE 0x00 #define CP210X_SET_BAUDDIV 0x01 #define CP210X_SET_MHS 0x07 /* CP210X_(SET_MHS|GET_MDMSTS) */ #define CP210X_DTR 0x0001 #define CP210X_RTS 0x0002 #define CP210X_CTS 0x0010 #define CP210X_DSR 0x0020 #define CP210X_RING 0x0040 #define CP210X_DCD 0x0080 #define CP210X_WRITE_DTR 0x0100 #define CP210X_WRITE_RTS 0x0200 #define TIMEOUT_S 30 static int configure_port(struct cp210x_transport *tr, int baud_rate) { int ret; ret = usb_control_msg(tr->handle, CP210x_REQTYPE_HOST_TO_DEVICE, CP210X_IFC_ENABLE, 0x1, 0, NULL, 0, 300); #ifdef DEBUG_CP210X printc("%s: %s: Sending control message " "CP210x_REQTYPE_HOST_TO_DEVICE, ret = %d\n", __FILE__, __FUNCTION__, ret); #endif if (ret < 0) { pr_error(__FILE__": can't enable CP210x UART"); return -1; } /* Set the baud rate to 500000 bps */ ret = usb_control_msg(tr->handle, CP210x_REQTYPE_HOST_TO_DEVICE, CP210X_SET_BAUDDIV, CP210X_CLOCK / baud_rate, 0, NULL, 0, 300); #ifdef DEBUG_CP210X printc("%s: %s: Sending control message " "CP210X_SET_BAUDDIV, ret = %d\n", __FILE__, __FUNCTION__, ret); #endif if (ret < 0) { pr_error(__FILE__": can't set baud rate"); return -1; } /* Set the modem control settings. * Clear RTS, DTR and WRITE_DTR, WRITE_RTS */ ret = usb_control_msg(tr->handle, CP210x_REQTYPE_HOST_TO_DEVICE, CP210X_SET_MHS, 0x303, 0, NULL, 0, 300); #ifdef DEBUG_CP210X printc("%s: %s: Sending control message " "CP210X_SET_MHS, ret %d\n", __FILE__, __FUNCTION__, ret); #endif if (ret < 0) { pr_error(__FILE__": can't set modem control"); return -1; } return 0; } static int open_interface(struct cp210x_transport *tr, struct usb_device *dev, int ino, int baud_rate) { #if defined(__linux__) int drv; char drName[256]; #endif printc_dbg(__FILE__": Trying to open interface %d on %s\n", ino, dev->filename); tr->int_number = ino; tr->handle = usb_open(dev); if (!tr->handle) { pr_error(__FILE__": can't open device"); return -1; } #if defined(__linux__) drv = usb_get_driver_np(tr->handle, tr->int_number, drName, sizeof(drName)); printc(__FILE__" : driver %d\n", drv); if (drv >= 0) { if (usb_detach_kernel_driver_np(tr->handle, tr->int_number) < 0) pr_error(__FILE__": warning: can't detach " "kernel driver"); } #endif #ifdef __Windows__ if (usb_set_configuration(tr->handle, 1) < 0) { pr_error(__FILE__": can't set configuration 1"); usb_close(tr->handle); return -1; } #endif if (usb_claim_interface(tr->handle, tr->int_number) < 0) { pr_error(__FILE__": can't claim interface"); usb_close(tr->handle); return -1; } if (configure_port(tr, baud_rate) < 0) { printc_err("Failed to configure for V1 device\n"); usb_close(tr->handle); return -1; } return 0; } static int open_device(struct cp210x_transport *tr, struct usb_device *dev, int baud_rate) { struct usb_config_descriptor *c = &dev->config[0]; int i; for (i = 0; i < c->bNumInterfaces; i++) { struct usb_interface *intf = &c->interface[i]; struct usb_interface_descriptor *desc = &intf->altsetting[0]; if (desc->bInterfaceClass == V1_INTERFACE_CLASS && !open_interface(tr, dev, desc->bInterfaceNumber, baud_rate)) return 0; } return -1; } static int usbtr_send(transport_t tr_base, const uint8_t *data, int len) { struct cp210x_transport *tr = (struct cp210x_transport *)tr_base; int sent; #ifdef DEBUG_CP210X debug_hexdump(__FILE__ ": USB transfer out", data, len); #endif while (len) { sent = usb_bulk_write(tr->handle, V1_OUT_EP, (char *)data, len, TIMEOUT_S * 1000); if (sent <= 0) { pr_error(__FILE__": can't send data"); return -1; } data += sent; len -= sent; } return 0; } static int usbtr_recv(transport_t tr_base, uint8_t *databuf, int max_len) { struct cp210x_transport *tr = (struct cp210x_transport *)tr_base; int rlen; time_t deadline = time(NULL) + TIMEOUT_S; #ifdef DEBUG_CP210X printc(__FILE__": %s : read max %d\n", __FUNCTION__, max_len); #endif while (time(NULL) < deadline) { rlen = usb_bulk_read(tr->handle, V1_IN_EP, (char *)databuf, max_len, TIMEOUT_S * 1000); #ifdef DEBUG_CP210X printc(__FILE__": %s : read %d\n", __FUNCTION__, rlen); #endif if (rlen < 0) { pr_error(__FILE__": can't receive data"); return -1; } if (rlen > 0) { #ifdef DEBUG_CP210X debug_hexdump(__FILE__": USB transfer in", databuf, rlen); #endif return rlen; } } pr_error(__FILE__": read operation timed out"); return -1; } static void usbtr_destroy(transport_t tr_base) { struct cp210x_transport *tr = (struct cp210x_transport *)tr_base; usb_release_interface(tr->handle, tr->int_number); usb_close(tr->handle); free(tr); } static int usbtr_flush(transport_t tr_base) { struct cp210x_transport *tr = (struct cp210x_transport *)tr_base; char buf[64]; /* Flush out lingering data */ while (usb_bulk_read(tr->handle, V1_IN_EP, buf, sizeof(buf), 100) > 0); return 0; } static int usbtr_set_modem(transport_t tr_base, transport_modem_t state) { struct cp210x_transport *tr = (struct cp210x_transport *)tr_base; int value = CP210X_WRITE_DTR | CP210X_WRITE_RTS; /* DTR and RTS bits are active-low for this device */ if (!(state & TRANSPORT_MODEM_DTR)) value |= CP210X_DTR; if (!(state & TRANSPORT_MODEM_RTS)) value |= CP210X_RTS; if (usb_control_msg(tr->handle, CP210x_REQTYPE_HOST_TO_DEVICE, CP210X_SET_MHS, value, 0, NULL, 0, 300) < 0) { pr_error("cp210x: failed to set modem control lines\n"); return -1; } return 0; } static const struct transport_class cp210x_class = { .destroy = usbtr_destroy, .send = usbtr_send, .recv = usbtr_recv, .flush = usbtr_flush, .set_modem = usbtr_set_modem }; transport_t cp210x_open(const char *devpath, const char *requested_serial, int baud_rate, uint16_t product, uint16_t vendor) { struct cp210x_transport *tr = malloc(sizeof(*tr)); struct usb_device *dev; if (!tr) { pr_error(__FILE__": can't allocate memory"); return NULL; } tr->base.ops = &cp210x_class; usb_init(); usb_find_busses(); usb_find_devices(); if (devpath) dev = usbutil_find_by_loc(devpath); else dev = usbutil_find_by_id(product, vendor, requested_serial); if (!dev) { free(tr); return NULL; } if (open_device(tr, dev, baud_rate) < 0) { printc_err(__FILE__ ": failed to open CP210X device\n"); free(tr); return NULL; } usbtr_flush(&tr->base); return (transport_t)tr; } mspdebug-0.25/transport/cp210x.h000066400000000000000000000023151313531517500164750ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * Copyright (C) 2010 Peter Jansen * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef CP210X_H_ #define CP210X_H_ #include "transport.h" /* Search the USB bus for the first CP210x device, and initialize it. If * successful, a valid transport is returned. * * A particular USB device may be specified in bus:dev form. */ transport_t cp210x_open(const char *usb_device, const char *requested_serial, int baud_rate, uint16_t product, uint16_t vendor); #endif mspdebug-0.25/transport/ftdi.c000066400000000000000000000165671313531517500164170ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include "ftdi.h" #include "util.h" #include "usbutil.h" #include "output.h" struct ftdi_transport { struct transport base; struct usb_dev_handle *handle; }; #define USB_INTERFACE 0 #define USB_CONFIG 1 #define EP_IN 0x81 #define EP_OUT 0x02 #define TIMEOUT_S 30 #define REQ_TIMEOUT_MS 100 #define REQTYPE_HOST_TO_DEVICE 0x40 #define FTDI_SIO_RESET 0 /* Reset the port */ #define FTDI_SIO_MODEM_CTRL 1 /* Set the modem control register */ #define FTDI_SIO_SET_FLOW_CTRL 2 /* Set flow control register */ #define FTDI_SIO_SET_BAUD_RATE 3 /* Set baud rate */ #define FTDI_SIO_SET_DATA 4 /* Set the data characteristics of the port */ #define FTDI_SIO_GET_MODEM_STATUS 5 /* Retrieve current value of modem status register */ #define FTDI_SIO_SET_EVENT_CHAR 6 /* Set the event character */ #define FTDI_SIO_SET_ERROR_CHAR 7 /* Set the error character */ #define FTDI_SIO_SET_LATENCY_TIMER 9 /* Set the latency timer */ #define FTDI_SIO_GET_LATENCY_TIMER 10 /* Get the latency timer */ #define FTDI_SIO_RESET_SIO 0 #define FTDI_SIO_RESET_PURGE_RX 1 #define FTDI_SIO_RESET_PURGE_TX 2 #define FTDI_PACKET_SIZE 64 #define FTDI_CLOCK 3000000 #define FTDI_DTR 0x0001 #define FTDI_RTS 0x0002 #define FTDI_WRITE_DTR 0x0100 #define FTDI_WRITE_RTS 0x0200 static int do_cfg(struct usb_dev_handle *handle, const char *what, int request, int value) { if (usb_control_msg(handle, REQTYPE_HOST_TO_DEVICE, request, value, 0, NULL, 0, REQ_TIMEOUT_MS)) { printc_err("ftdi: %s failed: %s\n", what, usb_strerror()); return -1; } return 0; } int configure_ftdi(struct usb_dev_handle *h, int baud_rate) { if (do_cfg(h, "reset FTDI", FTDI_SIO_RESET, FTDI_SIO_RESET_SIO) < 0 || do_cfg(h, "set data characteristics", FTDI_SIO_SET_DATA, 8) < 0 || do_cfg(h, "disable flow control", FTDI_SIO_SET_FLOW_CTRL, 0) < 0 || do_cfg(h, "set modem control lines", FTDI_SIO_MODEM_CTRL, 0x303) < 0 || do_cfg(h, "set baud rate", FTDI_SIO_SET_BAUD_RATE, FTDI_CLOCK / baud_rate) < 0 || do_cfg(h, "set latency timer", FTDI_SIO_SET_LATENCY_TIMER, 50) < 0 || do_cfg(h, "purge TX", FTDI_SIO_RESET, FTDI_SIO_RESET_PURGE_TX) < 0 || do_cfg(h, "purge RX", FTDI_SIO_RESET, FTDI_SIO_RESET_PURGE_RX) < 0) return -1; return 0; } static int open_device(struct ftdi_transport *tr, struct usb_device *dev, int baud_rate) { #ifdef __linux__ int driver; char drv_name[128]; #endif printc_dbg("ftdi: trying to open %s\n", dev->filename); tr->handle = usb_open(dev); if (!tr->handle) { printc_err("ftdi: can't open device: %s\n", usb_strerror()); return -1; } #ifdef __linux__ driver = usb_get_driver_np(tr->handle, USB_INTERFACE, drv_name, sizeof(drv_name)); if (driver >= 0) { printc_dbg("Detaching kernel driver \"%s\"\n", drv_name); if (usb_detach_kernel_driver_np(tr->handle, USB_INTERFACE) < 0) printc_err("warning: ftdi: can't detach " "kernel driver: %s\n", usb_strerror()); } #endif #ifdef __Windows__ if (usb_set_configuration(tr->handle, USB_CONFIG) < 0) { printc_err("ftdi: can't set configuration: %s\n", usb_strerror()); usb_close(tr->handle); return -1; } #endif if (usb_claim_interface(tr->handle, USB_INTERFACE) < 0) { printc_err("ftdi: can't claim interface: %s\n", usb_strerror()); usb_close(tr->handle); return -1; } if (configure_ftdi(tr->handle, baud_rate) < 0) { printc_err("ftdi: failed to configure device: %s\n", usb_strerror()); usb_close(tr->handle); return -1; } return 0; } static void tr_destroy(transport_t tr_base) { struct ftdi_transport *tr = (struct ftdi_transport *)tr_base; usb_close(tr->handle); free(tr); } static int tr_recv(transport_t tr_base, uint8_t *databuf, int max_len) { struct ftdi_transport *tr = (struct ftdi_transport *)tr_base; time_t deadline = time(NULL) + TIMEOUT_S; char tmpbuf[FTDI_PACKET_SIZE]; if (max_len > FTDI_PACKET_SIZE - 2) max_len = FTDI_PACKET_SIZE - 2; while(time(NULL) < deadline) { int r = usb_bulk_read(tr->handle, EP_IN, tmpbuf, max_len + 2, TIMEOUT_S * 1000); if (r <= 0) { printc_err("ftdi: usb_bulk_read: %s\n", usb_strerror()); return -1; } if (r > 2) { memcpy(databuf, tmpbuf + 2, r - 2); #ifdef DEBUG_OLIMEX_ISO printc_dbg("ftdi: tr_recv: flags = %02x %02x\n", tmpbuf[0], tmpbuf[1]); debug_hexdump("ftdi: tr_recv", databuf, r - 2); #endif return r - 2; } } printc_err("ftdi: timed out while receiving data\n"); return -1; } static int tr_send(transport_t tr_base, const uint8_t *databuf, int len) { struct ftdi_transport *tr = (struct ftdi_transport *)tr_base; #ifdef DEBUG_OLIMEX_ISO debug_hexdump("ftdi: tr_send", databuf, len); #endif while (len) { int r = usb_bulk_write(tr->handle, EP_OUT, (char *)databuf, len, TIMEOUT_S * 1000); if (r <= 0) { printc_err("ftdi: usb_bulk_write: %s\n", usb_strerror()); return -1; } databuf += r; len -= r; } return 0; } static int tr_flush(transport_t tr_base) { struct ftdi_transport *tr = malloc(sizeof(*tr)); return do_cfg(tr->handle, "purge RX", FTDI_SIO_RESET, FTDI_SIO_RESET_PURGE_RX); } static int tr_set_modem(transport_t tr_base, transport_modem_t state) { struct ftdi_transport *tr = malloc(sizeof(*tr)); int value = FTDI_WRITE_DTR | FTDI_WRITE_RTS; /* DTR and RTS bits are active-low for this device */ if (!(state & TRANSPORT_MODEM_DTR)) value |= FTDI_DTR; if (!(state & TRANSPORT_MODEM_RTS)) value |= FTDI_RTS; return do_cfg(tr->handle, "set modem control lines", FTDI_SIO_MODEM_CTRL, value); } static const struct transport_class ftdi_class = { .destroy = tr_destroy, .send = tr_send, .recv = tr_recv, .flush = tr_flush, .set_modem = tr_set_modem }; transport_t ftdi_open(const char *devpath, const char *requested_serial, uint16_t vendor, uint16_t product, int baud_rate) { struct ftdi_transport *tr = malloc(sizeof(*tr)); struct usb_device *dev; if (!tr) { pr_error("ftdi: can't allocate memory"); return NULL; } tr->base.ops = &ftdi_class; usb_init(); usb_find_busses(); usb_find_devices(); if (devpath) dev = usbutil_find_by_loc(devpath); else dev = usbutil_find_by_id(vendor, product, requested_serial); if (!dev) { free(tr); return NULL; } if (open_device(tr, dev, baud_rate) < 0) { printc_err("ftdi: failed to open device\n"); free(tr); return NULL; } return &tr->base; } mspdebug-0.25/transport/ftdi.h000066400000000000000000000023141313531517500164050ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef FTDI_H_ #define FTDI_H_ #include "transport.h" /* Search the USB bus for the first Olimex ISO device and initialize it. * If successful, return a transport object. Otherwise, return NULL. * * A particular USB device or serial number may be specified. */ transport_t ftdi_open(const char *usb_device, const char *requested_serial, uint16_t vendor, uint16_t product, int baud_rate); #endif mspdebug-0.25/transport/rf2500.c000066400000000000000000000142441313531517500163750ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009-2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #ifndef __Windows__ #include #else #include #endif #include "rf2500.h" #include "util.h" #include "usbutil.h" #include "output.h" struct rf2500_transport { struct transport base; int int_number; struct usb_dev_handle *handle; uint8_t buf[64]; int len; int offset; }; /********************************************************************* * USB transport * * These functions handle the details of slicing data over USB * transfers. The interface presented is a continuous byte stream with * no slicing codes. * * Writes are unbuffered -- a single write translates to at least * one transfer. */ #define USB_FET_VENDOR 0x0451 #define USB_FET_PRODUCT 0xf432 #define USB_FET_INTERFACE_CLASS 3 #define USB_FET_IN_EP 0x81 #define USB_FET_OUT_EP 0x01 static int open_interface(struct rf2500_transport *tr, struct usb_device *dev, int ino) { printc_dbg("Trying to open interface %d on %s\n", ino, dev->filename); tr->int_number = ino; tr->handle = usb_open(dev); if (!tr->handle) { pr_error("rf2500: can't open device"); return -1; } #if defined(__linux__) if (usb_detach_kernel_driver_np(tr->handle, tr->int_number) < 0) pr_error("rf2500: warning: can't " "detach kernel driver"); #endif #ifdef __Windows__ if (usb_set_configuration(tr->handle, 1) < 0) { pr_error("rf2500: can't set configuration 1"); usb_close(tr->handle); return -1; } #endif if (usb_claim_interface(tr->handle, tr->int_number) < 0) { pr_error("rf2500: can't claim interface"); usb_close(tr->handle); return -1; } return 0; } static int open_device(struct rf2500_transport *tr, struct usb_device *dev) { struct usb_config_descriptor *c = &dev->config[0]; int i; for (i = 0; i < c->bNumInterfaces; i++) { struct usb_interface *intf = &c->interface[i]; struct usb_interface_descriptor *desc = &intf->altsetting[0]; if (desc->bInterfaceClass == USB_FET_INTERFACE_CLASS && !open_interface(tr, dev, desc->bInterfaceNumber)) return 0; } return -1; } static int usbtr_send(transport_t tr_base, const uint8_t *data, int len) { struct rf2500_transport *tr = (struct rf2500_transport *)tr_base; while (len) { uint8_t pbuf[256]; int plen = len > 255 ? 255 : len; int txlen = plen + 1; memcpy(pbuf + 1, data, plen); /* This padding is needed to work around an apparent bug in * the RF2500 FET. Without this, the device hangs. */ if (txlen > 32 && (txlen & 0x3f)) while (txlen < 255 && (txlen & 0x3f)) pbuf[txlen++] = 0xff; else if (txlen > 16 && (txlen & 0xf)) while (txlen < 255 && (txlen & 0xf) != 1) pbuf[txlen++] = 0xff; pbuf[0] = txlen - 1; #ifdef DEBUG_USBTR debug_hexdump("USB transfer out", pbuf, txlen); #endif if (usb_bulk_write(tr->handle, USB_FET_OUT_EP, (char *)pbuf, txlen, 10000) < 0) { pr_error("rf2500: can't send data"); return -1; } data += plen; len -= plen; } return 0; } static int usbtr_recv(transport_t tr_base, uint8_t *databuf, int max_len) { struct rf2500_transport *tr = (struct rf2500_transport *)tr_base; int rlen; if (tr->offset >= tr->len) { if (usb_bulk_read(tr->handle, USB_FET_IN_EP, (char *)tr->buf, sizeof(tr->buf), 10000) < 0) { pr_error("rf2500: can't receive data"); return -1; } #ifdef DEBUG_USBTR debug_hexdump("USB transfer in", tr->buf, 64); #endif tr->len = tr->buf[1] + 2; if (tr->len > sizeof(tr->buf)) tr->len = sizeof(tr->buf); tr->offset = 2; } rlen = tr->len - tr->offset; if (rlen > max_len) rlen = max_len; memcpy(databuf, tr->buf + tr->offset, rlen); tr->offset += rlen; return rlen; } static void usbtr_destroy(transport_t tr_base) { struct rf2500_transport *tr = (struct rf2500_transport *)tr_base; usb_release_interface(tr->handle, tr->int_number); usb_close(tr->handle); free(tr); } static int usbtr_flush(transport_t tr_base) { struct rf2500_transport *tr = (struct rf2500_transport *)tr_base; #if !defined(__APPLE__) && !defined(__sun__) char buf[64]; /* Flush out lingering data. * * The timeout apparently doesn't work on OS/X, and this loop * just hangs once the endpoint buffer empties. */ while (usb_bulk_read(tr->handle, USB_FET_IN_EP, buf, sizeof(buf), 100) > 0); #endif tr->len = 0; tr->offset = 0; return 0; } static int usbtr_set_modem(transport_t tr_base, transport_modem_t state) { printc_err("rf2500: unsupported operation: set_modem\n"); return -1; } static const struct transport_class rf2500_transport = { .destroy = usbtr_destroy, .send = usbtr_send, .recv = usbtr_recv, .flush = usbtr_flush, .set_modem = usbtr_set_modem }; transport_t rf2500_open(const char *devpath, const char *requested_serial) { struct rf2500_transport *tr = malloc(sizeof(*tr)); struct usb_device *dev; if (!tr) { pr_error("rf2500: can't allocate memory"); return NULL; } memset(tr, 0, sizeof(*tr)); tr->base.ops = &rf2500_transport; usb_init(); usb_find_busses(); usb_find_devices(); if (devpath) dev = usbutil_find_by_loc(devpath); else dev = usbutil_find_by_id(USB_FET_VENDOR, USB_FET_PRODUCT, requested_serial); if (!dev) { free(tr); return NULL; } if (open_device(tr, dev) < 0) { printc_err("rf2500: failed to open RF2500 device\n"); free(tr); return NULL; } usbtr_flush(&tr->base); return (transport_t)tr; } mspdebug-0.25/transport/rf2500.h000066400000000000000000000022601313531517500163750ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef RF2500_H_ #define RF2500_H_ #include "transport.h" /* Search the USB bus for the first eZ430-RF2500, and initialize it. If * successful, 0 is returned and the fet_* functions are ready for use. * If an error occurs, -1 is returned. * * A particular device may be specified in bus:dev form. */ transport_t rf2500_open(const char *dev_path, const char *requested_serial); #endif mspdebug-0.25/transport/rf2500hidapi.c000066400000000000000000000112511313531517500175470ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009-2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include #include "rf2500.h" #include "util.h" #include "usbutil.h" #include "output.h" #define USB_FET_VENDOR 0x0451 #define USB_FET_PRODUCT 0xf432 #define USB_FET_IN_EP 0x81 #define USB_FET_OUT_EP 0x01 struct rf2500_transport { struct transport base; hid_device *handle; uint8_t buf[64]; int len; int offset; }; static int usbtr_send(transport_t tr_base, const uint8_t *data, int len) { struct rf2500_transport *tr = (struct rf2500_transport *)tr_base; while (len) { uint8_t pbuf[256]; int plen = len > 255 ? 255 : len; int txlen = plen + 1; memcpy(pbuf + 1, data, plen); /* This padding is needed to work around an apparent bug in * the RF2500 FET. Without this, the device hangs. */ if (txlen > 32 && (txlen & 0x3f)) while (txlen < 255 && (txlen & 0x3f)) pbuf[txlen++] = 0xff; else if (txlen > 16 && (txlen & 0xf)) while (txlen < 255 && (txlen & 0xf) != 1) pbuf[txlen++] = 0xff; pbuf[0] = txlen - 1; #ifdef DEBUG_USBTR debug_hexdump("HIDUSB transfer out", pbuf, txlen); #endif if (hid_write(tr->handle, (const unsigned char *)pbuf, txlen) < 0) { pr_error("rf2500: can't send data"); return -1; } data += plen; len -= plen; } return 0; } static int usbtr_recv(transport_t tr_base, uint8_t *databuf, int max_len) { struct rf2500_transport *tr = (struct rf2500_transport *)tr_base; int rlen; if (tr->offset >= tr->len) { if (hid_read_timeout(tr->handle, (unsigned char *)tr->buf, sizeof(tr->buf), 10000) < 0) { pr_error("rf2500: can't receive data"); return -1; } #ifdef DEBUG_USBTR debug_hexdump("HIDUSB transfer in", tr->buf, 64); #endif tr->len = tr->buf[1] + 2; if (tr->len > sizeof(tr->buf)) tr->len = sizeof(tr->buf); tr->offset = 2; } rlen = tr->len - tr->offset; if (rlen > max_len) rlen = max_len; memcpy(databuf, tr->buf + tr->offset, rlen); tr->offset += rlen; return rlen; } static void usbtr_destroy(transport_t tr_base) { struct rf2500_transport *tr = (struct rf2500_transport *)tr_base; hid_close(tr->handle); free(tr); hid_exit(); } static int usbtr_flush(transport_t tr_base) { struct rf2500_transport *tr = (struct rf2500_transport *)tr_base; unsigned char buf[64]; /* Flush out lingering data. * * The timeout apparently doesn't work on OS/X, and this loop * just hangs once the endpoint buffer empties. */ while (hid_read_timeout(tr->handle, buf, sizeof(buf), 100) > 0); tr->len = 0; tr->offset = 0; return 0; } static int usbtr_set_modem(transport_t tr_base, transport_modem_t state) { printc_err("rf2500: unsupported operation: set_modem\n"); return -1; } static const struct transport_class rf2500_transport = { .destroy = usbtr_destroy, .send = usbtr_send, .recv = usbtr_recv, .flush = usbtr_flush, .set_modem = usbtr_set_modem }; static const wchar_t * get_wc(const char *c) { const size_t csize = strlen(c)+1; wchar_t* wc = malloc(sizeof(wchar_t)*csize); mbstowcs (wc, c, csize); return wc; } transport_t rf2500_open(const char *devpath, const char *requested_serial) { struct rf2500_transport *tr = malloc(sizeof(*tr)); hid_device *handle; if (!tr) { pr_error("rf2500: can't allocate memory"); return NULL; } memset(tr, 0, sizeof(*tr)); tr->base.ops = &rf2500_transport; hid_init(); if (devpath) { handle = hid_open_path(devpath); } else { const wchar_t * wc_serial; if ( requested_serial ) { wc_serial = get_wc(requested_serial); } else { wc_serial = NULL; } handle = hid_open(USB_FET_VENDOR, USB_FET_PRODUCT, wc_serial); if ( wc_serial ) { free((wchar_t *)wc_serial); } } if (!handle) { printc_err("rf2500: failed to open RF2500 device\n"); free(tr); hid_exit(); return NULL; } tr->handle = handle; usbtr_flush(&tr->base); return (transport_t)tr; } mspdebug-0.25/transport/ti3410.c000066400000000000000000000343261313531517500164060ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include #ifndef __Windows__ #include #else #include #endif #include #include "ti3410.h" #include "util.h" #include "usbutil.h" #include "output.h" #include "ihex.h" /************************************************************************ * Definitions taken from drivers/usb/serial/ti_usb_3410_5052.h in the * Linux kernel (GPLv2+). */ /* Configuration ids */ #define TI_BOOT_CONFIG 1 #define TI_ACTIVE_CONFIG 2 /* Pipe transfer mode and timeout */ #define TI_PIPE_MODE_CONTINOUS 0x01 #define TI_PIPE_MODE_MASK 0x03 #define TI_PIPE_TIMEOUT_MASK 0x7C #define TI_PIPE_TIMEOUT_ENABLE 0x80 /* Module identifiers */ #define TI_I2C_PORT 0x01 #define TI_IEEE1284_PORT 0x02 #define TI_UART1_PORT 0x03 #define TI_UART2_PORT 0x04 #define TI_RAM_PORT 0x05 /* Purge modes */ #define TI_PURGE_OUTPUT 0x00 #define TI_PURGE_INPUT 0x80 /* Commands */ #define TI_GET_VERSION 0x01 #define TI_GET_PORT_STATUS 0x02 #define TI_GET_PORT_DEV_INFO 0x03 #define TI_GET_CONFIG 0x04 #define TI_SET_CONFIG 0x05 #define TI_OPEN_PORT 0x06 #define TI_CLOSE_PORT 0x07 #define TI_START_PORT 0x08 #define TI_STOP_PORT 0x09 #define TI_TEST_PORT 0x0A #define TI_PURGE_PORT 0x0B #define TI_RESET_EXT_DEVICE 0x0C #define TI_WRITE_DATA 0x80 #define TI_READ_DATA 0x81 #define TI_REQ_TYPE_CLASS 0x82 /* Bits per character */ #define TI_UART_5_DATA_BITS 0x00 #define TI_UART_6_DATA_BITS 0x01 #define TI_UART_7_DATA_BITS 0x02 #define TI_UART_8_DATA_BITS 0x03 /* Parity */ #define TI_UART_NO_PARITY 0x00 #define TI_UART_ODD_PARITY 0x01 #define TI_UART_EVEN_PARITY 0x02 #define TI_UART_MARK_PARITY 0x03 #define TI_UART_SPACE_PARITY 0x04 /* Stop bits */ #define TI_UART_1_STOP_BITS 0x00 #define TI_UART_1_5_STOP_BITS 0x01 #define TI_UART_2_STOP_BITS 0x02 /* Modem control */ #define TI_MCR_LOOP 0x04 #define TI_MCR_DTR 0x10 #define TI_MCR_RTS 0x20 /* Read/Write data */ #define TI_RW_DATA_ADDR_SFR 0x10 #define TI_RW_DATA_ADDR_IDATA 0x20 #define TI_RW_DATA_ADDR_XDATA 0x30 #define TI_RW_DATA_ADDR_CODE 0x40 #define TI_RW_DATA_ADDR_GPIO 0x50 #define TI_RW_DATA_ADDR_I2C 0x60 #define TI_RW_DATA_ADDR_FLASH 0x70 #define TI_RW_DATA_ADDR_DSP 0x80 #define TI_RW_DATA_UNSPECIFIED 0x00 #define TI_RW_DATA_BYTE 0x01 #define TI_RW_DATA_WORD 0x02 #define TI_RW_DATA_DOUBLE_WORD 0x04 #define TI_TRANSFER_TIMEOUT 2 #define TI_FIRMWARE_BUF_SIZE 16284 #define TI_DOWNLOAD_MAX_PACKET_SIZE 64 /************************************************************************/ struct ti3410_transport { struct transport base; struct usb_dev_handle *hnd; }; #define USB_FET_VENDOR 0x0451 #define USB_FET_PRODUCT 0xf430 #define USB_FET_INTERFACE 0 #define USB_FET_IN_EP 0x81 #define USB_FET_OUT_EP 0x01 #define USB_FET_INT_EP 0x83 #define USB_FDL_INTERFACE 0 #define USB_FDL_OUT_EP 0x01 #define TIMEOUT 1000 #define READ_TIMEOUT 5000 static int open_device(struct ti3410_transport *tr, struct usb_device *dev) { struct usb_dev_handle *hnd; hnd = usb_open(dev); if (!hnd) { pr_error("ti3410: failed to open USB device"); return -1; } #if defined(__linux__) if (usb_detach_kernel_driver_np(hnd, USB_FET_INTERFACE) < 0) pr_error("ti3410: warning: can't " "detach kernel driver"); #endif /* This device has two configurations -- we need the one which * has two bulk endpoints and a control. */ if (dev->config->bConfigurationValue == TI_BOOT_CONFIG) { printc_dbg("TI3410 device is in boot config, " "setting active\n"); if (usb_set_configuration(hnd, TI_ACTIVE_CONFIG) < 0) { pr_error("ti3410: failed to set active config"); usb_close(hnd); return -1; } } if (usb_claim_interface(hnd, USB_FET_INTERFACE) < 0) { pr_error("ti3410: can't claim interface"); usb_close(hnd); return -1; } tr->hnd = hnd; return 0; } static int set_termios(struct ti3410_transport *tr) { static const uint8_t tios_data[10] = { 0x00, 0x02, /* 460800 bps */ 0x60, 0x00, /* flags = ENABLE_MS_INTS | AUTO_START_DMA */ TI_UART_8_DATA_BITS, TI_UART_NO_PARITY, TI_UART_1_STOP_BITS, 0x00, /* cXon */ 0x00, /* cXoff */ 0x00 /* UART mode = RS232 */ }; if (usb_control_msg(tr->hnd, USB_TYPE_VENDOR | USB_RECIP_DEVICE, TI_SET_CONFIG, 0, TI_UART1_PORT, (char *)tios_data, sizeof(tios_data), TIMEOUT) < 0) { pr_error("ti3410: TI_SET_CONFIG failed"); return -1; } return 0; } static int set_mcr(struct ti3410_transport *tr) { static const uint8_t wb_data[9] = { TI_RW_DATA_ADDR_XDATA, TI_RW_DATA_BYTE, 1, /* byte count */ 0x00, 0x00, 0xff, 0xa4, /* base address */ TI_MCR_LOOP | TI_MCR_RTS | TI_MCR_DTR, /* mask */ TI_MCR_RTS | TI_MCR_DTR /* data */ }; if (usb_control_msg(tr->hnd, USB_TYPE_VENDOR | USB_RECIP_DEVICE, TI_WRITE_DATA, 0, TI_RAM_PORT, (char *)wb_data, sizeof(wb_data), TIMEOUT) < 0) { pr_error("ti3410: TI_SET_CONFIG failed"); return -1; } return 0; } static int do_open_start(struct ti3410_transport *tr) { if (set_termios(tr) < 0) return -1; if (set_mcr(tr) < 0) return -1; if (usb_control_msg(tr->hnd, USB_TYPE_VENDOR | USB_RECIP_DEVICE, TI_OPEN_PORT, TI_PIPE_MODE_CONTINOUS | TI_PIPE_TIMEOUT_ENABLE | (TI_TRANSFER_TIMEOUT << 2), TI_UART1_PORT, NULL, 0, TIMEOUT) < 0) { pr_error("ti3410: TI_OPEN_PORT failed"); return -1; } if (usb_control_msg(tr->hnd, USB_TYPE_VENDOR | USB_RECIP_DEVICE, TI_START_PORT, 0, TI_UART1_PORT, NULL, 0, TIMEOUT) < 0) { pr_error("ti3410: TI_START_PORT failed"); return -1; } return 0; } static int interrupt_flush(struct ti3410_transport *tr) { uint8_t buf[2]; return usb_interrupt_read(tr->hnd, USB_FET_INT_EP, (char *)buf, 2, TIMEOUT); } static int setup_port(struct ti3410_transport *tr) { interrupt_flush(tr); if (do_open_start(tr) < 0) return -1; if (usb_control_msg(tr->hnd, USB_TYPE_VENDOR | USB_RECIP_DEVICE, TI_PURGE_PORT, TI_PURGE_INPUT, TI_UART1_PORT, NULL, 0, TIMEOUT) < 0) { pr_error("ti3410: TI_PURGE_PORT (input) failed"); return -1; } interrupt_flush(tr); interrupt_flush(tr); if (usb_control_msg(tr->hnd, USB_TYPE_VENDOR | USB_RECIP_DEVICE, TI_PURGE_PORT, TI_PURGE_OUTPUT, TI_UART1_PORT, NULL, 0, TIMEOUT) < 0) { pr_error("ti3410: TI_PURGE_PORT (output) failed"); return -1; } interrupt_flush(tr); if (usb_clear_halt(tr->hnd, USB_FET_IN_EP) < 0 || usb_clear_halt(tr->hnd, USB_FET_OUT_EP) < 0) { pr_error("ti3410: failed to clear halt status"); return -1; } if (do_open_start(tr) < 0) return -1; return 0; } static void teardown_port(struct ti3410_transport *tr) { if (usb_control_msg(tr->hnd, USB_TYPE_VENDOR | USB_RECIP_DEVICE, TI_CLOSE_PORT, 0, TI_UART1_PORT, NULL, 0, TIMEOUT) < 0) pr_error("ti3410: warning: TI_CLOSE_PORT failed"); } static int ti3410_send(transport_t tr_base, const uint8_t *data, int len) { struct ti3410_transport *tr = (struct ti3410_transport *)tr_base; int sent; while (len) { sent = usb_bulk_write(tr->hnd, USB_FET_OUT_EP, (char *)data, len, TIMEOUT); if (sent <= 0) { pr_error("ti3410: can't send data"); return -1; } data += sent; len -= sent; } return 0; } static int ti3410_recv(transport_t tr_base, uint8_t *databuf, int max_len) { struct ti3410_transport *tr = (struct ti3410_transport *)tr_base; time_t deadline = time(NULL) + READ_TIMEOUT / 1000; int rlen; while (time(NULL) < deadline) { rlen = usb_bulk_read(tr->hnd, USB_FET_IN_EP, (char *)databuf, max_len, READ_TIMEOUT); if (rlen > 0) return rlen; if (rlen < 0) { printc_err("ti3410: usb_bulk_read: %s\n", usb_strerror()); return -1; } } printc_err("ti3410: read timeout\n"); return -1; } static void ti3410_destroy(transport_t tr_base) { struct ti3410_transport *tr = (struct ti3410_transport *)tr_base; teardown_port(tr); free(tr); } struct firmware { uint8_t buf[TI_FIRMWARE_BUF_SIZE]; unsigned int size; }; static FILE *find_firmware(void) { char path[256]; const char *env; FILE *in; printc_dbg("Searching for firmware for TI3410...\n"); env = getenv("MSPDEBUG_TI3410_FW"); if (env) { snprintf(path, sizeof(path), "%s", env); printc_dbg(" - checking %s\n", path); in = fopen(path, "r"); if (in) return in; } snprintf(path, sizeof(path), "%s", LIB_DIR "/mspdebug/ti_3410.fw.ihex"); printc_dbg(" - checking %s\n", path); in = fopen(path, "r"); if (in) return in; snprintf(path, sizeof(path), "%s", "ti_3410.fw.ihex"); printc_dbg(" - checking %s\n", path); in = fopen(path, "r"); if (in) return in; printc_err("ti3410: unable to locate firmware\n"); return NULL; } static int do_extract(void *user_data, const struct binfile_chunk *ch) { struct firmware *f = (struct firmware *)user_data; if (f->size != ch->addr) { printc_err("ti3410: firmware gap at 0x%x (ends at 0x%0x)\n", f->size, ch->addr); return -1; } if (f->size + ch->len > sizeof(f->buf)) { printc_err("ti3410: maximum firmware size exceeded\n"); return -1; } memcpy(f->buf + f->size, ch->data, ch->len); f->size += ch->len; return 0; } static int load_firmware(struct firmware *f) { FILE *in = find_firmware(); if (!in) return -1; if (!ihex_check(in)) { printc_err("ti3410: not a valid IHEX file\n"); fclose(in); return -1; } memset(f, 0, sizeof(*f)); if (ihex_extract(in, do_extract, f) < 0) { printc_err("ti3410: failed to load firmware\n"); fclose(in); return -1; } fclose(in); return 0; } static void prepare_firmware(struct firmware *f) { uint8_t cksum = 0; uint16_t real_size = f->size - 3; int i; for (i = 3; i < f->size; i++) cksum += f->buf[i]; f->buf[0] = real_size & 0xff; f->buf[1] = real_size >> 8; f->buf[2] = cksum; printc_dbg("Loaded %d byte firmware image (checksum = 0x%02x)\n", f->size, cksum); } static int do_download(struct usb_device *dev, const struct firmware *f) { struct usb_dev_handle *hnd; int offset = 0; printc_dbg("Starting download...\n"); hnd = usb_open(dev); if (!hnd) { pr_error("ti3410: failed to open USB device"); return -1; } #if defined(__linux__) if (usb_detach_kernel_driver_np(hnd, USB_FDL_INTERFACE) < 0) pr_error("ti3410: warning: can't " "detach kernel driver"); #endif if (usb_claim_interface(hnd, USB_FDL_INTERFACE) < 0) { pr_error("ti3410: can't claim interface"); usb_close(hnd); return -1; } while (offset < f->size) { int plen = f->size - offset; int r; if (plen > TI_DOWNLOAD_MAX_PACKET_SIZE) plen = TI_DOWNLOAD_MAX_PACKET_SIZE; r = usb_bulk_write(hnd, USB_FDL_OUT_EP, (char *)f->buf + offset, plen, TIMEOUT); if (r < 0) { pr_error("ti3410: bulk write failed"); usb_close(hnd); return -1; } offset += r; } delay_ms(100); if (usb_reset(hnd) < 0) pr_error("ti3410: warning: reset failed"); usb_close(hnd); return 0; } static int download_firmware(struct usb_device *dev) { struct firmware frm; if (load_firmware(&frm) < 0) return -1; prepare_firmware(&frm); if (do_download(dev, &frm) < 0) return -1; printc_dbg("Waiting for TI3410 reset...\n"); delay_s(2); return 0; } static int ti3410_flush(transport_t tr_base) { return 0; } static int ti3410_set_modem(transport_t tr_base, transport_modem_t state) { printc_err("ti3410: unsupported operation: set_modem\n"); return -1; } static const struct transport_class ti3410_transport = { .destroy = ti3410_destroy, .send = ti3410_send, .recv = ti3410_recv, .flush = ti3410_flush, .set_modem = ti3410_set_modem }; transport_t ti3410_open(const char *devpath, const char *requested_serial) { struct ti3410_transport *tr = malloc(sizeof(*tr)); struct usb_device *dev; if (!tr) { pr_error("ti3410: can't allocate memory"); return NULL; } tr->base.ops = &ti3410_transport; usb_init(); usb_find_busses(); usb_find_devices(); if (devpath) dev = usbutil_find_by_loc(devpath); else dev = usbutil_find_by_id(USB_FET_VENDOR, USB_FET_PRODUCT, requested_serial); if (!dev) { free(tr); return NULL; } if (dev->descriptor.bNumConfigurations == 1) { if (download_firmware(dev) < 0) { printc_err("ti3410: firmware download failed\n"); free(tr); return NULL; } usb_find_devices(); if (devpath) dev = usbutil_find_by_loc(devpath); else dev = usbutil_find_by_id(USB_FET_VENDOR, USB_FET_PRODUCT, requested_serial); if (!dev) { free(tr); return NULL; } } if (open_device(tr, dev) < 0) { printc_err("ti3410: failed to open TI3410 device\n"); free(tr); return NULL; } if (setup_port(tr) < 0) { printc_err("ti3410: failed to set up port\n"); teardown_port(tr); usb_close(tr->hnd); free(tr); return NULL; } return (transport_t)tr; } mspdebug-0.25/transport/ti3410.h000066400000000000000000000020161313531517500164020ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2011 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef TI3410_H_ #define TI3410_H_ #include "transport.h" /* This function is for opening an eZ430-F2013 or FET430UIF device via * libusb. */ transport_t ti3410_open(const char *dev_path, const char *requested_serial); #endif mspdebug-0.25/transport/transport.h000066400000000000000000000044351313531517500175210ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef TRANSPORT_H_ #define TRANSPORT_H_ #include /* This structure is used to provide a consistent interface to a * lower-level serial-port type device. */ struct transport; typedef struct transport *transport_t; typedef enum { TRANSPORT_MODEM_DTR = 0x01, TRANSPORT_MODEM_RTS = 0x02 } transport_modem_t; struct transport_class { /* Close the port and free resources */ void (*destroy)(transport_t tr); /* Send a block of data. Returns 0 on success, or -1 if an error * occurs. */ int (*send)(transport_t tr, const uint8_t *data, int len); /* Receive a block of data, up to the maximum size. Returns the * number of bytes received on success (which must be non-zero), * or -1 if an error occurs. Read timeouts are treated as * errors. */ int (*recv)(transport_t tr, uint8_t *data, int max_len); /* Flush any lingering data in either direction. */ int (*flush)(transport_t tr); /* Set modem control lines. Returns 0 on success or -1 if an * error occurs. */ int (*set_modem)(transport_t tr, transport_modem_t state); /* This pair of optional methods allows a transport to survive a * USB device reset. Before an impending reset, suspend() should * be called to release references to the bus. After the reset * is completed, resume() should be called to reattach. * * It is an error to invoke IO methods on a suspended device. */ int (*suspend)(transport_t tr); int (*resume)(transport_t tr); }; struct transport { const struct transport_class *ops; }; #endif mspdebug-0.25/ui/000077500000000000000000000000001313531517500136675ustar00rootroot00000000000000mspdebug-0.25/ui/aliasdb.c000066400000000000000000000075341313531517500154430ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include "aliasdb.h" #include "vector.h" #include "output.h" #include "util.h" struct alias { char src[256]; char dst[256]; }; static struct vector alias_list = { .ptr = NULL, .capacity = 0, .size = 0, .elemsize = sizeof(struct alias) }; static int list_is_sorted; static struct alias *find_alias(const char *name) { int i; for (i = 0; i < alias_list.size; i++) { struct alias *a = VECTOR_PTR(alias_list, i, struct alias); if (!strcasecmp(name, a->src)) return a; } return NULL; } struct recurse_list { const char *cmd; struct recurse_list *next; }; static int translate_rec(struct recurse_list *l, const char *command, const char *args, char *out_cmd, int max_len) { struct recurse_list *c; const struct alias *a; if (*command == '\\') { snprintf(out_cmd, max_len, "%s %s", command + 1, args); return 0; } for (c = l; c; c = c->next) if (!strcasecmp(c->cmd, command)) { printc_err("recursive alias: %s\n", command); return -1; } a = find_alias(command); if (a) { struct recurse_list r; char tmp_buf[1024]; char *new_args = tmp_buf; char *cmd; snprintf(tmp_buf, sizeof(tmp_buf), "%s %s", a->dst, args); r.next = l; r.cmd = command; cmd = get_arg(&new_args); return translate_rec(&r, cmd, new_args, out_cmd, max_len); } snprintf(out_cmd, max_len, "%s %s", command, args); return 0; } int translate_alias(const char *command, const char *args, char *out_cmd, int max_len) { return translate_rec(NULL, command, args, out_cmd, max_len); } static int cmp_alias(const void *a, const void *b) { const struct alias *aa = (const struct alias *)a; const struct alias *ab = (const struct alias *)b; return strcasecmp(aa->src, ab->src); } int cmd_alias(char **arg) { const char *src = get_arg(arg); const char *dst = get_arg(arg); struct alias *a; struct alias na; if (!src) { /* List aliases */ int i; if (!list_is_sorted) { qsort(alias_list.ptr, alias_list.size, alias_list.elemsize, cmp_alias); list_is_sorted = 1; } printc("%d aliases defined:\n", alias_list.size); for (i = 0; i < alias_list.size; i++) { struct alias *a = VECTOR_PTR(alias_list, i, struct alias); printc(" %20s = %s\n", a->src, a->dst); } return 0; } a = find_alias(src); if (!dst) { /* Delete alias */ struct alias *end = VECTOR_PTR(alias_list, alias_list.size - 1, struct alias); if (!a) { printc_err("alias: no such alias defined: %s\n", src); return -1; } if (end != a) memcpy(a, end, sizeof(*a)); vector_pop(&alias_list); list_is_sorted = 0; return 0; } if (a) { /* Overwrite old alias */ strncpy(a->dst, dst, sizeof(a->dst)); a->dst[sizeof(a->dst) - 1] = 0; return 0; } /* New alias */ strncpy(na.src, src, sizeof(na.src)); na.src[sizeof(na.src) - 1] = 0; strncpy(na.dst, dst, sizeof(na.dst)); na.dst[sizeof(na.dst) - 1] = 0; if (vector_push(&alias_list, &na, 1) < 0) { printc_err("alias: can't allocate memory: %s\n", last_error()); return -1; } list_is_sorted = 0; return 0; } mspdebug-0.25/ui/aliasdb.h000066400000000000000000000020311313531517500154330ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef ALIASDB_H_ #define ALIASDB_H_ /* "alias" command */ int cmd_alias(char **arg); /* Translate a command using the aliases table. */ int translate_alias(const char *command, const char *args, char *out_cmd, int max_len); #endif mspdebug-0.25/ui/cmddb.c000066400000000000000000000231441313531517500151100ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include "cmddb.h" #include "util.h" #include "devcmd.h" #include "flatfile.h" #include "gdb.h" #include "rtools.h" #include "sym.h" #include "stdcmd.h" #include "simio.h" #include "aliasdb.h" #include "power.h" const struct cmddb_record commands[] = { { .name = "help", .func = cmd_help, .help = "help [command]\n" " Without arguments, displays a list of commands. With a command\n" " name as an argument, displays help for that command.\n" }, { .name = "opt", .func = cmd_opt, .help = "opt [name] [value]\n" " Query or set option variables. With no arguments, displays all\n" " available options.\n" }, { .name = "read", .func = cmd_read, .help = "read \n" " Read commands from a file and evaluate them.\n" }, { .name = "setbreak", .func = cmd_setbreak, .help = "setbreak [index]\n" " Set a breakpoint. If no index is specified, the first available\n" " slot will be used.\n" }, { .name = "setwatch", .func = cmd_setwatch, .help = "setwatch [index]\n" " Set a watchpoint. If no index is specified. the first available\n" " slot will be used.\n" }, { .name = "setwatch_r", .func = cmd_setwatch_r, .help = "setwatch_r [index]\n" " Set a read-only watchpoint.\n" }, { .name = "setwatch_w", .func = cmd_setwatch_w, .help = "setwatch_w [index]\n" " Set a write-only watchpoint.\n" }, { .name = "delbreak", .func = cmd_delbreak, .help = "delbreak [index]\n" " Delete a breakpoint. If no index is specified, then all active\n" " breakpoints are cleared.\n" }, { .name = "break", .func = cmd_break, .help = "break\n" " List active breakpoints.\n" }, { .name = "regs", .func = cmd_regs, .help = "regs\n" " Read and display the current register contents.\n" }, { .name = "prog", .func = cmd_prog, .help = "prog \n" " Erase the device and flash the data contained in a binary file.\n" " This command also loads symbols from the file, if available.\n" }, { .name = "load", .func = cmd_load, .help = "load \n" " Flash the data contained in a binary file. Does not load symbols\n" " or erase the device.\n" }, { .name = "verify", .func = cmd_verify, .help = "verify \n" " Compare the contents of the given binary file to the device memory.\n" }, { .name = "load_raw", .func = cmd_load_raw, .help = "load_raw
\n" " Write the data contained in a raw binary file to the given memory\n" " address.\n" }, { .name = "verify_raw", .func = cmd_verify_raw, .help = "verify_raw
\n" " Compare the contents of a raw binary file to the device memory at\n" " the given address.\n" }, { .name = "save_raw", .func = cmd_save_raw, .help = "save_raw
\n" " Save a region of memory to a raw binary file.\n" }, { .name = "md", .func = cmd_md, .help = "md
[length]\n" " Read the specified number of bytes from memory at the given\n" " address, and display a hexdump.\n" }, { .name = "mw", .func = cmd_mw, .help = "mw
bytes ...\n" " Write a sequence of bytes to a memory address. Byte values are\n" " two-digit hexadecimal numbers.\n" }, { .name = "reset", .func = cmd_reset, .help = "reset\n" " Reset (and halt) the CPU.\n" }, { .name = "blow_jtag_fuse", .func = cmd_blow_jtag_fuse, .help = "blow-jtag-fuse\n" " Blow the device's JTAG fuse.\n" "\n" " \x1b[1mWARNING: this is an irreversible operation!\x1b[0m\n" }, { .name = "erase", .func = cmd_erase, .help = "erase [all|segment] [address]\n" "erase segrange
\n" " Erase the device under test. With no arguments, erases all of main\n" " memory. Specify arguments to perform a mass erase, or to erase\n" " individual segments. The \"segrange\" mode is used to erase an\n" " address range via a series of segment erases.\n" }, { .name = "step", .func = cmd_step, .help = "step [count]\n" " Single-step the CPU, and display the register state.\n" }, { .name = "run", .func = cmd_run, .help = "run\n" " Run the CPU to until a breakpoint is reached or the command is\n" " interrupted.\n" }, { .name = "set", .func = cmd_set, .help = "set \n" " Change the value of a CPU register.\n" }, { .name = "dis", .func = cmd_dis, .help = "dis
[length]\n" " Disassemble a section of memory.\n" }, { .name = "hexout", .func = cmd_hexout, .help = "hexout
\n" " Save a region of memory into a HEX file.\n" }, { .name = "gdb", .func = cmd_gdb, .help = "gdb [port]\n" " Run a GDB remote stub on the given TCP/IP port.\n" }, { .name = "=", .func = cmd_eval, .help = "= \n" " Evaluate an expression using the symbol table.\n" }, { .name = "sym", .func = cmd_sym, .help = "sym clear\n" " Clear the symbol table.\n" "sym set \n" " Set or overwrite the value of a symbol.\n" "sym del \n" " Delete a symbol from the symbol table.\n" "sym import \n" " Load symbols from the given file.\n" "sym import+ \n" " Load additional symbols from the given file.\n" "sym export \n" " Save the current symbols to a BSD-style symbol file.\n" "sym find \n" " Search for symbols by regular expression.\n" "sym rename \n" " Replace every occurance of a pattern in symbol names.\n" }, { .name = "isearch", .func = cmd_isearch, .help = "isearch
[options ...]\n" " Search for an instruction matching certain search terms. These\n" " terms may be any of the following:\n" " opcode \n" " byte|word|aword\n" " jump|single|double|noarg\n" " src \n" " dst \n" " srcreg \n" " dstreg \n" " srcmode R|I|S|&|@|+|#\n" " dstmode R|I|S|&|@|+|#\n" " For single-operand instructions, the operand is considered the\n" " destination operand.\n" }, { .name = "cgraph", .func = cmd_cgraph, .help = "cgraph
[function]\n" " Analyse the range given and produce a call graph. Displays a summary\n" " of all functions if no function address is given.\n" }, { .name = "exit", .func = cmd_exit, .help = "exit\n" " Exit from MSPDebug.\n" }, { .name = "simio", .func = cmd_simio, .help = "simio add [args ...]\n" " Add a new device to the IO simulator's bus.\n" "simio del \n" " Delete a device from the bus.\n" "simio devices\n" " Show all devices attached to the bus.\n" "simio classes\n" " Show the types of devices which may be attached.\n" "simio help \n" " Obtain more information about a device type.\n" "simio config [args ...]\n" " Change settings of an attached device.\n" "simio info \n" " Print status information for an attached device.\n" }, { .name = "alias", .func = cmd_alias, .help = "alias\n" " List all defined aliases.\n" "alias \n" " Remove an alias definition.\n" "alias \n" " Define a new alias.\n" }, { .name = "fill", .func = cmd_fill, .help = "fill
[b1 b2 ...]\n" " Fill the given memory range with a repeated byte sequence.\n" }, { .name = "power", .func = cmd_power, .help = "power info\n" " Show basic power statistics.\n" "power clear\n" " Clear power statistics.\n" "power all [granularity]\n" " Show all power data, optionally specifying a granularity in us.\n" "power session [granularity]\n" " Show data only for the specified session.\n" "power export-csv \n" " Write session data for the given session to a CSV file.\n" "power profile\n" " List power profile data by symbol.\n" }, #ifndef NO_SHELLCMD { .name = "!", .func = cmd_shellcmd, .help = "! [command [args ...]]\n" " Invoke an interactive shell, optionally execute command.\n" }, #endif /* !NO_SHELLCMD */ }; int cmddb_get(const char *name, struct cmddb_record *ret) { int len = strlen(name); int i; const struct cmddb_record *found = NULL; /* First look for an exact match */ for (i = 0; i < ARRAY_LEN(commands); i++) { const struct cmddb_record *r = &commands[i]; if (!strcasecmp(r->name, name)) { found = r; goto done; } } /* Allow partial matches if unambiguous */ for (i = 0; i < ARRAY_LEN(commands); i++) { const struct cmddb_record *r = &commands[i]; if (!strncasecmp(r->name, name, len)) { if (found) return -1; found = r; } } if (!found) return -1; done: memcpy(ret, found, sizeof(*ret)); return 0; } int cmddb_enum(cmddb_enum_func_t func, void *user_data) { int i; for (i = 0; i < ARRAY_LEN(commands); i++) if (func(user_data, &commands[i]) < 0) return -1; return 0; } mspdebug-0.25/ui/cmddb.h000066400000000000000000000024571313531517500151210ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef CMDDB_H_ #define CMDDB_H_ typedef int (*cmddb_func_t)(char **arg); struct cmddb_record { const char *name; cmddb_func_t func; const char *help; }; /* Fetch a command record */ int cmddb_get(const char *name, struct cmddb_record *r); /* Enumerate all command records. * * Returns 0, or -1 if an error occurs during enumeration. */ typedef int (*cmddb_enum_func_t)(void *user_data, const struct cmddb_record *r); int cmddb_enum(cmddb_enum_func_t func, void *user_data); #endif mspdebug-0.25/ui/devcmd.c000066400000000000000000000433271313531517500153060ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include #include #include "device.h" #include "binfile.h" #include "stab.h" #include "expr.h" #include "reader.h" #include "output_util.h" #include "util.h" #include "prog.h" #include "dis.h" #include "opdb.h" int cmd_regs(char **arg) { address_t regs[DEVICE_NUM_REGS]; uint8_t code[16]; int len = sizeof(code); int i; (void)arg; if (device_getregs(regs) < 0) return -1; /* Check for breakpoints */ for (i = 0; i < device_default->max_breakpoints; i++) { const struct device_breakpoint *bp = &device_default->breakpoints[i]; if ((bp->flags & DEVICE_BP_ENABLED) && (bp->type == DEVICE_BPTYPE_BREAK) && (bp->addr == regs[MSP430_REG_PC])) printc("Breakpoint %d triggered (0x%04x)\n", i, bp->addr); } show_regs(regs); /* Try to disassemble the instruction at PC */ if (len > 0x10000 - regs[0]) len = 0x10000 - regs[0]; if (device_readmem(regs[0], code, len) < 0) return 0; disassemble(regs[0], (uint8_t *)code, len, device_default->power_buf); return 0; } int cmd_md(char **arg) { char *off_text = get_arg(arg); char *len_text = get_arg(arg); address_t offset = 0; address_t length = 0x40; if (!off_text) { printc_err("md: offset must be specified\n"); return -1; } if (expr_eval(off_text, &offset) < 0) { printc_err("md: can't parse offset: %s\n", off_text); return -1; } if (len_text) { if (expr_eval(len_text, &length) < 0) { printc_err("md: can't parse length: %s\n", len_text); return -1; } } else if (offset < 0x10000 && offset + length > 0x10000) { length = 0x10000 - offset; } reader_set_repeat("md 0x%x 0x%x", offset + length, length); while (length) { uint8_t buf[4096]; int blen = length > sizeof(buf) ? sizeof(buf) : length; if (device_readmem(offset, buf, blen) < 0) return -1; hexdump(offset, buf, blen); offset += blen; length -= blen; } return 0; } int cmd_mw(char **arg) { char *off_text = get_arg(arg); char *byte_text; address_t offset = 0; address_t length = 0; uint8_t buf[1024]; if (!off_text) { printc_err("md: offset must be specified\n"); return -1; } if (expr_eval(off_text, &offset) < 0) { printc_err("md: can't parse offset: %s\n", off_text); return -1; } while ((byte_text = get_arg(arg))) { if (length >= sizeof(buf)) { printc_err("md: maximum length exceeded\n"); return -1; } buf[length++] = strtoul(byte_text, NULL, 16); } if (!length) return 0; if (device_writemem(offset, buf, length) < 0) return -1; return 0; } int cmd_reset(char **arg) { (void)arg; return device_ctl(DEVICE_CTL_RESET); } int cmd_erase(char **arg) { const char *type_text = get_arg(arg); const char *seg_text = get_arg(arg); device_erase_type_t type = DEVICE_ERASE_MAIN; address_t segment = 0; address_t total_size = 0; address_t segment_size = 0; if (seg_text && expr_eval(seg_text, &segment) < 0) { printc_err("erase: invalid expression: %s\n", seg_text); return -1; } if (type_text) { if (!strcasecmp(type_text, "all")) { type = DEVICE_ERASE_ALL; } else if (!strcasecmp(type_text, "segment")) { type = DEVICE_ERASE_SEGMENT; if (!seg_text) { printc_err("erase: expected segment " "address\n"); return -1; } } else if (!strcasecmp(type_text, "segrange")) { const char *total_text = get_arg(arg); const char *ss_text = get_arg(arg); if (!(total_text && ss_text)) { printc_err("erase: you must specify " "total and segment sizes\n"); return -1; } if (expr_eval(total_text, &total_size) < 0) { printc_err("erase: invalid expression: %s\n", total_text); return -1; } if (expr_eval(ss_text, &segment_size) < 0) { printc_err("erase: invalid expression: %s\n", ss_text); return -1; } if (segment_size > 0x200 || segment_size < 0x40) { printc_err("erase: invalid segment size: " "0x%x\n", segment_size); return -1; } } else { printc_err("erase: unknown erase type: %s\n", type_text); return -1; } } if (device_ctl(DEVICE_CTL_HALT) < 0) return -1; if (!segment_size) { printc("Erasing...\n"); return device_erase(type, segment); } else { printc("Erasing segments...\n"); while (total_size >= segment_size) { printc_dbg("Erasing 0x%04x...\n", segment); if (device_erase(DEVICE_ERASE_SEGMENT, segment) < 0) return -1; total_size -= segment_size; segment += segment_size; } } return 0; } static int bp_poll(void) { address_t regs[DEVICE_NUM_REGS]; int i; if (device_getregs(regs) < 0) return -1; for (i = 0; i < device_default->max_breakpoints; i++) { const struct device_breakpoint *bp = &device_default->breakpoints[i]; if ((bp->flags & DEVICE_BP_ENABLED) && (bp->type == DEVICE_BPTYPE_BREAK) && (bp->addr == regs[MSP430_REG_PC])) return 1; } return 0; } int cmd_step(char **arg) { char *count_text = get_arg(arg); address_t count = 1; int i; if (count_text) { if (expr_eval(count_text, &count) < 0) { printc_err("step: can't parse count: %s\n", count_text); return -1; } } for (i = 0; i < count; i++) { int r; if (device_ctl(DEVICE_CTL_STEP) < 0) return -1; r = bp_poll(); if (r < 0) return -1; if (r) { printc("Breakpoint hit after %d steps\n", i + 1); break; } } reader_set_repeat("step"); return cmd_regs(NULL); } int cmd_run(char **arg) { device_status_t status; address_t regs[DEVICE_NUM_REGS]; (void)arg; if (device_getregs(regs) < 0) { printc_err("warning: device: can't fetch registers\n"); } else { int i; for (i = 0; i < device_default->max_breakpoints; i++) { struct device_breakpoint *bp = &device_default->breakpoints[i]; if ((bp->flags & DEVICE_BP_ENABLED) && bp->type == DEVICE_BPTYPE_BREAK && bp->addr == regs[0]) break; } if (i < device_default->max_breakpoints) { printc("Stepping over breakpoint #%d at 0x%04x\n", i, regs[0]); device_ctl(DEVICE_CTL_STEP); } } if (device_ctl(DEVICE_CTL_RUN) < 0) { printc_err("run: failed to start CPU\n"); return -1; } printc("Running. Press Ctrl+C to interrupt...\n"); do { status = device_poll(); } while (status == DEVICE_STATUS_RUNNING); if (status == DEVICE_STATUS_INTR) printc("\n"); if (status == DEVICE_STATUS_ERROR) return -1; if (device_ctl(DEVICE_CTL_HALT) < 0) return -1; return cmd_regs(NULL); } int cmd_set(char **arg) { char *reg_text = get_arg(arg); char *val_text = get_arg(arg); int reg; address_t value = 0; address_t regs[DEVICE_NUM_REGS]; if (!(reg_text && val_text)) { printc_err("set: must specify a register and a value\n"); return -1; } reg = dis_reg_from_name(reg_text); if (reg < 0) { printc_err("set: unknown register: %s\n", reg_text); return -1; } if (expr_eval(val_text, &value) < 0) { printc_err("set: can't parse value: %s\n", val_text); return -1; } if (device_getregs(regs) < 0) return -1; regs[reg] = value; if (device_setregs(regs) < 0) return -1; show_regs(regs); return 0; } int cmd_dis(char **arg) { char *off_text = get_arg(arg); char *len_text = get_arg(arg); address_t offset = 0; address_t length = 0x40; uint8_t *buf; if (!off_text) { printc_err("dis: offset must be specified\n"); return -1; } if (expr_eval(off_text, &offset) < 0) { printc_err("dis: can't parse offset: %s\n", off_text); return -1; } if (len_text) { if (expr_eval(len_text, &length) < 0) { printc_err("dis: can't parse length: %s\n", len_text); return -1; } } else if (offset < 0x10000 && offset + length > 0x10000) { length = 0x10000 - offset; } buf = malloc(length); if (!buf) { pr_error("dis: couldn't allocate memory"); return -1; } if (device_readmem(offset, buf, length) < 0) { free(buf); return -1; } reader_set_repeat("dis 0x%x 0x%x", offset + length, length); disassemble(offset, buf, length, device_default->power_buf); free(buf); return 0; } #define IHEX_REC_DATA 0x00 #define IHEX_REC_EOF 0x01 #define IHEX_REC_ESAR 0x02 #define IHEX_REC_SSAR 0x03 #define IHEX_REC_ELAR 0x04 #define IHEX_REC_SLAR 0x05 #define IHEX_SEG(addr) (((addr) >> 16) & 0xFFFF) struct hexout_data { FILE *file; address_t addr; uint8_t buf[16]; int len; uint16_t segoff; }; static int hexout_start(struct hexout_data *hexout, const char *filename) { char * path = NULL; path = expand_tilde(filename); if (!path) return -1; hexout->file = fopen(path, "w"); free(path); if (!hexout->file) { pr_error("hexout: couldn't open output file"); return -1; } hexout->addr = 0; hexout->len = 0; hexout->segoff = 0; return 0; } static int hexout_write(FILE *out, uint8_t type, int len, uint16_t addr, const uint8_t *payload) { int i; int cksum = 0; if (fprintf(out, ":%02X%04X%02X", len, addr, type) < 0) goto fail; cksum += len; cksum += addr & 0xff; cksum += addr >> 8; cksum += type; for (i = 0; i < len; i++) { if (fprintf(out, "%02X", payload[i]) < 0) goto fail; cksum += payload[i]; } if (fprintf(out, "%02X\n", ~(cksum - 1) & 0xff) < 0) goto fail; return 0; fail: pr_error("hexout: can't write HEX data"); return -1; } static int hexout_flush(struct hexout_data *hexout) { while (hexout->len) { address_t addr_low = hexout->addr & 0xffff; address_t segoff = IHEX_SEG(hexout->addr); if (segoff != hexout->segoff) { uint8_t offset_data[] = {segoff >> 8, segoff & 0xff}; if (hexout_write(hexout->file, IHEX_REC_ELAR, 2, 0, offset_data) < 0) return -1; hexout->segoff = segoff; } uint32_t writesize = hexout->len; /* If the hexout buffer will wrap past the end of segment; * only write until the end of the segment to allow * emitting an ELAR record */ if (IHEX_SEG(hexout->addr + writesize) != segoff) writesize = 0x10000 - addr_low; if (hexout_write(hexout->file, IHEX_REC_DATA, writesize, addr_low, hexout->buf) < 0) return -1; hexout->len -= writesize; hexout->addr += writesize; memmove(hexout->buf, hexout->buf + writesize, sizeof(hexout->buf) - writesize); } return 0; } static int hexout_feed(struct hexout_data *hexout, uint32_t addr, const uint8_t *buf, int len) { while (len) { int count; if ((hexout->addr + hexout->len != addr || hexout->len >= sizeof(hexout->buf)) && hexout_flush(hexout) < 0) return -1; if (!hexout->len) hexout->addr = addr; count = sizeof(hexout->buf) - hexout->len; if (count > len) count = len; memcpy(hexout->buf + hexout->len, buf, count); hexout->len += count; addr += count; buf += count; len -= count; } return 0; } int cmd_hexout(char **arg) { char *off_text = get_arg(arg); char *len_text = get_arg(arg); char *filename = *arg; address_t off; address_t length; struct hexout_data hexout; if (!(off_text && len_text && *filename)) { printc_err("hexout: need offset, length and filename\n"); return -1; } if (expr_eval(off_text, &off) < 0 || expr_eval(len_text, &length) < 0) return -1; if (hexout_start(&hexout, filename) < 0) return -1; while (length) { uint8_t buf[4096]; int count = length; if (count > sizeof(buf)) count = sizeof(buf); printc("Reading %4d bytes from 0x%04x...\n", count, off); if (device_readmem(off, buf, count) < 0) { pr_error("hexout: can't read memory"); goto fail; } if (hexout_feed(&hexout, off, buf, count) < 0) goto fail; length -= count; off += count; } if (hexout_flush(&hexout) < 0) goto fail; if (hexout_write(hexout.file, IHEX_REC_EOF, 0, 0, NULL) < 0) { pr_error("hexout: failed to write terminator\n"); goto fail; } if (fclose(hexout.file) < 0) { pr_error("hexout: error on close"); return -1; } return 0; fail: fclose(hexout.file); unlink(filename); return -1; } static int cmd_prog_feed(void *user_data, const struct binfile_chunk *ch) { return prog_feed((struct prog_data *)user_data, ch); } static int do_cmd_prog(char **arg, int prog_flags) { FILE *in; struct prog_data prog; const char *path_arg; char * path; path_arg = get_arg(arg); if (!path_arg) { printc_err("prog: you need to specify a filename\n"); return -1; } if (prompt_abort(MODIFY_SYMS)) return 0; path = expand_tilde(path_arg); if (!path) return -1; in = fopen(path, "rb"); if (!in) { printc_err("prog: %s: %s\n", path, last_error()); free(path); return -1; } free(path); if (device_ctl(DEVICE_CTL_HALT) < 0) { fclose(in); return -1; } prog_init(&prog, prog_flags); if (binfile_extract(in, cmd_prog_feed, &prog) < 0) { fclose(in); return -1; } if ((prog_flags & PROG_WANT_ERASE) && (binfile_info(in) & BINFILE_HAS_SYMS)) { stab_clear(); binfile_syms(in); } fclose(in); if (prog_flush(&prog) < 0) return -1; printc("Done, %d bytes total\n", prog.total_written); if (device_ctl(DEVICE_CTL_RESET) < 0) printc_err("warning: prog: " "failed to reset after programming\n"); unmark_modified(MODIFY_SYMS); return 0; } int cmd_prog(char **arg) { return do_cmd_prog(arg, PROG_WANT_ERASE); } int cmd_load(char **arg) { return do_cmd_prog(arg, 0); } int cmd_verify(char **arg) { return do_cmd_prog(arg, PROG_VERIFY); } static int do_setbreak(device_bptype_t type, char **arg) { char *addr_text = get_arg(arg); char *index_text = get_arg(arg); int index = -1; address_t addr; if (!addr_text) { printc_err("setbreak: address required\n"); return -1; } if (expr_eval(addr_text, &addr) < 0) { printc_err("setbreak: invalid address\n"); return -1; } if (index_text) { address_t val; if (expr_eval(index_text, &val) < 0 || val >= device_default->max_breakpoints) { printc("setbreak: invalid breakpoint slot: %d\n", val); return -1; } index = val; } index = device_setbrk(device_default, index, 1, addr, type); if (index < 0) { printc_err("setbreak: all breakpoint slots are " "occupied\n"); return -1; } printc("Set breakpoint %d\n", index); return 0; } int cmd_setbreak(char **arg) { return do_setbreak(DEVICE_BPTYPE_BREAK, arg); } int cmd_setwatch(char **arg) { return do_setbreak(DEVICE_BPTYPE_WATCH, arg); } int cmd_setwatch_w(char **arg) { return do_setbreak(DEVICE_BPTYPE_WRITE, arg); } int cmd_setwatch_r(char **arg) { return do_setbreak(DEVICE_BPTYPE_READ, arg); } int cmd_delbreak(char **arg) { char *index_text = get_arg(arg); int ret = 0; if (index_text) { address_t index; if (expr_eval(index_text, &index) < 0 || index >= device_default->max_breakpoints) { printc("delbreak: invalid breakpoint slot: %d\n", index); return -1; } printc("Clearing breakpoint %d\n", index); device_setbrk(device_default, index, 0, 0, 0); } else { int i; printc("Clearing all breakpoints...\n"); for (i = 0; i < device_default->max_breakpoints; i++) device_setbrk(device_default, i, 0, 0, 0); } return ret; } int cmd_break(char **arg) { int i; (void)arg; printc("%d breakpoints available:\n", device_default->max_breakpoints); for (i = 0; i < device_default->max_breakpoints; i++) { const struct device_breakpoint *bp = &device_default->breakpoints[i]; if (bp->flags & DEVICE_BP_ENABLED) { char name[128]; print_address(bp->addr, name, sizeof(name), 0); printc(" %d. %s", i, name); switch (bp->type) { case DEVICE_BPTYPE_WATCH: printc(" [watchpoint]\n"); break; case DEVICE_BPTYPE_READ: printc(" [read watchpoint]\n"); break; case DEVICE_BPTYPE_WRITE: printc(" [write watchpoint]\n"); break; case DEVICE_BPTYPE_BREAK: printc("\n"); break; } } } return 0; } int cmd_fill(char **arg) { char *addr_text = get_arg(arg); char *len_text = get_arg(arg); char *byte_text; address_t addr = 0; address_t len = 0; uint8_t buf[256]; int period = 0; int phase = 0; int i; if (!(addr_text && len_text)) { printc_err("fill: address and length must be supplied\n"); return -1; } if (expr_eval(addr_text, &addr) < 0) { printc_err("fill: invalid address\n"); return -1; } if (expr_eval(len_text, &len) < 0) { printc_err("fill: invalid length\n"); return -1; } while ((byte_text = get_arg(arg))) { if (period >= sizeof(buf)) { printc_err("fill: maximum length exceeded\n"); return -1; } buf[period++] = strtoul(byte_text, NULL, 16); } if (!period) { printc_err("fill: no pattern supplied\n"); return -1; } for (i = period; i < sizeof(buf); i++) buf[i] = buf[i % period]; while (len > 0) { int plen = sizeof(buf) - phase; if (plen > len) plen = len; if (device_writemem(addr, buf + phase, plen) < 0) return -1; addr += plen; len -= plen; phase = (phase + plen) % period; } return 0; } int cmd_blow_jtag_fuse(char **arg) { (void)arg; if (!opdb_get_boolean("enable_fuse_blow")) { printc_err( "blow_jtag_fuse: fuse blow has not been enabled.\n" "\n" "If you really want to blow the JTAG fuse, you need to set the option\n" "\"enable_fuse_blow\" first. If in doubt, do not do this.\n" "\n" "\x1b[1mWARNING: this is in irreversible operation!\x1b[0m\n"); return -1; } return device_ctl(DEVICE_CTL_SECURE); } mspdebug-0.25/ui/devcmd.h000066400000000000000000000026261313531517500153100ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef DEVCMD_H_ #define DEVCMD_H_ int cmd_regs(char **arg); int cmd_md(char **arg); int cmd_mw(char **arg); int cmd_reset(char **arg); int cmd_erase(char **arg); int cmd_step(char **arg); int cmd_run(char **arg); int cmd_set(char **arg); int cmd_dis(char **arg); int cmd_hexout(char **arg); int cmd_prog(char **arg); int cmd_load(char **arg); int cmd_verify(char **arg); int cmd_setbreak(char **arg); int cmd_setwatch(char **arg); int cmd_setwatch_r(char **arg); int cmd_setwatch_w(char **arg); int cmd_delbreak(char **arg); int cmd_break(char **arg); int cmd_fill(char **arg); int cmd_blow_jtag_fuse(char **arg); #endif mspdebug-0.25/ui/flatfile.c000066400000000000000000000116741313531517500156320ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * Copyright (C) 2012 Ingo van Lil * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include "flatfile.h" #include #include #include #include #include #include "device.h" #include "expr.h" #include "output_util.h" enum operation { LOAD, SAVE, VERIFY }; static int read_flatfile(const char *path, uint8_t **buf, address_t *len) { FILE *in; char *fullpath = expand_tilde(path); size_t count; if (!fullpath) return -1; in = fopen(fullpath, "rb"); free(fullpath); if (!in) { printc_err("%s: %s\n", path, last_error()); return -1; } if (fseek(in, 0, SEEK_END) < 0) { printc_err("%s: can't seek to end: %s\n", path, last_error()); fclose(in); return -1; } *len = ftell(in); rewind(in); if (!*len) { *buf = malloc(1); count = 1; } else { *buf = malloc(*len); if (!*buf) { printc_err("flatfile: can't allocate memory\n"); fclose(in); return -1; } count = fread(*buf, *len, 1, in); } fclose(in); if (count != 1) { printc_err("%s: failed to read: %s\n", path, last_error()); free(*buf); *buf = NULL; return -1; } return 0; } static int write_flatfile(const char *path, uint8_t *buf, address_t len) { FILE *out; char *fullpath = expand_tilde(path); const char *errmsg = NULL; if (!fullpath) return -1; out = fopen(fullpath, "wb"); free(fullpath); if (!out) { printc_err("%s: %s\n", path, last_error()); return -1; } if (len && (fwrite(buf, len, 1, out) != 1)) errmsg = last_error(); if (fclose(out) != 0 && !errmsg) errmsg = last_error(); if (errmsg) { printc_err("%s: failed to write: %s\n", path, errmsg); return -1; } return 0; } static int do_flatfile(enum operation op, const char *path, address_t addr, address_t len) { uint8_t *in_buf = NULL; uint8_t *out_buf = NULL; int ret = -1; if (op == LOAD || op == VERIFY) { ret = read_flatfile(path, &in_buf, &len); if (ret != 0) goto out; } if (device_ctl(DEVICE_CTL_HALT) < 0) goto out; if (op == LOAD) { if (device_writemem(addr, in_buf, len) != 0) goto out; } else { out_buf = malloc(len); if (!out_buf) { printc_err("flatfile: can't allocate memory\n"); goto out; } if (device_readmem(addr, out_buf, len) != 0) goto out; } if (device_ctl(DEVICE_CTL_RESET) < 0) printc_err("warning: flatfile: " "failed to reset after programming\n"); if (op == VERIFY) { int i; for (i = 0; i < len; i++) { if (out_buf[i] != in_buf[i]) { printc("\x1b[1mERROR:\x1b[0m " "mismatch at %04x (read %02x, " "expected %02x)\n", addr + i, out_buf[i], in_buf[i]); goto out; } } ret = 0; } else if (op == SAVE) { ret = write_flatfile(path, out_buf, len); } if (ret == 0) printc("Done, %d bytes total\n", len); out: free(in_buf); free(out_buf); return ret; } int cmd_load_raw(char **arg) { const char *path, *addr_text; address_t addr; path = get_arg(arg); if (!path) { printc_err("load_raw: need file name argument\n"); return -1; } addr_text = get_arg(arg); if (!addr_text) { printc_err("load_raw: need flash address argument\n"); return -1; } else if (expr_eval(addr_text, &addr) < 0) { return -1; } return do_flatfile(LOAD, path, addr, 0); } int cmd_verify_raw(char **arg) { const char *path, *addr_text; address_t addr; path = get_arg(arg); if (!path) { printc_err("verify_raw: need file name argument\n"); return -1; } addr_text = get_arg(arg); if (!addr_text) { printc_err("verify_raw: need flash address argument\n"); return -1; } else if (expr_eval(addr_text, &addr) < 0) { return -1; } return do_flatfile(VERIFY, path, addr, 0); } int cmd_save_raw(char **arg) { const char *addr_text, *len_text, *path; address_t addr, len; addr_text = get_arg(arg); if (!addr_text) { printc_err("save_raw: need flash address argument\n"); return -1; } else if (expr_eval(addr_text, &addr) < 0) { return -1; } len_text = get_arg(arg); if (!len_text) { printc_err("save_raw: need length argument\n"); return -1; } else if (expr_eval(len_text, &len) < 0) return -1; path = get_arg(arg); if (!path) { printc_err("save_raw: need file name argument\n"); return -1; } return do_flatfile(SAVE, path, addr, len); } mspdebug-0.25/ui/flatfile.h000066400000000000000000000017261313531517500156340ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * Copyright (C) 2012 Ingo van Lil * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef FLATFILE_H_ #define FLATFILE_H_ int cmd_load_raw(char **arg); int cmd_verify_raw(char **arg); int cmd_save_raw(char **arg); #endif mspdebug-0.25/ui/gdb.c000066400000000000000000000300161313531517500145670ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include #include #include #include #include "sockets.h" #include "device.h" #include "util.h" #include "opdb.h" #include "gdb.h" #include "output.h" #include "reader.h" #include "expr.h" #include "gdb_proto.h" #include "ctrlc.h" static int register_bytes; /************************************************************************ * GDB server */ static int read_registers(struct gdb_data *data) { address_t regs[DEVICE_NUM_REGS]; int i; printc("Reading registers\n"); if (device_getregs(regs) < 0) return gdb_send(data, "E00"); gdb_packet_start(data); for (i = 0; i < DEVICE_NUM_REGS; i++) { address_t value = regs[i]; int j; for (j = 0; j < register_bytes; j++) { gdb_printf(data, "%02x", value & 0xff); value >>= 8; } } gdb_packet_end(data); return gdb_flush_ack(data); } struct monitor_buf { char buf[GDB_MAX_XFER]; int len; int trunc; }; static void monitor_capture(void *user_data, const char *text) { struct monitor_buf *mb = (struct monitor_buf *)user_data; int len = strlen(text); if (mb->trunc) return; if (mb->len + len + 64 > sizeof(mb->buf)) { text = "..."; len = strlen(text); mb->trunc = 1; } memcpy(mb->buf + mb->len, text, len); mb->len += len; mb->buf[mb->len++] = '\n'; } static int monitor_command(struct gdb_data *data, char *buf) { char cmd[128]; int len = 0; int i; struct monitor_buf mbuf; while (len + 1 < sizeof(cmd) && *buf && buf[1]) { if (len + 1 >= sizeof(cmd)) break; cmd[len++] = (hexval(buf[0]) << 4) | hexval(buf[1]); buf += 2; } cmd[len] = 0; printc("Monitor command received: %s\n", cmd); mbuf.len = 0; mbuf.trunc = 0; capture_start(monitor_capture, &mbuf); process_command(cmd); capture_end(); if (!mbuf.len) return gdb_send(data, "OK"); gdb_packet_start(data); for (i = 0; i < mbuf.len; i++) gdb_printf(data, "%02x", mbuf.buf[i]); gdb_packet_end(data); return gdb_flush_ack(data); } static int write_registers(struct gdb_data *data, char *buf) { address_t regs[DEVICE_NUM_REGS]; int i; if (strlen(buf) < DEVICE_NUM_REGS * 4) return gdb_send(data, "E00"); printc("Writing registers\n"); for (i = 0; i < DEVICE_NUM_REGS; i++) { regs[i] = (hexval(buf[2]) << 12) | (hexval(buf[3]) << 8) | (hexval(buf[0]) << 4) | hexval(buf[1]); buf += 4; } if (device_setregs(regs) < 0) return gdb_send(data, "E00"); return gdb_send(data, "OK"); } static int read_memory(struct gdb_data *data, char *text) { char *length_text = strchr(text, ','); address_t length, addr; uint8_t buf[GDB_MAX_XFER]; int i; if (!length_text) { printc_err("gdb: malformed memory read request\n"); return gdb_send(data, "E00"); } *(length_text++) = 0; length = strtoul(length_text, NULL, 16); addr = strtoul(text, NULL, 16); if (length > sizeof(buf)) length = sizeof(buf); printc("Reading %4d bytes from 0x%04x\n", length, addr); if (device_readmem(addr, buf, length) < 0) return gdb_send(data, "E00"); gdb_packet_start(data); for (i = 0; i < length; i++) gdb_printf(data, "%02x", buf[i]); gdb_packet_end(data); return gdb_flush_ack(data); } static int write_memory(struct gdb_data *data, char *text) { char *data_text = strchr(text, ':'); char *length_text = strchr(text, ','); address_t length, addr; uint8_t buf[GDB_MAX_XFER]; int buflen = 0; if (!(data_text && length_text)) { printc_err("gdb: malformed memory write request\n"); return gdb_send(data, "E00"); } *(data_text++) = 0; *(length_text++) = 0; length = strtoul(length_text, NULL, 16); addr = strtoul(text, NULL, 16); while (buflen < sizeof(buf) && *data_text && data_text[1]) { buf[buflen++] = (hexval(data_text[0]) << 4) | hexval(data_text[1]); data_text += 2; } if (buflen != length) { printc_err("gdb: length mismatch\n"); return gdb_send(data, "E00"); } printc("Writing %4d bytes to 0x%04x\n", length, addr); if (device_writemem(addr, buf, buflen) < 0) return gdb_send(data, "E00"); return gdb_send(data, "OK"); } static int run_set_pc(char *buf) { address_t regs[DEVICE_NUM_REGS]; if (!*buf) return 0; if (device_getregs(regs) < 0) return -1; regs[0] = strtoul(buf, NULL, 16); return device_setregs(regs); } static int run_final_status(struct gdb_data *data) { address_t regs[DEVICE_NUM_REGS]; int i; if (device_getregs(regs) < 0) return gdb_send(data, "E00"); gdb_packet_start(data); gdb_printf(data, "T05"); for (i = 0; i < 16; i++) { address_t value = regs[i]; int j; /* NOTE: this only gives GDB the lower 16 bits of each * register. It complains if we give the full data. */ gdb_printf(data, "%02x:", i); for (j = 0; j < register_bytes; j++) { gdb_printf(data, "%02x", value & 0xff); value >>= 8; } gdb_printf(data, ";"); } gdb_packet_end(data); return gdb_flush_ack(data); } static int single_step(struct gdb_data *data, char *buf) { printc("Single stepping\n"); if (run_set_pc(buf) < 0 || device_ctl(DEVICE_CTL_STEP) < 0) gdb_send(data, "E00"); return run_final_status(data); } static int run(struct gdb_data *data, char *buf) { printc("Running\n"); if (run_set_pc(buf) < 0 || device_ctl(DEVICE_CTL_RUN) < 0) return gdb_send(data, "E00"); for (;;) { device_status_t status = device_poll(); if (status == DEVICE_STATUS_ERROR) return gdb_send(data, "E00"); if (status == DEVICE_STATUS_HALTED) { printc("Target halted\n"); goto out; } if (status == DEVICE_STATUS_INTR) goto out; while (gdb_peek(data, 0)) { int c = gdb_getc(data); if (c < 0) return -1; if (c == 3) { printc("Interrupted by gdb\n"); goto out; } } } out: if (device_ctl(DEVICE_CTL_HALT) < 0) return gdb_send(data, "E00"); return run_final_status(data); } static int set_breakpoint(struct gdb_data *data, int enable, char *buf) { char *parts[2]; address_t addr; device_bptype_t type; int i; /* Break up the arguments */ for (i = 0; i < 2; i++) parts[i] = strsep(&buf, ","); /* Make sure there's a type argument */ if (!parts[0]) { printc_err("gdb: breakpoint requested with no type\n"); return gdb_send(data, "E00"); } switch (atoi(parts[0])) { case 0: case 1: type = DEVICE_BPTYPE_BREAK; break; case 2: type = DEVICE_BPTYPE_WRITE; break; case 3: type = DEVICE_BPTYPE_READ; break; case 4: type = DEVICE_BPTYPE_WATCH; break; default: printc_err("gdb: unsupported breakpoint type: %s\n", parts[0]); return gdb_send(data, ""); } /* There needs to be an address specified */ if (!parts[1]) { printc_err("gdb: breakpoint address missing\n"); return gdb_send(data, "E00"); } /* Parse the breakpoint address */ addr = strtoul(parts[1], NULL, 16); if (enable) { if (device_setbrk(device_default, -1, 1, addr, type) < 0) { printc_err("gdb: can't add breakpoint at " "0x%04x\n", addr); return gdb_send(data, "E00"); } printc("Breakpoint set at 0x%04x\n", addr); } else { device_setbrk(device_default, -1, 0, addr, type); printc("Breakpoint cleared at 0x%04x\n", addr); } return gdb_send(data, "OK"); } static int restart_program(struct gdb_data *data) { if (device_ctl(DEVICE_CTL_RESET) < 0) return gdb_send(data, "E00"); return gdb_send(data, "OK"); } static int gdb_send_empty_threadlist(struct gdb_data *data) { return gdb_send(data, ""); } static int gdb_send_supported(struct gdb_data *data) { gdb_packet_start(data); gdb_printf(data, "PacketSize=%x", GDB_MAX_XFER * 2); gdb_packet_end(data); return gdb_flush_ack(data); } static int process_gdb_command(struct gdb_data *data, char *buf) { #ifdef DEBUG_GDB printc("process_gdb_command: %s\n", buf); #endif switch (buf[0]) { case '?': /* Return target halt reason */ return run_final_status(data); case 'z': case 'Z': return set_breakpoint(data, buf[0] == 'Z', buf + 1); case 'r': /* Restart */ case 'R': return restart_program(data); case 'g': /* Read registers */ return read_registers(data); case 'G': /* Write registers */ return write_registers(data, buf + 1); case 'q': /* Query */ if (!strncmp(buf, "qRcmd,", 6)) return monitor_command(data, buf + 6); if (!strncmp(buf, "qSupported", 10)) { /* This is a hack to distinguish msp430-elf-gdb * from msp430-gdb. The former expects 32-bit * register fields. */ if (strstr(buf, "multiprocess+")) register_bytes = 4; return gdb_send_supported(data); } if (!strncmp(buf, "qfThreadInfo", 12)) return gdb_send_empty_threadlist(data); break; case 'm': /* Read memory */ return read_memory(data, buf + 1); case 'M': /* Write memory */ return write_memory(data, buf + 1); case 'c': /* Continue */ return run(data, buf + 1); case 's': /* Single step */ return single_step(data, buf + 1); case 'k': /* kill */ return -1; } #ifdef DEBUG_GDB printc("process_gdb_command: unknown command %s\n", buf); #endif /* For unknown/unsupported packets, return an empty reply */ return gdb_send(data, ""); } static void gdb_reader_loop(struct gdb_data *data) { while (!ctrlc_check()) { char buf[GDB_BUF_SIZE]; int len = 0; len = gdb_read_packet(data, buf); if (len < 0) return; if (len && process_gdb_command(data, buf) < 0) return; } } static int gdb_server(int port) { int sock; int client; struct sockaddr_in addr; socklen_t len; int arg; struct gdb_data data; int i; sock = socket(PF_INET, SOCK_STREAM, IPPROTO_TCP); if (SOCKET_ISERR(sock)) { pr_error("gdb: can't create socket"); return -1; } arg = 1; if (setsockopt(sock, SOL_SOCKET, SO_REUSEADDR, (void *)&arg, sizeof(arg)) < 0) pr_error("gdb: warning: can't reuse socket address"); addr.sin_family = AF_INET; addr.sin_port = htons(port); addr.sin_addr.s_addr = htonl(INADDR_ANY); if (bind(sock, (struct sockaddr *)&addr, sizeof(addr)) < 0) { printc_err("gdb: can't bind to port %d: %s\n", port, last_error()); closesocket(sock); return -1; } if (listen(sock, 1) < 0) { pr_error("gdb: can't listen on socket"); closesocket(sock); return -1; } printc("Bound to port %d. Now waiting for connection...\n", port); len = sizeof(addr); client = sockets_accept(sock, (struct sockaddr *)&addr, &len); if (SOCKET_ISERR(client)) { pr_error("gdb: failed to accept connection"); closesocket(sock); return -1; } closesocket(sock); printc("Client connected from %s:%d\n", inet_ntoa(addr.sin_addr), htons(addr.sin_port)); register_bytes = 2; gdb_init(&data, client); /* Put the hardware breakpoint setting into a known state. */ printc("Clearing all breakpoints...\n"); for (i = 0; i < device_default->max_breakpoints; i++) device_setbrk(device_default, i, 0, 0, 0); #ifdef DEBUG_GDB printc("starting GDB reader loop...\n"); #endif gdb_reader_loop(&data); #ifdef DEBUG_GDB printc("... reader loop returned\n"); #endif closesocket(client); return data.error ? -1 : 0; } int cmd_gdb(char **arg) { char *port_text = get_arg(arg); address_t port = opdb_get_numeric("gdb_default_port"); if (port_text && expr_eval(port_text, &port) < 0) { printc_err("gdb: can't parse port: %s\n", port_text); return -1; } if (port <= 0 || port > 65535) { printc_err("gdb: invalid port: %d\n", port); return -1; } do { if (gdb_server(port) < 0) return -1; } while (opdb_get_boolean("gdb_loop")); return 0; } mspdebug-0.25/ui/gdb.h000066400000000000000000000015471313531517500146030ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef GDB_H_ #define GDB_H_ int cmd_gdb(char **arg); #endif mspdebug-0.25/ui/input.c000066400000000000000000000021111313531517500151650ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include "input.h" #ifdef USE_READLINE #include "input_readline.h" /* Default input module */ const struct input_interface *input_module = &input_readline; #else #include "input_console.h" /* Default input module */ const struct input_interface *input_module = &input_console; #endif mspdebug-0.25/ui/input.h000066400000000000000000000034661313531517500152100ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef INPUT_H_ #define INPUT_H_ /* This defines the interface to an input module. The input module is * responsible for providing a way of fetching commands to be executed, * and a way of presenting yes/no questions to the user ("are you sure * you want to ...?"). */ struct input_interface { /* Initialize/tear down the input subsystem. */ int (*init)(void); void (*exit)(void); /* Read a command from the user into the supplied buffer. This * function returns 0 on success, -1 if an error occurs, and 1 * if the end of input has been reached. */ int (*read_command)(char *buf, int max_len); /* Prompt the user before performing a destructive operation. * The question should be phrased so that "yes" confirms that * the operation should proceed. * * Returns 1 for no (abort), 0 for yes (continue), and -1 if an * error occurs. */ int (*prompt_abort)(const char *message); }; /* Variable which holds a reference to the selected input module. */ extern const struct input_interface *input_module; #endif mspdebug-0.25/ui/input_async.c000066400000000000000000000075331313531517500163770ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include "input_async.h" #include "util.h" #include "ctrlc.h" #include "thread.h" #define MAX_LINE_LENGTH 1024 typedef enum { STATE_BLOCKED, STATE_RECEIVING, STATE_READY, STATE_EOF } mailbox_state_t; struct mailbox { thread_lock_t lock_ack; thread_cond_t cond_ack; int ack; thread_lock_t lock_text; thread_cond_t cond_text; int text_len; int text_eof; char text[MAX_LINE_LENGTH]; }; static struct mailbox linebox; static void handle_special(const char *text) { if (!strcmp(text, "break")) ctrlc_raise(); } static void handle_command(const char *text) { int len = strlen(text); if (len >= sizeof(linebox.text)) len = sizeof(linebox.text) - 1; /* Deliver the command to the mailbox */ thread_lock_acquire(&linebox.lock_text); memcpy(linebox.text, text, len); linebox.text[len] = 0; linebox.text_len = len; thread_lock_release(&linebox.lock_text); thread_cond_notify(&linebox.cond_text); /* Wait for ACK */ thread_lock_acquire(&linebox.lock_ack); while (!linebox.ack) thread_cond_wait(&linebox.cond_ack, &linebox.lock_ack); linebox.ack = 0; thread_lock_release(&linebox.lock_ack); } static void io_worker(void *thread_arg) { char buf[MAX_LINE_LENGTH]; (void)thread_arg; /* Read commands from stdin and dispatch them */ while (fgets(buf, sizeof(buf), stdin)) { int len = strlen(buf); while (len > 0 && isspace(buf[len - 1])) len--; buf[len] = 0; if (buf[0] == '\\') handle_special(buf + 1); else if (buf[0] == ':') handle_command(buf + 1); else handle_command(buf); } /* Deliver EOF */ thread_lock_acquire(&linebox.lock_text); linebox.text_eof = 1; thread_lock_release(&linebox.lock_text); thread_cond_notify(&linebox.cond_text); } static int async_init(void) { thread_t thr; thread_lock_init(&linebox.lock_text); thread_lock_init(&linebox.lock_ack); thread_cond_init(&linebox.cond_text); thread_cond_init(&linebox.cond_ack); linebox.text_len = -1; linebox.text_eof = 0; linebox.ack = 0; if (thread_create(&thr, io_worker, NULL) < 0) { fprintf(stderr, "async_init: failed to " "start reader thread: %s\n", last_error()); return -1; } return 0; } static void async_exit(void) { } static int async_read_command(char *buf, int max_len) { /* Wait for text or EOF */ thread_lock_acquire(&linebox.lock_text); while (!linebox.text_eof && (linebox.text_len < 0)) thread_cond_wait(&linebox.cond_text, &linebox.lock_text); if (linebox.text_eof) { thread_lock_release(&linebox.lock_text); return 1; } strncpy(buf, linebox.text, max_len); buf[max_len - 1] = 0; linebox.text_len = -1; thread_lock_release(&linebox.lock_text); /* Send ACK */ thread_lock_acquire(&linebox.lock_ack); linebox.ack = 1; thread_lock_release(&linebox.lock_ack); thread_cond_notify(&linebox.cond_ack); return 0; } static int async_prompt_abort(const char *message) { (void)message; return 0; } const struct input_interface input_async = { .init = async_init, .exit = async_exit, .read_command = async_read_command, .prompt_abort = async_prompt_abort }; mspdebug-0.25/ui/input_async.h000066400000000000000000000017021313531517500163740ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef INPUT_ASYNC_H_ #define INPUT_ASYNC_H_ #include "input.h" /* Asynchronous input reader */ extern const struct input_interface input_async; #endif mspdebug-0.25/ui/input_console.c000066400000000000000000000043441313531517500167210ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include #include "input_console.h" #include "util.h" #define LINE_BUF_SIZE 128 static char *readline(const char *prompt) { char *buf = malloc(LINE_BUF_SIZE); if (!buf) { fprintf(stdout, "readline: can't allocate memory: %s\n", last_error()); return NULL; } for (;;) { printf("%s", prompt); fflush(stdout); if (fgets(buf, LINE_BUF_SIZE, stdin)) { int len = strlen(buf); while (len > 0 && isspace(buf[len - 1])) len--; buf[len] = 0; return buf; } if (feof(stdin)) break; printf("\n"); } free(buf); return NULL; } static int console_init(void) { return 0; } static void console_exit(void) { } static int console_read_command(char *out, int max_len) { char *buf = readline("(mspdebug) "); if (!buf) { printf("\n"); return 1; } strncpy(out, buf, max_len); out[max_len - 1] = 0; free(buf); return 0; } static int console_prompt_abort(const char *message) { char buf[32]; for (;;) { printf("%s ", message); fflush(stdout); if (!fgets(buf, sizeof(buf), stdin)) { printf("\n"); return 1; } if (toupper(buf[0]) == 'Y') return 0; if (toupper(buf[0]) == 'N') return 1; printf("Please answer \"y\" or \"n\".\n"); } return 0; } const struct input_interface input_console = { .init = console_init, .exit = console_exit, .read_command = console_read_command, .prompt_abort = console_prompt_abort }; mspdebug-0.25/ui/input_console.h000066400000000000000000000016501313531517500167230ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef INPUT_CONSOLE_H_ #define INPUT_CONSOLE_H_ #include "input.h" extern const struct input_interface input_console; #endif mspdebug-0.25/ui/input_readline.c000066400000000000000000000234731313531517500170460ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2016 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include #include #include #include "input_readline.h" #include "cmddb.h" #include "opdb.h" #include "stab.h" #include "util.h" #define HISTORY_FILENAME "~/.mspdebug_history" struct find_context { const char *search_text; const char *skip_until; const char *result; }; static int cmddb_find_command(void *user_data, const struct cmddb_record *r) { struct find_context *find_data = user_data; if (find_data->skip_until) { if (r->name == find_data->skip_until) find_data->skip_until = NULL; } else if (!find_data->result) { size_t len = strlen(find_data->search_text); if (strncasecmp(r->name, find_data->search_text, len) == 0) find_data->result = r->name; } return 0; } static char *command_generator(const char *text, int state) { static struct find_context find_data; if (state == 0) { // start a new search find_data.search_text = text; find_data.skip_until = NULL; } else { // continue searching after the last match find_data.skip_until = find_data.result; } find_data.result = NULL; cmddb_enum(cmddb_find_command, &find_data); if (find_data.result) return strdup(find_data.result); return NULL; } static int opdb_find_option(void *user_data, const struct opdb_key *key, const union opdb_value *value) { (void)value; struct find_context *find_data = user_data; if (find_data->skip_until) { if (key->name == find_data->skip_until) find_data->skip_until = NULL; } else if (!find_data->result) { size_t len = strlen(find_data->search_text); if (strncasecmp(key->name, find_data->search_text, len) == 0) find_data->result = key->name; } return 0; } static char *option_generator(const char *text, int state) { static struct find_context find_data; if (state == 0) { // start a new search find_data.search_text = text; find_data.skip_until = NULL; } else { // continue searching after the last match find_data.skip_until = find_data.result; } find_data.result = NULL; opdb_enum(opdb_find_option, &find_data); if (find_data.result) return strdup(find_data.result); return NULL; } static int stab_find_symbol(void *user_data, const char *name, address_t value) { (void)value; struct find_context *find_data = user_data; if (find_data->skip_until) { if (strcmp(name, find_data->skip_until) == 0) find_data->skip_until = NULL; } else if (!find_data->result) { size_t len = strlen(find_data->search_text); if (strncmp(name, find_data->search_text, len) == 0) { // name is stack-allocated and becomes invalid after // returning, so we copy it to a static buffer. static char buffer[MAX_SYMBOL_LENGTH]; snprintf(buffer, sizeof(buffer), "%s", name); find_data->result = buffer; } } return 0; } static char *symbol_generator(const char *text, int state) { static struct find_context find_data; if (state == 0) { // start a new search find_data.search_text = text; find_data.skip_until = NULL; } else { // continue searching after the last match find_data.skip_until = find_data.result; } find_data.result = NULL; stab_enum(stab_find_symbol, &find_data); if (find_data.result) return strdup(find_data.result); return NULL; } static char *array_generator(const char *text, int state, const char **array) { static const char **array_ptr; if (state == 0) { array_ptr = array; } else { ++array_ptr; } while (*array_ptr) { if (strncasecmp(*array_ptr, text, strlen(text)) == 0) return strdup(*array_ptr); array_ptr++; } return NULL; } static rl_compentry_func_t *complete_addrcmd(char **arg, const char *line, int start) { const char *token = get_arg(arg); if (token == NULL || token == line + start) return symbol_generator; return NULL; } static char *erase_subcmd_generator(const char *text, int state) { const char *subcmds[] = { "all", "segment", "segrange", NULL }; return array_generator(text, state, subcmds); } static rl_compentry_func_t *complete_erase(char **arg, const char *line, int start) { const char *subcmd = get_arg(arg); if (subcmd == NULL || subcmd == line + start) return erase_subcmd_generator; else return complete_addrcmd(arg, line, start); } static rl_compentry_func_t *complete_help(char **arg, const char *line, int start) { const char *topic = get_arg(arg); if (topic == NULL || topic == line + start) return command_generator; return NULL; } static rl_compentry_func_t *complete_loadraw(char **arg, const char *line, int start) { const char *filename_arg = get_arg(arg); if (filename_arg == NULL || filename_arg == line + start) return NULL; // default filename completion else return complete_addrcmd(arg, line, start); } static rl_compentry_func_t *complete_opt(char **arg, const char *line, int start) { const char *opt_text = get_arg(arg); if (opt_text == NULL || opt_text == line + start) return option_generator; return NULL; } static char *power_subcmd_generator(const char *text, int state) { const char *subcmds[] = { "info", "clear", "all", "session", "export-csv", "profile", NULL }; return array_generator(text, state, subcmds); } static rl_compentry_func_t *complete_power(char **arg, const char *line, int start) { const char *subcmd = get_arg(arg); if (subcmd == NULL || subcmd == line + start) return power_subcmd_generator; return NULL; } static char *simio_subcmd_generator(const char *text, int state) { const char *subcmds[] = { "add", "del", "devices", "classes", "help", "config", "info", NULL }; return array_generator(text, state, subcmds); } static rl_compentry_func_t *complete_simio(char **arg, const char *line, int start) { const char *subcmd = get_arg(arg); if (subcmd == NULL || subcmd == line + start) return simio_subcmd_generator; return NULL; } static char *sym_subcmd_generator(const char *text, int state) { const char *subcmds[] = { "clear", "set", "del", "import", "import+", "export", "find", "rename", NULL }; return array_generator(text, state, subcmds); } static rl_compentry_func_t *complete_sym(char **arg, const char *line, int start) { const char *subcmd = get_arg(arg); if (subcmd == NULL || subcmd == line + start) return sym_subcmd_generator; else if (strcasecmp(subcmd, "set") == 0 || strcasecmp(subcmd, "del") == 0 || strcasecmp(subcmd, "find") == 0) return complete_addrcmd(arg, line, start); return NULL; } struct cmd_completer { const char *name; rl_compentry_func_t *(*completer)(char **arg, const char *line, int start); }; static const struct cmd_completer cmd_completers[] = { { "cgraph", complete_addrcmd }, { "dis", complete_addrcmd }, { "erase", complete_erase }, { "fill", complete_addrcmd }, { "help", complete_help }, { "hexout", complete_addrcmd }, { "isearch", complete_addrcmd }, { "load_raw", complete_loadraw }, { "md", complete_addrcmd }, { "mw", complete_addrcmd }, { "opt", complete_opt }, { "power", complete_power }, { "save_raw", complete_addrcmd }, { "setbreak", complete_addrcmd }, { "setwatch", complete_addrcmd }, { "setwatch_r", complete_addrcmd }, { "setwatch_w", complete_addrcmd }, { "simio", complete_simio }, { "sym", complete_sym }, { "verify_raw", complete_loadraw }, { NULL, NULL } }; static char **mspdebug_completion(const char *text, int start, int end) { rl_compentry_func_t *generator = NULL; // copy the current command line, terminate at cursor position char *line = strdup(rl_line_buffer); line[end] = '\0'; char *arg = line; const char *cmd_text = get_arg(&arg); struct cmddb_record cmd; if (cmd_text == NULL || cmd_text == line + start) generator = command_generator; else if (!cmddb_get(cmd_text, &cmd)) { const struct cmd_completer *c = cmd_completers; while (c->name) { if (!strcmp(cmd.name, c->name)) { generator = c->completer(&arg, line, start); break; } c++; } } free(line); if (generator) return rl_completion_matches(text, generator); return NULL; } static int readline_init(void) { char *path = expand_tilde(HISTORY_FILENAME); if (path) { read_history(path); free(path); } rl_attempted_completion_function = mspdebug_completion; return 0; } static void readline_exit(void) { char *path = expand_tilde(HISTORY_FILENAME); if (path) { write_history(path); free(path); } } static int readline_read_command(char *out, int max_len) { char *buf = readline("(mspdebug) "); if (!buf) { printf("\n"); return 1; } if (*buf) add_history(buf); strncpy(out, buf, max_len); out[max_len - 1] = 0; free(buf); return 0; } static int readline_prompt_abort(const char *message) { char buf[32]; for (;;) { printf("%s ", message); fflush(stdout); if (!fgets(buf, sizeof(buf), stdin)) { printf("\n"); return 1; } if (toupper(buf[0]) == 'Y') return 0; if (toupper(buf[0]) == 'N') return 1; printf("Please answer \"y\" or \"n\".\n"); } return 0; } const struct input_interface input_readline = { .init = readline_init, .exit = readline_exit, .read_command = readline_read_command, .prompt_abort = readline_prompt_abort }; mspdebug-0.25/ui/input_readline.h000066400000000000000000000016531313531517500170470ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2016 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef INPUT_READLINE_H_ #define INPUT_READLINE_H_ #include "input.h" extern const struct input_interface input_readline; #endif mspdebug-0.25/ui/main.c000066400000000000000000000276121313531517500147670ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2017 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include #include #include #include "dis.h" #include "device.h" #include "binfile.h" #include "stab.h" #include "util.h" #include "usbutil.h" #include "gdb.h" #include "rtools.h" #include "sym.h" #include "devcmd.h" #include "expr.h" #include "opdb.h" #include "reader.h" #include "output.h" #include "output_util.h" #include "simio.h" #include "ctrlc.h" #include "sim.h" #include "bsl.h" #include "fet.h" #include "vector.h" #include "fet_db.h" #include "fet_olimex_db.h" #include "flash_bsl.h" #include "gdbc.h" #include "tilib.h" #include "goodfet.h" #include "input.h" #include "input_async.h" #include "pif.h" #include "loadbsl.h" #include "fet3.h" #include "rom_bsl.h" #include "chipinfo.h" #ifdef __CYGWIN__ #include #endif #define OPT_NO_RC 0x01 #define OPT_EMBEDDED 0x02 struct cmdline_args { const char *driver_name; const char *alt_config; int flags; struct device_args devarg; }; static const struct device_class *const driver_table[] = { &device_rf2500, &device_olimex, &device_olimex_v1, &device_olimex_iso, &device_olimex_iso_mk2, &device_sim, &device_uif, &device_bsl, &device_flash_bsl, &device_gdbc, &device_tilib, &device_goodfet, &device_pif, &device_gpio, &device_loadbsl, &device_ezfet, &device_rom_bsl, &device_bp }; static const char *version_text = "MSPDebug version 0.25 - debugging tool for MSP430 MCUs\n" "Copyright (C) 2009-2017 Daniel Beer \n" "This is free software; see the source for copying conditions. There is NO\n" "warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR " "PURPOSE.\n"; static void usage(const char *progname) { int i; printc("Usage: %s [options] [command ...]\n" "\n" " -q\n" " Start in quiet mode.\n" " -d device\n" " Connect via the given tty device, rather than USB.\n" " -U bus:dev\n" " Specify a particular USB device to connect to.\n" " -s serial\n" " Specify a particular device serial number to connect to.\n" " -j\n" " Use JTAG, rather than Spy-Bi-Wire (UIF devices only).\n" " -v voltage\n" " Set the supply voltage, in millivolts.\n" " -n\n" " Do not read a configuration file on startup.\n" " -C \n" " Load an alternative configuration file.\n" " --long-password\n" " Send 32-byte IVT as BSL password (flash-bsl only)\n" " --help\n" " Show this help text.\n" " --fet-list\n" " Show a list of devices supported by the FET driver.\n" " --fet-force-id string\n" " Override the device ID returned by the FET.\n" " --fet-skip-close\n" " Skip the JTAG close procedure when using the FET driver.\n" " --usb-list\n" " Show a list of available USB devices.\n" " --force-reset\n" " Force target reset in initialization sequence.\n" " --allow-fw-update\n" " Update FET firmware (tilib only) if necessary.\n" " --require-fw-update \n" " Require FET firmware update. The required image format depends\n" " on the driver.\n" " --version\n" " Show copyright and version information.\n" " --embedded\n" " Run in embedded mode.\n" " --bsl-entry-sequence \n" " Specify a BSL entry sequence. Each character specifies a modem\n" " control line transition (R: RTS on, r: RTS off, D: DTR on, \n" " d: DTR off).\n" " --bsl-gpio-rts\n" " On some host (say RaspberryPi) defines a GPIO pin# to be used as RTS\n" " --bsl-gpio-dtr\n" " On some host (say RaspberryPi) defines a GPIO pin# to be used as DTR\n" "\n" "Most drivers connect by default via USB, unless told otherwise via the\n" "-d option. By default, the first USB device found is opened.\n" "\n" "If commands are given, they will be executed. Otherwise, an interactive\n" "command reader is started.\n\n", progname); printc("Available drivers are:\n"); for (i = 0; i < ARRAY_LEN(driver_table); i++) { const struct device_class *drv = driver_table[i]; printc(" %s\n %s\n", drv->name, drv->help); } } static void process_rc_file(const char *config) { char text[256]; if (!config) { if (!access(".mspdebug", F_OK)) { config = ".mspdebug"; } else { const char *home = getenv("HOME"); if (home) { snprintf(text, sizeof(text), "%s/.mspdebug", home); if (!access(text, F_OK)) config = text; } } } if (config) process_file(config, 0); } static int add_fet_device(void *user_data, const struct fet_db_record *r) { struct vector *v = (struct vector *)user_data; return vector_push(v, &r->name, 1); } static int add_fet_olimex_device(void *user_data, const char *name) { struct vector *v = (struct vector *)user_data; return vector_push(v, &name, 1); } static int list_devices(void) { struct vector v; vector_init(&v, sizeof(const char *)); if (fet_db_enum(add_fet_device, &v) < 0) { pr_error("couldn't allocate memory"); vector_destroy(&v); return -1; } printc("Devices supported by FET driver:\n"); namelist_print(&v); vector_destroy(&v); vector_init(&v, sizeof(const char *)); if (fet_olimex_db_enum(add_fet_olimex_device, &v) < 0) { pr_error("couldn't allocate memory"); vector_destroy(&v); return -1; } printc("\n"); printc("Devices supported by Olimex FET driver:\n"); namelist_print(&v); vector_destroy(&v); return 0; } static int parse_cmdline_args(int argc, char **argv, struct cmdline_args *args) { enum { LOPT_HELP = 0x100, LOPT_FET_LIST, LOPT_FET_FORCE_ID, LOPT_FET_SKIP_CLOSE, LOPT_USB_LIST, LOPT_VERSION, LOPT_LONG_PASSWORD, LOPT_FORCE_RESET, LOPT_ALLOW_FW_UPDATE, LOPT_REQUIRE_FW_UPDATE, LOPT_EMBEDDED, LOPT_BSL_ENTRY_SEQUENCE, LOPT_BSL_GPIO_RTS, LOPT_BSL_GPIO_DTR, }; static const struct option longopts[] = { {"help", 0, 0, LOPT_HELP}, {"fet-list", 0, 0, LOPT_FET_LIST}, {"fet-force-id", 1, 0, LOPT_FET_FORCE_ID}, {"fet-skip-close", 0, 0, LOPT_FET_SKIP_CLOSE}, {"usb-list", 0, 0, LOPT_USB_LIST}, {"version", 0, 0, LOPT_VERSION}, {"long-password", 0, 0, LOPT_LONG_PASSWORD}, {"force-reset", 0, 0, LOPT_FORCE_RESET}, {"allow-fw-update", 0, 0, LOPT_ALLOW_FW_UPDATE}, {"require-fw-update", 1, 0, LOPT_REQUIRE_FW_UPDATE}, {"embedded", 0, 0, LOPT_EMBEDDED}, {"bsl-entry-sequence", 1, 0, LOPT_BSL_ENTRY_SEQUENCE}, {"bsl-gpio-rts", 1, 0, LOPT_BSL_GPIO_RTS}, {"bsl-gpio-dtr", 1, 0, LOPT_BSL_GPIO_DTR}, {NULL, 0, 0, 0} }; int opt; int want_usb = 0; while ((opt = getopt_long(argc, argv, "d:jv:nU:s:qC:", longopts, NULL)) >= 0) switch (opt) { case 'C': args->alt_config = optarg; break; case 'q': { static const union opdb_value v = { .boolean = 1 }; opdb_set("quiet", &v); } break; case LOPT_BSL_ENTRY_SEQUENCE: args->devarg.bsl_entry_seq = optarg; break; case LOPT_BSL_GPIO_RTS: args->devarg.bsl_gpio_used = 1; args->devarg.bsl_gpio_rts = atoi ( optarg ); break; case LOPT_BSL_GPIO_DTR: args->devarg.bsl_gpio_used = 1; args->devarg.bsl_gpio_dtr = atoi ( optarg ); break; case LOPT_EMBEDDED: args->flags |= OPT_EMBEDDED; break; case LOPT_ALLOW_FW_UPDATE: args->devarg.flags |= DEVICE_FLAG_DO_FWUPDATE; break; case LOPT_USB_LIST: usb_init(); usb_find_busses(); usb_find_devices(); usbutil_list(); exit(0); case 'd': args->devarg.path = optarg; args->devarg.flags |= DEVICE_FLAG_TTY; break; case LOPT_REQUIRE_FW_UPDATE: args->devarg.require_fwupdate = optarg; break; case 'U': args->devarg.path = optarg; want_usb = 1; break; case 's': args->devarg.requested_serial = optarg; break; case LOPT_FET_LIST: exit(list_devices()); case LOPT_FET_FORCE_ID: args->devarg.forced_chip_id = optarg; break; case LOPT_FET_SKIP_CLOSE: args->devarg.flags |= DEVICE_FLAG_SKIP_CLOSE; break; case LOPT_HELP: usage(argv[0]); exit(0); case LOPT_VERSION: printc("%s", version_text); printc("%s", chipinfo_copyright()); exit(0); case 'v': args->devarg.vcc_mv = atoi(optarg); break; case 'j': args->devarg.flags |= DEVICE_FLAG_JTAG; break; case 'n': args->flags |= OPT_NO_RC; break; case LOPT_LONG_PASSWORD: args->devarg.flags |= DEVICE_FLAG_LONG_PW; break; case LOPT_FORCE_RESET: args->devarg.flags |= DEVICE_FLAG_FORCE_RESET; break; case '?': printc_err("Try --help for usage information.\n"); return -1; } if (want_usb && (args->devarg.flags & DEVICE_FLAG_TTY)) { printc_err("You can't simultaneously specify a serial and " "a USB device.\n"); return -1; } if (optind >= argc) { printc_err("You need to specify a driver. Try --help for " "a list.\n"); return -1; } args->driver_name = argv[optind]; optind++; return 0; } int setup_driver(struct cmdline_args *args) { int i; i = 0; while (i < ARRAY_LEN(driver_table) && strcasecmp(driver_table[i]->name, args->driver_name)) i++; if (i >= ARRAY_LEN(driver_table)) { printc_err("Unknown driver: %s. Try --help for a list.\n", args->driver_name); return -1; } if (stab_init() < 0) return -1; device_default = driver_table[i]->open(&args->devarg); if (!device_default) { stab_exit(); return -1; } return 0; } #ifdef __Windows__ static int sockets_init(void) { WSADATA data; if (WSAStartup(MAKEWORD(2, 2), &data)) { printc_err("Winsock init failed"); return -1; } return 0; } static void sockets_exit(void) { WSACleanup(); } #else static int sockets_init(void) { return 0; } static void sockets_exit(void) { } #endif int main(int argc, char **argv) { struct cmdline_args args = {0}; int ret = 0; setvbuf(stderr, NULL, _IOFBF, 0); setvbuf(stdout, NULL, _IOFBF, 0); opdb_reset(); ctrlc_init(); args.devarg.vcc_mv = 3000; args.devarg.requested_serial = NULL; if (parse_cmdline_args(argc, argv, &args) < 0) goto fail_parse; if (args.flags & OPT_EMBEDDED) input_module = &input_async; if (input_module->init() < 0) goto fail_input; output_set_embedded(args.flags & OPT_EMBEDDED); if (sockets_init() < 0) { ret = -1; goto fail_sockets; } printc_dbg("%s", version_text); printc_dbg("%s\n", chipinfo_copyright()); if (setup_driver(&args) < 0) { ret = -1; goto fail_driver; } if (device_probe_id(device_default, args.devarg.forced_chip_id) < 0) printc_err("warning: device ID probe failed\n"); simio_init(); if (!(args.flags & OPT_NO_RC)) process_rc_file(args.alt_config); /* Process commands */ if (optind < argc) { while (optind < argc) { if (process_command(argv[optind++]) < 0) { ret = -1; break; } } } else { reader_loop(); } simio_exit(); device_destroy(); stab_exit(); fail_driver: sockets_exit(); fail_sockets: input_module->exit(); fail_input: fail_parse: /* We need to do this on Windows, because in embedded mode we * may still have a running background thread for input. If so, * returning from main() won't cause the process to terminate. */ #if defined(__CYGWIN__) cygwin_internal(CW_EXIT_PROCESS, (ret == 0) ? EXIT_SUCCESS : EXIT_FAILURE, 1); #elif defined(__Windows__) ExitProcess(ret); #endif return ret; } mspdebug-0.25/ui/power.c000066400000000000000000000211621313531517500151710ustar00rootroot00000000000000/* MSPDebug - debugging tool MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include "util.h" #include "stab.h" #include "output.h" #include "output_util.h" #include "device.h" #include "power.h" #include "powerbuf.h" static void print_header(powerbuf_t pb, unsigned int s) { unsigned int length; const struct powerbuf_session *rec = powerbuf_session_info(pb, s, &length); printc("Session #%d: %s", s, ctime(&rec->wall_clock)); printc("%d samples (spanning %.03f ms)\n", length, (double)(length * pb->interval_us) / 1000.0); printc("%.01f uA average (%.01f uAs total charge)\n", (double)rec->total_ua / (double)length, (double)(rec->total_ua * pb->interval_us) / 1000000.0); } static void dump_session_data(powerbuf_t pb, unsigned int s, unsigned int gran) { unsigned int length; const struct powerbuf_session *rec = powerbuf_session_info(pb, s, &length); unsigned int i; int idx; print_header(pb, s); printc("\n"); printc("%15s %15s %-15s\n", "Time (us)", "Current (uA)", "MAB"); printc("------------------------------------------------\n"); idx = rec->start_index; for (i = 0; i + gran <= length; i += gran) { address_t mab = pb->mab[idx]; unsigned long ua_tot = 0; char addr[128]; int j; for (j = 0; j < gran; j++) { ua_tot += pb->current_ua[idx]; idx = (idx + 1) % pb->max_samples; } print_address(mab, addr, sizeof(addr), 0); printc("%15d %15.01f %s\n", i * pb->interval_us, ((double)ua_tot) / (double)gran, addr); } printc("\n"); } static int sc_info(powerbuf_t pb) { int sess_num = powerbuf_num_sessions(pb); int i; printc("Sample granularity is %d us\n", pb->interval_us); printc("%d sessions:\n", sess_num); for (i = sess_num - 1; i >= 0; i--) { printc("\n"); print_header(pb, i); } return 0; } static int sc_clear(powerbuf_t pb) { powerbuf_clear(pb); return 0; } static int parse_granularity(powerbuf_t pb, char **arg, int *gran_out) { const char *text = get_arg(arg); int request = 10000; int gran; if (text) request = atoi(text); if (request <= 0) { printc_err("power: invalid granularity: %d us\n", request); return -1; } gran = (request + (pb->interval_us / 2)) / pb->interval_us; if (gran <= 0) gran = 1; *gran_out = gran; return 0; } static int sc_all(powerbuf_t pb, char **arg) { int i; int gran; if (parse_granularity(pb, arg, &gran) < 0) return -1; for (i = powerbuf_num_sessions(pb) - 1; i >= 0; i--) dump_session_data(pb, i, gran); return 0; } static int sc_session(powerbuf_t pb, char **arg) { const char *sess_text = get_arg(arg); int sess; int gran; if (!sess_text) { printc_err("power: you must specify a session number\n"); return -1; } sess = atoi(sess_text); if (sess < 0 || sess >= powerbuf_num_sessions(pb)) { printc_err("power: invalid session: %d\n", sess); return -1; } if (parse_granularity(pb, arg, &gran) < 0) return -1; dump_session_data(pb, sess, gran); return 0; } static int sc_export_csv(powerbuf_t pb, char **arg) { const char *sess_text = get_arg(arg); const char *filename = get_arg(arg); unsigned int length; const struct powerbuf_session *rec; FILE *out; int sess; unsigned int i; if (!(sess_text && filename)) { printc_err("power: expected a session number and filename\n"); return -1; } sess = atoi(sess_text); if (sess < 0 || sess >= powerbuf_num_sessions(pb)) { printc_err("power: invalid session: %d\n", sess); return -1; } rec = powerbuf_session_info(pb, sess, &length); out = fopen(filename, "w"); if (!out) { printc_err("power: can't open %s: %s\n", filename, last_error()); return -1; } for (i = 0; i < length; i++) { const unsigned int idx = (rec->start_index + i) % pb->max_samples; if (fprintf(out, "%15d,%15d, 0x%05x\n", i * pb->interval_us, pb->current_ua[idx], pb->mab[idx]) < 0) { printc_err("power: write error: %s: %s\n", filename, last_error()); fclose(out); return -1; } } if (fclose(out) < 0) { printc_err("power: error on close of %s: %s\n", filename, last_error()); return -1; } printc("Exported %d samples to %s\n", length, filename); return 0; } struct profile_rec { char name[64]; address_t addr; unsigned long long charge; int samples; }; static int add_symbol(void *user_data, const char *name, address_t offset) { struct vector *v = (struct vector *)user_data; struct profile_rec rec; strncpy(rec.name, name, sizeof(rec.name)); rec.name[sizeof(rec.name) - 1] = 0; rec.addr = offset; rec.charge = 0; rec.samples = 0; return vector_push(v, &rec, 1); } static void merge_power(struct vector *list, powerbuf_t pb) { int num_samples = (pb->current_head + pb->max_samples - pb->current_tail) % pb->max_samples; int dst = 0; int src = 0; /* Skip samples that don't match any known symbol */ while ((dst < list->size) && (src < num_samples) && (pb->mab[pb->sorted[src]] < VECTOR_PTR(*list, dst, struct profile_rec)->addr)) src++; while ((dst < list->size) && (src < num_samples)) { address_t mab = pb->mab[pb->sorted[src]]; unsigned int ua = pb->current_ua[pb->sorted[src]]; if ((dst + 1 < list->size) && (VECTOR_PTR(*list, dst + 1, struct profile_rec)->addr <= mab)) { dst++; } else { struct profile_rec *r = VECTOR_PTR(*list, dst, struct profile_rec); r->charge += ua; r->samples++; src++; } } } static int cmp_by_addr(const void *a, const void *b) { const struct profile_rec *pa = (const struct profile_rec *)a; const struct profile_rec *pb = (const struct profile_rec *)b; if (pa->addr < pb->addr) return -1; if (pa->addr > pb->addr) return 1; return 0; } static int cmp_by_charge_rev(const void *a, const void *b) { const struct profile_rec *pa = (const struct profile_rec *)a; const struct profile_rec *pb = (const struct profile_rec *)b; if (pa->charge < pb->charge) return 1; if (pa->charge > pb->charge) return -1; return 0; } static void print_profile(int interval_us, const struct vector *list) { int i; printc("%-7s %-15s %15s %15s %15s\n", "Addr", "Name", "Charge (uAs)", "Time (ms)", "Current (uA)"); printc("---------------------------------------" "---------------------------------\n"); for (i = 0; i < list->size; i++) { const struct profile_rec *r = VECTOR_PTR(*list, i, const struct profile_rec); if (!r->samples) continue; printc("0x%05x %-15s %15.01f %15.01f %15.01f\n", r->addr, r->name, (double)(r->charge * interval_us) / 1000000.0, (double)(r->samples * interval_us) / 1000.0, (double)r->charge / (double)r->samples); } } static int sc_profile(powerbuf_t pb) { struct vector list; /* First, assemble a list of symbols */ vector_init(&list, sizeof(struct profile_rec)); if (stab_enum(add_symbol, &list) < 0) { printc_err("Out of memory: %s\n", last_error()); vector_destroy(&list); return -1; } /* Merge in power profile samples */ qsort(list.ptr, list.size, list.elemsize, cmp_by_addr); powerbuf_sort(pb); merge_power(&list, pb); /* Prepare and print profile */ qsort(list.ptr, list.size, list.elemsize, cmp_by_charge_rev); print_profile(pb->interval_us, &list); vector_destroy(&list); return 0; } int cmd_power(char **arg) { powerbuf_t pb = device_default->power_buf; char *subcmd = get_arg(arg); if (!pb) { printc_err("power: power profiling is not supported " "by this device.\n"); return -1; } if (!subcmd) { printc_err("power: need to specify a subcommand " "(try \"help power\")\n"); return -1; } if (!strcasecmp(subcmd, "info")) return sc_info(pb); if (!strcasecmp(subcmd, "clear")) return sc_clear(pb); if (!strcasecmp(subcmd, "all")) return sc_all(pb, arg); if (!strcasecmp(subcmd, "session")) return sc_session(pb, arg); if (!strcasecmp(subcmd, "export-csv")) return sc_export_csv(pb, arg); if (!strcasecmp(subcmd, "profile")) return sc_profile(pb); printc_err("power: unknown subcommand: %s (try \"help power\")\n", subcmd); return -1; } mspdebug-0.25/ui/power.h000066400000000000000000000015501313531517500151750ustar00rootroot00000000000000/* MSPDebug - debugging tool MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef POWER_H_ #define POWER_H_ int cmd_power(char **arg); #endif mspdebug-0.25/ui/reader.c000066400000000000000000000075331313531517500153050ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include #include #include "vector.h" #include "util.h" #include "output.h" #include "cmddb.h" #include "stdcmd.h" #include "reader.h" #include "opdb.h" #include "aliasdb.h" #include "ctrlc.h" #include "input.h" #define MAX_READER_LINE 1024 static int modify_flags; static int in_reader_loop; static int want_exit; static char repeat_buf[MAX_READER_LINE]; void mark_modified(int flags) { modify_flags |= flags; } void unmark_modified(int flags) { modify_flags &= ~flags; } int prompt_abort(int flags) { if (!(in_reader_loop && (modify_flags & flags))) return 0; return input_module->prompt_abort("Symbols have not been saved " "since modification. Continue (y/n)?"); } static int do_command(char *arg, int interactive) { const char *cmd_text; int len = strlen(arg); while (len && isspace(arg[len - 1])) len--; arg[len] = 0; cmd_text = get_arg(&arg); if (cmd_text) { char translated[1024]; struct cmddb_record cmd; if (translate_alias(cmd_text, arg, translated, sizeof(translated)) < 0) return -1; arg = translated; cmd_text = get_arg(&arg); /* Allow ^[# to stash a command in history without * attempting to execute */ if (*cmd_text == '#') return 0; if (!cmddb_get(cmd_text, &cmd)) { int old = in_reader_loop; int ret; in_reader_loop = interactive; ret = cmd.func(&arg); in_reader_loop = old; return ret; } printc_err("unknown command: %s (try \"help\")\n", cmd_text); return -1; } return 0; } void reader_exit(void) { want_exit = 1; } void reader_set_repeat(const char *fmt, ...) { va_list ap; va_start(ap, fmt); vsnprintf(repeat_buf, sizeof(repeat_buf), fmt, ap); va_end(ap); } void reader_loop(void) { int old = in_reader_loop; in_reader_loop = 1; if (!opdb_get_boolean("quiet")) { printc("\n"); cmd_help(NULL); printc("\n"); } do { want_exit = 0; for (;;) { char tmpbuf[MAX_READER_LINE]; char *buf = tmpbuf; printc_shell("ready\n"); if (input_module->read_command(tmpbuf, sizeof(tmpbuf))) break; if (*buf) repeat_buf[0] = 0; else memcpy(tmpbuf, repeat_buf, sizeof(tmpbuf)); ctrlc_clear(); printc_shell("busy\n"); do_command(buf, 1); if (want_exit) break; } } while (prompt_abort(MODIFY_SYMS)); in_reader_loop = old; } int process_command(char *cmd) { return do_command(cmd, 0); } int process_file(const char *filename, int show) { FILE *in; char buf[1024], *path; int line_no = 0; path = expand_tilde(filename); if (!path) return -1; in = fopen(path, "r"); free(path); if (!in) { printc_err("read: can't open %s: %s\n", filename, last_error()); return -1; } while (fgets(buf, sizeof(buf), in)) { char *cmd = buf; line_no++; while (*cmd && isspace(*cmd)) cmd++; if (*cmd == '#') continue; if (show) printc("\x1b[1m=>\x1b[0m %s", cmd); if (do_command(cmd, 0) < 0) { printc_err("read: error processing %s (line %d)\n", filename, line_no); fclose(in); return -1; } } fclose(in); return 0; } mspdebug-0.25/ui/reader.h000066400000000000000000000044171313531517500153100ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef READER_H_ #define READER_H_ /* Commmand processor modification flags. * * Within the context of a command processor, various data items may be * marked as having been modified. These flags can be checked, and a prompt * invoked to ask the user to confirm before proceeding with a destructive * operation. * * The same prompting occurs when the user elects to quit the command * processor. */ #define MODIFY_SYMS 0x01 void mark_modified(int flags); void unmark_modified(int flags); /* This should be called before a destructive operation to give the user * a chance to abort. If it returns 1, then the operation should be aborted. * * The flags argument should be a bitwise combination representing the bits * modify_flags that will be affected by the operation. */ int prompt_abort(int flags); /* Run the reader loop */ void reader_loop(void); /* Cause the reader loop to exit */ void reader_exit(void); /* Set up the command to be repeated. When the user presses enter without * typing anything, the last executed command is repeated, by default. * * Using this function, a command can specify an alternate command for * the next execution. */ void reader_set_repeat(const char *fmt, ...); /* Commands can be fed directly to the processor either one at a time, * or by specifying a file to read from. * * If show is non-zero, commands will be printed as they are executed. */ int process_command(char *cmd); int process_file(const char *filename, int show); #endif mspdebug-0.25/ui/rtools.c000066400000000000000000000473361313531517500153720ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include #include "util.h" #include "device.h" #include "dis.h" #include "rtools.h" #include "stab.h" #include "expr.h" #include "output_util.h" #include "vector.h" /************************************************************************ * Instruction search ("isearch") */ #define ISEARCH_OPCODE 0x0001 #define ISEARCH_DSIZE 0x0002 #define ISEARCH_SRC_ADDR 0x0004 #define ISEARCH_DST_ADDR 0x0008 #define ISEARCH_SRC_MODE 0x0010 #define ISEARCH_DST_MODE 0x0020 #define ISEARCH_SRC_REG 0x0040 #define ISEARCH_DST_REG 0x0080 #define ISEARCH_TYPE 0x0100 struct isearch_query { int flags; struct msp430_instruction insn; }; static int isearch_opcode(const char *term, char **arg, struct isearch_query *q) { const char *opname = get_arg(arg); int opc; (void)term; if (q->flags & ISEARCH_OPCODE) { printc_err("isearch: opcode already specified\n"); return -1; } if (!opname) { printc_err("isearch: opcode name expected\n"); return -1; } opc = dis_opcode_from_name(opname); if (opc < 0) { printc_err("isearch: unknown opcode: %s\n", opname); return -1; } q->insn.op = opc; q->flags |= ISEARCH_OPCODE; return 0; } static int isearch_bw(const char *term, char **arg, struct isearch_query *q) { (void)arg; if (q->flags & ISEARCH_DSIZE) { printc_err("isearch: operand size already specified\n"); return -1; } q->flags |= ISEARCH_DSIZE; switch (toupper(*term)) { case 'B': q->insn.dsize = MSP430_DSIZE_BYTE; break; case 'W': q->insn.dsize = MSP430_DSIZE_WORD; break; case 'A': q->insn.dsize = MSP430_DSIZE_AWORD; break; } return 0; } static int isearch_type(const char *term, char **arg, struct isearch_query *q) { (void)arg; if (q->flags & ISEARCH_TYPE) { printc_err("isearch: instruction type already " "specified\n"); return -1; } q->flags |= ISEARCH_TYPE; switch (toupper(*term)) { case 'J': q->insn.itype = MSP430_ITYPE_JUMP; break; case 'S': q->insn.itype = MSP430_ITYPE_SINGLE; break; case 'D': q->insn.itype = MSP430_ITYPE_DOUBLE; break; default: q->insn.itype = MSP430_ITYPE_NOARG; break; } return 0; } static int isearch_addr(const char *term, char **arg, struct isearch_query *q) { int which = toupper(*term) == 'S' ? ISEARCH_SRC_ADDR : ISEARCH_DST_ADDR; const char *addr_text; address_t addr; if (q->flags & which) { printc_err("isearch: address already specified\n"); return -1; } addr_text = get_arg(arg); if (!addr_text) { printc_err("isearch: address expected\n"); return -1; } if (expr_eval(addr_text, &addr) < 0) return -1; q->flags |= which; if (which == ISEARCH_SRC_ADDR) q->insn.src_addr = addr; else q->insn.dst_addr = addr; return 0; } static int isearch_reg(const char *term, char **arg, struct isearch_query *q) { int which = toupper(*term) == 'S' ? ISEARCH_SRC_REG : ISEARCH_DST_REG; const char *reg_text; int reg; if (q->flags & which) { printc_err("isearch: register already specified\n"); return -1; } reg_text = get_arg(arg); if (!reg_text) { printc_err("isearch: register expected\n"); return -1; } reg = dis_reg_from_name(reg_text); if (reg < 0) { printc_err("isearch: unknown register: %s\n", reg_text); return -1; } q->flags |= which; if (which == ISEARCH_SRC_REG) q->insn.src_reg = reg; else q->insn.dst_reg = reg; return 0; } static int isearch_mode(const char *term, char **arg, struct isearch_query *q) { int which = toupper(*term) == 'S' ? ISEARCH_SRC_MODE : ISEARCH_DST_MODE; const char *what_text; int what; if (q->flags & which) { printc_err("isearch: mode already specified\n"); return -1; } what_text = get_arg(arg); if (!what_text) { printc_err("isearch: mode must be specified\n"); return -1; } switch (toupper(*what_text)) { case 'R': what = MSP430_AMODE_REGISTER; break; case '@': what = MSP430_AMODE_INDIRECT; break; case '+': what = MSP430_AMODE_INDIRECT_INC; break; case '#': what = MSP430_AMODE_IMMEDIATE; break; case 'I': what = MSP430_AMODE_INDEXED; break; case '&': what = MSP430_AMODE_ABSOLUTE; break; case 'S': what = MSP430_AMODE_SYMBOLIC; break; default: printc_err("isearch: unknown address mode: %s\n", what_text); return -1; } q->flags |= which; if (which == ISEARCH_SRC_MODE) q->insn.src_mode = what; else q->insn.dst_mode = what; return 0; } static int isearch_match(const struct msp430_instruction *insn, const struct isearch_query *q) { if ((q->flags & (ISEARCH_SRC_ADDR | ISEARCH_SRC_MODE | ISEARCH_SRC_REG)) && insn->itype != MSP430_ITYPE_DOUBLE) return 0; if ((q->flags & (ISEARCH_DST_ADDR | ISEARCH_DST_MODE | ISEARCH_DST_REG)) && insn->itype == MSP430_ITYPE_NOARG) return 0; if ((q->flags & ISEARCH_OPCODE) && insn->op != q->insn.op) return 0; if ((q->flags & ISEARCH_DSIZE) && q->insn.dsize != insn->dsize) return 0; if (q->flags & ISEARCH_SRC_ADDR) { if (insn->src_mode != MSP430_AMODE_INDEXED && insn->src_mode != MSP430_AMODE_SYMBOLIC && insn->src_mode != MSP430_AMODE_ABSOLUTE && insn->src_mode != MSP430_AMODE_IMMEDIATE) return 0; if (insn->src_addr != q->insn.src_addr) return 0; } if (q->flags & ISEARCH_DST_ADDR) { if (insn->dst_mode != MSP430_AMODE_INDEXED && insn->dst_mode != MSP430_AMODE_SYMBOLIC && insn->dst_mode != MSP430_AMODE_ABSOLUTE && insn->dst_mode != MSP430_AMODE_IMMEDIATE) return 0; if (insn->dst_addr != q->insn.dst_addr) return 0; } if ((q->flags & ISEARCH_SRC_MODE) && insn->src_mode != q->insn.src_mode) return 0; if ((q->flags & ISEARCH_DST_MODE) && insn->dst_mode != q->insn.dst_mode) return 0; if (q->flags & ISEARCH_SRC_REG) { if (insn->src_mode != MSP430_AMODE_REGISTER && insn->src_mode != MSP430_AMODE_INDIRECT && insn->src_mode != MSP430_AMODE_INDIRECT_INC && insn->src_mode != MSP430_AMODE_INDEXED) return 0; if (insn->src_reg != q->insn.src_reg) return 0; } if (q->flags & ISEARCH_DST_REG) { if (insn->dst_mode != MSP430_AMODE_REGISTER && insn->dst_mode != MSP430_AMODE_INDIRECT && insn->dst_mode != MSP430_AMODE_INDIRECT_INC && insn->dst_mode != MSP430_AMODE_INDEXED) return 0; if (insn->dst_reg != q->insn.dst_reg) return 0; } if ((q->flags & ISEARCH_TYPE) && insn->itype != q->insn.itype) return 0; return 1; } static int do_isearch(address_t addr, address_t len, const struct isearch_query *q) { uint8_t *mbuf; address_t i; mbuf = malloc(len); if (!mbuf) { printc_err("isearch: couldn't allocate memory: %s\n", last_error()); return -1; } if (device_readmem(addr, mbuf, len) < 0) { printc_err("isearch: couldn't read device memory\n"); free(mbuf); return -1; } addr &= ~1; len &= ~1; for (i = 0; i < len; i += 2) { struct msp430_instruction insn; int count = dis_decode(mbuf + i, addr + i, len - i, &insn); if (count >= 0 && isearch_match(&insn, q)) disassemble(addr + i, mbuf + i, count, device_default->power_buf); } free(mbuf); return 0; } int cmd_isearch(char **arg) { static const struct { const char *name; int (*func)(const char *term, char **arg, struct isearch_query *q); } term_handlers[] = { {"opcode", isearch_opcode}, {"byte", isearch_bw}, {"word", isearch_bw}, {"aword", isearch_bw}, {"jump", isearch_type}, {"single", isearch_type}, {"double", isearch_type}, {"src", isearch_addr}, {"dst", isearch_addr}, {"srcreg", isearch_reg}, {"dstreg", isearch_reg}, {"srcmode", isearch_mode}, {"dstmode", isearch_mode} }; struct isearch_query q; const char *addr_text; const char *len_text; address_t addr; address_t len; addr_text = get_arg(arg); len_text = get_arg(arg); if (!(addr_text && len_text)) { printc_err("isearch: address and length expected\n"); return -1; } if (expr_eval(addr_text, &addr) < 0 || expr_eval(len_text, &len) < 0) return -1; q.flags = 0; for (;;) { const char *term = get_arg(arg); int i; if (!term) break; for (i = 0; i < ARRAY_LEN(term_handlers); i++) if (!strcasecmp(term_handlers[i].name, term)) { if (term_handlers[i].func(term, arg, &q) < 0) return -1; break; } } if (!q.flags) { printc_err("isearch: no query terms given " "(perhaps you mean \"dis\"?)\n"); return -1; } return do_isearch(addr, len, &q); } /************************************************************************ * Call graph ("cgraph") */ struct cg_edge { int is_tail_call; address_t src; address_t dst; }; static int cmp_branch_by_dst(const void *a, const void *b) { const struct cg_edge *br_a = (const struct cg_edge *)a; const struct cg_edge *br_b = (const struct cg_edge *)b; if (br_a->dst < br_b->dst) return -1; if (br_a->dst > br_b->dst) return 1; if (br_a->src < br_b->src) return -1; if (br_a->src > br_b->src) return 1; if (!br_a->is_tail_call && br_b->is_tail_call) return -1; if (br_a->is_tail_call && !br_b->is_tail_call) return 1; return 0; } static int cmp_branch_by_src(const void *a, const void *b) { const struct cg_edge *br_a = (const struct cg_edge *)a; const struct cg_edge *br_b = (const struct cg_edge *)b; if (br_a->src < br_b->src) return -1; if (br_a->src > br_b->src) return 1; if (br_a->dst < br_b->dst) return -1; if (br_a->dst > br_b->dst) return 1; if (!br_a->is_tail_call && br_b->is_tail_call) return -1; if (br_a->is_tail_call && !br_b->is_tail_call) return 1; return 0; } struct cg_node { address_t offset; }; static int cmp_node(const void *a, const void *b) { const struct cg_node *na = (const struct cg_node *)a; const struct cg_node *nb = (const struct cg_node *)b; if (na->offset < nb->offset) return -1; if (na->offset > nb->offset) return 1; return 0; } struct call_graph { int offset; int len; struct vector edge_to; struct vector edge_from; struct vector node_list; }; #define CG_NODE(g, i) (VECTOR_PTR((g)->node_list, (i), struct cg_node)) #define CG_EDGE_FROM(g, i) (VECTOR_PTR((g)->edge_from, (i), struct cg_edge)) #define CG_EDGE_TO(g, i) (VECTOR_PTR((g)->edge_to, (i), struct cg_edge)) static void cgraph_destroy(struct call_graph *graph) { vector_destroy(&graph->edge_to); vector_destroy(&graph->edge_from); vector_destroy(&graph->node_list); } static int find_possible_edges(int offset, int len, uint8_t *memory, struct call_graph *graph) { int i; for (i = 0; i < len; i += 2) { struct msp430_instruction insn; if (dis_decode(memory + i, offset + i, len - i, &insn) < 0) continue; if (insn.dst_mode == MSP430_AMODE_IMMEDIATE && (insn.op == MSP430_OP_CALL || insn.op == MSP430_OP_BR) && !(insn.dst_addr & 1)) { struct cg_edge br; br.src = offset + i; br.dst = insn.dst_addr; br.is_tail_call = insn.op != MSP430_OP_CALL; if (vector_push(&graph->edge_from, &br, 1) < 0) return -1; } } return 0; } static int add_nodes_from_edges(struct call_graph *graph) { int i; address_t last_addr = 0; int have_last_addr = 0; qsort(graph->edge_from.ptr, graph->edge_from.size, graph->edge_from.elemsize, cmp_branch_by_dst); /* Look for unique destination addresses */ for (i = 0; i < graph->edge_from.size; i++) { const struct cg_edge *br = CG_EDGE_FROM(graph, i); if (!have_last_addr || br->dst != last_addr) { struct cg_node n; n.offset = br->dst; last_addr = br->dst; have_last_addr = 1; if (vector_push(&graph->node_list, &n, 1) < 0) return -1; } } return 0; } static void relabel_sources(struct call_graph *graph) { int i = 0; /* Node index */ int j = 0; /* Edge index */ /* Identify the source nodes for each edge */ qsort(graph->edge_from.ptr, graph->edge_from.size, graph->edge_from.elemsize, cmp_branch_by_src); while (j < graph->edge_from.size) { struct cg_edge *br = CG_EDGE_FROM(graph, j); struct cg_node *n; /* Skip over nodes which are too early for this edge */ while (i + 1 < graph->node_list.size && CG_NODE(graph, i + 1)->offset <= br->src) i++; n = CG_NODE(graph, i); if (n->offset <= br->src) br->src = n->offset; j++; } } static void remove_duplicate_nodes(struct call_graph *graph) { int i = 0; int j = 0; qsort(graph->node_list.ptr, graph->node_list.size, graph->node_list.elemsize, cmp_node); while (i < graph->node_list.size) { struct cg_node *n = CG_NODE(graph, i); struct cg_node *l = CG_NODE(graph, j - 1); if (!j || n->offset != l->offset) { if (i != j) memcpy(l + 1, n, sizeof(*l)); j++; } i++; } graph->node_list.size = j; } static void remove_duplicate_edges(struct call_graph *graph) { int i = 0; /* Source index */ int j = 0; /* Destination index */ qsort(graph->edge_from.ptr, graph->edge_from.size, graph->edge_from.elemsize, cmp_branch_by_src); while (i < graph->edge_from.size) { struct cg_edge *e = CG_EDGE_FROM(graph, i); struct cg_edge *l = CG_EDGE_FROM(graph, j - 1); if (!j || l->src != e->src || l->dst != e->dst || l->is_tail_call != e->is_tail_call) { if (i != j) memcpy(l + 1, e, sizeof(*l)); j++; } i++; } graph->edge_from.size = j; } static int build_inverse(struct call_graph *graph) { graph->edge_to.size = 0; if (vector_push(&graph->edge_to, graph->edge_from.ptr, graph->edge_from.size) < 0) return -1; qsort(graph->edge_to.ptr, graph->edge_to.size, graph->edge_to.elemsize, cmp_branch_by_dst); return 0; } static int add_irq_edges(address_t offset, address_t len, uint8_t *memory, struct call_graph *graph) { int i; if (offset > 0x10000 || offset + len <= 0xffe0) return 0; if (offset < 0xffe0) { len -= (0xffe0 - offset); memory += (0xffe0 - offset); offset = 0xffe0; } if (offset + len > 0x10000) len = 0x10000 - offset; if (offset & 1) { offset++; memory++; len--; } for (i = 0; i < len; i += 2) { struct cg_edge br; br.src = offset + i; br.dst = ((address_t)memory[i]) | (((address_t)memory[i + 1]) << 8); br.is_tail_call = 0; if (vector_push(&graph->edge_from, &br, 1) < 0) return -1; } return 0; } static int add_symbol_nodes(void *user_data, const char *name, address_t offset) { struct call_graph *graph = (struct call_graph *)user_data; while (*name) { if (*name == '.') return 0; name++; } if (offset > graph->offset && offset <= graph->offset + graph->len) { struct cg_node n; n.offset = offset; return vector_push(&graph->node_list, &n, 1); } return 0; } static int cgraph_init(address_t offset, address_t len, uint8_t *memory, struct call_graph *graph) { vector_init(&graph->edge_to, sizeof(struct cg_edge)); vector_init(&graph->edge_from, sizeof(struct cg_edge)); vector_init(&graph->node_list, sizeof(struct cg_node)); graph->offset = offset; graph->len = len; if (find_possible_edges(offset, len, memory, graph) < 0) goto fail; if (add_irq_edges(offset, len, memory, graph) < 0) goto fail; if (stab_enum(add_symbol_nodes, graph) < 0) goto fail; if (add_nodes_from_edges(graph) < 0) goto fail; remove_duplicate_nodes(graph); relabel_sources(graph); remove_duplicate_edges(graph); if (build_inverse(graph) < 0) goto fail; return 0; fail: cgraph_destroy(graph); return -1; } static void cgraph_summary(struct call_graph *graph) { int i; int j = 0; /* Edge from index */ int k = 0; /* Edge to index */ for (i = 0; i < graph->node_list.size; i++) { struct cg_node *n = CG_NODE(graph, i); int from_count = 0; int to_count = 0; char name[64]; while (j < graph->edge_from.size && CG_EDGE_FROM(graph, j)->src < n->offset) j++; while (k < graph->edge_to.size && CG_EDGE_TO(graph, k)->dst < n->offset) k++; while (j < graph->edge_from.size && CG_EDGE_FROM(graph, j)->src == n->offset) { from_count++; j++; } while (k < graph->edge_to.size && CG_EDGE_TO(graph, k)->dst == n->offset) { to_count++; k++; } print_address(n->offset, name, sizeof(name), 0); printc("0x%04x [%3d ==> %3d] %s\n", n->offset, to_count, from_count, name); } } static void cgraph_func_info(struct call_graph *graph, address_t addr) { int i = 0; int j = 0; int k = 0; char name[64]; struct cg_node *n; while (i + 1 < graph->node_list.size && CG_NODE(graph, i + 1)->offset <= addr) i++; if (i >= graph->node_list.size || CG_NODE(graph, i)->offset > addr) { printc("No information for address 0x%04x\n", addr); return; } n = CG_NODE(graph, i); while (j < graph->edge_from.size && CG_EDGE_FROM(graph, j)->src < n->offset) j++; while (k < graph->edge_to.size && CG_EDGE_TO(graph, k)->dst < n->offset) k++; print_address(n->offset, name, sizeof(name), 0); printc("0x%04x %s:\n", n->offset, name); if (j < graph->edge_from.size && CG_EDGE_FROM(graph, j)->src == n->offset) { printc(" Callees:\n"); while (j < graph->edge_from.size) { struct cg_edge *e = CG_EDGE_FROM(graph, j); if (e->src != n->offset) break; print_address(e->dst, name, sizeof(name), 0); printc(" %s%s\n", e->is_tail_call ? "*" : "", name); j++; } printc("\n"); } if (k < graph->edge_to.size && CG_EDGE_TO(graph, k)->dst == n->offset) { printc(" Callers:\n"); while (k < graph->edge_to.size) { struct cg_edge *e = CG_EDGE_TO(graph, k); if (e->dst != n->offset) break; print_address(e->src, name, sizeof(name), 0); printc(" %s%s\n", e->is_tail_call ? "*" : "", name); k++; } } } int cmd_cgraph(char **arg) { char *offset_text, *len_text, *addr_text;; address_t offset, len, addr; uint8_t *memory; struct call_graph graph; /* Figure out what the arguments are */ offset_text = get_arg(arg); len_text = get_arg(arg); addr_text = get_arg(arg); if (!(offset_text && len_text)) { printc_err("cgraph: offset and length must be " "specified\n"); return -1; } if (expr_eval(offset_text, &offset) < 0) { printc_err("cgraph: invalid offset: %s\n", offset_text); return -1; } offset &= ~1; if (expr_eval(len_text, &len) < 0) { printc_err("cgraph: invalid length: %s\n", len_text); return -1; } len &= ~1; if (addr_text && expr_eval(addr_text, &addr) < 0) { printc_err("cgraph: invalid address: %s\n", addr_text); return -1; } /* Grab the memory to be analysed */ memory = malloc(len); if (!memory) { printc_err("cgraph: couldn't allocate memory: %s\n", last_error()); return -1; } if (device_readmem(offset, memory, len) < 0) { printc_err("cgraph: couldn't fetch memory\n"); free(memory); return -1; } /* Produce and display the call graph */ if (cgraph_init(offset, len, memory, &graph) < 0) { printc_err("cgraph: couldn't build call graph\n"); free(memory); return -1; } free(memory); if (addr_text) cgraph_func_info(&graph, addr); else cgraph_summary(&graph); cgraph_destroy(&graph); return 0; } mspdebug-0.25/ui/rtools.h000066400000000000000000000016151313531517500153650ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef RTOOLS_H_ #define RTOOLS_H_ int cmd_isearch(char **arg); int cmd_cgraph(char **arg); #endif mspdebug-0.25/ui/stdcmd.c000066400000000000000000000132661313531517500153210ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef NO_SHELLCMD #include #include #include #include #include "ctrlc.h" #endif /* !NO_SHELLCMD */ #include #include #include #include "cmddb.h" #include "opdb.h" #include "vector.h" #include "stdcmd.h" #include "output.h" #include "output_util.h" #include "reader.h" #include "expr.h" static const char *type_text(opdb_type_t type) { switch (type) { case OPDB_TYPE_BOOLEAN: return "boolean"; case OPDB_TYPE_NUMERIC: return "numeric"; case OPDB_TYPE_STRING: return "text"; } return "unknown"; } static int push_option_name(void *user_data, const struct opdb_key *key, const union opdb_value *value) { (void)value; return vector_push((struct vector *)user_data, &key->name, 1); } static int push_command_name(void *user_data, const struct cmddb_record *rec) { return vector_push((struct vector *)user_data, &rec->name, 1); } int cmd_help(char **arg) { const char *topic = get_arg(arg); if (topic) { struct cmddb_record cmd; struct opdb_key key; if (!cmddb_get(topic, &cmd)) { printc("\x1b[1mCOMMAND: %s\x1b[0m\n\n%s\n", cmd.name, cmd.help); return 0; } if (!opdb_get(topic, &key, NULL)) { printc("\x1b[1mOPTION: %s (%s)\x1b[0m\n\n%s\n", key.name, type_text(key.type), key.help); return 0; } printc_err("help: unknown command: %s\n", topic); return -1; } else { struct vector v; vector_init(&v, sizeof(const char *)); if (!cmddb_enum(push_command_name, &v)) { printc("Available commands:\n"); namelist_print(&v); printc("\n"); } else { pr_error("help: can't allocate memory for command list"); } vector_realloc(&v, 0); if (!opdb_enum(push_option_name, &v)) { printc("Available options:\n"); namelist_print(&v); printc("\n"); } else { pr_error("help: can't allocate memory for option list"); } vector_destroy(&v); printc("Type \"help \" for more information.\n"); printc("Use the \"opt\" command (\"help opt\") to set " "options.\n"); #if defined(__Windows__) && !defined(USE_READLINE) printc("Press Ctrl+Z, Enter to quit.\n"); #else printc("Press Ctrl+D to quit.\n"); #endif } return 0; } static int parse_option(opdb_type_t type, union opdb_value *value, const char *word) { switch (type) { case OPDB_TYPE_BOOLEAN: value->numeric = (isdigit(word[0]) && word[0] > '0') || word[0] == 't' || word[0] == 'y' || (word[0] == 'o' && word[1] == 'n'); break; case OPDB_TYPE_NUMERIC: return expr_eval(word, &value->numeric); case OPDB_TYPE_STRING: strncpy(value->string, word, sizeof(value->string)); value->string[sizeof(value->string) - 1] = 0; break; } return 0; } static int display_option(void *user_data, const struct opdb_key *key, const union opdb_value *value) { (void)user_data; printc("%32s = ", key->name); switch (key->type) { case OPDB_TYPE_BOOLEAN: printc("%s", value->boolean ? "true" : "false"); break; case OPDB_TYPE_NUMERIC: printc("0x%x (%u)", value->numeric, value->numeric); break; case OPDB_TYPE_STRING: printc("%s", value->string); break; } printc("\n"); return 0; } int cmd_opt(char **arg) { const char *opt_text = get_arg(arg); struct opdb_key key; union opdb_value value; if (opt_text) { if (opdb_get(opt_text, &key, &value) < 0) { printc_err("opt: no such option: %s\n", opt_text); return -1; } } if (**arg) { if (parse_option(key.type, &value, *arg) < 0) { printc_err("opt: can't parse option: %s\n", *arg); return -1; } opdb_set(key.name, &value); } else if (opt_text) { display_option(NULL, &key, &value); } else { opdb_enum(display_option, NULL); } return 0; } int cmd_read(char **arg) { char *filename = get_arg(arg); if (!filename) { printc_err("read: filename must be specified\n"); return -1; } return process_file(filename, 1); } int cmd_exit(char **arg) { (void)arg; reader_exit(); return 0; } #ifndef NO_SHELLCMD int cmd_shellcmd(char **arg) { int fd; pid_t pid; char *sh, *p; static char *shell = NULL; static char shell_name[16]; if (shell == NULL) { sh = getenv("SHELL"); if (sh == NULL) { sh = "/bin/sh"; } shell = strdup(sh); p = strdup(sh); if (shell == NULL || p == NULL) { pr_error("!: error: strdup"); return -1; } memset(shell_name, 0, sizeof(shell_name)); *shell_name = '-'; strncpy(shell_name + 1, basename(p), sizeof(shell_name) - 2); shell_name[sizeof(shell_name) - 1] = '\0'; free(p); } pid = fork(); if (pid == -1) { pr_error("!: error: fork"); return -1; } if (pid == 0) { ctrlc_exit(); for (fd = 3; fd < 1024; fd++) { (void)close(fd); } if (arg && *arg[0]) { execl(shell, shell_name, "-c", *arg, NULL); } else { execl(shell, shell_name, NULL); } printc_err("!: error: execl(\"%s\")", shell); pr_error(""); _exit(1); } while (waitpid(-1, NULL, 0) != pid) { ; } return 0; } #endif /* !NO_SHELLCMD */ mspdebug-0.25/ui/stdcmd.h000066400000000000000000000020141313531517500153130ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef STDCMD_H_ #define STDCMD_H_ /* Built-in commands */ int cmd_help(char **arg); int cmd_read(char **arg); int cmd_opt(char **arg); int cmd_exit(char **arg); #ifndef NO_SHELLCMD int cmd_shellcmd(char **arg); #endif #endif mspdebug-0.25/ui/sym.c000066400000000000000000000170471313531517500146540ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include #include #include #include "stab.h" #include "expr.h" #include "binfile.h" #include "util.h" #include "output.h" #include "output_util.h" #include "vector.h" #include "sym.h" #include "reader.h" #include "demangle.h" int cmd_eval(char **arg) { address_t addr; char name[MAX_SYMBOL_LENGTH]; if (expr_eval(*arg, &addr) < 0) { printc_err("=: can't parse: %s\n", *arg); return -1; } print_address(addr, name, sizeof(name), 0); printc("0x%05x = %s\n", addr, name); return 0; } static int cmd_sym_load_add(int clear, char **arg) { FILE *in; char * path; if (clear && prompt_abort(MODIFY_SYMS)) return 0; path = expand_tilde(*arg); if (!path) return -1; in = fopen(path, "rb"); free(path); if (!in) { printc_err("sym: %s: %s\n", *arg, last_error()); return -1; } if (clear) { stab_clear(); unmark_modified(MODIFY_SYMS); } else { mark_modified(MODIFY_SYMS); } if (binfile_syms(in) < 0) { fclose(in); return -1; } fclose(in); return 0; } static int savemap_cb(void *user_data, const char *name, address_t value) { FILE *savemap_out = (FILE *)user_data; if (fprintf(savemap_out, "%04x t %s\n", value, name) < 0) { pr_error("sym: can't write to file"); return -1; } return 0; } static int cmd_sym_savemap(char **arg) { FILE *savemap_out; char *fname = get_arg(arg); if (!fname) { printc_err("sym: filename required to save map\n"); return -1; } savemap_out = fopen(fname, "w"); if (!savemap_out) { printc_err("sym: couldn't write to %s: %s\n", fname, last_error()); return -1; } if (stab_enum(savemap_cb, savemap_out) < 0) { fclose(savemap_out); return -1; } if (fclose(savemap_out) < 0) { printc_err("sym: error on close: %s\n", last_error()); return -1; } unmark_modified(MODIFY_SYMS); return 0; } static int print_sym(void *user_data, const char *name, address_t value) { (void)user_data; char demangled[MAX_SYMBOL_LENGTH]; if (demangle(name, demangled, sizeof(demangled)) > 0) printc("0x%04x: %s (%s)\n", value, name, demangled); else printc("0x%04x: %s\n", value, name); return 0; } static int find_sym(void *user_data, const char *name, address_t value) { regex_t *find_preg = (regex_t *)user_data; char demangled[MAX_SYMBOL_LENGTH]; int len = demangle(name, demangled, sizeof(demangled)); if (!regexec(find_preg, name, 0, NULL, 0) || (len > 0 && !regexec(find_preg, demangled, 0, NULL, 0))) { if (len > 0) printc("0x%04x: %s (%s)\n", value, name, demangled); else printc("0x%04x: %s\n", value, name); } return 0; } static int cmd_sym_find(char **arg) { regex_t find_preg; char *expr = get_arg(arg); if (!expr) { stab_enum(print_sym, NULL); return 0; } if (regcomp(&find_preg, expr, REG_EXTENDED | REG_NOSUB)) { printc_err("sym: failed to compile: %s\n", expr); return -1; } stab_enum(find_sym, &find_preg); regfree(&find_preg); return 0; } struct rename_record { char old_name[MAX_SYMBOL_LENGTH]; int start, end; }; struct rename_data { struct vector list; regex_t preg; }; static int renames_do(struct rename_data *rename, const char *replace) { int i; int count = 0; for (i = 0; i < rename->list.size; i++) { struct rename_record *r = VECTOR_PTR(rename->list, i, struct rename_record); char new_name[MAX_SYMBOL_LENGTH]; int len = r->start; address_t value; if (len + 1 > sizeof(new_name)) len = sizeof(new_name) - 1; memcpy(new_name, r->old_name, len); snprintf(new_name + len, sizeof(new_name) - len, "%s%s", replace, r->old_name + r->end); printc("%s -> %s\n", r->old_name, new_name); if (stab_get(r->old_name, &value) < 0) { printc_err("sym: warning: " "symbol missing: %s\n", r->old_name); } else { stab_del(r->old_name); if (stab_set(new_name, value) < 0) { printc_err("sym: warning: " "failed to set new name: %s\n", new_name); } } count++; } printc("%d symbols renamed\n", count); return 0; } static int find_renames(void *user_data, const char *name, address_t value) { struct rename_data *rename = (struct rename_data *)user_data; regmatch_t pmatch; (void)value; if (!regexec(&rename->preg, name, 1, &pmatch, 0) && pmatch.rm_so >= 0 && pmatch.rm_eo > pmatch.rm_so) { struct rename_record r; strncpy(r.old_name, name, sizeof(r.old_name)); r.old_name[sizeof(r.old_name) - 1] = 0; r.start = pmatch.rm_so; r.end = pmatch.rm_eo; return vector_push(&rename->list, &r, 1); } return 0; } static int cmd_sym_rename(char **arg) { const char *expr = get_arg(arg); const char *replace = get_arg(arg); int ret; struct rename_data rename; if (!(expr && replace)) { printc_err("sym: expected pattern and replacement\n"); return -1; } if (regcomp(&rename.preg, expr, REG_EXTENDED)) { printc_err("sym: failed to compile: %s\n", expr); return -1; } vector_init(&rename.list, sizeof(struct rename_record)); if (stab_enum(find_renames, &rename) < 0) { printc_err("sym: rename failed\n"); regfree(&rename.preg); vector_destroy(&rename.list); return -1; } regfree(&rename.preg); ret = renames_do(&rename, replace); vector_destroy(&rename.list); if (ret > 0) mark_modified(MODIFY_SYMS); return ret >= 0 ? 0 : -1; } static int cmd_sym_del(char **arg) { char *name = get_arg(arg); if (!name) { printc_err("sym: need a name to delete " "symbol table entries\n"); return -1; } if (stab_del(name) < 0) { printc_err("sym: can't delete nonexistent symbol: %s\n", name); return -1; } mark_modified(MODIFY_SYMS); return 0; } int cmd_sym(char **arg) { char *subcmd = get_arg(arg); if (!subcmd) { printc_err("sym: need to specify a subcommand " "(try \"help sym\")\n"); return -1; } if (!strcasecmp(subcmd, "clear")) { if (prompt_abort(MODIFY_SYMS)) return 0; stab_clear(); unmark_modified(MODIFY_SYMS); return 0; } if (!strcasecmp(subcmd, "set")) { char *name = get_arg(arg); char *val_text = get_arg(arg); address_t value; if (!(name && val_text)) { printc_err("sym: need a name and value to set " "symbol table entries\n"); return -1; } if (expr_eval(val_text, &value) < 0) { printc_err("sym: can't parse value: %s\n", val_text); return -1; } if (stab_set(name, value) < 0) return -1; mark_modified(MODIFY_SYMS); return 0; } if (!strcasecmp(subcmd, "del")) return cmd_sym_del(arg); if (!strcasecmp(subcmd, "import")) return cmd_sym_load_add(1, arg); if (!strcasecmp(subcmd, "import+")) return cmd_sym_load_add(0, arg); if (!strcasecmp(subcmd, "export")) return cmd_sym_savemap(arg); if (!strcasecmp(subcmd, "rename")) return cmd_sym_rename(arg); if (!strcasecmp(subcmd, "find")) return cmd_sym_find(arg); printc_err("sym: unknown subcommand: %s\n", subcmd); return -1; } mspdebug-0.25/ui/sym.h000066400000000000000000000015771313531517500146620ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef SYM_H_ #define SYM_H_ int cmd_eval(char **arg); int cmd_sym(char **arg); #endif mspdebug-0.25/util/000077500000000000000000000000001313531517500142275ustar00rootroot00000000000000mspdebug-0.25/util/btree.c000066400000000000000000000433021313531517500154760ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include #include "btree.h" #include "output.h" #include "util.h" #define MAX_HEIGHT 16 /* Btree pages consist of the following: a page header (struct btree_page), * followed by a block of memory consisting of: * * For a leaf node: * An array of N keys, then an array of N data. * * For a non-leaf node: * An array of N keys, then an array of N struct btree_page *. * * Where N is the branch factor. */ struct btree_page { int height; int num_children; struct btree *owner; const struct btree_def *def; }; #define PAGE_KEY(p, i) \ (((char *)(p)) + sizeof(struct btree_page) + \ (i) * (p)->def->key_size) #define PAGE_DATA(p, i) \ (((char *)(p)) + sizeof(struct btree_page) + \ (p)->def->branches * (p)->def->key_size + \ (i) * (p)->def->data_size) #define PAGE_PTR(p, i) \ ((struct btree_page **) \ (((char *)(p)) + sizeof(struct btree_page) + \ (p)->def->branches * (p)->def->key_size + \ (i) * sizeof(struct btree_page *))) \ struct btree { const struct btree_def *def; struct btree_page *root; struct btree_page *path[MAX_HEIGHT]; int slot[MAX_HEIGHT]; }; /************************************************************************ * Debugging */ #ifdef DEBUG_BTREE static void check_page(struct btree_page *p, const void *lbound, const void *ubound, int height) { const struct btree_def *def = p->def; int i; assert (p); assert (p->height == height); if (p != p->owner->root) { assert (p->num_children >= def->branches / 2); assert (p->num_children <= def->branches); } for (i = 0; i < p->num_children; i++) { const void *key = PAGE_KEY(p, i); const void *next_key = ubound; if (i + 1 < p->num_children) next_key = PAGE_KEY(p, i + 1); assert (def->compare(key, lbound) >= 0); if (next_key) { assert (def->compare(key, next_key) < 0); } if (ubound) { assert (def->compare(key, ubound) < 0); } if (p->height) check_page(*PAGE_PTR(p, i), key, next_key, height - 1); } } static void check_btree(btree_t bt) { assert (bt->def); if (bt->root->height) { assert (bt->root->num_children >= 2); } check_page(bt->root, bt->def->zero, NULL, bt->root->height); } #else #define check_btree(bt) #endif /************************************************************************ * B+Tree auxiliary functions */ static void destroy_page(struct btree_page *p) { if (!p) return; if (p->height) { int i; for (i = 0; i < p->num_children; i++) destroy_page(*PAGE_PTR(p, i)); } free(p); } static struct btree_page *allocate_page(btree_t bt, int height) { const struct btree_def *def = bt->def; struct btree_page *p; int size = sizeof(*p) + def->key_size * def->branches; if (height) size += sizeof(struct btree_page *) * def->branches; else size += sizeof(def->data_size) * def->branches; p = malloc(size); if (!p) { printc_err("btree: couldn't allocate page: %s\n", last_error()); return NULL; } memset(p, 0, size); p->def = bt->def; p->owner = bt; p->height = height; return p; } static void split_page(struct btree_page *op, struct btree_page *np) { const struct btree_def *def = op->def; btree_t bt = op->owner; const int halfsize = def->branches / 2; assert (op->num_children == def->branches); memcpy(PAGE_KEY(np, 0), PAGE_KEY(op, halfsize), halfsize * def->key_size); if (op->height) memcpy(PAGE_PTR(np, 0), PAGE_PTR(op, halfsize), halfsize * sizeof(struct btree_page *)); else memcpy(PAGE_DATA(np, 0), PAGE_DATA(op, halfsize), halfsize * def->data_size); op->num_children = halfsize; np->num_children = halfsize; /* Fix up the cursor if we split an active page */ if (bt->slot[0] >= 0 && bt->path[op->height] == op && bt->slot[op->height] > op->num_children) { bt->slot[op->height] -= op->num_children; bt->path[op->height] = np; } } static void insert_data(struct btree_page *p, int s, const void *key, const void *data) { const struct btree_def *def = p->def; btree_t bt = p->owner; int r = p->num_children - s; assert (!p->height); assert (p->num_children < def->branches); assert (s >= 0 && s <= p->num_children); memmove(PAGE_KEY(p, s + 1), PAGE_KEY(p, s), r * def->key_size); memmove(PAGE_DATA(p, s + 1), PAGE_DATA(p, s), r * def->data_size); memcpy(PAGE_KEY(p, s), key, def->key_size); memcpy(PAGE_DATA(p, s), data, def->data_size); p->num_children++; /* Fix up the cursor if we inserted before it, or if we're inserting * a pointer to the cursor data itself (as in a borrow). */ if (bt->slot[0] >= 0) { if (data == PAGE_DATA(bt->path[0], bt->slot[0])) { bt->path[0] = p; bt->slot[0] = s; } else if (bt->path[0] == p && s <= bt->slot[0]) { bt->slot[0]++; } } } static void insert_ptr(struct btree_page *p, int s, const void *key, struct btree_page *ptr) { const struct btree_def *def = p->def; btree_t bt = p->owner; int r = p->num_children - s; assert (p->height); assert (p->num_children < def->branches); assert (s >= 0 && s <= p->num_children); memmove(PAGE_KEY(p, s + 1), PAGE_KEY(p, s), r * def->key_size); memmove(PAGE_PTR(p, s + 1), PAGE_PTR(p, s), r * sizeof(struct btree_page *)); memcpy(PAGE_KEY(p, s), key, def->key_size); *PAGE_PTR(p, s) = ptr; p->num_children++; /* Fix up the cursor if we inserted before it, or if we just inserted * the pointer for the active path (as in a split or borrow). */ if (bt->slot[0] >= 0) { if (ptr == bt->path[p->height - 1]) { bt->path[p->height] = p; bt->slot[p->height] = s; } else if (bt->path[p->height] == p && s <= bt->slot[p->height]) { bt->slot[p->height]++; } } } static void delete_item(struct btree_page *p, int s) { const struct btree_def *def = p->def; btree_t bt = p->owner; int r = p->num_children - s - 1; assert (s >= 0 && s < p->num_children); memmove(PAGE_KEY(p, s), PAGE_KEY(p, s + 1), r * def->key_size); if (p->height) memmove(PAGE_PTR(p, s), PAGE_PTR(p, s + 1), r * sizeof(struct btree_page *)); else memmove(PAGE_DATA(p, s), PAGE_DATA(p, s + 1), r * def->data_size); p->num_children--; /* Fix up the cursor if we deleted before it */ if (bt->slot[0] >= 0 && bt->path[p->height] == p && s <= bt->slot[p->height]) bt->slot[p->height]--; } static void move_item(struct btree_page *from, int from_pos, struct btree_page *to, int to_pos) { if (from->height) insert_ptr(to, to_pos, PAGE_KEY(from, from_pos), *PAGE_PTR(from, from_pos)); else insert_data(to, to_pos, PAGE_KEY(from, from_pos), PAGE_DATA(from, from_pos)); delete_item(from, from_pos); } static void merge_pages(struct btree_page *lower, struct btree_page *higher) { const struct btree_def *def = lower->def; btree_t bt = lower->owner; assert (lower->num_children + higher->num_children < def->branches); memcpy(PAGE_KEY(lower, lower->num_children), PAGE_KEY(higher, 0), higher->num_children * def->key_size); if (lower->height) memcpy(PAGE_PTR(lower, lower->num_children), PAGE_PTR(higher, 0), higher->num_children * sizeof(struct btree_page *)); else memcpy(PAGE_DATA(lower, lower->num_children), PAGE_DATA(higher, 0), higher->num_children * def->data_size); lower->num_children += higher->num_children; /* Fix up the cursor if we subsumed an active page */ if (bt->slot[0] >= 0) { if (bt->path[higher->height] == higher) { bt->path[higher->height] = lower; bt->slot[higher->height] += lower->num_children; } } } static int find_key_le(const struct btree_page *p, const void *key) { const struct btree_def *def = p->def; int i; for (i = 0; i < p->num_children; i++) if (def->compare(key, PAGE_KEY(p, i)) < 0) return i - 1; return p->num_children - 1; } static int trace_path(btree_t bt, const void *key, struct btree_page **path, int *slot) { const struct btree_def *def = bt->def; struct btree_page *p = bt->root; int h; for (h = p->height; h >= 0; h--) { int s = find_key_le(p, key); path[h] = p; slot[h] = s; if (h) { assert (s >= 0); p = *PAGE_PTR(p, s); } else if (s >= 0 && !def->compare(key, PAGE_KEY(p, s))) { return 1; } } return 0; } static void cursor_first(btree_t bt) { int h; struct btree_page *p = bt->root; if (!bt->root->num_children) { bt->slot[0] = -1; return; } for (h = bt->root->height; h >= 0; h--) { assert (p->num_children > 0); bt->path[h] = p; bt->slot[h] = 0; if (h) p = *PAGE_PTR(p, 0); } } static void cursor_next(btree_t bt) { int h; if (bt->slot[0] < 0) return; /* Ascend until we find a suitable sibling */ for (h = 0; h <= bt->root->height; h++) { struct btree_page *p = bt->path[h]; if (bt->slot[h] + 1 < p->num_children) { bt->slot[h]++; while (h > 0) { p = *PAGE_PTR(p, bt->slot[h]); h--; bt->slot[h] = 0; bt->path[h] = p; } return; } } /* Exhausted all levels */ bt->slot[0] = -1; } /************************************************************************ * Public interface */ btree_t btree_alloc(const struct btree_def *def) { btree_t bt; if (def->branches < 2 || (def->branches & 1)) { printc_err("btree: invalid branch count: %d\n", def->branches); return NULL; } bt = malloc(sizeof(*bt)); if (!bt) { printc_err("btree: couldn't allocate tree: %s\n", last_error()); return NULL; } memset(bt, 0, sizeof(*bt)); bt->def = def; bt->slot[0] = -1; bt->root = allocate_page(bt, 0); if (!bt->root) { printc_err("btree: couldn't allocate root node: %s\n", last_error()); free(bt); return NULL; } return bt; } void btree_free(btree_t bt) { check_btree(bt); destroy_page(bt->root); free(bt); } void btree_clear(btree_t bt) { struct btree_page *p; struct btree_page *path_up = 0; check_btree(bt); /* The cursor will have nothing to point to after this. */ bt->slot[0] = -1; /* First, find the last leaf node, which we can re-use as an * empty root. */ p = bt->root; while (p->height) { path_up = p; p = *PAGE_PTR(p, p->num_children - 1); } /* Unlink it from the tree and then destroy everything else. */ if (path_up) { path_up->num_children--; destroy_page(bt->root); } /* Clear it out and make it the new root */ p->num_children = 0; bt->root = p; } int btree_put(btree_t bt, const void *key, const void *data) { const struct btree_def *def = bt->def; struct btree_page *new_root = NULL; struct btree_page *path_new[MAX_HEIGHT] = {0}; struct btree_page *path_old[MAX_HEIGHT] = {0}; int slot_old[MAX_HEIGHT] = {0}; int h; check_btree(bt); /* Special case: cursor overwrite */ if (!key) { if (bt->slot[0] < 0) { printc_err("btree: put at invalid cursor\n"); return -1; } memcpy(PAGE_DATA(bt->path[0], bt->slot[0]), data, def->data_size); return 1; } /* Find a path down the tree that leads to the page which should * contain this datum (though the page might be too big to hold it). */ if (trace_path(bt, key, path_old, slot_old)) { /* Special case: overwrite existing item */ memcpy(PAGE_DATA(path_old[0], slot_old[0]), data, def->data_size); return 1; } /* Trace from the leaf up. If the leaf is at its maximum size, it will * need to split, and cause a pointer to be added in the parent page * of the same node (which may in turn cause it to split). */ for (h = 0; h <= bt->root->height; h++) { if (path_old[h]->num_children < def->branches) break; path_new[h] = allocate_page(bt, h); if (!path_new[h]) goto fail; } /* If the split reaches the top (i.e. the root splits), then we need * to allocate a new root node. */ if (h > bt->root->height) { if (h >= MAX_HEIGHT) { printc_err("btree: maximum height exceeded\n"); goto fail; } new_root = allocate_page(bt, h); if (!new_root) goto fail; } /* Trace up to one page above the split. At each page that needs * splitting, copy the top half of keys into the new page. Also, * insert a key into one of the pages at all pages from the leaf * to the page above the top of the split. */ for (h = 0; h <= bt->root->height; h++) { int s = slot_old[h] + 1; struct btree_page *p = path_old[h]; /* If there's a split at this level, copy the top half of * the keys from the old page to the new one. Check to see * if the position we were going to insert into is in the * old page or the new one. */ if (path_new[h]) { split_page(path_old[h], path_new[h]); if (s > p->num_children) { s -= p->num_children; p = path_new[h]; } } /* Insert the key in the appropriate page */ if (h) insert_ptr(p, s, PAGE_KEY(path_new[h - 1], 0), path_new[h - 1]); else insert_data(p, s, key, data); /* If there was no split at this level, there's nothing to * insert higher up, and we're all done. */ if (!path_new[h]) return 0; } /* If we made it this far, the split reached the top of the tree, and * we need to grow it using the extra page we allocated. */ assert (new_root); if (bt->slot[0] >= 0) { /* Fix up the cursor, if active */ bt->slot[new_root->height] = bt->path[bt->root->height] == new_root ? 1 : 0; bt->path[new_root->height] = new_root; } memcpy(PAGE_KEY(new_root, 0), def->zero, def->key_size); *PAGE_PTR(new_root, 0) = path_old[h - 1]; memcpy(PAGE_KEY(new_root, 1), PAGE_KEY(path_new[h - 1], 0), def->key_size); *PAGE_PTR(new_root, 1) = path_new[h - 1]; new_root->num_children = 2; bt->root = new_root; return 0; fail: for (h = 0; h <= bt->root->height; h++) if (path_new[h]) free(path_new[h]); return -1; } int btree_delete(btree_t bt, const void *key) { const struct btree_def *def = bt->def; const int halfsize = def->branches / 2; struct btree_page *path[MAX_HEIGHT] = {0}; int slot[MAX_HEIGHT] = {0}; int h; check_btree(bt); /* Trace a path to the item to be deleted */ if (!key) { if (bt->slot[0] < 0) return 1; memcpy(path, bt->path, sizeof(path)); memcpy(slot, bt->slot, sizeof(slot)); } else if (!trace_path(bt, key, path, slot)) { return 1; } /* Select the next item if we're deleting at the cursor */ if (bt->slot[0] == slot[0] && bt->path[0] == path[0]) cursor_next(bt); /* Delete from the leaf node. If it's still full enough, then we don't * need to do anything else. */ delete_item(path[0], slot[0]); if (path[0]->num_children >= halfsize) return 0; /* Trace back up the tree, fixing underfull nodes. If we can fix by * borrowing, do it and we're done. Otherwise, we need to fix by * merging, which may result in another underfull node, and we need * to continue. */ for (h = 1; h <= bt->root->height; h++) { struct btree_page *p = path[h]; struct btree_page *c = path[h - 1]; int s = slot[h]; if (s > 0) { /* Borrow/merge from lower page */ struct btree_page *d = *PAGE_PTR(p, s - 1); if (d->num_children > halfsize) { move_item(d, d->num_children - 1, c, 0); memcpy(PAGE_KEY(p, s), PAGE_KEY(c, 0), def->key_size); return 0; } merge_pages(d, c); delete_item(p, s); free(c); } else { /* Borrow/merge from higher page */ struct btree_page *d = *PAGE_PTR(p, s + 1); if (d->num_children > halfsize) { move_item(d, 0, c, c->num_children); memcpy(PAGE_KEY(p, s + 1), PAGE_KEY(d, 0), def->key_size); return 0; } merge_pages(c, d); delete_item(p, s + 1); free(d); } if (p->num_children >= halfsize) return 0; } /* If the root contains only a single pointer to another page, * shrink the tree. This does not affect the cursor. */ if (bt->root->height && bt->root->num_children == 1) { struct btree_page *old = bt->root; bt->root = *PAGE_PTR(old, 0); free(old); } return 0; } int btree_get(btree_t bt, const void *key, void *data) { const struct btree_def *def = bt->def; struct btree_page *p = bt->root; int h; check_btree(bt); if (!key) return btree_select(bt, NULL, BTREE_READ, NULL, data); for (h = bt->root->height; h >= 0; h--) { int s = find_key_le(p, key); if (h) { assert (s >= 0 && s < p->num_children); p = *PAGE_PTR(p, s); } else if (s >= 0 && !def->compare(key, PAGE_KEY(p, s))) { memcpy(data, PAGE_DATA(p, s), def->data_size); return 0; } } return 1; } int btree_select(btree_t bt, const void *key, btree_selmode_t mode, void *key_ret, void *data_ret) { const struct btree_def *def = bt->def; check_btree(bt); switch (mode) { case BTREE_CLEAR: bt->slot[0] = -1; break; case BTREE_READ: break; case BTREE_EXACT: case BTREE_LE: if (!trace_path(bt, key, bt->path, bt->slot) && mode == BTREE_EXACT) bt->slot[0] = -1; break; case BTREE_FIRST: cursor_first(bt); break; case BTREE_NEXT: cursor_next(bt); break; } /* Return the data at the cursor */ if (bt->slot[0] >= 0) { if (key_ret) memcpy(key_ret, PAGE_KEY(bt->path[0], bt->slot[0]), def->key_size); if (data_ret) memcpy(data_ret, PAGE_DATA(bt->path[0], bt->slot[0]), def->data_size); return 0; } return 1; } mspdebug-0.25/util/btree.h000066400000000000000000000062411313531517500155040ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef BTREE_H_ #define BTREE_H_ typedef int (*btree_compare_t)(const void *left, const void *right); struct btree_def { int key_size; int data_size; int branches; const void *zero; btree_compare_t compare; }; struct btree; typedef struct btree *btree_t; /* Instantiate a new B+Tree, given the definition. The definition must * remain valid for the duration of the B+Tree's existence. * * Returns NULL on error. */ btree_t btree_alloc(const struct btree_def *def); /* Destroy a B+Tree */ void btree_free(btree_t bt); /* Clear all data from a B+Tree */ void btree_clear(btree_t bt); /* Add or update a record in a B+Tree. Any existing data for the key will * be overwritten. * * Specifying a NULL key causes the cursor value to be overwritten. * * Returns 1 if the key already existed, 0 if a new key was inserted, * or -1 if an error occurs (failed memory allocation). */ int btree_put(btree_t bt, const void *key, const void *data); /* Delete a value from a B+Tree. If the key is NULL, the value at the cursor * is deleted, and the cursor is updated to point to the next item. * * Returns 0 if the key existed, 1 if it didn't. */ int btree_delete(btree_t bt, const void *key); /* Retrieve an item from the B+Tree. If the key is NULL, the value at the * cursor is retrieved. Optionally, the actual key value can be retrieved * into key_ret (this may be useful if the keys are compared case-insensitive, * or if fetching the cursor item). * * Returns 0 if the key existed, 1 if it didn't. */ int btree_get(btree_t bt, const void *key, void *data); /* Cursor manipulation. This function takes a cursor movement command, * some of which require a key argument. * * After the command is completed, the currently selected key and value * are returned via the supplied pointers key_ret and data_ret (each of * which may be NULL). * * Returns 0 if a record was selected, 1 if not. */ typedef enum { BTREE_EXACT, /* find the exact item */ BTREE_LE, /* find the largest item <= the key */ BTREE_NEXT, /* find the next item after the cursor */ BTREE_FIRST, /* find the first item in the tree */ BTREE_CLEAR, /* clear the cursor */ BTREE_READ /* fetch the current record without moving */ } btree_selmode_t; int btree_select(btree_t bt, const void *key, btree_selmode_t mode, void *key_ret, void *data_ret); #endif mspdebug-0.25/util/bytes.h000066400000000000000000000037731313531517500155400ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2013 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef BYTES_H_ #define BYTES_H_ #include /* Read/write big-endian 16-bit */ static inline uint16_t r16be(const uint8_t *buf) { return (((uint16_t)buf[0]) << 8) | ((uint16_t)buf[1]); } static inline void w16be(uint8_t *buf, uint16_t v) { buf[0] = v >> 8; buf[1] = v; } /* Read/write little-endian 16-bit */ static inline uint16_t r16le(const uint8_t *buf) { return (((uint16_t)buf[1]) << 8) | ((uint16_t)buf[0]); } static inline void w16le(uint8_t *buf, uint16_t v) { buf[1] = v >> 8; buf[0] = v; } /* Read/write big-endian 32-bit */ static inline uint32_t r32be(const uint8_t *buf) { return (((uint32_t)buf[0]) << 24) | (((uint32_t)buf[1]) << 16) | (((uint32_t)buf[2]) << 8) | ((uint32_t)buf[3]); } static inline void w32be(uint8_t *buf, uint32_t v) { buf[0] = v >> 24; buf[1] = v >> 16; buf[2] = v >> 8; buf[3] = v; } /* Read/write little-endian 32-bit */ static inline uint32_t r32le(const uint8_t *buf) { return (((uint32_t)buf[3]) << 24) | (((uint32_t)buf[2]) << 16) | (((uint32_t)buf[1]) << 8) | ((uint32_t)buf[0]); } static inline void w32le(uint8_t *buf, uint32_t v) { buf[3] = v >> 24; buf[2] = v >> 16; buf[1] = v >> 8; buf[0] = v; } #endif mspdebug-0.25/util/chipinfo.c000066400000000000000000000050731313531517500161770ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2013 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include "chipinfo.h" #include "../chipinfo.db" static int is_match(const struct chipinfo_id *a, const struct chipinfo_id *b, const struct chipinfo_id *mask) { if ((a->ver_id ^ b->ver_id) & mask->ver_id) return 0; if ((a->ver_sub_id ^ b->ver_sub_id) & mask->ver_sub_id) return 0; if ((a->revision ^ b->revision) & mask->revision) return 0; if ((a->fab ^ b->fab) & mask->fab) return 0; if ((a->self ^ b->self) & mask->self) return 0; if ((a->config ^ b->config) & mask->config) return 0; if ((a->fuses ^ b->fuses) & mask->fuses) return 0; return 1; } const struct chipinfo *chipinfo_find_by_id(const struct chipinfo_id *id) { const struct chipinfo *i; for (i = chipinfo_db; i->name; i++) if (is_match(&i->id, id, &i->id_mask)) return i; return NULL; } const struct chipinfo *chipinfo_find_by_name(const char *name) { const struct chipinfo *i; for (i = chipinfo_db; i->name; i++) if (!strcasecmp(name, i->name)) return i; return NULL; } const struct chipinfo_memory *chipinfo_find_mem_by_name (const struct chipinfo *info, const char *name) { const struct chipinfo_memory *m; for (m = info->memory; m->name; m++) if (!strcasecmp(m->name, name)) return m; return NULL; } const struct chipinfo_memory *chipinfo_find_mem_by_addr (const struct chipinfo *info, uint32_t offset) { const struct chipinfo_memory *m; const struct chipinfo_memory *best = NULL; for (m = info->memory; m->name; m++) { if (!m->mapped) continue; if (m->offset + m->size <= offset) continue; if (!best || (m->offset < best->offset)) best = m; } return best; } const char *chipinfo_copyright(void) { return "Chip info database from MSP430.dll v" CI_DLL430_VERSION_STRING " Copyright (C) 2013 TI, Inc.\n"; } mspdebug-0.25/util/chipinfo.h000066400000000000000000000102161313531517500161770ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2013 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef CHIPINFO_H_ #define CHIPINFO_H_ #include struct chipinfo_funclet { uint16_t code_size; uint16_t max_payload; uint16_t entry_point; uint16_t code[512]; }; typedef enum { CHIPINFO_PSA_REGULAR, CHIPINFO_PSA_ENHANCED } chipinfo_psa_t; struct chipinfo_id { uint16_t ver_id; uint16_t ver_sub_id; uint8_t revision; uint8_t fab; uint16_t self; uint8_t config; uint8_t fuses; uint32_t activation_key; }; struct chipinfo_eem { uint8_t state_storage; uint8_t cycle_counter; uint8_t cycle_counter_ops; uint8_t trig_emulation_level; uint8_t trig_mem; uint8_t trig_reg; uint8_t trig_combinations; uint8_t trig_options; uint8_t trig_dma; uint8_t trig_read_write; uint8_t trig_reg_ops; uint8_t trig_comp_level; uint8_t trig_mem_cond_level; uint8_t trig_mem_umask_level; uint8_t seq_states; uint8_t seq_start; uint8_t seq_end; uint8_t seq_reset; uint8_t seq_blocked; }; struct chipinfo_voltage { uint16_t vcc_min; uint16_t vcc_max; uint16_t vcc_flash_min; uint16_t vcc_secure_min; uint16_t vpp_secure_min; uint16_t vpp_secure_max; uint8_t has_test_vpp; }; struct chipinfo_power { uint32_t reg_mask; uint32_t enable_lpm5; uint32_t disable_lpm5; uint32_t reg_mask_3v; uint32_t enable_lpm5_3v; uint32_t disable_lpm5_3v; }; typedef enum { CHIPINFO_CLOCK_SYS_BC_1XX, CHIPINFO_CLOCK_SYS_BC_2XX, CHIPINFO_CLOCK_SYS_FLL_PLUS, CHIPINFO_CLOCK_SYS_MOD_OSC } chipinfo_clock_sys_t; typedef enum { CHIPINFO_FEATURE_I2C = 0x0001, CHIPINFO_FEATURE_LCFE = 0x0002, CHIPINFO_FEATURE_QUICK_MEM_READ = 0x0004, CHIPINFO_FEATURE_SFLLDH = 0x0008, CHIPINFO_FEATURE_FRAM = 0x0010, CHIPINFO_FEATURE_NO_BSL = 0x0020, CHIPINFO_FEATURE_TMR = 0x0040, CHIPINFO_FEATURE_JTAG = 0x0080, CHIPINFO_FEATURE_DTC = 0x0100, CHIPINFO_FEATURE_SYNC = 0x0200, CHIPINFO_FEATURE_INSTR = 0x0400, CHIPINFO_FEATURE_1337 = 0x0800, CHIPINFO_FEATURE_PSACH = 0x1000 } chipinfo_features_t; typedef enum { CHIPINFO_MEMTYPE_ROM, CHIPINFO_MEMTYPE_RAM, CHIPINFO_MEMTYPE_FLASH, CHIPINFO_MEMTYPE_REGISTER } chipinfo_memtype_t; struct chipinfo_memory { const char *name; chipinfo_memtype_t type; unsigned int bits; unsigned int mapped; unsigned int size; uint32_t offset; unsigned int seg_size; unsigned int bank_size; unsigned int banks; }; struct chipinfo_clockmap { const char *name; uint8_t value; }; struct chipinfo { const char *name; unsigned int bits; chipinfo_psa_t psa; uint8_t clock_control; uint16_t mclk_control; chipinfo_clock_sys_t clock_sys; chipinfo_features_t features; struct chipinfo_id id; struct chipinfo_id id_mask; struct chipinfo_eem eem; struct chipinfo_voltage voltage; struct chipinfo_power power; struct chipinfo_memory memory[16]; struct chipinfo_clockmap clock_map[32]; uint8_t v3_functions[128]; const struct chipinfo_funclet *v3_erase; const struct chipinfo_funclet *v3_write; const struct chipinfo_funclet *v3_unlock; }; extern const struct chipinfo chipinfo_db[]; const struct chipinfo *chipinfo_find_by_id(const struct chipinfo_id *id); const struct chipinfo *chipinfo_find_by_name(const char *name); const struct chipinfo_memory *chipinfo_find_mem_by_addr (const struct chipinfo *info, uint32_t offset); const struct chipinfo_memory *chipinfo_find_mem_by_name (const struct chipinfo *info, const char *name); const char *chipinfo_copyright(void); #endif mspdebug-0.25/util/ctrlc.c000066400000000000000000000052451313531517500155100ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include "ctrlc.h" #ifdef __Windows__ #include static int ctrlc_flag; static HANDLE ctrlc_event; static CRITICAL_SECTION ctrlc_cs; static WINAPI BOOL ctrlc_handler(DWORD event) { if ((event == CTRL_C_EVENT) || (event == CTRL_BREAK_EVENT)) { ctrlc_raise(); return TRUE; } return FALSE; } void ctrlc_init(void) { ctrlc_event = CreateEvent(0, TRUE, FALSE, NULL); InitializeCriticalSection(&ctrlc_cs); SetConsoleCtrlHandler(ctrlc_handler, TRUE); } void ctrlc_exit(void) { SetConsoleCtrlHandler(NULL, TRUE); DeleteCriticalSection(&ctrlc_cs); CloseHandle(ctrlc_event); } int ctrlc_check(void) { int cc; EnterCriticalSection(&ctrlc_cs); cc = ctrlc_flag; LeaveCriticalSection(&ctrlc_cs); return cc; } void ctrlc_clear(void) { EnterCriticalSection(&ctrlc_cs); ctrlc_flag = 0; ResetEvent(ctrlc_event); LeaveCriticalSection(&ctrlc_cs); } void ctrlc_raise(void) { EnterCriticalSection(&ctrlc_cs); ctrlc_flag = 1; SetEvent(ctrlc_event); LeaveCriticalSection(&ctrlc_cs); } HANDLE ctrlc_win32_event(void) { return ctrlc_event; } #else /* __Windows__ */ #include #include static volatile sig_atomic_t ctrlc_flag; static pthread_t ctrlc_thread; static void sigint_handler(int signum) { (void)signum; ctrlc_flag = 1; } void ctrlc_init(void) { #ifndef __CYGWIN__ static const struct sigaction siga = { .sa_handler = sigint_handler, .sa_flags = 0 }; #endif ctrlc_thread = pthread_self(); #ifdef __CYGWIN__ signal(SIGINT, sigint_handler); #else sigaction(SIGINT, &siga, NULL); #endif } void ctrlc_exit(void) { signal(SIGINT, SIG_DFL); } void ctrlc_clear(void) { ctrlc_flag = 0; } void ctrlc_raise(void) { pthread_kill(ctrlc_thread, SIGINT); } int ctrlc_check(void) { #ifdef __CYGWIN__ /* Cygwin's signal emulation seems to require the process to * block. */ usleep(1); #endif return ctrlc_flag; } #endif mspdebug-0.25/util/ctrlc.h000066400000000000000000000046611313531517500155160ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef CTRLC_H_ #define CTRLC_H_ #ifdef __Windows__ #include #endif /* The Ctrl+C subsystem provides a mechanism for interrupting IO * operations in a controlled way. Relevant signals are captured (SIGINT * on Linux and console events on Windows) and the event is reported to * the system. * * The Ctrl+C state has the semantics of an event variable: it can be * either set, reset or checked via the interface provided. */ /* Set up Ctrl+C handling and register all necessary handlers. */ void ctrlc_init(void); void ctrlc_exit(void); /* Check the state of the Ctrl+C event variable. This function returns * non-zero if the event is raised. */ int ctrlc_check(void); /* Manually reset the Ctrl+C event. This should be done before starting * the processing of a command. */ void ctrlc_clear(void); /* Manually raise a Ctrl+C event. This function is safe to call from any * thread. */ void ctrlc_raise(void); #ifdef __Windows__ /* On Unix systems, Ctrl+C generates a signal which will also interrupt * any IO operation currently in progress, after which the event will be * checked by the initiator of the operation. * * Under Windows, we don't have this facility, so we expose a kernel * object which becomes signalled when the Ctrl+C event is raised. * Implementations of Windows IO operations should allow operations to * be interrupted by the signalling of this object. * * The event can be manually cleared before IO operations, but this * doesn't clear the recorded Ctrl+C event. If the event is manually * cleared, the Ctrl+C event status should be checked *after* doing so. */ HANDLE ctrlc_win32_event(void); #endif #endif mspdebug-0.25/util/demangle.c000066400000000000000000000050261313531517500161520ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include "opdb.h" #include "stab.h" /* Buffer in which the demangler result will be constructed. */ struct dmbuf { char *out; size_t max_len; size_t len; }; /* Add a chunk of text to the buffer */ static int dm_append(struct dmbuf *d, const char *text, size_t len) { size_t i; if (d->len + len + 1 > d->max_len) return -1; for (i = 0; i < len; i++) { if (!text[i]) return -1; d->out[d->len++] = text[i]; } d->out[d->len] = 0; return 0; } /* Demangle a single component (possibly part of a nested name). */ static int dm_component(struct dmbuf *d, const char *text, const char **out) { char *next; unsigned int len = strtoul(text, &next, 10); if (next == text) return -1; if (dm_append(d, next, len) < 0) return -1; if (out) *out = next + len; return 0; } /* Demangler interface */ int demangle(const char *raw, char *out, size_t max_len) { struct dmbuf d; d.out = out; d.max_len = max_len; d.len = 0; if (*raw != '_' || raw[1] != 'Z') return -1; raw += 2; if (*raw == 'N') { const char *next; /* Skip CV qualifiers */ raw++; while (*raw == 'v' || *raw == 'V' || *raw == 'K') raw++; next = raw; while (*next != 'C' && *next != 'D' && *next != 'E') { const char *comp = next; if (d.len > 0 && dm_append(&d, "::", 2) < 0) return -1; if (dm_component(&d, comp, &next) < 0) return -1; if (*next == 'C' || *next == 'D') { /* Constructor/Destructor */ if (dm_append(&d, "::", 2) < 0) return -1; if (*next == 'D' && dm_append(&d, "~", 1) < 0) return -1; if (dm_component(&d, comp, NULL) < 0) return -1; } } } else { if (dm_component(&d, raw, NULL) < 0) return -1; } return d.len; } mspdebug-0.25/util/demangle.h000066400000000000000000000017071313531517500161610ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef DEMANGLE_H_ #define DEMANGLE_H_ /* Demangle a function name into the buffer "out". */ int demangle(const char *raw, char *out, size_t max_len); #endif mspdebug-0.25/util/dis.c000066400000000000000000000612641313531517500151630ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include #include #include "dis.h" #include "util.h" #define ALL_ONES 0xfffff #define EXTENSION_BIT 0x20000 /**********************************************************************/ /* Disassembler */ static address_t add_index(address_t reg_base, address_t index, int is_20bit) { return (reg_base + index) & (is_20bit ? 0xfffff : 0xffff); } static int decode_00xx(const uint8_t *code, address_t len, struct msp430_instruction *insn) { uint16_t op = code[0] | (code[1] << 8); int subtype = (op >> 4) & 0xf; int have_arg = 0; address_t arg = 0; /* Parameters common to most cases */ insn->op = MSP430_OP_MOVA; insn->itype = MSP430_ITYPE_DOUBLE; insn->dsize = MSP430_DSIZE_AWORD; insn->dst_mode = MSP430_AMODE_REGISTER; insn->dst_reg = op & 0xf; insn->src_mode = MSP430_AMODE_REGISTER; insn->src_reg = (op >> 8) & 0xf; if (len >= 4) { have_arg = 1; arg = code[2] | (code[3] << 8); } switch (subtype) { case 0: insn->src_mode = MSP430_AMODE_INDIRECT; return 2; case 1: insn->src_mode = MSP430_AMODE_INDIRECT_INC; return 2; case 2: if (!have_arg) return -1; insn->src_mode = MSP430_AMODE_ABSOLUTE; insn->src_addr = ((op & 0xf00) << 8) | arg; return 4; case 3: if (!have_arg) return -1; insn->src_mode = MSP430_AMODE_INDEXED; insn->src_addr = arg; return 4; case 4: case 5: /* RxxM */ insn->itype = MSP430_ITYPE_DOUBLE; insn->op = op & 0xf3e0; insn->dst_mode = MSP430_AMODE_REGISTER; insn->dst_reg = op & 0xf; insn->src_mode = MSP430_AMODE_IMMEDIATE; insn->src_addr = 1 + ((op >> 10) & 3); insn->dsize = (op & 0x0010) ? MSP430_DSIZE_WORD : MSP430_DSIZE_AWORD; return 2; case 6: if (!have_arg) return -1; insn->dst_mode = MSP430_AMODE_ABSOLUTE; insn->dst_addr = ((op & 0xf) << 16) | arg; return 4; case 7: if (!have_arg) return -1; insn->dst_mode = MSP430_AMODE_INDEXED; insn->dst_addr = arg; return 4; case 8: if (!have_arg) return -1; insn->src_mode = MSP430_AMODE_IMMEDIATE; insn->src_addr = ((op & 0xf00) << 8) | arg; return 4; case 9: if (!have_arg) return -1; insn->op = MSP430_OP_CMPA; insn->src_mode = MSP430_AMODE_IMMEDIATE; insn->src_addr = ((op & 0xf00) << 8) | arg; return 4; case 10: if (!have_arg) return -1; insn->op = MSP430_OP_ADDA; insn->src_mode = MSP430_AMODE_IMMEDIATE; insn->src_addr = ((op & 0xf00) << 8) | arg; return 4; case 11: if (!have_arg) return -1; insn->op = MSP430_OP_SUBA; insn->src_mode = MSP430_AMODE_IMMEDIATE; insn->src_addr = ((op & 0xf00) << 8) | arg; return 4; case 12: return 2; case 13: insn->op = MSP430_OP_CMPA; return 2; case 14: insn->op = MSP430_OP_ADDA; return 2; case 15: insn->op = MSP430_OP_SUBA; return 2; } return -1; } static int decode_13xx(const uint8_t *code, address_t len, struct msp430_instruction *insn) { uint16_t op = code[0] | (code[1] << 8); int subtype = (op >> 4) & 0xf; insn->itype = MSP430_ITYPE_SINGLE; insn->op = MSP430_OP_CALLA; switch (subtype) { case 0: insn->itype = MSP430_ITYPE_NOARG; insn->op = MSP430_OP_RETI; return 2; case 4: insn->dst_mode = MSP430_AMODE_REGISTER; insn->dst_reg = op & 0xf; return 2; case 5: insn->dst_mode = MSP430_AMODE_INDEXED; insn->dst_reg = op & 0xf; break; case 6: insn->dst_mode = MSP430_AMODE_INDIRECT; insn->dst_reg = op & 0xf; return 2; case 7: insn->dst_mode = MSP430_AMODE_INDIRECT_INC; insn->dst_reg = op & 0xf; return 2; case 8: insn->dst_mode = MSP430_AMODE_ABSOLUTE; insn->dst_addr = (address_t)(op & 0xf) << 16; break; case 9: insn->dst_mode = MSP430_AMODE_SYMBOLIC; insn->dst_addr = (address_t)(op & 0xf) << 16; break; case 11: insn->dst_mode = MSP430_AMODE_IMMEDIATE; insn->dst_addr = (address_t)(op & 0xf) << 16; break; default: return -1; } if (len < 4) return -1; insn->dsize = MSP430_DSIZE_AWORD; insn->dst_addr |= code[2]; insn->dst_addr |= code[3] << 8; return 4; } static int decode_14xx(const uint8_t *code, struct msp430_instruction *insn) { uint16_t op = (code[1] << 8) | code[0]; /* PUSHM/POPM */ insn->itype = MSP430_ITYPE_DOUBLE; insn->op = op & 0xfe00; insn->dst_mode = MSP430_AMODE_REGISTER; insn->dst_reg = op & 0xf; insn->src_mode = MSP430_AMODE_IMMEDIATE; insn->src_addr = 1 + ((op >> 4) & 0xf); insn->dsize = (op & 0x0100) ? MSP430_DSIZE_WORD : MSP430_DSIZE_AWORD; return 2; } /* Decode a single-operand instruction. * * Returns the number of bytes consumed in decoding, or -1 if the a * valid single-operand instruction could not be found. */ static int decode_single(const uint8_t *code, address_t offset, address_t size, struct msp430_instruction *insn) { uint16_t op = (code[1] << 8) | code[0]; int need_arg = 0; insn->itype = MSP430_ITYPE_SINGLE; insn->op = op & 0xff80; insn->dsize = (op & 0x0400) ? MSP430_DSIZE_BYTE : MSP430_DSIZE_WORD; insn->dst_mode = (op >> 4) & 0x3; insn->dst_reg = op & 0xf; switch (insn->dst_mode) { case MSP430_AMODE_REGISTER: break; case MSP430_AMODE_INDEXED: need_arg = 1; if (insn->dst_reg == MSP430_REG_PC) { insn->dst_addr = offset + 4; insn->dst_mode = MSP430_AMODE_SYMBOLIC; } else if (insn->dst_reg == MSP430_REG_SR) { insn->dst_mode = MSP430_AMODE_ABSOLUTE; } else if (insn->dst_reg == MSP430_REG_R3) { need_arg = 0; /* constant generator: #1 */ } break; case MSP430_AMODE_INDIRECT: break; case MSP430_AMODE_INDIRECT_INC: if (insn->dst_reg == MSP430_REG_PC) { insn->dst_mode = MSP430_AMODE_IMMEDIATE; need_arg = 1; } break; default: break; } if (need_arg) { if (size < 4) return -1; insn->dst_addr = add_index(insn->dst_addr, (code[3] << 8) | code[2], 0); return 4; } return 2; } /* Decode a double-operand instruction. * * Returns the number of bytes consumed or -1 if a valid instruction * could not be found. */ static int decode_double(const uint8_t *code, address_t offset, address_t size, struct msp430_instruction *insn, uint16_t ex_word) { uint16_t op = (code[1] << 8) | code[0]; int need_src = 0; int need_dst = 0; int ret = 2; /* Decode and consume opcode */ insn->itype = MSP430_ITYPE_DOUBLE; insn->op = op & 0xf000; insn->dsize = (op & 0x0040) ? MSP430_DSIZE_BYTE : MSP430_DSIZE_WORD; insn->src_mode = (op >> 4) & 0x3; insn->src_reg = (op >> 8) & 0xf; insn->dst_mode = (op >> 7) & 0x1; insn->dst_reg = op & 0xf; offset += 2; code += 2; size -= 2; /* Decode and consume source operand */ switch (insn->src_mode) { case MSP430_AMODE_REGISTER: break; case MSP430_AMODE_INDEXED: need_src = 1; if (insn->src_reg == MSP430_REG_PC) { insn->src_mode = MSP430_AMODE_SYMBOLIC; insn->src_addr = offset; } else if (insn->src_reg == MSP430_REG_SR) insn->src_mode = MSP430_AMODE_ABSOLUTE; else if (insn->src_reg == MSP430_REG_R3) need_src = 0; break; case MSP430_AMODE_INDIRECT: break; case MSP430_AMODE_INDIRECT_INC: if (insn->src_reg == MSP430_REG_PC) { insn->src_mode = MSP430_AMODE_IMMEDIATE; need_src = 1; } break; default: break; } if (need_src) { if (size < 2) return -1; insn->src_addr = add_index(insn->src_addr, ((ex_word << 9) & 0xf0000) | ((code[1] << 8) | code[0]), ex_word); offset += 2; code += 2; size -= 2; ret += 2; } /* Decode and consume destination operand */ switch (insn->dst_mode) { case MSP430_AMODE_REGISTER: break; case MSP430_AMODE_INDEXED: need_dst = 1; if (insn->dst_reg == MSP430_REG_PC) { insn->dst_mode = MSP430_AMODE_SYMBOLIC; insn->dst_addr = offset; } else if (insn->dst_reg == MSP430_REG_SR) insn->dst_mode = MSP430_AMODE_ABSOLUTE; break; default: break; } if (need_dst) { if (size < 2) return -1; insn->dst_addr = add_index(insn->dst_addr, ((ex_word << 16) & 0xf0000) | (code[1] << 8) | code[0], ex_word); ret += 2; } return ret; } /* Decode a jump instruction. * * All jump instructions are one word in length, so this function * always returns 2 (to indicate the consumption of 2 bytes). */ static int decode_jump(const uint8_t *code, address_t offset, struct msp430_instruction *insn) { uint16_t op = (code[1] << 8) | code[0]; int tgtrel = op & 0x3ff; if (tgtrel & 0x200) tgtrel -= 0x400; insn->op = op & 0xfc00; insn->itype = MSP430_ITYPE_JUMP; insn->dst_addr = offset + 2 + tgtrel * 2; insn->dst_mode = MSP430_AMODE_SYMBOLIC; insn->dst_reg = MSP430_REG_PC; return 2; } static void remap_cgen(msp430_amode_t *mode, address_t *addr, msp430_reg_t *reg) { if (*reg == MSP430_REG_SR) { if (*mode == MSP430_AMODE_INDIRECT) { *mode = MSP430_AMODE_IMMEDIATE; *addr = 4; } else if (*mode == MSP430_AMODE_INDIRECT_INC) { *mode = MSP430_AMODE_IMMEDIATE; *addr = 8; } } else if (*reg == MSP430_REG_R3) { if (*mode == MSP430_AMODE_REGISTER) *addr = 0; else if (*mode == MSP430_AMODE_INDEXED) *addr = 1; else if (*mode == MSP430_AMODE_INDIRECT) *addr = 2; else if (*mode == MSP430_AMODE_INDIRECT_INC) *addr = ALL_ONES; *mode = MSP430_AMODE_IMMEDIATE; } } /* Take a decoded instruction and replace certain addressing modes of * the constant generator registers with their corresponding immediate * values. */ static void find_cgens(struct msp430_instruction *insn) { if (insn->itype == MSP430_ITYPE_DOUBLE) remap_cgen(&insn->src_mode, &insn->src_addr, &insn->src_reg); else if (insn->itype == MSP430_ITYPE_SINGLE) remap_cgen(&insn->dst_mode, &insn->dst_addr, &insn->dst_reg); } /* Recognise special cases of real instructions and translate them to * emulated instructions. */ static void find_emulated_ops(struct msp430_instruction *insn) { switch (insn->op) { case MSP430_OP_ADD: if (insn->src_mode == MSP430_AMODE_IMMEDIATE) { if (insn->src_addr == 1) { insn->op = MSP430_OP_INC; insn->itype = MSP430_ITYPE_SINGLE; } else if (insn->src_addr == 2) { insn->op = MSP430_OP_INCD; insn->itype = MSP430_ITYPE_SINGLE; } } else if (insn->dst_mode == insn->src_mode && insn->dst_reg == insn->src_reg && insn->dst_addr == insn->src_addr) { insn->op = MSP430_OP_RLA; insn->itype = MSP430_ITYPE_SINGLE; } break; case MSP430_OP_ADDA: if (insn->src_mode == MSP430_AMODE_IMMEDIATE && insn->src_addr == 2) { insn->op = MSP430_OP_INCDA; insn->itype = MSP430_ITYPE_SINGLE; } break; case MSP430_OP_ADDX: if (insn->src_mode == MSP430_AMODE_IMMEDIATE) { if (insn->src_addr == 1) { insn->op = MSP430_OP_INCX; insn->itype = MSP430_ITYPE_SINGLE; } else if (insn->src_addr == 2) { insn->op = MSP430_OP_INCDX; insn->itype = MSP430_ITYPE_SINGLE; } } else if (insn->dst_mode == insn->src_mode && insn->dst_reg == insn->src_reg && insn->dst_addr == insn->src_addr) { insn->op = MSP430_OP_RLAX; insn->itype = MSP430_ITYPE_SINGLE; } break; case MSP430_OP_ADDC: if (insn->src_mode == MSP430_AMODE_IMMEDIATE && !insn->src_addr) { insn->op = MSP430_OP_ADC; insn->itype = MSP430_ITYPE_SINGLE; } else if (insn->dst_mode == insn->src_mode && insn->dst_reg == insn->src_reg && insn->dst_addr == insn->src_addr) { insn->op = MSP430_OP_RLC; insn->itype = MSP430_ITYPE_SINGLE; } break; case MSP430_OP_ADDCX: if (insn->src_mode == MSP430_AMODE_IMMEDIATE && !insn->src_addr) { insn->op = MSP430_OP_ADCX; insn->itype = MSP430_ITYPE_SINGLE; } else if (insn->dst_mode == insn->src_mode && insn->dst_reg == insn->src_reg && insn->dst_addr == insn->src_addr) { insn->op = MSP430_OP_RLCX; insn->itype = MSP430_ITYPE_SINGLE; } break; case MSP430_OP_BIC: if (insn->dst_mode == MSP430_AMODE_REGISTER && insn->dst_reg == MSP430_REG_SR && insn->src_mode == MSP430_AMODE_IMMEDIATE) { if (insn->src_addr == 1) { insn->op = MSP430_OP_CLRC; insn->itype = MSP430_ITYPE_NOARG; } else if (insn->src_addr == 4) { insn->op = MSP430_OP_CLRN; insn->itype = MSP430_ITYPE_NOARG; } else if (insn->src_addr == 2) { insn->op = MSP430_OP_CLRZ; insn->itype = MSP430_ITYPE_NOARG; } else if (insn->src_addr == 8) { insn->op = MSP430_OP_DINT; insn->itype = MSP430_ITYPE_NOARG; } } break; case MSP430_OP_BIS: if (insn->dst_mode == MSP430_AMODE_REGISTER && insn->dst_reg == MSP430_REG_SR && insn->src_mode == MSP430_AMODE_IMMEDIATE) { if (insn->src_addr == 1) { insn->op = MSP430_OP_SETC; insn->itype = MSP430_ITYPE_NOARG; } else if (insn->src_addr == 4) { insn->op = MSP430_OP_SETN; insn->itype = MSP430_ITYPE_NOARG; } else if (insn->src_addr == 2) { insn->op = MSP430_OP_SETZ; insn->itype = MSP430_ITYPE_NOARG; } else if (insn->src_addr == 8) { insn->op = MSP430_OP_EINT; insn->itype = MSP430_ITYPE_NOARG; } } break; case MSP430_OP_CMP: if (insn->src_mode == MSP430_AMODE_IMMEDIATE && !insn->src_addr) { insn->op = MSP430_OP_TST; insn->itype = MSP430_ITYPE_SINGLE; } break; case MSP430_OP_CMPA: if (insn->src_mode == MSP430_AMODE_IMMEDIATE && !insn->src_addr) { insn->op = MSP430_OP_TSTA; insn->itype = MSP430_ITYPE_SINGLE; } break; case MSP430_OP_CMPX: if (insn->src_mode == MSP430_AMODE_IMMEDIATE && !insn->src_addr) { insn->op = MSP430_OP_TSTX; insn->itype = MSP430_ITYPE_SINGLE; } break; case MSP430_OP_DADD: if (insn->src_mode == MSP430_AMODE_IMMEDIATE && !insn->src_addr) { insn->op = MSP430_OP_DADC; insn->itype = MSP430_ITYPE_SINGLE; } break; case MSP430_OP_DADDX: if (insn->src_mode == MSP430_AMODE_IMMEDIATE && !insn->src_addr) { insn->op = MSP430_OP_DADCX; insn->itype = MSP430_ITYPE_SINGLE; } break; case MSP430_OP_MOV: if (insn->src_mode == MSP430_AMODE_INDIRECT_INC && insn->src_reg == MSP430_REG_SP) { if (insn->dst_mode == MSP430_AMODE_REGISTER && insn->dst_reg == MSP430_REG_PC) { insn->op = MSP430_OP_RET; insn->itype = MSP430_ITYPE_NOARG; } else { insn->op = MSP430_OP_POP; insn->itype = MSP430_ITYPE_SINGLE; } } else if (insn->dst_mode == MSP430_AMODE_REGISTER && insn->dst_reg == MSP430_REG_PC) { insn->op = MSP430_OP_BR; insn->itype = MSP430_ITYPE_SINGLE; insn->dst_mode = insn->src_mode; insn->dst_reg = insn->src_reg; insn->dst_addr = insn->src_addr; } else if (insn->src_mode == MSP430_AMODE_IMMEDIATE && !insn->src_addr) { if (insn->dst_mode == MSP430_AMODE_REGISTER && insn->dst_reg == MSP430_REG_R3) { insn->op = MSP430_OP_NOP; insn->itype = MSP430_ITYPE_NOARG; } else { insn->op = MSP430_OP_CLR; insn->itype = MSP430_ITYPE_SINGLE; } } break; case MSP430_OP_MOVA: if (insn->src_mode == MSP430_AMODE_INDIRECT_INC && insn->src_reg == MSP430_REG_SP) { if (insn->dst_mode == MSP430_AMODE_REGISTER && insn->dst_reg == MSP430_REG_PC) { insn->op = MSP430_OP_RETA; insn->itype = MSP430_ITYPE_NOARG; } else { insn->op = MSP430_OP_POPX; insn->itype = MSP430_ITYPE_SINGLE; } } else if (insn->dst_mode == MSP430_AMODE_REGISTER && insn->dst_reg == MSP430_REG_PC) { insn->op = MSP430_OP_BRA; insn->itype = MSP430_ITYPE_SINGLE; insn->dst_mode = insn->src_mode; insn->dst_reg = insn->src_reg; insn->dst_addr = insn->src_addr; } else if (insn->src_mode == MSP430_AMODE_IMMEDIATE && !insn->src_addr) { if (insn->dst_mode == MSP430_AMODE_REGISTER && insn->dst_reg == MSP430_REG_R3) { insn->op = MSP430_OP_NOP; insn->itype = MSP430_ITYPE_NOARG; } else { insn->op = MSP430_OP_CLRX; insn->itype = MSP430_ITYPE_SINGLE; } } break; case MSP430_OP_SUB: if (insn->src_mode == MSP430_AMODE_IMMEDIATE) { if (insn->src_addr == 1) { insn->op = MSP430_OP_DEC; insn->itype = MSP430_ITYPE_SINGLE; } else if (insn->src_addr == 2) { insn->op = MSP430_OP_DECD; insn->itype = MSP430_ITYPE_SINGLE; } } break; case MSP430_OP_SUBA: if (insn->src_mode == MSP430_AMODE_IMMEDIATE && insn->src_addr == 2) { insn->op = MSP430_OP_DECDA; insn->itype = MSP430_ITYPE_SINGLE; } break; case MSP430_OP_SUBX: if (insn->src_mode == MSP430_AMODE_IMMEDIATE) { if (insn->src_addr == 1) { insn->op = MSP430_OP_DECX; insn->itype = MSP430_ITYPE_SINGLE; } else if (insn->src_addr == 2) { insn->op = MSP430_OP_DECDX; insn->itype = MSP430_ITYPE_SINGLE; } } break; case MSP430_OP_SUBC: if (insn->src_mode == MSP430_AMODE_IMMEDIATE && !insn->src_addr) { insn->op = MSP430_OP_SBC; insn->itype = MSP430_ITYPE_SINGLE; } break; case MSP430_OP_SUBCX: if (insn->src_mode == MSP430_AMODE_IMMEDIATE && !insn->src_addr) { insn->op = MSP430_OP_SECX; insn->itype = MSP430_ITYPE_SINGLE; } break; case MSP430_OP_XOR: if (insn->src_mode == MSP430_AMODE_IMMEDIATE && insn->src_addr == ALL_ONES) { insn->op = MSP430_OP_INV; insn->itype = MSP430_ITYPE_SINGLE; } break; case MSP430_OP_XORX: if (insn->src_mode == MSP430_AMODE_IMMEDIATE && insn->src_addr == ALL_ONES) { insn->op = MSP430_OP_INVX; insn->itype = MSP430_ITYPE_SINGLE; } break; default: break; } } /* Decode a single instruction. * * Returns the number of bytes consumed, or -1 if an error occured. * * The caller needs to pass a pointer to the bytes to be decoded, the * virtual offset of those bytes, and the maximum number available. If * successful, the decoded instruction is written into the structure * pointed to by insn. */ int dis_decode(const uint8_t *code, address_t offset, address_t len, struct msp430_instruction *insn) { uint16_t op; uint16_t ex_word = 0; int ret; address_t ds_mask = ALL_ONES; memset(insn, 0, sizeof(*insn)); insn->offset = offset; /* Perform decoding */ if (len < 2) return -1; op = (code[1] << 8) | code[0]; if ((op & 0xf800) == 0x1800) { ex_word = op; code += 2; offset += 2; len -= 2; if (len < 2) return -1; op = (code[1] << 8) | code[0]; if ((op & 0xf000) >= 0x4000) ret = decode_double(code, offset, len, insn, ex_word); else if ((op & 0xf000) == 0x1000 && (op & 0xfc00) < 0x1280) ret = decode_single(code, offset, len, insn); else return -1; insn->op |= EXTENSION_BIT; ret += 2; if (insn->dst_mode == MSP430_AMODE_REGISTER && (insn->itype == MSP430_ITYPE_SINGLE || insn->src_mode == MSP430_AMODE_REGISTER)) { if ((ex_word >> 8) & 1) { if (insn->op != MSP430_OP_RRCX) return -1; insn->op = MSP430_OP_RRUX; } insn->rep_register = (ex_word >> 7) & 1; insn->rep_index = ex_word & 0xf; } if (!(ex_word & 0x40)) insn->dsize |= 2; } else { if ((op & 0xf000) == 0x0000) ret = decode_00xx(code, len, insn); else if ((op & 0xfc00) == 0x1400) ret = decode_14xx(code, insn); else if ((op & 0xff00) == 0x1300) ret = decode_13xx(code, len, insn); else if ((op & 0xf000) == 0x1000) ret = decode_single(code, offset, len, insn); else if ((op & 0xf000) >= 0x2000 && (op & 0xf000) < 0x4000) ret = decode_jump(code, offset, insn); else if ((op & 0xf000) >= 0x4000) ret = decode_double(code, offset, len, insn, 0); else return -1; } /* Interpret "emulated" instructions, constant generation, and * trim data sizes. */ find_cgens(insn); find_emulated_ops(insn); if (insn->dsize == MSP430_DSIZE_BYTE) ds_mask = 0xff; else if (insn->dsize == MSP430_DSIZE_WORD) ds_mask = 0xffff; if (insn->src_mode == MSP430_AMODE_IMMEDIATE) insn->src_addr &= ds_mask; if (insn->dst_mode == MSP430_AMODE_IMMEDIATE) insn->dst_addr &= ds_mask; insn->len = ret; return ret; } static const struct { msp430_op_t op; const char *mnemonic; } opcode_names[] = { /* Single operand */ {MSP430_OP_RRC, "RRC"}, {MSP430_OP_SWPB, "SWPB"}, {MSP430_OP_RRA, "RRA"}, {MSP430_OP_SXT, "SXT"}, {MSP430_OP_PUSH, "PUSH"}, {MSP430_OP_CALL, "CALL"}, {MSP430_OP_RETI, "RETI"}, /* Jump */ {MSP430_OP_JNZ, "JNZ"}, {MSP430_OP_JZ, "JZ"}, {MSP430_OP_JNC, "JNC"}, {MSP430_OP_JC, "JC"}, {MSP430_OP_JN, "JN"}, {MSP430_OP_JL, "JL"}, {MSP430_OP_JGE, "JGE"}, {MSP430_OP_JMP, "JMP"}, /* Double operand */ {MSP430_OP_MOV, "MOV"}, {MSP430_OP_ADD, "ADD"}, {MSP430_OP_ADDC, "ADDC"}, {MSP430_OP_SUBC, "SUBC"}, {MSP430_OP_SUB, "SUB"}, {MSP430_OP_CMP, "CMP"}, {MSP430_OP_DADD, "DADD"}, {MSP430_OP_BIT, "BIT"}, {MSP430_OP_BIC, "BIC"}, {MSP430_OP_BIS, "BIS"}, {MSP430_OP_XOR, "XOR"}, {MSP430_OP_AND, "AND"}, /* Emulated instructions */ {MSP430_OP_ADC, "ADC"}, {MSP430_OP_BR, "BR"}, {MSP430_OP_CLR, "CLR"}, {MSP430_OP_CLRC, "CLRC"}, {MSP430_OP_CLRN, "CLRN"}, {MSP430_OP_CLRZ, "CLRZ"}, {MSP430_OP_DADC, "DADC"}, {MSP430_OP_DEC, "DEC"}, {MSP430_OP_DECD, "DECD"}, {MSP430_OP_DINT, "DINT"}, {MSP430_OP_EINT, "EINT"}, {MSP430_OP_INC, "INC"}, {MSP430_OP_INCD, "INCD"}, {MSP430_OP_INV, "INV"}, {MSP430_OP_NOP, "NOP"}, {MSP430_OP_POP, "POP"}, {MSP430_OP_RET, "RET"}, {MSP430_OP_RLA, "RLA"}, {MSP430_OP_RLC, "RLC"}, {MSP430_OP_SBC, "SBC"}, {MSP430_OP_SETC, "SETC"}, {MSP430_OP_SETN, "SETN"}, {MSP430_OP_SETZ, "SETZ"}, {MSP430_OP_TST, "TST"}, /* MSP430X double operand (extension word) */ {MSP430_OP_MOVX, "MOVX"}, {MSP430_OP_ADDX, "ADDX"}, {MSP430_OP_ADDCX, "ADDCX"}, {MSP430_OP_SUBCX, "SUBCX"}, {MSP430_OP_SUBX, "SUBX"}, {MSP430_OP_CMPX, "CMPX"}, {MSP430_OP_DADDX, "DADDX"}, {MSP430_OP_BITX, "BITX"}, {MSP430_OP_BICX, "BICX"}, {MSP430_OP_BISX, "BISX"}, {MSP430_OP_XORX, "XORX"}, {MSP430_OP_ANDX, "ANDX"}, /* MSP430X single operand (extension word) */ {MSP430_OP_RRCX, "RRCX"}, {MSP430_OP_RRUX, "RRUX"}, {MSP430_OP_SWPBX, "SWPBX"}, {MSP430_OP_RRAX, "RRAX"}, {MSP430_OP_SXTX, "SXTX"}, {MSP430_OP_PUSHX, "PUSHX"}, /* MSP430X group 13xx */ {MSP430_OP_CALLA, "CALLA"}, /* MSP430X group 14xx */ {MSP430_OP_PUSHM, "PUSHM"}, {MSP430_OP_POPM, "POPM"}, /* MSP430X address instructions */ {MSP430_OP_MOVA, "MOVA"}, {MSP430_OP_CMPA, "CMPA"}, {MSP430_OP_SUBA, "SUBA"}, {MSP430_OP_ADDA, "ADDA"}, /* MSP430X group 00xx, non-address */ {MSP430_OP_RRCM, "RRCM"}, {MSP430_OP_RRAM, "RRAM"}, {MSP430_OP_RLAM, "RLAM"}, {MSP430_OP_RRUM, "RRUM"}, /* MSP430X emulated instructions */ {MSP430_OP_ADCX, "ADCX"}, {MSP430_OP_BRA, "BRA"}, {MSP430_OP_RETA, "RETA"}, {MSP430_OP_CLRX, "CLRX"}, {MSP430_OP_DADCX, "DADCX"}, {MSP430_OP_DECX, "DECX"}, {MSP430_OP_DECDA, "DECDA"}, {MSP430_OP_DECDX, "DECDX"}, {MSP430_OP_INCX, "INCX"}, {MSP430_OP_INCDA, "INCDA"}, {MSP430_OP_INVX, "INVX"}, {MSP430_OP_RLAX, "RLAX"}, {MSP430_OP_RLCX, "RLCX"}, {MSP430_OP_SECX, "SECX"}, {MSP430_OP_TSTA, "TSTA"}, {MSP430_OP_TSTX, "TSTX"}, {MSP430_OP_POPX, "POPX"}, {MSP430_OP_INCDX, "INCDX"} }; /* Return the mnemonic for an operation, if possible. */ const char *dis_opcode_name(msp430_op_t op) { int i; for (i = 0; i < ARRAY_LEN(opcode_names); i++) if (op == opcode_names[i].op) return opcode_names[i].mnemonic; return NULL; } int dis_opcode_from_name(const char *name) { int i; for (i = 0; i < ARRAY_LEN(opcode_names); i++) if (!strcasecmp(name, opcode_names[i].mnemonic)) return opcode_names[i].op; return -1; } static const char *const msp430_reg_names[] = { "PC", "SP", "SR", "R3", "R4", "R5", "R6", "R7", "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15" }; int dis_reg_from_name(const char *name) { int i; if (!strcasecmp(name, "pc")) return 0; if (!strcasecmp(name, "sp")) return 1; if (!strcasecmp(name, "sr")) return 2; if (toupper(*name) == 'R') name++; for (i = 0; name[i]; i++) if (!isdigit(name[i])) return -1; i = atoi(name); if (i < 0 || i > 15) return -1; return i; } const char *dis_reg_name(msp430_reg_t reg) { if (reg <= 15) return msp430_reg_names[reg]; return NULL; } mspdebug-0.25/util/dis.h000066400000000000000000000213241313531517500151610ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef DIS_H_ #include #include "util.h" /* Addressing modes. * * Addressing modes are not determined solely by the address mode bits * in an instruction. Rather, those bits specify one of four possible * modes (REGISTER, INDEXED, INDIRECT and INDIRECT_INC). Using some of * these modes in conjunction with special registers like PC or the * constant generator registers results in extra modes. For example, the * following code, written using INDIRECT_INC on PC: * * MOV @PC+, R5 * .word 0x5729 * * can also be written as an instruction using IMMEDIATE addressing: * * MOV #0x5729, R5 */ typedef enum { MSP430_AMODE_REGISTER = 0x0, MSP430_AMODE_INDEXED = 0x1, MSP430_AMODE_SYMBOLIC = 0x81, MSP430_AMODE_ABSOLUTE = 0x82, MSP430_AMODE_INDIRECT = 0x2, MSP430_AMODE_INDIRECT_INC = 0x3, MSP430_AMODE_IMMEDIATE = 0x83 } msp430_amode_t; /* MSP430 registers. * * These are divided into: * * PC/R0: program counter * SP/R1: stack pointer * SR/R2: status register/constant generator 1 * R3: constant generator 2 * R4-R15: general purpose registers */ typedef enum { MSP430_REG_PC = 0, MSP430_REG_SP = 1, MSP430_REG_SR = 2, MSP430_REG_R3 = 3, MSP430_REG_R4 = 4, MSP430_REG_R5 = 5, MSP430_REG_R6 = 6, MSP430_REG_R7 = 7, MSP430_REG_R8 = 8, MSP430_REG_R9 = 9, MSP430_REG_R10 = 10, MSP430_REG_R11 = 11, MSP430_REG_R12 = 12, MSP430_REG_R13 = 13, MSP430_REG_R14 = 14, MSP430_REG_R15 = 15, } msp430_reg_t; /* Status register bits. */ #define MSP430_SR_V 0x0100 #define MSP430_SR_SCG1 0x0080 #define MSP430_SR_SCG0 0x0040 #define MSP430_SR_OSCOFF 0x0020 #define MSP430_SR_CPUOFF 0x0010 #define MSP430_SR_GIE 0x0008 #define MSP430_SR_N 0x0004 #define MSP430_SR_Z 0x0002 #define MSP430_SR_C 0x0001 /* MSP430 instruction formats. * * NOARG is not an actual instruction format recognised by the CPU. * It is used only for emulated instructions. */ typedef enum { MSP430_ITYPE_NOARG, MSP430_ITYPE_JUMP, MSP430_ITYPE_DOUBLE, MSP430_ITYPE_SINGLE } msp430_itype_t; /* MSP430(X) data sizes. * * An address-word is a 20-bit value. When stored in memory, they are * stored as two 16-bit words in the following order: * * data[15:0], {12'b0, data[19:16]} */ typedef enum { MSP430_DSIZE_WORD = 0, MSP430_DSIZE_BYTE = 1, MSP430_DSIZE_UNKNOWN = 2, MSP430_DSIZE_AWORD = 3, } msp430_dsize_t; /* MSP430 operations. * * Some of these are emulated instructions. Emulated instructions are * alternate mnemonics for combinations of some real opcodes with * common operand values. For example, the following real instruction: * * MOV #0, R8 * * can be written as the following emulated instruction: * * CLR R8 */ typedef enum { /* Single operand */ MSP430_OP_RRC = 0x1000, MSP430_OP_SWPB = 0x1080, MSP430_OP_RRA = 0x1100, MSP430_OP_SXT = 0x1180, MSP430_OP_PUSH = 0x1200, MSP430_OP_CALL = 0x1280, MSP430_OP_RETI = 0x1300, /* Jump */ MSP430_OP_JNZ = 0x2000, MSP430_OP_JZ = 0x2400, MSP430_OP_JNC = 0x2800, MSP430_OP_JC = 0x2C00, MSP430_OP_JN = 0x3000, MSP430_OP_JGE = 0x3400, MSP430_OP_JL = 0x3800, MSP430_OP_JMP = 0x3C00, /* Double operand */ MSP430_OP_MOV = 0x4000, MSP430_OP_ADD = 0x5000, MSP430_OP_ADDC = 0x6000, MSP430_OP_SUBC = 0x7000, MSP430_OP_SUB = 0x8000, MSP430_OP_CMP = 0x9000, MSP430_OP_DADD = 0xA000, MSP430_OP_BIT = 0xB000, MSP430_OP_BIC = 0xC000, MSP430_OP_BIS = 0xD000, MSP430_OP_XOR = 0xE000, MSP430_OP_AND = 0xF000, /* Emulated instructions */ MSP430_OP_ADC = 0x10000, MSP430_OP_BR = 0x10001, MSP430_OP_CLR = 0x10002, MSP430_OP_CLRC = 0x10003, MSP430_OP_CLRN = 0x10004, MSP430_OP_CLRZ = 0x10005, MSP430_OP_DADC = 0x10006, MSP430_OP_DEC = 0x10007, MSP430_OP_DECD = 0x10008, MSP430_OP_DINT = 0x10009, MSP430_OP_EINT = 0x1000A, MSP430_OP_INC = 0x1000B, MSP430_OP_INCD = 0x1000C, MSP430_OP_INV = 0x1000D, MSP430_OP_NOP = 0x1000E, MSP430_OP_POP = 0x1000F, MSP430_OP_RET = 0x10010, MSP430_OP_RLA = 0x10011, MSP430_OP_RLC = 0x10012, MSP430_OP_SBC = 0x10013, MSP430_OP_SETC = 0x10014, MSP430_OP_SETN = 0x10015, MSP430_OP_SETZ = 0x10016, MSP430_OP_TST = 0x10017, /* MSP430X single operand (extension word) */ MSP430_OP_RRCX = 0x21000, MSP430_OP_RRUX = 0x21001, /* note: ZC = 1 */ MSP430_OP_SWPBX = 0x21080, MSP430_OP_RRAX = 0x21100, MSP430_OP_SXTX = 0x21180, MSP430_OP_PUSHX = 0x21200, /* MSP430X double operand (extension word) */ MSP430_OP_MOVX = 0x24000, MSP430_OP_ADDX = 0x25000, MSP430_OP_ADDCX = 0x26000, MSP430_OP_SUBCX = 0x27000, MSP430_OP_SUBX = 0x28000, MSP430_OP_CMPX = 0x29000, MSP430_OP_DADDX = 0x2A000, MSP430_OP_BITX = 0x2B000, MSP430_OP_BICX = 0x2C000, MSP430_OP_BISX = 0x2D000, MSP430_OP_XORX = 0x2E000, MSP430_OP_ANDX = 0x2F000, /* MSP430X group 13xx */ MSP430_OP_CALLA = 0x21300, /* MSP430X group 14xx */ MSP430_OP_PUSHM = 0x1400, MSP430_OP_POPM = 0x1600, /* MSP430X address instructions */ MSP430_OP_MOVA = 0x0000, MSP430_OP_CMPA = 0x0090, MSP430_OP_ADDA = 0x00A0, MSP430_OP_SUBA = 0x00B0, /* MSP430X group 00xx, non-address */ MSP430_OP_RRCM = 0x0040, MSP430_OP_RRAM = 0x0140, MSP430_OP_RLAM = 0x0240, MSP430_OP_RRUM = 0x0340, /* MSP430X emulated instructions */ MSP430_OP_ADCX = 0x40000, MSP430_OP_BRA = 0x40001, MSP430_OP_RETA = 0x40002, MSP430_OP_CLRX = 0x40003, MSP430_OP_DADCX = 0x40004, MSP430_OP_DECX = 0x40005, MSP430_OP_DECDA = 0x40006, MSP430_OP_DECDX = 0x40007, MSP430_OP_INCX = 0x40008, MSP430_OP_INCDA = 0x40009, MSP430_OP_INVX = 0x4000A, MSP430_OP_RLAX = 0x4000B, MSP430_OP_RLCX = 0x4000C, MSP430_OP_SECX = 0x4000D, MSP430_OP_TSTA = 0x4000E, MSP430_OP_TSTX = 0x4000F, MSP430_OP_POPX = 0x40010, MSP430_OP_INCDX = 0x40011, } msp430_op_t; /* This represents a decoded instruction. All decoded addresses are * absolute or register-indexed, depending on the addressing mode. * * For jump instructions, the target address is stored in dst_operand. */ struct msp430_instruction { address_t offset; int len; msp430_op_t op; msp430_itype_t itype; msp430_dsize_t dsize; msp430_amode_t src_mode; address_t src_addr; msp430_reg_t src_reg; msp430_amode_t dst_mode; address_t dst_addr; msp430_reg_t dst_reg; int rep_index; int rep_register; }; /* Decode a single instruction. * * Returns the number of bytes consumed, or -1 if an error occured. * * The caller needs to pass a pointer to the bytes to be decoded, the * virtual offset of those bytes, and the maximum number available. If * successful, the decoded instruction is written into the structure * pointed to by insn. */ int dis_decode(const uint8_t *code, address_t offset, address_t len, struct msp430_instruction *insn); /* Look up names for registers and opcodes */ int dis_opcode_from_name(const char *name); const char *dis_opcode_name(msp430_op_t op); int dis_reg_from_name(const char *name); const char *dis_reg_name(msp430_reg_t reg); #endif mspdebug-0.25/util/dynload.c000066400000000000000000000027701313531517500160330ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2011 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include "dynload.h" #include "util.h" #ifdef __Windows__ dynload_handle_t dynload_open(const char *filename) { return LoadLibrary(filename); } void dynload_close(dynload_handle_t hnd) { FreeLibrary(hnd); } void *dynload_sym(dynload_handle_t hnd, const char *name) { return GetProcAddress(hnd, name); } const char *dynload_error(void) { return last_error(); } #else /* __Windows__ */ #include dynload_handle_t dynload_open(const char *filename) { return dlopen(filename, RTLD_LAZY); } void dynload_close(dynload_handle_t hnd) { dlclose(hnd); } void *dynload_sym(dynload_handle_t hnd, const char *name) { return dlsym(hnd, name); } const char *dynload_error(void) { return dlerror(); } #endif mspdebug-0.25/util/dynload.h000066400000000000000000000023271313531517500160360ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2011 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef DYNLOAD_H_ #define DYNLOAD_H_ /* Portable dynamic loader interface. */ #ifdef __Windows__ #include typedef HMODULE dynload_handle_t; #else /* __Windows__ */ typedef void *dynload_handle_t; #endif /* __Windows__ */ dynload_handle_t dynload_open(const char *filename); void dynload_close(dynload_handle_t hnd); void *dynload_sym(dynload_handle_t hnd, const char *name); const char *dynload_error(void); #endif mspdebug-0.25/util/expr.c000066400000000000000000000142731313531517500153600ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include #include #include #include "expr.h" #include "stab.h" #include "util.h" #include "output.h" #include "opdb.h" #include "demangle.h" #include "device.h" #include "dis.h" /************************************************************************ * Address expression parsing. */ struct addr_exp_state { int last_operator; address_t data_stack[32]; int data_stack_size; int op_stack[32]; int op_stack_size; }; static int addr_exp_data(struct addr_exp_state *s, const char *text) { address_t value; if (!s->last_operator || s->last_operator == ')') { printc_err("syntax error at token %s\n", text); return -1; } /* Hex value */ if (*text == '0' && text[1] == 'x') { value = strtoul(text + 2, NULL, 16); } else if (*text == '0' && text[1] == 'd') { value = atoi(text + 2); } else if (*text == '@') { int reg = dis_reg_from_name(text + 1); if (reg < 0) { printc_err("invalid register: %s\n", text); return -1; } address_t regs[DEVICE_NUM_REGS]; if (device_getregs(regs) < 0) return -1; value = regs[reg]; } else if (stab_get(text, &value) < 0) { char *end; value = strtol(text, &end, opdb_get_numeric("iradix")); if (*end) { printc_err("can't parse token: %s\n", text); return -1; } } if (s->data_stack_size + 1 > ARRAY_LEN(s->data_stack)) { printc_err("data stack overflow at token %s\n", text); return -1; } s->data_stack[s->data_stack_size++] = value; s->last_operator = 0; return 0; } static int addr_exp_pop(struct addr_exp_state *s) { char op = s->op_stack[--s->op_stack_size]; address_t data1 = s->data_stack[--s->data_stack_size]; address_t data2 = 0; address_t result = 0; if (op != 'N') data2 = s->data_stack[--s->data_stack_size]; assert (s->op_stack_size >= 0); assert (s->data_stack_size >= 0); switch (op) { case '+': result = data2 + data1; break; case '-': result = data2 - data1; break; case '*': result = data2 * data1; break; case '/': if (!data1) goto divzero; result = data2 / data1; break; case '%': if (!data1) goto divzero; result = data2 % data1; break; case 'N': result = -data1; break; } s->data_stack[s->data_stack_size++] = result; return 0; divzero: printc_err("divide by zero\n"); return -1; } static int can_push(struct addr_exp_state *s, char op) { char top; if (!s->op_stack_size || op == '(') return 1; top = s->op_stack[s->op_stack_size - 1]; if (top == '(') return 1; switch (op) { case 'N': return 1; case '*': case '%': case '/': return top == '+' || top == '-'; default: break; } return 0; } static int addr_exp_op(struct addr_exp_state *s, char op) { if (op == '(') { if (!s->last_operator || s->last_operator == ')') goto syntax_error; } else if (op == '-') { if (s->last_operator && s->last_operator != ')') op = 'N'; } else { if (s->last_operator && s->last_operator != ')') goto syntax_error; } if (op == ')') { /* ) collapses the stack to the last matching ( */ while (s->op_stack_size && s->op_stack[s->op_stack_size - 1] != '(') if (addr_exp_pop(s) < 0) return -1; if (!s->op_stack_size) { printc_err("parenthesis mismatch: )\n"); return -1; } s->op_stack_size--; } else { while (!can_push(s, op)) if (addr_exp_pop(s) < 0) return -1; if (s->op_stack_size + 1 > ARRAY_LEN(s->op_stack)) { printc_err("operator stack overflow: %c\n", op); return -1; } s->op_stack[s->op_stack_size++] = op; } s->last_operator = op; return 0; syntax_error: printc_err("syntax error at operator %c\n", op); return -1; } static int addr_exp_finish(struct addr_exp_state *s, address_t *ret) { if (s->last_operator && s->last_operator != ')') { printc_err("syntax error at end of expression\n"); return -1; } while (s->op_stack_size) { if (s->op_stack[s->op_stack_size - 1] == '(') { printc_err("parenthesis mismatch: (\n"); return -1; } if (addr_exp_pop(s) < 0) return -1; } if (s->data_stack_size != 1) { printc_err("no data: stack size is %d\n", s->data_stack_size); return -1; } if (ret) *ret = s->data_stack[0]; return 0; } int expr_eval(const char *text, address_t *addr) { const char *text_save = text; char token_buf[MAX_SYMBOL_LENGTH]; int token_len = 0; struct addr_exp_state s = {0}; s.last_operator = '('; for (;;) { int cc; /* Figure out what class this character is */ if (*text == '+' || *text == '-' || *text == '*' || *text == '/' || *text == '%' || *text == '(' || *text == ')') cc = 1; else if (!*text || isspace(*text)) cc = 2; else if (isalnum(*text) || *text == '.' || *text == '_' || *text == '$' || *text == ':' || *text == '@') cc = 3; else { printc_err("illegal character in expression: %c\n", *text); return -1; } /* Accumulate and process token text */ if (cc == 3) { if (token_len + 1 < sizeof(token_buf)) token_buf[token_len++] = *text; } else if (token_len) { token_buf[token_len] = 0; token_len = 0; if (addr_exp_data(&s, token_buf) < 0) goto fail; } /* Process operators */ if (cc == 1) { if (addr_exp_op(&s, *text) < 0) goto fail; } if (!*text) break; text++; } if (addr_exp_finish(&s, addr) < 0) goto fail; return 0; fail: printc_err("bad address expression: %s\n", text_save); return -1; } mspdebug-0.25/util/expr.h000066400000000000000000000020541313531517500153570ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef EXPR_H_ #define EXPR_H_ #include #include "stab.h" /* Parse an address expression, storing the result in the integer * pointed to. Returns 0 if parsed successfully, -1 if not. */ int expr_eval(const char *text, address_t *value); #endif mspdebug-0.25/util/gdb_proto.c000066400000000000000000000104541313531517500163560ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2011 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include #include #include "sockets.h" #include "gdb_proto.h" #include "output.h" #include "util.h" void gdb_init(struct gdb_data *data, int sock) { data->sock = sock; data->error = 0; data->head = 0; data->tail = 0; data->outlen = 0; } void gdb_printf(struct gdb_data *data, const char *fmt, ...) { va_list ap; int len; va_start(ap, fmt); len = vsnprintf(data->outbuf + data->outlen, sizeof(data->outbuf) - data->outlen, fmt, ap); va_end(ap); data->outlen += len; } /* Returns -1 for error, 0 for timeout, >0 if data received. */ static int gdb_read(struct gdb_data *data, int timeout_ms) { int was_timeout; int len = sockets_recv(data->sock, data->xbuf, sizeof(data->xbuf), 0, timeout_ms, &was_timeout); if (was_timeout) return 0; if (len < 0) { data->error = 1; pr_error("gdb: recv"); return -1; } if (!len) { data->error = 1; printc("Connection closed\n"); return -1; } data->head = 0; data->tail = len; return len; } int gdb_peek(struct gdb_data *data, int timeout_ms) { if (data->head == data->tail) return gdb_read(data, timeout_ms); return data->head != data->tail; } int gdb_getc(struct gdb_data *data) { int c; /* If the buffer is empty, receive some more data */ if (data->head == data->tail && gdb_read(data, -1) <= 0) return -1; c = data->xbuf[data->head]; data->head++; return c; } static int gdb_flush(struct gdb_data *data) { if (sockets_send(data->sock, data->outbuf, data->outlen, 0) < 0) { data->error = 1; pr_error("gdb: flush"); return -1; } data->outlen = 0; return 0; } int gdb_flush_ack(struct gdb_data *data) { int c; #ifdef DEBUG_GDB printc("-> %s\n", data->outbuf); #endif data->outbuf[data->outlen] = 0; do { if (sockets_send(data->sock, data->outbuf, data->outlen, 0) < 0) { data->error = 1; pr_error("gdb: flush_ack"); return -1; } do { c = gdb_getc(data); if (c < 0) return -1; } while (c != '+' && c != '-'); } while (c != '+'); data->outlen = 0; return 0; } void gdb_packet_start(struct gdb_data *data) { gdb_printf(data, "$"); } void gdb_packet_end(struct gdb_data *data) { int i; int c = 0; for (i = 1; i < data->outlen; i++) c = (c + data->outbuf[i]) & 0xff; gdb_printf(data, "#%02x", c); } int gdb_send(struct gdb_data *data, const char *msg) { gdb_packet_start(data); gdb_printf(data, "%s", msg); gdb_packet_end(data); return gdb_flush_ack(data); } int gdb_read_packet(struct gdb_data *data, char *buf) { int c; int len = 0; int cksum_calc = 0; int cksum_recv = 0; /* Wait for packet start */ do { c = gdb_getc(data); if (c < 0) return -1; } while (c != '$'); /* Read packet payload */ while (len + 1 < GDB_BUF_SIZE) { c = gdb_getc(data); if (c < 0) return -1; if (c == '#') break; buf[len++] = c; cksum_calc = (cksum_calc + c) & 0xff; } buf[len] = 0; /* Read packet checksum */ c = gdb_getc(data); if (c < 0) return -1; cksum_recv = hexval(c); c = gdb_getc(data); if (c < 0) return -1; cksum_recv = (cksum_recv << 4) | hexval(c); #ifdef DEBUG_GDB printc("<- $%s#%02x\n", buf, cksum_recv); #endif if (cksum_recv != cksum_calc) { printc_err("gdb: bad checksum (calc = 0x%02x, " "recv = 0x%02x)\n", cksum_calc, cksum_recv); printc_err("gdb: packet data was: %s\n", buf); gdb_printf(data, "-"); if (gdb_flush(data) < 0) return -1; return 0; } /* Send acknowledgement */ gdb_printf(data, "+"); if (gdb_flush(data) < 0) return -1; return len; } mspdebug-0.25/util/gdb_proto.h000066400000000000000000000030541313531517500163610ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2011 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef GDB_PROTO_H_ #define GDB_PROTO_H_ #define GDB_MAX_XFER 8192 #define GDB_BUF_SIZE (GDB_MAX_XFER * 2 + 64) struct gdb_data { int sock; int error; char xbuf[1024]; int head; int tail; char outbuf[GDB_BUF_SIZE]; int outlen; }; void gdb_init(struct gdb_data *d, int sock); void gdb_printf(struct gdb_data *data, const char *fmt, ...); int gdb_send(struct gdb_data *data, const char *msg); void gdb_packet_start(struct gdb_data *data); void gdb_packet_end(struct gdb_data *data); int gdb_peek(struct gdb_data *data, int timeout_ms); int gdb_getc(struct gdb_data *data); int gdb_flush_ack(struct gdb_data *data); int gdb_read_packet(struct gdb_data *data, char *buf); #endif mspdebug-0.25/util/gpio.c000066400000000000000000000133571313531517500153420ustar00rootroot00000000000000/* * C Implementation: gpio * * Description: * * * Author: Paolo Zebelloni , (C) 2014 * * Copyright: See COPYING file that comes with this distribution * */ #include "gpio.h" #include "output.h" #ifdef __Windows__ /* Added for building on Windows * * Daniel Beer , 3 Mar 2015 */ int gpio_is_exported ( unsigned int gpio ) { printc_err("gpio: GPIO interface not supported on Windows\n"); return -1; } int gpio_export ( unsigned int gpio ) { printc_err("gpio: GPIO interface not supported on Windows\n"); return -1; } int gpio_unexport ( unsigned int gpio ) { printc_err("gpio: GPIO interface not supported on Windows\n"); return -1; } int gpio_set_dir ( unsigned int gpio, unsigned int out_flag ) { printc_err("gpio: GPIO interface not supported on Windows\n"); return -1; } int gpio_set_value ( unsigned int gpio, unsigned int value ) { printc_err("gpio: GPIO interface not supported on Windows\n"); return -1; } int gpio_set_value_fd (int fd, int value) { printc_err("gpio: GPIO interface not supported on Windows\n"); return -1; } int gpio_get_value ( unsigned int gpio ) { return 0; } int gpio_get_value_fd (int fd, unsigned int gpio) { return 0; } int gpio_open_fd (unsigned int gpio) { printc_err("gpio: GPIO interface not supported on Windows\n"); return -1; } #else #include #include #include #include #include #include #include #include #include #define SYSFS_GPIO_DIR "/sys/class/gpio" #define MAX_BUF 64 /** * @return 1 if the gpio is already exported, 0 otherwise, -1 on error */ int gpio_is_exported ( unsigned int gpio ) { char dir_name[100] = {}; snprintf(dir_name, sizeof(dir_name) - 1, SYSFS_GPIO_DIR "/gpio%d", gpio); struct stat s; int err = stat(dir_name, &s); if(-1 == err) { if(errno == ENOENT) { return 0; } else { return -1; } } else { if(S_ISDIR(s.st_mode)) { return 1; } else { return -1; } } return -1; } /** * Before a Linux application can configure and use a GPIO, the GPIO first has to be exported to user. * Each GPIO is not accessible from user space until the GPIO has been exported. * You can only export a GPIO that isn't owned by a Linux kernel driver * @param gpio GPIO number * @return 0 if OK, -1 if fails */ int gpio_export ( unsigned int gpio ) { int fd, len; char buf[MAX_BUF]; fd = open ( SYSFS_GPIO_DIR "/export", O_WRONLY ); if ( fd < 0 ) { pr_error ( "gpio/export" ); return -1; } len = snprintf ( buf, sizeof ( buf ), "%d", gpio ); write ( fd, buf, len ); close ( fd ); return 0; } /** * Complement of gpio_export(). * @param gpio GPIO number * @return 0 if OK, -1 if fails */ int gpio_unexport ( unsigned int gpio ) { int fd, len; char buf[MAX_BUF]; fd = open ( SYSFS_GPIO_DIR "/unexport", O_WRONLY ); if ( fd < 0 ) { pr_error ( "gpio/unexport" ); return -1; } len = snprintf ( buf, sizeof ( buf ), "%d", gpio ); write ( fd, buf, len ); close ( fd ); return 0; } /** * To avoid hardware issues where two devices are driving the same signal, GPIOs default to be configured as an input. * If you want to use the GPIO as an output, you need to change the configuration * @param gpio GPIO number * @param out_flag TRUE means OUT, FALSE means IN * @return 0 if OK, -1 if fails */ int gpio_set_dir ( unsigned int gpio, unsigned int out_flag ) { int fd; char buf[MAX_BUF]; snprintf ( buf, MAX_BUF, SYSFS_GPIO_DIR "/gpio%d/direction", gpio ); fd = open ( buf, O_WRONLY ); if ( fd < 0 ) { pr_error ( "gpio/direction" ); return -1; } if ( out_flag ) write ( fd, "out", 4 ); else write ( fd, "in", 3 ); close ( fd ); return 0; } /** * Set HI or LO state to GPIO (output) pin. * @param gpio GPIO number * @param value TRUE means HI, FALSE means LO * @return 0 if OK, -1 if fails */ int gpio_set_value ( unsigned int gpio, unsigned int value ) { int fd; char buf[MAX_BUF]; snprintf ( buf, MAX_BUF, SYSFS_GPIO_DIR "/gpio%d/value", gpio ); fd = open ( buf, O_WRONLY ); if ( fd < 0 ) { pr_error ( "gpio/set-value" ); return -1; } write ( fd, value ? "1" : "0", 2 ); close ( fd ); return 0; } /** * Read state of GPIO (input) pin. * @param gpio GPIO number * @return 0 if LO, 1 if HI, -1 if fails */ int gpio_get_value ( unsigned int gpio ) { int fd; char buf[MAX_BUF]; char ch; snprintf ( buf, MAX_BUF, SYSFS_GPIO_DIR "/gpio%d/value", gpio ); fd = open ( buf, O_RDONLY ); if ( fd < 0 ) { pr_error ( "gpio/get-value" ); return -1; } read ( fd, &ch, 1 ); close ( fd ); return ( ch != '0' ); } /** * Opens GPIO (input/output) pin file descriptor * @param gpio GPIO number * @return file descriptor, -1 if fails */ int gpio_open_fd ( unsigned int gpio ) { int fd; char buf[MAX_BUF]; snprintf ( buf, MAX_BUF, SYSFS_GPIO_DIR "/gpio%d/value", gpio ); fd = open ( buf, O_RDWR ); if ( fd < 0 ) { pr_error ( "gpio/get-value" ); return -1; } return fd; } /** * Sets GPIO (output) value with given file descriptor * @param file descriptor * @param gpio GPIO number * @return 0 if OK, -1 if fails */ int gpio_set_value_fd (int fd, int value) { ssize_t ret; char gpio_value = value + '0'; ret = write (fd, &gpio_value, 1); if (ret != 1) { printf("Error setting value gpio\n"); return -1; } return 0; } /** * Read state of GPIO (input) pin, with file descriptor * @param file descriptor * @param gpio GPIO number * @return 0 if LO, 1 if HI, -1 if fails */ int gpio_get_value_fd (int fd, unsigned int gpio) { ssize_t ret; char value; ret = pread (fd, &value, 1, 0); if (ret != 1) { printf("Error getting value of gpio %u\n", gpio); return -1; } return value == '1'; } #endif mspdebug-0.25/util/gpio.h000066400000000000000000000012171313531517500153370ustar00rootroot00000000000000// // C++ Interface: gpio // // Description: // // // Author: Paolo Zebelloni , (C) 2014 // // Copyright: See COPYING file that comes with this distribution // // #ifndef _GPIO_H #define _GPIO_H int gpio_is_exported ( unsigned int gpio ); int gpio_export ( unsigned int gpio ); int gpio_unexport ( unsigned int gpio ); int gpio_set_dir ( unsigned int gpio, unsigned int out_flag ); int gpio_set_value ( unsigned int gpio, unsigned int value ); int gpio_set_value_fd (int fd, int value); int gpio_get_value ( unsigned int gpio ); int gpio_get_value_fd (int fd, unsigned int gpio); int gpio_open_fd (unsigned int gpio); #endif mspdebug-0.25/util/list.c000066400000000000000000000023401313531517500153450ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include "list.h" void list_init(struct list_node *head) { head->next = head; head->prev = head; } void list_insert(struct list_node *item, struct list_node *after) { item->next = after; item->prev = after->prev; after->prev->next = item; after->prev = item; } void list_remove(struct list_node *item) { item->next->prev = item->prev; item->prev->next = item->next; item->prev = NULL; item->next = NULL; } mspdebug-0.25/util/list.h000066400000000000000000000033741313531517500153620ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef LIST_H_ #define LIST_H_ /* This is the list node definition. It's intended to be embedded within * another data structure. * * All lists are circular and doubly-linked. So, to iterate over the * members of a list, do something like this: * * struct list_node *n; * * for (n = list->next; n != list; n = n->next) { * ... * } * * An empty list must be created first with list_init(). This sets the * next and prev pointers to the list head itself. */ struct list_node { struct list_node *next; struct list_node *prev; }; /* Check to see if a list contains anything. */ #define LIST_EMPTY(h) ((h)->next == (h)) /* Create an empty list */ void list_init(struct list_node *head); /* Add an item to a list. The item will appear before the item * specified as after. */ void list_insert(struct list_node *item, struct list_node *after); /* Remove a node from its containing list. */ void list_remove(struct list_node *item); #endif mspdebug-0.25/util/opdb.c000066400000000000000000000114521313531517500153220ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include "opdb.h" #include "util.h" static const struct opdb_key keys[] = { { .name = "color", .type = OPDB_TYPE_BOOLEAN, .help = "Colorize debugging output.\n", .defval = { .boolean = 0 } }, { .name = "gdb_loop", .type = OPDB_TYPE_BOOLEAN, .help = "Automatically restart the GDB server after disconnection. If this\n" "option is set, then the GDB server keeps running until an error occurs,\n" "or the user interrupts with Ctrl+C.\n", .defval = { .boolean = 0 } }, { .name = "quiet", .type = OPDB_TYPE_BOOLEAN, .help = "Supress debugging output.\n", .defval = { .boolean = 0 } }, { .name = "iradix", .type = OPDB_TYPE_NUMERIC, .help = "Default input radix.\n", .defval = { .numeric = 10 } }, { .name = "fet_block_size", .type = OPDB_TYPE_NUMERIC, .help = "Size of buffer used for memory transfers to and from the FET device.\n" "Increasing this value will result in faster transfers, but may cause\n" "problems with some chips.\n", .defval = { .numeric = 64 } }, { .name = "gdbc_xfer_size", .type = OPDB_TYPE_NUMERIC, .help = "Maximum size of memory transfers for the GDB client. Increasing this\n" "value will result in faster transfers, but may cause problems with some\n" "servers.\n", .defval = { .numeric = 64 } }, { .name = "enable_locked_flash_access", .type = OPDB_TYPE_BOOLEAN, .help = "If set, some drivers will allow erase/program access to the info A\n" "segment. If in doubt, do not enable this.\n", .defval = { .boolean = 0 } }, { .name = "enable_bsl_access", .type = OPDB_TYPE_BOOLEAN, .help = "If set, some drivers will allow erase/program access to flash\n" "BSL memory. If in doubt, do not enable this.\n" }, { .name = "gdb_default_port", .type = OPDB_TYPE_NUMERIC, .help = "Default TCP port for GDB server, if no argument is given.\n", .defval = { .numeric = 2000 } }, { .name = "enable_fuse_blow", .type = OPDB_TYPE_BOOLEAN, .help = "If set, some drivers will allow the JTAG security fuse to be blown.\n" "\n" "\x1b[1mWARNING: this is an irreversible operation!\x1b[0m\n" "\n" "If in doubt, do not enable this option.\n" } }; static union opdb_value values[ARRAY_LEN(keys)]; static int opdb_find(const char *name) { int i; for (i = 0; i < ARRAY_LEN(keys); i++) { const struct opdb_key *key = &keys[i]; if (!strcasecmp(key->name, name)) return i; } return -1; } void opdb_reset(void) { int i; for (i = 0; i < ARRAY_LEN(keys); i++) { const struct opdb_key *key = &keys[i]; union opdb_value *value = &values[i]; memcpy(value, &key->defval, sizeof(*value)); } } int opdb_enum(opdb_enum_func_t func, void *user_data) { int i; for (i = 0; i < ARRAY_LEN(keys); i++) { const struct opdb_key *key = &keys[i]; const union opdb_value *value = &values[i]; if (func(user_data, key, value) < 0) return -1; } return 0; } int opdb_get(const char *name, struct opdb_key *key, union opdb_value *value) { int i; i = opdb_find(name); if (i < 0) return -1; if (key) memcpy(key, &keys[i], sizeof(*key)); if (value) memcpy(value, &values[i], sizeof(*value)); return 0; } int opdb_set(const char *name, const union opdb_value *value) { int i; union opdb_value *v; i = opdb_find(name); if (i < 0) return -1; v = &values[i]; memcpy(v, value, sizeof(values[i])); if (keys[i].type == OPDB_TYPE_STRING) v->string[sizeof(v->string) - 1] = 0; return 0; } const char *opdb_get_string(const char *name) { int idx = opdb_find(name); if (idx < 0) return ""; return values[idx].string; } int opdb_get_boolean(const char *name) { int idx = opdb_find(name); if (idx < 0) return 0; return values[idx].boolean; } address_t opdb_get_numeric(const char *name) { int idx = opdb_find(name); if (idx < 0) return 0; return values[idx].numeric; } fperm_t opdb_read_fperm(void) { fperm_t ret = 0; if (opdb_get_boolean("enable_locked_flash_access")) ret |= FPERM_LOCKED_FLASH; if (opdb_get_boolean("enable_bsl_access")) ret |= FPERM_BSL; return ret; } mspdebug-0.25/util/opdb.h000066400000000000000000000040111313531517500153200ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef OPDB_H_ #define OPDB_H_ #include "util.h" typedef enum { OPDB_TYPE_BOOLEAN, OPDB_TYPE_NUMERIC, OPDB_TYPE_STRING } opdb_type_t; union opdb_value { char string[128]; address_t numeric; int boolean; }; struct opdb_key { const char *name; const char *help; opdb_type_t type; union opdb_value defval; }; /* Reset all options to default values. This should be called on start-up * to initialize the database. */ void opdb_reset(void); /* Enumerate all option key/value pairs */ typedef int (*opdb_enum_func_t)(void *user_data, const struct opdb_key *key, const union opdb_value *value); int opdb_enum(opdb_enum_func_t func, void *user_data); /* Retrieve information about an option. Returns 0 if found, -1 otherwise. */ int opdb_get(const char *name, struct opdb_key *key, union opdb_value *value); int opdb_set(const char *name, const union opdb_value *value); /* Get wrappers */ const char *opdb_get_string(const char *name); int opdb_get_boolean(const char *name); address_t opdb_get_numeric(const char *name); /* Check flash unlock bits, as configured by the user */ typedef enum { FPERM_LOCKED_FLASH = 0x01, FPERM_BSL = 0x02 } fperm_t; fperm_t opdb_read_fperm(void); #endif mspdebug-0.25/util/output.c000066400000000000000000000144321313531517500157370ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include #ifdef __Windows__ #include #endif #include "opdb.h" #include "output.h" #include "util.h" static capture_func_t capture_func; static void *capture_data; static int is_embedded_mode; #define LINEBUF_SIZE 4096 struct linebuf { /* Line buffer */ char buf[LINEBUF_SIZE]; int len; /* Does the buffer contain a trailing incomplete ANSI code? */ int ansi_mode; }; /* Return the lower three bits of n, reversed */ static int rev_bits(int n) { const int a = (n & 1) << 2; const int b = (n & 2); const int c = (n & 4) >> 2; return a | b | c; } /* Take a Windows color code and an ANSI colour-change code component * and return the resulting Windows color code. */ static int ansi_apply(int old_state, int code) { /* 0: reset */ if (code == 0) return 7; /* 1: bold */ if (code == 1) return old_state | 0x8; /* 30-37: foreground colour */ if (code >= 30 && code <= 37) return (old_state & 0xf8) | rev_bits(code - 30); /* 40-47: background colour */ if (code >= 40 && code <= 47) return (old_state & 0x0f) | (rev_bits(code - 40) << 4); return old_state; } /* Parse an ANSI code and compute the next Windows console colour code. * Returns the number of bytes consumed. */ static int parse_ansi(const char *text, int *ansi_state) { int next_state = *ansi_state; int code = 0; int len = 0; /* Parse the ANSI code and see how long it is */ while (text[len]) { char c = text[len++]; if (isdigit(c)) { code = code * 10 + c - '0'; } else { next_state = ansi_apply(next_state, code); code = 0; } if (isalpha(c)) break; } *ansi_state = next_state; return len; } /* Parse printable characters, up to either the end of the line or the * next ANSI code. Returns the number of bytes consumed. */ static int parse_text(const char *text) { int len = 0; while (text[len] && text[len] != 0x1b) len++; return len; } /* Print an ANSI code, or change the console text colour. */ static void emit_ansi(const char *code, int len, int ansi_state, FILE *out) { #ifdef __Windows__ if (is_embedded_mode) { fwrite(code, 1, len, out); } else { fflush(out); SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), ansi_state); } #else fwrite(code, 1, len, out); #endif } /* Process and print a single line of text. The given line of text must * be nul-terminated with no line-ending characters. Embedded ANSI * sequences are handled appropriately. */ static void handle_line(const char *text, FILE *out, char sigil) { const int want_color = opdb_get_boolean("color"); char cap_buf[LINEBUF_SIZE]; int cap_len = 0; int ansi_state = 7; if (is_embedded_mode) { out = stdout; fputc(sigil, out); } while (*text) { int r; if (*text == 0x1b) { r = parse_ansi(text, &ansi_state); if (want_color) emit_ansi(text, r, ansi_state, out); } else { r = parse_text(text); memcpy(cap_buf + cap_len, text, r); cap_len += r; fwrite(text, 1, r, out); } text += r; } /* Reset colours if necessary */ if (want_color && (ansi_state != 7)) emit_ansi("\x1b[0m", 4, 7, out); fputc('\n', out); fflush(out); /* Invoke output capture callback */ cap_buf[cap_len] = 0; if (capture_func) capture_func(capture_data, cap_buf); } /* Push a chunk of text, possibly with embedded ANSI sequences, into a * buffer. The text is reassembled into lines, and each line is * processed/printed once completely assembled. * * The number of printable (non-ANSI, non-newline) characters in the * chunk of text is returned. The buffer keeps track of whether or not * we're currently within an ANSI code, so pushing code fragments works * correctly. */ static int write_text(struct linebuf *ob, const char *text, FILE *out, char sigil) { int count = 0; /* Separate the text into lines and count the number of * printing characters. */ while (*text) { if (*text == '\n') { ob->buf[ob->len] = 0; ob->len = 0; ob->ansi_mode = 0; handle_line(ob->buf, out, sigil); } else { if (*text == 0x1b) ob->ansi_mode = 1; if (ob->len + 1 < sizeof(ob->buf)) ob->buf[ob->len++] = *text; if (!ob->ansi_mode) count++; if (isalpha(*text)) ob->ansi_mode = 0; } text++; } return count; } static struct linebuf lb_normal; static struct linebuf lb_debug; static struct linebuf lb_error; static struct linebuf lb_shell; int printc(const char *fmt, ...) { char buf[4096]; va_list ap; va_start(ap, fmt); vsnprintf(buf, sizeof(buf), fmt, ap); va_end(ap); return write_text(&lb_normal, buf, stdout, ':'); } int printc_dbg(const char *fmt, ...) { char buf[4096]; va_list ap; if (opdb_get_boolean("quiet")) return 0; va_start(ap, fmt); vsnprintf(buf, sizeof(buf), fmt, ap); va_end(ap); return write_text(&lb_debug, buf, stdout, '-'); } int printc_err(const char *fmt, ...) { char buf[4096]; va_list ap; va_start(ap, fmt); vsnprintf(buf, sizeof(buf), fmt, ap); va_end(ap); return write_text(&lb_error, buf, stderr, '!'); } int printc_shell(const char *fmt, ...) { char buf[4096]; va_list ap; if (!is_embedded_mode) return 0; va_start(ap, fmt); vsnprintf(buf, sizeof(buf), fmt, ap); va_end(ap); return write_text(&lb_shell, buf, stdout, '\\'); } void output_set_embedded(int enable) { is_embedded_mode = enable; } void pr_error(const char *prefix) { printc_err("%s: %s\n", prefix, last_error()); } void capture_start(capture_func_t func, void *data) { capture_func = func; capture_data = data; } void capture_end(void) { capture_func = NULL; } mspdebug-0.25/util/output.h000066400000000000000000000042601313531517500157420ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef OUTPUT_H_ #define OUTPUT_H_ #include "vector.h" /* Print output. ANSI colour codes may be embedded, and these will be * stripped on output if colour output is disabled. * * Returns the number of characters printed (not including colour * codes). */ int printc(const char *fmt, ...) __attribute__((format (printf, 1, 2))); int printc_dbg(const char *fmt, ...) __attribute__((format (printf, 1, 2))); int printc_err(const char *fmt, ...) __attribute__((format (printf, 1, 2))); int printc_shell(const char *fmt, ...) __attribute__((format (printf, 1, 2))); void pr_error(const char *prefix); /* Enable embedded output mode. When enabled, all logical streams * are sent to stdout (not stderr), and prefixed with the following * sigils: * * : normal * ! error * - debug * \ shell * * Additionally, ANSI codes are used for colourized output on Windows * instead of changing the console text attributes. */ void output_set_embedded(int enable); /* Capture output. Capturing is started by calling capture_begin() with * a callback function. The callback is invoked for each line of output * printed to either stdout or stderr (output still goes to * stdout/stderr as well). * * Capture is ended by calling capture_end(). */ typedef void (*capture_func_t)(void *user_data, const char *text); void capture_start(capture_func_t, void *user_data); void capture_end(void); #endif mspdebug-0.25/util/output_util.c000066400000000000000000000173241313531517500167770ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include #include "dis.h" #include "output_util.h" #include "stab.h" #include "util.h" #include "demangle.h" static int format_addr(msp430_amode_t amode, address_t addr) { char name[MAX_SYMBOL_LENGTH]; const char *prefix = ""; switch (amode) { case MSP430_AMODE_REGISTER: case MSP430_AMODE_INDIRECT: case MSP430_AMODE_INDIRECT_INC: return 0; case MSP430_AMODE_IMMEDIATE: prefix = "#"; case MSP430_AMODE_INDEXED: break; case MSP430_AMODE_ABSOLUTE: prefix = "&"; break; case MSP430_AMODE_SYMBOLIC: break; } print_address(addr, name, sizeof(name), PRINT_ADDRESS_EXACT); return printc("%s\x1b[1m%s\x1b[0m", prefix, name); } static int format_reg(msp430_amode_t amode, msp430_reg_t reg) { const char *prefix = ""; const char *suffix = ""; const char *name; switch (amode) { case MSP430_AMODE_REGISTER: break; case MSP430_AMODE_INDEXED: prefix = "("; suffix = ")"; break; case MSP430_AMODE_IMMEDIATE: case MSP430_AMODE_SYMBOLIC: case MSP430_AMODE_ABSOLUTE: return 0; case MSP430_AMODE_INDIRECT_INC: suffix = "+"; case MSP430_AMODE_INDIRECT: prefix = "@"; break; } name = dis_reg_name(reg); if (!name) name = "???"; return printc("%s\x1b[33m%s\x1b[0m%s", prefix, name, suffix); } /* Given an operands addressing mode, value and associated register, * print the canonical representation of it to stdout. * * Returns the number of characters printed. */ static int format_operand(msp430_amode_t amode, address_t addr, msp430_reg_t reg) { int len = 0; len += format_addr(amode, addr); len += format_reg(amode, reg); return len; } /* Write assembly language for the instruction to this buffer */ static int dis_format(const struct msp430_instruction *insn) { int len = 0; const char *opname = dis_opcode_name(insn->op); const char *suffix = ""; if (!opname) opname = "???"; if (insn->dsize == MSP430_DSIZE_BYTE) suffix = ".B"; else if (insn->dsize == MSP430_DSIZE_AWORD) suffix = ".A"; else if (insn->dsize == MSP430_DSIZE_UNKNOWN) suffix = ".?"; /* Don't show the .A suffix for these instructions */ if (insn->op == MSP430_OP_MOVA || insn->op == MSP430_OP_CMPA || insn->op == MSP430_OP_SUBA || insn->op == MSP430_OP_ADDA || insn->op == MSP430_OP_BRA || insn->op == MSP430_OP_RETA) suffix = ""; len += printc("\x1b[36m%s%s\x1b[0m", opname, suffix); while (len < 8) len += printc(" "); /* Source operand */ if (insn->itype == MSP430_ITYPE_DOUBLE) { len += format_operand(insn->src_mode, insn->src_addr, insn->src_reg); len += printc(","); while (len < 15) len += printc(" "); len += printc(" "); } /* Destination operand */ if (insn->itype != MSP430_ITYPE_NOARG) len += format_operand(insn->dst_mode, insn->dst_addr, insn->dst_reg); /* Repetition count */ if (insn->rep_register) len += printc(" [repeat %s]", dis_reg_name(insn->rep_index)); else if (insn->rep_index) len += printc(" [repeat %d]", insn->rep_index + 1); return len; } void disassemble(address_t offset, const uint8_t *data, int length, powerbuf_t power) { int first_line = 1; unsigned long long ua_total = 0; int samples_total = 0; while (length) { struct msp430_instruction insn = {0}; int retval; int count; int i; address_t oboff; char obname[MAX_SYMBOL_LENGTH]; if (first_line || (!stab_nearest(offset, obname, sizeof(obname), &oboff) && !oboff)) { char buffer[MAX_SYMBOL_LENGTH]; print_address(offset, buffer, sizeof(buffer), 0); printc("\x1b[m%s\x1b[0m:\n", buffer); } first_line = 0; retval = dis_decode(data, offset, length, &insn); count = retval > 0 ? retval : 2; if (count > length) count = length; printc(" \x1b[36m%05x\x1b[0m:", offset); for (i = 0; i < count; i++) printc(" %02x", data[i]); while (i < 9) { printc(" "); i++; } if (retval >= 0) i = dis_format(&insn); if (power) { unsigned long long ua; int samples; while (i < 40) { printc(" "); i++; } samples = powerbuf_get_by_mab(power, offset, &ua); if (samples) { printc(" ;; %.01f uA", (double)ua / (double)samples); ua_total += ua; samples_total += samples; } } printc("\n"); offset += count; length -= count; data += count; } if (power && samples_total) printc(";; Total over this block: " "%.01f uAs in %.01f ms (%.01f uA avg)\n", (double)(ua_total * power->interval_us) / 1000000.0, (double)(samples_total * power->interval_us) / 1000.0, (double)ua_total / (double)samples_total); } void hexdump(address_t addr, const uint8_t *data, int data_len) { int offset = 0; while (offset < data_len) { int i, j; /* Address label */ printc(" \x1b[36m%05x:\x1b[0m", offset + addr); /* Hex portion */ for (i = 0; i < 16 && offset + i < data_len; i++) printc(" %02x", data[offset + i]); for (j = i; j < 16; j++) printc(" "); /* Printable characters */ printc(" \x1b[32m|"); for (j = 0; j < i; j++) { int c = data[offset + j]; printc("%c", (c >= 32 && c <= 126) ? c : '.'); } for (; j < 16; j++) printc(" "); printc("|\x1b[0m\n"); offset += i; } } void show_regs(const address_t *regs) { int i; for (i = 0; i < 4; i++) { int j; printc(" "); for (j = 0; j < 4; j++) { int k = j * 4 + i; printc("(\x1b[1m%3s:\x1b[0m %05x) ", dis_reg_name(k), regs[k]); } printc("\n"); } } int print_address(address_t addr, char *out, int max_len, print_address_flags_t f) { char name[MAX_SYMBOL_LENGTH]; address_t offset; if (!stab_nearest(addr, name, sizeof(name), &offset)) { char demangled[MAX_SYMBOL_LENGTH]; int len; if (offset) { if (f & PRINT_ADDRESS_EXACT) { snprintf(out, max_len, "0x%04x", addr); return 0; } len = snprintf(out, max_len, "%s+0x%x", name, offset); } else { len = snprintf(out, max_len, "%s", name); } if (demangle(name, demangled, sizeof(demangled)) > 0) snprintf(out + len, max_len - len, " (%s)", demangled); return 1; } snprintf(out, max_len, "0x%04x", addr); return 0; } /************************************************************************ * Name lists */ static int namelist_cmp(const void *a, const void *b) { return strcasecmp(*(const char **)a, *(const char **)b); } void namelist_print(struct vector *v) { int i; int max_len = 0; int rows, cols; qsort(v->ptr, v->size, v->elemsize, namelist_cmp); for (i = 0; i < v->size; i++) { const char *text = VECTOR_AT(*v, i, const char *); int len = strlen(text); if (len > max_len) max_len = len; } max_len += 2; cols = 72 / max_len; rows = (v->size + cols - 1) / cols; for (i = 0; i < rows; i++) { int j; printc(" "); for (j = 0; j < cols; j++) { int k = j * rows + i; const char *text; if (k >= v->size) break; text = VECTOR_AT(*v, k, const char *); printc("%s", text); for (k = strlen(text); k < max_len; k++) printc(" "); } printc("\n"); } } mspdebug-0.25/util/output_util.h000066400000000000000000000033161313531517500170000ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef OUTPUT_UTIL_H_ #define OUTPUT_UTIL_H_ #include "output.h" #include "util.h" #include "powerbuf.h" /* Print colorized disassembly on command processor standard output */ void disassemble(address_t addr, const uint8_t *buf, int len, powerbuf_t power); /* Print colorized hexdump on standard output */ void hexdump(address_t addr, const uint8_t *buf, int len); /* Colorized register dump */ void show_regs(const address_t *regs); /* Given an address, format it either as sym+0x0offset or just 0x0offset. * * Returns non-zero if the result is of the form sym+0x0offset. */ typedef enum { PRINT_ADDRESS_EXACT = 0x01 } print_address_flags_t; int print_address(address_t addr, char *buf, int max_len, print_address_flags_t f); /* Name lists. This function is used for printing multi-column sorted * lists of constant strings. Expected is a vector of const char *. */ void namelist_print(struct vector *v); #endif mspdebug-0.25/util/powerbuf.c000066400000000000000000000243041313531517500162270ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include "powerbuf.h" powerbuf_t powerbuf_new(unsigned int max_samples, unsigned int interval_us) { powerbuf_t pb = malloc(sizeof(*pb)); if (!pb) return NULL; if (max_samples <= 0) { free(pb); return NULL; } memset(pb, 0, sizeof(*pb)); pb->current_ua = malloc(sizeof(pb->current_ua[0]) * max_samples); if (!pb->current_ua) { free(pb); return NULL; } pb->mab = malloc(sizeof(pb->mab[0]) * max_samples); if (!pb->mab) { free(pb->current_ua); free(pb); return NULL; } pb->sorted = malloc(sizeof(pb->sorted[0]) * max_samples); if (!pb->sorted) { free(pb->current_ua); free(pb->mab); free(pb); return NULL; } pb->interval_us = interval_us; pb->max_samples = max_samples; pb->session_head = pb->session_tail = 0; pb->current_head = pb->current_tail = 0; return pb; } void powerbuf_free(powerbuf_t pb) { free(pb->current_ua); free(pb->mab); free(pb->sorted); free(pb); } void powerbuf_clear(powerbuf_t pb) { pb->session_head = pb->session_tail = 0; pb->current_head = pb->current_tail = 0; pb->sort_valid = 0; } static unsigned int session_length(powerbuf_t pb, unsigned int idx) { const unsigned int next_idx = (idx + 1) % POWERBUF_MAX_SESSIONS; unsigned int end_index = pb->current_head; /* If a session follows this one, the end index is the start * index of the following session. Otherwise, it's the end index * of the entire current/MAB buffer. */ if (next_idx != pb->session_head) end_index = pb->sessions[next_idx].start_index; /* Return (end-start) modulo max_samples */ return (end_index + pb->max_samples - pb->sessions[idx].start_index) % pb->max_samples; } static void pop_oldest_session(powerbuf_t pb) { unsigned int length = session_length(pb, pb->session_tail); /* Remove corresponding samples from the tail of the current/MAB * buffers. */ pb->current_tail = (pb->current_tail + length) % pb->max_samples; /* Remove the session from the session buffer. */ pb->session_tail = (pb->session_tail + 1) % POWERBUF_MAX_SESSIONS; } void powerbuf_begin_session(powerbuf_t pb, time_t when) { struct powerbuf_session *s; unsigned int next_head; /* If the most recent session is empty, remove it */ powerbuf_end_session(pb); /* If the session buffer is full, drop the oldest */ next_head = (pb->session_head + 1) % POWERBUF_MAX_SESSIONS; if (next_head == pb->session_tail) pop_oldest_session(pb); /* Copy data to the head */ s = &pb->sessions[pb->session_head]; s->wall_clock = when; s->start_index = pb->current_head; s->total_ua = 0; /* Advance the head pointer */ pb->session_head = next_head; } /* Return the index of the nth most recent session */ static unsigned int rev_index(powerbuf_t pb, unsigned int n) { return (pb->session_head + POWERBUF_MAX_SESSIONS - 1 - n) % POWERBUF_MAX_SESSIONS; } void powerbuf_end_session(powerbuf_t pb) { /* (head-1) modulo MAX_SESSIONS */ const unsigned int last_idx = rev_index(pb, 0); /* If there are no sessions, do nothing */ if (pb->session_head == pb->session_tail) return; /* If no samples were added since the session began, decrement * the head pointer. */ if (pb->sessions[last_idx].start_index == pb->current_head) pb->session_head = last_idx; } unsigned int powerbuf_num_sessions(powerbuf_t pb) { /* (head-tail) modulo MAX_SESSIONS */ return (pb->session_head + POWERBUF_MAX_SESSIONS - pb->session_tail) % POWERBUF_MAX_SESSIONS; } const struct powerbuf_session *powerbuf_session_info(powerbuf_t pb, unsigned int rev_idx, unsigned int *length) { /* (head-1-rev_idx) modulo MAX_SESSIONS */ const unsigned int idx_map = rev_index(pb, rev_idx); if (length) *length = session_length(pb, idx_map); return &pb->sessions[idx_map]; } static void ensure_room(powerbuf_t pb, unsigned int required) { unsigned int room = (pb->current_tail + pb->max_samples - pb->current_head - 1) % pb->max_samples; /* Drop old sessions if they're smaller than what we need to * reclaim. */ while (room < required && powerbuf_num_sessions(pb) > 1) { const unsigned int len = session_length(pb, pb->session_tail); if (room + len > required) break; pop_oldest_session(pb); room += len; } /* If we still lack space, it must be because the oldest session * is larger than what we still need to reclaim (we'll never be * asked to reclaim more than the buffer can hold). * * We also know at this point that (required-room) is <= the * length of the oldest session. */ while (room < required) { struct powerbuf_session *old = &pb->sessions[pb->session_tail]; unsigned int cont_len = pb->max_samples - old->start_index; int i; if (cont_len + room > required) cont_len = required - room; /* Un-integrate current */ for (i = 0; i < cont_len; i++) old->total_ua -= pb->current_ua[old->start_index + i]; /* Advance the start index and buffer tail */ old->start_index = (old->start_index + cont_len) % pb->max_samples; pb->current_tail = (pb->current_tail + cont_len) % pb->max_samples; room += cont_len; } } void powerbuf_add_samples(powerbuf_t pb, unsigned int count, const unsigned int *current_ua, const address_t *mab) { struct powerbuf_session *cur = &pb->sessions[rev_index(pb, 0)]; int i; /* If no session is active, do nothing */ if (pb->session_head == pb->session_tail) return; /* Make sure that we can't overflow the buffer in a single * chunk. */ if (count > pb->max_samples - 1) { int extra = pb->max_samples - 1 - count; current_ua += extra; mab += extra; count -= extra; } /* Push old samples/sessions out of the buffer if we need to. */ ensure_room(pb, count); /* Add current integral to the session's running count */ for (i = 0; i < count; i++) cur->total_ua += current_ua[i]; /* Add samples in contiguous chunks */ while (count) { unsigned int cont_len = pb->max_samples - pb->current_head; /* Don't copy more than we have */ if (cont_len > count) cont_len = count; /* Copy samples */ memcpy(pb->current_ua + pb->current_head, current_ua, sizeof(pb->current_ua[0]) * cont_len); memcpy(pb->mab + pb->current_head, mab, sizeof(pb->mab[0]) * cont_len); pb->current_head = (pb->current_head + cont_len) % pb->max_samples; /* Advance source pointers and count */ current_ua += cont_len; mab += cont_len; count -= cont_len; } pb->sort_valid = 0; } address_t powerbuf_last_mab(powerbuf_t pb) { const struct powerbuf_session *s = &pb->sessions[rev_index(pb, 0)]; const unsigned int last = (pb->current_head + pb->max_samples - 1) % pb->max_samples; if (s->start_index == pb->current_head) return 0; return pb->mab[last]; } static void sift_down(powerbuf_t pb, int start, int end) { int root = start; while (root * 2 + 1 <= end) { int left_child = root * 2 + 1; int biggest = root; unsigned int temp; /* Find the largest of * (root, left child, right child) */ if (pb->mab[pb->sorted[biggest]] < pb->mab[pb->sorted[left_child]]) biggest = left_child; if (left_child + 1 <= end && (pb->mab[pb->sorted[biggest]] < pb->mab[pb->sorted[left_child + 1]])) biggest = left_child + 1; /* If no changes are needed, the heap property is ok and * we can stop. */ if (biggest == root) break; /* Swap the root with its largest child */ temp = pb->sorted[biggest]; pb->sorted[biggest] = pb->sorted[root]; pb->sorted[root] = temp; /* Continue to push down the old root (now a child) */ root = biggest; } } static void heapify(powerbuf_t pb, int num_samples) { int start = (num_samples - 2) / 2; while (start >= 0) { sift_down(pb, start, num_samples - 1); start--; } } static void heap_extract(powerbuf_t pb, int num_samples) { int end = num_samples - 1; while (end > 0) { unsigned int temp; /* Swap the top of the heap with the end of the array, * and shrink the heap. */ temp = pb->sorted[0]; pb->sorted[0] = pb->sorted[end]; pb->sorted[end] = temp; end--; /* Fix up the heap (push down the new root) */ sift_down(pb, 0, end); } } void powerbuf_sort(powerbuf_t pb) { const unsigned int num_samples = (pb->current_head + pb->max_samples - pb->current_tail) % pb->max_samples; unsigned int i; if (pb->sort_valid) return; /* Prepare an index list */ for (i = 0; i < num_samples; i++) pb->sorted[i] = (pb->current_tail + i) % pb->max_samples; if (num_samples < 2) { pb->sort_valid = 1; return; } heapify(pb, num_samples); heap_extract(pb, num_samples); pb->sort_valid = 1; } /* Find the index within the sorted index of the first sample with an * MAB >= the given mab parameter. */ static int find_mab_ge(powerbuf_t pb, address_t mab) { const int num_samples = (pb->current_head + pb->max_samples - pb->current_tail) % pb->max_samples; int low = 0; int high = num_samples - 1; while (low <= high) { int mid = (low + high) / 2; if (pb->mab[pb->sorted[mid]] < mab) low = mid + 1; else if ((mid <= 0) || (pb->mab[pb->sorted[mid - 1]] < mab)) return mid; else high = mid - 1; } return -1; } int powerbuf_get_by_mab(powerbuf_t pb, address_t mab, unsigned long long *sum_ua) { const unsigned int num_samples = (pb->current_head + pb->max_samples - pb->current_tail) % pb->max_samples; int i; int count = 0; if (!pb->sort_valid) powerbuf_sort(pb); i = find_mab_ge(pb, mab); if (i < 0) return 0; *sum_ua = 0; while ((i < num_samples) && (pb->mab[pb->sorted[i]] == mab)) { *sum_ua += pb->current_ua[pb->sorted[i]]; count++; i++; } return count; } mspdebug-0.25/util/powerbuf.h000066400000000000000000000115131313531517500162320ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef POWERBUF_H_ #define POWERBUF_H_ /* This header file describes a data structure for recording power * profiling data. * * Power profile data consists of zero or more discontiguous "sessions". * Within each session is a sequence of evenly spaced current samples * and the corresponding MAB values. */ #include #include "util.h" /* Per-session information header. */ struct powerbuf_session { /* Time that this session started. */ time_t wall_clock; /* Index of first sample in sample buffer corresponding to this * session. */ unsigned int start_index; /* Integral of current consumed over this session. */ unsigned long long total_ua; }; #define POWERBUF_MAX_SESSIONS 8 #define POWERBUF_DEFAULT_SAMPLES 131072 /* Power buffer data structure. The power buffer contains three circular * buffers, two of which are dynamically allocated. Helper functions are * provided for managing access. */ struct powerbuf { /* These parameters are set at the time of construction and * shouldn't be modified. */ unsigned int interval_us; unsigned int max_samples; /* Session circular buffer. New sessions are created by * overwriting the head and advancing it. Old sessions drop out * the end of the buffer. */ struct powerbuf_session sessions[POWERBUF_MAX_SESSIONS]; unsigned int session_head; unsigned int session_tail; /* Sample circular buffer. A single head/tail pair indicates the * extent of both the current and MAB samples, since they are * synchronous with respect to one another. * * Adding samples to the buffer causes old samples to fall out * the tail end. If enough samples are pushed, old sessions will * also drop out above. */ unsigned int *current_ua; address_t *mab; unsigned int current_head; unsigned int current_tail; /* Index by MAB. This is a flat array which points to indices * within current_ua/mab. The indices are sorted in order of * increasing MAB. * * Note that this array is invalidated by any modification to * the sample buffers. You need to call powerbuf_sort() before * accessing it. */ int sort_valid; unsigned int *sorted; }; typedef struct powerbuf *powerbuf_t; /* Allocate/destroy a power buffer. The number of samples is fixed and * can't change over the lifetime of the buffer. */ powerbuf_t powerbuf_new(unsigned int max_samples, unsigned int interval_us); void powerbuf_free(powerbuf_t pb); /* Clear all sessions and samples from the buffer. */ void powerbuf_clear(powerbuf_t pb); /* Begin a new session. This may cause an old session to drop out the * end of the buffer. If the current session is empty, it will be * overwritten. * * powerbuf_end_session() simply discards any empty session previously * created by powerbuf_begin_session(). */ void powerbuf_begin_session(powerbuf_t pb, time_t when); void powerbuf_end_session(powerbuf_t pb); /* This interface provides a convenient way of accessing the session * circular buffer. Rather than using direct indices, we present an * interface that mimics a flat array. Indices (rev_idx) start at 0, * with 0 being the index of the most recent session. */ unsigned int powerbuf_num_sessions(powerbuf_t pb); const struct powerbuf_session *powerbuf_session_info(powerbuf_t pb, unsigned int rev_idx, unsigned int *length); /* Push samples into the buffer. The number of elements in both the * current_ua and mab arrays is given by the parameter "count". */ void powerbuf_add_samples(powerbuf_t pb, unsigned int count, const unsigned int *current_ua, const address_t *mab); /* Retrieve the last known MAB for this session, or 0 if none exists. */ address_t powerbuf_last_mab(powerbuf_t pb); /* Prepare the sorted MAB index. */ void powerbuf_sort(powerbuf_t pb); /* Obtain charge consumption data by MAB over all sessions. This * automatically calls powerbuf_sort() if necessary. * * Returns the number of samples found on success. The sum of all * current samples is written to the sum_ua argument. */ int powerbuf_get_by_mab(powerbuf_t pb, address_t mab, unsigned long long *sum_ua); #endif mspdebug-0.25/util/prog.c000066400000000000000000000057071313531517500153530ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include "device.h" #include "prog.h" #include "output.h" void prog_init(struct prog_data *prog, int flags) { memset(prog, 0, sizeof(*prog)); prog->flags = flags; } int prog_flush(struct prog_data *prog) { if (!prog->len) return 0; if (!prog->have_erased && (prog->flags & PROG_WANT_ERASE)) { printc("Erasing...\n"); if (device_erase(DEVICE_ERASE_MAIN, 0) < 0) return -1; printc("Programming...\n"); prog->have_erased = 1; } printc_dbg("%s %4d bytes at %04x", (prog->flags & PROG_VERIFY) ? "Verifying" : "Writing", prog->len, prog->addr); if (prog->section[0]) printc_dbg(" [section: %s]", prog->section); printc_dbg("...\n"); if (prog->flags & PROG_VERIFY) { uint8_t cmp_buf[PROG_BUFSIZE]; int i; if (device_readmem(prog->addr, cmp_buf, prog->len) < 0) return -1; for (i = 0; i < prog->len; i++) if (cmp_buf[i] != prog->buf[i]) { printc("\x1b[1mERROR:\x1b[0m " "mismatch at %04x (read %02x, " "expected %02x)\n", prog->addr + i, cmp_buf[i], prog->buf[i]); return -1; } } else { if (device_writemem(prog->addr, prog->buf, prog->len) < 0) return -1; } prog->total_written += prog->len; prog->addr += prog->len; prog->len = 0; return 0; } int prog_feed(struct prog_data *prog, const struct binfile_chunk *ch) { const char *section = ch->name ? ch->name : ""; const uint8_t *data = ch->data; int len = ch->len; /* Flush if this chunk is discontiguous, or in a different * section. */ if (prog->len && ((prog->addr + prog->len != ch->addr) || strcmp(prog->section, section))) { if (prog_flush(prog) < 0) return -1; } if (!prog->len) { prog->addr = ch->addr; strncpy(prog->section, section, sizeof(prog->section)); prog->section[sizeof(prog->section) - 1] = 0; } /* Add the buffer in piece by piece, flushing when it gets * full. */ while (len) { int count = sizeof(prog->buf) - prog->len; if (count > len) count = len; if (!count) { if (prog_flush(prog) < 0) return -1; } else { memcpy(prog->buf + prog->len, data, count); prog->len += count; data += count; len -= count; } } return 0; } mspdebug-0.25/util/prog.h000066400000000000000000000024431313531517500153520ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef PROG_H_ #define PROG_H_ #include "binfile.h" #define PROG_BUFSIZE 4096 struct prog_data { char section[64]; uint8_t buf[PROG_BUFSIZE]; address_t addr; int len; int flags; int have_erased; address_t total_written; }; #define PROG_WANT_ERASE 0x01 #define PROG_VERIFY 0x02 void prog_init(struct prog_data *data, int flags); int prog_feed(struct prog_data *data, const struct binfile_chunk *ch); int prog_flush(struct prog_data *data); #endif mspdebug-0.25/util/sockets.c000066400000000000000000000100251313531517500160440ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef __Windows__ #include #endif #include #include #include #include "sockets.h" #include "util.h" #include "ctrlc.h" #ifdef __Windows__ #include #endif #ifdef __Windows__ static DWORD error_save = 0; static void sockets_begin(SOCKET s, DWORD event) { u_long mode = 1; ioctlsocket(s, FIONBIO, &mode); WSAEventSelect(s, ctrlc_win32_event(), event); /* We explicitly check for Ctrl+C after resetting the event in * sockets_wait(). */ ResetEvent(ctrlc_win32_event()); } static int sockets_wait(DWORD timeout) { DWORD r; error_save = WSAGetLastError(); if (ctrlc_check()) error_save = ERROR_OPERATION_ABORTED; if (error_save != WSAEWOULDBLOCK) return -1; r = WaitForSingleObject(ctrlc_win32_event(), timeout); if (r == WAIT_TIMEOUT) { error_save = WAIT_TIMEOUT; return -1; } return 0; } static void sockets_end(SOCKET s) { u_long mode = 0; ioctlsocket(s, FIONBIO, &mode); WSAEventSelect(s, ctrlc_win32_event(), 0); WSASetLastError(error_save); } SOCKET sockets_accept(SOCKET s, struct sockaddr *addr, socklen_t *addrlen) { SOCKET client = INVALID_SOCKET; sockets_begin(s, FD_ACCEPT); do { client = WSAAccept(s, addr, addrlen, NULL, 0); } while (SOCKET_ISERR(client) && !sockets_wait(INFINITE)); sockets_end(s); return client; } int sockets_connect(SOCKET s, const struct sockaddr *addr, socklen_t addrlen) { int ret = -1; sockets_begin(s, FD_CONNECT); connect(s, addr, addrlen); do { WSANETWORKEVENTS evts; WSAEnumNetworkEvents(s, NULL, &evts); if (evts.lNetworkEvents & FD_CONNECT) { error_save = evts.iErrorCode[FD_CONNECT_BIT]; if (!error_save) ret = 0; break; } } while (!sockets_wait(INFINITE)); sockets_end(s); return ret; } ssize_t sockets_send(SOCKET s, const void *buf, size_t len, int flags) { int ret = -1; sockets_begin(s, FD_WRITE | FD_CLOSE); do { ret = send(s, buf, len, flags); } while (ret < 0 && !sockets_wait(INFINITE)); sockets_end(s); return ret; } ssize_t sockets_recv(SOCKET s, void *buf, size_t len, int flags, int timeout_ms, int *was_timeout) { int ret = -1; DWORD to_arg = (timeout_ms >= 0) ? timeout_ms : INFINITE; sockets_begin(s, FD_READ | FD_CLOSE); do { ret = recv(s, buf, len, flags); } while (ret < 0 && !sockets_wait(to_arg)); if (was_timeout) *was_timeout = (ret < 0 && (error_save == WAIT_TIMEOUT)); sockets_end(s); return ret; } #else /* __Windows__ */ SOCKET sockets_accept(SOCKET s, struct sockaddr *addr, socklen_t *addrlen) { return accept(s, addr, addrlen); } int sockets_connect(SOCKET s, const struct sockaddr *addr, socklen_t addrlen) { return connect(s, addr, addrlen); } ssize_t sockets_send(SOCKET s, const void *buf, size_t len, int flags) { return send(s, buf, len, flags); } ssize_t sockets_recv(SOCKET s, void *buf, size_t buf_len, int flags, int timeout_ms, int *was_timeout) { fd_set r; struct timeval to = { .tv_sec = timeout_ms / 1000, .tv_usec = timeout_ms % 1000 }; FD_ZERO(&r); FD_SET(s, &r); if (select(s + 1, &r, NULL, NULL, timeout_ms < 0 ? NULL : &to) < 0) return -1; if (was_timeout) *was_timeout = !FD_ISSET(s, &r); if (!FD_ISSET(s, &r)) { errno = ETIMEDOUT; return 0; } return recv(s, buf, buf_len, flags); } #endif mspdebug-0.25/util/sockets.h000066400000000000000000000031721313531517500160560ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef SOCKETS_H_ #define SOCKETS_H_ #ifdef __Windows__ #include #include typedef int socklen_t; #define SOCKET_ISERR(x) ((x) == INVALID_SOCKET) #else #include #include #include #include #include #include #define closesocket close typedef int SOCKET; #define SOCKET_ISERR(x) ((x) < 0) #endif /* These are versions of the blocking IO calls which can be interrupted * by the user pressing Ctrl+C. */ SOCKET sockets_accept(SOCKET s, struct sockaddr *addr, socklen_t *addrlen); int sockets_connect(SOCKET s, const struct sockaddr *addr, socklen_t addrlen); ssize_t sockets_send(SOCKET s, const void *buf, size_t len, int flags); ssize_t sockets_recv(SOCKET s, void *buf, size_t len, int flags, int timeout_ms, int *was_timeout); #endif mspdebug-0.25/util/sport.c000066400000000000000000000146541313531517500155540ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include #include #include "sport.h" #include "util.h" #include "output.h" #include "ctrlc.h" #ifdef __linux__ #include #endif #define TIMEOUT_S 30 #ifndef __Windows__ #include #ifndef B460800 #define B460800 460800 #endif #ifndef B500000 #define B500000 500000 #endif struct baud_rate { int rate; int code; }; static const struct baud_rate baud_rates[] = { {9600, B9600}, {115200, B115200}, {460800, B460800}, {500000, B500000} }; static int rate_to_code(int rate) { int i; for (i = 0; i < ARRAY_LEN(baud_rates); i++) if (baud_rates[i].rate == rate) return baud_rates[i].code; return -1; } #if defined(__linux__) static int set_nonstandard_rate(int fd, struct termios *attr, int rate) { struct serial_struct ss; /* We need to set the rate code to B38400 on Linux for * the non-standard rate to take effect. */ cfsetispeed(attr, B38400); cfsetospeed(attr, B38400); if (ioctl(fd, TIOCGSERIAL, &ss) < 0) { pr_error("sport: TIOCGSERIAL failed"); return -1; } ss.custom_divisor = ss.baud_base / rate; ss.flags = ASYNC_SPD_CUST; if (ioctl(fd, TIOCSSERIAL, &ss) < 0) { pr_error("sport: TIOCSSERIAL failed"); return -1; } return 0; } #elif defined(__OpenBSD__) || defined(__FreeBSD__) || \ defined(__NetBSD__) || defined(__DragonFly__) static int set_nonstandard_rate(int fd, struct termios *attr, int rate) { cfsetispeed(attr, rate); cfsetospeed(attr, rate); return 0; } #else static int set_nonstandard_rate(int fd, struct termios *attr, int rate) { printc_err("sport: Can't set non-standard baud rate %d on " "this platform\n", rate); return -1; } #endif sport_t sport_open(const char *device, int rate, int flags) { int fd = open(device, O_RDWR | O_NOCTTY); struct termios attr; int rate_code = rate_to_code(rate); if (fd < 0) return -1; tcgetattr(fd, &attr); #ifdef __sun__ attr.c_iflag &= ~(IMAXBEL | IGNBRK | BRKINT | PARMRK | ISTRIP | INLCR | IGNCR | ICRNL | IXON); attr.c_oflag &= ~OPOST; attr.c_lflag &= ~(ECHO | ECHONL | ICANON | ISIG | IEXTEN); attr.c_cflag &= ~(CSIZE | PARENB); attr.c_cflag |= CS8; #else cfmakeraw(&attr); #endif if (rate_code >= 0) { cfsetispeed(&attr, rate_code); cfsetospeed(&attr, rate_code); } else if (set_nonstandard_rate(fd, &attr, rate) < 0) { close(fd); return -1; } if (flags & SPORT_EVEN_PARITY) attr.c_cflag |= PARENB; if (tcsetattr(fd, TCSAFLUSH, &attr) < 0) { close(fd); return -1; } return fd; } void sport_close(sport_t s) { close(s); } int sport_flush(sport_t s) { return tcflush(s, TCIFLUSH); } int sport_set_modem(sport_t s, int bits) { return ioctl(s, TIOCMSET, &bits); } int sport_read(sport_t s, uint8_t *data, int len) { int r; do { struct timeval tv = { .tv_sec = TIMEOUT_S, .tv_usec = 0 }; fd_set set; FD_ZERO(&set); FD_SET(s, &set); r = select(s + 1, &set, NULL, NULL, &tv); if (r > 0) r = read(s, data, len); if (!r) errno = ETIMEDOUT; if (r <= 0) return -1; } while (r <= 0); return r; } int sport_write(sport_t s, const uint8_t *data, int len) { return write(s, data, len); } #else /* __Windows__ */ sport_t sport_open(const char *device, int rate, int flags) { HANDLE hs = CreateFile(device, GENERIC_READ | GENERIC_WRITE, 0, 0, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL | FILE_FLAG_OVERLAPPED, 0); DCB params = {0}; COMMTIMEOUTS timeouts = {0}; if (hs == INVALID_HANDLE_VALUE) return INVALID_HANDLE_VALUE; if (!GetCommState(hs, ¶ms)) { CloseHandle(hs); return INVALID_HANDLE_VALUE; } params.BaudRate = rate; params.ByteSize = 8; params.StopBits = ONESTOPBIT; params.Parity = (flags & SPORT_EVEN_PARITY) ? EVENPARITY : NOPARITY; if (!SetCommState(hs, ¶ms)) { CloseHandle(hs); return INVALID_HANDLE_VALUE; } timeouts.ReadIntervalTimeout = 50; if (!SetCommTimeouts(hs, &timeouts)) { CloseHandle(hs); return INVALID_HANDLE_VALUE; } return hs; } void sport_close(sport_t s) { CloseHandle(s); } int sport_flush(sport_t s) { if (!PurgeComm(s, PURGE_RXABORT | PURGE_RXCLEAR)) return -1; return 0; } int sport_set_modem(sport_t s, int bits) { if (!EscapeCommFunction(s, (bits & SPORT_MC_DTR) ? SETDTR : CLRDTR)) return -1; if (!EscapeCommFunction(s, (bits & SPORT_MC_RTS) ? SETRTS : CLRRTS)) return -1; return 0; } static int xfer_wait(sport_t s, LPOVERLAPPED ovl) { DWORD result = 0; ResetEvent(ctrlc_win32_event()); while (!GetOverlappedResult(s, ovl, &result, FALSE)) { DWORD r; if (GetLastError() != ERROR_IO_INCOMPLETE) return -1; if (ctrlc_check()) { CancelIo(s); SetLastError(ERROR_OPERATION_ABORTED); return -1; } r = WaitForSingleObject(ctrlc_win32_event(), TIMEOUT_S * 1000); if (r == WAIT_TIMEOUT) { CancelIo(s); SetLastError(WAIT_TIMEOUT); return -1; } } return result; } int sport_read(sport_t s, uint8_t *data, int len) { OVERLAPPED ovl = {0}; ovl.hEvent = ctrlc_win32_event(); ReadFile(s, (void *)data, len, NULL, &ovl); return xfer_wait(s, &ovl); } int sport_write(sport_t s, const uint8_t *data, int len) { OVERLAPPED ovl = {0}; ovl.hEvent = ctrlc_win32_event(); WriteFile(s, (void *)data, len, NULL, &ovl); return xfer_wait(s, &ovl); } #endif int sport_read_all(sport_t s, uint8_t *data, int len) { while (len) { int r = sport_read(s, data, len); if (r <= 0) return -1; data += r; len -= r; } return 0; } int sport_write_all(sport_t s, const uint8_t *data, int len) { while (len) { int r = sport_write(s, data, len); if (r <= 0) return -1; data += r; len -= r; } return 0; } mspdebug-0.25/util/sport.h000066400000000000000000000035271313531517500155560ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2011 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef SPORT_H_ #define SPORT_H_ #include #ifndef __Windows__ #include #include typedef int sport_t; #define SPORT_ISERR(x) ((x) < 0) #define SPORT_MC_DTR TIOCM_DTR #define SPORT_MC_RTS TIOCM_RTS #else /* __Windows__ */ #include typedef HANDLE sport_t; #define SPORT_ISERR(x) ((x) == INVALID_HANDLE_VALUE) #define SPORT_MC_DTR 0x01 #define SPORT_MC_RTS 0x02 #endif /* Various utility functions for IO */ #define SPORT_EVEN_PARITY 0x01 sport_t sport_open(const char *device, int rate, int flags); void sport_close(sport_t s); int sport_flush(sport_t s); int sport_set_modem(sport_t s, int bits); /* Read/write a serial port. These functions return the number of * bytes transferred, or -1 on error. */ int sport_read(sport_t s, uint8_t *data, int len); int sport_write(sport_t s, const uint8_t *data, int len); /* Same as above, but requires that all data be transferred. */ int sport_read_all(sport_t s, uint8_t *data, int len); int sport_write_all(sport_t s, const uint8_t *data, int len); #endif mspdebug-0.25/util/stab.c000066400000000000000000000122301313531517500153220ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include #include #include #include #include "btree.h" #include "stab.h" #include "util.h" #include "output.h" /************************************************************************ * B+Tree definitions */ struct sym_key { char name[MAX_SYMBOL_LENGTH]; }; static const struct sym_key sym_key_zero = { .name = {0} }; static int sym_key_compare(const void *left, const void *right) { return strcmp(((const struct sym_key *)left)->name, ((const struct sym_key *)right)->name); } static void sym_key_init(struct sym_key *key, const char *text) { int len = strlen(text); if (len >= sizeof(key->name)) len = sizeof(key->name) - 1; memcpy(key->name, text, len); key->name[len] = 0; } struct addr_key { address_t addr; char name[MAX_SYMBOL_LENGTH]; }; static const struct addr_key addr_key_zero = { .addr = 0, .name = {0} }; static int addr_key_compare(const void *left, const void *right) { const struct addr_key *kl = (const struct addr_key *)left; const struct addr_key *kr = (const struct addr_key *)right; if (kl->addr < kr->addr) return -1; if (kl->addr > kr->addr) return 1; return strcmp(kl->name, kr->name); } static void addr_key_init(struct addr_key *key, address_t addr, const char *text) { int len = strlen(text); if (len >= sizeof(key->name)) len = sizeof(key->name) - 1; key->addr = addr; memcpy(key->name, text, len); key->name[len] = 0; } static const struct btree_def sym_table_def = { .compare = sym_key_compare, .zero = &sym_key_zero, .branches = 32, .key_size = sizeof(struct sym_key), .data_size = sizeof(address_t) }; static const struct btree_def addr_table_def = { .compare = addr_key_compare, .zero = &addr_key_zero, .branches = 32, .key_size = sizeof(struct addr_key), .data_size = 0 }; /************************************************************************ * Symbol table methods */ static btree_t stab_sym; static btree_t stab_addr; void stab_clear(void) { btree_clear(stab_sym); btree_clear(stab_addr); } int stab_set(const char *name, int value) { struct sym_key skey; struct addr_key akey; address_t addr = value; address_t old_addr; sym_key_init(&skey, name); /* Look for an old address first, and delete the reverse mapping * if it's there. */ if (!btree_get(stab_sym, &skey, &old_addr)) { addr_key_init(&akey, old_addr, skey.name); btree_delete(stab_addr, &akey); } /* Put the new mapping into both tables */ addr_key_init(&akey, addr, name); if (btree_put(stab_addr, &akey, NULL) < 0 || btree_put(stab_sym, &skey, &addr) < 0) { printc_err("stab: can't set %s = 0x%04x\n", name, addr); return -1; } return 0; } int stab_nearest(address_t addr, char *ret_name, int max_len, address_t *ret_offset) { struct addr_key akey; int i; akey.addr = addr; for (i = 0; i < sizeof(akey.name); i++) akey.name[i] = 0xff; akey.name[sizeof(akey.name) - 1] = 0xff; if (!btree_select(stab_addr, &akey, BTREE_LE, &akey, NULL)) { strncpy(ret_name, akey.name, max_len); ret_name[max_len - 1] = 0; *ret_offset = addr - akey.addr; return 0; } return -1; } int stab_get(const char *name, address_t *value) { struct sym_key skey; address_t addr; sym_key_init(&skey, name); if (btree_get(stab_sym, &skey, &addr)) return -1; *value = addr; return 0; } int stab_del(const char *name) { struct sym_key skey; address_t value; struct addr_key akey; sym_key_init(&skey, name); if (btree_get(stab_sym, &skey, &value)) return -1; addr_key_init(&akey, value, name); btree_delete(stab_sym, &skey); btree_delete(stab_addr, &akey); return 0; } int stab_enum(stab_callback_t cb, void *user_data) { int ret; struct addr_key akey; ret = btree_select(stab_addr, NULL, BTREE_FIRST, &akey, NULL); while (!ret) { if (cb(user_data, akey.name, akey.addr) < 0) return -1; ret = btree_select(stab_addr, NULL, BTREE_NEXT, &akey, NULL); } return 0; } int stab_init(void) { stab_sym = btree_alloc(&sym_table_def); if (!stab_sym) { printc_err("stab: failed to allocate symbol table\n"); return -1; } stab_addr = btree_alloc(&addr_table_def); if (!stab_addr) { printc_err("stab: failed to allocate address table\n"); btree_free(stab_sym); return -1; } return 0; } void stab_exit(void) { btree_free(stab_sym); btree_free(stab_addr); } mspdebug-0.25/util/stab.h000066400000000000000000000036401313531517500153340ustar00rootroot00000000000000/* MSPDebug - debugging tool for the eZ430 * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef STAB_H_ #define STAB_H_ #include #include "util.h" #define MAX_SYMBOL_LENGTH 512 /* Create/destroy a symbol table. The constructor returns NULL if it * was unable to allocate memory for the table. */ int stab_init(void); void stab_exit(void); /* Reset the symbol table (delete all symbols) */ void stab_clear(void); /* Set a symbol in the table. Returns 0 on success, or -1 on error. */ int stab_set(const char *name, int value); /* Take an address and find the nearest symbol and offset (always * non-negative). * * Returns 0 if found, 1 otherwise. */ int stab_nearest(address_t addr, char *ret_name, int max_len, address_t *ret_offset); /* Retrieve the value of a symbol. Returns 0 on success or -1 if the symbol * doesn't exist. */ int stab_get(const char *name, address_t *value); /* Delete a symbol table entry. Returns 0 on success or -1 if the symbol * doesn't exist. */ int stab_del(const char *name); /* Enumerate all symbols in the table */ typedef int (*stab_callback_t)(void *user_data, const char *name, address_t value); int stab_enum(stab_callback_t cb, void *user_data); #endif mspdebug-0.25/util/thread.h000066400000000000000000000076341313531517500156610ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2012 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef THREAD_H_ #define THREAD_H_ /* Thread start routine signature for all OSes */ typedef void (*thread_func_t)(void *user_data); #ifdef __Windows__ #include /* Windows threads. Threads are identified by a HANDLE, which becomes * signalled when the thread exits. * * thread_create() returns 0 on success or -1 if an error occurs. */ typedef HANDLE thread_t; static inline int thread_create(thread_t *t, thread_func_t func, void *arg) { *t = CreateThread(NULL, 0, (LPTHREAD_START_ROUTINE)func, arg, 0, NULL); return (*t) ? 0 : -1; } static inline void thread_join(thread_t t) { WaitForSingleObject(t, INFINITE); } /* Windows mutexes. We use critical sections, because we don't need to * share between processes. * * None of these functions are expected to fail, although * InitializeCriticalSection may raise an exception on some versions of * Windows under low memory conditions. */ typedef CRITICAL_SECTION thread_lock_t; static inline void thread_lock_init(thread_lock_t *lock) { InitializeCriticalSection(lock); } static inline void thread_lock_destroy(thread_lock_t *lock) { DeleteCriticalSection(lock); } static inline void thread_lock_acquire(thread_lock_t *lock) { EnterCriticalSection(lock); } static inline void thread_lock_release(thread_lock_t *lock) { LeaveCriticalSection(lock); } /* Windows condition variables. These are simulated using kernel event * objects. Note that this implementation is correct _only_ for the * case of a single waiter. */ typedef HANDLE thread_cond_t; static inline void thread_cond_init(thread_cond_t *c) { *c = CreateEvent(0, TRUE, FALSE, NULL); } static inline void thread_cond_destroy(thread_cond_t *c) { CloseHandle(*c); } static inline void thread_cond_wait(thread_cond_t *c, thread_lock_t *m) { thread_lock_release(m); WaitForSingleObject(*c, INFINITE); thread_lock_acquire(m); ResetEvent(*c); } static inline void thread_cond_notify(thread_cond_t *c) { SetEvent(*c); } #else /* __Windows__ */ #include /* POSIX thread creation. */ typedef pthread_t thread_t; static inline int thread_create(thread_t *t, thread_func_t func, void *arg) { return pthread_create(t, NULL, (void *(*)(void *))func, arg); } static inline void thread_join(thread_t t) { pthread_join(t, NULL); } /* POSIX mutexes. */ typedef pthread_mutex_t thread_lock_t; static inline void thread_lock_init(thread_lock_t *lock) { pthread_mutex_init(lock, NULL); } static inline void thread_lock_destroy(thread_lock_t *lock) { pthread_mutex_destroy(lock); } static inline void thread_lock_acquire(thread_lock_t *lock) { pthread_mutex_lock(lock); } static inline void thread_lock_release(thread_lock_t *lock) { pthread_mutex_unlock(lock); } /* POSIX condition variables. */ typedef pthread_cond_t thread_cond_t; static inline void thread_cond_init(thread_cond_t *c) { pthread_cond_init(c, NULL); } static inline void thread_cond_destroy(thread_cond_t *c) { pthread_cond_destroy(c); } static inline void thread_cond_wait(thread_cond_t *c, thread_lock_t *m) { pthread_cond_wait(c, m); } static inline void thread_cond_notify(thread_cond_t *c) { pthread_cond_signal(c); } #endif #endif mspdebug-0.25/util/usbutil.c000066400000000000000000000102021313531517500160550ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009-2013 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include "usbutil.h" #include "util.h" #include "output.h" static const char *device_help(const struct usb_device *dev) { static const struct { int vendor; int product; const char *help; } info[] = { {0x0451, 0xf432, "eZ430-RF2500"}, {0x0451, 0xf430, "FET430UIF"}, {0x2047, 0x0010, "FET430UIF (V3 firmware)"}, {0x15ba, 0x0002, "Olimex MSP430-JTAG-TINY (v1)"}, {0x15ba, 0x0008, "Olimex MSP430-JTAG-ISO"}, {0x15ba, 0x0031, "Olimex MSP430-JTAG-TINY (v2)"}, {0x15ba, 0x0100, "Olimex MSP430-JTAG-ISO-MK2 (v2)"}, {0x2047, 0x0200, "USB bootstrap loader"} }; int i; for (i = 0; i < ARRAY_LEN(info); i++) if (dev->descriptor.idProduct == info[i].product && dev->descriptor.idVendor == info[i].vendor) return info[i].help; return ""; } static int read_serial(struct usb_device *dev, char *buf, int max_len) { struct usb_dev_handle *dh = usb_open(dev); if (!dh) return -1; if (usb_get_string_simple(dh, dev->descriptor.iSerialNumber, buf, max_len) < 0) { usb_close(dh); return -1; } usb_close(dh); return 0; } void usbutil_list(void) { const struct usb_bus *bus; for (bus = usb_get_busses(); bus; bus = bus->next) { struct usb_device *dev; int busnum = atoi(bus->dirname); printc("Devices on bus %03d:\n", busnum); for (dev = bus->devices; dev; dev = dev->next) { int devnum = atoi(dev->filename); char serial[128]; printc(" %03d:%03d %04x:%04x %s", busnum, devnum, dev->descriptor.idVendor, dev->descriptor.idProduct, device_help(dev)); if (!read_serial(dev, serial, sizeof(serial))) printc(" [serial: %s]\n", serial); else printc("\n"); } } } struct usb_device *usbutil_find_by_id(int vendor, int product, const char *requested_serial) { struct usb_bus *bus; for (bus = usb_get_busses(); bus; bus = bus->next) { struct usb_device *dev; for (dev = bus->devices; dev; dev = dev->next) { if (dev->descriptor.idVendor == vendor && dev->descriptor.idProduct == product) { char buf[128]; if (!requested_serial || (!read_serial(dev, buf, sizeof(buf)) && !strcasecmp(requested_serial, buf))) return dev; } } } if(requested_serial) printc_err("usbutil: unable to find device matching " "%04x:%04x with serial %s\n", vendor, product, requested_serial); else printc_err("usbutil: unable to find a device matching " "%04x:%04x\n", vendor, product); return NULL; } struct usb_device *usbutil_find_by_loc(const char *loc) { char buf[64]; char *bus_text; char *dev_text; int target_bus; int target_dev; struct usb_bus *bus; strncpy(buf, loc, sizeof(buf)); buf[sizeof(buf) - 1] = 0; bus_text = strtok(buf, ":\t\r\n"); dev_text = strtok(NULL, ":\t\r\n"); if (!(bus_text && dev_text)) { printc_err("usbutil: location must be specified as " ":\n"); return NULL; } target_bus = atoi(bus_text); target_dev = atoi(dev_text); for (bus = usb_get_busses(); bus; bus = bus->next) { struct usb_device *dev; int busnum = atoi(bus->dirname); if (busnum != target_bus) continue; for (dev = bus->devices; dev; dev = dev->next) { int devnum = atoi(dev->filename); if (devnum == target_dev) return dev; } } printc_err("usbutil: unable to find %03d:%03d\n", target_bus, target_dev); return NULL; } mspdebug-0.25/util/usbutil.h000066400000000000000000000024001313531517500160630ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef USBUTIL_H_ #define USBUTIL_H_ #ifndef __Windows__ #include #else #include #endif /* List all available USB devices. */ void usbutil_list(void); /* Search for the first device matching the given Vendor:Product */ struct usb_device *usbutil_find_by_id(int vendor, int product, const char *requested_serial); /* Search for a device using a bus:dev location string */ struct usb_device *usbutil_find_by_loc(const char *loc); #endif mspdebug-0.25/util/util.c000066400000000000000000000141171313531517500153540ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include #include #include #include #ifdef __Windows__ #include #endif #include "ctrlc.h" #include "util.h" #include "output.h" char *get_arg(char **text) { char *start; char *rewrite; char *end; int qstate = 0; int qval = 0; if (!text) return NULL; start = *text; while (*start && isspace(*start)) start++; if (!*start) return NULL; /* We've found the start of the argument. Parse it. */ end = start; rewrite = start; while (*end) { switch (qstate) { case 0: /* Bare */ if (isspace(*end)) goto out; else if (*end == '"') qstate = 1; else *(rewrite++) = *end; break; case 1: /* In quotes */ if (*end == '"') qstate = 0; else if (*end == '\\') qstate = 2; else *(rewrite++) = *end; break; case 2: /* Backslash */ if (*end == '\\') *(rewrite++) = '\\'; else if (*end == 'n') *(rewrite++) = '\n'; else if (*end == 'r') *(rewrite++) = '\r'; else if (*end == 't') *(rewrite++) = '\t'; else if (*end >= '0' && *end <= '3') { qstate = 30; qval = *end - '0'; } else if (*end == 'x') { qstate = 40; qval = 0; } else *(rewrite++) = *end; if (qstate == 2) qstate = 1; break; case 30: /* Octal */ case 31: if (*end >= '0' && *end <= '7') qval = (qval << 3) | (*end - '0'); if (qstate == 31) { *(rewrite++) = qval; qstate = 1; } else { qstate++; } break; case 40: /* Hex */ case 41: if (isdigit(*end)) qval = (qval << 4) | (*end - '0'); else if (isupper(*end)) qval = (qval << 4) | (*end - 'A' + 10); else if (islower(*end)) qval = (qval << 4) | (*end - 'a' + 10); if (qstate == 41) { *(rewrite++) = qval; qstate = 1; } else { qstate++; } break; } end++; } out: /* Leave the text pointer at the end of the next argument */ while (*end && isspace(*end)) end++; *rewrite = 0; *text = end; return start; } void debug_hexdump(const char *label, const uint8_t *data, int len) { int offset = 0; printc("%s [0x%x bytes]\n", label, len); while (offset < len) { int i; printc(" "); for (i = 0; i < 16 && offset + i < len; i++) printc("%02x ", data[offset + i]); printc("\n"); offset += i; } } int hexval(int c) { if (isdigit(c)) return c - '0'; if (isupper(c)) return c - 'A' + 10; if (islower(c)) return c - 'a' + 10; return 0; } #ifdef __Windows__ char *strsep(char **strp, const char *delim) { char *start = *strp; char *end = start; if (!start) return NULL; while (*end) { const char *d = delim; while (*d) { if (*d == *end) { *(end++) = 0; *strp = end; return start; } d++; } end++; } *strp = NULL; return start; } #endif #ifdef __Windows__ const char *last_error(void) { DWORD err = GetLastError(); static char msg_buf[128]; int len; FormatMessage(FORMAT_MESSAGE_FROM_SYSTEM, NULL, err, 0, msg_buf, sizeof(msg_buf), NULL); /* Trim trailing newline characters */ len = strlen(msg_buf); while (len > 0 && isspace(msg_buf[len - 1])) len--; msg_buf[len] = 0; return msg_buf; } #else const char *last_error(void) { return strerror(errno); } #endif /* Expand leading `~/' in path names. Caller must free the returned ptr */ char *expand_tilde(const char *path) { char *home, *expanded; size_t len; if (!path) return NULL; if (!*path) return strdup(""); expanded = NULL; if (*path == '~' && *(path + 1) == '/') { home = getenv("HOME"); if (home) { /* Trailing '\0' will fit in leading '~'s place */ len = strlen(home) + strlen(path); expanded = (char *)malloc(len); if (expanded) snprintf(expanded, len, "%s%s", home, path + 1); else printc_err("%s: malloc: %s\n", __FUNCTION__, last_error()); } else { printc_err("%s: getenv: %s\n", __FUNCTION__, last_error()); } } else { expanded = strdup(path); if (!expanded) printc_err("%s: malloc: %s\n", __FUNCTION__, last_error()); } /* Caller must free()! */ return expanded; } #ifdef __Windows__ int delay_s(unsigned int s) { Sleep(s * 1000); return 0; } int delay_ms(unsigned int s) { Sleep(s); return 0; } #else int delay_s(unsigned int s) { return delay_ms(1000 * s); } int delay_ms(unsigned int s) { struct timespec rq, rm; int ret; rm.tv_sec = s / 1000; rm.tv_nsec = (s % 1000) * 1000000; do { if (ctrlc_check()) { ret = -1; break; } rq.tv_sec = rm.tv_sec; rq.tv_nsec = rm.tv_nsec; ret = nanosleep(&rq, &rm); } while(ret == -1 && errno == EINTR); return ret; } #endif int base64_encode(const uint8_t *src, int len, char *dst, int max_len) { static const char basis[] = "ABCDEFGHIJKLMNOPQRSTUVWXYZ" "abcdefghijklmnopqrstuvwxyz0123456789+/"; int i = 0; int k = 0; while ((i < len) && (k + 4) < max_len) { int a = src[i++]; dst[k++] = basis[a >> 2]; if (i < len) { int b = src[i++]; dst[k++] = basis[((a & 3) << 4) | (b & 0xf0) >> 4]; if (i < len) { int c = src[i++]; dst[k++] = basis[((b & 0xf) << 2) | ((c & 0xc0) >> 6)]; dst[k++] = basis[c & 0x3f]; } else { dst[k++] = basis[(b & 0xf) << 2]; dst[k++] = '='; } } else { dst[k++] = basis[(a & 3) << 4]; dst[k++] = '='; dst[k++] = '='; } } dst[k] = 0; return i; } mspdebug-0.25/util/util.h000066400000000000000000000046161313531517500153640ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef UTIL_H_ #define UTIL_H_ #include #include #define ARRAY_LEN(a) (sizeof(a) / sizeof((a)[0])) #define LE_BYTE(b, x) ((int)((uint8_t *)(b))[x]) #define LE_WORD(b, x) ((LE_BYTE(b, x + 1) << 8) | LE_BYTE(b, x)) #define LE_LONG(b, x) ((LE_WORD(b, x + 2) << 16) | LE_WORD(b, x)) /* This type fits an MSP430X register value */ typedef uint32_t address_t; #define ADDRESS_NONE ((address_t)0xffffffff) /* Retrive a string describing the last system error */ const char *last_error(void); /* Retrieve the next word from a pointer to the rest of a command * argument buffer. Returns NULL if no more words. */ char *get_arg(char **text); /* Display hex output for debug purposes */ void debug_hexdump(const char *label, const uint8_t *data, int len); static inline int ishex(int c) { return isdigit(c) || (c >= 'A' && c <= 'F') || (c >= 'a' && c <= 'f'); } int hexval(int c); #ifdef __Windows__ char *strsep(char **strp, const char *delim); #endif /* Expand `~' in path names. Caller must free the returned ptr */ char *expand_tilde(const char *path); /* Sleep for a number of seconds (_s) or milliseconds (_ms) */ int delay_s(unsigned int s); int delay_ms(unsigned int s); /* Base64 encode a block without breaking into lines. Returns the number * of source bytes encoded. The output is nul-terminated. */ static inline int base64_encoded_size(int decoded_size) { return ((decoded_size + 2) / 3) * 4; } int base64_encode(const uint8_t *src, int len, char *dst, int max_len); /* printf format for long long args */ #ifdef __MINGW32__ #define LLFMT "I64d" #else #define LLFMT "lld" #endif #endif mspdebug-0.25/util/vector.c000066400000000000000000000043311313531517500156760ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include "vector.h" void vector_init(struct vector *v, int elemsize) { memset(v, 0, sizeof(*v)); v->elemsize = elemsize; } void vector_destroy(struct vector *v) { if (v->ptr) free(v->ptr); memset(v, 0, sizeof(*v)); } int vector_realloc(struct vector *v, int capacity) { assert (capacity >= 0); if (capacity) { void *new_ptr = realloc(v->ptr, capacity * v->elemsize); if (!new_ptr) return -1; v->ptr = new_ptr; } else { free(v->ptr); v->ptr = NULL; } v->capacity = capacity; if (v->size > capacity) v->size = capacity; return 0; } static int size_for(struct vector *v, int needed) { int cap = needed; /* Find the smallest power of 2 which is greater than the * necessary capacity. */ while (cap & (cap - 1)) cap &= (cap - 1); if (cap < needed) cap <<= 1; /* Don't allocate fewer than 8 elements */ if (cap < 8) cap = 8; if (v->capacity >= cap && v->capacity <= cap * 2) return 0; if (vector_realloc(v, cap) < 0) return -1; return 0; } int vector_push(struct vector *v, const void *data, int count) { int needed = v->size + count; assert (count >= 0); if (size_for(v, needed) < 0) return -1; memcpy((char *)v->ptr + v->size * v->elemsize, data, count * v->elemsize); v->size += count; return 0; } void vector_pop(struct vector *v) { if (v->size <= 0) return; size_for(v, v->size - 1); v->size--; } mspdebug-0.25/util/vector.h000066400000000000000000000041431313531517500157040ustar00rootroot00000000000000/* MSPDebug - debugging tool for MSP430 MCUs * Copyright (C) 2009, 2010 Daniel Beer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef VECTOR_H_ #define VECTOR_H_ /* A vector is a flexible array type. It can be used to hold elements of * any type. * * elemsize: size in bytes of each element * capacity: maximum number of elements that ptr can hold * size: number of elements currently held */ struct vector { void *ptr; int elemsize; int capacity; int size; }; /* Create and destroy vectors */ void vector_init(struct vector *v, int elemsize); void vector_destroy(struct vector *v); /* Reallocate a vector to the given size. Returns 0 if successful, or -1 * if memory could not be allocated. */ int vector_realloc(struct vector *v, int capacity); /* Append any number of elements to the end of a vector, reallocating if * necessary. Returns 0 on success or -1 if memory could not be allocated. */ int vector_push(struct vector *v, const void *data, int count); /* Remove the last element from a vector. */ void vector_pop(struct vector *v); /* Dereference a vector, giving an expression for the element of type t at * position i in vector v. Use as follows: * * struct vector v; * * VECTOR_AT(v, 3, int) = 57; * *VECTOR_PTR(v, 3, int) = 57; */ #define VECTOR_AT(v, i, t) (*VECTOR_PTR(v, i, t)) #define VECTOR_PTR(v, i, t) \ ((t *)((char *)(v).ptr + (i) * (v).elemsize)) #endif