pax_global_header00006660000000000000000000000064134743246040014521gustar00rootroot0000000000000052 comment=c3a74de25f2d60284f909da1c6793793faa62b17 myhdl-0.11/000077500000000000000000000000001347432460400125575ustar00rootroot00000000000000myhdl-0.11/.github/000077500000000000000000000000001347432460400141175ustar00rootroot00000000000000myhdl-0.11/.github/ISSUE_TEMPLATE/000077500000000000000000000000001347432460400163025ustar00rootroot00000000000000myhdl-0.11/.github/ISSUE_TEMPLATE/bug_report.md000066400000000000000000000002601347432460400207720ustar00rootroot00000000000000--- name: Bug report about: Create a report to help us improve title: '' labels: bug assignees: '' --- Summary ## System information ``` MyHDL Version: Python Version: ``` myhdl-0.11/.github/ISSUE_TEMPLATE/feature_request.md000066400000000000000000000001521347432460400220250ustar00rootroot00000000000000--- name: Feature request about: Suggest an enhancement title: '' labels: enhancement assignees: '' --- myhdl-0.11/.github/ISSUE_TEMPLATE/usage_help.md000066400000000000000000000003071347432460400207400ustar00rootroot00000000000000--- name: Usage question about: Guidance on using MyHDL title: '' labels: question assignees: '' --- Please refer to our [discourse](http://discourse.myhdl.org/) or myhdl-0.11/.gitignore000066400000000000000000000005031347432460400145450ustar00rootroot00000000000000# General *~ *.swp *.out *.coverage build/ .cache .style.yapf # Python *.py[cod] __pycache__/ *egg-info/ dist/ .tox # Cosim *.o *.vpi *.so # Simulator generated files *.vcd modelsim.ini transcript *.log work/ work_nvc/ work_vlog/ work_vcom/ *.wlf # Test artifacts myhdl/**/*.v myhdl/**/*.vhd # Pycharm ide junk .idea/ myhdl-0.11/.hgignore000066400000000000000000000004041347432460400143600ustar00rootroot00000000000000syntax: glob .project .pydevproject CHANGELOG.txt MANIFEST modelsim.ini transcript *~ *.pyc *.swp *.v *.vhd *_ghdl *.o *.so *.log *.cf *.vpi *.orig *.vcd *.0 *.bak *.wlf *.rej *.out doc/build build/ dist/ old_conversion/ work/ work_vlog/ work_vcom/ *egg-info/ myhdl-0.11/.hgtags000066400000000000000000000040361347432460400140400ustar00rootroot0000000000000001ae44dd12e14ead938025d3f462a3cfdc220191 rel-0-4-1 01ae44dd12e14ead938025d3f462a3cfdc220191 rel_0-4-1 042b08c4a3cd7a08f5324990919fe19d862ead10 rel_0-6dev5 0a64f9387dd6ba341c9c01fb02282c7a05cb8de3 rel_0-5b1 0a9c1e60c542071deca8962aebf41812caa19cfd rel_0-5c1 18a5c6e04f6d147415aa15f834ecefee9b7fb260 rel_0-6dev4 18bd2f66222f9f32f82c53eff1d741157659c463 rel_0-3 2dbf142564387579cb1d87836ee4074915338166 rel_0-5dev2 3990d24e17e10de97a280eef64dc0131ad4866d3 rel_0-5 4564bba709ff38812ab1a83043dee7e3c1ea157a rel_0-5dev4 4e4baba6b59c32c1996df0e9358ecd65f155fa66 rel_0-1 4ed19bc3797263463b7a5828a768ffb6d62fa65d rel_0-5-1 50d0bfef3515b9b202bb5a3e88f5fab42a17c463 rel_0-2 54cb9498e9d4eea3675c559d874523d44dff29aa rel_0-5dev5 774ccdc8418b7f1bd07ffd419c43cc1090832b58 rel_0-4 7d5da2f750e7224e36d5e19d76bd66a6c28026c4 rel_0-6dev6 88a10384aecd4f48200f46b5cc0a324353500295 start 8945deac3a13fb77891eacaff80678bc5b4ecb0a TO_SVN 8945deac3a13fb77891eacaff80678bc5b4ecb0a rel_0-5-1dev1 b3154bb08e673d9bbd7c53abbfad6eb8853158e1 rel_0-5dev1 c74e985279e1d1cc719edf4efaf2da32da3a99e9 rel_0-5dev3 cb299ed9ac827c2cf594c83cec0a3093d46429eb alpha d4b7ac64ae3387637d688b05a68d007cdfef572b rel_0-5a1 e061a57835c1763995b1b1cf873367d876455647 rel_0-6dev2 c5db34e3d223b3ece00e62c192cc1ffaabd4e3a1 rel_0-6dev9 0000000000000000000000000000000000000000 rel_0-6dev9 bc1ecbdfa56dad48003743e666c472ca66b86f0f rel_0-6dev9 5e746c91ea7a47fae2a956a232e85827aac5daba rel_0-6dev10 0000000000000000000000000000000000000000 rel_0-6dev10 15b58c07d987f8a450d0cf3f02d328daa236c63a rel_0-6dev10 9e45b91ac223c8d26f145f7859a51edc266b903d rel_0-6 9e45b91ac223c8d26f145f7859a51edc266b903d 0.6 5e442df5265c924787a7616018ebd9270e3a39df 0.7 2273fc486116a7f3b251446db87de4648bdd2a61 0.7-final 25296ea8db6ea3d6e6bf431ca41ea81937d1d5d0 pypy-1.5 0f922ef8753e6e2d26bc13dae55820aa40536ca4 pypy-1.6 a6ef9dc5d7c58c6081d00ffbc87d6fbe07f2130f pypy-1.7 0513735d2cb5583668d58289a617c3aa71401c28 pypy-1.8 2421272373d81ab3aa13a65d0f3d3fc7a783288c pypy-1.9 41f6e9fdcb55ab8196a954906d8de1a09fac02fd 0.8 0f5597633e99138f613d1d613a215fb4652345ac 0.8.1 myhdl-0.11/.landscape.yaml000066400000000000000000000001371347432460400154540ustar00rootroot00000000000000doc-warnings: yes test-warnings: yes strictness: veryhigh max-line-length: 100 autodetect: yes myhdl-0.11/.travis.yml000066400000000000000000000012311347432460400146650ustar00rootroot00000000000000# http://docs.travis-ci.com/user/workers/container-based-infrastructure/ dist: xenial sudo: true language: python python: - "3.7" - "3.6" - "2.7" - "pypy3.5" install: - pip install . env: - CI_TARGET=core - CI_TARGET=iverilog - CI_TARGET=ghdl matrix: allow_failures: - python: "pypy3.5" before_script: - if [[ "$CI_TARGET" == "iverilog" ]]; then sudo apt-get -qq update; sudo apt-get install iverilog; elif [[ "$CI_TARGET" == "ghdl" ]]; then sudo add-apt-repository ppa:mati75/ghdl -y; sudo apt-get -qq update; sudo apt-get install ghdl; fi script: ./scripts/ci.sh notifications: email: false myhdl-0.11/CHANGES.txt000066400000000000000000000044471347432460400144010ustar00rootroot00000000000000Release 0.9.0 11-Jul-2015 ------------------------- Full details about new features and changes can be found here: http://docs.myhdl.org/en/latest/whatsnew/0.9.html Release 0.8.1 26-Aug-2014 ------------------------- Maintenance release for 0.8. Release 0.8 20-May-2013 ----------------------- Full details about new features and changes can be found here: http://docs.myhdl.org/en/latest/whatsnew/0.8.html Release 0.7 24-Dec-2010 ----------------------- Full details about new features and changes can be found here: http://docs.myhdl.org/en/latest/whatsnew/0.7.html Release 0.6 9-Jan-2009 ----------------------- Full details about new features and changes can be found here: http://docs.myhdl.org/en/latest/whatsnew/0.6.html Release 0.5.1 1-May-2006 ------------------------- Maintenance release for 0.5. See the bug tracker for fixed issues. Release 0.5 29-Dec-2005 ----------------------- Full details about new features and changes can be found here: http://old.myhdl.org/doku.php/whatsnew:0.5 Release 0.4.1 29-Dec-2004 ------------------------- * Maintenance release that solves most outstanding issues and implements some feature requests. See the SourceForge Bug and RFE Trackers for details. (Use the group 'MyHDL 0.4' to find the relevant issues.) More info can also be found on the mailing list. * Added cosimulation support for the cver Verilog simulator. Note: the documentation was not modified in this release. Release 0.4 4-Feb-2004 ---------------------- * Conversion to Verilog to provide a path to implementation For full details about the changes, consult: http://old.myhdl.org/doc/0.4/whatsnew04/whatsnew04.html Release 0.3 30-Aug-2003 ----------------------- * VCD output for waveform viewing * Enumeration types support * Inferring the sensitivity list for combinatorial logic * Inferring the list of instances * Inferring the list of processes * Class intbv enhancements * Function concat() * Python 2.3 support For full details about the changes, consult: http://old.myhdl.org/doc/0.3/whatsnew03/whatsnew03.html Release 0.2 19-May-2003 ----------------------- * Added cosimulation support to MyHDL. A PLI interface module to the Icarus Verilog simulator is included. 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Here is a sample; alter the names: Yoyodyne, Inc., hereby disclaims all copyright interest in the library `Frob' (a library for tweaking knobs) written by James Random Hacker. , 1 April 1990 Ty Coon, President of Vice That's all there is to it! myhdl-0.11/MANIFEST.in000066400000000000000000000012331347432460400143140ustar00rootroot00000000000000global-include *.py global-include *.txt global-include *.pdf global-include *.ps global-include *.c global-include Makefile global-include makefile* global-include *.v global-include *.vhd prune .hg prune dist prune doc prune olddoc prune myhdl/old_conversion prune myhdl/*/work prune myhdl/*/*/work prune myhdl/*/*/*/work prune myhdl/*/work_vlog prune myhdl/*/*/work_vlog prune myhdl/*/*/*/work_vlog prune myhdl/*/work_vcom prune myhdl/*/*/work_vcom prune myhdl/*/*/*/work_vcom graft doc/build/html #include doc/paper-a4/MyHDL.pdf #include doc/paper-letter/MyHDL.pdf prune myhdl/experiments exclude myhdl/test/conversion/*/*.v exclude myhdl/test/conversion/*/*.vhd myhdl-0.11/Makefile000066400000000000000000000003621347432460400142200ustar00rootroot00000000000000install: python setup.py install localinstall: python setup.py install --home=$(HOME) docs: tox -e docs html livedocs: tox -e docs livehtml release: - rm MANIFEST - rm CHANGELOG.txt hg glog > CHANGELOG.txt python setup.py sdist myhdl-0.11/README.md000066400000000000000000000037151347432460400140440ustar00rootroot00000000000000MyHDL 0.11 ========== [![Join the chat at https://gitter.im/myhdl/myhdl](https://badges.gitter.im/Join%20Chat.svg)](https://gitter.im/myhdl/myhdl?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge) [![Documentation Status](https://readthedocs.org/projects/myhdl/badge/?version=stable)](http://docs.myhdl.org/en/stable/manual/) [![Documentation Status](https://readthedocs.org/projects/myhdl/badge/?version=latest)](http://docs.myhdl.org/en/latest/manual) [![Build Status](https://travis-ci.org/myhdl/myhdl.svg?branch=master)](https://travis-ci.org/myhdl/myhdl) What is MyHDL? -------------- MyHDL is a free, open-source package for using Python as a hardware description and verification language. To find out whether MyHDL can be useful to you, please read: - http://www.myhdl.org/start/why.html License ------- MyHDL is available under the LGPL license. See ``LICENSE.txt``. Website ------- The project website is located at http://www.myhdl.org Documentation ------------- The manual is available on-line: - http://docs.myhdl.org/en/stable/manual What's new ---------- To find out what's new in this release, please read: - http://docs.myhdl.org/en/stable/whatsnew/0.11.html Installation ------------ It is recommended to install MyHDL (and your project's other dependencies) in a virtualenv. Installing the latest stable release: ``` pip install myhdl ``` To install the development version from github: ``` pip install -e 'git+https://github.com/myhdl/myhdl#egg=myhdl ``` To install a local clone of the repository: ``` pip install -e path/to/dir ``` To install a specific commit hash, tag or branch from git: ``` pip install -e 'git+https://github.com/myhdl/myhdl@f696b8#egg=myhdl ``` You can test the proper installation as follows: ``` cd myhdl/test/core py.test ``` To install co-simulation support: Go to the directory ``cosimulation/`` for your target platform and following the instructions in the ``README.txt`` file. myhdl-0.11/cosimulation/000077500000000000000000000000001347432460400152655ustar00rootroot00000000000000myhdl-0.11/cosimulation/cver/000077500000000000000000000000001347432460400162245ustar00rootroot00000000000000myhdl-0.11/cosimulation/cver/Makefile.lnx000066400000000000000000000011531347432460400204640ustar00rootroot00000000000000# could add to CFLAGS to turn on warnings if you are using gcc WARNS=-Wall # change this path to point to the pli include files directory for cver INCS=-I$(HOME)/Tools/gplcver-2.12a.src/pli_incs # maybe want -O and/or -g # -fno-stack-protector apparently needed with newer gcc's CFLAGS= -fPIC -fno-stack-protector -Wall -g $(INCS) LFLAGS= -G -shared -export-dynamic # change to your compiler CC=gcc all: myhdl_vpi.so myhdl_vpi.o: myhdl_vpi.c $(CC) $(CFLAGS) -c myhdl_vpi.c # make rules for dynamic libaries myhdl_vpi.so: myhdl_vpi.o $(LD) $(LFLAGS) myhdl_vpi.o -o myhdl_vpi.so clean: -rm *.o *.so myhdl-0.11/cosimulation/cver/Makefile.lnx64000066400000000000000000000010321347432460400206320ustar00rootroot00000000000000# could add to CFLAGS to turn on warnings if you are using gcc WARNS=-Wall # change this path to point to the pli include files directory for cver INCS=-I /usr/include/pli_incs # maybe want -O and/or -g CFLAGS= -fPIC -Wall -g -m32 $(INCS) LFLAGS= -G -shared -export-dynamic -melf_i386 # change to your compiler CC=gcc all: myhdl_vpi.so myhdl_vpi.o: myhdl_vpi.c $(CC) $(CFLAGS) -c myhdl_vpi.c # make rules for dynamic libaries myhdl_vpi.so: myhdl_vpi.o $(LD) $(LFLAGS) myhdl_vpi.o -o myhdl_vpi.so clean: -rm *.o *.so myhdl-0.11/cosimulation/cver/Makefile.osx000066400000000000000000000012401347432460400204710ustar00rootroot00000000000000# could add to CFLAGS to turn on warnings if you are using gcc WARNS=-Wall # change path if not running test from installed directory location INCS=-I/opt/local/share/gplcver/pli_incs # you must use exactly these flags for OSX CFLAGS= -fPIC -Wall $(INCS) -dynamic -fno-common LFLAGS= -flat_namespace -bundle -undefined suppress # change to your compiler CC=gcc all: myhdl_vpi.dylib myhdl_vpi.o: myhdl_vpi.c $(CC) $(CFLAGS) -c myhdl_vpi.c # make rules for dynamic libaries myhdl_vpi.dylib: myhdl_vpi.o $(CC) $(LFLAGS) myhdl_vpi.o -o myhdl_vpi.dylib clean: -rm *.o *.so myhdl-0.11/cosimulation/cver/README.txt000066400000000000000000000020411347432460400177170ustar00rootroot00000000000000MyHDL co-simulation relies on Unix-style interprocess communication. To run co-simulation on Windows, compile and use all tools involved (including Python itself) on a Unix-like environment for Windows, such as cygwin. For co-simulation with cver, the following is required: * a working cver installation * a 'myhdl_vpi.so' file, generated from 'myhdl_vpi.c' For Linux, a makefile 'makefile.lnx' is provided to generate 'myhdl_vpi.so'. However, you will have to edit the makefile to point to the correct pli include files for cver. See the makefile for instructions. To test whether it works, go to the 'test' subdirectory and run the tests with 'python test_all.py'. For co-simulation with MyHDL, 'cver' should be run with the 'myhdl_vpi.so' PLI module, using the '+loadvpi' option, and with the 'vpi_compat_bootstrap' routine as the bootstrap routine. The Verilog code should contain the appropriate calls to the '$to_myhdl' and 'from_myhdl' tasks. The 'myhdl_vpi.c' module was developed and verified with cver version GPLCVER_1.10f on Linux. myhdl-0.11/cosimulation/cver/myhdl_vpi.c000066400000000000000000000305411347432460400203660ustar00rootroot00000000000000#include #include #include #include #include #include "vpi_user.h" #include "cv_vpi_user.h" #define MAXLINE 4096 #define MAXWIDTH 10 #define MAXARGS 64 // #define DEBUG 1 /* Sized variables */ #ifndef PLI_TYPES #define PLI_TYPES typedef int PLI_INT32; typedef unsigned int PLI_UINT32; typedef short PLI_INT16; typedef unsigned short PLI_UINT16; typedef char PLI_BYTE8; typedef unsigned char PLI_UBYTE8; #endif /* 64 bit type for time calculations */ typedef unsigned long long myhdl_time64_t; static int rpipe; static int wpipe; static vpiHandle from_myhdl_systf_handle = NULL; static vpiHandle to_myhdl_systf_handle = NULL; static char changeFlag[MAXARGS]; static char bufcp[MAXLINE]; static myhdl_time64_t myhdl_time; static myhdl_time64_t verilog_time; static myhdl_time64_t pli_time; static int delta; /* prototypes */ static PLI_INT32 from_myhdl_calltf(PLI_BYTE8 *user_data); static PLI_INT32 to_myhdl_calltf(PLI_BYTE8 *user_data); static PLI_INT32 readonly_callback(p_cb_data cb_data); static PLI_INT32 delay_callback(p_cb_data cb_data); static PLI_INT32 delta_callback(p_cb_data cb_data); static PLI_INT32 change_callback(p_cb_data cb_data); static int init_pipes(); static myhdl_time64_t timestruct_to_time(const struct t_vpi_time*ts); /* from Icarus */ static myhdl_time64_t timestruct_to_time(const struct t_vpi_time*ts) { myhdl_time64_t ti = ts->high; ti <<= 32; ti += ts->low & 0xffffffff; return ti; } static int init_pipes() { char *w; char *r; static int init_pipes_flag = 0; if (init_pipes_flag) { return(0); } if ((w = getenv("MYHDL_TO_PIPE")) == NULL) { vpi_printf("ERROR: no write pipe to myhdl\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } if ((r = getenv("MYHDL_FROM_PIPE")) == NULL) { vpi_printf("ERROR: no read pipe from myhdl\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } wpipe = atoi(w); rpipe = atoi(r); init_pipes_flag = 1; return (0); } static PLI_INT32 from_myhdl_calltf(PLI_BYTE8 *user_data) { vpiHandle reg_iter, reg_handle; s_vpi_time verilog_time_s; char buf[MAXLINE]; char s[MAXWIDTH]; int n; static int from_myhdl_flag = 0; if (from_myhdl_flag) { vpi_printf("ERROR: $from_myhdl called more than once\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } from_myhdl_flag = 1; init_pipes(); verilog_time_s.type = vpiSimTime; vpi_get_time(NULL, &verilog_time_s); verilog_time = timestruct_to_time(&verilog_time_s); if (verilog_time != 0) { vpi_printf("ERROR: $from_myhdl should be called at time 0\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } sprintf(buf, "FROM 0 "); pli_time = 0; delta = 0; from_myhdl_systf_handle = vpi_handle(vpiSysTfCall, NULL); reg_iter = vpi_iterate(vpiArgument, from_myhdl_systf_handle); while ((reg_handle = vpi_scan(reg_iter)) != NULL) { if (vpi_get(vpiType, reg_handle) != vpiReg) { vpi_printf("ERROR: $from_myhdl argument %s should be a reg\n", vpi_get_str(vpiName, reg_handle)); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } strcat(buf, vpi_get_str(vpiName, reg_handle)); strcat(buf, " "); sprintf(s, "%d ", vpi_get(vpiSize, reg_handle)); strcat(buf, s); } n = write(wpipe, buf, strlen(buf)); if ((n = read(rpipe, buf, MAXLINE)) == 0) { vpi_printf("Info: MyHDL simulator down\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } assert(n > 0); buf[n] = '\0'; return(0); } static PLI_INT32 to_myhdl_calltf(PLI_BYTE8 *user_data) { vpiHandle net_iter, net_handle, cb_h; char buf[MAXLINE]; char s[MAXWIDTH]; int n; int i; int *id; s_cb_data cb_data_s; s_vpi_time verilog_time_s; s_vpi_time time_s; s_vpi_value value_s; static int to_myhdl_flag = 0; if (to_myhdl_flag) { vpi_printf("ERROR: $to_myhdl called more than once\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } to_myhdl_flag = 1; init_pipes(); verilog_time_s.type = vpiSimTime; vpi_get_time(NULL, &verilog_time_s); verilog_time = timestruct_to_time(&verilog_time_s); if (verilog_time != 0) { vpi_printf("ERROR: $to_myhdl should be called at time 0\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } sprintf(buf, "TO 0 "); pli_time = 0; delta = 0; time_s.type = vpiSuppressTime; value_s.format = vpiSuppressVal; cb_data_s.reason = cbValueChange; cb_data_s.cb_rtn = change_callback; cb_data_s.time = &time_s; cb_data_s.value = &value_s; // value_s.format = vpiHexStrVal; i = 0; to_myhdl_systf_handle = vpi_handle(vpiSysTfCall, NULL); net_iter = vpi_iterate(vpiArgument, to_myhdl_systf_handle); while ((net_handle = vpi_scan(net_iter)) != NULL) { if (i == MAXARGS) { vpi_printf("ERROR: $to_myhdl max #args (%d) exceeded\n", MAXARGS); vpi_control(vpiFinish, 1); /* abort simulation */ } strcat(buf, vpi_get_str(vpiName, net_handle)); strcat(buf, " "); sprintf(s, "%d ", vpi_get(vpiSize, net_handle)); strcat(buf, s); changeFlag[i] = 0; id = malloc(sizeof(int)); *id = i; cb_data_s.user_data = (PLI_BYTE8 *)id; cb_data_s.obj = net_handle; cb_h = vpi_register_cb(&cb_data_s); vpi_free_object(cb_h); i++; } n = write(wpipe, buf, strlen(buf)); if ((n = read(rpipe, buf, MAXLINE)) == 0) { vpi_printf("ABORT from $to_myhdl\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } buf[n] = '\0'; assert(n > 0); // register read-only callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 0; cb_data_s.reason = cbReadOnlySynch; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = readonly_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; cb_h = vpi_register_cb(&cb_data_s); vpi_free_object(cb_h); // pre-register delta cycle callback // delta = 0; time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 1; cb_data_s.reason = cbAfterDelay; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = delta_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; cb_h = vpi_register_cb(&cb_data_s); vpi_free_object(cb_h); return(0); } static PLI_INT32 readonly_callback(p_cb_data cb_data) { vpiHandle net_iter, net_handle, cb_h; s_cb_data cb_data_s; s_vpi_time verilog_time_s; s_vpi_value value_s; s_vpi_time time_s; char buf[MAXLINE]; int n; int i; char *myhdl_time_string; myhdl_time64_t delay; static int start_flag = 1; if (start_flag) { start_flag = 0; n = write(wpipe, "START", 5); // vpi_printf("INFO: RO cb at start-up\n"); if ((n = read(rpipe, buf, MAXLINE)) == 0) { vpi_printf("ABORT from RO cb at start-up\n"); vpi_control(vpiFinish, 1); /* abort simulation */ } assert(n > 0); } buf[0] = '\0'; verilog_time_s.type = vpiSimTime; vpi_get_time(NULL, &verilog_time_s); verilog_time = timestruct_to_time(&verilog_time_s); if (verilog_time != (pli_time * 1000 + delta)) { vpi_printf("%u %u\n", verilog_time_s.high, verilog_time_s.low ); vpi_printf("%llu %llu %d\n", verilog_time, pli_time, delta); } /* Icarus 0.7 fails on this assertion beyond 32 bits due to a bug */ // assert(verilog_time == pli_time * 1000 + delta); assert( (verilog_time & 0xFFFFFFFF) == ( (pli_time * 1000 + delta) & 0xFFFFFFFF ) ); sprintf(buf, "%llu ", pli_time); net_iter = vpi_iterate(vpiArgument, to_myhdl_systf_handle); value_s.format = vpiHexStrVal; i = 0; while ((net_handle = vpi_scan(net_iter)) != NULL) { if (changeFlag[i]) { strcat(buf, vpi_get_str(vpiName, net_handle)); strcat(buf, " "); vpi_get_value(net_handle, &value_s); strcat(buf, value_s.value.str); strcat(buf, " "); changeFlag[i] = 0; } i++; } n = write(wpipe, buf, strlen(buf)); if ((n = read(rpipe, buf, MAXLINE)) == 0) { // vpi_printf("ABORT from RO cb\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } assert(n > 0); buf[n] = '\0'; /* save copy for later callback */ strcpy(bufcp, buf); myhdl_time_string = strtok(buf, " "); myhdl_time = (myhdl_time64_t) strtoull(myhdl_time_string, (char **) NULL, 10); delay = (myhdl_time - pli_time) * 1000; assert(delay >= 0); assert(delay <= 0xFFFFFFFF); if (delay > 0) { // schedule cbAfterDelay callback assert(delay > delta); delay -= delta; /* Icarus 20030518 runs RO callbacks when time has already advanced */ /* Therefore, one had to compensate for the prescheduled delta callback */ /* delay -= 1; */ /* Icarus 20031009 has a different scheduler, more correct I believe */ /* compensation is no longer necessary */ delta = 0; pli_time = myhdl_time; // register cbAfterDelay callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = (PLI_UINT32) delay; cb_data_s.reason = cbAfterDelay; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = delay_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; cb_h = vpi_register_cb(&cb_data_s); vpi_free_object(cb_h); } else { delta++; assert(delta < 1000); } return(0); } static PLI_INT32 delay_callback(p_cb_data cb_data) { s_vpi_time time_s; s_cb_data cb_data_s; vpiHandle cb_h; // register readonly callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 0; cb_data_s.reason = cbReadOnlySynch; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = readonly_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; cb_h = vpi_register_cb(&cb_data_s); vpi_free_object(cb_h); // register delta callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 1; cb_data_s.reason = cbAfterDelay; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = delta_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; cb_h = vpi_register_cb(&cb_data_s); vpi_free_object(cb_h); return(0); } static PLI_INT32 delta_callback(p_cb_data cb_data) { s_cb_data cb_data_s; s_vpi_time time_s; vpiHandle reg_iter, reg_handle, cb_h; s_vpi_value value_s; if (delta == 0) { return(0); } /* skip time value */ strtok(bufcp, " "); reg_iter = vpi_iterate(vpiArgument, from_myhdl_systf_handle); value_s.format = vpiHexStrVal; while ((value_s.value.str = strtok(NULL, " ")) != NULL) { reg_handle = vpi_scan(reg_iter); vpi_put_value(reg_handle, &value_s, NULL, vpiNoDelay); } if (reg_iter != NULL) { vpi_free_object(reg_iter); } // register readonly callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 0; cb_data_s.reason = cbReadOnlySynch; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = readonly_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; cb_h = vpi_register_cb(&cb_data_s); vpi_free_object(cb_h); // register delta callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 1; cb_data_s.reason = cbAfterDelay; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = delta_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; cb_h = vpi_register_cb(&cb_data_s); vpi_free_object(cb_h); return(0); } static PLI_INT32 change_callback(p_cb_data cb_data) { int *id; // vpi_printf("change callback"); id = (int *)cb_data->user_data; changeFlag[*id] = 1; return(0); } void myhdl_register() { s_vpi_systf_data tf_data; tf_data.type = vpiSysTask; tf_data.tfname = "$to_myhdl"; tf_data.calltf = (void *) to_myhdl_calltf; tf_data.compiletf = NULL; tf_data.sizetf = NULL; tf_data.user_data = "$to_myhdl"; vpi_register_systf(&tf_data); tf_data.type = vpiSysTask; tf_data.tfname = "$from_myhdl"; tf_data.calltf = (void *) from_myhdl_calltf; tf_data.compiletf = NULL; tf_data.sizetf = NULL; tf_data.user_data = "$from_myhdl"; vpi_register_systf(&tf_data); } void (*vlog_startup_routines[])() = { myhdl_register, 0 }; /* dummy +loadvpi= boostrap routine - mimics old style exec all routines */ /* in standard PLI vlog_startup_routines table */ void vpi_compat_bootstrap(void) { int i; for (i = 0;; i++) { if (vlog_startup_routines[i] == NULL) break; vlog_startup_routines[i](); } } myhdl-0.11/cosimulation/cver/test/000077500000000000000000000000001347432460400172035ustar00rootroot00000000000000myhdl-0.11/cosimulation/cver/test/bin2gray.py000066400000000000000000000004651347432460400212770ustar00rootroot00000000000000import os from myhdl import Cosimulation cmd = "cver -q +loadvpi=../myhdl_vpi:vpi_compat_bootstrap +define+width=%s " + \ "../../test/verilog/bin2gray.v " + \ "../../test/verilog/dut_bin2gray.v " def bin2gray(B, G, width): return Cosimulation(cmd % width, B=B, G=G) myhdl-0.11/cosimulation/cver/test/dff.py000066400000000000000000000004221347432460400203120ustar00rootroot00000000000000import os from myhdl import Cosimulation cmd = "cver -q +loadvpi=../myhdl_vpi:vpi_compat_bootstrap " + \ "../../test/verilog/dff.v " + \ "../../test/verilog/dut_dff.v " def dff(q, d, clk, reset): return Cosimulation(cmd, **locals()) myhdl-0.11/cosimulation/cver/test/dff_clkout.py000066400000000000000000000005061347432460400216760ustar00rootroot00000000000000import os import os.path as path from myhdl import Cosimulation cmd = "cver -q +loadvpi=../myhdl_vpi:vpi_compat_bootstrap " + \ "../../test/verilog/dff_clkout.v " + \ "../../test/verilog/dut_dff_clkout.v " def dff_clkout(clkout, q, d, clk, reset): return Cosimulation(cmd, **locals()) myhdl-0.11/cosimulation/cver/test/inc.py000066400000000000000000000004531347432460400203300ustar00rootroot00000000000000import os from myhdl import Cosimulation cmd = "cver -q +loadvpi=../myhdl_vpi:vpi_compat_bootstrap +define+n=%s " + \ "../../test/verilog/inc.v " + \ "../../test/verilog/dut_inc.v " def inc(count, enable, clock, reset, n): return Cosimulation(cmd % n, **locals()) myhdl-0.11/cosimulation/cver/test/test_all.py000066400000000000000000000026521347432460400213710ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run cosimulation unit tests. """ import sys sys.path.append("../../test") import test_bin2gray, test_inc, test_dff # modules = (test_inc, ) modules = (test_bin2gray, test_inc, test_dff ) import unittest tl = unittest.defaultTestLoader def suite(): alltests = unittest.TestSuite() for m in modules: alltests.addTest(tl.loadTestsFromModule(m)) return alltests def main(): unittest.main(defaultTest='suite', testRunner=unittest.TextTestRunner(verbosity=2)) if __name__ == '__main__': main() myhdl-0.11/cosimulation/icarus/000077500000000000000000000000001347432460400165535ustar00rootroot00000000000000myhdl-0.11/cosimulation/icarus/Makefile000066400000000000000000000002521347432460400202120ustar00rootroot00000000000000all: myhdl.vpi myhdl.vpi: myhdl.c myhdl_table.c iverilog-vpi myhdl.c myhdl_table.c .PHONY: test test: myhdl.vpi cd test && python test_all.py clean: -rm *.o *.vpi myhdl-0.11/cosimulation/icarus/README.txt000066400000000000000000000022421347432460400202510ustar00rootroot00000000000000MyHDL co-simulation relies on Unix-style interprocess communication. To run co-simulation on Windows, compile and use all tools involved (including Python itself) on a Unix-like environment for Windows, such as cygwin. For co-simulation with Icarus, a working Icarus installation is required, so that the commands 'iverilog' and 'vvp' are available. Run the Makefile by typing 'make'. This should generate a 'myhdl.vpi' PLI module. Install it in an appropriate location, where 'vvp' can find it. Note that you can use the '-m' flag to vvp to specify the PLI module path. To test whether it works, go to the 'test' subdirectory and run the tests with 'python test_all.py'. For co-simulation with MyHDL, 'vvp' should be run with the 'myhdl.vpi' PLI module, and the Verilog code should contain the appropriate calls to the '$to_myhdl' and 'from_myhdl' tasks. The 'myhdl.vpi' module was developed and verified with Icarus 0.7. Between snapshot 20030518 (used in MyHDL 0.3), and 20031009, the Icarus scheduler has been improved. This requires a small update of myhdl.c. The current version is supposed to work with recent snapshots - the older version is available in myhdl_20030518.c myhdl-0.11/cosimulation/icarus/myhdl.c000066400000000000000000000273621347432460400200460ustar00rootroot00000000000000#include #include #include #include #include #include "vpi_user.h" #define MAXLINE 4096 #define MAXWIDTH 10 #define MAXARGS 1024 // #define DEBUG 1 /* Sized variables */ #ifndef PLI_TYPES #define PLI_TYPES typedef int PLI_INT32; typedef unsigned int PLI_UINT32; typedef short PLI_INT16; typedef unsigned short PLI_UINT16; typedef char PLI_BYTE8; typedef unsigned char PLI_UBYTE8; #endif /* 64 bit type for time calculations */ typedef unsigned long long myhdl_time64_t; static int rpipe; static int wpipe; static vpiHandle from_myhdl_systf_handle = NULL; static vpiHandle to_myhdl_systf_handle = NULL; static char changeFlag[MAXARGS]; static char bufcp[MAXLINE]; static myhdl_time64_t myhdl_time; static myhdl_time64_t verilog_time; static myhdl_time64_t pli_time; static int delta; /* prototypes */ static PLI_INT32 from_myhdl_calltf(PLI_BYTE8 *user_data); static PLI_INT32 to_myhdl_calltf(PLI_BYTE8 *user_data); static PLI_INT32 readonly_callback(p_cb_data cb_data); static PLI_INT32 delay_callback(p_cb_data cb_data); static PLI_INT32 delta_callback(p_cb_data cb_data); static PLI_INT32 change_callback(p_cb_data cb_data); static int init_pipes(); static myhdl_time64_t timestruct_to_time(const struct t_vpi_time*ts); /* from Icarus */ static myhdl_time64_t timestruct_to_time(const struct t_vpi_time*ts) { myhdl_time64_t ti = ts->high; ti <<= 32; ti += ts->low & 0xffffffff; return ti; } static int init_pipes() { char *w; char *r; static int init_pipes_flag = 0; if (init_pipes_flag) { return(0); } if ((w = getenv("MYHDL_TO_PIPE")) == NULL) { vpi_printf("ERROR: no write pipe to myhdl\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } if ((r = getenv("MYHDL_FROM_PIPE")) == NULL) { vpi_printf("ERROR: no read pipe from myhdl\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } wpipe = atoi(w); rpipe = atoi(r); init_pipes_flag = 1; return (0); } static PLI_INT32 from_myhdl_calltf(PLI_BYTE8 *user_data) { vpiHandle reg_iter, reg_handle; s_vpi_time verilog_time_s; char buf[MAXLINE]; char s[MAXWIDTH]; int n; static int from_myhdl_flag = 0; if (from_myhdl_flag) { vpi_printf("ERROR: $from_myhdl called more than once\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } from_myhdl_flag = 1; init_pipes(); verilog_time_s.type = vpiSimTime; vpi_get_time(NULL, &verilog_time_s); verilog_time = timestruct_to_time(&verilog_time_s); if (verilog_time != 0) { vpi_printf("ERROR: $from_myhdl should be called at time 0\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } sprintf(buf, "FROM 0 "); pli_time = 0; delta = 0; from_myhdl_systf_handle = vpi_handle(vpiSysTfCall, NULL); reg_iter = vpi_iterate(vpiArgument, from_myhdl_systf_handle); while ((reg_handle = vpi_scan(reg_iter)) != NULL) { if (vpi_get(vpiType, reg_handle) != vpiReg) { vpi_printf("ERROR: $from_myhdl argument %s should be a reg\n", vpi_get_str(vpiName, reg_handle)); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } strcat(buf, vpi_get_str(vpiName, reg_handle)); strcat(buf, " "); sprintf(s, "%d ", vpi_get(vpiSize, reg_handle)); strcat(buf, s); } n = write(wpipe, buf, strlen(buf)); if ((n = read(rpipe, buf, MAXLINE)) == 0) { vpi_printf("Info: MyHDL simulator down\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } assert(n > 0); buf[n] = '\0'; return(0); } static PLI_INT32 to_myhdl_calltf(PLI_BYTE8 *user_data) { vpiHandle net_iter, net_handle; char buf[MAXLINE]; char s[MAXWIDTH]; int n; int i; int *id; s_cb_data cb_data_s; s_vpi_time verilog_time_s; s_vpi_time time_s; s_vpi_value value_s; static int to_myhdl_flag = 0; if (to_myhdl_flag) { vpi_printf("ERROR: $to_myhdl called more than once\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } to_myhdl_flag = 1; init_pipes(); verilog_time_s.type = vpiSimTime; vpi_get_time(NULL, &verilog_time_s); verilog_time = timestruct_to_time(&verilog_time_s); if (verilog_time != 0) { vpi_printf("ERROR: $to_myhdl should be called at time 0\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } sprintf(buf, "TO 0 "); pli_time = 0; delta = 0; time_s.type = vpiSuppressTime; value_s.format = vpiSuppressVal; cb_data_s.reason = cbValueChange; cb_data_s.cb_rtn = change_callback; cb_data_s.time = &time_s; // icarus stops on the following line but shouldn't // cb_data_s.value = &value_s; cb_data_s.value = NULL; i = 0; to_myhdl_systf_handle = vpi_handle(vpiSysTfCall, NULL); net_iter = vpi_iterate(vpiArgument, to_myhdl_systf_handle); while ((net_handle = vpi_scan(net_iter)) != NULL) { if (i == MAXARGS) { vpi_printf("ERROR: $to_myhdl max #args (%d) exceeded\n", MAXARGS); vpi_control(vpiFinish, 1); /* abort simulation */ } strcat(buf, vpi_get_str(vpiName, net_handle)); strcat(buf, " "); sprintf(s, "%d ", vpi_get(vpiSize, net_handle)); strcat(buf, s); changeFlag[i] = 0; id = malloc(sizeof(int)); *id = i; cb_data_s.user_data = (PLI_BYTE8 *)id; cb_data_s.obj = net_handle; vpi_register_cb(&cb_data_s); i++; } n = write(wpipe, buf, strlen(buf)); if ((n = read(rpipe, buf, MAXLINE)) == 0) { vpi_printf("ABORT from $to_myhdl\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } buf[n] = '\0'; assert(n > 0); // register read-only callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 0; cb_data_s.reason = cbReadOnlySynch; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = readonly_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; vpi_register_cb(&cb_data_s); // pre-register delta cycle callback // delta = 0; time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 1; cb_data_s.reason = cbAfterDelay; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = delta_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; vpi_register_cb(&cb_data_s); return(0); } static PLI_INT32 readonly_callback(p_cb_data cb_data) { vpiHandle net_iter, net_handle; s_cb_data cb_data_s; s_vpi_time verilog_time_s; s_vpi_value value_s; s_vpi_time time_s; char buf[MAXLINE]; int n; int i; char *myhdl_time_string; myhdl_time64_t delay; static int start_flag = 1; if (start_flag) { start_flag = 0; n = write(wpipe, "START", 5); // vpi_printf("INFO: RO cb at start-up\n"); if ((n = read(rpipe, buf, MAXLINE)) == 0) { vpi_printf("ABORT from RO cb at start-up\n"); vpi_control(vpiFinish, 1); /* abort simulation */ } assert(n > 0); } buf[0] = '\0'; verilog_time_s.type = vpiSimTime; vpi_get_time(NULL, &verilog_time_s); verilog_time = timestruct_to_time(&verilog_time_s); if (verilog_time != (pli_time * 1000 + delta)) { vpi_printf("%u %u\n", verilog_time_s.high, verilog_time_s.low ); vpi_printf("%llu %llu %d\n", verilog_time, pli_time, delta); } /* Icarus 0.7 fails on this assertion beyond 32 bits due to a bug */ // assert(verilog_time == pli_time * 1000 + delta); assert( (verilog_time & 0xFFFFFFFF) == ( (pli_time * 1000 + delta) & 0xFFFFFFFF ) ); sprintf(buf, "%llu ", pli_time); net_iter = vpi_iterate(vpiArgument, to_myhdl_systf_handle); value_s.format = vpiHexStrVal; i = 0; while ((net_handle = vpi_scan(net_iter)) != NULL) { if (changeFlag[i]) { strcat(buf, vpi_get_str(vpiName, net_handle)); strcat(buf, " "); vpi_get_value(net_handle, &value_s); strcat(buf, value_s.value.str); strcat(buf, " "); changeFlag[i] = 0; } i++; } n = write(wpipe, buf, strlen(buf)); if ((n = read(rpipe, buf, MAXLINE)) == 0) { // vpi_printf("ABORT from RO cb\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } assert(n > 0); buf[n] = '\0'; /* save copy for later callback */ strcpy(bufcp, buf); myhdl_time_string = strtok(buf, " "); myhdl_time = (myhdl_time64_t) strtoull(myhdl_time_string, (char **) NULL, 10); delay = (myhdl_time - pli_time) * 1000; assert(delay >= 0); assert(delay <= 0xFFFFFFFF); if (delay > 0) { // schedule cbAfterDelay callback assert(delay > delta); delay -= delta; /* Icarus 20030518 runs RO callbacks when time has already advanced */ /* Therefore, one had to compensate for the prescheduled delta callback */ /* delay -= 1; */ /* Icarus 20031009 has a different scheduler, more correct I believe */ /* compensation is no longer necessary */ delta = 0; pli_time = myhdl_time; // register cbAfterDelay callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = (PLI_UINT32) delay; cb_data_s.reason = cbAfterDelay; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = delay_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; vpi_register_cb(&cb_data_s); } else { delta++; assert(delta < 1000); } return(0); } static PLI_INT32 delay_callback(p_cb_data cb_data) { s_vpi_time time_s; s_cb_data cb_data_s; // register readonly callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 0; cb_data_s.reason = cbReadOnlySynch; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = readonly_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; vpi_register_cb(&cb_data_s); // register delta callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 1; cb_data_s.reason = cbAfterDelay; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = delta_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; vpi_register_cb(&cb_data_s); return(0); } static PLI_INT32 delta_callback(p_cb_data cb_data) { s_cb_data cb_data_s; s_vpi_time time_s; vpiHandle reg_iter, reg_handle; s_vpi_value value_s; if (delta == 0) { return(0); } /* skip time value */ strtok(bufcp, " "); reg_iter = vpi_iterate(vpiArgument, from_myhdl_systf_handle); value_s.format = vpiHexStrVal; while ((value_s.value.str = strtok(NULL, " ")) != NULL) { reg_handle = vpi_scan(reg_iter); vpi_put_value(reg_handle, &value_s, NULL, vpiNoDelay); } if (reg_iter != NULL) { vpi_free_object(reg_iter); } // register readonly callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 0; cb_data_s.reason = cbReadOnlySynch; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = readonly_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; vpi_register_cb(&cb_data_s); // register delta callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 1; cb_data_s.reason = cbAfterDelay; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = delta_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; vpi_register_cb(&cb_data_s); return(0); } static PLI_INT32 change_callback(p_cb_data cb_data) { int *id; // vpi_printf("change callback"); id = (int *)cb_data->user_data; changeFlag[*id] = 1; return(0); } void myhdl_register() { s_vpi_systf_data tf_data; tf_data.type = vpiSysTask; tf_data.tfname = "$to_myhdl"; tf_data.calltf = (void *) to_myhdl_calltf; tf_data.compiletf = NULL; tf_data.sizetf = NULL; tf_data.user_data = "$to_myhdl"; vpi_register_systf(&tf_data); tf_data.type = vpiSysTask; tf_data.tfname = "$from_myhdl"; tf_data.calltf = (void *) from_myhdl_calltf; tf_data.compiletf = NULL; tf_data.sizetf = NULL; tf_data.user_data = "$from_myhdl"; vpi_register_systf(&tf_data); } myhdl-0.11/cosimulation/icarus/myhdl.c.20030518000066400000000000000000000267651347432460400207550ustar00rootroot00000000000000#include #include #include #include "vpi_user.h" #include #define MAXLINE 4096 #define MAXWIDTH 10 #define MAXARGS 64 // #define DEBUG 1 /* Sized variables */ #ifndef PLI_TYPES #define PLI_TYPES typedef int PLI_INT32; typedef unsigned int PLI_UINT32; typedef short PLI_INT16; typedef unsigned short PLI_UINT16; typedef char PLI_BYTE8; typedef unsigned char PLI_UBYTE8; #endif /* 64 bit type for time calculations */ typedef unsigned long long myhdl_time64_t; static int rpipe; static int wpipe; static vpiHandle from_myhdl_systf_handle = NULL; static vpiHandle to_myhdl_systf_handle = NULL; static char changeFlag[MAXARGS]; static char bufcp[MAXLINE]; static myhdl_time64_t myhdl_time; static myhdl_time64_t verilog_time; static myhdl_time64_t pli_time; static myhdl_time64_t delay; static int delta; /* prototypes */ static PLI_INT32 from_myhdl_calltf(PLI_BYTE8 *user_data); static PLI_INT32 to_myhdl_calltf(PLI_BYTE8 *user_data); static PLI_INT32 readonly_callback(p_cb_data cb_data); static PLI_INT32 delay_callback(p_cb_data cb_data); static PLI_INT32 delta_callback(p_cb_data cb_data); static PLI_INT32 change_callback(p_cb_data cb_data); static int init_pipes(); static myhdl_time64_t timestruct_to_time(const struct t_vpi_time*ts); /* from Icarus */ static myhdl_time64_t timestruct_to_time(const struct t_vpi_time*ts) { myhdl_time64_t ti = ts->high; ti <<= 32; ti += ts->low & 0xffffffff; return ti; } static int init_pipes() { char *w; char *r; static int init_pipes_flag = 0; if (init_pipes_flag) { return(0); } if ((w = getenv("MYHDL_TO_PIPE")) == NULL) { vpi_printf("ERROR: no write pipe to myhdl\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } if ((r = getenv("MYHDL_FROM_PIPE")) == NULL) { vpi_printf("ERROR: no read pipe from myhdl\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } wpipe = atoi(w); rpipe = atoi(r); init_pipes_flag = 1; return (0); } static PLI_INT32 from_myhdl_calltf(PLI_BYTE8 *user_data) { vpiHandle reg_iter, reg_handle; s_vpi_time verilog_time_s; char buf[MAXLINE]; char s[MAXWIDTH]; int n; static int from_myhdl_flag = 0; if (from_myhdl_flag) { vpi_printf("ERROR: $from_myhdl called more than once\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } from_myhdl_flag = 1; init_pipes(); verilog_time_s.type = vpiSimTime; vpi_get_time(NULL, &verilog_time_s); verilog_time = timestruct_to_time(&verilog_time_s); if (verilog_time != 0) { vpi_printf("ERROR: $from_myhdl should be called at time 0\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } sprintf(buf, "FROM 0 "); pli_time = 0; delta = 0; from_myhdl_systf_handle = vpi_handle(vpiSysTfCall, NULL); reg_iter = vpi_iterate(vpiArgument, from_myhdl_systf_handle); while ((reg_handle = vpi_scan(reg_iter)) != NULL) { if (vpi_get(vpiType, reg_handle) != vpiReg) { vpi_printf("ERROR: $from_myhdl argument %s should be a reg\n", vpi_get_str(vpiName, reg_handle)); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } strcat(buf, vpi_get_str(vpiName, reg_handle)); strcat(buf, " "); sprintf(s, "%d ", vpi_get(vpiSize, reg_handle)); strcat(buf, s); } n = write(wpipe, buf, strlen(buf)); if ((n = read(rpipe, buf, MAXLINE)) == 0) { vpi_printf("Info: MyHDL simulator down\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } assert(n > 0); buf[n] = '\0'; return(0); } static PLI_INT32 to_myhdl_calltf(PLI_BYTE8 *user_data) { vpiHandle net_iter, net_handle; char buf[MAXLINE]; char s[MAXWIDTH]; int n; int i; int *id; s_cb_data cb_data_s; s_vpi_time verilog_time_s; s_vpi_time time_s; s_vpi_value value_s; static int to_myhdl_flag = 0; if (to_myhdl_flag) { vpi_printf("ERROR: $to_myhdl called more than once\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } to_myhdl_flag = 1; init_pipes(); verilog_time_s.type = vpiSimTime; vpi_get_time(NULL, &verilog_time_s); verilog_time = timestruct_to_time(&verilog_time_s); if (verilog_time != 0) { vpi_printf("ERROR: $to_myhdl should be called at time 0\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } sprintf(buf, "TO 0 "); pli_time = 0; delta = 0; time_s.type = vpiSuppressTime; cb_data_s.reason = cbValueChange; cb_data_s.cb_rtn = change_callback; cb_data_s.time = &time_s; cb_data_s.value = NULL; // value_s.format = vpiHexStrVal; i = 0; to_myhdl_systf_handle = vpi_handle(vpiSysTfCall, NULL); net_iter = vpi_iterate(vpiArgument, to_myhdl_systf_handle); while ((net_handle = vpi_scan(net_iter)) != NULL) { if (i == MAXARGS) { vpi_printf("ERROR: $to_myhdl max #args (%d) exceeded\n", MAXARGS); vpi_control(vpiFinish, 1); /* abort simulation */ } strcat(buf, vpi_get_str(vpiName, net_handle)); strcat(buf, " "); sprintf(s, "%d ", vpi_get(vpiSize, net_handle)); strcat(buf, s); changeFlag[i] = 0; id = malloc(sizeof(int)); *id = i; cb_data_s.user_data = (PLI_BYTE8 *)id; cb_data_s.obj = net_handle; vpi_register_cb(&cb_data_s); i++; } n = write(wpipe, buf, strlen(buf)); if ((n = read(rpipe, buf, MAXLINE)) == 0) { vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } buf[n] = '\0'; assert(n > 0); // register read-only callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 0; cb_data_s.reason = cbReadOnlySynch; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = readonly_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; vpi_register_cb(&cb_data_s); // pre-register delta cycle callback // delta = 0; time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 1; cb_data_s.reason = cbAfterDelay; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = delta_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; vpi_register_cb(&cb_data_s); return(0); } static PLI_INT32 readonly_callback(p_cb_data cb_data) { vpiHandle systf_handle; vpiHandle net_iter, net_handle; vpiHandle reg_iter, reg_handle; s_cb_data cb_data_s; s_vpi_time verilog_time_s; s_vpi_value value_s; s_vpi_time time_s; char buf[MAXLINE]; int n; int i; char *myhdl_time_string; myhdl_time64_t delay; static int start_flag = 1; if (start_flag) { start_flag = 0; n = write(wpipe, "START", 5); if ((n = read(rpipe, buf, MAXLINE)) == 0) { vpi_control(vpiFinish, 1); /* abort simulation */ } assert(n > 0); } buf[0] = '\0'; verilog_time_s.type = vpiSimTime; vpi_get_time(NULL, &verilog_time_s); verilog_time = timestruct_to_time(&verilog_time_s); /* if (verilog_time != (pli_time * 1000 + delta)) { */ /* vpi_printf("%u %u\n", verilog_time_s.high, verilog_time_s.low ); */ /* vpi_printf("%llu %llu %d", verilog_time, pli_time, delta); */ /* } */ /* Icarus 0.7 fails on this assertion beyond 32 bits due to a bug */ // assert(verilog_time == pli_time * 1000 + delta); assert( (verilog_time & 0xFFFFFFFF) == ( (pli_time * 1000 + delta) & 0xFFFFFFFF ) ); sprintf(buf, "%llu ", pli_time); net_iter = vpi_iterate(vpiArgument, to_myhdl_systf_handle); value_s.format = vpiHexStrVal; i = 0; while ((net_handle = vpi_scan(net_iter)) != NULL) { if (changeFlag[i]) { strcat(buf, vpi_get_str(vpiName, net_handle)); strcat(buf, " "); vpi_get_value(net_handle, &value_s); strcat(buf, value_s.value.str); strcat(buf, " "); changeFlag[i] = 0; } i++; } n = write(wpipe, buf, strlen(buf)); if ((n = read(rpipe, buf, MAXLINE)) == 0) { vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } assert(n > 0); buf[n] = '\0'; /* save copy for later callback */ strcpy(bufcp, buf); myhdl_time_string = strtok(buf, " "); myhdl_time = (myhdl_time64_t) strtoull(myhdl_time_string, (char **) NULL, 10); delay = (myhdl_time - pli_time) * 1000; assert(delay >= 0); assert(delay <= 0xFFFFFFFF); if (delay > 0) { // schedule cbAfterDelay callback assert(delay > delta); delay -= delta; /* Icarus runs RO callbacks when time has already advanced */ /* Therefore, compensate for the prescheduled delta callback */ delay -= 1; delta = 0; pli_time = myhdl_time; // register cbAfterDelay callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = (PLI_UINT32) delay; cb_data_s.reason = cbAfterDelay; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = delay_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; vpi_register_cb(&cb_data_s); } else { delta++; assert(delta < 1000); } return(0); } static PLI_INT32 delay_callback(p_cb_data cb_data) { s_vpi_time time_s; s_cb_data cb_data_s; // register readonly callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 0; cb_data_s.reason = cbReadOnlySynch; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = readonly_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; vpi_register_cb(&cb_data_s); // register delta callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 1; cb_data_s.reason = cbAfterDelay; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = delta_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; vpi_register_cb(&cb_data_s); return(0); } static PLI_INT32 delta_callback(p_cb_data cb_data) { s_cb_data cb_data_s; s_vpi_time time_s; vpiHandle systf_handle; vpiHandle reg_iter, reg_handle; s_vpi_value value_s; if (delta == 0) { return(0); } /* skip time value */ strtok(bufcp, " "); reg_iter = vpi_iterate(vpiArgument, from_myhdl_systf_handle); value_s.format = vpiHexStrVal; while ((value_s.value.str = strtok(NULL, " ")) != NULL) { reg_handle = vpi_scan(reg_iter); vpi_put_value(reg_handle, &value_s, NULL, vpiNoDelay); } if (reg_iter != NULL) { vpi_free_object(reg_iter); } // register readonly callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 0; cb_data_s.reason = cbReadOnlySynch; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = readonly_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; vpi_register_cb(&cb_data_s); // register delta callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 1; cb_data_s.reason = cbAfterDelay; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = delta_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; vpi_register_cb(&cb_data_s); return(0); } static PLI_INT32 change_callback(p_cb_data cb_data) { s_cb_data cb_data_s; s_vpi_time time_s; s_vpi_time verilog_time; vpiHandle systf_handle; int *id; id = (int *)cb_data->user_data; changeFlag[*id] = 1; } void myhdl_register() { s_vpi_systf_data tf_data; tf_data.type = vpiSysTask; tf_data.tfname = "$to_myhdl"; tf_data.calltf = (void *) to_myhdl_calltf; tf_data.compiletf = NULL; tf_data.sizetf = NULL; tf_data.user_data = "$to_myhdl"; vpi_register_systf(&tf_data); tf_data.type = vpiSysTask; tf_data.tfname = "$from_myhdl"; tf_data.calltf = (void *) from_myhdl_calltf; tf_data.compiletf = NULL; tf_data.sizetf = NULL; tf_data.user_data = "$from_myhdl"; vpi_register_systf(&tf_data); } myhdl-0.11/cosimulation/icarus/myhdl_20030518.c000066400000000000000000000267651347432460400210360ustar00rootroot00000000000000#include #include #include #include "vpi_user.h" #include #define MAXLINE 4096 #define MAXWIDTH 10 #define MAXARGS 64 // #define DEBUG 1 /* Sized variables */ #ifndef PLI_TYPES #define PLI_TYPES typedef int PLI_INT32; typedef unsigned int PLI_UINT32; typedef short PLI_INT16; typedef unsigned short PLI_UINT16; typedef char PLI_BYTE8; typedef unsigned char PLI_UBYTE8; #endif /* 64 bit type for time calculations */ typedef unsigned long long myhdl_time64_t; static int rpipe; static int wpipe; static vpiHandle from_myhdl_systf_handle = NULL; static vpiHandle to_myhdl_systf_handle = NULL; static char changeFlag[MAXARGS]; static char bufcp[MAXLINE]; static myhdl_time64_t myhdl_time; static myhdl_time64_t verilog_time; static myhdl_time64_t pli_time; static myhdl_time64_t delay; static int delta; /* prototypes */ static PLI_INT32 from_myhdl_calltf(PLI_BYTE8 *user_data); static PLI_INT32 to_myhdl_calltf(PLI_BYTE8 *user_data); static PLI_INT32 readonly_callback(p_cb_data cb_data); static PLI_INT32 delay_callback(p_cb_data cb_data); static PLI_INT32 delta_callback(p_cb_data cb_data); static PLI_INT32 change_callback(p_cb_data cb_data); static int init_pipes(); static myhdl_time64_t timestruct_to_time(const struct t_vpi_time*ts); /* from Icarus */ static myhdl_time64_t timestruct_to_time(const struct t_vpi_time*ts) { myhdl_time64_t ti = ts->high; ti <<= 32; ti += ts->low & 0xffffffff; return ti; } static int init_pipes() { char *w; char *r; static int init_pipes_flag = 0; if (init_pipes_flag) { return(0); } if ((w = getenv("MYHDL_TO_PIPE")) == NULL) { vpi_printf("ERROR: no write pipe to myhdl\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } if ((r = getenv("MYHDL_FROM_PIPE")) == NULL) { vpi_printf("ERROR: no read pipe from myhdl\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } wpipe = atoi(w); rpipe = atoi(r); init_pipes_flag = 1; return (0); } static PLI_INT32 from_myhdl_calltf(PLI_BYTE8 *user_data) { vpiHandle reg_iter, reg_handle; s_vpi_time verilog_time_s; char buf[MAXLINE]; char s[MAXWIDTH]; int n; static int from_myhdl_flag = 0; if (from_myhdl_flag) { vpi_printf("ERROR: $from_myhdl called more than once\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } from_myhdl_flag = 1; init_pipes(); verilog_time_s.type = vpiSimTime; vpi_get_time(NULL, &verilog_time_s); verilog_time = timestruct_to_time(&verilog_time_s); if (verilog_time != 0) { vpi_printf("ERROR: $from_myhdl should be called at time 0\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } sprintf(buf, "FROM 0 "); pli_time = 0; delta = 0; from_myhdl_systf_handle = vpi_handle(vpiSysTfCall, NULL); reg_iter = vpi_iterate(vpiArgument, from_myhdl_systf_handle); while ((reg_handle = vpi_scan(reg_iter)) != NULL) { if (vpi_get(vpiType, reg_handle) != vpiReg) { vpi_printf("ERROR: $from_myhdl argument %s should be a reg\n", vpi_get_str(vpiName, reg_handle)); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } strcat(buf, vpi_get_str(vpiName, reg_handle)); strcat(buf, " "); sprintf(s, "%d ", vpi_get(vpiSize, reg_handle)); strcat(buf, s); } n = write(wpipe, buf, strlen(buf)); if ((n = read(rpipe, buf, MAXLINE)) == 0) { vpi_printf("Info: MyHDL simulator down\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } assert(n > 0); buf[n] = '\0'; return(0); } static PLI_INT32 to_myhdl_calltf(PLI_BYTE8 *user_data) { vpiHandle net_iter, net_handle; char buf[MAXLINE]; char s[MAXWIDTH]; int n; int i; int *id; s_cb_data cb_data_s; s_vpi_time verilog_time_s; s_vpi_time time_s; s_vpi_value value_s; static int to_myhdl_flag = 0; if (to_myhdl_flag) { vpi_printf("ERROR: $to_myhdl called more than once\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } to_myhdl_flag = 1; init_pipes(); verilog_time_s.type = vpiSimTime; vpi_get_time(NULL, &verilog_time_s); verilog_time = timestruct_to_time(&verilog_time_s); if (verilog_time != 0) { vpi_printf("ERROR: $to_myhdl should be called at time 0\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } sprintf(buf, "TO 0 "); pli_time = 0; delta = 0; time_s.type = vpiSuppressTime; cb_data_s.reason = cbValueChange; cb_data_s.cb_rtn = change_callback; cb_data_s.time = &time_s; cb_data_s.value = NULL; // value_s.format = vpiHexStrVal; i = 0; to_myhdl_systf_handle = vpi_handle(vpiSysTfCall, NULL); net_iter = vpi_iterate(vpiArgument, to_myhdl_systf_handle); while ((net_handle = vpi_scan(net_iter)) != NULL) { if (i == MAXARGS) { vpi_printf("ERROR: $to_myhdl max #args (%d) exceeded\n", MAXARGS); vpi_control(vpiFinish, 1); /* abort simulation */ } strcat(buf, vpi_get_str(vpiName, net_handle)); strcat(buf, " "); sprintf(s, "%d ", vpi_get(vpiSize, net_handle)); strcat(buf, s); changeFlag[i] = 0; id = malloc(sizeof(int)); *id = i; cb_data_s.user_data = (PLI_BYTE8 *)id; cb_data_s.obj = net_handle; vpi_register_cb(&cb_data_s); i++; } n = write(wpipe, buf, strlen(buf)); if ((n = read(rpipe, buf, MAXLINE)) == 0) { vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } buf[n] = '\0'; assert(n > 0); // register read-only callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 0; cb_data_s.reason = cbReadOnlySynch; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = readonly_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; vpi_register_cb(&cb_data_s); // pre-register delta cycle callback // delta = 0; time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 1; cb_data_s.reason = cbAfterDelay; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = delta_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; vpi_register_cb(&cb_data_s); return(0); } static PLI_INT32 readonly_callback(p_cb_data cb_data) { vpiHandle systf_handle; vpiHandle net_iter, net_handle; vpiHandle reg_iter, reg_handle; s_cb_data cb_data_s; s_vpi_time verilog_time_s; s_vpi_value value_s; s_vpi_time time_s; char buf[MAXLINE]; int n; int i; char *myhdl_time_string; myhdl_time64_t delay; static int start_flag = 1; if (start_flag) { start_flag = 0; n = write(wpipe, "START", 5); if ((n = read(rpipe, buf, MAXLINE)) == 0) { vpi_control(vpiFinish, 1); /* abort simulation */ } assert(n > 0); } buf[0] = '\0'; verilog_time_s.type = vpiSimTime; vpi_get_time(NULL, &verilog_time_s); verilog_time = timestruct_to_time(&verilog_time_s); /* if (verilog_time != (pli_time * 1000 + delta)) { */ /* vpi_printf("%u %u\n", verilog_time_s.high, verilog_time_s.low ); */ /* vpi_printf("%llu %llu %d", verilog_time, pli_time, delta); */ /* } */ /* Icarus 0.7 fails on this assertion beyond 32 bits due to a bug */ // assert(verilog_time == pli_time * 1000 + delta); assert( (verilog_time & 0xFFFFFFFF) == ( (pli_time * 1000 + delta) & 0xFFFFFFFF ) ); sprintf(buf, "%llu ", pli_time); net_iter = vpi_iterate(vpiArgument, to_myhdl_systf_handle); value_s.format = vpiHexStrVal; i = 0; while ((net_handle = vpi_scan(net_iter)) != NULL) { if (changeFlag[i]) { strcat(buf, vpi_get_str(vpiName, net_handle)); strcat(buf, " "); vpi_get_value(net_handle, &value_s); strcat(buf, value_s.value.str); strcat(buf, " "); changeFlag[i] = 0; } i++; } n = write(wpipe, buf, strlen(buf)); if ((n = read(rpipe, buf, MAXLINE)) == 0) { vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } assert(n > 0); buf[n] = '\0'; /* save copy for later callback */ strcpy(bufcp, buf); myhdl_time_string = strtok(buf, " "); myhdl_time = (myhdl_time64_t) strtoull(myhdl_time_string, (char **) NULL, 10); delay = (myhdl_time - pli_time) * 1000; assert(delay >= 0); assert(delay <= 0xFFFFFFFF); if (delay > 0) { // schedule cbAfterDelay callback assert(delay > delta); delay -= delta; /* Icarus runs RO callbacks when time has already advanced */ /* Therefore, compensate for the prescheduled delta callback */ delay -= 1; delta = 0; pli_time = myhdl_time; // register cbAfterDelay callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = (PLI_UINT32) delay; cb_data_s.reason = cbAfterDelay; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = delay_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; vpi_register_cb(&cb_data_s); } else { delta++; assert(delta < 1000); } return(0); } static PLI_INT32 delay_callback(p_cb_data cb_data) { s_vpi_time time_s; s_cb_data cb_data_s; // register readonly callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 0; cb_data_s.reason = cbReadOnlySynch; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = readonly_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; vpi_register_cb(&cb_data_s); // register delta callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 1; cb_data_s.reason = cbAfterDelay; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = delta_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; vpi_register_cb(&cb_data_s); return(0); } static PLI_INT32 delta_callback(p_cb_data cb_data) { s_cb_data cb_data_s; s_vpi_time time_s; vpiHandle systf_handle; vpiHandle reg_iter, reg_handle; s_vpi_value value_s; if (delta == 0) { return(0); } /* skip time value */ strtok(bufcp, " "); reg_iter = vpi_iterate(vpiArgument, from_myhdl_systf_handle); value_s.format = vpiHexStrVal; while ((value_s.value.str = strtok(NULL, " ")) != NULL) { reg_handle = vpi_scan(reg_iter); vpi_put_value(reg_handle, &value_s, NULL, vpiNoDelay); } if (reg_iter != NULL) { vpi_free_object(reg_iter); } // register readonly callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 0; cb_data_s.reason = cbReadOnlySynch; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = readonly_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; vpi_register_cb(&cb_data_s); // register delta callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 1; cb_data_s.reason = cbAfterDelay; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = delta_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; vpi_register_cb(&cb_data_s); return(0); } static PLI_INT32 change_callback(p_cb_data cb_data) { s_cb_data cb_data_s; s_vpi_time time_s; s_vpi_time verilog_time; vpiHandle systf_handle; int *id; id = (int *)cb_data->user_data; changeFlag[*id] = 1; } void myhdl_register() { s_vpi_systf_data tf_data; tf_data.type = vpiSysTask; tf_data.tfname = "$to_myhdl"; tf_data.calltf = (void *) to_myhdl_calltf; tf_data.compiletf = NULL; tf_data.sizetf = NULL; tf_data.user_data = "$to_myhdl"; vpi_register_systf(&tf_data); tf_data.type = vpiSysTask; tf_data.tfname = "$from_myhdl"; tf_data.calltf = (void *) from_myhdl_calltf; tf_data.compiletf = NULL; tf_data.sizetf = NULL; tf_data.user_data = "$from_myhdl"; vpi_register_systf(&tf_data); } myhdl-0.11/cosimulation/icarus/myhdl_table.c000066400000000000000000000001761347432460400212070ustar00rootroot00000000000000# include "vpi_user.h" extern void myhdl_register(); void (*vlog_startup_routines[])() = { myhdl_register, 0 }; myhdl-0.11/cosimulation/icarus/test/000077500000000000000000000000001347432460400175325ustar00rootroot00000000000000myhdl-0.11/cosimulation/icarus/test/bin2gray.py000066400000000000000000000005231347432460400216210ustar00rootroot00000000000000import os from myhdl import Cosimulation cmd = "iverilog -o bin2gray.o -Dwidth=%s " + \ "../../test/verilog/bin2gray.v " + \ "../../test/verilog/dut_bin2gray.v " def bin2gray(B, G): width = len(B) os.system(cmd % width) return Cosimulation("vvp -m ../myhdl.vpi bin2gray.o", B=B, G=G) myhdl-0.11/cosimulation/icarus/test/dff.py000066400000000000000000000004341347432460400206440ustar00rootroot00000000000000import os from myhdl import Cosimulation cmd = "iverilog -o dff.o " + \ "../../test/verilog/dff.v " + \ "../../test/verilog/dut_dff.v " def dff(q, d, clk, reset): os.system(cmd) return Cosimulation("vvp -m ../myhdl.vpi dff.o", **locals()) myhdl-0.11/cosimulation/icarus/test/dff_clkout.py000066400000000000000000000006401347432460400222240ustar00rootroot00000000000000import os import os.path as path from myhdl import Cosimulation cmd = "iverilog -o dff_clkout.o " + \ "../../test/verilog/dff_clkout.v " + \ "../../test/verilog/dut_dff_clkout.v " def dff_clkout(clkout, q, d, clk, reset): if path.exists("dff_clkout"): os.remove("dff_clkout") os.system(cmd) return Cosimulation("vvp -m ../myhdl.vpi dff_clkout.o", **locals()) myhdl-0.11/cosimulation/icarus/test/inc.py000066400000000000000000000004651347432460400206620ustar00rootroot00000000000000import os from myhdl import Cosimulation cmd = "iverilog -o inc.o -Dn=%s " + \ "../../test/verilog/inc.v " + \ "../../test/verilog/dut_inc.v " def inc(count, enable, clock, reset, n): os.system(cmd % n) return Cosimulation("vvp -m ../myhdl.vpi inc.o", **locals()) myhdl-0.11/cosimulation/icarus/test/tb_test.v000066400000000000000000000006121347432460400213640ustar00rootroot00000000000000module tb; reg [16:0] a; reg [4:0] b; reg [9:0] c; reg clk; initial begin $to_myhdl(c); $from_myhdl(a, b); end always @ (a, b) begin c = a + b; $display("Verilog: %d c =%d a=%d b=%d", $time, c, a, b); end initial begin clk = 0; forever begin clk = #50 ~clk; end end endmodule // tb myhdl-0.11/cosimulation/icarus/test/test.py000066400000000000000000000013141347432460400210620ustar00rootroot00000000000000from __future__ import generators from __future__ import print_function from myhdl import Signal, Simulation, Cosimulation from myhdl import delay, intbv, now import os cmd = "iverilog -o tb_test.o ./tb_test.v " os.system(cmd) a = Signal(intbv(1)) b = Signal(intbv(2)) c = Signal(intbv(3)) cosim = Cosimulation("vvp -v -m ../myhdl.vpi tb_test.o", a=a, b=b, c=c) def stimulus(a, b): for i in range(10): yield delay(10) # print "Python a=%s b=%s" % (a, b) a.next = a + 1 b.next = b + 2 def response(c): while 1: yield c print("Python: %s %s %s %s" % (now(), c, a, b)) sim = Simulation(stimulus(a=a, b=b), response(c=c), cosim) sim.run() myhdl-0.11/cosimulation/icarus/test/test_all.py000066400000000000000000000027611347432460400217210ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run cosimulation unit tests. """ import sys sys.path.append("../../test") sys.path.append("../../../example/manual") import test_gray_properties, test_gray_original, test_inc, test_dff modules = (test_gray_properties, test_gray_original, test_inc, test_dff ) import unittest tl = unittest.defaultTestLoader def suite(): alltests = unittest.TestSuite() for m in modules: alltests.addTest(tl.loadTestsFromModule(m)) return alltests def main(): unittest.main(defaultTest='suite', testRunner=unittest.TextTestRunner(verbosity=2)) if __name__ == '__main__': main() myhdl-0.11/cosimulation/icarus/test/test_gray.py000066400000000000000000000026521347432460400221120ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run cosimulation unit tests. """ import sys sys.path.append("../../../example/manual") import test_gray_properties, test_gray_original modules = (test_gray_properties, test_gray_original) import unittest tl = unittest.defaultTestLoader def suite(): alltests = unittest.TestSuite() for m in modules: alltests.addTest(tl.loadTestsFromModule(m)) return alltests def main(): unittest.main(defaultTest='suite', testRunner=unittest.TextTestRunner(verbosity=2)) if __name__ == '__main__': main() myhdl-0.11/cosimulation/modelsim-win/000077500000000000000000000000001347432460400176715ustar00rootroot00000000000000myhdl-0.11/cosimulation/modelsim-win/Makefile000066400000000000000000000011561347432460400213340ustar00rootroot00000000000000INCS := C:\\modeltech64_10.4\\include LIB_PATH := C:\\modeltech64_10.4\\win64 ifneq ($(filter cl%,$(CC)),) CFLAGS := /LD /I$(INCS) LIBFLAGS := $(LIB_PATH)\\mtipli.lib else CFLAGS := -static -g -I$(INCS) -o myhdl_vpi.dll LIBFLAGS := -L$(LIB_PATH) -lmtipli endif all: myhdl_vpi.dll myhdl_vpi.dll: myhdl_vpi.c $(CC) $(CFLAGS) $< $(LIBFLAGS) clean: @del /q myhdl_vpi.dll || rm -rf myhdl_vpi.dll 2>&1> /dev/null ||: @del /q myhdl_vpi.lib || rm -rf myhdl_vpi.lib 2>&1> /dev/null ||: @del /q myhdl_vpi.exp || rm -rf myhdl_vpi.exp 2>&1> /dev/null ||: @del /q myhdl_vpi.obj || rm -rf myhdl_vpi.obj 2>&1> /dev/null ||: myhdl-0.11/cosimulation/modelsim-win/myhdl_vpi.c000066400000000000000000000322401347432460400220310ustar00rootroot00000000000000 #include #include #include #include #include #include "vpi_user.h" #include "sv_vpi_user.h" #define MAXLINE 4096 #define MAXWIDTH 10 #define MAXARGS 64 // #define DEBUG 1 /* Sized variables */ #ifndef PLI_TYPES #define PLI_TYPES typedef int PLI_INT32; typedef unsigned int PLI_UINT32; typedef short PLI_INT16; typedef unsigned short PLI_UINT16; typedef char PLI_BYTE8; typedef unsigned char PLI_UBYTE8; #endif /* 64 bit type for time calculations */ typedef unsigned long long myhdl_time64_t; static HANDLE rpipe; static HANDLE wpipe; static vpiHandle from_myhdl_systf_handle = NULL; static vpiHandle to_myhdl_systf_handle = NULL; static char changeFlag[MAXARGS]; static char bufcp[MAXLINE]; static myhdl_time64_t myhdl_time; static myhdl_time64_t verilog_time; static myhdl_time64_t pli_time; static int delta; /* prototypes */ static PLI_INT32 from_myhdl_calltf(PLI_BYTE8 *user_data); static PLI_INT32 to_myhdl_calltf(PLI_BYTE8 *user_data); static PLI_INT32 readonly_callback(p_cb_data cb_data); static PLI_INT32 delay_callback(p_cb_data cb_data); static PLI_INT32 delta_callback(p_cb_data cb_data); static PLI_INT32 change_callback(p_cb_data cb_data); static int init_pipes(); static myhdl_time64_t timestruct_to_time(const struct t_vpi_time*ts); /* from Icarus */ static myhdl_time64_t timestruct_to_time(const struct t_vpi_time*ts) { myhdl_time64_t ti = ts->high; ti <<= 32; ti += ts->low & 0xffffffff; return ti; } static int read_pipe(void *buf, size_t count) { DWORD read; if (!ReadFile(rpipe, buf, (DWORD)count, &read, NULL)) { return -1; } return (int)read; } static int write_pipe(const void *buf, size_t count) { DWORD written; if (!WriteFile(wpipe, buf, (DWORD)count, &written, NULL)) { return -1; } return (int)written; } static int init_pipes() { char *w; char *r; static int init_pipes_flag = 0; if (init_pipes_flag) { return(0); } if ((w = getenv("MYHDL_TO_PIPE")) == NULL) { vpi_printf("ERROR: no write pipe to myhdl\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } if ((r = getenv("MYHDL_FROM_PIPE")) == NULL) { vpi_printf("ERROR: no read pipe from myhdl\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } wpipe = (HANDLE)atoi(w); rpipe = (HANDLE)atoi(r); init_pipes_flag = 1; return (0); } static PLI_INT32 from_myhdl_calltf(PLI_BYTE8 *user_data) { vpiHandle reg_iter, reg_handle; s_vpi_time verilog_time_s; char buf[MAXLINE]; char s[MAXWIDTH]; int n; static int from_myhdl_flag = 0; if (from_myhdl_flag) { vpi_printf("ERROR: $from_myhdl called more than once\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } from_myhdl_flag = 1; init_pipes(); verilog_time_s.type = vpiSimTime; vpi_get_time(NULL, &verilog_time_s); verilog_time = timestruct_to_time(&verilog_time_s); if (verilog_time != 0) { vpi_printf("ERROR: $from_myhdl should be called at time 0\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } sprintf(buf, "FROM 0 "); pli_time = 0; delta = 0; from_myhdl_systf_handle = vpi_handle(vpiSysTfCall, NULL); reg_iter = vpi_iterate(vpiArgument, from_myhdl_systf_handle); while ((reg_handle = vpi_scan(reg_iter)) != NULL) { if (vpi_get(vpiType, reg_handle) != vpiReg) { vpi_printf("ERROR: $from_myhdl argument %s should be a reg\n", vpi_get_str(vpiName, reg_handle)); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } strcat(buf, vpi_get_str(vpiName, reg_handle)); strcat(buf, " "); sprintf(s, "%d ", vpi_get(vpiSize, reg_handle)); strcat(buf, s); vpi_free_object(reg_handle); } //vpi_free_object(reg_iter); n = write_pipe(buf, strlen(buf)); if ((n = read_pipe(buf, MAXLINE)) <= 0) { vpi_printf("Info: MyHDL simulator down\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } assert(n > 0); buf[n] = '\0'; return(0); } static PLI_INT32 to_myhdl_calltf(PLI_BYTE8 *user_data) { vpiHandle net_iter, net_handle, cb_h; char buf[MAXLINE]; char s[MAXWIDTH]; int n; int i; int *id; s_cb_data cb_data_s; s_vpi_time verilog_time_s; s_vpi_time time_s; s_vpi_value value_s; static int to_myhdl_flag = 0; if (to_myhdl_flag) { vpi_printf("ERROR: $to_myhdl called more than once\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } to_myhdl_flag = 1; init_pipes(); verilog_time_s.type = vpiSimTime; vpi_get_time(NULL, &verilog_time_s); verilog_time = timestruct_to_time(&verilog_time_s); if (verilog_time != 0) { vpi_printf("ERROR: $to_myhdl should be called at time 0\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } sprintf(buf, "TO 0 "); pli_time = 0; delta = 0; time_s.type = vpiSuppressTime; value_s.format = vpiSuppressVal; cb_data_s.reason = cbValueChange; cb_data_s.cb_rtn = change_callback; cb_data_s.time = &time_s; cb_data_s.value = &value_s; // value_s.format = vpiHexStrVal; i = 0; to_myhdl_systf_handle = vpi_handle(vpiSysTfCall, NULL); net_iter = vpi_iterate(vpiArgument, to_myhdl_systf_handle); while ((net_handle = vpi_scan(net_iter)) != NULL) { if (i == MAXARGS) { vpi_printf("ERROR: $to_myhdl max #args (%d) exceeded\n", MAXARGS); vpi_control(vpiFinish, 1); /* abort simulation */ } strcat(buf, vpi_get_str(vpiName, net_handle)); strcat(buf, " "); sprintf(s, "%d ", vpi_get(vpiSize, net_handle)); strcat(buf, s); changeFlag[i] = 0; id = malloc(sizeof(int)); *id = i; cb_data_s.user_data = (PLI_BYTE8 *)id; cb_data_s.obj = net_handle; cb_h = vpi_register_cb(&cb_data_s); vpi_free_object(cb_h); i++; vpi_free_object(net_handle); } //vpi_free_object(net_iter); n = write_pipe(buf, strlen(buf)); if ((n = read_pipe(buf, MAXLINE)) <= 0) { vpi_printf("ABORT from $to_myhdl\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } buf[n] = '\0'; assert(n > 0); // register read-only callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 0; cb_data_s.reason = cbReadOnlySynch; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = readonly_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; cb_h = vpi_register_cb(&cb_data_s); vpi_free_object(cb_h); // pre-register delta cycle callback // delta = 0; time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 1; cb_data_s.reason = cbAfterDelay; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = delta_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; cb_h = vpi_register_cb(&cb_data_s); vpi_free_object(cb_h); return(0); } static PLI_INT32 readonly_callback(p_cb_data cb_data) { vpiHandle net_iter, net_handle, cb_h; s_cb_data cb_data_s; s_vpi_time verilog_time_s; s_vpi_value value_s; s_vpi_time time_s; char buf[MAXLINE]; int n; int i; char *myhdl_time_string; myhdl_time64_t delay; static int start_flag = 1; if (start_flag) { start_flag = 0; n = write_pipe("START", 5); // vpi_printf("INFO: RO cb at start-up\n"); if ((n = read_pipe(buf, MAXLINE)) <= 0) { vpi_printf("ABORT from RO cb at start-up\n"); vpi_control(vpiFinish, 1); /* abort simulation */ } assert(n > 0); } buf[0] = '\0'; verilog_time_s.type = vpiSimTime; vpi_get_time(NULL, &verilog_time_s); verilog_time = timestruct_to_time(&verilog_time_s); if (verilog_time != (pli_time * 1000 + delta)) { vpi_printf("%u %u\n", verilog_time_s.high, verilog_time_s.low ); vpi_printf("%llu %llu %d\n", verilog_time, pli_time, delta); } /* Icarus 0.7 fails on this assertion beyond 32 bits due to a bug */ // assert(verilog_time == pli_time * 1000 + delta); assert( (verilog_time & 0xFFFFFFFF) == ( (pli_time * 1000 + delta) & 0xFFFFFFFF ) ); sprintf(buf, "%llu ", pli_time); net_iter = vpi_iterate(vpiArgument, to_myhdl_systf_handle); value_s.format = vpiHexStrVal; i = 0; while ((net_handle = vpi_scan(net_iter)) != NULL) { if (changeFlag[i]) { strcat(buf, vpi_get_str(vpiName, net_handle)); strcat(buf, " "); vpi_get_value(net_handle, &value_s); strcat(buf, value_s.value.str); strcat(buf, " "); changeFlag[i] = 0; } i++; vpi_free_object(net_handle); // done with this one } //vpi_free_object(net_iter); n = write_pipe(buf, strlen(buf)); if ((n = read_pipe(buf, MAXLINE)) <= 0) { // vpi_printf("ABORT from RO cb\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } assert(n > 0); buf[n] = '\0'; /* save copy for later callback */ strcpy(bufcp, buf); myhdl_time_string = strtok(buf, " "); myhdl_time = (myhdl_time64_t) strtoull(myhdl_time_string, (char **) NULL, 10); delay = (myhdl_time - pli_time) * 1000; assert(delay >= 0); assert(delay <= 0xFFFFFFFF); if (delay > 0) { // schedule cbAfterDelay callback assert(delay > delta); delay -= delta; /* Icarus 20030518 runs RO callbacks when time has already advanced */ /* Therefore, one had to compensate for the prescheduled delta callback */ /* delay -= 1; */ /* Icarus 20031009 has a different scheduler, more correct I believe */ /* compensation is no longer necessary */ delta = 0; pli_time = myhdl_time; // register cbAfterDelay callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = (PLI_UINT32) delay; cb_data_s.reason = cbAfterDelay; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = delay_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; cb_h = vpi_register_cb(&cb_data_s); vpi_free_object(cb_h); } else { delta++; assert(delta < 1000); } return(0); } static PLI_INT32 delay_callback(p_cb_data cb_data) { s_vpi_time time_s; s_cb_data cb_data_s; vpiHandle cb_h; // register readonly callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 0; cb_data_s.reason = cbReadOnlySynch; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = readonly_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; cb_h = vpi_register_cb(&cb_data_s); vpi_free_object(cb_h); // register delta callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 1; cb_data_s.reason = cbAfterDelay; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = delta_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; cb_h = vpi_register_cb(&cb_data_s); vpi_free_object(cb_h); return(0); } static PLI_INT32 delta_callback(p_cb_data cb_data) { s_cb_data cb_data_s; s_vpi_time time_s; vpiHandle reg_iter, reg_handle, cb_h; s_vpi_value value_s; if (delta == 0) { return(0); } /* skip time value */ strtok(bufcp, " "); reg_iter = vpi_iterate(vpiArgument, from_myhdl_systf_handle); value_s.format = vpiHexStrVal; while ((value_s.value.str = strtok(NULL, " ")) != NULL) { reg_handle = vpi_scan(reg_iter); vpi_put_value(reg_handle, &value_s, NULL, vpiNoDelay); vpi_free_object(reg_handle); } if (reg_iter != NULL) { vpi_free_object(reg_iter); } // register readonly callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 0; cb_data_s.reason = cbReadOnlySynch; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = readonly_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; cb_h = vpi_register_cb(&cb_data_s); vpi_free_object(cb_h); // register delta callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 1; cb_data_s.reason = cbAfterDelay; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = delta_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; cb_h = vpi_register_cb(&cb_data_s); vpi_free_object(cb_h); return(0); } static PLI_INT32 change_callback(p_cb_data cb_data) { int *id; // vpi_printf("change callback"); id = (int *)cb_data->user_data; changeFlag[*id] = 1; return(0); } __declspec(dllexport) void myhdl_register() { s_vpi_systf_data tf_data; tf_data.type = vpiSysTask; tf_data.tfname = "$to_myhdl"; tf_data.calltf = (void *) to_myhdl_calltf; tf_data.compiletf = NULL; tf_data.sizetf = NULL; tf_data.user_data = "$to_myhdl"; vpi_register_systf(&tf_data); //vpi_free_object(tf_data); // @mod cfelton tf_data.type = vpiSysTask; tf_data.tfname = "$from_myhdl"; tf_data.calltf = (void *) from_myhdl_calltf; tf_data.compiletf = NULL; tf_data.sizetf = NULL; tf_data.user_data = "$from_myhdl"; vpi_register_systf(&tf_data); //vpi_free_object(tf_data); // @mod cfelton } __declspec(dllexport) void (*vlog_startup_routines[])() = { myhdl_register, 0 }; /* dummy +loadvpi= boostrap routine - mimics old style exec all routines */ /* in standard PLI vlog_startup_routines table */ __declspec(dllexport) void vpi_compat_bootstrap(void) { int i; for (i = 0;; i++) { if (vlog_startup_routines[i] == NULL) break; vlog_startup_routines[i](); } } myhdl-0.11/cosimulation/modelsim-win/test/000077500000000000000000000000001347432460400206505ustar00rootroot00000000000000myhdl-0.11/cosimulation/modelsim-win/test/bin2gray.py000066400000000000000000000005461347432460400227440ustar00rootroot00000000000000import os from myhdl import Cosimulation cmd = 'vsim -c -quiet -pli ../myhdl_vpi.dll -do cosim.do dut_bin2gray' def bin2gray(B, G, width): os.system('vlog -quiet +define+width=%s ../../test/verilog/bin2gray.v' % (width)) os.system('vlog -quiet +define+width=%s ../../test/verilog/dut_bin2gray.v' % (width)) return Cosimulation(cmd, B=B, G=G) myhdl-0.11/cosimulation/modelsim-win/test/cosim.do000066400000000000000000000000161347432460400223030ustar00rootroot00000000000000run -all quit myhdl-0.11/cosimulation/modelsim-win/test/dff.py000066400000000000000000000004431347432460400217620ustar00rootroot00000000000000import os from myhdl import Cosimulation cmd = 'vsim -c -quiet -pli ../myhdl_vpi.dll -do cosim.do dut_dff' def dff(q, d, clk, reset): os.system('vlog -quiet ../../test/verilog/dff.v') os.system('vlog -quiet ../../test/verilog/dut_dff.v') return Cosimulation(cmd, **locals()) myhdl-0.11/cosimulation/modelsim-win/test/dff_clkout.py000066400000000000000000000005071347432460400233440ustar00rootroot00000000000000import os from myhdl import Cosimulation cmd = 'vsim -c -quiet -pli ../myhdl_vpi.dll -do cosim.do dut_dff_clkout' def dff_clkout(clkout, q, d, clk, reset): os.system('vlog -quiet ../../test/verilog/dff_clkout.v') os.system('vlog -quiet ../../test/verilog/dut_dff_clkout.v') return Cosimulation(cmd, **locals()) myhdl-0.11/cosimulation/modelsim-win/test/inc.py000066400000000000000000000005271347432460400217770ustar00rootroot00000000000000import os from myhdl import Cosimulation cmd = 'vsim -c -quiet -pli ../myhdl_vpi.dll -do cosim.do dut_inc' def inc(count, enable, clock, reset, n): os.system('vlog -quiet +define+n=%s ../../test/verilog/inc.v' % (n)) os.system('vlog -quiet +define+n=%s ../../test/verilog/dut_inc.v' % (n)) return Cosimulation(cmd, **locals()) myhdl-0.11/cosimulation/modelsim-win/test/test_all.py000066400000000000000000000026461347432460400230410ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run cosimulation unit tests. """ import sys sys.path.append("../../test") import test_bin2gray, test_inc, test_dff # modules = (test_dff, ) modules = (test_bin2gray, test_inc, test_dff ) import unittest tl = unittest.defaultTestLoader def suite(): alltests = unittest.TestSuite() for m in modules: alltests.addTest(tl.loadTestsFromModule(m)) return alltests def main(): unittest.main(defaultTest='suite', testRunner=unittest.TextTestRunner(verbosity=2)) if __name__ == '__main__': main() myhdl-0.11/cosimulation/modelsim/000077500000000000000000000000001347432460400170765ustar00rootroot00000000000000myhdl-0.11/cosimulation/modelsim/Makefile000066400000000000000000000011771347432460400205440ustar00rootroot00000000000000# This makefile assumes that 32bit Modelsim is installed. # If you have a 64 bit version, run 'ARCH=64 make' ARCH?=32 CFLAGS_32= -m32 CFLAGS_64= -m64 # Guess include dir based on location of vsim INCS=-I $(shell dirname `which vsim`)/../include CFLAGS= -Wall -shared -BSymbolic -fPIC $(CFLAGS_$(ARCH)) $(INCS) VSIM_VERSION=$(shell vsim -version 2>/dev/null; echo $$?) all: myhdl_vpi.so myhdl_vpi.so: myhdl_vpi.c $(info Compiling $(ARCH)bit vpi lib for "$(VSIM_VERSION)") $(info ) $(CC) $(CFLAGS) -o $@ $? clean: @rm -f myhdl_vpi.so .PHONY: test test: myhdl_vpi.so rm -rf test/work cd test && vlib work && python test_all.py myhdl-0.11/cosimulation/modelsim/myhdl_vpi.c000066400000000000000000000313361347432460400212430ustar00rootroot00000000000000 #include #include #include #include #include #include "vpi_user.h" #include "sv_vpi_user.h" #define MAXLINE 4096 #define MAXWIDTH 10 #define MAXARGS 64 // #define DEBUG 1 /* Sized variables */ #ifndef PLI_TYPES #define PLI_TYPES typedef int PLI_INT32; typedef unsigned int PLI_UINT32; typedef short PLI_INT16; typedef unsigned short PLI_UINT16; typedef char PLI_BYTE8; typedef unsigned char PLI_UBYTE8; #endif /* 64 bit type for time calculations */ typedef unsigned long long myhdl_time64_t; static int rpipe; static int wpipe; static vpiHandle from_myhdl_systf_handle = NULL; static vpiHandle to_myhdl_systf_handle = NULL; static char changeFlag[MAXARGS]; static char bufcp[MAXLINE]; static myhdl_time64_t myhdl_time; static myhdl_time64_t verilog_time; static myhdl_time64_t pli_time; static int delta; /* prototypes */ static PLI_INT32 from_myhdl_calltf(PLI_BYTE8 *user_data); static PLI_INT32 to_myhdl_calltf(PLI_BYTE8 *user_data); static PLI_INT32 readonly_callback(p_cb_data cb_data); static PLI_INT32 delay_callback(p_cb_data cb_data); static PLI_INT32 delta_callback(p_cb_data cb_data); static PLI_INT32 change_callback(p_cb_data cb_data); static int init_pipes(); static myhdl_time64_t timestruct_to_time(const struct t_vpi_time*ts); /* from Icarus */ static myhdl_time64_t timestruct_to_time(const struct t_vpi_time*ts) { myhdl_time64_t ti = ts->high; ti <<= 32; ti += ts->low & 0xffffffff; return ti; } static int init_pipes() { char *w; char *r; static int init_pipes_flag = 0; if (init_pipes_flag) { return(0); } if ((w = getenv("MYHDL_TO_PIPE")) == NULL) { vpi_printf("ERROR: no write pipe to myhdl\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } if ((r = getenv("MYHDL_FROM_PIPE")) == NULL) { vpi_printf("ERROR: no read pipe from myhdl\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } wpipe = atoi(w); rpipe = atoi(r); init_pipes_flag = 1; return (0); } static PLI_INT32 from_myhdl_calltf(PLI_BYTE8 *user_data) { vpiHandle reg_iter, reg_handle; s_vpi_time verilog_time_s; char buf[MAXLINE]; char s[MAXWIDTH]; int n; static int from_myhdl_flag = 0; if (from_myhdl_flag) { vpi_printf("ERROR: $from_myhdl called more than once\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } from_myhdl_flag = 1; init_pipes(); verilog_time_s.type = vpiSimTime; vpi_get_time(NULL, &verilog_time_s); verilog_time = timestruct_to_time(&verilog_time_s); if (verilog_time != 0) { vpi_printf("ERROR: $from_myhdl should be called at time 0\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } sprintf(buf, "FROM 0 "); pli_time = 0; delta = 0; from_myhdl_systf_handle = vpi_handle(vpiSysTfCall, NULL); reg_iter = vpi_iterate(vpiArgument, from_myhdl_systf_handle); while ((reg_handle = vpi_scan(reg_iter)) != NULL) { if (vpi_get(vpiType, reg_handle) != vpiReg) { vpi_printf("ERROR: $from_myhdl argument %s should be a reg\n", vpi_get_str(vpiName, reg_handle)); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } strcat(buf, vpi_get_str(vpiName, reg_handle)); strcat(buf, " "); sprintf(s, "%d ", vpi_get(vpiSize, reg_handle)); strcat(buf, s); vpi_free_object(reg_handle); } //vpi_free_object(reg_iter); n = write(wpipe, buf, strlen(buf)); if ((n = read(rpipe, buf, MAXLINE)) == 0) { vpi_printf("Info: MyHDL simulator down\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } assert(n > 0); buf[n] = '\0'; return(0); } static PLI_INT32 to_myhdl_calltf(PLI_BYTE8 *user_data) { vpiHandle net_iter, net_handle, cb_h; char buf[MAXLINE]; char s[MAXWIDTH]; int n; int i; int *id; s_cb_data cb_data_s; s_vpi_time verilog_time_s; s_vpi_time time_s; s_vpi_value value_s; static int to_myhdl_flag = 0; if (to_myhdl_flag) { vpi_printf("ERROR: $to_myhdl called more than once\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } to_myhdl_flag = 1; init_pipes(); verilog_time_s.type = vpiSimTime; vpi_get_time(NULL, &verilog_time_s); verilog_time = timestruct_to_time(&verilog_time_s); if (verilog_time != 0) { vpi_printf("ERROR: $to_myhdl should be called at time 0\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } sprintf(buf, "TO 0 "); pli_time = 0; delta = 0; time_s.type = vpiSuppressTime; value_s.format = vpiSuppressVal; cb_data_s.reason = cbValueChange; cb_data_s.cb_rtn = change_callback; cb_data_s.time = &time_s; cb_data_s.value = &value_s; // value_s.format = vpiHexStrVal; i = 0; to_myhdl_systf_handle = vpi_handle(vpiSysTfCall, NULL); net_iter = vpi_iterate(vpiArgument, to_myhdl_systf_handle); while ((net_handle = vpi_scan(net_iter)) != NULL) { if (i == MAXARGS) { vpi_printf("ERROR: $to_myhdl max #args (%d) exceeded\n", MAXARGS); vpi_control(vpiFinish, 1); /* abort simulation */ } strcat(buf, vpi_get_str(vpiName, net_handle)); strcat(buf, " "); sprintf(s, "%d ", vpi_get(vpiSize, net_handle)); strcat(buf, s); changeFlag[i] = 0; id = malloc(sizeof(int)); *id = i; cb_data_s.user_data = (PLI_BYTE8 *)id; cb_data_s.obj = net_handle; cb_h = vpi_register_cb(&cb_data_s); vpi_free_object(cb_h); i++; vpi_free_object(net_handle); } //vpi_free_object(net_iter); n = write(wpipe, buf, strlen(buf)); if ((n = read(rpipe, buf, MAXLINE)) == 0) { vpi_printf("ABORT from $to_myhdl\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } buf[n] = '\0'; assert(n > 0); // register read-only callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 0; cb_data_s.reason = cbReadOnlySynch; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = readonly_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; cb_h = vpi_register_cb(&cb_data_s); vpi_free_object(cb_h); // pre-register delta cycle callback // delta = 0; time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 1; cb_data_s.reason = cbAfterDelay; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = delta_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; cb_h = vpi_register_cb(&cb_data_s); vpi_free_object(cb_h); return(0); } static PLI_INT32 readonly_callback(p_cb_data cb_data) { vpiHandle net_iter, net_handle, cb_h; s_cb_data cb_data_s; s_vpi_time verilog_time_s; s_vpi_value value_s; s_vpi_time time_s; char buf[MAXLINE]; int n; int i; char *myhdl_time_string; myhdl_time64_t delay; static int start_flag = 1; if (start_flag) { start_flag = 0; n = write(wpipe, "START", 5); // vpi_printf("INFO: RO cb at start-up\n"); if ((n = read(rpipe, buf, MAXLINE)) == 0) { vpi_printf("ABORT from RO cb at start-up\n"); vpi_control(vpiFinish, 1); /* abort simulation */ } assert(n > 0); } buf[0] = '\0'; verilog_time_s.type = vpiSimTime; vpi_get_time(NULL, &verilog_time_s); verilog_time = timestruct_to_time(&verilog_time_s); if (verilog_time != (pli_time * 1000 + delta)) { vpi_printf("%u %u\n", verilog_time_s.high, verilog_time_s.low ); vpi_printf("%llu %llu %d\n", verilog_time, pli_time, delta); } /* Icarus 0.7 fails on this assertion beyond 32 bits due to a bug */ // assert(verilog_time == pli_time * 1000 + delta); assert( (verilog_time & 0xFFFFFFFF) == ( (pli_time * 1000 + delta) & 0xFFFFFFFF ) ); sprintf(buf, "%llu ", pli_time); net_iter = vpi_iterate(vpiArgument, to_myhdl_systf_handle); value_s.format = vpiHexStrVal; i = 0; while ((net_handle = vpi_scan(net_iter)) != NULL) { if (changeFlag[i]) { strcat(buf, vpi_get_str(vpiName, net_handle)); strcat(buf, " "); vpi_get_value(net_handle, &value_s); strcat(buf, value_s.value.str); strcat(buf, " "); changeFlag[i] = 0; } i++; vpi_free_object(net_handle); // done with this one } //vpi_free_object(net_iter); n = write(wpipe, buf, strlen(buf)); if ((n = read(rpipe, buf, MAXLINE)) == 0) { // vpi_printf("ABORT from RO cb\n"); vpi_control(vpiFinish, 1); /* abort simulation */ return(0); } assert(n > 0); buf[n] = '\0'; /* save copy for later callback */ strcpy(bufcp, buf); myhdl_time_string = strtok(buf, " "); myhdl_time = (myhdl_time64_t) strtoull(myhdl_time_string, (char **) NULL, 10); delay = (myhdl_time - pli_time) * 1000; assert(delay >= 0); assert(delay <= 0xFFFFFFFF); if (delay > 0) { // schedule cbAfterDelay callback assert(delay > delta); delay -= delta; /* Icarus 20030518 runs RO callbacks when time has already advanced */ /* Therefore, one had to compensate for the prescheduled delta callback */ /* delay -= 1; */ /* Icarus 20031009 has a different scheduler, more correct I believe */ /* compensation is no longer necessary */ delta = 0; pli_time = myhdl_time; // register cbAfterDelay callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = (PLI_UINT32) delay; cb_data_s.reason = cbAfterDelay; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = delay_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; cb_h = vpi_register_cb(&cb_data_s); vpi_free_object(cb_h); } else { delta++; assert(delta < 1000); } return(0); } static PLI_INT32 delay_callback(p_cb_data cb_data) { s_vpi_time time_s; s_cb_data cb_data_s; vpiHandle cb_h; // register readonly callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 0; cb_data_s.reason = cbReadOnlySynch; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = readonly_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; cb_h = vpi_register_cb(&cb_data_s); vpi_free_object(cb_h); // register delta callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 1; cb_data_s.reason = cbAfterDelay; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = delta_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; cb_h = vpi_register_cb(&cb_data_s); vpi_free_object(cb_h); return(0); } static PLI_INT32 delta_callback(p_cb_data cb_data) { s_cb_data cb_data_s; s_vpi_time time_s; vpiHandle reg_iter, reg_handle, cb_h; s_vpi_value value_s; if (delta == 0) { return(0); } /* skip time value */ strtok(bufcp, " "); reg_iter = vpi_iterate(vpiArgument, from_myhdl_systf_handle); value_s.format = vpiHexStrVal; while ((value_s.value.str = strtok(NULL, " ")) != NULL) { reg_handle = vpi_scan(reg_iter); vpi_put_value(reg_handle, &value_s, NULL, vpiNoDelay); vpi_free_object(reg_handle); } if (reg_iter != NULL) { vpi_free_object(reg_iter); } // register readonly callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 0; cb_data_s.reason = cbReadOnlySynch; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = readonly_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; cb_h = vpi_register_cb(&cb_data_s); vpi_free_object(cb_h); // register delta callback // time_s.type = vpiSimTime; time_s.high = 0; time_s.low = 1; cb_data_s.reason = cbAfterDelay; cb_data_s.user_data = NULL; cb_data_s.cb_rtn = delta_callback; cb_data_s.obj = NULL; cb_data_s.time = &time_s; cb_data_s.value = NULL; cb_h = vpi_register_cb(&cb_data_s); vpi_free_object(cb_h); return(0); } static PLI_INT32 change_callback(p_cb_data cb_data) { int *id; // vpi_printf("change callback"); id = (int *)cb_data->user_data; changeFlag[*id] = 1; return(0); } void myhdl_register() { s_vpi_systf_data tf_data; tf_data.type = vpiSysTask; tf_data.tfname = "$to_myhdl"; tf_data.calltf = (void *) to_myhdl_calltf; tf_data.compiletf = NULL; tf_data.sizetf = NULL; tf_data.user_data = "$to_myhdl"; vpi_register_systf(&tf_data); //vpi_free_object(tf_data); // @mod cfelton tf_data.type = vpiSysTask; tf_data.tfname = "$from_myhdl"; tf_data.calltf = (void *) from_myhdl_calltf; tf_data.compiletf = NULL; tf_data.sizetf = NULL; tf_data.user_data = "$from_myhdl"; vpi_register_systf(&tf_data); //vpi_free_object(tf_data); // @mod cfelton } void (*vlog_startup_routines[])() = { myhdl_register, 0 }; /* dummy +loadvpi= boostrap routine - mimics old style exec all routines */ /* in standard PLI vlog_startup_routines table */ void vpi_compat_bootstrap(void) { int i; for (i = 0;; i++) { if (vlog_startup_routines[i] == NULL) break; vlog_startup_routines[i](); } } myhdl-0.11/cosimulation/modelsim/test/000077500000000000000000000000001347432460400200555ustar00rootroot00000000000000myhdl-0.11/cosimulation/modelsim/test/bin2gray.py000066400000000000000000000005761347432460400221540ustar00rootroot00000000000000import os from myhdl import Cosimulation cmd = 'vsim -c -quiet -pli ../myhdl_vpi.so -do cosim.do dut_bin2gray' def bin2gray(B, G, width): os.system('vlog -quiet +define+width=%s ../../test/verilog/bin2gray.v' % (width)) os.system('vlog -quiet +define+width=%s ../../test/verilog/dut_bin2gray.v' % (width)) return Cosimulation(cmd, B=B, G=G) myhdl-0.11/cosimulation/modelsim/test/cosim.do000066400000000000000000000000161347432460400215100ustar00rootroot00000000000000run -all quit myhdl-0.11/cosimulation/modelsim/test/dff.py000066400000000000000000000004711347432460400211700ustar00rootroot00000000000000import os from myhdl import Cosimulation cmd = 'vsim -c -quiet -pli ../myhdl_vpi.so -do cosim.do dut_dff' def dff(q, d, clk, reset): os.system('vlog -quiet ../../test/verilog/dff.v') os.system('vlog -quiet ../../test/verilog/dut_dff.v') return Cosimulation(cmd, **locals()) myhdl-0.11/cosimulation/modelsim/test/dff_clkout.py000066400000000000000000000005671347432460400225570ustar00rootroot00000000000000import os import os.path as path from myhdl import Cosimulation cmd = 'vsim -c -quiet -pli ../myhdl_vpi.so -do cosim.do dut_dff_clkout' def dff_clkout(clkout, q, d, clk, reset): os.system('vlog -quiet ../../test/verilog/dff_clkout.v') os.system('vlog -quiet ../../test/verilog/dut_dff_clkout.v') return Cosimulation(cmd, **locals()) myhdl-0.11/cosimulation/modelsim/test/inc.py000066400000000000000000000005471347432460400212060ustar00rootroot00000000000000import os from myhdl import Cosimulation cmd = 'vsim -c -quiet -pli ../myhdl_vpi.so -do cosim.do dut_inc' def inc(count, enable, clock, reset, n): os.system('vlog -quiet +define+n=%s ../../test/verilog/inc.v' % (n)) os.system('vlog -quiet +define+n=%s ../../test/verilog/dut_inc.v' % (n)) return Cosimulation(cmd, **locals()) myhdl-0.11/cosimulation/modelsim/test/test_all.py000066400000000000000000000026521347432460400222430ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run cosimulation unit tests. """ import sys sys.path.append("../../test") import test_bin2gray, test_inc, test_dff # modules = (test_dff, ) modules = (test_bin2gray, test_inc, test_dff ) import unittest tl = unittest.defaultTestLoader def suite(): alltests = unittest.TestSuite() for m in modules: alltests.addTest(tl.loadTestsFromModule(m)) return alltests def main(): unittest.main(defaultTest='suite', testRunner=unittest.TextTestRunner(verbosity=2)) if __name__ == '__main__': main() myhdl-0.11/cosimulation/test/000077500000000000000000000000001347432460400162445ustar00rootroot00000000000000myhdl-0.11/cosimulation/test/bin2gray.py000066400000000000000000000005011347432460400203270ustar00rootroot00000000000000from myhdl import always_comb def bin2gray(B, G, width): """ Gray encoder. B -- input intbv signal, binary encoded G -- output intbv signal, gray encoded width -- bit width """ @always_comb def logic(): for i in range(width): G.next[i] = B[i+1] ^ B[i] return logic myhdl-0.11/cosimulation/test/dff.py000066400000000000000000000006131347432460400173550ustar00rootroot00000000000000import myhdl from myhdl import * ACTIVE_LOW, INACTIVE_HIGH = 0, 1 def dff(q, d, clk, reset): """ D flip-flop. q -- output d -- input clock -- clock input reset -- asynchronous reset input """ @always(clk.posedge, reset.negedge) def logic(): if reset == ACTIVE_LOW: q.next = 0 else: q.next = d return logic myhdl-0.11/cosimulation/test/dff_clkout.py000066400000000000000000000004721347432460400207410ustar00rootroot00000000000000import myhdl from myhdl import * from dff import dff ACTIVE_LOW, INACTIVE_HIGH = 0, 1 def dff_clkout(clkout, q, d, clk, reset): DFF_1 = dff(q, d, clkout, reset) @instance def assign(): while 1: yield clk clkout.next = clk return DFF_1, assign myhdl-0.11/cosimulation/test/inc.py000066400000000000000000000010221347432460400173620ustar00rootroot00000000000000import myhdl from myhdl import * ACTIVE_LOW, INACTIVE_HIGH = 0, 1 def inc(count, enable, clock, reset, n): """ Incrementer with enable. count -- output enable -- control input, increment when 1 clock -- clock input reset -- asynchronous reset input n -- counter max value """ @always(clock.posedge, reset.negedge) def logic(): if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = (count + 1) % n return logic myhdl-0.11/cosimulation/test/test_all.py000066400000000000000000000026331347432460400204310ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run cosimulation unit tests. """ import sys sys.path.append("../../test") import test_bin2gray import test_inc import test_dff modules = (test_bin2gray, test_inc, test_dff) import unittest tl = unittest.defaultTestLoader def suite(): alltests = unittest.TestSuite() for m in modules: alltests.addTest(tl.loadTestsFromModule(m)) return alltests def main(): unittest.main(defaultTest='suite', testRunner=unittest.TextTestRunner(verbosity=2)) if __name__ == '__main__': main() myhdl-0.11/cosimulation/test/test_bin2gray.py000066400000000000000000000052461347432460400214010ustar00rootroot00000000000000from __future__ import generators import unittest from unittest import TestCase from myhdl import Simulation, Signal, delay, intbv, bin from bin2gray import bin2gray MAX_WIDTH = 10 def nextLn(Ln): """ Return Gray code Ln+1, given Ln. """ Ln0 = ['0' + codeword for codeword in Ln] Ln1 = ['1' + codeword for codeword in Ln] Ln1.reverse() return Ln0 + Ln1 class TestOriginalGrayCode(TestCase): def testOriginalGrayCode(self): """ Check that the code is an original Gray code """ Rn = [] def stimulus(B, G, n): for i in range(2**n): B.next = intbv(i) yield delay(10) Rn.append(bin(G, width=n)) Ln = ['0', '1'] # n == 1 for n in range(2, MAX_WIDTH): Ln = nextLn(Ln) del Rn[:] B = Signal(intbv(1)) G = Signal(intbv(0)) dut = bin2gray(B, G, n) stim = stimulus(B, G, n) sim = Simulation(dut, stim) sim.run(quiet=1) self.assertEqual(Ln, Rn) class TestGrayCodeProperties(TestCase): def testSingleBitChange(self): """ Check that only one bit changes in successive codewords """ def test(B, G, G_Z, width): B.next = intbv(0) yield delay(10) for i in range(1, 2**width): G_Z.next = G B.next = intbv(i) yield delay(10) diffcode = bin(G ^ G_Z) self.assertEqual(diffcode.count('1'), 1) for width in range(2, MAX_WIDTH): B = Signal(intbv(1)) G = Signal(intbv(0)) G_Z = Signal(intbv(0)) dut = bin2gray(B, G, width) check = test(B, G, G_Z, width) sim = Simulation(dut, check) sim.run(quiet=1) def testUniqueCodeWords(self): """ Check that all codewords occur exactly once """ def test(B, G, width): actual = [] for i in range(2**width): B.next = intbv(i) yield delay(10) actual.append(int(G)) actual.sort() expected = list(range(2**width)) self.assertEqual(actual, expected) for width in range(1, MAX_WIDTH): B = Signal(intbv(1)) G = Signal(intbv(0)) dut = bin2gray(B, G, width) check = test(B, G, width) sim = Simulation(dut, check) sim.run(quiet=1) if __name__ == '__main__': unittest.main() myhdl-0.11/cosimulation/test/test_dff.py000066400000000000000000000052211347432460400204140ustar00rootroot00000000000000from __future__ import generators import unittest from unittest import TestCase import random from random import randrange random.seed(2) from myhdl import Simulation, StopSimulation, Signal, \ delay, intbv, negedge, posedge, now from dff import dff from dff_clkout import dff_clkout ACTIVE_LOW, INACTIVE_HIGH = 0, 1 class TestDff(TestCase): vals = [randrange(2) for i in range(1000)] def clkGen(self, clk): while 1: yield delay(10) clk.next = not clk def stimulus(self, d, clk, reset): reset.next = ACTIVE_LOW yield negedge(clk) reset.next = INACTIVE_HIGH for v in self.vals: d.next = v yield negedge(clk) raise StopSimulation def check(self, q, clk, reset): yield posedge(reset) v_Z = 0 first = 1 for v in self.vals: yield posedge(clk) if not first: self.assertEqual(q, v_Z) first = 0 yield delay(3) self.assertEqual(q, v) v_Z = v def bench(self): q, d, clk, reset = [Signal(intbv(0)) for i in range(4)] DFF_1 = dff(q, d, clk, reset) CLK_1 = self.clkGen(clk) ST_1 = self.stimulus(d, clk, reset) CH_1 = self.check(q, clk, reset) sim = Simulation(DFF_1, CLK_1, ST_1, CH_1) return sim def test1(self): """ dff test """ sim = self.bench() sim.run(quiet=1) def test2(self): """ dff test with simulation suspends """ sim = self.bench() while sim.run(duration=randrange(1,5), quiet=1): pass def bench_clkout(self): clkout = Signal(intbv(0)) q = Signal(intbv(0), delay=1) d = Signal(intbv(0)) clk = Signal(intbv(0)) reset = Signal(intbv(0)) DFF_1 = dff_clkout(clkout, q, d, clk, reset) CLK_1 = self.clkGen(clk) ST_1 = self.stimulus(d, clkout, reset) CH_1 = self.check(q, clkout, reset) sim = Simulation(DFF_1, CLK_1, ST_1, CH_1) return sim def test1_clkout(self): """ dff_clkout test """ sim = self.bench_clkout() sim.run(quiet=1) def test2_clkout(self): """ dff_clkout test with simulation suspends """ sim = self.bench_clkout() while sim.run(duration=randrange(1,5), quiet=1): pass if __name__ == '__main__': unittest.main() myhdl-0.11/cosimulation/test/test_inc.py000066400000000000000000000037461347432460400204400ustar00rootroot00000000000000from __future__ import generators import unittest from unittest import TestCase import random from random import randrange random.seed(2) #import psyco #psyco.profile() from myhdl import Simulation, StopSimulation, Signal, \ delay, intbv, negedge, posedge, now from inc import inc ACTIVE_LOW, INACTIVE_HIGH = 0, 1 class TestInc(TestCase): def clockGen(self, clock): while 1: yield delay(10) clock.next = not clock def stimulus(self, enable, clock, reset): reset.next = ACTIVE_LOW yield negedge(clock) reset.next = INACTIVE_HIGH for i in range(1000): enable.next = min(1, randrange(5)) yield negedge(clock) raise StopSimulation def check(self, count, enable, clock, reset, n): expect = 0 yield posedge(reset) self.assertEqual(count, expect) while 1: yield posedge(clock) if enable: expect = (expect + 1) % n yield delay(1) # print "%d count %s expect %s" % (now(), count, expect) self.assertEqual(count, expect) def bench(self): n = 253 count, enable, clock, reset = [Signal(intbv(0)) for i in range(4)] INC_1 = inc(count, enable, clock, reset, n=n) CLK_1 = self.clockGen(clock) ST_1 = self.stimulus(enable, clock, reset) CH_1 = self.check(count, enable, clock, reset, n=n) sim = Simulation(INC_1, CLK_1, ST_1, CH_1) return sim def test1(self): """ Check increment operation """ sim = self.bench() sim.run(quiet=1) def test2(self): """ Check increment operation with suspended simulation runs """ sim = self.bench() while sim.run(duration=randrange(1, 6), quiet=1): pass if __name__ == '__main__': unittest.main() myhdl-0.11/cosimulation/test/verilog/000077500000000000000000000000001347432460400177135ustar00rootroot00000000000000myhdl-0.11/cosimulation/test/verilog/bin2gray.v000066400000000000000000000002261347432460400216170ustar00rootroot00000000000000module bin2gray(B, G); parameter width = 8; input [width-1:0] B; output [width-1:0] G; assign G = (B >> 1) ^ B; endmodule // bin2gray myhdl-0.11/cosimulation/test/verilog/dff.v000066400000000000000000000004551347432460400206450ustar00rootroot00000000000000module dff(q, d, clk, reset); input d; input clk; input reset; output q; reg q; always @(posedge clk or negedge reset) begin if (reset == 0) begin q <= 0; end else begin q <= d; end end // always @ (posedge clk or negedge reset) endmodule // inc myhdl-0.11/cosimulation/test/verilog/dff_clkout.v000066400000000000000000000007111347432460400222210ustar00rootroot00000000000000module dff_clkout(clkout, q, d, clk, reset); input d; input clk; input reset; output clkout; reg clkout; output q; reg q; always @(posedge clkout or negedge reset) begin if (reset == 0) begin q <= 0; end else begin q <= d; end end // always @ (posedge clk or negedge reset) initial begin clkout = 0; q = 0; end always @(clk) clkout = clk; endmodule // inc myhdl-0.11/cosimulation/test/verilog/dut_bin2gray.v000066400000000000000000000003241347432460400224720ustar00rootroot00000000000000module dut_bin2gray; reg [`width-1:0] B; wire [`width-1:0] G; initial begin $from_myhdl(B); $to_myhdl(G); end bin2gray dut (.B(B), .G(G)); defparam dut.width = `width; endmodule myhdl-0.11/cosimulation/test/verilog/dut_dff.v000066400000000000000000000003311347432460400215120ustar00rootroot00000000000000module dut_dff; reg d; reg clk; reg reset; wire q; initial begin $from_myhdl(d, clk, reset); $to_myhdl(q); end dff dut (.q(q), .d(d), .clk(clk), .reset(reset)); endmodule // inc myhdl-0.11/cosimulation/test/verilog/dut_dff_clkout.v000066400000000000000000000004141347432460400230750ustar00rootroot00000000000000module dut_dff_clkout; wire clkout; reg d; reg clk; reg reset; wire q; initial begin $from_myhdl(d, clk, reset); $to_myhdl(clkout, q); end dff_clkout dut (.clkout(clkout), .q(q), .d(d), .clk(clk), .reset(reset)); endmodule myhdl-0.11/cosimulation/test/verilog/dut_inc.v000066400000000000000000000004431347432460400215300ustar00rootroot00000000000000module dut_inc; reg enable; reg clock; reg reset; wire [15:0] count; initial begin $from_myhdl(enable, clock, reset); $to_myhdl(count); end inc dut (.count(count), .enable(enable), .clock(clock), .reset(reset)); defparam dut.n= `n; endmodule // inc myhdl-0.11/cosimulation/test/verilog/inc.v000066400000000000000000000010121347432460400206450ustar00rootroot00000000000000module inc(count, enable, clock, reset); parameter n = 8; input enable; input clock; input reset; output [15:0] count; reg [15:0] count; initial count = 0; always @(posedge clock or negedge reset) begin if (reset == 0) begin count <= 0; end else begin if (enable) begin count <= (count + 1) % n; end end end // always @ (posedge clock or negedge reset) // always @ (count) begin // $display("%d count %d", $time, count); // end endmodule // inc myhdl-0.11/doc/000077500000000000000000000000001347432460400133245ustar00rootroot00000000000000myhdl-0.11/doc/Makefile000066400000000000000000000103251347432460400147650ustar00rootroot00000000000000# Makefile for Sphinx documentation # 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text-align: center; } span.eqno { float: right; } img.logo { border: 0; } myhdl-0.11/doc/source/_templates/000077500000000000000000000000001347432460400167615ustar00rootroot00000000000000myhdl-0.11/doc/source/_templates/layout.html000066400000000000000000000006431347432460400211670ustar00rootroot00000000000000{% extends "!layout.html" %} {% block relbar1 %} {{ super() }} {% endblock %} {# put the sidebar before the body #} {% block sidebar1 %}{{ sidebar() }}{% endblock %} {% block sidebar2 %}{% endblock %} myhdl-0.11/doc/source/_templates/placeholder000066400000000000000000000000001347432460400211540ustar00rootroot00000000000000myhdl-0.11/doc/source/conf.py000066400000000000000000000176711347432460400161370ustar00rootroot00000000000000# -*- coding: utf-8 -*- # # MyHDL documentation build configuration file, created by # sphinx-quickstart on Wed Dec 19 16:54:56 2012. # # This file is execfile()d with the current directory set to its containing dir. # # Note that not all possible configuration values are present in this # autogenerated file. # # All configuration values have a default; values that are commented out # serve to show the default. import sys, os # If extensions (or modules to document with autodoc) are in another directory, # add these directories to sys.path here. If the directory is relative to the # documentation root, use os.path.abspath to make it absolute, like shown here. sys.path.insert(0, os.path.abspath('../..')) sys.path.append(os.path.abspath('.')) import myhdl # -- General configuration ----------------------------------------------------- # If your documentation needs a minimal Sphinx version, state it here. #needs_sphinx = '1.0' # Add any Sphinx extension module names here, as strings. They can be extensions # coming with Sphinx (named 'sphinx.ext.*') or your custom ones. extensions = ['sphinx.ext.intersphinx', 'sphinx.ext.doctest', 'myhdldoctools'] # Add any paths that contain templates here, relative to this directory. templates_path = ['_templates'] # The suffix of source filenames. source_suffix = '.rst' # The encoding of source files. #source_encoding = 'utf-8-sig' # The master toctree document. master_doc = 'index' # General information about the project. project = u'MyHDL' copyright = u'2018, Jan Decaluwe' # The version info for the project you're documenting, acts as replacement for # |version| and |release|, also used in various other places throughout the # built documents. # # The short X.Y version. # version = myhdl.__version__ # The full version, including alpha/beta/rc tags. release = myhdl.__version__ # The language for content autogenerated by Sphinx. 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Default is True. #html_show_sphinx = True # If true, "(C) Copyright ..." is shown in the HTML footer. Default is True. #html_show_copyright = True # If true, an OpenSearch description file will be output, and all pages will # contain a tag referring to it. The value of this option must be the # base URL from which the finished HTML is served. #html_use_opensearch = '' # This is the file name suffix for HTML files (e.g. ".xhtml"). #html_file_suffix = None # Output file base name for HTML help builder. htmlhelp_basename = 'MyHDLdoc' # -- Options for LaTeX output -------------------------------------------------- latex_elements = { # The paper size ('letterpaper' or 'a4paper'). 'papersize': 'a4paper', # The font size ('10pt', '11pt' or '12pt'). 'pointsize': '11pt', # Additional stuff for the LaTeX preamble. 'preamble': '\usepackage{palatino}', } # Grouping the document tree into LaTeX files. List of tuples # (source start file, target name, title, author, document class [howto/manual]). latex_documents = [(u'manual/index', u'MyHDL.tex', u'MyHDL manual', u'Jan Decaluwe', u'manual', True), ] # The name of an image file (relative to this directory) to place at the top of # the title page. #latex_logo = None # For "manual" documents, if this is true, then toplevel headings are parts, # not chapters. #latex_use_parts = False # If true, show page references after internal links. #latex_show_pagerefs = False # If true, show URL addresses after external links. #latex_show_urls = False # Documents to append as an appendix to all manuals. #latex_appendices = [] # If false, no module index is generated. #latex_domain_indices = True # -- Options for manual page output -------------------------------------------- # One entry per manual page. List of tuples # (source start file, name, description, authors, manual section). man_pages = [ ('index', 'myhdl', u'MyHDL Documentation', [u'Jan Decaluwe'], 1) ] # If true, show URL addresses after external links. #man_show_urls = False # -- Options for Texinfo output ------------------------------------------------ # Grouping the document tree into Texinfo files. List of tuples # (source start file, target name, title, author, # dir menu entry, description, category) texinfo_documents = [ ('index', 'MyHDL', u'MyHDL Documentation', u'Jan Decaluwe', 'MyHDL', 'One line description of project.', 'Miscellaneous'), ] # Documents to append as an appendix to all manuals. #texinfo_appendices = [] # If false, no module index is generated. #texinfo_domain_indices = True # How to display URL addresses: 'footnote', 'no', or 'inline'. #texinfo_show_urls = 'footnote' # Example configuration for intersphinx: refer to the Python standard library. intersphinx_mapping = {'http://docs.python.org/': None} myhdl-0.11/doc/source/index.rst000066400000000000000000000014011347432460400164610ustar00rootroot00000000000000.. MyHDL documentation master file, created by sphinx-quickstart.py on Thu Mar 20 11:33:23 2008. You can adapt this file completely to your liking, but it should at least contain the root `toctree` directive. .. include:: |myhdl-site|_ .. |myhdl-site| replace:: Back to the main site |raquo| .. _myhdl-site: http://www.myhdl.org Welcome to the MyHDL documentation ================================== .. toctree:: :maxdepth: 2 manual/index whatsnew/0.11 python3 Old Whatsnew documents ====================== .. toctree:: :maxdepth: 1 whatsnew/0.10 whatsnew/0.9 whatsnew/0.8 whatsnew/0.7 whatsnew/0.6 whatsnew/0.5 whatsnew/0.4 whatsnew/0.3 Index ===== * :ref:`genindex` Search ====== * :ref:`search` myhdl-0.11/doc/source/manual/000077500000000000000000000000001347432460400161015ustar00rootroot00000000000000myhdl-0.11/doc/source/manual/background.rst000066400000000000000000000112731347432460400207560ustar00rootroot00000000000000.. currentmodule:: myhdl .. _background: ********************** Background information ********************** .. _prerequisites: Prerequisites ============= You need a basic understanding of Python to use MyHDL. If you don't know Python, don't worry: it is is one of the easiest programming languages to learn [#]_. Learning Python is one of the best time investments that engineering professionals can make [#]_. For starters, http://docs.python.org/tutorial is probably the best choice for an on-line tutorial. For alternatives, see http://wiki.python.org/moin/BeginnersGuide. A working knowledge of a hardware description language such as Verilog or VHDL is helpful. Code examples in this manual are sometimes shortened for clarity. Complete executable examples can be found in the distribution directory at :file:`example/manual/`. .. _tutorial: A small tutorial on generators ============================== .. index:: single: generators; tutorial on Generators were introduced in Python 2.2. Because generators are the key concept in MyHDL, a small tutorial is included here. Consider the following nonsensical function:: def function(): for i in range(5): return i You can see why it doesn't make a lot of sense. As soon as the first loop iteration is entered, the function returns:: >>> function() 0 Returning is fatal for the function call. Further loop iterations never get a chance, and nothing is left over from the function call when it returns. To change the function into a generator function, we replace :keyword:`return` with :keyword:`yield`:: def generator(): for i in range(5): yield i Now we get:: >>> generator() When a generator function is called, it returns a generator object. A generator object supports the iterator protocol, which is an expensive way of saying that you can let it generate subsequent values by calling its :func:`next` method:: >>> g = generator() >>> g.next() 0 >>> g.next() 1 >>> g.next() 2 >>> g.next() 3 >>> g.next() 4 >>> g.next() Traceback (most recent call last): File "", line 1, in ? StopIteration Now we can generate the subsequent values from the for loop on demand, until they are exhausted. What happens is that the :keyword:`yield` statement is like a :keyword:`return`, except that it is non-fatal: the generator remembers its state and the point in the code when it yielded. A higher order agent can decide when to get the next value by calling the generator's :func:`next` method. We say that generators are :dfn:`resumable functions`. .. index:: single: VHDL; process single: Verilog; always block If you are familiar with hardware description languages, this may ring a bell. In hardware simulations, there is also a higher order agent, the Simulator, that interacts with such resumable functions; they are called :dfn:`processes` in VHDL and :dfn:`always blocks` in Verilog. Similarly, Python generators provide an elegant and efficient method to model concurrency, without having to resort to some form of threading. .. index:: single: sensitivity list The use of generators to model concurrency is the first key concept in MyHDL. The second key concept is a related one: in MyHDL, the yielded values are used to specify the conditions on which the generator should wait before resuming. In other words, :keyword:`yield` statements work as general sensitivity lists. .. _deco: About decorators ================ .. index:: single: decorators; about Python 2.4 introduced a feature called decorators. MyHDL takes advantage of this feature by defining a number of decorators that facilitate hardware descriptions. However, some users may not yet be familiar with decorators. Therefore, an introduction is included here. A decorator consists of special syntax in front of a function declaration. It refers to a decorator function. The decorator function automatically transforms the declared function into some other callable object. A decorator function :func:`deco` is used in a decorator statement as follows:: @deco def func(arg1, arg2, ...): This code is equivalent to the following:: def func(arg1, arg2, ...): func = deco(func) Note that the decorator statement goes directly in front of the function declaration, and that the function name :func:`func` is automatically reused for the final result. MyHDL uses decorators to create ready-to-simulate generators from local function definitions. Their functionality and usage will be described extensively in this manual. .. rubric:: Footnotes .. [#] You must be bored by such claims, but in Python's case it's true. .. [#] I am not biased. myhdl-0.11/doc/source/manual/conversion.rst000066400000000000000000000754221347432460400210320ustar00rootroot00000000000000.. currentmodule:: myhdl .. _conv: ****************************** Conversion to Verilog and VHDL ****************************** .. _conv-intro: Introduction ============ Subject to some limitations, MyHDL supports the automatic conversion of MyHDL code to Verilog or VHDL code. This feature provides a path from MyHDL into a standard Verilog or VHDL based design environment. This chapter describes the concepts of conversion. Concrete examples can be found in the companion chapter :ref:`conv-usage`. .. _conv-solution: Solution description ==================== To be convertible, the hardware description should satisfy certain restrictions, defined as the :dfn:`convertible subset`. This is described in detail in :ref:`conv-subset`. A convertible design can be converted to an equivalent model in Verilog or VHDL, using the function :func:`toVerilog` or :func:`toVHDL` from the MyHDL library. When the design is intended for implementation a third-party :dfn:`synthesis tool` is used to compile the Verilog or VHDL model into an implementation for an ASIC or FPGA. With this step, there is an automated path from a hardware description in Python to an FPGA or ASIC implementation. The conversion does not start from source files, but from an instantiated design that has been *elaborated* by the Python interpreter. The converter uses the Python profiler to track the interpreter's operation and to infer the design structure and name spaces. It then selectively compiles pieces of source code for additional analysis and for conversion. .. _conv-features: Features ======== Conversion after elaboration *Elaboration* refers to the initial processing of a hardware description to achieve a representation of a design instance that is ready for simulation or synthesis. In particular, structural parameters and constructs are processed in this step. In MyHDL, the Python interpreter itself is used for elaboration. A :class:`Simulation` object is constructed with elaborated design instances as arguments. Likewise, conversion works on an elaborated design instance. The Python interpreter is thus used as much as possible. Arbitrarily complex structure As the conversion works on an elaborated design instance, any modeling constraints only apply to the leaf elements of the design structure, that is, the co-operating generators. In other words, there are no restrictions on the description of the design structure: Python's full power can be used for that purpose. Also, the design hierarchy can be arbitrarily deep. Generator are mapped to Verilog or VHDL constructs The converter analyzes the code of each generator and maps it to equivalent constructs in the target HDL. For Verilog, it will map generators to ``always`` blocks, continuous assignments or ``initial`` blocks. For VHDL, it will map them to ``process`` statements or concurrent signal assignments. The module ports are inferred from signal usage In MyHDL, the input or output direction of ports is not explicitly declared. The converter investigates signal usage in the design hierarchy to infer whether a signal is used as input, output, or as an internal signal. Interfaces are convertible An *interface*: an object that has a number of :class:`Signal` objects as its attributes. The converter supports this by name expansion and mangling. Function calls are mapped to Verilog or VHDL subprograms The converter analyzes function calls and function code. Each function is mapped to an appropriate subprogram in the target HDL: a function or task in Verilog, and a function or procedure in VHDL. In order to support the full power of Python functions, a unique subprogram is generated per Python function call. If-then-else structures may be mapped to case statements Python does not provide a case statement. However, the converter recognizes if-then-else structures in which a variable is sequentially compared to items of an enumeration type, and maps such a structure to a Verilog or VHDL case statement with the appropriate synthesis attributes. Choice of encoding schemes for enumeration types The :func:`enum` function in MyHDL returns an enumeration type. This function takes an additional parameter *encoding* that specifies the desired encoding in the implementation: binary, one hot, or one cold. The converter generates the appropriate code for the specified encoding. RAM memory Certain synthesis tools can map Verilog memories or VHDL arrays to RAM structures. To support this interesting feature, the converter maps lists of signals to Verilog memories or VHDL arrays. ROM memory Some synthesis tools can infer a ROM from a case statement. The converter does the expansion into a case statement automatically, based on a higher level description. The ROM access is described in a single line, by indexing into a tuple of integers. Signed arithmetic In MyHDL, working with negative numbers is trivial: one just uses an ``intbv`` object with an appropriate constraint on its values. In contrast, both Verilog and VHDL make a difference between an unsigned and a signed representation. To work with negative values, the user has to declare a signed variable explicitly. But when signed and unsigned operands are mixed in an expression, things may become tricky. In Verilog, when signed and unsigned operands are mixed, all operands are interpreted as *unsigned*. Obviously, this leads to unexpected results. The designer will have to add sign extensions and type casts to solve this. In VHDL, mixing signed and unsigned will generally not work. The designer will have to match the operands manually by adding resizings and type casts. In MyHDL, these issues don't exist because ``intbv`` objects simply work as (constrained) integers. Moreover, the converter automates the cumbersome tasks that are required in Verilog and VHDL. It uses signed or unsigned types based on the value constraints of the intbv objects, and automatically performs the required sign extensions, resizings, and type casts. User-defined code If desired, the user can bypass the conversion process and describe user-defined code to be inserted instead. .. _conv-subset: The convertible subset ====================== .. _conv-subset-intro: Introduction ------------ Unsurprisingly, not all MyHDL code can be converted. Although the restrictions are significant, the convertible subset is much broader than the RTL synthesis subset which is an industry standard. In other words, MyHDL code written according to the RTL synthesis rules, should always be convertible. However, it is also possible to write convertible code for non-synthesizable models or test benches. The converter attempts to issue clear error messages when it encounters a construct that cannot be converted. Recall that any restrictions only apply to the design after elaboration. In practice, this means that they apply only to the code of the generators, that are the leaf functional blocks in a MyHDL design. .. _conv-subset-style: Coding style ------------ A natural restriction on convertible code is that it should be written in MyHDL style: cooperating generators, communicating through signals, and with sensitivity specify resume conditions. For pure modeling, it doesn't matter how generators are created. However, in convertible code they should be created using one of the MyHDL decorators: :func:`instance`, :func:`always`, :func:`always_seq`, or :func:`always_comb`. .. _conv-subset-types: Supported types --------------- The most important restriction regards object types. Only a limited amount of types can be converted. Python :class:`int` and :class:`long` objects are mapped to Verilog or VHDL integers. All other supported types need to have a defined bit width. The supported types are the Python :class:`bool` type, the MyHDL :class:`intbv` type, and MyHDL enumeration types returned by function :func:`enum`. .. index:: single: intbv; conversion :class:`intbv` objects must be constructed so that a bit width can be inferred. This can be done by specifying minimum and maximum values, e.g. as follows:: index = intbv(0, min=MIN, max=MAX) The Verilog converter supports :class:`intbv` objects that can take negative values. Alternatively, a slice can be taken from an :class:`intbv` object as follows:: index = intbv(0)[N:] Such as slice returns a new :class:`intbv` object, with minimum value ``0`` , and maximum value ``2**N``. In addition to the scalar types described above, the converter also supports a number of tuple and list based types. The mapping from MyHDL types is summarized in the following table. +--------------------------------------------+-------------------------------+-----------+-------------------------------+-----------+ | MyHDL type | VHDL type | Notes | Verilog type | Notes | +============================================+===============================+===========+===============================+===========+ | ``int`` | ``integer`` | | ``integer`` | | +--------------------------------------------+-------------------------------+-----------+-------------------------------+-----------+ | ``bool`` | ``std_logic`` | \(1) | ``reg`` | | +--------------------------------------------+-------------------------------+-----------+-------------------------------+-----------+ | ``intbv`` with ``min >= 0`` | ``unsigned`` | \(2) | ``reg`` | | +--------------------------------------------+-------------------------------+-----------+-------------------------------+-----------+ | ``intbv`` with ``min < 0`` | ``signed`` | \(2) | ``reg signed`` | | +--------------------------------------------+-------------------------------+-----------+-------------------------------+-----------+ | ``enum`` | dedicated enumeration type | | ``reg`` | | +--------------------------------------------+-------------------------------+-----------+-------------------------------+-----------+ | ``tuple`` of ``int`` | mapped to case statement | \(3) | mapped to case statement | \(3) | +--------------------------------------------+-------------------------------+-----------+-------------------------------+-----------+ | ``list`` of ``bool`` | ``array of std_logic`` | | ``reg`` | \(5) | +--------------------------------------------+-------------------------------+-----------+-------------------------------+-----------+ | ``list`` of ``intbv`` with ``min >= 0`` | ``array of unsigned`` | \(4) | ``reg`` | \(4)\(5) | +--------------------------------------------+-------------------------------+-----------+-------------------------------+-----------+ | ``list`` of ``intbv`` with ``min < 0`` | ``array of signed`` | \(4) | ``reg signed`` | \(4)\(5) | +--------------------------------------------+-------------------------------+-----------+-------------------------------+-----------+ Notes: (1) The VHDL ``std_logic`` type is defined in the standard VHDL package ``IEEE.std_logic_1164``. (2) The VHDL ``unsigned`` and ``signed`` types used are those from the standard VHDL packages ``IEEE.numeric_std``. (3) A MyHDL ``tuple`` of ``int`` is used for ROM inference, and can only be used in a very specific way: an indexing operation into the tuple should be the rhs of an assignment. (4) All list members should have identical value constraints. (5) Lists are mapped to Verilog memories. The table as presented applies to MyHDL variables. The converter also supports MyHDL signals that use ``bool``, ``intbv`` or ``enum`` objects as their underlying type. For VHDL, these are mapped to VHDL signals with an underlying type as specified in the table above. Verilog doesn't have the signal concept. For Verilog, a MyHDL signal is mapped to a Verilog ``reg`` as in the table above, or to a Verilog ``wire``, depending on the signal usage. The converter supports MyHDL list of signals provided the underlying signal type is either ``bool`` or ``intbv``. They may be mapped to a VHDL signal with a VHDL type as specified in the table, or to a Verilog memory. However, list of signals are not always mapped to a corresponding VHDL or Verilog object. See :ref:`conv-listofsigs` for more info. .. _conv-subset-statements: Supported statements -------------------- The following is a list of the statements that are supported by the Verilog converter, possibly qualified with restrictions or usage notes. :keyword:`assert` An :keyword:`assert` statement in Python looks as follow:: assert test_expression It can be converted provided ``test_expression`` is convertible. :keyword:`break` :keyword:`continue` :keyword:`def` :keyword:`for` The only supported iteration scheme is iterating through sequences of integers returned by built-in function :func:`range` or MyHDL function :func:`downrange`. The optional :keyword:`else` clause is not supported. :keyword:`if` :keyword:`if`, :keyword:`elif`, and :keyword:`else` clauses are fully supported. :keyword:`pass` :keyword:`print` A :keyword:`print` statement with multiple arguments:: print arg1, arg2, ... is supported. However, there are restrictions on the arguments. First, they should be of one of the following forms:: arg formatstring % arg formatstring % (arg1, arg2, ...) where ``arg`` is a ``bool``, ``int``, ``intbv``, ``enum``, or a ``Signal`` of these types. The ``formatstring`` contains ordinary characters and conversion specifiers as in Python. However, the only supported conversion specifiers are ``%s`` and ``%d``. Justification and width specification are thus not supported. Printing without a newline:: print arg1 , is not supported. :keyword:`raise` This statement is mapped to statements that end the simulation with an error message. :keyword:`return` :keyword:`yield` A `yield` expression is used to specify a sensitivity list. The yielded expression can be a :class:`Signal`, a signal edge as specified by MyHDL functions :attr:`Signal.posedge` or :attr:`Signal.negedge`, or a tuple of signals and edge specifications. It can also be a :func:`delay` object. :keyword:`while` The optional :keyword:`else` clause is not supported. .. _conv-subset-builtin: Supported built-in functions ---------------------------- The following is a list of the built-in functions that are supported by the converter. :func:`bool` This function can be used to typecast an object explicitly to its boolean interpretation. :func:`len` For :class:`Signal` and :class:`intbv` objects, function :func:`len` returns the bit width. :func:`int` This function can be used to typecast an object explicitly to its integer interpretation. Docstrings ---------- The converter propagates comments under the form of Python docstrings. Docstrings are typically used in Python to document certain objects in a standard way. Such "official" docstrings are put into the converted output at appropriate locations. The converter supports official docstrings for the top level module and for generators. Within generators, "nonofficial" docstrings are propagated also. These are strings (triple quoted by convention) that can occur anywhere between statements. Regular Python comments are ignored by the Python parser, and they are not present in the parse tree. Therefore, these are not propagated. With docstrings, you have an elegant way to specify which comments should be propagated and which not. .. _conv-listofsigs: Conversion of lists of signals ============================== Lists of signals are useful for many purposes. For example, they make it easy to create a repetitive structure. Another application is the description of memory behavior. The converter output is non-hierarchical. That implies that all signals are declared at the top-level in VHDL or Verilog (as VHDL signals, or Verilog regs and wires.) However, some signals that are a list member at some level in the MyHDL design hierarchy may be used as a plain signal at a lower level. For such signals, a choice has to be made whether to declare a Verilog memory or VHDL array, or a number of plain signal names. If possible, plain signal declarations are preferred, because Verilog memories and arrays have some restrictions in usage and tool support. This is possible if the list syntax is strictly used outside generator code, for example when lists of signals are used to describe structure. Conversely, when list syntax is used in some generator, then a Verilog memory or VHDL array will be declared. The typical example is the description of RAM memories. .. _conv-interfaces: Conversion of Interfaces ======================== Complex designs often have many signals that are passed to different levels of hierarchy. Typically, many signals logically belong together. This can be modelled by an *interface*: an object that has a number of :class:`Signal` objects as its attributes. Grouping signals into an interface simplifies the code, improves efficiency, and reduces errors. The converter supports interface using hierarchical name expansion and name mangling. .. _conv-meth-assign: Assignment issues ================= .. _conv-meth-assign-python: Name assignment in Python ------------------------- Name assignment in Python is a different concept than in many other languages. This point is very important for effective modeling in Python, and even more so for synthesizable MyHDL code. Therefore, the issues are discussed here explicitly. Consider the following name assignments:: a = 4 a = ``a string'' a = False In many languages, the meaning would be that an existing variable *a* gets a number of different values. In Python, such a concept of a variable doesn't exist. Instead, assignment merely creates a new binding of a name to a certain object, that replaces any previous binding. So in the example, the name *a* is bound a number of different objects in sequence. The converter has to investigate name assignment and usage in MyHDL code, and to map names to Verilog or VHDL objects. To achieve that, it tries to infer the type and possibly the bit width of each expression that is assigned to a name. Multiple assignments to the same name can be supported if it can be determined that a consistent type and bit width is being used in the assignments. This can be done for boolean expressions, numeric expressions, and enumeration type literals. In other cases, a single assignment should be used when an object is created. Subsequent value changes are then achieved by modification of an existing object. This technique should be used for :class:`Signal` and :class:`intbv` objects. .. _conv-meth-assign-signal: Signal assignment ----------------- Signal assignment in MyHDL is implemented using attribute assignment to attribute ``next``. Value changes are thus modeled by modification of the existing object. The converter investigates the :class:`Signal` object to infer the type and bit width of the corresponding Verilog or VHDL object. .. _conv-meth-assign-intbv: :class:`intbv` objects ---------------------- .. index:: single: intbv; conversion Type :class:`intbv` is likely to be the workhorse for synthesizable modeling in MyHDL. An :class:`intbv` instance behaves like a (mutable) integer whose individual bits can be accessed and modified. Also, it is possible to constrain its set of values. In addition to error checking, this makes it possible to infer a bit width, which is required for implementation. As noted before, it is not possible to modify value of an :class:`intbv` object using name assignment. In the following, we will show how it can be done instead. Consider:: a = intbv(0)[8:] This is an :class:`intbv` object with initial value ``0`` and bit width 8. To change its value to ``5``, we can use slice assignment:: a[8:] = 5 The same can be achieved by leaving the bit width unspecified, which has the meaning to change "all" bits:: a[:] = 5 Often the new value will depend on the old one. For example, to increment an :class:`intbv` with the technique above:: a[:] = a + 1 Python also provides *augmented* assignment operators, which can be used to implement in-place operations. These are supported on :class:`intbv` objects and by the converter, so that the increment can also be done as follows:: a += 1 .. _conv-subset-exclude: Excluding code from conversion ============================== For some tasks, such as debugging, it may be useful to insert arbitrary Python code that should not be converted. The converter supports this by ignoring all code that is embedded in a ``if __debug__`` test. The value of the ``__debug__`` variable is not taken into account. .. index:: single: user-defined code; description .. _conv-custom: User-defined code ================= MyHDL provides a way to include user-defined code during the conversion process. There are special function attributes that are understood by the converter but ignored by the simulator. The attributes are :attr:`verilog_code` for Verilog and :attr:`vhdl_code` for VHDL. They operate like a special return value. When defined in a MyHDL function, the converter will use their value instead of the regular return value. Effectively, it will stop converting at that point. The value of :attr:`verilog_code` or :attr:`vhdl_code` should be a Python template string. A template string supports ``$``-based substitutions. The ``$name`` notation can be used to refer to the variable names in the context of the string. The converter will substitute the appropriate values in the string and then insert it instead of the regular converted output. There is one more issue with user-defined code. Normally, the converter infers inputs, internal signals, and outputs. It also detects undriven and multiple driven signals. To do this, it assumes that signals are not driven by default. It then processes the code to find out which signals are driven from where. Proper signal usage inference cannot be done with user-defined code. Without user help, this will result in warnings or errors during the inference process, or in compilation errors from invalid code. The user can solve this by setting the :attr:`driven` or :attr:`read` attribute for signals that are driven or read from the user-defined code. These attributes are ``False`` by default. The allowed "true" values of the :attr:`driven` attribute are ``True``, ``'wire'`` and ``'reg'``. The latter two values specifies how the user-defined Verilog code drives the signal in Verilog. To decide which value to use, consider how the signal should be declared in Verilog after the user-defined code is inserted. For an example of user-defined code, see :ref:`conv-usage-custom`. Template transformation ======================= .. note:: This section is only relevant for VHDL. There is a difference between VHDL and Verilog in the way in which sensitivity to signal edges is specified. In Verilog, edge specifiers can be used directly in the sensitivity list. In VHDL, this is not possible: only signals can be used in the sensitivity list. To check for an edge, one uses the ``rising_edge()`` or ``falling_edge()`` functions in the code. MyHDL follows the Verilog scheme to specify edges in the sensitivity list. Consequently, when mapping such code to VHDL, it needs to be transformed to equivalent VHDL. This is an important issue because it affects all synthesizable templates that infer sequential logic. We will illustrate this feature with some examples. This is the MyHDL code for a D flip-flop:: @always(clk.posedge) def logic(): q.next = d It is converted to VHDL as follows:: DFF_LOGIC: process (clk) is begin if rising_edge(clk) then q <= d; end if; end process DFF_LOGIC; The converter can handle the more general case. For example, this is MyHDL code for a D flip-flop with asynchronous set, asynchronous reset, and preference of set over reset:: @always(clk.posedge, set.negedge, rst.negedge) def logic(): if set == 0: q.next = 1 elif rst == 0: q.next = 0 else: q.next = d This is converted to VHDL as follows:: DFFSR_LOGIC: process (clk, set, rst) is begin if (set = '0') then q <= '1'; elsif (rst = '0') then q <= '0'; elsif rising_edge(clk) then q <= d; end if; end process DFFSR_LOGIC; All cases with practical utility can be handled in this way. However, there are other cases that cannot be transformed to equivalent VHDL. The converter will detect those cases and give an error. .. _conv-meth-conv: Conversion output verification by co-simulation =============================================== .. note:: This section is only relevant for Verilog. To verify the converted Verilog output, co-simulation can be used. To make this task easier, the converter also generates a test bench that makes it possible to simulate the Verilog design using the Verilog co-simulation interface. This permits one to verify the Verilog code with the same test bench used for the MyHDL code. .. _conv-testbench: Conversion of test benches ========================== After conversion, we obviously want to verify that the VHDL or Verilog code works correctly. For Verilog, we can use co-simulation as discussed earlier. However, for VHDL, co-simulation is currently not supported. An alternative is to convert the test bench itself, so that both test bench and design can be run in the HDL simulator. Of course, this is not a fully general solution, as there are important constraints on the kind of code that can be converted. Thus, the question is whether the conversion restrictions permit one to develop sufficiently complex test benches. In this section, we present some insights about this. The most important restrictions regard the types that can be used, as discussed earlier in this chapter. However, the "convertible subset" is wider than the "synthesis subset". We will present a number of non-synthesizable feature that are of interest for test benches. the :keyword:`while` loop :keyword:`while` loops can be used for high-level control structures. the :keyword:`raise` statement A :keyword:`raise` statement can stop the simulation on an error condition. :func:`delay()` objects Delay modeling is essential for test benches. the :keyword:`print` statement :keyword:`print` statements can be used for simple debugging. the :keyword:`assert` statement. Originally, :keyword:`assert` statements were only intended to insert debugging assertions in code. Recently, there is a tendency to use them to write self-checking unit tests, controlled by unit test frameworks such as ``py.test``. In particular, they are a powerful way to write self-checking test benches for MyHDL designs. As :keyword:`assert` statements are convertible, a whole unit test suite in MyHDL can be converted to an equivalent test suite in Verilog and VHDL. Additionally, the same techniques as for synthesizable code can be used to master complexity. In particular, any code outside generators is executed during elaboration, and therefore not considered in the conversion process. This feature can for example be used for complex calculations that set up constants or expected results. Furthermore, a tuple of ints can be used to hold a table of values that will be mapped to a case statement in Verilog and VHDL. .. _conv-meth: Methodology notes ================= .. _conv-meth-sim: Simulate first -------------- In the Python philosophy, the run-time rules. The Python compiler doesn't attempt to detect a lot of errors beyond syntax errors, which given Python's ultra-dynamic nature would be an almost impossible task anyway. To verify a Python program, one should run it, preferably using unit testing to verify each feature. The same philosophy should be used when converting a MyHDL description to Verilog: make sure the simulation runs fine first. Although the converter checks many things and attempts to issue clear error messages, there is no guarantee that it does a meaningful job unless the simulation runs fine. .. _conv-meth-hier: Handling hierarchy ------------------ Recall that conversion occurs after elaboration. A consequence is that the converted output is non-hierarchical. In many cases, this is not an issue. The purpose of conversion is to provide a path into a traditional design flow by using Verilog and VHDL as a "back-end" format. Hierarchy is quite relevant to humans, but much less so to tools. However, in some cases hierarchy is desirable. For example, if you convert a test bench you may prefer to keep its code separate from the design under test. In other words, conversion should stop at the design under test instance, and insert an instantiation instead. There is a workaround to accomplish this with a small amount of additional work. The workaround is to define user-defined code consisting of an instantiation of the design under test. As discussed in :ref:`conv-custom`, when the converter sees the hook it will stop converting and insert the instantiation instead. Of course, you will want to convert the design under test itself also. Therefore, you should use a flag that controls whether the hook is defined or not and set it according to the desired conversion. .. _conv-issues: Known issues ============ Verilog and VHDL integers are 32 bit wide Usually, Verilog and VHDL integers are 32 bit wide. In contrast, Python is moving toward integers with undefined width. Python :class:`int` and :class:`long` variables are mapped to Verilog integers; so for values wider than 32 bit this mapping is incorrect. Synthesis pragmas are specified as Verilog comments. The recommended way to specify synthesis pragmas in Verilog is through attribute lists. However, the Icarus simulator doesn't support them for ``case`` statements (to specify ``parallel_case`` and ``full_case`` pragmas). Therefore, the old but deprecated method of synthesis pragmas in Verilog comments is still used. Inconsistent place of the sensitivity list inferred from ``always_comb``. The semantics of ``always_comb``, both in Verilog and MyHDL, is to have an implicit sensitivity list at the end of the code. However, this may not be synthesizable. Therefore, the inferred sensitivity list is put at the top of the corresponding ``always`` block or ``process``. This may cause inconsistent behavior at the start of the simulation. The workaround is to create events at time 0. myhdl-0.11/doc/source/manual/conversion_examples.rst000066400000000000000000000347631347432460400227330ustar00rootroot00000000000000.. currentmodule:: myhdl .. _conv-usage: ******************* Conversion examples ******************* .. _conv-usage-intro: Introduction ============ In this chapter, we will demonstrate the conversion process with a number of examples. For the concepts of MyHDL conversion, read the companion chapter :ref:`conv`. .. _conv-usage-seq: A small sequential design ========================= Consider the following MyHDL code for an incrementer block: .. include-example:: inc.py This design can be converted to Verilog and VHDL. The first step is to elaborate it, just as we do for simulation. Then we can use the :func:`convert` method on the elaborated instance. .. include-example:: convert_inc.py For flexibility, we wrap the conversion in a :func:`convert_inc` function. ``inc_1`` is an elaborated design instance that provides the conversion method. The conversion to Verilog generates an equivalent Verilog module in file :file:`inc.v`. The Verilog code looks as follows: .. include-example:: inc.v The converter infers a proper Verilog module interface and maps the MyHDL generator to a Verilog always block. Similarly, the conversion to VHDL generates a file :file:`inc.vhd` with the following content: .. include-example:: inc.vhd The MyHDL generator is mapped to a VHDL process in this case. Note that the VHDL file refers to a VHDL package called ``pck_myhdl_``. This package contains a number of convenience functions that make the conversion easier. Note also the use of an ``inout`` in the interface. This is not recommended VHDL design practice, but it is required here to have a valid VHDL design that matches the behavior of the MyHDL design. As this is only an issue for ports and as the converter output is non-hierarchical, the issue is not very common and has an easy workaround. .. _conv-usage-comb: A small combinatorial design ============================ The second example is a small combinatorial design, more specifically the binary to Gray code converter from previous chapters: .. include-example:: bin2gray.py As before, you can create an instance and convert to Verilog and VHDL as follows: .. include-example:: convert_bin2gray.py The generated Verilog code looks as follows: .. include-example:: bin2gray.v The generated VHDL code looks as follows: .. include-example:: bin2gray.vhd .. _conv-usage-hier: A hierarchical design ===================== The converter can handle designs with an arbitrarily deep hierarchy. For example, suppose we want to design an incrementer with Gray code output. Using the designs from previous sections, we can proceed as follows: .. include-example:: gray_inc.py According to Gray code properties, only a single bit will change in consecutive values. However, as the ``bin2gray`` module is combinatorial, the output bits may have transient glitches, which may not be desirable. To solve this, let's create an additional level of hierarchy and add an output register to the design. (This will create an additional latency of a clock cycle, which may not be acceptable, but we will ignore that here.) .. include-example:: gray_inc_reg.py We can convert this hierarchical design as follows: .. include-example:: convert_gray_inc_reg.py The Verilog output code looks as follows: .. include-example:: gray_inc_reg.v The VHDL output code looks as follows: .. include-example:: gray_inc_reg.vhd Note that the output is a flat "net list of blocks", and that hierarchical signal names are generated as necessary. .. _conv-usage-fsm: Optimizations for finite state machines ======================================= As often in hardware design, finite state machines deserve special attention. In Verilog and VHDL, finite state machines are typically described using case statements. Python doesn't have a case statement, but the converter recognizes particular if-then-else structures and maps them to case statements. This optimization occurs when a variable whose type is an enumerated type is sequentially tested against enumeration items in an if-then-else structure. Also, the appropriate synthesis pragmas for efficient synthesis are generated in the Verilog code. As a further optimization, function :func:`enum` was enhanced to support alternative encoding schemes elegantly, using an additional parameter *encoding*. For example:: t_State = enum('SEARCH', 'CONFIRM', 'SYNC', encoding='one_hot') The default encoding is ``'binary'``; the other possibilities are ``'one_hot'`` and ``'one_cold'``. This parameter only affects the conversion output, not the behavior of the type. The generated Verilog code for case statements is optimized for an efficient implementation according to the encoding. Note that in contrast, a Verilog designer has to make nontrivial code changes to implement a different encoding scheme. As an example, consider the following finite state machine, whose state variable uses the enumeration type defined above:: ACTIVE_LOW = bool(0) FRAME_SIZE = 8 t_State = enum('SEARCH', 'CONFIRM', 'SYNC', encoding="one_hot") def FramerCtrl(SOF, state, syncFlag, clk, reset_n): """ Framing control FSM. SOF -- start-of-frame output bit state -- FramerState output syncFlag -- sync pattern found indication input clk -- clock input reset_n -- active low reset """ index = Signal(intbv(0)[8:]) # position in frame @always(clk.posedge, reset_n.negedge) def FSM(): if reset_n == ACTIVE_LOW: SOF.next = 0 index.next = 0 state.next = t_State.SEARCH else: index.next = (index + 1) % FRAME_SIZE SOF.next = 0 if state == t_State.SEARCH: index.next = 1 if syncFlag: state.next = t_State.CONFIRM elif state == t_State.CONFIRM: if index == 0: if syncFlag: state.next = t_State.SYNC else: state.next = t_State.SEARCH elif state == t_State.SYNC: if index == 0: if not syncFlag: state.next = t_State.SEARCH SOF.next = (index == FRAME_SIZE-1) else: raise ValueError("Undefined state") return FSM The conversion is done as before:: SOF = Signal(bool(0)) syncFlag = Signal(bool(0)) clk = Signal(bool(0)) reset_n = Signal(bool(1)) state = Signal(t_State.SEARCH) toVerilog(FramerCtrl, SOF, state, syncFlag, clk, reset_n) toVHDL(FramerCtrl, SOF, state, syncFlag, clk, reset_n) The Verilog output looks as follows:: module FramerCtrl ( SOF, state, syncFlag, clk, reset_n ); output SOF; reg SOF; output [2:0] state; reg [2:0] state; input syncFlag; input clk; input reset_n; reg [7:0] index; always @(posedge clk, negedge reset_n) begin: FRAMERCTRL_FSM if ((reset_n == 0)) begin SOF <= 0; index <= 0; state <= 3'b001; end else begin index <= ((index + 1) % 8); SOF <= 0; // synthesis parallel_case full_case casez (state) 3'b??1: begin index <= 1; if (syncFlag) begin state <= 3'b010; end end 3'b?1?: begin if ((index == 0)) begin if (syncFlag) begin state <= 3'b100; end else begin state <= 3'b001; end end end 3'b1??: begin if ((index == 0)) begin if ((!syncFlag)) begin state <= 3'b001; end end SOF <= (index == (8 - 1)); end default: begin $finish; end endcase end end endmodule The VHDL output looks as follows:: package pck_FramerCtrl is type t_enum_t_State_1 is ( SEARCH, CONFIRM, SYNC ); attribute enum_encoding of t_enum_t_State_1: type is "001 010 100"; end package pck_FramerCtrl; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use std.textio.all; use work.pck_myhdl_06.all; use work.pck_FramerCtrl.all; entity FramerCtrl is port ( SOF: out std_logic; state: inout t_enum_t_State_1; syncFlag: in std_logic; clk: in std_logic; reset_n: in std_logic ); end entity FramerCtrl; architecture MyHDL of FramerCtrl is signal index: unsigned(7 downto 0); begin FRAMERCTRL_FSM: process (clk, reset_n) is begin if (reset_n = '0') then SOF <= '0'; index <= "00000000"; state <= SEARCH; elsif rising_edge(clk) then index <= ((index + 1) mod 8); SOF <= '0'; case state is when SEARCH => index <= "00000001"; if to_boolean(syncFlag) then state <= CONFIRM; end if; when CONFIRM => if (index = 0) then if to_boolean(syncFlag) then state <= SYNC; else state <= SEARCH; end if; end if; when SYNC => if (index = 0) then if (not to_boolean(syncFlag)) then state <= SEARCH; end if; end if; SOF <= to_std_logic(signed(resize(index, 9)) = (8 - 1)); when others => assert False report "End of Simulation" severity Failure; end case; end if; end process FRAMERCTRL_FSM; end architecture MyHDL; .. _conv-usage-ram: RAM inference ============= Certain synthesis tools can infer RAM structures. To support this feature, the converter maps lists of signals in MyHDL to Verilog memories and VHDL arrays. The following MyHDL example is a ram model that uses a list of signals to model the internal memory. :: def RAM(dout, din, addr, we, clk, depth=128): """ Ram model """ mem = [Signal(intbv(0)[8:]) for i in range(depth)] @always(clk.posedge) def write(): if we: mem[addr].next = din @always_comb def read(): dout.next = mem[addr] return write, read With the appropriate signal definitions for the interface ports, it is converted to the following Verilog code. Note how the list of signals ``mem`` is mapped to a Verilog memory. :: module ram ( dout, din, addr, we, clk ); output [7:0] dout; wire [7:0] dout; input [7:0] din; input [6:0] addr; input we; input clk; reg [7:0] mem [0:128-1]; always @(posedge clk) begin: RAM_1_WRITE if (we) begin mem[addr] <= din; end end assign dout = mem[addr]; endmodule In VHDL, the list of MyHDL signals is modeled as a VHDL array signal:: library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.pck_myhdl_06.all; entity ram is port ( dout: out unsigned(7 downto 0); din: in unsigned(7 downto 0); addr: in unsigned(6 downto 0); we: in std_logic; clk: in std_logic ); end entity ram; architecture MyHDL of ram is type t_array_mem is array(0 to 128-1) of unsigned(7 downto 0); signal mem: t_array_mem; begin RAM_WRITE: process (clk) is begin if rising_edge(clk) then if to_boolean(we) then mem(to_integer(addr)) <= din; end if; end if; end process RAM_WRITE; dout <= mem(to_integer(addr)); end architecture MyHDL; .. _conv-usage-rom: ROM inference ============= Some synthesis tools can infer a ROM memory from a case statement. The Verilog converter can perform the expansion into a case statement automatically, based on a higher level description. The ROM access is described in a single line, by indexing into a tuple of integers. The tuple can be described manually, but also by programmatical means. Note that a tuple is used instead of a list to stress the read-only character of the memory. The following example illustrates this functionality. ROM access is described as follows:: def rom(dout, addr, CONTENT): @always_comb def read(): dout.next = CONTENT[int(addr)] return read The ROM content is described as a tuple of integers. When the ROM content is defined, the conversion can be performed:: CONTENT = (17, 134, 52, 9) dout = Signal(intbv(0)[8:]) addr = Signal(intbv(0)[4:]) toVerilog(rom, dout, addr, CONTENT) toVHDL(rom, dout, addr, CONTENT) The Verilog output code is as follows:: module rom ( dout, addr ); output [7:0] dout; reg [7:0] dout; input [3:0] addr; always @(addr) begin: ROM_READ // synthesis parallel_case full_case case (addr) 0: dout <= 17; 1: dout <= 134; 2: dout <= 52; default: dout <= 9; endcase end endmodule The VHDL output code is as follows:: library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use std.textio.all; use work.pck_myhdl_06.all; entity rom is port ( dout: out unsigned(7 downto 0); addr: in unsigned(3 downto 0) ); end entity rom; architecture MyHDL of rom is begin ROM_READ: process (addr) is begin case to_integer(addr) is when 0 => dout <= "00010001"; when 1 => dout <= "10000110"; when 2 => dout <= "00110100"; when others => dout <= "00001001"; end case; end process ROM_READ; end architecture MyHDL; .. index:: single: user-defined code; example .. _conv-usage-custom: User-defined code ================= MyHDL provides a way to include user-defined code during the conversion process, using the special function attributes :attr:`vhdl_code` and :attr:`verilog_code`. For example:: def inc_comb(nextCount, count, n): @always(count) def logic(): # do nothing here pass nextCount.driven = "wire" return logic inc_comb.verilog_code =\ """ assign $nextCount = ($count + 1) % $n; """ inc_comb.vhdl_code =\ """ $nextCount <= ($count + 1) mod $n; """ The converted code looks as follows in Verilog:: module inc_comb ( nextCount, count ); output [7:0] nextCount; wire [7:0] nextCount; input [7:0] count; assign nextCount = (count + 1) % 256; endmodule and as follows in VHDL:: library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.pck_myhdl_06.all; entity inc_comb is port ( nextCount: out unsigned(7 downto 0); count: in unsigned(7 downto 0) ); end entity inc_comb; architecture MyHDL of inc_comb is begin nextCount <= (count + 1) mod 256; end architecture MyHDL; In this example, conversion of the :func:`inc_comb` function is bypassed and the user-defined code is inserted instead. The user-defined code is a Python template string that can refer to signals and parameters in the MyHDL context through ``$``-based substitutions. During conversion, the appropriate hierarchical names and parameter values will be substituted. The MyHDL code contains the following assignment:: nextCount.driven = "wire" This specifies that the nextCount signal is driven as a Verilog wire from this module. For more info about user-defined code, see :ref:`conv-custom`. myhdl-0.11/doc/source/manual/cosimulation.rst000066400000000000000000000411711347432460400213450ustar00rootroot00000000000000.. currentmodule:: myhdl .. _cosim: ************************** Co-simulation with Verilog ************************** .. _cosim-intro: Introduction ============ One of the most exciting possibilities of MyHDL\ is to use it as a hardware verification language (HVL). A HVL is a language used to write test benches and verification environments, and to control simulations. Nowadays, it is generally acknowledged that HVLs should be equipped with modern software techniques, such as object orientation. The reason is that verification it the most complex and time-consuming task of the design process. Consequently, every useful technique is welcome. Moreover, test benches are not required to be implementable. Therefore, unlike with synthesizable code, there are no constraints on creativity. Technically, verification of a design implemented in another language requires co-simulation. MyHDL is enabled for co-simulation with any HDL simulator that has a procedural language interface (PLI). The MyHDL\ side is designed to be independent of a particular simulator, On the other hand, for each HDL simulator a specific PLI module will have to be written in C. Currently, the MyHDL release contains a PLI module for two Verilog simulators: Icarus and Cver. .. _cosim-hdl: The HDL side ============ To introduce co-simulation, we will continue to use the Gray encoder example from the previous chapters. Suppose that we want to synthesize it and write it in Verilog for that purpose. Clearly we would like to reuse our unit test verification environment. To start, let's recall how the Gray encoder in MyHDL looks like: .. include-example:: bin2gray.py To show the co-simulation flow, we don't need the Verilog implementation yet, but only the interface. Our Gray encoder in Verilog would have the following interface:: module bin2gray(B, G); parameter width = 8; input [width-1:0] B; output [width-1:0] G; .... To write a test bench, one creates a new module that instantiates the design under test (DUT). The test bench declares nets and regs (or signals in VHDL) that are attached to the DUT, and to stimulus generators and response checkers. In an all-HDL flow, the generators and checkers are written in the HDL itself, but we will want to write them in MyHDL. To make the connection, we need to declare which regs & nets are driven and read by the MyHDL\ simulator. For our example, this is done as follows:: module dut_bin2gray; reg [`width-1:0] B; wire [`width-1:0] G; initial begin $from_myhdl(B); $to_myhdl(G); end bin2gray dut (.B(B), .G(G)); defparam dut.width = `width; endmodule The ``$from_myhdl`` task call declares which regs are driven by MyHDL, and the ``$to_myhdl`` task call which regs & nets are read by it. These tasks take an arbitrary number of arguments. They are defined in a PLI module written in C and made available in a simulator-dependent manner. In Icarus Verilog, the tasks are defined in a ``myhdl.vpi`` module that is compiled from C source code. .. _cosim-myhdl: The MyHDL side ============== MyHDL supports co-simulation by a ``Cosimulation`` object. A ``Cosimulation`` object must know how to run a HDL simulation. Therefore, the first argument to its constructor is a command string to execute a simulation. The way to generate and run an simulation executable is simulator dependent. For example, in Icarus Verilog, a simulation executable for our example can be obtained obtained by running the ``iverilog`` compiler as follows:: % iverilog -o bin2gray -Dwidth=4 bin2gray.v dut_bin2gray.v This generates a ``bin2gray`` executable for a parameter ``width`` of 4, by compiling the contributing Verilog files. The simulation itself is run by the ``vvp`` command:: % vvp -m ./myhdl.vpi bin2gray This runs the ``bin2gray`` simulation, and specifies to use the ``myhdl.vpi`` PLI module present in the current directory. (This is just a command line usage example; actually simulating with the ``myhdl.vpi`` module is only meaningful from a ``Cosimulation`` object.) We can use a ``Cosimulation`` object to provide a HDL version of a design to the MyHDL simulator. Instead of a generator function, we write a function that returns a ``Cosimulation`` object. For our example and the Icarus Verilog simulator, this is done as follows:: import os from myhdl import Cosimulation cmd = "iverilog -o bin2gray.o -Dwidth=%s " + \ "../../test/verilog/bin2gray.v " + \ "../../test/verilog/dut_bin2gray.v " def bin2gray(B, G): width = len(B) os.system(cmd % width) return Cosimulation("vvp -m ../myhdl.vpi bin2gray.o", B=B, G=G) After the executable command argument, the ``Cosimulation`` constructor takes an arbitrary number of keyword arguments. Those arguments make the link between MyHDL Signals and HDL nets, regs, or signals, by named association. The keyword is the name of an argument in a ``$to_myhdl`` or ``$from_myhdl`` call; the argument is a MyHDL Signal. With all this in place, we can now use the existing unit test to verify the Verilog implementation. Note that we kept the same name and parameters for the the ``bin2gray`` function: all we need to do is to provide this alternative definition to the existing unit test. Let's try it on the Verilog design:: module bin2gray(B, G); parameter width = 8; input [width-1:0] B; output [width-1:0] G; assign G = (B >> 1) ^ B; endmodule // bin2gray When we run our unit tests, we get:: % python test_gray.py testSingleBitChange (test_gray_properties.TestGrayCodeProperties) Check that only one bit changes in successive codewords. ... ok testUniqueCodeWords (test_gray_properties.TestGrayCodeProperties) Check that all codewords occur exactly once. ... ok testOriginalGrayCode (test_gray_original.TestOriginalGrayCode) Check that the code is an original Gray code. ... ok ---------------------------------------------------------------------- Ran 3 tests in 0.706s OK .. _cosim-restr: Restrictions ============ In the ideal case, it should be possible to simulate any HDL description seamlessly with MyHDL. Moreover the communicating signals at each side should act transparently as a single one, enabling fully race free operation. For various reasons, it may not be possible or desirable to achieve full generality. As anyone that has developed applications with the Verilog PLI can testify, the restrictions in a particular simulator, and the differences over various simulators, can be quite frustrating. Moreover, full generality may require a disproportionate amount of development work compared to a slightly less general solution that may be sufficient for the target application. Consequently, I have tried to achieve a solution which is simple enough so that one can reasonably expect that any PLI-enabled simulator can support it, and that is relatively easy to verify and maintain. At the same time, the solution is sufficiently general to cover the target application space. The result is a compromise that places certain restrictions on the HDL code. In this section, these restrictions are presented. .. _cosim-pass: Only passive HDL can be co-simulated ------------------------------------ The most important restriction of the MyHDL co-simulation solution is that only "passive" HDL can be co-simulated. This means that the HDL code should not contain any statements with time delays. In other words, the MyHDL simulator should be the master of time; in particular, any clock signal should be generated at the MyHDL side. At first this may seem like an important restriction, but if one considers the target application for co-simulation, it probably isn't. MyHDL supports co-simulation so that test benches for HDL designs can be written in Python. Let's consider the nature of the target HDL designs. For high-level, behavioral models that are not intended for implementation, it should come as no surprise that I would recommend to write them in MyHDL directly; that is one of the goals of the MyHDL effort. Likewise, gate level designs with annotated timing are not the target application: static timing analysis is a much better verification method for such designs. Rather, the targeted HDL designs are naturally models that are intended for implementation, most likely through synthesis. As time delays are meaningless in synthesizable code, the restriction is compatible with the target application. .. _cosim-race: Race sensitivity issues ----------------------- In a typical RTL code, some events cause other events to occur in the same time step. For example, when a clock signal triggers some signals may change in the same time step. For race-free operation, an HDL must differentiate between such events within a time step. This is done by the concept of "delta" cycles. In a fully general, race free co-simulation, the co-simulators would communicate at the level of delta cycles. However, in MyHDL co-simulation, this is not entirely the case. Delta cycles from the MyHDL simulator toward the HDL co-simulator are preserved. However, in the opposite direction, they are not. The signals changes are only returned to the MyHDL simulator after all delta cycles have been performed in the HDL co-simulator. What does this mean? Let's start with the good news. As explained in the previous section, the concept behind MyHDL co-simulation implies that clocks are generated at the MyHDL side. *When using a MyHDL clock and its corresponding HDL signal directly as a clock, co-simulation is race free.* In other words, the case that most closely reflects the MyHDL co-simulation approach, is race free. The situation is different when you want to use a signal driven by the HDL (and the corresponding MyHDL signal) as a clock. Communication triggered by such a clock is not race free. The solution is to treat such an interface as a chip interface instead of an RTL interface. For example, when data is triggered at positive clock edges, it can safely be sampled at negative clock edges. Alternatively, the MyHDL data signals can be declared with a delay value, so that they are guaranteed to change after the clock edge. .. _cosim-impl: Implementation notes ==================== This section requires some knowledge of PLI terminology. Enabling a simulator for co-simulation requires a PLI module written in C. In Verilog, the PLI is part of the "standard". However, different simulators implement different versions and portions of the standard. Worse yet, the behavior of certain PLI callbacks is not defined on some essential points. As a result, one should plan to write or at least customize a specific PLI module for any simulator. The release contains a PLI module for the open source Icarus and Cver simulators. This section documents the current approach and status of the PLI module implementation and some reflections on future implementations. .. _cosim-icarus: Icarus Verilog -------------- .. _cosim-icarus-delta: Delta cycle implementation ^^^^^^^^^^^^^^^^^^^^^^^^^^ To make co-simulation work, a specific type of PLI callback is needed. The callback should be run when all pending events have been processed, while allowing the creation of new events in the current time step (e.g. by the MyHDL simulator). In some Verilog simulators, the ``cbReadWriteSync`` callback does exactly that. However, in others, including Icarus, it does not. The callback's behavior is not fully standardized; some simulators run the callback before non- blocking assignment events have been processed. Consequently, I had to look for a workaround. One half of the solution is to use the ``cbReadOnlySync`` callback. This callback runs after all pending events have been processed. However, it does not permit one to create new events in the current time step. The second half of the solution is to map MyHDL delta cycles onto real Verilog time steps. Note that fortunately I had some freedom here because of the restriction that only passive HDL code can be co-simulated. I chose to make the time granularity in the Verilog simulator a 1000 times finer than in the MyHDL simulator. For each MyHDL time step, 1000 Verilog time steps are available for MyHDL delta cycles. In practice, only a few delta cycles per time step should be needed. Exceeding this limit almost certainly indicates a design error; the limit is checked at run-time. The factor 1000 also makes it easy to distinguish "real" time from delta cycle time when printing out the Verilog time. .. _cosim-icarus-pass: Passive Verilog check ^^^^^^^^^^^^^^^^^^^^^ As explained before, co-simulated Verilog should not contain delay statements. Ideally, there should be a run-time check to flag non-compliant code. However, there is currently no such check in the Icarus module. The check can be written using the ``cbNextSimTime`` VPI callback in Verilog. However, Icarus 0.7 doesn't support this callback. In the meantime, support for it has been added to the Icarus development branch. When Icarus 0.8 is released, a check will be added. In the mean time, just don't do this. It may appear to "work" but it really won't as events will be missed over the co-simulation interface. .. _cosim-cver: Cver ---- MyHDL co-simulation is supported with the open source Verilog simulator Cver. The PLI module is based on the one for Icarus and basically has the same functionality. Only some cosmetic modifications were required. .. _cosim-impl-verilog: Other Verilog simulators ------------------------ The Icarus module is written with VPI calls, which are provided by the most recent generation of the Verilog PLI. Some simulators may only support TF/ACC calls, requiring a complete redesign of the interface module. If the simulator supports VPI, the Icarus module should be reusable to a large extent. However, it may be possible to improve on it. The workaround to support delta cycles described in Section :ref:`cosim-icarus-delta` may not be necessary. In some simulators, the ``cbReadWriteSync`` callback occurs after all events (including non-blocking assignments) have been processed. In that case, the functionality can be supported without a finer time granularity in the Verilog simulator. There are also Verilog standardization efforts underway to resolve the ambiguity of the ``cbReadWriteSync`` callback. The solution will be to introduce new, well defined callbacks. From reading some proposals, I conclude that the ``cbEndOfSimTime`` callback would provide the required functionality. The MyHDL project currently has no access to commercial Verilog simulators, so progress in co-simulation support depends on external interest and participation. Users have reported that they are using MyHDL co-simulation with the simulators from Aldec and Modelsim. .. _cosim-impl-syscalls: Interrupted system calls ------------------------ The PLI module uses ``read`` and ``write`` system calls to communicate between the co-simulators. The implementation assumes that these calls are restarted automatically by the operating system when interrupted. This is apparently what happens on the Linux box on which MyHDL is developed. It is known how non-restarted interrupted system calls should be handled, but currently such code cannot be tested on the MyHDL development platform. Also, it is not clear whether this is still a relevant issue with modern operating systems. Therefore, this issue has not been addressed at this moment. However, assertions have been included that should trigger when this situation occurs. Whenever an assertion fires in the PLI module, please report it. The same holds for Python exceptions that cannot be easily explained. .. _cosim-impl-vhdl: What about VHDL? ---------------- It would be nice to have an interface to VHDL simulators such as the Modelsim VHDL simulator. Let us summarize the requirements to accomplish that: * We need a procedural interface to the internals of the simulator. * The procedural interface should be a widely used industry standard so that we can reuse the work in several simulators. * MyHDL is an open-source project and therefore there should be also be an open-source simulator that implements the procedural interface. ``vpi`` for Verilog matches these requirements. It is a widely used standard and is supported by the open-source Verilog simulators Icarus and cver. However, for VHDL the situation is different. While there exists a standard called ``vhpi``, it much less popular than ``vpi``. Also, to our knowledge there is only one credible open source VHDL simulator (GHDL) and it is unclear whether it has ``vhpi`` capabilities that are powerful enough for MyHDL's purposes. Consequently, the development of co-simulation for VHDL is currently on hold. For some applications, there is an alternative: see :ref:`conv-testbench`. myhdl-0.11/doc/source/manual/highlevel.rst000066400000000000000000000453421347432460400206120ustar00rootroot00000000000000.. currentmodule:: myhdl .. _model-hl: ******************* High level modeling ******************* Introduction ============ .. index:: single: modeling; high level To write synthesizable models in MyHDL, you should stick to the RTL templates shown in :ref:`model-rtl`. However, modeling in MyHDL is much more powerful than that. Conceptually, MyHDL is a library for general event-driven modeling and simulation of hardware systems. There are many reasons why it can be useful to model at a higher abstraction level than RTL. For example, you can use MyHDL to verify architectural features, such as system throughput, latency and buffer sizes. You can also write high level models for specialized technology-dependent cores that are not going through synthesis. Last but not least, you can use MyHDL to write test benches that verify a system model or a synthesizable description. This chapter explores some of the options for high level modeling with MyHDL. .. _model-bfm: Modeling with bus-functional procedures ======================================= .. index:: single: bus-functional procedure A :dfn:`bus-functional procedure` is a reusable encapsulation of the low-level operations needed to implement some abstract transaction on a physical interface. Bus-functional procedures are typically used in flexible verification environments. .. % Once again, MyHDL uses generator functions to support bus-functional procedures. In MyHDL, the difference between instances and bus-functional procedure calls comes from the way in which a generator function is used. As an example, we will design a bus-functional procedure of a simplified UART transmitter. We assume 8 data bits, no parity bit, and a single stop bit, and we add print statements to follow the simulation behavior:: T_9600 = int(1e9 / 9600) def rs232_tx(tx, data, duration=T_9600): """ Simple rs232 transmitter procedure. tx -- serial output data data -- input data byte to be transmitted duration -- transmit bit duration """ print "-- Transmitting %s --" % hex(data) print "TX: start bit" tx.next = 0 yield delay(duration) for i in range(8): print "TX: %s" % data[i] tx.next = data[i] yield delay(duration) print "TX: stop bit" tx.next = 1 yield delay(duration) This looks exactly like the generator functions in previous sections. It becomes a bus-functional procedure when we use it differently. Suppose that in a test bench, we want to generate a number of data bytes to be transmitted. This can be modeled as follows:: testvals = (0xc5, 0x3a, 0x4b) def stimulus(): tx = Signal(1) for val in testvals: txData = intbv(val) yield rs232_tx(tx, txData) .. index:: single: wait; for the completion of a generator We use the bus-functional procedure call as a clause in a ``yield`` statement. This introduces a fourth form of the ``yield`` statement: using a generator as a clause. Although this is a more dynamic usage than in the previous cases, the meaning is actually very similar: at that point, the original generator should wait for the completion of a generator. In this case, the original generator resumes when the ``rs232_tx(tx, txData)`` generator returns. .. % When simulating this, we get:: -- Transmitting 0xc5 -- TX: start bit TX: 1 TX: 0 TX: 1 TX: 0 TX: 0 TX: 0 TX: 1 TX: 1 TX: stop bit -- Transmitting 0x3a -- TX: start bit TX: 0 TX: 1 TX: 0 TX: 1 ... We will continue with this example by designing the corresponding UART receiver bus-functional procedure. This will allow us to introduce further capabilities of MyHDL and its use of the ``yield`` statement. .. index:: single: sensitivity list Until now, the ``yield`` statements had a single clause. However, they can have multiple clauses as well. In that case, the generator resumes as soon as the wait condition specified by one of the clauses is satisfied. This corresponds to the functionality of sensitivity lists in Verilog and VHDL. .. % For example, suppose we want to design an UART receive procedure with a timeout. We can specify the timeout condition while waiting for the start bit, as in the following generator function:: def rs232_rx(rx, data, duration=T_9600, timeout=MAX_TIMEOUT): """ Simple rs232 receiver procedure. rx -- serial input data data -- data received duration -- receive bit duration """ # wait on start bit until timeout yield rx.negedge, delay(timeout) if rx == 1: raise StopSimulation, "RX time out error" # sample in the middle of the bit duration yield delay(duration // 2) print "RX: start bit" for i in range(8): yield delay(duration) print "RX: %s" % rx data[i] = rx yield delay(duration) print "RX: stop bit" print "-- Received %s --" % hex(data) If the timeout condition is triggered, the receive bit ``rx`` will still be ``1``. In that case, we raise an exception to stop the simulation. The ``StopSimulation`` exception is predefined in MyHDL for such purposes. In the other case, we proceed by positioning the sample point in the middle of the bit duration, and sampling the received data bits. When a ``yield`` statement has multiple clauses, they can be of any type that is supported as a single clause, including generators. For example, we can verify the transmitter and receiver generator against each other by yielding them together, as follows:: def test(): tx = Signal(1) rx = tx rxData = intbv(0) for val in testvals: txData = intbv(val) yield rs232_rx(rx, rxData), rs232_tx(tx, txData) Both forked generators will run concurrently, and the original generator will resume as soon as one of them finishes (which will be the transmitter in this case). The simulation output shows how the UART procedures run in lockstep:: -- Transmitting 0xc5 -- TX: start bit RX: start bit TX: 1 RX: 1 TX: 0 RX: 0 TX: 1 RX: 1 TX: 0 RX: 0 TX: 0 RX: 0 TX: 0 RX: 0 TX: 1 RX: 1 TX: 1 RX: 1 TX: stop bit RX: stop bit -- Received 0xc5 -- -- Transmitting 0x3a -- TX: start bit RX: start bit TX: 0 RX: 0 ... For completeness, we will verify the timeout behavior with a test bench that disconnects the ``rx`` from the ``tx`` signal, and we specify a small timeout for the receive procedure:: def testTimeout(): tx = Signal(1) rx = Signal(1) rxData = intbv(0) for val in testvals: txData = intbv(val) yield rs232_rx(rx, rxData, timeout=4*T_9600-1), rs232_tx(tx, txData) The simulation now stops with a timeout exception after a few transmit cycles:: -- Transmitting 0xc5 -- TX: start bit TX: 1 TX: 0 TX: 1 StopSimulation: RX time out error Recall that the original generator resumes as soon as one of the forked generators returns. In the previous cases, this is just fine, as the transmitter and receiver generators run in lockstep. However, it may be desirable to resume the caller only when *all* of the forked generators have finished. For example, suppose that we want to characterize the robustness of the transmitter and receiver design to bit duration differences. We can adapt our test bench as follows, to run the transmitter at a faster rate:: T_10200 = int(1e9 / 10200) def testNoJoin(): tx = Signal(1) rx = tx rxData = intbv(0) for val in testvals: txData = intbv(val) yield rs232_rx(rx, rxData), rs232_tx(tx, txData, duration=T_10200) Simulating this shows how the transmission of the new byte starts before the previous one is received, potentially creating additional transmission errors:: -- Transmitting 0xc5 -- TX: start bit RX: start bit ... TX: 1 RX: 1 TX: 1 TX: stop bit RX: 1 -- Transmitting 0x3a -- TX: start bit RX: stop bit -- Received 0xc5 -- RX: start bit TX: 0 It is more likely that we want to characterize the design on a byte by byte basis, and align the two generators before transmitting each byte. In MyHDL, this is done with the :func:`join` function. By joining clauses together in a ``yield`` statement, we create a new clause that triggers only when all of its clause arguments have triggered. For example, we can adapt the test bench as follows:: def testJoin(): tx = Signal(1) rx = tx rxData = intbv(0) for val in testvals: txData = intbv(val) yield join(rs232_rx(rx, rxData), rs232_tx(tx, txData, duration=T_10200)) Now, transmission of a new byte only starts when the previous one is received:: -- Transmitting 0xc5 -- TX: start bit RX: start bit ... TX: 1 RX: 1 TX: 1 TX: stop bit RX: 1 RX: stop bit -- Received 0xc5 -- -- Transmitting 0x3a -- TX: start bit RX: start bit TX: 0 RX: 0 .. _model-mem: Modeling memories with built-in types ===================================== .. index:: single: modeling; memories Python has powerful built-in data types that can be useful to model hardware memories. This can be merely a matter of putting an interface around some data type operations. For example, a :dfn:`dictionary` comes in handy to model sparse memory structures. (In other languages, this data type is called :dfn:`associative array`, or :dfn:`hash table`.) A sparse memory is one in which only a small part of the addresses is used in a particular application or simulation. Instead of statically allocating the full address space, which can be large, it is better to dynamically allocate the needed storage space. This is exactly what a dictionary provides. The following is an example of a sparse memory model:: def sparseMemory(dout, din, addr, we, en, clk): """ Sparse memory model based on a dictionary. Ports: dout -- data out din -- data in addr -- address bus we -- write enable: write if 1, read otherwise en -- interface enable: enabled if 1 clk -- clock input """ memory = {} @always(clk.posedge) def access(): if en: if we: memory[addr.val] = din.val else: dout.next = memory[addr.val] return access Note how we use the ``val`` attribute of the ``din`` signal, as we don't want to store the signal object itself, but its current value. Similarly, we use the ``val`` attribute of the ``addr`` signal as the dictionary key. In many cases, MyHDL code uses a signal's current value automatically when there is no ambiguity: for example, when a signal is used in an expression. However, in other cases, such as in this example, you have to refer to the value explicitly: for example, when the Signal is used as a dictionary key, or when it is not used in an expression. One option is to use the ``val`` attribute, as in this example. Another possibility is to use the ``int()`` or ``bool()`` functions to typecast the Signal to an integer or a boolean value. These functions are also useful with :class:`intbv` objects. As a second example, we will demonstrate how to use a list to model a synchronous fifo:: def fifo(dout, din, re, we, empty, full, clk, maxFilling=sys.maxint): """ Synchronous fifo model based on a list. Ports: dout -- data out din -- data in re -- read enable we -- write enable empty -- empty indication flag full -- full indication flag clk -- clock input Optional parameter: maxFilling -- maximum fifo filling, "infinite" by default """ memory = [] @always(clk.posedge) def access(): if we: memory.insert(0, din.val) if re: dout.next = memory.pop() filling = len(memory) empty.next = (filling == 0) full.next = (filling == maxFilling) return access Again, the model is merely a MyHDL interface around some operations on a list: :func:`insert` to insert entries, :func:`pop` to retrieve them, and :func:`len` to get the size of a Python object. .. _model-err: Modeling errors using exceptions ================================ In the previous section, we used Python data types for modeling. If such a type is used inappropriately, Python's run time error system will come into play. For example, if we access an address in the :func:`sparseMemory` model that was not initialized before, we will get a traceback similar to the following (some lines omitted for clarity):: Traceback (most recent call last): ... File "sparseMemory.py", line 31, in access dout.next = memory[addr.val] KeyError: Signal(51) Similarly, if the ``fifo`` is empty, and we attempt to read from it, we get:: Traceback (most recent call last): ... File "fifo.py", line 34, in fifo dout.next = memory.pop() IndexError: pop from empty list Instead of these low level errors, it may be preferable to define errors at the functional level. In Python, this is typically done by defining a custom ``Error`` exception, by subclassing the standard ``Exception`` class. This exception is then raised explicitly when an error condition occurs. For example, we can change the :func:`sparseMemory` function as follows (with the doc string is omitted for brevity):: class Error(Exception): pass def sparseMemory2(dout, din, addr, we, en, clk): memory = {} @always(clk.posedge) def access(): if en: if we: memory[addr.val] = din.val else: try: dout.next = memory[addr.val] except KeyError: raise Error, "Uninitialized address %s" % hex(addr) return access This works by catching the low level data type exception, and raising the custom exception with an appropriate error message instead. If the :func:`sparseMemory` function is defined in a module with the same name, an access error is now reported as follows:: Traceback (most recent call last): ... File "sparseMemory.py", line 61, in access raise Error, "Uninitialized address %s" % hex(addr) Error: Uninitialized address 0x33 Likewise, the :func:`fifo` function can be adapted as follows, to report underflow and overflow errors:: class Error(Exception): pass def fifo2(dout, din, re, we, empty, full, clk, maxFilling=sys.maxint): memory = [] @always(clk.posedge) def access(): if we: memory.insert(0, din.val) if re: try: dout.next = memory.pop() except IndexError: raise Error, "Underflow -- Read from empty fifo" filling = len(memory) empty.next = (filling == 0) full.next = (filling == maxFilling) if filling > maxFilling: raise Error, "Overflow -- Max filling %s exceeded" % maxFilling return access In this case, the underflow error is detected as before, by catching a low level exception on the list data type. On the other hand, the overflow error is detected by a regular check on the length of the list. .. _model-obj: Object oriented modeling ======================== .. index:: single: modeling; object oriented The models in the previous sections used high-level built-in data types internally. However, they had a conventional RTL-style interface. Communication with such a module is done through signals that are attached to it during instantiation. A more advanced approach is to model hardware blocks as objects. Communication with objects is done through method calls. A method encapsulates all details of a certain task performed by the object. As an object has a method interface instead of an RTL-style hardware interface, this is a much higher level approach. As an example, we will design a synchronized queue object. Such an object can be filled by producer, and independently read by a consumer. When the queue is empty, the consumer should wait until an item is available. The queue can be modeled as an object with a :meth:`put(item)` and a :meth:`get` method, as follows:: from myhdl import * def trigger(event): event.next = not event class queue: def __init__(self): self.l = [] self.sync = Signal(0) self.item = None def put(self,item): # non time-consuming method self.l.append(item) trigger(self.sync) def get(self): # time-consuming method if not self.l: yield self.sync self.item = self.l.pop(0) The :class:`queue` object constructor initializes an internal list to hold items, and a *sync* signal to synchronize the operation between the methods. Whenever :meth:`put` puts an item in the queue, the signal is triggered. When the :meth:`get` method sees that the list is empty, it waits on the trigger first. :meth:`get` is a generator method because it may consume time. As the ``yield`` statement is used in MyHDL for timing control, the method cannot "yield" the item. Instead, it makes it available in the *item* instance variable. To test the queue operation, we will model a producer and a consumer in the test bench. As a waiting consumer should not block a whole system, it should run in a concurrent "thread". As always in MyHDL, concurrency is modeled by Python generators. Producer and consumer will thus run independently, and we will monitor their operation through some print statements:: q = queue() def Producer(q): yield delay(120) for i in range(5): print "%s: PUT item %s" % (now(), i) q.put(i) yield delay(max(5, 45 - 10*i)) def Consumer(q): yield delay(100) while 1: print "%s: TRY to get item" % now() yield q.get() print "%s: GOT item %s" % (now(), q.item) yield delay(30) def main(): P = Producer(q) C = Consumer(q) return P, C sim = Simulation(main()) sim.run() Note that the generator method :meth:`get` is called in a ``yield`` statement in the :func:`Consumer` function. The new generator will take over from :func:`Consumer`, until it is done. Running this test bench produces the following output:: % python queue.py 100: TRY to get item 120: PUT item 0 120: GOT item 0 150: TRY to get item 165: PUT item 1 165: GOT item 1 195: TRY to get item 200: PUT item 2 200: GOT item 2 225: PUT item 3 230: TRY to get item 230: GOT item 3 240: PUT item 4 260: TRY to get item 260: GOT item 4 290: TRY to get item StopSimulation: No more events myhdl-0.11/doc/source/manual/hwtypes.rst000066400000000000000000000265221347432460400203450ustar00rootroot00000000000000.. currentmodule:: myhdl .. testsetup:: * from myhdl import * .. _hwtypes: *********************** Hardware-oriented types *********************** .. _hwtypes-intbv: The :class:`intbv` class ======================== .. index:: single: intbv; basic usage Hardware design involves dealing with bits and bit-oriented operations. The standard Python type :class:`int` has most of the desired features, but lacks support for indexing and slicing. For this reason, MyHDL provides the :class:`intbv` class. The name was chosen to suggest an integer with bit vector flavor. :class:`intbv` works transparently with other integer-like types. Like class :class:`int`, it provides access to the underlying two's complement representation for bitwise operations. However, unlike :class:`int`, it is a mutable type. This means that its value can be changed after object creation, through methods and operators such as slice assignment. :class:`intbv` supports the same operators as :class:`int` for arithmetic. In addition, it provides a number of features to make it suitable for hardware design. First, the range of allowed values can be constrained. This makes it possible to check the value at run time during simulation. Moreover, back end tools can determine the smallest possible bit width for representing the object. Secondly, it supports bit level operations by providing an indexing and slicing interface. :class:`intbv` objects are constructed in general as follows:: intbv([val=None] [, min=None] [, max=None]) *val* is the initial value. *min* and *max* can be used to constrain the value. Following the Python conventions, *min* is inclusive, and *max* is exclusive. Therefore, the allowed value range is *min* .. *max*-1. Let's look at some examples. An unconstrained :class:`intbv` object is created as follows:: >>> a = intbv(24) .. index:: single: intbv; min single: intbv; max single: intbv; bit width After object creation, *min* and *max* are available as attributes for inspection. Also, the standard Python function :func:`len` can be used to determine the bit width. If we inspect the previously created object, we get:: >>> a intbv(24) >>> print(a.min) None >>> print(a.max) None >>> len(a) 0 As the instantiation was unconstrained, the *min* and *max* attributes are undefined. Likewise, the bit width is undefined, which is indicated by a return value ``0``. A constrained :class:`intbv` object is created as follows: >>> a = intbv(24, min=0, max=25) Inspecting the object now gives:: >>> a intbv(24) >>> a.min 0 >>> a.max 25 >>> len(a) 5 We see that the allowed value range is 0 .. 24, and that 5 bits are required to represent the object. The *min* and *max* bound attributes enable fine-grained control and error checking of the value range. In particular, the bound values do not have to be symmetric or powers of 2. In all cases, the bit width is set appropriately to represent the values in the range. For example:: >>> a = intbv(6, min=0, max=7) >>> len(a) 3 >>> a = intbv(6, min=-3, max=7) >>> len(a) 4 >>> a = intbv(6, min=-13, max=7) >>> len(a) 5 .. _hwtypes-indexing: Bit indexing ============ .. index:: single: bit indexing A common requirement in hardware design is access to the individual bits. The :class:`intbv` class implements an indexing interface that provides access to the bits of the underlying two's complement representation. The following illustrates bit index read access:: >>> from myhdl import bin >>> a = intbv(24) >>> bin(a) '11000' >>> int(a[0]) 0 >>> int(a[3]) 1 >>> b = intbv(-23) >>> bin(b) '101001' >>> int(b[0]) 1 >>> int(b[3]) 1 >>> int(b[4]) 0 We use the :func:`bin` function provide by MyHDL because it shows the two's complement representation for negative values, unlike Python's builtin with the same name. Note that lower indices correspond to less significant bits. The following code illustrates bit index assignment:: >>> bin(a) '11000' >>> a[3] = 0 >>> bin(a) '10000' >>> a intbv(16) >>> b intbv(-23) >>> bin(b) '101001' >>> b[3] = 0 >>> bin(b) '100001' >>> b intbv(-31) .. _hwtypes-slicing: Bit slicing =========== .. index:: single: bit slicing The :class:`intbv` type also supports bit slicing, for both read access assignment. For example:: >>> a = intbv(24) >>> bin(a) '11000' >>> a[4:1] intbv(4) >>> bin(a[4:1]) '100' >>> a[4:1] = 0b001 >>> bin(a) '10010' >>> a intbv(18) In accordance with the most common hardware convention, and unlike standard Python, slicing ranges are downward. As in standard Python, the slicing range is half-open: the highest index bit is not included. Unlike standard Python however, this index corresponds to the *leftmost* item. Both indices can be omitted from the slice. If the rightmost index is omitted, it is ``0`` by default. If the leftmost index is omitted, the meaning is to access "all" higher order bits. For example:: >>> bin(a) '11000' >>> bin(a[4:]) '1000' >>> a[4:] = '0001' >>> bin(a) '10001' >>> a[:] = 0b10101 >>> bin(a) '10101' The half-openness of a slice may seem awkward at first, but it helps to avoid one-off count issues in practice. For example, the slice ``a[8:]`` has exactly ``8`` bits. Likewise, the slice ``a[7:2]`` has ``7-2=5`` bits. You can think about it as follows: for a slice ``[i:j]``, only bits below index ``i`` are included, and the bit with index ``j`` is the last bit included. When an :class:`intbv` object is sliced, a new :class:`intbv` object is returned. This new :class:`intbv` object is always positive, and the value bounds are set up in accordance with the bit width specified by the slice. For example:: >>> a = intbv(6, min=-3, max=7) >>> len(a) 4 >>> b = a[4:] >>> b intbv(6L) >>> len(b) 4 >>> b.min 0 >>> b.max 16 In the example, the original object is sliced with a slice equal to its bit width. The returned object has the same value and bit width, but its value range consists of all positive values that can be represented by the bit width. The object returned by a slice is positive, even when the original object is negative:: >>> a = intbv(-3) >>> bin(a, width=5) '11101' >>> b = a[5:] >>> b intbv(29L) >>> bin(b) '11101' In this example, the bit pattern of the two objects is identical within the bit width, but their values have opposite sign. Sometimes hardware engineers prefer to constrain an object by defining its bit width directly, instead of the range of allowed values. Using the slicing properties of the :class:`intbv` class one can do that as follows:: >>> a = intbv(24)[5:] What actually happens here is that first an unconstrained :class:`intbv` is created, which is then sliced. Slicing an :class:`intbv` returns a new :class:`intbv` with the constraints set up appropriately. Inspecting the object now shows:: >>> a.min 0 >>> a.max 32 >>> len(a) 5 Note that the *max* attribute is 32, as with 5 bits it is possible to represent the range 0 .. 31. Creating an :class:`intbv` in this way is convenient but has the disadvantage that only positive value ranges between 0 and a power of 2 can be specified. .. _hwtypes-modbv: The :class:`modbv` class ======================== In hardware modeling, there is often a need for the elegant modeling of wrap-around behavior. :class:`intbv` instances do not support this automatically, as they assert that any assigned value is within the bound constraints. However, wrap-around modeling can be straightforward. For example, the wrap-around condition for a counter is often decoded explicitly, as it is needed for other purposes. Also, the modulo operator provides an elegant one-liner in many scenarios:: count.next = (count + 1) % 2**8 However, some interesting cases are not supported by the :class:`intbv` type. For example, we would like to describe a free running counter using a variable and augmented assignment as follows:: count_var += 1 This is not possible with the :class:`intbv` type, as we cannot add the modulo behavior to this description. A similar problem exist for an augmented left shift as follows:: shifter <<= 4 To support these operations directly, MyHDL provides the :class:`modbv` type. :class:`modbv` is implemented as a subclass of :class:`intbv`. The two classes have an identical interface and work together in a straightforward way for arithmetic operations. The only difference is how the bounds are handled: out-of-bound values result in an error with :class:`intbv`, and in wrap-around with :class:`modbv`. For example, the modulo counter above can be modeled as follows:: count = Signal(modbv(0, min=0, max=2**8)) ... count.next = count + 1 The wrap-around behavior is defined in general as follows:: val = (val - min) % (max - min) + min In a typical case when ``min==0``, this reduces to:: val = val % max .. _hwtypes-signed: Unsigned and signed representation ================================== .. index:: single: intbv; intbv.signed :class:`intbv` is designed to be as high level as possible. The underlying value of an :class:`intbv` object is a Python :class:`int`, which is represented as a two's complement number with "indefinite" bit width. The range bounds are only used for error checking, and to calculate the minimum required bit width for representation. As a result, arithmetic can be performed like with normal integers. In contrast, HDLs such as Verilog and VHDL typically require designers to deal with representational issues, especially for synthesizable code. They provide low-level types like ``signed`` and ``unsigned`` for arithmetic. The rules for arithmetic with such types are much more complicated than with plain integers. In some cases it can be useful to interpret :class:`intbv` objects in terms of "signed" and "unsigned". Basically, it depends on attribute *min*. if *min* < 0, then the object is "signed", otherwise it is "unsigned". In particular, the bit width of a "signed" object will account for a sign bit, but that of an "unsigned" will not, because that would be redundant. From earlier sections, we have learned that the return value from a slicing operation is always "unsigned". In some applications, it is desirable to convert an "unsigned" :class:`intbv` to a "signed", in other words, to interpret the msb bit as a sign bit. The msb bit is the highest order bit within the object's bit width. For this purpose, :class:`intbv` provides the :meth:`intbv.signed` method. For example:: >>> a = intbv(12, min=0, max=16) >>> bin(a) '1100' >>> b = a.signed() >>> b -4 >>> bin(b, width=4) '1100' :meth:`intbv.signed` extends the msb bit into the higher-order bits of the underlying object value, and returns the result as an integer. Naturally, for a "signed" the return value will always be identical to the original value, as it has the sign bit already. As an example let's take a 8 bit wide data bus that would be modeled as follows:: data_bus = intbv(0)[8:] Now consider that a complex number is transferred over this data bus. The upper 4 bits of the data bus are used for the real value and the lower 4 bits for the imaginary value. As real and imaginary values have a positive and negative value range, we can slice them off from the data bus and convert them as follows:: real.next = data_bus[8:4].signed() imag.next = data_bus[4:].signed() myhdl-0.11/doc/source/manual/index.rst000066400000000000000000000003751347432460400177470ustar00rootroot00000000000000******************** The MyHDL manual ******************** .. toctree:: :maxdepth: 2 preface background intro hwtypes structure rtl highlevel unittest cosimulation conversion conversion_examples reference myhdl-0.11/doc/source/manual/intro.rst000066400000000000000000000263771347432460400200050ustar00rootroot00000000000000.. currentmodule:: myhdl .. _intro: ********************* Introduction to MyHDL ********************* .. _intro-basic: A basic MyHDL simulation ======================== We will introduce MyHDL with a classic ``Hello World`` style example. All example code can be found in the distribution directory under :file:`example/manual/`. Here are the contents of a MyHDL simulation script called :file:`hello1.py`: .. include-example:: hello1.py When we run this simulation, we get the following output: .. run-example:: hello1.py The first line of the script imports a number of objects from the ``myhdl`` package. In Python we can only use identifiers that are literally defined in the source file. Then, we define a function called :func:`HelloWorld`. In MyHDL, a hardware module is modeled by a function decorated with the :func:`block` decorator. The name :dfn:`block` was chosen to avoid confusion with the Python concept of a module. We will use this terminology further on. The parameter list of the :func:`HelloWorld` function is used to define the interface of the hardware block. In this first example, the interface is empty. .. index:: single: decorator; always Inside the top level function we declare a local function called :func:`say_hello` that defines the desired behavior. This function is decorated with an :func:`always` decorator that has a :func:`delay` object as its parameter. The meaning is that the function will be executed whenever the specified delay interval has expired. Behind the curtains, the :func:`always` decorator creates a Python *generator* and reuses the name of the decorated function for it. Generators are the fundamental objects in MyHDL, and we will say much more about them further on. Finally, the top level function returns the :func:`say_hello` generator. This is the simplest case of the basic MyHDL code pattern to define the contents of a hardware block. We will describe the general case further on. In MyHDL, we create an *instance* of a hardware block by calling the corresponding function. The :func:`block` decorator make sure that the return value is actually an instance of a block class, with a useful API. In the example, variable ``inst`` refers to a :func:`HelloWorld` block instance. To simulate the instance, we use its :meth:`run_sim` method. We can use it to run the simulation for the desired amount of timesteps. .. _intro-conc: Signals and concurrency ======================= An actual hardware design is typically massively concurrent, which means that a large amount of functional units are running in parallel. MyHDL supports this behavior by allowing an arbitrary number of concurrently running generators. With concurrency comes the problem of deterministic communication. Hardware languages use special objects to support deterministic communication between concurrent code. In particular, MyHDL has a :class:`Signal` object which is roughly modeled after VHDL signals. We will demonstrate signals and concurrency by extending and modifying our first example. We define a hardware block that contains two generators, one that drives a clock signal, and one that is sensitive to a positive edge on a clock signal: .. include-example:: hello2.py .. index:: single: VHDL; signal assignment single: Verilog; non-blocking assignment The clock driver function :func:`clk_driver` drives the clock signal. If defines a generator that continuously toggles a clock signal after a certain delay. A new value of a signal is specified by assigning to its ``next`` attribute. This is the MyHDL equivalent of the VHDL signal assignment and the Verilog non-blocking assignment. .. index:: single: wait; for a rising edge The :func:`say_hello` function is modified from the first example. It is made sensitive to a rising edge of the clock signal, specified by the ``posedge`` attribute of a signal. The edge specifier is the argument of the ``always`` decorator. As a result, the decorated function will be executed on every rising clock edge. The ``clk`` signal is constructed with an initial value ``0``. One generator drives it, the other is sensitive to it. The result of this communication is that the generators run in parallel, but that their actions are coordinated by the clock signal. When we run the simulation, we get: .. run-example:: hello2.py .. _intro-hier: Parameters, ports and hierarchy =============================== We have seen that MyHDL uses functions to model hardware blocks. So far these functions did not have parameters. However, to create general, reusable blocks we will need parameters. For example, we can create a clock driver block as follows: .. include-example:: ClkDriver.py The block encapsulates a clock driver generator. It has two parameters. The first parameter is *clk* is the clock signal. A asignal parameter is MyHDL's way to model a dfn:port:. The second parameter is the clock *period*, with a default value of ``20``. .. index:: single: decorator; instance As the low time of the clock may differ from the high time in case of an odd period, we cannot use the :func:`always` decorator with a single delay value anymore. Instead, the :func:`drive_clk` function is now a generator function with an explicit definition of the desired behavior. It is decorated with the :func:`instance` decorator. You can see that :func:`drive_clk` is a generator function because it contains ``yield`` statements. When a generator function is called, it returns a generator object. This is basically what the :func:`instance` decorator does. It is less sophisticated than the :func:`always` decorator, but it can be used to create a generator from any local generator function. The ``yield`` statement is a general Python construct, but MyHDL uses it in a specific way. It has a similar meaning as the wait statement in VHDL: the statement suspends execution of a generator, and its clauses specify the conditions on which the generator should wait before resuming. In this case, the generator waits for a certain delay. Note that to make sure that the generator runs "forever", we wrap its behavior in a ``while True`` loop. Similarly, we can define a general :func:`Hello` function as follows: .. include-example:: Hello.py .. index:: single: instance; defined We can create any number of instances by calling the functions with the appropriate parameters. Hierarchy can be modeled by defining the instances in a higher-level function, and returning them. This pattern can be repeated for an arbitrary number of hierarchical levels. Consequently, the general definition of a MyHDL instance is recursive: an instance is either a sequence of instances, or a generator. As an example, we will create a higher-level function with four instances of the lower-level functions, and simulate it: .. include-example:: greetings.py As in standard Python, positional or named parameter association can be used in instantiations, or a mix of both [#]_. All these styles are demonstrated in the example above. Named association can be very useful if there are a lot of parameters, as the argument order in the call does not matter in that case. The simulation produces the following output: .. run-example:: greetings.py Terminology review ================== Some commonly used terminology has different meanings in Python versus hardware design. For a good understanding, it is important to make these differences explicit. .. index:: single: module; in Python versus hardware design A :dfn:`module` in Python refers to all source code in a particular file. A module can be reused by other modules by importing it. In hardware design on the other hand, a module typically refers to a reusable unit of hardware with a well defined interface. Because these meanings are so different, the terminology chosen for a hardware module in MyHDL is *block* instead, as explained earlier in this chapter. A hardware block can can be reused in another block by :dfn:`instantiating` it. .. index:: single: instance; in Python versus hardware design An :dfn:`instance` in Python (and other object-oriented languages) refers to the object created by a class constructor. In hardware design, an instance is a particular incarnation of a hardware block, created by *instantiating* the block. In MyHDL, such as block instance is actually an instance of a particular class. Therefore, the two meanings are not exactly the same, but they coincide nicely. Normally, the meaning the words "block" and "instance" should be clear from the context. Sometimes, we qualify them with the words "hardware" or "MyHDL" for clarity. .. _intro-python: Some remarks on MyHDL and Python ================================ To conclude this introductory chapter, it is useful to stress that MyHDL is not a language in itself. The underlying language is Python, and MyHDL is implemented as a Python package called ``myhdl``. Moreover, it is a design goal to keep the ``myhdl`` package as minimalistic as possible, so that MyHDL descriptions are very much "pure Python". To have Python as the underlying language is significant in several ways: * Python is a very powerful high level language. This translates into high productivity and elegant solutions to complex problems. * Python is continuously improved by some very clever minds, supported by a large user base. Python profits fully from the open source development model. * Python comes with an extensive standard library. Some functionality is likely to be of direct interest to MyHDL users: examples include string handling, regular expressions, random number generation, unit test support, operating system interfacing and GUI development. In addition, there are modules for mathematics, database connections, networking programming, internet data handling, and so on. .. _intro-summary: Summary and perspective ======================= Here is an overview of what we have learned in this chapter: * Generators are the basic building blocks of MyHDL models. They provide the way to model massive concurrency and sensitivity lists. * MyHDL provides decorators that create useful generators from local functions and a decorator to create hardware blocks. * Hardware structure and hierarchy is described with Python functions, decorated with the :func:`block` decorator. * :class:`Signal` objects are used to communicate between concurrent generators. * A block instance provides a method to simulate it. These concepts are sufficient to start modeling and simulating with MyHDL. However, there is much more to MyHDL. Here is an overview of what can be learned from the following chapters: * MyHDL supports hardware-oriented types that make it easier to write typical hardware models. These are described in Chapter :ref:`hwtypes`. * MyHDL supports sophisticated and high level modeling techniques. This is described in Chapter :ref:`model-hl`. * MyHDL enables the use of modern software verification techniques, such as unit testing, on hardware designs. This is the topic of Chapter :ref:`unittest`. * It is possible to co-simulate MyHDL models with other HDL languages such as Verilog and VHDL. This is described in Chapter :ref:`cosim`. * Last but not least, MyHDL models can be converted to Verilog or VHDL, providing a path to a silicon implementation. This is the topic of Chapter :ref:`conv`. .. rubric:: Footnotes .. [#] All positional parameters have to go before any named parameter. myhdl-0.11/doc/source/manual/preface.rst000066400000000000000000000054431347432460400202460ustar00rootroot00000000000000******** Overview ******** The goal of the MyHDL project is to empower hardware designers with the elegance and simplicity of the Python language. MyHDL is a free, open-source package for using Python as a hardware description and verification language. Python is a very high level language, and hardware designers can use its full power to model and simulate their designs. Moreover, MyHDL can convert a design to Verilog or VHDL. This provides a path into a traditional design flow. *Modeling* Python's power and clarity make MyHDL an ideal solution for high level modeling. Python is famous for enabling elegant solutions to complex modeling problems. Moreover, Python is outstanding for rapid application development and experimentation. The key idea behind MyHDL is the use of Python generators to model hardware concurrency. Generators are best described as resumable functions. MyHDL generators are similar to always blocks in Verilog and processes in VHDL. A hardware module (called a *block* in MyHDL terminology) is modeled as a function that returns generators. This approach makes it straightforward to support features such as arbitrary hierarchy, named port association, arrays of instances, and conditional instantiation. Furthermore, MyHDL provides classes that implement traditional hardware description concepts. It provides a signal class to support communication between generators, a class to support bit oriented operations, and a class for enumeration types. *Simulation and Verification* The built-in simulator runs on top of the Python interpreter. It supports waveform viewing by tracing signal changes in a VCD file. With MyHDL, the Python unit test framework can be used on hardware designs. Although unit testing is a popular modern software verification technique, it is still uncommon in the hardware design world. MyHDL can also be used as hardware verification language for Verilog designs, by co-simulation with traditional HDL simulators. *Conversion to Verilog and VHDL* Subject to some limitations, MyHDL designs can be converted to Verilog or VHDL. This provides a path into a traditional design flow, including synthesis and implementation. The convertible subset is restricted, but much wider than the standard synthesis subset. It includes features that can be used for high level modeling and test benches. The converter works on an instantiated design that has been fully elaborated. Consequently, the original design structure can be arbitrarily complex. Moreover, the conversion limitations apply only to code inside generators. Outside generators, Python's full power can be used without compromising convertibility. Finally, the converter automates a number of tasks that are hard in Verilog or VHDL directly. A notable feature is the automated handling of signed arithmetic issues. myhdl-0.11/doc/source/manual/reference.rst000066400000000000000000001012201347432460400205650ustar00rootroot00000000000000.. module:: myhdl .. _ref: ********* Reference ********* MyHDL is implemented as a Python package called :mod:`myhdl`. This chapter describes the objects that are exported by this package. .. _ref-sim: Simulation ========== .. _ref-simclass: The :class:`Simulation` class ----------------------------- .. class:: Simulation(arg [, arg ...]) Class to construct a new simulation. Each argument should be a MyHDL instance. In MyHDL, an instance is recursively defined as being either a sequence of instances, or a MyHDL generator, or a Cosimulation object. See section :ref:`ref-gen` for the definition of MyHDL generators and their interaction with a :class:`Simulation` object. See Section :ref:`ref-cosim` for the :class:`Cosimulation` object. At most one :class:`Cosimulation` object can be passed to a :class:`Simulation` constructor. A :class:`Simulation` object has the following method: .. method:: Simulation.run([duration]) Run the simulation forever (by default) or for a specified duration. .. method:: Simulation.quit() Quit the simulation after it has run for a specified duration. The method should be called (the simulation instance must be quit) before another simulation instance is created. The method is called by default when the simulation is run forever. .. _ref-simsupport: Simulation support functions ---------------------------- .. function:: now() Returns the current simulation time. .. exception:: StopSimulation() Base exception that is caught by the ``Simulation.run()`` method to stop a simulation. .. _ref-trace: Waveform tracing ---------------- .. function:: traceSignals(func [, *args] [, **kwargs]) Enables signal tracing to a VCD file for waveform viewing. *func* is a function that returns an instance. :func:`traceSignals` calls *func* under its control and passes *\*args* and *\*\*kwargs* to the call. In this way, it finds the hierarchy and the signals to be traced. The return value is the same as would be returned by the call ``func(*args, **kwargs)``. The top-level instance name and the basename of the VCD output filename is ``func.func_name`` by default. If the VCD file exists already, it will be moved to a backup file by attaching a timestamp to it, before creating the new file. The ``traceSignals`` callable has the following attribute: .. attribute:: name This attribute is used to overwrite the default top-level instance name and the basename of the VCD output filename. .. attribute:: directory This attribute is used to set the directory to which VCD files are written. By default, the current working directory is used. .. attribute:: filename This attribute is used to set the filename to which VCD files are written. By default, the name attribbute is used. .. attribute:: timescale This attribute is used to set the timescale corresponding to unit steps, according to the VCD format. The assigned value should be a string. The default timescale is "1ns". .. _ref-model: Modeling ======== .. _ref-block: The `block` decorator --------------------- .. function:: block() The `block` decorator enables a method-based API which is more consistent, simplifies implementation, and reduces the size of the `myhdl` namespace. The methods work on block instances, created by calling a function decorated with the `block` decorator:: @block def myblock(): ... return inst = myblock() # inst supports the methods of the block instance API The API on a block instance looks as follows: .. method:: .run_sim(duration=None) Run a simulation "forever" (default) or for a specified duration. .. method:: .config_sim(backend='myhdl', trace=False) Optional simulation configuration: *backend*: Defaults to 'myhdl *trace*: Enable waveform tracing, default False. .. method:: .quit_sim() Quit an active simulation. This is method is currently required because only a single simulation can be active. .. method:: .convert(hdl='Verilog', **kwargs) Converts MyHDL code to a target HDL. *hdl*: 'VHDL' or 'Verilog'. Defaults to Verilog. Supported keyword arguments: *path*: Destination folder. Defaults to current working dir. *name*: Module and output file name. Defaults to `self.mod.__name__`. *trace*: Whether the testbench should dump all signal waveforms. Defaults to False. *testbench*: Verilog only. Specifies whether a testbench should be created. Defaults to True. *timescale*: timescale parameter. Defaults to '1ns/10ps'. Verilog only. .. method:: .verify_convert() Verify conversion output, by comparing target HDL simulation log with MyHDL simulation log. .. method:: .analyze_convert() Analyze conversion output by compilation with target HDL compiler. .. _ref-sig: Signals ------- The :class:`SignalType` type ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ .. class:: SignalType This type is the abstract base type of all signals. It is not used to construct signals, but it can be used to check whether an object is a signal. Regular signals ^^^^^^^^^^^^^^^ .. class:: Signal([val=None] [, delay=0]) This class is used to construct a new signal and to initialize its value to *val*. Optionally, a delay can be specified. A :class:`Signal` object has the following attributes: .. attribute:: posedge Attribute that represents the positive edge of a signal, to be used in sensitivity lists. .. attribute:: negedge Attribute that represents the negative edge of a signal, to be used in sensitivity lists. .. attribute:: next Read-write attribute that represents the next value of the signal. .. attribute:: val Read-only attribute that represents the current value of the signal. This attribute is always available to access the current value; however in many practical case it will not be needed. Whenever there is no ambiguity, the Signal object's current value is used implicitly. In particular, all Python's standard numeric, bit-wise, logical and comparison operators are implemented on a Signal object by delegating to its current value. The exception is augmented assignment. These operators are not implemented as they would break the rule that the current value should be a read-only attribute. In addition, when a Signal object is assigned to the ``next`` attribute of another Signal object, its current value is assigned instead. .. attribute:: min Read-only attribute that is the minimum value (inclusive) of a numeric signal, or ``None`` for no minimum. .. attribute:: max Read-only attribute that is the maximum value (exclusive) of a numeric signal, or ``None`` for no maximum. .. attribute:: driven Writable attribute that can be used to indicate that the signal is supposed to be driven from the MyHDL code, and possibly how it should be declared in Verilog after conversion. The allowed values are ``'reg'``, ``'wire'``, ``True`` and ``False``. This attribute is useful when the converter cannot infer automatically whether and how a signal is driven. This occurs when the signal is driven from user-defined code. ``'reg'`` and ``'wire'`` are "true" values that permit finer control for the Verilog case. .. attribute:: read Writable boolean attribute that can be used to indicate that the signal is read. This attribute is useful when the converter cannot infer automatically whether a signal is read. This occurs when the signal is read from user-defined code. A :class:`Signal` object also has a call interface: .. method:: Signal.__call__(left[, right=None]) This method returns a :class:`_SliceSignal` shadow signal. .. class:: ResetSignal(val, active, isasync) This Signal subclass defines reset signals. *val*, *active*, and *isasync* are mandatory arguments. *val* is a boolean value that specifies the initial value, *active* is a boolean value that specifies the active level. *isasync* is a boolean value that specifies the reset style: asynchronous (``True``) or synchronous (``False``). This class should be used in conjunction with the :func:`always_seq` decorator. Shadow signals ^^^^^^^^^^^^^^ .. class:: _SliceSignal(sig, left[, right=None]) This class implements read-only structural slicing and indexing. It creates a new shadow signal of the slice or index of the parent signal *sig*. If the *right* parameter is omitted, you get indexing instead of slicing. Parameters *left* and *right* have the usual meaning for slice indices: in particular, *left* is non-inclusive but *right* is inclusive. *sig* should be appropriate for slicing and indexing, which means it should be based on :class:`intbv` in practice. The class constructor is not intended to be used explicitly. Instead, use the call interface of a regular signal.The following calls are equivalent:: sl = _SliceSignal(sig, left, right) sl = sig(left, right) .. class:: ConcatSignal(*args) This class creates a new shadow signal of the concatenation of its arguments. You can pass an arbitrary number of arguments to the constructor. The arguments should be bit-oriented with a defined number of bits. The following argument types are supported: :class:`intbv` objects with a defined bit width, :class:`bool` objects, signals of the previous objects, and bit strings. The new signal follows the value changes of the signal arguments. The non-signal arguments are used to define constant values in the concatenation. .. class:: TristateSignal(val) This class is used to construct a new tristate signal. The underlying type is specified by the *val* parameter. It is a Signal subclass and has the usual attributes, with one exception: it doesn't support the ``next`` attribute. Consequently, direct signal assignment to a tristate signal is not supported. The initial value is the tristate value ``None``. The current value of a tristate is determined by resolving the values from its drivers. When exactly one driver value is different from ``None``, that is the resolved value; otherwise it is ``None``. When more than one driver value is different from ``None``, a contention warning is issued. This class has the following method: .. method:: driver() Returns a new driver to the tristate signal. It is initialized to ``None``. A driver object is an instance of a special :class:`SignalType` subclass. In particular, its ``next`` attribute can be used to assign a new value to it. .. _ref-gen: MyHDL generators and trigger objects ------------------------------------ .. index:: single: sensitivity list MyHDL generators are standard Python generators with specialized :keyword:`yield` statements. In hardware description languages, the equivalent statements are called *sensitivity lists*. The general format of :keyword:`yield` statements in in MyHDL generators is: :keyword:`yield` clause [, clause ...] When a generator executes a :keyword:`yield` statement, its execution is suspended at that point. At the same time, each *clause* is a *trigger object* which defines the condition upon which the generator should be resumed. However, per invocation of a :keyword:`yield` statement, the generator resumes exactly once, regardless of the number of clauses. This happens on the first trigger that occurs. In this section, the trigger objects and their functionality will be described. Some MyHDL objects that are described elsewhere can directly be used as trigger objects. In particular, a :class:`Signal` can be used as a trigger object. Whenever a signal changes value, the generator resumes. Likewise, the objects referred to by the signal attributes ``posedge`` and ``negedge`` are trigger objects. The generator resumes on the occurrence of a positive or a negative edge on the signal, respectively. An edge occurs when there is a change from false to true (positive) or vice versa (negative). For the full description of the :class:`Signal` class and its attributes, see section :ref:`ref-sig`. Furthermore, MyHDL generators can be used as clauses in ``yield`` statements. Such a generator is forked, and starts operating immediately, while the original generator waits for it to complete. The original generator resumes when the forked generator returns. In addition, the following functions return trigger objects: .. function:: delay(t) Return a trigger object that specifies that the generator should resume after a delay *t*. .. function:: join(arg [, arg ...]) Join a number of trigger objects together and return a joined trigger object. The effect is that the joined trigger object will trigger when *all* of its arguments have triggered. Finally, as a special case, the Python ``None`` object can be present in a ``yield`` statement. It is the do-nothing trigger object. The generator immediately resumes, as if no ``yield`` statement were present. This can be useful if the ``yield`` statement also has generator clauses: those generators are forked, while the original generator resumes immediately. .. _ref-deco: Decorator functions to create generators ---------------------------------------- MyHDL defines a number of decorator functions, that make it easier to create generators from local generator functions. .. function:: instance() The :func:`instance` decorator is the most general decorator. It automatically creates a generator by calling the decorated generator function. It is used as follows:: def top(...): ... @instance def inst(): ... return inst, ... This is equivalent to:: def top(...): ... def _gen_func(): ... inst = _gen_func() ... return inst, ... .. function:: always(arg [, *args]) The :func:`always` decorator is a specialized decorator that targets a widely used coding pattern. It is used as follows:: def top(...): ... @always(event1, event2, ...) def inst() ... return inst, ... This is equivalent to the following:: def top(...): ... def _func(): def _gen_func() while True: yield event1, event2, ... _func() ... inst = _gen_func() ... return inst, ... The argument list of the decorator corresponds to the sensitivity list. Only signals, edge specifiers, or delay objects are allowed. The decorated function should be a classic function. .. function:: always_comb() The :func:`always_comb` decorator is used to describe combinatorial logic. :: def top(...): ... @always_comb def comb_inst(): ... return comb_inst, ... The :func:`always_comb` decorator infers the inputs of the combinatorial logic and the corresponding sensitivity list automatically. The decorated function should be a classic function. .. function:: always_seq(edge, reset) The :func:`always_seq` decorator is used to describe sequential (clocked) logic. The *edge* parameter should be a clock edge (``clock.posedge`` or ``clock.negedge``). The *reset* parameter should a :class:`ResetSignal` object. MyHDL data types ---------------- MyHDL defines a number of data types that are useful for hardware description. .. _ref-intbv: The :class:`intbv` class ^^^^^^^^^^^^^^^^^^^^^^^^ .. class:: intbv([val=0] [, min=None] [, max=None]) This class represents :class:`int`\ -like objects with some additional features that make it suitable for hardware design. The *val* argument can be an :class:`int`, a :class:`long`, an :class:`intbv` or a bit string (a string with only '0's or '1's). For a bit string argument, the value is calculated as in ``int(bitstring, 2)``. The optional *min* and *max* arguments can be used to specify the minimum and maximum value of the :class:`intbv` object. As in standard Python practice for ranges, the minimum value is inclusive and the maximum value is exclusive. The minimum and maximum values of an :class:`intbv` object are available as attributes: .. attribute:: min Read-only attribute that is the minimum value (inclusive) of an :class:`intbv`, or *None* for no minimum. .. attribute:: max Read-only attribute that is the maximum value (exclusive) of an :class:`intbv`, or *None* for no maximum. .. method:: signed() Interprets the msb bit as as sign bit and extends it into the higher-order bits of the underlying object value. The msb bit is the highest-order bit within the object's bit width. :rtype: integer Unlike :class:`int` objects, :class:`intbv` objects are mutable; this is also the reason for their existence. Mutability is needed to support assignment to indexes and slices, as is common in hardware design. For the same reason, :class:`intbv` is not a subclass from :class:`int`, even though :class:`int` provides most of the desired functionality. (It is not possible to derive a mutable subtype from an immutable base type.) An :class:`intbv` object supports the same comparison, numeric, bitwise, logical, and conversion operations as :class:`int` objects. See http://www.python.org/doc/current/lib/typesnumeric.html for more information on such operations. In all binary operations, :class:`intbv` objects can work together with :class:`int` objects. For mixed-type numeric operations, the result type is an :class:`int` or a :class:`long`. For mixed-type bitwise operations, the result type is an :class:`intbv`. In addition, :class:`intbv` supports a number of sequence operators. In particular, the :func:`len` function returns the object's bit width. Furthermore, :class:`intbv` objects support indexing and slicing operations: +-----------------+---------------------------------+--------+ | Operation | Result | Notes | +=================+=================================+========+ | ``bv[i]`` | item *i* of *bv* | \(1) | +-----------------+---------------------------------+--------+ | ``bv[i] = x`` | item *i* of *bv* is replaced by | \(1) | | | *x* | | +-----------------+---------------------------------+--------+ | ``bv[i:j]`` | slice of *bv* from *i* downto | (2)(3) | | | *j* | | +-----------------+---------------------------------+--------+ | ``bv[i:j] = t`` | slice of *bv* from *i* downto | (2)(4) | | | *j* is replaced by *t* | | +-----------------+---------------------------------+--------+ (1) Indexing follows the most common hardware design conventions: the lsb bit is the rightmost bit, and it has index 0. This has the following desirable property: if the :class:`intbv` value is decomposed as a sum of powers of 2, the bit with index *i* corresponds to the term ``2**i``. (2) In contrast to standard Python sequencing conventions, slicing range are downward. This is a consequence of the indexing convention, combined with the common convention that the most significant digits of a number are the leftmost ones. The Python convention of half-open ranges is followed: the bit with the highest index is not included. However, it is the *leftmost* bit in this case. As in standard Python, this takes care of one-off issues in many practical cases: in particular, ``bv[i:]`` returns *i* bits; ``bv[i:j]`` has ``i-j`` bits. When the low index *j* is omitted, it defaults to ``0``. When the high index *i* is omitted, it means "all" higher order bits. (3) The object returned from a slicing access operation is always a positive :class:`intbv`; higher order bits are implicitly assumed to be zero. The bit width is implicitly stored in the return object, so that it can be used in concatenations and as an iterator. In addition, for a bit width w, the *min* and *max* attributes are implicitly set to ``0`` and ``2**w``, respectively. (4) When setting a slice to a value, it is checked whether the slice is wide enough. In addition, an :class:`intbv` object supports the iterator protocol. This makes it possible to iterate over all its bits, from the high index to index 0. This is only possible for :class:`intbv` objects with a defined bit width. .. _ref-modvb: The :class:`modbv` class ^^^^^^^^^^^^^^^^^^^^^^^^ .. class:: modbv([val=0] [, min=None] [, max=None]) The :class:`modbv` class implements modular bit vector types. It is implemented as a subclass of :class:`intbv` and supports the same parameters and operators. The difference is in the handling of the *min* and *max* boundaries. Instead of throwing an exception when those constraints are exceeded, the value of :class:`modbv` objects wraps around according to the following formula:: val = (val - min) % (max - min) + min This formula is a generalization of modulo wrap-around behavior that is often useful when describing hardware system behavior. The :func:`enum` factory function ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ .. function:: enum(arg [, arg ...] [, encoding='binary']) Returns an enumeration type. The arguments should be string literals that represent the desired names of the enumeration type attributes. The returned type should be assigned to a type name. For example:: t_EnumType = enum('ATTR_NAME_1', 'ATTR_NAME_2', ...) The enumeration type identifiers are available as attributes of the type name, for example: ``t_EnumType.ATTR_NAME_1`` The optional keyword argument *encoding* specifies the encoding scheme used in Verilog output. The available encodings are ``'binary'``, ``'one_hot'``, and ``'one_cold'``. .. _ref-model-misc: Modeling support functions -------------------------- MyHDL defines a number of additional support functions that are useful for hardware description. :func:`bin` ^^^^^^^^^^^ .. function:: bin(num [, width]) Returns a bit string representation. If the optional *width* is provided, and if it is larger than the width of the default representation, the bit string is padded with the sign bit. This function complements the standard Python conversion functions ``hex`` and ``oct``. A binary string representation is often useful in hardware design. :rtype: string :func:`concat` ^^^^^^^^^^^^^^ .. function:: concat(base [, arg ...]) Returns an :class:`intbv` object formed by concatenating the arguments. The following argument types are supported: :class:`intbv` objects with a defined bit width, :class:`bool` objects, signals of the previous objects, and bit strings. All these objects have a defined bit width. The first argument *base* is special as it does not need to have a defined bit width. In addition to the previously mentioned objects, unsized :class:`intbv`, :class:`int` and :class:`long` objects are supported, as well as signals of such objects. :rtype: :class:`intbv` :func:`downrange` ^^^^^^^^^^^^^^^^^ .. function:: downrange(high [, low=0]) Generates a downward range list of integers. This function is modeled after the standard ``range`` function, but works in the downward direction. The returned interval is half-open, with the *high* index not included. *low* is optional and defaults to zero. This function is especially useful in conjunction with the :class:`intbv` class, that also works with downward indexing. :func:`instances` ^^^^^^^^^^^^^^^^^ .. function:: instances() Looks up all MyHDL instances in the local name space and returns them in a list. :rtype: list .. _ref-cosim: Co-simulation ============= .. _ref-cosim-myhdl: MyHDL ----- .. class:: Cosimulation(exe, **kwargs) Class to construct a new Cosimulation object. The *exe* argument is the command to execute an HDL simulation, which can be either a string of the entire command line or a list of strings. In the latter case, the first element is the executable, and subsequent elements are program arguments. Providing a list of arguments allows Python to correctly handle spaces or other characters in program arguments. The *kwargs* keyword arguments provide a named association between signals (regs & nets) in the HDL simulator and signals in the MyHDL simulator. Each keyword should be a name listed in a ``$to_myhdl`` or ``$from_myhdl`` call in the HDL code. Each argument should be a :class:`Signal` declared in the MyHDL code. .. _ref-cosim-verilog: Verilog ------- .. function:: $to_myhdl(arg, [, arg ...]) Task that defines which signals (regs & nets) should be read by the MyHDL simulator. This task should be called at the start of the simulation. .. function:: $from_myhdl(arg, [, arg ...]) Task that defines which signals should be driven by the MyHDL simulator. In Verilog, only regs can be specified. This task should be called at the start of the simulation. .. _ref-conv: Conversion to Verilog and VHDL ============================== .. _ref-conv-conv: Conversion ---------- .. function:: toVerilog(func [, *args] [, **kwargs]) Converts a MyHDL design instance to equivalent Verilog code, and also generates a test bench to verify it. *func* is a function that returns an instance. :func:`toVerilog` calls *func* under its control and passes *\*args* and *\*\*kwargs* to the call. The return value is the same as would be returned by the call ``func(*args, **kwargs)``. It should be assigned to an instance name. The top-level instance name and the basename of the Verilog output filename is ``func.func_name`` by default. For more information about the restrictions on convertible MyHDL code, see section :ref:`conv-subset` in Chapter :ref:`conv`. :func:`toVerilog` has the following attribute: .. attribute:: name This attribute is used to overwrite the default top-level instance name and the basename of the Verilog output filename. .. attribute:: directory This attribute is used to set the directory to which converted verilog files are written. By default, the current working directory is used. .. attribute:: timescale This attribute is used to set the timescale in Verilog format. The assigned value should be a string. The default timescale is "1ns/10ps". .. function:: toVHDL(func[, *args][, **kwargs]) Converts a MyHDL design instance to equivalent VHDL code. *func* is a function that returns an instance. :func:`toVHDL` calls *func* under its control and passes *\*args* and *\*\*kwargs* to the call. The return value is the same as would be returned by the call ``func(*args, **kwargs)``. It can be assigned to an instance name. The top-level instance name and the basename of the Verilog output filename is ``func.func_name`` by default. :func:`toVHDL` has the following attributes: .. attribute:: name This attribute is used to overwrite the default top-level instance name and the basename of the VHDL output. .. attribute:: directory This attribute is used to set the directory to which converted VHDL files are written. By default, the current working directory is used. .. attribute:: component_declarations This attribute can be used to add component declarations to the VHDL output. When a string is assigned to it, it will be copied to the appropriate place in the output file. .. attribute:: library This attribute can be used to set the library in the VHDL output file. The assigned value should be a string. The default library is ``work``. .. attribute:: std_logic_ports This boolean attribute can be used to have only ``std_logic`` type ports on the top-level interface (when ``True``) instead of the default ``signed/unsigned`` types (when ``False``, the default). .. _ref-conv-user: User-defined Verilog and VHDL code ---------------------------------- User-defined code can be inserted in the Verilog or VHDL output through the use of function attributes. Suppose a function :func:`` defines a hardware module. User-defined code can be specified for the function with the following function attributes: .. attribute:: .vhdl_code A template string for user-defined code in the VHDL output. .. attribute:: .verilog_code A template string for user-defined code in the Verilog output. When such a function attribute is defined, the normal conversion process is bypassed and the user-defined code is inserted instead. The template strings should be suitable for the standard :class:`string.Template` constructor. They can contain interpolation variables (indicated by a ``$`` prefix) for all signals in the context. Note that the function attribute can be defined anywhere where :func:`` is visible, either outside or inside the function itself. These function attributes cannot be used with generator functions or decorated local functions, as these are not elaborated before simulation or conversion. In other words, they can only be used with functions that define structure. Conversion output verification ============================== .. module:: myhdl.conversion MyHDL provides an interface to verify converted designs. This is used extensively in the package itself to verify the conversion functionality. This capability is exported by the package so that users can use it also. Verification interface ---------------------- All functions related to conversion verification are implemented in the :mod:`myhdl.conversion` package. .. function:: verify(func[, *args][, **kwargs]) Used like :func:`toVHDL()` and :func:`toVerilog()`. It converts MyHDL code, simulates both the MyHDL code and the HDL code and reports any differences. The default HDL simulator is GHDL. This function has the following attribute: .. attribute:: simulator Used to set the name of the HDL simulator. ``"GHDL"`` is the default. .. function:: analyze(func[, *args][, **kwargs]) Used like :func:`toVHDL()` and :func:`toVerilog()`. It converts MyHDL code, and analyzes the resulting HDL. Used to verify whether the HDL output is syntactically correct. This function has the following attribute: .. attribute:: simulator Used to set the name of the HDL simulator used to analyze the code. ``"GHDL"`` is the default. HDL simulator registration -------------------------- To use a HDL simulator to verify conversions, it needs to be registered first. This is needed once per simulator. A number of HDL simulators are preregistered in the MyHDL distribution, as follows: +-----------------+---------------------------------+ | Identifier | Simulator | +=================+=================================+ | ``"GHDL"`` | The GHDL VHDL simulator | +-----------------+---------------------------------+ | ``"vsim"`` | The ModelSim VHDL simulator | +-----------------+---------------------------------+ | ``"icarus"`` | The Icarus Verilog simulator | +-----------------+---------------------------------+ | ``"cver"`` | The cver Verilog simulator | +-----------------+---------------------------------+ | ``"vlog"`` | The Modelsim VHDL simulator | +-----------------+---------------------------------+ Of course, a simulator has to be installed before it can be used. If another simulator is required, it has to be registered by the user. This is done with the function :func:`registerSimulation` that lives in the module :mod:`myhdl.conversion._verify`. The same module also has the registrations for the predefined simulators. The verification functions work by comparing the HDL simulator output with the MyHDL simulator output. Therefore, they have to deal with the specific details of each HDL simulator output, which may be somewhat tricky. This is reflected in the interface of the :func:`registerSimulation` function. As registration is rarely needed, this interface is not further described here. Please refer to the source code in :mod:`myhdl.conversion._verify` to learn how registration works. If you need help, please contact the MyHDL community. myhdl-0.11/doc/source/manual/rtl.rst000066400000000000000000000206611347432460400174410ustar00rootroot00000000000000.. currentmodule:: myhdl .. _model-rtl: ************ RTL modeling ************ Introduction ============ .. index:: single: modeling; RTL style RTL (Register Transfer Level) is a modeling abstraction level that is typically used to write synthesizable models. :dfn:`Synthesis` refers to the process by which an HDL description is automatically compiled into an implementation for an ASIC or FPGA. This chapter describes how MyHDL supports it. .. _model-comb: Combinatorial logic =================== .. index:: single: combinatorial logic .. _model-comb-templ: Template -------- Combinatorial logic is described with a code pattern as follows:: from myhdl import block, always_comb @block def top(): ... @always_comb def comb_logic(): ... return comb_logic, ... The :func:`always_comb` decorator describes combinatorial logic. The name refers to a similar construct in SystemVerilog. The decorated function is a local function that specifies what happens when one of the input signals of the logic changes. The :func:`always_comb` decorator infers the input signals automatically. It returns a generator that is sensitive to all inputs, and that executes the function whenever an input changes. .. _model-comb-ex: Example ------- The following is an example of a combinatorial multiplexer .. include-example:: mux.py To verify it, we will simulate the logic with some random patterns. The ``random`` module in Python's standard library comes in handy for such purposes. The function ``randrange(n)`` returns a random natural integer smaller than *n*. It is used in the test bench code to produce random input values. .. include-example:: test_mux.py It is often useful to keep the random values reproducible. This can be accomplished by providing a seed value as in the code. The run produces the following output: .. run-example:: test_mux.py .. _model-seq: Sequential logic ================ .. index:: single: sequential logic .. _model-seq-templ: Template -------- Sequential RTL models are sensitive to a clock edge. In addition, they may be sensitive to a reset signal. The :func:`always_seq` decorator supports this model directly:: from myhdl import block, always_seq @block def top(, clock, ..., reset, ...): ... @always_seq(clock.posedge, reset=reset) def seq_logic(): ... return seq_logic, ... The :func:`always_seq` decorator automatically infers the reset functionality. It detects which signals need to be reset, and uses their initial values as the reset values. The reset signal itself needs to be specified as a :class:`ResetSignal` object. For example:: reset = ResetSignal(0, active=0, isasync=True) The first parameter specifies the initial value. The *active* parameter specifies the value on which the reset is active, and the *isasync* parameter specifies whether it is an asychronous (``True``) or a synchronous (``False``) reset. If no reset is needed, you can assign ``None`` to the *reset* parameter in the :func:`always_seq` parameter. .. _model-seq-ex: Example ------- The following code is a description of an incrementer with enable, and an asynchronous reset. .. include-example:: inc.py For the test bench, we will use an independent clock generator, stimulus generator, and monitor. After applying enough stimulus patterns, we can raise the :func:`StopSimulation()` exception to stop the simulation run. The test bench for a small incrementer and a small number of patterns is a follows .. include-example:: test_inc.py The simulation produces the following output .. run-example:: test_inc.py .. _mode-seq-templ-alt: Alternative template -------------------- The template with the :func:`always_seq` decorator is convenient as it infers the reset functionality automatically. Alternatively, you can use a more explicit template as follows:: from myhdl import block, always @block def top(, clock, ..., reset, ...): ... @always(clock.posedge, reset.negedge) def seq_logic(): if not reset: else: return seq_logic,... With this template, the reset values have to be specified explicitly. .. _model-fsm: Finite State Machine modeling ============================= .. index:: single: modeling; Finite State Machine Finite State Machine (FSM) modeling is very common in RTL design and therefore deserves special attention. For code clarity, the state values are typically represented by a set of identifiers. A standard Python idiom for this purpose is to assign a range of integers to a tuple of identifiers, like so .. doctest:: >>> SEARCH, CONFIRM, SYNC = range(3) >>> CONFIRM 1 However, this technique has some drawbacks. Though it is clearly the intention that the identifiers belong together, this information is lost as soon as they are defined. Also, the identifiers evaluate to integers, whereas a string representation of the identifiers would be preferable. To solve these issues, we need an *enumeration type*. .. index:: single: enum(); example usage MyHDL supports enumeration types by providing a function :func:`enum`. The arguments to :func:`enum` are the string representations of the identifiers, and its return value is an enumeration type. The identifiers are available as attributes of the type. For example .. doctest:: >>> from myhdl import enum >>> t_State = enum('SEARCH', 'CONFIRM', 'SYNC') >>> t_State >>> t_State.CONFIRM CONFIRM We can use this type to construct a state signal as follows:: state = Signal(t_State.SEARCH) As an example, we will use a framing controller FSM. It is an imaginary example, but similar control structures are often found in telecommunication applications. Suppose that we need to find the Start Of Frame (SOF) position of an incoming frame of bytes. A sync pattern detector continuously looks for a framing pattern and indicates it to the FSM with a ``syncFlag`` signal. When found, the FSM moves from the initial ``SEARCH`` state to the ``CONFIRM`` state. When the ``syncFlag`` is confirmed on the expected position, the FSM declares ``SYNC``, otherwise it falls back to the ``SEARCH`` state. This FSM can be coded as follows .. include-example:: fsm.py .. index:: single: waveform viewing At this point, we will use the example to demonstrate the MyHDL support for waveform viewing. During simulation, signal changes can be written to a VCD output file. The VCD file can then be loaded and viewed in a waveform viewer tool such as :program:`gtkwave`. .. % The user interface of this feature consists of a single function, :func:`traceSignals`. To explain how it works, recall that in MyHDL, an instance is created by assigning the result of a function call to an instance name. For example:: tb_fsm = testbench() To enable VCD tracing, the instance should be created as follows instead:: tb_fsm = traceSignals(testbench) Note that the first argument of :func:`traceSignals` consists of the uncalled function. By calling the function under its control, :func:`traceSignals` gathers information about the hierarchy and the signals to be traced. In addition to a function argument, :func:`traceSignals` accepts an arbitrary number of non-keyword and keyword arguments that will be passed to the function call. A small test bench for our framing controller example, with signal tracing enabled, is shown below: .. include-example:: test_fsm.py When we run the test bench, it generates a VCD file called :file:`testbench.vcd`. When we load this file into :program:`gtkwave`, we can view the waveforms: .. image:: tbfsm.png Signals are dumped in a suitable format. This format is inferred at the :class:`Signal` construction time, from the type of the initial value. In particular, :class:`bool` signals are dumped as single bits. (This only works starting with Python 2.3, when :class:`bool` has become a separate type). Likewise, :class:`intbv` signals with a defined bit width are dumped as bit vectors. To support the general case, other types of signals are dumped as a string representation, as returned by the standard :func:`str` function. .. warning:: Support for literal string representations is not part of the VCD standard. It is specific to :program:`gtkwave`. To generate a standard VCD file, you need to use signals with a defined bit width only. myhdl-0.11/doc/source/manual/structure.rst000066400000000000000000000142671347432460400207050ustar00rootroot00000000000000.. currentmodule:: myhdl .. _model-structure: ******************* Structural modeling ******************* .. index:: single: modeling; structural Introduction ============ Hardware descriptions need to support the concepts of module instantiation and hierarchy. In MyHDL, an instance is recursively defined as being either a sequence of instances, or a generator. Hierarchy is modeled by defining instances in a higher-level function, and returning them. The following is a schematic example of the basic case. :: from myhdl import block @block def top(...): ... instance_1 = module_1(...) instance_2 = module_2(...) ... instance_n = module_n(...) ... return instance_1, instance_2, ... , instance_n Note that MyHDL uses conventional procedural techniques for modeling structure. This makes it straightforward to model more complex cases. .. _model-conf: Conditional instantiation ========================= .. index:: single: conditional instantiation To model conditional instantiation, we can select the returned instance under parameter control. For example:: from myhdl import block SLOW, MEDIUM, FAST = range(3) @block def top(..., speed=SLOW): ... def slowAndSmall(): ... ... def fastAndLarge(): ... if speed == SLOW: return slowAndSmall() elif speed == FAST: return fastAndLarge() else: raise NotImplementedError .. _model-instarray: Lists of instances and signals ------------------------------ .. index:: single: lists of instances and signals Python lists are easy to create. We can use them to model lists of instances. Suppose we have a top module that instantiates a single ``channel`` submodule, as follows:: from myhdl import block, Signal @block def top(...): din = Signal(0) dout = Signal(0) clk = Signal(bool(0)) reset = Signal(bool(0)) channel_inst = channel(dout, din, clk, reset) return channel_inst If we wanted to support an arbitrary number of channels, we can use lists of signals and a list of instances, as follows:: from myhdl import block, Signal @block def top(..., n=8): din = [Signal(0) for i in range(n)] dout = [Signal(0) for in range(n)] clk = Signal(bool(0)) reset = Signal(bool(0)) channel_inst = [None for i in range(n)] for i in range(n): channel_inst[i] = channel(dout[i], din[i], clk, reset) return channel_inst .. _model-shadow-signals: Converting between lists of signals and bit vectors =================================================== Compared to HDLs such as VHDL and Verilog, MyHDL signals are less flexible for structural modeling. For example, slicing a signal returns a slice of the current value. For behavioral code, this is just fine. However, it implies that you cannot use such as slice in structural descriptions. In other words, a signal slice cannot be used as a signal. In MyHDL, you can address such cases by a concept called shadow signals. A shadow signal is constructed out of other signals and follows their value changes automatically. For example, a :class:`_SliceSignal` follows the value of an index or a slice from another signal. Likewise, A :class:`ConcatSignal` follows the values of a number of signals as a concatenation. As an example, suppose we have a system with N requesters that need arbitration. Each requester has a ``request`` output and a ``grant`` input. To connect them in the system, we can use list of signals. For example, a list of request signals can be constructed as follows:: request_list = [Signal(bool()) for i in range(M)] Suppose that an arbiter module is available that is instantiated as follows:: arb = arbiter(grant_vector, request_vector, clock, reset) The ``request_vector`` input is a bit vector that can have any of its bits asserted. The ``grant_vector`` is an output bit vector with just a single bit asserted, or none. Such a module is typically based on bit vectors because they are easy to process in RTL code. In MyHDL, a bit vector is modeled using the :class:`intbv` type. We need a way to "connect" the list of signals to the bit vector and vice versa. Of course, we can do this with explicit code, but shadow signals can do this automatically. For example, we can construct a ``request_vector`` as a :class:`ConcatSignal` object:: request_vector = ConcatSignal(*reversed(request_list) Note that we reverse the list first. This is done because the index range of lists is the inverse of the range of :class:`intbv` bit vectors. By reversing, the indices correspond to the same bit. The inverse problem exist for the ``grant_vector``. It would be defined as follows:: grant_vector = Signal(intbv(0)[M:]) To construct a list of signals that are connected automatically to the bit vector, we can use the :class:`Signal` call interface to construct :class:`_SliceSignal` objects:: grant_list = [grant_vector(i) for i in range(M)] Note the round brackets used for this type of slicing. Also, it may not be necessary to construct this list explicitly. You can simply use ``grant_vector(i)`` in an instantiation. To decide when to use normal or shadow signals, consider the data flow. Use normal signals to connect to *outputs*. Use shadow signals to transform these signals so that they can be used as *inputs*. .. _model-infer-instlist: Inferring the list of instances =============================== In MyHDL, instances have to be returned explicitly by a top level function. It may be convenient to assemble the list of instances automatically. For this purpose, MyHDL provides the function :func:`instances`. Using the first example in this section, it is used as follows:: from myhdl import block, instances @block def top(...): ... instance_1 = module_1(...) instance_2 = module_2(...) ... instance_n = module_n(...) ... return instances() Function :func:`instances` uses introspection to inspect the type of the local variables defined by the calling function. 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È,šñu«õsÎEæt ‡lš¸öú´iÒÞ]“®n |8®¹eá, £ÝŸi¥tZÉ¥™ƒgÝn±ôRÌë,©4~w€4UòƵTev„Äwì9æë¥;Ïmycÿü+v¸.|Ö2ußo›×…²}Ç4-éÄJ"ÆÂ§¹SúµK±•qî$Ãåó˜\iŽºpŒ"áÖ­¬†§õõ³3åPN\xLކˆˆïèÁyu#RNDDòè°8\&P)*«Ü”ß[5kÉ®Ðû/ã¢ïßšîØØÓ´à-»|Ö6uÇ¢³l¿ÍKYŽY£Ï¦µŒ^4ê]}yÿÔÚ¹kîË+”¹O;ׄ¶ž|›”&W™ØùÖDŸ¾›Ké£?ç®{™¢}Ðg]•¾YxäQô“—Í;‘UÑ·€7TV¹É15Kúwþ°v¾ ;|}«Õâsš˜¼ÆØušÐÅœêôáoVÒ2ˆˆˆï=yÿñùþ7çölâ×(hÊ!y› _Î$ð›²ö¯#µ¬ï]·ïß *bl?X¾nDÚì¦Î.^Í>»ÖaFÓ¼ãù§þëþžn¿odˆæÆö[_ÀárŒ÷Ö¥U¦²®LøNØ2á/ª²â’TžC?þ¯Ú于»”6.ÿ c7äLÚ©¹¶m¦m½4mkÙßœç=ývÚôb^àØtøîDÔwÚ“ºX2`yáóé3 Þա˼ŸÏ#"ʾ3»érw+t 3}ßÄR%ÏH|tpá’;^cÇø™–>½¡hÄa;þ8ù Q"M½·ké_émÆ´¶ÆÞMéù&–¹/V5ýá¹K·ù{&ûè«s£J¡ßÙòyðç‰r2óê>uǦA.U´s3„h^Õ¼“~„TÆæU|î(Z©sµr¨«ÊXÂ<R“ÕøFRK˜Wñ¹k|«]s¢s!5û{ ŠV–?#ÎÌÐ~Îãñ‰èUt¤—·¯R‘}¶™¹¹T*ÕcŒ%ËŽØô戜·Æ |Ç̙ԸäKÝõeY¹L–÷X;o EñW×'ÆÇyyûÊeùù l): ... return inst = myblock() # inst supports the methods of the block instance API The API on a block instance looks as follows: .. method:: .run_sim(duration=None) Run a simulation "forever" (default) or for a specified duration. .. method:: .config_sim(backend='myhdl', trace=False) Optional simulation configuration: *backend*: Defaults to 'myhdl *trace*: Enable waveform tracing, default False. .. method:: .quit_sim() Quit an active simulation. This is method is currently required because only a single simulation can be active. .. method:: .convert(hdl='Verilog', **kwargs) Converts MyHDL code to a target HDL. *hdl*: 'VHDL' or 'Verilog'. Defaults to Verilog. Supported keyword arguments: *path*: Destination folder. Defaults to current working dir. *name*: Module and output file name. Defaults to `self.mod.__name__`. *trace*: Whether the testbench should dump all signal waveforms. Defaults to False. *testbench*: Verilog only. Specifies whether a testbench should be created. Defaults to True. *timescale*: timescale parameter. Defaults to '1ns/10ps'. Verilog only. .. method:: .verify_convert() Verify conversion output, by comparing target HDL simulation log with MyHDL simulation log. .. method:: .analyze_convert() Analyze conversion output by compilation with target HDL compiler. Backwards compatibility issues ============================== In the 0.10 release, the old API still available next to the new API based on the `block` decorator. It is likely that the old deprecated API will be removed in a future release, resulting in backwards incompatibility for legacy code. Therefore, users are encouraged to start using the new API in their development methodology. myhdl-0.11/doc/source/whatsnew/0.11.rst000066400000000000000000000004071347432460400175760ustar00rootroot00000000000000.. py:currentmodule:: myhdl .. _new11: ************************ What's new in MyHDL 0.11 ************************ The `isasync` arguments ======================= The `async` argument has been replaced with `isasync` to avoid the Python 3.7 keyword conflict. myhdl-0.11/doc/source/whatsnew/0.3.rst000066400000000000000000000322211347432460400175160ustar00rootroot00000000000000======================= What’s New in MyHDL 0.3 ======================= :Author: Jan Decaluwe VCD output for waveform viewing =============================== |image| MyHDL now has support for waveform viewing. During simulation, signal changes can be written to a VCD output file that can be loaded into a waveform viewer tool such as **gtkwave**. The user interface of this feature consists of a single function, :func:`traceSignals()`. To explain how it works, recall that in MyHDL, an instance is created by assigning the result of a function call to an instance name. For example: :: tb_fsm = testbench() To enable VCD tracing, the instance should be created as follows instead: :: tb_fsm = traceSignals(testbench) All signals in the instance hierarchy will be traced in a VCD file called . Note that first the argument of :func:`traceSignals()` consists of the uncalled function. By calling the function under its control, :func:`traceSignals()` gathers information about the hierarchy and the signals to be traced. In addition to a function argument, :func:`traceSignals()` accepts an arbitrary number of non-keyword and keyword arguments that will be passed to the function call. Signals are dumped in a suitable format. This format is inferred at the :class:`Signal` construction time, from the type of the initial value. In particular, :class:`bool` signals are dumped as single bits. (This only works starting with Python 2.3, when :class:`bool` has become a separate type). Likewise, :class:`intbv` signals with a defined bit width are dumped as bit vectors. To support the general case, other types of signals are dumped as a string representation, as returned by the standard :func:`str()` function. [warning] Support for literal string representations is not part of the VCD standard. It is specific to **gtkwave**. To generate a standard VCD file, you need to use signals with a defined bit width only. Enumeration types ================= It is often desirable to define a set of identifiers. A standard Python idiom for this purpose is to assign a range of integers to a tuple of identifiers, like so: :: >>> SEARCH, CONFIRM, SYNC = range(3) >>> CONFIRM 1 However, this technique has some drawbacks. Though it is clearly the intention that the identifiers belong together, this information is lost as soon as they are defined. Also, the identifiers evaluate to integers, whereas a string representation of the identifiers would be preferable. To solve these issues, we need an *enumeration type*. MyHDL 0.3 supports enumeration types by providing a function :func:`enum()`. The arguments to :func:`enum()` are the string representations of the identifiers, and its return value is an enumeration type. The identifiers are available as attributes of the type. For example: :: >>> from myhdl import enum >>> t_State = enum('SEARCH', 'CONFIRM', 'SYNC') >>> t_State >>> t_State.CONFIRM CONFIRM Enumeration types are often used for the state variable in a finite state machine. In the waveform in Section \ `1 <#vcd-output-for-waveform-viewing>`__, you see a :class:`Signal` called ``state``. Note how the waveforms show the string representation of the enumeration type identifiers The ``state`` signal has been constructed with an enumeration type identifier as its initial value, as follows: :: state = Signal(t_State.SEARCH) Inferring the sensitivity list for combinatorial logic ====================================================== In MyHDL, combinatorial logic is described by a generator function with a sensitivity list that contains all inputs signals (the signals that are read inside the function). It may be easy to forget some input signals, especially it there are a lot of them or if the code is being modified. There are various ways to solve this. One way is to use a sophisticated editor. Another way is direct language support. For example, recent versions of Verilog have the ``always @*`` construct, that infers all input signals. The SystemVerilog 3.1 standard improves on this by introducing the ``always_comb`` block with slightly enhanced semantics. MyHDL 0.3 provides a function called :func:`always_comb()` which is named and modeled after the SystemVerilog counterpart. :func:`always_comb()` takes a classic local function as its argument. This function should specify the combinatorial logic behavior. :func:`always_comb()` returns a generator that is sensitive to all inputs, and that will run the function whenever an input changes. For example, suppose that we have a mux module described as follows: :: def mux(z, a, b, sel): """ Multiplexer. z -- mux output a, b -- data inputs sel -- control input """ def logic() while 1: yield a, b, sel if sel == 1: z.next = a else: z.next = b mux_logic = logic() return mux_logic Using :func:`always_comb()`, we can describe it as follows instead: :: def mux(z, a, b, sel): """ Multiplexer. z -- mux output a, b -- data inputs sel -- control input """ def logic() if sel == 1: z.next = a else: z.next = b mux_logic = always_comb(logic) return mux_logic Note that in the first version, the sensitivity list is at the beginning of the generator function code. This is traditionally done in synthesizable RTL style modeling. However, the semantics of this style are not entirely correct: at the start of the simulation, the combinatorial output will not reflect the initial state of the inputs. :func:`always_comb()` solves this by putting the sensitivity list at the end of the code. Inferring the list of instances =============================== In MyHDL, the instances defined in a top level function need to be returned explicitly. The following is a schematic example: :: def top(...): ... instance_1 = module_1(...) instance_2 = module_2(...) ... instance_n = module_n(...) ... return instance_1, instance_2, ... , instance_n It may be convenient to assemble the list of instances automatically, especially if there are many instances. For this purpose, MyHDL 0.3 provides the function :func:`instances()`. It is used as follows: :: from myhdl import instances def top(...): ... instance_1 = module_1(...) instance_2 = module_2(...) ... instance_n = module_n(...) ... return instances() Function :func:`instances()` uses introspection to inspect the type of the local variables defined by the calling function. All variables that comply with the definition of an instance are assembled in a list, and that list is returned. Inferring the list of processes =============================== In addition to instances, a top level function may also define local generators functions, which I will call *processes* because of the analogy with VHDL. Like instances, processes need to be returned explicitly, with the qualification that they have to be called first to turn them into generators. The following is a schematic example: :: def top(...): ... def process_1(): ... def process_2(): ... ... def process_n(): ... ... return process_1(), process_2(), ..., process_n() As for instances, it may be more convenient to assemble the list of processes automatically. One option is to turn each process into an instance by calling it and assigning the returned generator to a local variable. Those instances will then be found by the :func:`instances()` function described in Section \ `4 <#inferring-the-list-of-instances>`__. Another option is to use the function :func:`processes()` provided by MyHDL 0.3. This function uses introspection to find the processes, calls each of them, and assembles the returned generators into a list. It can be used as follows: :: from myhdl import processes def top(...): ... def process_1(): ... def process_2(): ... ... def process_n(): ... ... return processes() To conclude, a top level function with both instances and processes can use the following idiomatic code to return all of them: :: return instances(), processes() Class :class:`intbv` enhancements ================================= Class :class:`intbv` has been enhanced with new features. It is now possible to leave the left index of a slicing operation unspecified. The meaning is to access “all†higher order bits. For example: :: >>> from myhdl import intbv >>> n = intbv() >>> hex(n) '0x0' >>> n[:] = 0xde >>> hex(n) '0xde' >>> n[:8] = 0xfa >>> hex(n) '0xfade' >>> n[8:] = 0xb4 >>> hex(n) '0xfab4' :class:`intbv` objects now have ``min`` and ``max`` attributes that can be specified at construction time. The meaning is that only values within ``range(min, max)`` are permitted. The default value for these attributes is ``None``, meaning “infiniteâ€. For example (traceback output shortened for clarity): :: >>> n = intbv(min=-17, max=53) >>> n intbv(0) >>> n.min -17 >>> n.max 53 >>> n[:] = 28 >>> n intbv(28) >>> n[:] = -18 Traceback (most recent call last): .... ValueError: intbv value -18 < minimum -17 >>> n[:] = 53 Traceback (most recent call last): .... ValueError: intbv value 53 >= maximum 53 When a slice is taken from an :class:`intbv` object, the return value is a new :class:`intbv` object with a defined bit width. As in Verilog, the value of the new :class:`intbv` object is always positive, regardless of the sign of the original value. In addition, the ``min`` and ``max`` attributes are set implicitly: :: >>> v = intbv()[6:] >>> v intbv(0) >>> v.min 0 >>> v.max 64 Lastly, a small change was implemented with regard to binary operations. In previous versions, both numeric and bit-wise operations always returned a new :class:`intbv` object, even in mixed-mode operations with :class:`int` objects. This has changed: numeric operations return an :class:`int`, and bitwise operations return a :class:`intbv`. In this way, the return value corresponds better to the nature of the operation. Function :func:`concat()` ========================== In previous versions, the :class:`intbv` class provided a method. This method is no longer available. Instead, there is now a :func:`concat()` function that supports a much broader range of objects. A function is more natural because MyHDL objects of various types can be concatenated: :class:`intbv` objects with a defined bit width, :class:`bool` objects, the corresponding signal objects, and bit strings. All these objects have a defined bit width. Moreover, the first argument doesn’t need to have a defined bit width. It can also be an unsized :class:`intbv`, an :class:`int`, a :class:`long`, or a corresponding signal object. Function :func:`concat()` returns an :class:`intbv` object. Python 2.3 support ================== Python 2.3 was released on July 29, 2003, and as of this writing, it is the latest stable Python release. MyHDL 0.3 works with both Python 2.2 and Python 2.3. In good Python tradition, MyHDL code developed with Python 2.2 should run without changes or problems in Python 2.3. In general, I am not that keen on early upgrading. However, as it happens, the evolution of Python enables features that are really important or even crucial to MyHDL. Python 2.2 generators are the best example: they are the cornerstone of MyHDL. But Python 2.3 also has significant benefits, which I will summarize below. First, generators and the ``yield`` statement are a default Python 2.3 feature. This means that statements are no longer required. Second, Python 2.3 has a :class:`bool` type, which is implemented as a subtype of :class:`int`. For general Python use, the implications are rather limited - the main difference is that logical result values will print as ``False`` and ``True`` instead of ``0`` and ``1``. However, in MyHDL, I can use the :class:`bool` type to infer a bit width. If a :class:`Signal` is constructed with a :class:`bool` value, it is a single bit :class:`Signal`. One application is waveform viewing as in Section \ `1 <#vcd-output-for-waveform-viewing>`__ In the waveform, note how single bit signals are displayed as level changes. With Python 2.2, the waveforms of these signals would only show value changes, which is not as clear for single bits. Finally, Python 2.3 is significantly faster. MyHDL code runs 25–35% faster in Python 2.3. This is a very nice speedup compared to the small burden of a straightforward upgrade. Python is a very stable language, so upgrading to Python 2.3 is virtually risk free. Given the additional benefits, I recommend MyHDL users to do so as soon as possible. For the next major MyHDLrelease, the new features will become required and only Python 2.3 (and higher) will be supported. .. |image| image:: ../manual/tbfsm.png myhdl-0.11/doc/source/whatsnew/0.4.rst000066400000000000000000000640361347432460400175300ustar00rootroot00000000000000============================================== What's new in MyHDL 0.4: Conversion to Verilog ============================================== :Author: Jan Decaluwe Introduction ============ MyHDL 0.4 supports the automatic conversion of a subset of MyHDL code to synthesizable Verilog code. This feature provides a direct path from Python to an FPGA or ASIC implementation. MyHDL aims to be a complete design language, for tasks such as high level modeling and verification, but also for implementation. However, prior to 0.4 a user had to translate MyHDL code manually to Verilog or VHDL. Needless to say, this was inconvenient. With MyHDL0.4, this manual step is no longer necessary. Solution description ==================== The solution works as follows. The hardware description should be modeled in MyHDL style, and satisfy certain constraints that are typical for implementation-oriented hardware modeling. Subsequently, such a design is converted to an equivalent model in the Verilog language, using the function :func:`toVerilog` from the MyHDLlibrary. Finally, a third-party *synthesis tool* is used to convert the Verilog design to a gate implementation for an ASIC or FPGA. There are a number of Verilog synthesis tools available, varying in price, capabilities, and target implementation technology. The conversion does not start from source files, but from a design that has been *elaborated* by the Python interpreter. The converter uses the Python profiler to track the interpreter’s operation and to infer the design structure and name spaces. It then selectively compiles pieces of source code for additional analysis and for conversion. This is done using the Python compiler package. Features ======== The design is converted after elaboration ----------------------------------------- *Elaboration* refers to the initial processing of a hardware description to achieve a representation of a design instance that is ready for simulation or synthesis. In particular, structural parameters and constructs are processed in this step. In MyHDL, the Python interpreter itself is used for elaboration. A :class:`Simulation` object is constructed with elaborated design instances as arguments. Likewise, the Verilog conversion works on an elaborated design instance. The Python interpreter is thus used as much as possible. The structural description can be arbitrarily complex and hierarchical ---------------------------------------------------------------------- As the conversion works on an elaborated design instance, any modeling constraints only apply to the leaf elements of the design structure, that is, the co-operating generators. In other words, there are no restrictions on the description of the design structure: Python’s full power can be used for that purpose. Also, the design hierarchy can be arbitrarily deep. Generators are mapped to Verilog always or initial blocks --------------------------------------------------------- The converter analyzes the code of each generator and maps it to a Verilog ``always`` blocks if possible, and to an ``initial`` block otherwise. The converted Verilog design will be a flat “net list of blocksâ€. The Verilog module interface is inferred from signal usage ---------------------------------------------------------- In MyHDL, the input or output direction of interface signals is not explicitly declared. The converter investigates signal usage in the design hierarchy to infer whether a signal is used as input, output, or as an internal signal. Internal signals are given a hierarchical name in the Verilog output. Function calls are mapped to a unique Verilog function or task call ------------------------------------------------------------------- The converter analyzes function calls and function code to see if they should be mapped to Verilog functions or to tasks. Python functions are much more powerful than Verilog subprograms; for example, they are inherently generic, and they can be called with named association. To support this power in Verilog, a unique Verilog function or task is generated per Python function call. If-then-else structures may be mapped to Verilog case statements ---------------------------------------------------------------- Python does not provide a case statement. However, the converter recognizes if-then-else structures in which a variable is sequentially compared to items of an enumeration type, and maps such a structure to a Verilog case statement with the appropriate synthesis attributes. Choice of encoding schemes for enumeration types ------------------------------------------------ The :func:`enum` function in MyHDL returns an enumeration type. This function takes an additional parameter ``encoding`` that specifies the desired encoding in the implementation: binary, one hot, or one cold. The Verilog converter generates the appropriate code. The convertible subset ====================== Introduction ------------ Unsurprisingly, not all MyHDL code can be converted to Verilog. In fact, there are very important restrictions. As the goal of the conversion functionality is implementation, this should not be a big issue: anyone familiar with synthesis is used to similar restrictions in the *synthesizable subset* of Verilog and VHDL. The converter attempts to issue clear error messages when it encounters a construct that cannot be converted. In practice, the synthesizable subset usually refers to RTL synthesis, which is by far the most popular type of synthesis today. There are industry standards that define the RTL synthesis subset. However, those were not used as a model for the restrictions of the MyHDL converter, but as a minimal starting point. On that basis, whenever it was judged easy or useful to support an additional feature, this was done. For example, it is actually easier to convert :keyword:`while` loops than :keyword:`for` loops even though they are not RTL-synthesizable. As another example, :keyword:`print` is supported because it’s so useful for debugging, even though it’s not synthesizable. In summary, the convertible subset is a superset of the standard RTL synthesis subset, and supports synthesis tools with more advanced capabilities, such as behavioral synthesis. Recall that any restrictions only apply to the design post elaboration. In practice, this means that they apply only to the code of the generators, that are the leaf functional blocks in a MyHDL design. Coding style ------------ A natural restriction on convertible code is that it should be written in MyHDL style: cooperating generators, communicating through signals, and with ``yield`` statements specifying wait points and resume conditions. Supported resume conditions are a signal edge, a signal change, or a tuple of such conditions. Supported types --------------- The most important restriction regards object types. Verilog is an almost typeless language, while Python is strongly (albeit dynamically) typed. The converter has to infer the types of names used in the code, and map those names to Verilog variables. Only a limited amount of types can be converted. Python :class:`int` and :class:`long` objects are mapped to Verilog integers. All other supported types are mapped to Verilog regs (or wires), and therefore need to have a defined bit width. The supported types are the Python :class:`bool` type, the MyHDL :class:`intbv` type, and MyHDL enumeration types returned by function :func:`enum`. The latter objects can also be used as the base object of a :class:`Signal`. :class:`intbv` objects must be constructed so that a bit width can be inferred. This can be done by specifying minimum and maximum values, e.g. as follows: :: index = intbv(0, min=0, max=2**N) Alternatively, a slice can be taken from an :class:`intbv` object as follows: :: index = intbv(0)[N:] Such as slice returns a new :class:`intbv` object, with minimum value ``0`` , and maximum value ``2**N``. Supported statements -------------------- The following is a list of the statements that are supported by the Verilog converter, possibly qualified with restrictions or usage notes. The :keyword:`break` statement. The :keyword:`continue` statement. The :keyword:`def` statement. The :keyword:`for` statement. The only supported iteration scheme is iterating through sequences of integers returned by built-in function :func:`range` or MyHDLfunction :func:`downrange`. The optional :keyword:`else` clause is not supported. The :keyword:`if` statement. :keyword:`if`, :keyword:`elif`, and :keyword:`else` clauses are fully supported. The :keyword:`pass` statement. The :keyword:`print` statement. When printing an interpolated string, the format specifiers are copied verbatim to the Verilog output. Printing to a file (with syntax ``’>>’``) is not supported. The :keyword:`raise` statement. This statement is mapped to Verilog statements that end the simulation with an error message. The :keyword:`return` statement. The :keyword:`yield` statement. The yielded expression can be a signal, a signal edge as specified by MyHDL functions :func:`posedge` or :func:`negedge`, or a tuple of signals and edge specifications. The :keyword:`while` statement. The optional :keyword:`else` clause is not supported. Methodology notes ================= Simulation ---------- In the Python philosophy, the run-time rules. The Python compiler doesn’t attempt to detect a lot of errors beyond syntax errors, which given Python’s ultra-dynamic nature would be an almost impossible task anyway. To verify a Python program, one should run it, preferably using unit testing to verify each feature. The same philosophy should be used when converting a MyHDL description to Verilog: make sure the simulation runs fine first. Although the converter checks many things and attempts to issue clear error messages, there is no guarantee that it does a meaningful job unless the simulation runs fine. Conversion output verification ------------------------------ It is always prudent to verify the converted Verilog output. To make this task easier, the converter also generates a test bench that makes it possible to simulate the Verilog design using the Verilog co-simulation interface. This permits one to verify the Verilog code with the same test bench used for the MyHDL code. This is also how the Verilog converter development is being verified. Assignment issues ----------------- Name assignment in Python ~~~~~~~~~~~~~~~~~~~~~~~~~ Name assignment in Python is a different concept than in many other languages. This point is very important for effective modeling in Python, and even more so for synthesizable MyHDL code. Therefore, the issues are discussed here explicitly. Consider the following name assignments: :: a = 4 a = ``a string'' a = False In many languages, the meaning would be that an existing variable ``a`` gets a number of different values. In Python, such a concept of a variable doesn’t exist. Instead, assignment merely creates a new binding of a name to a certain object, that replaces any previous binding. So in the example, the name ``a`` is bound a number of different objects in sequence. The Verilog converter has to investigate name assignment and usage in MyHDL code, and to map names to Verilog variables. To achieve that, it tries to infer the type and possibly the bit width of each expression that is assigned to a name. Multiple assignments to the same name can be supported if it can be determined that a consistent type and bit width is being used in the assignments. This can be done for boolean expressions, numeric expressions, and enumeration type literals. In Verilog, the corresponding name is mapped to a single bit ``reg``, an ``integer``, or a ``reg`` with the appropriate width, respectively. In other cases, a single assignment should be used when an object is created. Subsequent value changes are then achieved by modification of an existing object. This technique should be used for :class:`Signal` and :class:`intbv` objects. Signal assignment ~~~~~~~~~~~~~~~~~ Signal assignment in MyHDL is implemented using attribute assignment to attribute ``next``. Value changes are thus modeled by modification of the existing object. The converter investigates the :class:`Signal` object to infer the type and bit width of the corresponding Verilog variable. :class:`intbv` objects ~~~~~~~~~~~~~~~~~~~~~~ Type :class:`intbv` is likely to be the workhorse for synthesizable modeling in MyHDL. An :class:`intbv` instance behaves like a (mutable) integer whose individual bits can be accessed and modified. Also, it is possible to constrain its set of values. In addition to error checking, this makes it possible to infer a bit width, which is required for implementation. In Verilog, an :class:`intbv` instance will be mapped to a ``reg`` with an appropriate width. As noted before, it is not possible to modify its value using name assignment. In the following, we will show how it can be done instead. Consider: :: a = intbv(0)[8:] This is an :class:`intbv` object with initial value ``0`` and bit width 8. The change its value to ``5``, we can use slice assignment: :: a[8:] = 5 The same can be achieved by leaving the bit width unspecified, which has the meaning to change “all†bits: :: a[:] = 5 Often the new value will depend on the old one. For example, to increment an :class:`intbv` with the technique above: :: a[:] = a + 1 Python also provides *augmented* assignment operators, which can be used to implement in-place operations. These are supported on :class:`intbv` objects and by the converter, so that the increment can also be done as follows: :: a += 1 Converter usage =============== We will demonstrate the conversion process by showing some examples. A small design with a single generator -------------------------------------- Consider the following MyHDL code for an incrementer module: :: def inc(count, enable, clock, reset, n): """ Incrementer with enable. count -- output enable -- control input, increment when 1 clock -- clock input reset -- asynchronous reset input n -- counter max value """ def incProcess(): while 1: yield posedge(clock), negedge(reset) if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = (count + 1) % n return incProcess() In Verilog terminology, function :func:`inc` corresponds to a module, while generator function :func:`incProcess` roughly corresponds to an always block. Normally, to simulate the design, we would “elaborate†an instance as follows: :: m = 8 n = 2 ** m count = Signal(intbv(0)[m:]) enable = Signal(bool(0)) clock, reset = [Signal(bool()) for i in range(2)] inc_inst = inc(count, enable, clock, reset, n=n) ``incinst`` is an elaborated design instance that can be simulated. To convert it to Verilog, we change the last line as follows: :: inc_inst = toVerilog(inc, count, enable, clock, reset, n=n) Again, this creates an instance that can be simulated, but as a side effect, it also generates an equivalent Verilog module in file . The Verilog code looks as follows: :: module inc_inst ( count, enable, clock, reset ); output [7:0] count; reg [7:0] count; input enable; input clock; input reset; always @(posedge clock or negedge reset) begin: _MYHDL1_BLOCK if ((reset == 0)) begin count <= 0; end else begin if (enable) begin count <= ((count + 1) % 256); end end end endmodule You can see the module interface and the always block, as expected from the MyHDL design. Converting a generator directly ------------------------------- It is also possible to convert a generator directly. For example, consider the following generator function: :: def bin2gray(B, G, width): """ Gray encoder. B -- input intbv signal, binary encoded G -- output intbv signal, gray encoded width -- bit width """ Bext = intbv(0)[width+1:] while 1: yield B Bext[:] = B for i in range(width): G.next[i] = Bext[i+1] ^ Bext[i] As before, you can create an instance and convert to Verilog as follows: :: width = 8 B = Signal(intbv(0)[width:]) G = Signal(intbv(0)[width:]) bin2gray_inst = toVerilog(bin2gray, B, G, width) The generated Verilog code looks as follows: :: module bin2gray_inst ( B, G ); input [7:0] B; output [7:0] G; reg [7:0] G; always @(B) begin: _MYHDL1_BLOCK integer i; reg [9-1:0] Bext; Bext[9-1:0] = B; for (i=0; i<8; i=i+1) begin G[i] <= (Bext[(i + 1)] ^ Bext[i]); end end endmodule A hierarchical design --------------------- The hierarchy of convertible designs can be arbitrarily deep. For example, suppose we want to design an incrementer with Gray code output. Using the designs from previous sections, we can proceed as follows: :: def GrayInc(graycnt, enable, clock, reset, width): bincnt = Signal(intbv()[width:]) INC_1 = inc(bincnt, enable, clock, reset, n=2**width) BIN2GRAY_1 = bin2gray(B=bincnt, G=graycnt, width=width) return INC_1, BIN2GRAY_1 According to Gray code properties, only a single bit will change in consecutive values. However, as the ``bin2gray`` module is combinatorial, the output bits may have transient glitches, which may not be desirable. To solve this, let’s create an additional level of hierarchy and add an output register to the design. (This will create an additional latency of a clock cycle, which may not be acceptable, but we will ignore that here.) :: def GrayIncReg(graycnt, enable, clock, reset, width): graycnt_comb = Signal(intbv()[width:]) GRAY_INC_1 = GrayInc(graycnt_comb, enable, clock, reset, width) def reg(): while 1: yield posedge(clock) graycnt.next = graycnt_comb REG_1 = reg() return GRAY_INC_1, REG_1 We can convert this hierarchical design as before: :: width = 8 graycnt = Signal(intbv()[width:]) enable, clock, reset = [Signal(bool()) for i in range(3)] GRAY_INC_REG_1 = toVerilog(GrayIncReg, graycnt, enable, clock, reset, width) The Verilog output code looks as follows: :: module GRAY_INC_REG_1 ( graycnt, enable, clock, reset ); output [7:0] graycnt; reg [7:0] graycnt; input enable; input clock; input reset; reg [7:0] graycnt_comb; reg [7:0] _GRAY_INC_1_bincnt; always @(posedge clock or negedge reset) begin: _MYHDL1_BLOCK if ((reset == 0)) begin _GRAY_INC_1_bincnt <= 0; end else begin if (enable) begin _GRAY_INC_1_bincnt <= ((_GRAY_INC_1_bincnt + 1) % 256); end end end always @(_GRAY_INC_1_bincnt) begin: _MYHDL4_BLOCK integer i; reg [9-1:0] Bext; Bext[9-1:0] = _GRAY_INC_1_bincnt; for (i=0; i<8; i=i+1) begin graycnt_comb[i] <= (Bext[(i + 1)] ^ Bext[i]); end end always @(posedge clock) begin: _MYHDL9_BLOCK graycnt <= graycnt_comb; end endmodule Note that the output is a flat “net list of blocksâ€, and that hierarchical signal names are generated as necessary. Optimizations for finite state machines --------------------------------------- As often in hardware design, finite state machines deserve special attention. In Verilog and VHDL, finite state machines are typically described using case statements. Python doesn’t have a case statement, but the converter recognizes particular if-then-else structures and maps them to case statements. This optimization occurs when a variable whose type is an enumerated type is sequentially tested against enumeration items in an if-then-else structure. Also, the appropriate synthesis pragmas for efficient synthesis are generated in the Verilog code. As a further optimization, function :func:`enum` was enhanced to support alternative encoding schemes elegantly, using an additional parameter ``encoding``. For example: :: t_State = enum('SEARCH', 'CONFIRM', 'SYNC', encoding='one_hot') The default encoding is ``’binary’``; the other possibilities are ``’onehot’`` and ``’onecold’``. This parameter only affects the conversion output, not the behavior of the type. The generated Verilog code for case statements is optimized for an efficient implementation according to the encoding. Note that in contrast, a Verilog designer has to make nontrivial code changes to implement a different encoding scheme. As an example, consider the following finite state machine, whose state variable uses the enumeration type defined above: :: FRAME_SIZE = 8 def FramerCtrl(SOF, state, syncFlag, clk, reset_n): """ Framing control FSM. SOF -- start-of-frame output bit state -- FramerState output syncFlag -- sync pattern found indication input clk -- clock input reset_n -- active low reset """ index = intbv(0, min=0, max=8) # position in frame while 1: yield posedge(clk), negedge(reset_n) if reset_n == ACTIVE_LOW: SOF.next = 0 index[:] = 0 state.next = t_State.SEARCH else: SOF.next = 0 if state == t_State.SEARCH: index[:] = 0 if syncFlag: state.next = t_State.CONFIRM elif state == t_State.CONFIRM: if index == 0: if syncFlag: state.next = t_State.SYNC else: state.next = t_State.SEARCH elif state == t_State.SYNC: if index == 0: if not syncFlag: state.next = t_State.SEARCH SOF.next = (index == FRAME_SIZE-1) else: raise ValueError("Undefined state") index[:]= (index + 1) % FRAME_SIZE The conversion is done as before: :: SOF = Signal(bool(0)) syncFlag = Signal(bool(0)) clk = Signal(bool(0)) reset_n = Signal(bool(1)) state = Signal(t_State.SEARCH) framerctrl_inst = toVerilog(FramerCtrl, SOF, state, syncFlag, clk, reset_n) The Verilog output looks as follows: :: module framerctrl_inst ( SOF, state, syncFlag, clk, reset_n ); output SOF; reg SOF; output [2:0] state; reg [2:0] state; input syncFlag; input clk; input reset_n; always @(posedge clk or negedge reset_n) begin: _MYHDL1_BLOCK reg [3-1:0] index; if ((reset_n == 0)) begin SOF <= 0; index[3-1:0] = 0; state <= 3'b001; end else begin SOF <= 0; // synthesis parallel_case full_case casez (state) 3'b??1: begin index[3-1:0] = 0; if (syncFlag) begin state <= 3'b010; end end 3'b?1?: begin if ((index == 0)) begin if (syncFlag) begin state <= 3'b100; end else begin state <= 3'b001; end end end 3'b1??: begin if ((index == 0)) begin if ((!syncFlag)) begin state <= 3'b001; end end SOF <= (index == (8 - 1)); end default: begin $display("Verilog: ValueError(Undefined state)"); $finish; end endcase index[3-1:0] = ((index + 1) % 8); end end endmodule Known issues ============ Negative values of :class:`intbv` instances are not supported. The :class:`intbv` class is quite capable of representing negative values. However, the ``signed`` type support in Verilog is relatively recent and mapping to it may be tricky. In my judgment, this was not the most urgent requirement, so I decided to leave this for later. Verilog integers are 32 bit wide Usually, Verilog integers are 32 bit wide. In contrast, Python is moving toward integers with undefined width. Python :class:`int` and :class:`long` variables are mapped to Verilog integers; so for values wider than 32 bit this mapping is incorrect. Synthesis pragmas are specified as Verilog comments. The recommended way to specify synthesis pragmas in Verilog is through attribute lists. However, my Verilog simulator (Icarus) doesn’t support them for ``case`` statements (to specify ``parallelcase`` and ``fullcase`` pragmas). Therefore, I still used the old but deprecated method of synthesis pragmas in Verilog comments. Inconsistent place of the sensitivity list inferred from ``alwayscomb``. The semantics of ``alwayscomb``, both in Verilog and MyHDL, is to have an implicit sensitivity list at the end of the code. However, this may not be synthesizable. Therefore, the inferred sensitivity list is put at the top of the corresponding ``always`` block. This may cause inconsistent behavior at the start of the simulation. The workaround is to create events at time 0. Non-blocking assignments to task arguments don’t work. I didn’t get non-blocking (signal) assignments to task arguments to work. I don’t know yet whether the issue is my own, a Verilog issue, or an issue with my Verilog simulator Icarus. I’ll need to check this further. myhdl-0.11/doc/source/whatsnew/0.5.rst000066400000000000000000000507351347432460400175320ustar00rootroot00000000000000.. currentmodule:: myhdl .. _new05: ======================= What's new in MyHDL 0.5 ======================= :Author: Jan Decaluwe Modeling ======== Creating generators with decorators ----------------------------------- Introduction ~~~~~~~~~~~~ Python 2.4 introduced a new feature called *decorators*. A decorator consists of special syntax in front of a function declaration. It refers to a decorator function. The decorator function automatically transforms the declared function into some other callable object. MyHDL 0.5 defines decorators that can be used to create ready-to-run generators from local functions. The use of decorators results in clearer, more explicit code. The ``@instance`` decorator ~~~~~~~~~~~~~~~~~~~~~~~~~~~ The ``@instance`` decorator is the most general decorator in MyHDL. In earlier versions of MyHDL, local generator functions are typically used as follows: :: def top(...): ... def gen_func(): ... inst = gen_func() ... return inst, ... Note that the generator function :func:`gen_func()` is intended to be called exactly once, and that its name is not necessary anymore afterwards. In MyHDL 0.5, this can be rewritten as follows, using the ``@instance`` decorator: :: def top(...): ... @instance def inst(): ... return inst, ... Behind the curtains, the ``@instance`` decorator automatically creates a generator by calling the generator function, and by reusing its name. Note that it is placed immediately in front of the corresponding generator function, resulting in clearer code. The ``@always`` decorator ~~~~~~~~~~~~~~~~~~~~~~~~~ The ``@always`` decorator is a specialized decorator that targets a very popular coding pattern. It is used as follows: :: def top(...): ... @always(event1, event2, ...) def inst() ... return inst, ... The meaning of this code is that the decorated function is executed whenever one of the events occurs. The argument list of the decorator corresponds to the sensitivity list. Appropriate events are edge specifiers, signals, and delay objects. The decorated function is a classic function instead of a generator function. Behind the curtains, the ``always`` decorator creates an enclosing ``while True`` loop automatically, and inserts a ``yield`` statement with the sensitivity list. The ``@always_comb`` decorator ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The ``@always_comb`` decorator is used to describe combinatorial logic. It is nothing else than the :func:`always_comb` function from earlier MyHDL versions used as a decorator: :: def top(...): ... @always_comb def comb_inst(): ... return comb_inst, ... The ``@always_comb`` decorator infers the inputs of the combinatorial logic and the corresponding sensitivity list automatically. More information ~~~~~~~~~~~~~~~~ For more information about the background and the design decisions regarding MyHDL decorators, see `mep-100`_. Recommended style changes ------------------------- Decorator usage ~~~~~~~~~~~~~~~ The use of decorators has clear advantages in terms of code clarity. Therefore, it is recommended that all local generators be created using decorators. Edge specifiers ~~~~~~~~~~~~~~~ Signal edges are typically specified using the :func:`posedge()` and :func:`negedge()` functions in MyHDL. However, these functions are simply wrappers around attributes with the same name. The design decision to use functions have been reviewed and found questionable. In fact, using the attributes directly instead has significant advantages, listed in order of increasing significance: * one character less to type * more object-oriented style * less symbols in the ``myhdl`` namespace * no brackets, which is better for clarity * no function call overhead From MyHDL 0.5 on, it is therefore recommended to use the edge specifier attributes. For example: :: clk.posedge # instead of posedge(clk) rst.negedge # instead of negedge(clk) Deprecated features ------------------- Edge specifier functions ~~~~~~~~~~~~~~~~~~~~~~~~ Functions :func:`posedge()` and :func:`negedge()` are deprecated. As discussed before, it is recommended to use the signal attributes with the same name instead. In MyHDL 0.5, the functions will be removed from all documentation and examples. They will be removed from MyHDL in a future version. processes() function ~~~~~~~~~~~~~~~~~~~~ Function :func:`processes()` is deprecated. It looks up local generator functions and calls them to create generators. When MyHDL 0.5 decorators are used as recommended, this functionality becomes superfluous as it is part of the decorator functionality. On the other hand, the companion function :func:`instances()` continues to be relevant and useful. It merely looks up instances in a local namespace. Having a single lookup function will also improve usability. In MyHDL 0.5, the :func:`processes()` function will be removed from all documentation and examples. It will be removed from MyHDL in a future version. Backwards incompatible changes ------------------------------ Default initial value of an intbv instance ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ It has always been possible to construct an :class:`intbv` instance without explicit initial value: :: m = intbv() Prior to MyHDL 0.4, the default initial value was ``0``. In MyHDL 0.5, this has been changed to ``None``. This is a first step towards support for ``X`` and ``Z`` functionality as found in other HDLs. This may be occasionally useful :-) For example, it may be meaningful to initialize memory locations to ``None`` to make sure that they will not be read before they have been initialized. If ``None`` is supported, it seems also logical to make it the default initial value, to be interpreted as "No value". **Warning**: if you have calls like the above in your code, it will probably fail with MyHDL 0.5, as many integer-like operations are not supported with `None` values. **Workaround**: change your existing code by using ``0`` as an explicit initial value, like so:: m = intbv(0) Python version -------------- Because of the usage of new features such as decorators, MyHDL 0.5 requires upgrading to Python 2.4 or higher. Verilog conversion ================== Decorator support ----------------- The Verilog converter was enhanced to support the proposed decorators. Mapping a list of signals to a RAM memory ----------------------------------------- Certain synthesis tools can map Verilog memories to memory structures. For example, this is supported by the Xilinx toolset. To support this interesting feature, the Verilog converter now maps lists of signals in MyHDL to Verilog memories. The following MyHDL example is a ram model that uses a list of signals to model the internal memory. :: def RAM(dout, din, addr, we, clk, depth=128): """ Ram model """ mem = [Signal(intbv(0)[8:]) for i in range(depth)] @always(clk.posedge) def write(): if we: mem[int(addr)].next = din @always_comb def read(): dout.next = mem[int(addr)] return write, read With the appropriate signal definitions for the interface ports, it is mapped by :func:`toVerilog` to the following Verilog code. Note how the list of signals ``mem`` is mapped to a Verilog memory. :: module RAM ( dout, din, addr, we, clk ); output [7:0] dout; wire [7:0] dout; input [7:0] din; input [6:0] addr; input we; input clk; reg [7:0] mem [0:128-1]; always @(posedge clk) begin: _RAM_write if (we) begin mem[addr] <= din; end end assign dout = mem[addr]; endmodule Lists of signals can also be used in MyHDL to elegantly describe iterative hierarchical structures. (See the MyHDL manual.) However, there is an important difference: such signals will have a name at some level of the hierarchy, while in the case described above, the individual signals are anonymous. The :func:`toVerilog` converter detects which case we are in. In the first case, the individual signals will still be declared in the Verilog output, using the highest-level hierarchical name. It is only in the second case that the list of signals is declared as a Verilog memory. Mapping combinatorial logic to assign statements ------------------------------------------------ When possible, combinatorial logic is now converted to Verilog assign statements. There are two conditions for this to happen. First, the logic has to be explicitly described as a combinatorial function using the ``@always_comb`` decorator. Secondly, the function has to be simple enough so that a mapping to assign statements is possible: only signal assignments are permitted. Otherwise, a Verilog always block is used as previously. See the RAM model of the previous section for an example. This was done because certain synthesis tools require assign statements to recognize code templates. Mapping a tuple of integers to a ROM memory -------------------------------------------- Some synthesis tools, such as the Xilinx tool, can infer a ROM memory from a case statement. :func:`toVerilog` has been enhanced to do the expansion into a case statement automatically, based on a higher level description. The rom access is described in a single line, by indexing into a tuple of integers. The tuple can be described manually, but also by programmatical means. Note that a tuple is used instead of a list to stress the read-only character of the memory. The following example illustrates this functionality. :: def rom(dout, addr, CONTENT): @always_comb def read(): dout.next = CONTENT[int(addr)] return read dout = Signal(intbv(0)[8:]) addr = Signal(intbv(0)[4:]) CONTENT = (17, 134, 52, 9) toVerilog(rom, dout, addr, CONTENT) The output Verilog code is as follows: :: module rom ( dout, addr ); output [7:0] dout; reg [7:0] dout; input [3:0] addr; always @(addr) begin: _rom_read // synthesis parallel_case full_case case (addr) 0: dout <= 17; 1: dout <= 134; 2: dout <= 52; default: dout <= 9; endcase end endmodule Support for signed arithmetic ----------------------------- Getting signed representations right in Verilog is tricky. One issue is that a signed representation is treated as a special case, and unsigned as the rule. For example, whenever one of the operands in an expression is unsigned, all others are also treated like unsigned. While this is understandable from a historical perspective (for backwards compatibility reasons) it is the opposite from what one expects from a high-level point of view, when working with negative numbers. The basic problem is that a Verilog user has to deal with representation explicitly in all cases, even for abstract integer operations. It would be much better to leave representational issues to a tool. MyHDL doesn't make the distinction between signed and unsigned. The :class:`intbv` class can handle any kind of integer, including negative ones. If required, you can access the 2's complement representation of an :class:`intbv` object, but for integer operations such a counting, there is no need to worry about this. Of course, the Verilog converter has to deal with the representation carefully. MyHDL 0.4 avoided the issue by simply prohibiting :class:`intbv` objects with negative values. MyHDL 0.5 adds support for negative values and uses the signed Verilog representation to accomplish this. The problematic cases are those when signed and unsigned representations are mixed in Verilog expressions. The converter avoids this by making sure that signed arithmetic is used whenever one of the operands is signed. Note that this is exactly the opposite of the Verilog default. More specifically, the converter may convert an unsigned operand by adding a sign bit and casting to a signed interpretation, using the Verilog ``$signed`` function. Operands that are treated like this are positive :class:`intbv` objects, slices and subscripts of :class:`intbv` objects, and :class:`bool` objects. Integer constants are treated as a special case. Unsized integer numbers were always treated as signed numbers in Verilog. However, as their representation is minimally 32 bits wide, they usually don't give problems when mixed with unsigned numbers. Therefore, integer constants don't cause signed casting of other operands in the same expression: users would actually find it surprizing if they did. Support for user-defined Verilog code ------------------------------------- Introduction ~~~~~~~~~~~~ In order to provide a path to implementation, MyHDL code can be converted to Verilog. However, in some cases the conversion may fail or the result may not be acceptable. For example: * conversion will fail if the MyHDL code doesn't follow the rules of the convertible subset * a user may want to explicitly instantiate an existing Verilog module, instead of converting the corresponding MyHDL code * it may be necessary to include technology-dependent modules in the Verilog output As a conclusion, MyHDL users need a method to include user-defined Verilog code during the conversion process. Solution ~~~~~~~~ MyHDL 0.5 defines a hook that is understood by ``toVerilog`` but ignored by the MyHDL simulator. The hook is called ``__verilog__``. Its operation can be understood as a special return value. When a MyHDL function defines ``__verilog__``, the Verilog converter will use its value instead of the regular return value. The value of ``__verilog__`` should be a format string that uses keys in its format specifiers. The keys refer to the variable names in the context of the string. Example:: def inc_comb(nextCount, count, n): @always_comb def logic(): nextCount.next = (count + 1) % n __verilog__ = \ """ assign %(nextCount)s = (%(count)s + 1) %% %(n)s; """ nextCount.driven = "wire" return logic In this example, conversion of the ``inc_comb`` function is bypassed and the user-defined Verilog code is inserted instead. Note that the user-defined code refers to signals and parameters in the MyHDL context by using format specifiers. During conversion, the appropriate hierarchical names and parameter values will be filled in. Note also that the format specifier indicator `%` needs to be escaped (by doubling it) if it is required in the user-defined code. There is one more issue that needs user attention. Normally, the Verilog converter infers inputs, internal signals, and outputs. It also detects undriven and multiple driven signals. To do this, it assumes that signals are not driven by default. It then processes the code to find out which signals are driven from where. However, it cannot do this for user-defined code. Without additional help, this will result in warnings or errors during the inference process, or in compilation errors from invalid Verilog code. The user should solve this by setting the ``driven`` attribute for signals that are driven from the user-defined code. In the example code above, note the following assignment:: nextCount.driven = "wire" This specifies that the ``nextCount`` signal is driven as a Verilog wire from this module. The allowed values of the ``driven`` attribute are ``"wire"`` and ``"reg"``. The value specifies how the user-defined Verilog code drives the signal in Verilog. To decide which value to use, consider how the signal should be declared in Verilog after the user-defined code is inserted. Limitations ~~~~~~~~~~~ It is not possible to use the ``__verilog__`` hook in a generator function - it should be in a classic function. This is because in MyHDL those functions are completely run (elaborated) before the conversion starts, while generator functions are not. More info ~~~~~~~~~ For more information about the background and the design decisions regarding user-defined Verilog code, see `mep-101`_. Backwards incompatible changes ------------------------------ Verilog conversion output filename ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ A Verilog conversion is performed with a call that looks as follows:: instance_name = toVerilog(func, ...) In MyHDL 0.4, the Verilog output filename was called ``instance_name.v``. In MyHDL 0.5, the default output filename is ``func_name.v``, where ``func_name`` is the name of the function, available as the ``func.func_name`` attribute. This was done for the following reasons. The MyHDL 0.4 was overly clever and therefore complicated. It involves frame handling and parsing the source file for the assignment pattern. Besides being too clever, it also had awkward limitations. For example, it was not possible to construct a dynamic name for the instance, which is very un-Pythonic behavior. Both the implementation complexity and the limitations are gone with the new behavior: the name of the top-level function argument is simply used. In addition, it is now possible to specify a user-defined name for the instance as follows:: toVerilog.name = "my_name" toVerilog(func, ....) To support this feature, it was necessary to make toVerilog an instance of a class with a call interface. **Warning**: When existing converting code is re-run, the Verilog output filename will be different than in 0.4. Simulation ========== Performance optimizations ------------------------- To improve the simulation performance of MyHDL, we mainly put our trust in Python development itself. There are good reasons to be optimistic. What MyHDL itself can do is to minimize the overhead of the simulation loop. In MyHDL 0.5, a first step was taken in this respect. MyHDL supports a number of "trigger objects". These are the objects that can occur in ``yield`` statements, for example :class:`delay`, ``posedge``, :class:`Signal`, and generator objects. Each of these are handled differently and so the simulation loop has to account for the object type. Prior to MyHDL 0.5, this type check was explicitly done for each occurrence of a ``yield`` statement during simulation. As many generators will loop endlessly, it is clear that the same things will be checked over and over again, resulting in an important overhead. In MyHDL 0.5, all generators are predigested. Certain trigger object patterns that tend to occur often are given specialized simulation handlers, so that continuously performing the same type check is avoided. More specifically, they consist of generators that only contain ``yield`` statements with a specific argument. Currently, 5 different kinds of generators are recognized and accelerated, corresponding to the following ``yield`` statement arguments: * a :class:`delay` object * a :class:`Signal` object * a tuple of :class:`Signal` objects * a ``posedge`` or ``negedge`` object * a tuple of ``posedge`` and/or ``negedge`` objects Backwards incompatible changes ------------------------------ Waveform tracing output filename ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Waveform tracing is initiated by a call that looks as follows:: instance_name = traceSignals(func, ...) In MyHDL 0.4, the output filename was called `instance_name.vcd`. In MyHDL 0.5, the default output filename is `func_name.vcd`, where `func_name` is the name of the function, available as the `func.func_name` attribute. This was done for the same reasons as in the similar case for `toVerilog`, as described earlier. A user-defined name for the output file can be specified as follows:: traceSignals.name = "my_name" inst = traceSignals(func, ....) **Warning**: When existing converting code is re-run, the vcd output filename will be different than in 0.4. .. _mep-100: http://dev.myhdl.org/meps/mep-100.html .. _mep-101: http://dev.myhdl.org/meps/mep-101.html myhdl-0.11/doc/source/whatsnew/0.6.rst000066400000000000000000000561051347432460400175300ustar00rootroot00000000000000.. currentmodule:: myhdl .. _new06: *********************** What's new in MyHDL 0.6 *********************** Conversion to VHDL ================== Rationale --------- Since the MyHDL to Verilog conversion has been developed, a path to implementation from MyHDL is available. Given the widespread support for Verilog, it could thus be argued that there was no real need for a converter to VHDL. However, it turns out that VHDL is still very much alive and will remain so for the foreseeable future. This is especially true for the FPGA market, which is especially interesting for MyHDL. It seems much more dynamic than the ASIC market. Moreover, because of the nature of FPGA's, FPGA designers may be more willing to try out new ideas. To convince designers to use a new tool, it should integrate with their current design flow. That is why the MyHDL to VHDL converter is needed. It should lower the threshold for VHDL designers to start using MyHDL. Advantages ---------- MyHDL to VHDL conversion offers the following advantages: MyHDL integration in a VHDL-based design flow Designers can start using MyHDL and benefit from its power and flexibility, within the context of their proven design flow. The converter automates a number of hard tasks The converter automates a number of tasks that are hard to do in VHDL directly. For example, when mixing ``unsigned`` and ``signed`` types it can be difficult to describe the desired behavior correctly. In contrast, a MyHDL designer can use the high-level ``intbv`` type, and let the converter deal with type conversions and resizings. MyHDL as an IP development platform The possibility to convert the same MyHDL source to equivalent Verilog and VHDL creates a novel application: using MyHDL as an IP development platform. IP developers can serve customers for both target languages from a single MyHDL code base. Moreover, MyHDL's flexibility and parametrizability make it ideally suited to this application. Solution description -------------------- Approach ^^^^^^^^ The approach followed to convert MyHDL code to VHDL is identical to the one followed for conversion to Verilog in previous MyHDL releases. In particular, the MyHDL code analyzer in the converter is identical for both target languages. The goal is that all MyHDL code that can be converted to Verilog can be converted to VHDL also, and vice versa. This has been achieved except for a few minor issues due to limitations of the target languages. User interface ^^^^^^^^^^^^^^ Conversion to VHDL is implemented by the following function in the ``myhdl`` package: .. function:: toVHDL(func[, *args][, **kwargs]) :noindex: Converts a MyHDL design instance to equivalent VHDL code. *func* is a function that returns an instance. :func:`toVHDL` calls *func* under its control and passes *\*args* and *\*\*kwargs* to the call. The return value is the same as the one returned by the call ``func(*args, **kwargs)``. It can be assigned to an instance name. The top-level instance name and the basename of the Verilog output filename is ``func.func_name`` by default. :func:`toVHDL` has the following attributes: .. attribute:: toVHDL.name This attribute is used to overwrite the default top-level instance name and the basename of the VHDL output. .. attribute:: toVHDL.component_declarations This attribute can be used to add component declarations to the VHDL output. When a string is assigned to it, it will be copied to the appropriate place in the output file. Type mapping ^^^^^^^^^^^^^ In contrast to Verilog, VHDL is a strongly typed language. The converter has to carefully perform type inferencing, and handle type conversions and resizings appropriately. To do this right, a well-chosen mapping from MyHDL types to VHDL types is crucial. MyHDL types are mapped to VHDL types according to the following table: +--------------------------------------------+-----------------------------------+-----------+ | MyHDL type | VHDL type | Notes | +============================================+===================================+===========+ | ``int`` | ``integer`` | | +--------------------------------------------+-----------------------------------+-----------+ | ``bool`` | ``std_logic`` | \(1) | +--------------------------------------------+-----------------------------------+-----------+ | ``intbv`` with ``min >= 0`` | ``unsigned`` | \(2) | +--------------------------------------------+-----------------------------------+-----------+ | ``intbv`` with ``min < 0`` | ``signed`` | \(2) | +--------------------------------------------+-----------------------------------+-----------+ | ``enum`` | dedicated enumeration type | | +--------------------------------------------+-----------------------------------+-----------+ | ``tuple`` of ``int`` | mapped to case statement | \(3) | +--------------------------------------------+-----------------------------------+-----------+ | ``list`` of ``bool`` | ``array of std_logic`` | | +--------------------------------------------+-----------------------------------+-----------+ | ``list`` of ``intbv`` with ``min >= 0`` | ``array of unsigned`` | \(4) | +--------------------------------------------+-----------------------------------+-----------+ | ``list`` of ``intbv`` with ``min < 0`` | ``array of signed`` | \(4) | +--------------------------------------------+-----------------------------------+-----------+ Notes: (1) The VHDL ``std_logic`` type is defined in the standard VHDL package ``IEEE.std_logic_1164``. (2) The VHDL ``unsigned`` and ``signed`` types used are those from the standard VHDL packages ``IEEE.numeric_std``. (3) A MyHDL ``tuple`` of ``int`` is used for ROM inference, and can only be used in a very specific way: an indexing operation into the tuple should be the rhs of an assignment. (4) All list members should have identical value constraints. The table as presented applies to MyHDL variables. They are mapped to VHDL variables (except for the case of a ``tuple`` of ``int``). The converter also supports MyHDL signals that use ``bool``, ``intbv`` or ``enum`` objects as their underlying type. These are mapped to VHDL signals with a type as specified in the table above. The converter supports MyHDL list of signals provided the underlying signal type is either ``bool`` or ``intbv``. They may be mapped to a VHDL signal with a VHDL type as specified in the table. However, list of signals are not always mapped to a corresponding VHDL signal. See :ref:`new06-listofsigs` for more info. Template transformation ^^^^^^^^^^^^^^^^^^^^^^^ There is a difference between VHDL and Verilog in the way in which sensitivity to signal edges is specified. In Verilog, edge specifiers can be used directly in the sensitivity list. In VHDL, this is not possible: only signals can be used in the sensitivity list. To check for an edge, one uses the ``rising_edge()`` or ``falling_edge()`` functions in the code. MyHDL follows the Verilog scheme to specify edges in the sensitivity list. Consequently, when mapping such code to VHDL, it needs to be transformed to equivalent VHDL. This is an important issue because it affects all synthesizable templates that infer sequential logic. We will illustrate this feature with some examples. This is the MyHDL code for a D flip-flop:: @always(clk.posedge) def logic(): q.next = d It is converted to VHDL as follows:: DFF_LOGIC: process (clk) is begin if rising_edge(clk) then q <= d; end if; end process DFF_LOGIC; The converter can handle the more general case. For example, this is MyHDL code for a D flip-flop with asynchronous set, asynchronous reset, and preference of set over reset:: @always(clk.posedge, set.negedge, rst.negedge) def logic(): if set == 0: q.next = 1 elif rst == 0: q.next = 0 else: q.next = d This is converted to VHDL as follows:: DFFSR_LOGIC: process (clk, set, rst) is begin if (set = '0') then q <= '1'; elsif (rst = '0') then q <= '0'; elsif rising_edge(clk) then q <= d; end if; end process DFFSR_LOGIC; All cases with practical utility can be handled in this way. However, there are other cases that cannot be transformed to equivalent VHDL. The converter will detect those cases and give an error. .. _new06-listofsigs: Conversion of lists of signals ============================== Lists of signals are useful for many purposes. For example, they make it easy to create a repetitive structure. Another application is the description of memory behavior. The converter output is non-hierarchical. That implies that all signals are declared at the top-level in VHDL or Verilog (as VHDL signals, or Verilog regs and wires.) However, some signals that are a list member at some level in the design hierarchy may be used as a plain signal at a lower level. For such signals, a choice has to be made whether to declare a Verilog memory or VHDL array, or a number of plain signal names. If possible, plain signal declarations are preferred, because Verilog memories and arrays have some restrictions in usage and tool support. This is possible if the list syntax is strictly used outside generator code, for example when lists of signals are used to describe structure. Conversely, when list syntax is used in some generator, then a Verilog memory or VHDL array will be declared. The typical example is the description of RAM memories. The converter in the previous MyHDL release had a severe restriction on the latter case: it didn't allow that, for a certain signal, list syntax was used in some generator, and plain signal syntax in another. This restriction, together with its rather obscure error message, has caused regular user complaints. In this release, this restriction has been lifted. .. _new06-test: Conversion of test benches ========================== Background ---------- After conversion, we obviously want to verify that the VHDL or Verilog code works correctly. In previous MyHDL versions, the proposed verification technique was co-simulation: use the same MyHDL test bench to simulate the converted Verilog code and the original MyHDL code. While co-simulation works well, there are a number of issues with it: * Co-simulation requires that the HDL simulator has an interface to its internal workings, such as ``vpi`` for Verilog and ``vhpi`` for VHDL. * ``vpi`` for Verilog is well-established and available for open-source simulators such as Icarus and cver. However, ``vhpi`` for VHDL is much less established; it is unclear whether there is an open source solution that is powerful enough for MyHDL's purposes. * Even though ``vpi`` is a "standard", there are differences between various simulators. Therefore, some customization is typically required per Verilog simulator. * MyHDL co-simulation uses unix-style interprocess communication that doesn't work on Windows natively. This is an exception to the rest of MyHDL that should run on any Python platform. The conclusion is that co-simulation is probably not a viable solution for the VHDL case, and it has some disadvantages for Verilog as well. The proposed alternative is to convert the test bench itself, so that both test bench and design can be run in the HDL simulator. Of course, this is not a fully general solution either, as there are important restrictions on the kind of code that can be converted. However, with the additional features that have been developed, it should be a useful solution for verifying converted code. Print statement --------------- In previous MyHDL versions, :keyword:`print` statement conversion to Verilog was supported in a quick and dirty way, by merely copying the format string without checks. With the advent of VHDL conversion, this has now been implemented more rigorously. This was necessary because VHDL doesn't work with format strings. Rather, the format string specification has to be converted to a sequence of VHDL ``write`` and ``writeline`` calls. A :keyword:`print` statement with multiple arguments:: print arg1, arg2, ... is supported. However, there are restrictions on the arguments. First, they should be of one of the following forms:: arg formatstring % arg formatstring % (arg1, arg2, ...) where ``arg`` is a ``bool``, ``int``, ``intbv``, ``enum``, or a ``Signal`` of these types. The ``formatstring`` contains ordinary characters and conversion specifiers as in Python. However, the only supported conversion specifiers are ``%s`` and ``%d``. Justification and width specification are thus not supported. Printing without a newline:: print arg1 , is not supported. This is because the solution is based on ``std.textio``. In VHDL ``std.textio``, subsequent ``write()`` calls to a line are only printed upon a ``writeline()`` call. As a normal :keyword:`print` implies a newline, the correct behavior can be guaranteed, but for a :keyword:`print` without newline this is not possible. In the future, other techniques may be used and this restriction may be lifted. Assert statement ---------------- An :keyword:`assert` statement in Python looks as follow:: assert test_expression It can be converted provided ``test_expression`` is convertible. Delay objects ------------- Delay objects are constructed as follows:: delay(t) with ``t`` an integer. They are used in :keyword:`yield` statements and as the argument of :func:`always` decorators, to specify delays. They can now be converted. Methodology notes ----------------- The question is whether the conversion restrictions permit one to develop sufficiently complex test benches. In this section, we present some insights about this. The most important restrictions are the types that can be used. These remain "hardware-oriented" as before. Even in the previous MyHDL release, the "convertible subset" was much wider than the "synthesis subset". For example, :keyword:`while` and :keyword:`raise` statement were already convertible. The support for :func:`delay()` objects is the most important new feature to write high-level models and test benches. With the :keyword:`print` statement, simple debugging can be done. Of particular interest is the :keyword:`assert` statement. Originally, :keyword:`assert` statements were only intended to insert debugging assertions in code. Recently, there is a tendency to use them to write self-checking unit tests, controlled by unit test frameworks such as ``py.test``. In particular, they are a powerful way to write self-checking test benches for MyHDL designs. As :keyword:`assert` statements are now convertible, a whole test suite in MyHDL can be converted to an equivalent test suite in Verilog and VHDL. Finally, the same techniques as for synthesizable code can be used to master complexity. In particular, any code outside generators is executed during elaboration, and therefore not considered in the conversion process. This feature can for example be used for complex calculations that set up constants or expected results. Furthermore, a tuple of ints can be used to hold a table of values that will be mapped to a case statement in Verilog and VHDL. Conversion output verification ============================== .. note:: This functionality is not needed in a typical design flow. It is only relevant to debug the MyHDL converter itself. Approach -------- To verify the converter output, a methodology has been developed and implemented that doesn't rely on co-simulation and works for both Verilog and VHDL. The solution builds on the features explained in section :ref:`new06-test`. The idea is basically to convert the test bench as well as the functional code. In particular, ``print`` statements in MyHDL are converted to equivalent statements in the HDL. The verification process consists of running both the MyHDL and the HDL simulation, comparing the simulation output, and reporting any differences. The goal is to make the verification process as easy as possible. The use of ``print`` statements to debug a design is a very common and simple technique. The verification process itself is implemented in a single function with an interface that is identical to ``toVHDL`` and ``toVerilog``. As this is a native Python solution, it runs on any platform on which the HDL simulator runs. Moreover, any HDL simulator can be used as no ``vpi`` or ``vhpi`` capabilities are needed. Of course, per HDL simulator some customization is required to define the details on how it is used. This needs to be done once per HDL simulator and is fully under user control. Verification interface ---------------------- All functions related to conversion verification are implemented in the ``myhdl.conversion`` package. (To keep the ``myhdl`` namespace clean, they are not available from the ``myhdl`` namespace directly.) .. function:: verify(func[, *args][, **kwargs]) Used like :func:`toVHDL()`. It converts MyHDL code, simulates both the MyHDL code and the HDL code and reports any differences. The default HDL simulator is GHDL. .. function:: analyze(func[, *args][, **kwargs]) Used like :func:`toVHDL()`. It converts MyHDL code, and analyzes the resulting HDL. Used to verify whether the HDL output is syntactically correct. The two previous functions have the following attribute: .. attribute:: analyze.simulator Used to set the name of the HDL analyzer. GHDL is the default. .. attribute:: verify.simulator Used to set the name of the HDL simulator. GHDL is the default. HDL simulator registration -------------------------- To be able to use a HDL simulator to verify conversions, it needs to be registered first. This is needed once per simulator (or rather, per set of analysis and simulation commands). Registering is done with the following function: .. function:: registerSimulator(name=None, hdl=None, analyze=None, elaborate=None, simulate=None, offset=0) Registers a particular HDL simulator to be used by :func:`verify()` and :func:`analyze()`. *name* is the name of the simulator. *hdl* specifies the HDL: ``"VHDL"`` or ``"Verilog"``. *analyze* is a command string to analyze the HDL source code. *elaborate* is a command string to elaborate the HDL code. This command is optional. *simulate* is a command string to simulate the HDL code. *offset* is an integer specifying the number of initial lines to be ignored from the HDL simulator output. The command strings should be string templates that refer to the ``topname`` variable that specifies the design name. The templates can also use the ``unitname`` variable which is the lower case version of ``topname``. The command strings can assume that a subdirectory called ``work`` is available in the current working directory. Analysis and elaboration results can be put there if desired. The :func:`analyze()` function runs the *analyze* command. The :func:`verify()` function runs the *analyze* command, then the *elaborate* command if any, and then the *simulate* command. The GHDL simulator is registered by default, but its registration can be overwritten if required. Example: preregistered HDL simulators ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ A number of open-source HDL simulators are preregistered in the MyHDL distribution. If they are installed in the typical way, they are readily available for conversion verification. We will illustrate the registration process by showing the registrations of these simulators. GHDL registration:: registerSimulator( name="GHDL", hdl="VHDL", analyze="ghdl -a --workdir=work pck_myhdl_%(version)s.vhd %(topname)s.vhd", elaborate="ghdl -e --workdir=work -o %(unitname)s_ghdl %(topname)s", simulate="ghdl -r %(unitname)s_ghdl" ) Icarus registration:: registerSimulator( name="icarus", hdl="Verilog", analyze="iverilog -o %(topname)s.o %(topname)s.v", simulate="vvp %(topname)s.o" ) cver registration:: registerSimulator( name="cver", hdl="Verilog", analyze="cver -c -q %(topname)s.v", simulate="cver -q %(topname)s.v", offset=3 ) New modeling features ===================== New signed() method for intbv ----------------------------- The :class:`intbv` object has a new method :meth:`signed()` that implements sign extension. The extended bit is the msb bit of the bit representation of the object. Clearly, this method only has an effect for :class:`intbv` objects whose valid values are a finite range of positive integers. This method can be converted to VHDL and Verilog. always_comb and list of signals ------------------------------- In the previous MyHDL release, one could use lists of signals in an :func:`always_comb` block, but they were not considered to infer the sensitivity list. To several users, this was unexpected behavior, or even a bug. In the present release, lists of signals are considered and the corresponding signals are added to the sensitivity list. The converter to Verilog and VHDL is adapted accordingly. Backwards incompatible changes ============================== .. _new06-deco: Decorator usage --------------- The basic building block of a MyHDL design is a specialized Python generator. In MyHDL 0.5, decorators were introduced to make it easier to create useful MyHDL generators. Moreover, they make the code clearer. As a result, they are now the de facto standard to describe hardware modules in MyHDL. The implementation of certain tasks, such a signal tracing and conversion, can be simplified significantly if decorators are used to create the generators. These simplifications have now been adopted in the code. This means that decorator usage is assumed. Legacy code written for the mentioned purposes without decorators, can always be easily converted into code with decorators. For pure modeling, it doesn't matter how generators are created and this will remain so. Therefore, designers can continue to experiment with innovative modeling concepts in the fullest generality. instances() function -------------------- The :func:`instances()` function can be used to automatically lookup and return the instances that are defined in a MyHDL module. In accordance with the section :ref:`new06-deco`, its functionality has been changed. Only generators created by decorators are considered when looking up instances. Conversion of printing without a newline ---------------------------------------- Printing without a newline (a print statement followed by a comma) is no longer supported by the converter to Verilog. This is done to be compatible with the converter to VHDL. Currently, the VHDL solution relies on ``std.textio`` and this implies that printing without a newline cannot be reliably converted. myhdl-0.11/doc/source/whatsnew/0.7.rst000066400000000000000000000352451347432460400175330ustar00rootroot00000000000000.. currentmodule:: myhdl .. _new07: *********************** What's new in MyHDL 0.7 *********************** Conversion to VHDL/Verilog rewritten with the ``ast`` module ============================================================ The most important code change is a change that hopefully no-one will notice :-). The conversion code is now based on the ``ast`` package instead of the ``compiler`` package. Since Python 2.6, the ``compiler`` package is deprecated and replaced by the new ``ast`` package in the standard library. In Python 3, the ``compiler`` package is no longer available. This was a considerable effort, spent on re-implementing existing behavior instead of on new interesting features. This was unfortunate, but it had to be done with priority. Now the conversion code is ready for the future. Shadow signals ============== Background ---------- Compared to HDLs such as VHDL and Verilog, MyHDL signals are less flexible for structural modeling. For example, slicing a signal returns a slice of the current value. For behavioral code, this is just fine. However, it implies that you cannot use such as slice in structural descriptions. In other words, a signal slice cannot be used as a signal. To solve these issues, a new concept was introduced: shadow signals. The whole reasoning behind shadow signals is explained in more detail in `mep-105`_. .. _mep-105: http://www.myhdl.org/doku.php/meps:mep-105 Introducing shadow signals -------------------------- A shadow signal is related to another signal or signals as a shadow to its parent object. It follows any change to its parent signal or signals directly. However, it is not the same as the original: in particular, the user cannot assign to a shadow signal. Also, there may be a delta cycle delay between a change in the original and the corresponding change in the shadow signal. Finally, to be useful, the shadow signal performs some kind of transformation of the values of its parent signal or signals. A shadow signal is convenient because it is directly constructed from its parent signals. The constructor infers everything that's needed: the type info, the initial value, and the transformation of the parent signal values. For simulation, the transformation is defined by a generator which is automatically created and added to the list of generators to be simulated. For conversion, the constructor defines a piece of dedicated Verilog and VHDL code which is automatically added to the converter output. Currently, three kinds of shadow signals have been implemented. The original inspiration for shadow signals was to have solution for structural slicing. This is the purpose of the :class:`_SliceSignal` subclass. The opposite is also useful: a signal that shadows a composition of other signals. This is the purpose of the :class:`ConcatSignal` subclass. As often is the case, the idea of shadow signals had some useful side effects. In particular, I realized that the :class:`TristateSignal` proposed in `mep-103`_ could be interpreted as a shadow signal of its drivers. With the machinery of the shadow signal in place, it became easier to support this for simulation and conversion. .. _mep-103: http://www.myhdl.org/doku.php/meps:mep-103 Concrete shadow signal subclasses --------------------------------- .. class:: _SliceSignal(sig, left[, right=None]) :noindex: This class implements read-only structural slicing and indexing. It creates a new signal that shadows the slice or index of the parent signal *sig*. If the *right* parameter is omitted, you get indexing instead of slicing. Parameters *left* and *right* have the usual meaning for slice indices: in particular, *left* is non-inclusive but *right* is inclusive. *sig* should be appropriate for slicing and indexing, which means it should be based on :class:`intbv` in practice. The class constructors is not intended to be used explicitly. Instead, regular signals now have a call interface that returns a :class:`_SliceSignal`: .. method:: Signal.__call__(left[, right=None]) :noindex: Therefore, instead of:: sl = _SliceSignal(sig, left, right) you can do:: sl = sig(left, right) Obviously, the call interface was intended to be similar to a slicing interface. Of course, it is not exactly the same which may seem inconvenient. On the other hand, there are Python functions with a similar slicing functionality and a similar interface, such as the ``range`` function. Moreover, the call interface conveys the notion that something is being constructed, which is what really happens. .. class:: ConcatSignal(*args) :noindex: This class creates a new signal that shadows the concatenation of its parent signal values. You can pass an arbitrary number of signals to the constructor. The signal arguments should be bit-oriented with a defined number of bits. .. class:: TristateSignal(val) :noindex: This class is used to construct a new tristate signal. The underlying type is specified by the *val* parameter. It is a Signal subclass and has the usual attributes, with one exception: it doesn't support the ``next`` attribute. Consequently, direct signal assignment to a tristate signal is not supported. The initial value is the tristate value ``None``. The current value of a tristate is determined by resolving the values from its drivers. When exactly one driver value is different from ``None``, that is the resolved value; otherwise it is ``None``. When more than one driver value is different from ``None``, a contention warning is issued. This class has the following method: .. method:: driver() :noindex: Returns a new driver to the tristate signal. It is initialized to ``None``. A driver object is an instance of a special :class:`SignalType` subclass. In particular, its ``next`` attribute can be used to assign a new value to it. Example ------- A typical application of shadow signals is conversion of list of signals to bit vectors and vice versa. For example, suppose we have a system with N requesters that need arbitration. Each requester has a ``request`` output and a ``grant`` input. To connect them in the system, we can use list of signals. For example, a list of request signals can be constructed as follows:: request_list = [Signal(bool()) for i in range(M)] Suppose that an arbiter module is available that is instantiated as follows:: arb = arbiter(grant_vector, request_vector, clock, reset) The ``request_vector`` input is a bit vector that can have any of its bits asserted. The ``grant_vector`` is an output bit vector with just a single bit asserted, or none. Such a module is typically based on bit vectors because they are easy to process in RTL code. In MyHDL, a bit vector is modeled using the :class:`intbv` type. We need a way to "connect" the list of signals to the bit vector and vice versa. Of course, we can do this with explicit code, but shadow signals can do this automatically. For example, we can construct a ``request_vector`` as a :class:`ConcatSignal` object:: request_vector = ConcatSignal(*reversed(request_list) Note that we reverse the list first. This is done because the index range of lists is the inverse of the range of :class:`intbv` bit vectors. By reversing, the indices correspond to the same bit. The inverse problem exist for the ``grant_vector``. It would be defined as follows:: grant_vector = Signal(intbv(0)[M:]) To construct a list of signals that are connected automatically to the bit vector, we can use the :class:`Signal` call interface to construct :class:`_SliceSignal` objects:: grant_list = [grant_vector(i) for i in range(M)] Note the round brackets used for this type of slicing. Also, it may not be necessary to construct this list explicitly. You can simply use ``grant_vector(i)`` in an instantiation. To decide when to use normal or shadow signals, consider the data flow. Use normal signals to connect to *outputs*. Use shadow signals to transform these signals so that they can be used as *inputs*. Using :class:`Signal` and :class:`intbv` objects as indices =========================================================== Previously, it was necessary convert :class:`Signal` and :class:`intbv` objects explicitly to :class:`int` when using them as indices for indexing and slicing. This conversion is no longer required; the objects can be used directly. The corresponding classes now have an :func:`__index__` method that takes care of the type conversion automatically. This feature is fully supported by the VHDL/Verilog converter. New configuration attributes for conversion file headers ======================================================== New configuration attributes are available to control the file headers of converted output files. .. attribute:: toVerilog.no_myhdl_header Specifies that MyHDL conversion to Verilog should not generate a default header. Default value is *False*. .. attribute:: toVHDL.no_myhdl_header Specifies that MyHDL conversion to VHDL should not generate a default header. Default value is *False*. .. attribute:: toVerilog.header Specifies an additional custom header for Verilog output. .. attribute:: toVHDL.header Specifies an additional custom header for VHDL output. The value for the custom headers should be a string that is suitable for the standard :class:`string.Template` constructor. A number of variables (indicated by a ``$`` prefix) are available for string interpolation. For example, the standard header is defined as follows:: myhdl_header = """\ -- File: $filename -- Generated by MyHDL $version -- Date: $date """ The same interpolation variables are available in custom headers. Conversion propagates docstrings ================================ The converter now propagates comments under the form of Python docstrings. Docstrings are typically used in Python to document certain objects in a standard way. Such "official" docstrings are put into the converted output at appropriate locations. The converter supports official docstrings for the top level module and for generators. Within generators, "nonofficial" docstrings are propagated also. These are strings (triple quoted by convention) that can occur anywhere between statements. Regular Python comments are ignored by the Python parser, and they are not present in the parse tree. Therefore, these are not propagated. With docstrings, you have an elegant way to specify which comments should be propagated and which not. New method to specify user-defined code ======================================= The current way to specify user-defined code for conversion is through the ``__vhdl__`` and ``__verilog__`` hooks. This method has a number of disadvantages. First, the use of "magic" variables (whose names start and end with double underscores) was a bad choice. According to Python conventions, such variables should be reserved for the Python language itself. Moreover, when new hooks would become desirable, we would have to specify additional magic variables. A second problem that standard Python strings were used to define the user-defined output. These strings can contain the signal names from the context for interpolation. Typically, these are multiple-line strings that may be quite lengthy. When something goes wrong with the string interpolation, the error messages may be quite cryptic as the line and column information is not present. For these reasons, a new way to specify user-defined code has been implemented that avoids these problems. The proper way to specify meta-information of a function is by using function attributes. Suppose a function :func:`` defines a hardware module. We can now specify user-defined code for it with the following function attributes: .. attribute:: .vhdl_code A template string for user-defined code in the VHDL output. .. attribute:: .verilog_code A template string for user-defined code in the Verilog output. When such a function attribute is defined, the normal conversion process is bypassed and the user-defined code is inserted instead. The template strings should be suitable for the standard :class:`string.Template` constructor. They can contain interpolation variables (indicated by a ``$`` prefix) for all signals in the context. Note that the function attribute can be defined anywhere where :func:`` is visible, either outside or inside the function itself. The old method for user-defined code is still available but is deprecated and will be unsupported in the future. More powerful mapping to case statements ======================================== The converter has become more powerful to map if-then-else structures to case statements in VHDL and Verilog. Previously, only if-then-else structures testing enumerated types were considered. Now, integer tests are considered also. Small changes ============= :class:`SignalType` as the base class of Signals ------------------------------------------------ :func:`Signal` has become a function instead of a class. It returns different Signal subtypes depending on parameters. This implies that you cannot use :func:`Signal` for type checking. The base type of all Signals is now :class:`SignalType`. This type can be used to check whether an object is a Signal instance. Default value of :class:`intbv` objects --------------------------------------- The default initial value of an :class:`intbv` object has been changed from *None* to ``0``. Though this is backward-incompatible, the *None* value never has been put to good use, so this is most likely not an issue. Combinatorial always blocks use blocking assignments ---------------------------------------------------- The converter now uses blocking assignments for combinatorial always blocks in Verilog. This is in line with generally accepted Verilog coding conventions. No synthesis pragmas in Verilog output -------------------------------------- The converter no longer outputs the synthesis pragmas ``full_case`` and ``parallel_case``. These pragmas do more harm than good as they can cause simulation-synthesis mismatches. Synthesis tools should be able to infer the appropriate optimizations from the source code directly. Python version ============== MyHDL 0.7 requires Python 2.6, mainly because of its dependency on the new ``ast`` package. Acknowledgments =============== Several people have contributed to MyHDL 0.7 by giving feedback, making suggestions, fixing bugs and implementing features. In particular, I would like to thank Benoit Allard, Günter Dannoritzer, Tom Dillon, Knut Eldhuset, Angel Ezquerra, Christopher Felton, and Jian LUO. Thanks to Francesco Balau for packaging MyHDL for Ubuntu. I would also like to thank `Easics`_ for the opportunity to use MyHDL in industrial projects. .. _`Easics`: http://www.easics.com myhdl-0.11/doc/source/whatsnew/0.8.rst000066400000000000000000000302101347432460400175170ustar00rootroot00000000000000.. currentmodule:: myhdl .. _new08: *********************** What's new in MyHDL 0.8 *********************** Modular bit vector types ======================== Rationale --------- In hardware modeling, there is often a need for the elegant modeling of wrap-around behavior. :class:`intbv` instances don't provide this automatically, because they assert that any assigned value is within the bound constraints. Therefore, one has currently has to use other language features for wrap-around modeling. Often, this is straightforward. For example, the wrap-around condition for a counter is often decoded explicitly, as it is needed for other purposes. Also, the modulo operator provides an elegant one-liner in most scenarios. However, in some important cases the current solution is not satisfactory. For example, we would like to describe a free running counter using a variable and augmented assignment as follows:: count += 1 This is not possible with the :class:`intbv` type, as we cannot add the modulo behavior to this description. A similar problem exist of for a left shift as follows:: shifter <<= 4 These operations can only supported directly with a new type. For these reasons, it was felt that this would be a useful addition to MyHDL. Solution -------- The proposed solution is to borrow the idea behind Ada modular types. These are natural integer types with wrap-around behaviour. The wrap-around behavior of modular types is based on the sound mathematical concept of modulo arithmetic. Therefore, the modulus is not limited to powers of 2. Ada's modular type is called :class:`mod`. In MyHDL, we want also want to give it "bit-vector" support, like :class:`intbv`. Therefore, proposed MyHDL type is called :class:`modbv`. Implementation -------------- :class:`modbv` is implemented as a subclass of :class:`intbv`. The two classes have an identical interface and work together in a straightforward way for arithmetic operations. The only difference is how the bounds are handled: out-of-bound values result in an error with :class:`intbv`, and in wrap-around with :class:`modbv`. The Wrap-around behavior would be defined as follows, with val denoting the current value and min/max the bounds:: val = (val - min) % (max - min) + min Interface --------- .. class:: modbv([val=0] [, min=None] [, max=None]) :noindex: The :class:`modbv` class implements modular bit vector types. It is implemented as a subclass of :class:`intbv` and supports the same parameters and operators. The difference is in the handling of the *min* and *max* boundaries. Instead of throwing an exception when those constraints are exceeded, the value of :class:`modbv` objects wraps around according to the following formula:: val = (val - min) % (max - min) + min This formula is a generalization of modulo wrap-around behavior that is often useful when describing hardware system behavior. Conversion ---------- :dfn:`Full-range` :class:`modbv` objects are those where the max bound is a power of 2, and the min bound is 0 or the negative of the max bound. For these objects, conversion worked out-of-the-box because this corresponds to the target types in Verilog and VHDL. Currently, conversion is restricted to full-range :class:`modbv` objects. It may be possible to support conversion of the modulo behavior of more general cases, but this requires more sophistication in the converter. This may be considered in the future. See also -------- For a more in-depth discussion, see `mep-106`_. .. _mep-106: http://www.myhdl.org/doku.php/meps:mep-106 ``always_seq`` decorator ======================== Rationale --------- In classical synthesizable RTL coding, the reset behavior is described explicitly. A typical template is as follows:: @always(clock.posedge, reset.negedge) def seq(): if reset == 0: else: The reset behavior is described using a the top-level if-else structure with a number of assignments under the if. A significant piece of code at a prominent location is therefore dedicated to non-functional behavior. Reset behavior coding is error-prone. For a proper gate-level implementation, most if not all registers should typically be reset. However, it is easy to forget some reset assignments. Such bugs are not necessarily easily detected during RTL or gate-level simulations. In the template, the edge that asserts reset is in the sensitivity list. It is easy to forget this, and in that case the reset will not behave asynchronously as intended but synchronously. Note also that it is somewhat strange to specify an edge sensitivity when describing asynchronous behavior. Solution -------- The proposed solution is to infer the reset structure automatically. The main idea is to use the initial values of signals as the specification of reset values. This is possible in MyHDL, because all objects are constructed with an initial value. The assumption is that the initial value also specifies the desired reset value. The solution is implemented with two new MyHDL constructs. The first one is a new decorator called :func:`always_seq`. Using this decorator, code with identical behavior as in the previous section can be described as follows:: @always_seq(clock.posedge, reset=reset) The :func:`always_seq` decorator takes two arguments: a clock edge and a reset signal. It inspects the code to find the registers, and uses the initial values to construct the reset behavior. The second construct is a specialized signal subclass called :class:`ResetSignal`. It is used as follows:: reset = ResetSignal(1, active=0, async=True) The ResetSignal constructor has three arguments: the initial value as usual, an *active* argument with the active level, and an *async* argument that specifies whether the reset style is asynchronous or synchronous. The proposed solution has some very desirable features. Explicit reset behavior coding is no longer necessary. Code reviewers are thus no longer distracted by non-functional code. It is sufficient to check the initial values to verify whether the reset value is correctly specified. Moreover, one indentation level is saved for functional coding. Even more importantly, the reset structure is correct by construction. All registers are automatically included in the reset behavior, and the sensitivity list is automatically correct according to the reset style. Traditionally, the reset behavior is spread out over all sequential processes. Therefore, it has to be debugged by investigating all those processes. Even worse, if a change in style or active level is required, all processes are affected. In contrast, with the proposed technique all reset features are specified at single location in the :class:`ResetSignal` constructor. Changes are trivial. For example, to change to an active high synchronous reset one merely has to change the constructor as follows:: reset = ResetSignal(1, active=1, async=False) Occasionally, it is useful to have registers without reset at all. The proposed technique is also useful in that case. In particular, the :func:`always_seq` decorator accepts ``None`` as the reset argument:: @always_seq(clock.posedge, reset=None) A reviewer will have no doubt what the intention is. In contrast, in the case of a traditional always block, the reviewer may think that the designer has delayed the detailed reset coding for later and then forgotten about it. Interface --------- .. function:: always_seq(edge, reset) :noindex: The :func:`always_seq` decorator is used to describe sequential (clocked) logic. The *edge* parameter should be a clock edge (``clock.posedge`` or ``clock.negedge``). The *reset* parameter should a :class:`ResetSignal` object. .. class:: ResetSignal(val, active, async) :noindex: This :class:`Signal` subclass defines reset signals. *val*, *active*, and *async* are mandatory arguments. *val* is a boolean value that specifies the initial value, *active* is a boolean value that specifies the active level. *async* is a boolean value that specifies the reset style: asynchronous (``True``) or asynchronous (``False``). Conversion ---------- As modeling the reset behavior is a typical task in synthesizable RTL coding, the proposed technique is fully convertible to Verilog and VHDL. Limitations ----------- All registers in a process are reset ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ All registers in a process are automatically included in the reset behavior. If it is the intention that some registers should not be reset, those registers and the corresponding code should be factored out in a separate process. Actually, this is not really a limitation but a feature. If some registers in a process are reset and others not, a synthesis tool may generate undesirable feedback loops that are active during the reset condition. This is not good practice and probably not the intention. Register inferencing from variables is not supported ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ An important limitation is that the proposed technique is limited to registers inferred from signals. Registers inferred from variables are not supported, because such state variables cannot be described in classic functions (in particular the functions required by MyHDL decorators such as :func:`always_seq` and :func:`always`). In fact, the reason is a Python2 limitation. Currently, to infer registers from variables, one has to use the :func:`instance` decorator and declare the state variables outside an infinite ``while True`` loop. In Python3, this limitation can be lifted with the introduction of the ``nonlocal`` declaration. This will make it possible for functions to modify variables in the enclosing scope. It should be possible to adapt the :func:`always_seq` and :func:`always` decorators to support such variables. See also -------- For a more in-depth discussion, see `mep-109`_. .. _mep-109: http://www.myhdl.org/doku.php/meps:mep-109 Other improvements ================== Conversion of top-level class methods ------------------------------------- Often it is desirable to embed an HDL module description in a class. Previous versions would only convert a class method if it was not the top-level. This release adds the conversion of top-level class methods. Example ^^^^^^^^ .. code-block:: python class DFilter(object): def __init__(self,delay_length=3,fs=1): def nulls(self): def m_top(self,clock,reset,x,y): clock = Signal(bool(0)) reset = ResetSignal(0,active=0,async=True) x = Signal(intbv(0, min=-8, max=8)) y = Signal(intbv(0, min=-64, max=64)) filt = DFilter() toVerilog(filt.m_top,clock,reset,x,y) toVHDL(filt.m_top,clock,reset,x,y) See also ^^^^^^^^ For a more in-depth discussion, see `mep-108`_. .. _mep-108: http://www.myhdl.org/doku.php/meps:mep-108 Tracing lists of signals ------------------------ Tracing lists of signals is now supported. Contributed by Frederik Teichtert, http://teichert-ing.de . The following shows how the list of signals are displayed in a waveform viewer .. code-block:: python delay_taps = [Signal(intbv(0,min=-8,max=8)) for ii in range(3)] .. image:: los.png :align: center ``library`` attribute for :func:`toVHDL` ---------------------------------------- :func:`toVHDL` now has a ``library`` function that can be used to set the library name in the VHDL output. The assigned value should be a string. The default library is "work". ``timescale`` attribute for :func:`traceSignals` ------------------------------------------------ :func:`traceSignals` now has a ``timescale`` attribute that can be used to set the timescale in the VCD output. The assigned value should be a string. The default timescale is "1ns". Acknowledgments =============== Several people have contributed to MyHDL 0.8 by giving feedback, making suggestions, fixing bugs and implementing features. In particular, I would like to thank Christopher Felton and Frederik Teichert. I would also like to thank `Easics`_ for the opportunity to use MyHDL in industrial projects. .. _`Easics`: http://www.easics.com myhdl-0.11/doc/source/whatsnew/0.9.rst000066400000000000000000000071201347432460400175240ustar00rootroot00000000000000.. currentmodule:: myhdl .. _new09: *********************** What's new in MyHDL 0.9 *********************** Python 3 support ================ Experimental Python 3 support has been added to MyHDL 0.9. This was a major effort to modernize the code. As a result, Python 2 and 3 are supported from a single codebase. See :doc:`/python3` for more info. Interfaces (Conversion of attribute accesses) ============================================= Rationale --------- Complex designs often have many signals that are passed to different levels of hierarchy. Typically, many signals logically belong together. This can be modelled by an *interface*: an object that has a number of :class:`Signal` objects as its attributes. Grouping signals into an interface simplifies the code, improves efficiency, and reduces errors. The following is an example of an *interface* definition:: class Complex: def __init__(self, min=-2, max=2): self.real = Signal(intbv(0, min=min, max=max)) self.imag = Signal(intbv(0, min=min, max=max)) Although previous versions supported interfaces for modeling, they were not convertible. MyHDL 0.9 now supports conversion of designs that use interfaces. The following is an example using the above ``Complex`` interface definition:: a,b = Complex(-8,8), Complex(-8,8) c = Complex(-128,128) def complex_multiply(clock, reset, a, b, c): @always_seq(clock.posedge, reset=reset) def cmult(): c.real.next = (a.real*b.real) - (a.imag*b.imag) c.imag.next = (a.real*b.imag) + (a.imag*b.real) return cmult Solution -------- The proposed solution is to create unique names for attributes which are used by `MyHDL generator`_\s. The converter will create a unique name by using the name of the parent and the name of the attribute along with the name of the MyHDL module instance. The converter will essentially replace the "." with an "_" for each interface element. In essence, interfaces are supported using hierarchical name expansion and name mangling. Note that the MyHDL converter supports interfaces, even though the target HDLs do not. This is another great example where the converter supports a high-level feature that is not available in the target HDLs. See also -------- For additional information see the original proposal `mep-107`_. .. _mep-107: http://dev.myhdl.org/meps/mep-107.html .. _MyHDL generator: http://docs.myhdl.org/en/latest/manual/reference.html#myhdl-generators-and-trigger-objects Other noteworthy improvements ============================= ``ConcatSignal`` interface -------------------------- The interface of :class:`ConcatSignal` was enhanced. In addition to signals, you can now also use constant values in the concatenation. ``std_logic`` type ports ------------------------ :func:`toVHDL` has a new attribute ``std_logic_ports``. When set, only ``std_logic`` type ports are used in the interface of the top-level VHDL module. Development flow ---------------- The MyHDL development flow has been modernized by moving to git and `github`_ for version control. In addition, travis has set up so that all pull requests are tested automatically, enabling continuous intergration. Acknowledgments =============== The Python 3 support effort was coordinated by Keerthan Jaic, who also implemented most of if. Convertible interfaces were championed by Chris Felton, and implemented by Keerthan Jaic. MyHDL development is a collaborative effort, as can be seen on `github`_. Thanks to all who contributed with suggestions, issues and pull requests. .. _github: https://www.github.com/jandecaluwe/myhdl myhdl-0.11/doc/source/whatsnew/los.png000066400000000000000000000454161347432460400200010ustar00rootroot00000000000000‰PNG  IHDR±É»Výÿ ÂiCCPICC ProfileH ­–wTSÉÇç½—^h H'ôŽô*½*ØI ´BB•Å\ATD°¢« ®µ ¢XÁöY”u±`Ce_àGvÏïüö¿ßÍ™™O¾sß¼;÷Íœs Ô²‚4X€t¾HîïÅXÇÀ?PpÊ,v¦À3,,ü«}èC½Q»k.Yë_Ýþ÷„<‡›É C§8™ìt”O£­Œ-Š@|P]/[$0eº å| 'Ír™„fùÐŒOd¸7êÓÂb “ w :#‹„®CþeK>'™…޲›Çâ ‰²YzúJ  l”ðu’þÁ,V‚tM+Iʳ{AŸD_쓜)HcåÎüùvéib4_3¦‰ö”ÌÔˆ tTFs–ÃfùFÌ1Ë”|³] ò ŸãdS²Ï'ˆšcqj”ç§® ’úóBBçtv¦7šûÙgóx‘1sÌáúøÎ±pe¸Ô?3+Bªçñ¼Cæ|RX’ï=KˆÒ˜›æ/}¯@&“Ÿ"ÝK¢ÐOêÃÍü{¿"^dÀÜ:"a¤Ô'1Ù9§ó„R]6s¦gbŠÃ¥yàò£¤9ä°|¤¹>À£?°¶ÀØ?bDÜ‘dÞ+¹Âä$žˆá‰Þ®ƒÉg[˜1¬-­l€äNI|xw{æ®@Ê’ãʘ‘@zV¡çµæo-þ M(ÿ[Ó»€,zÖ[n±Å¬Ùg1’ H@РкÀ˜£ÚàFBA$ˆËð@:‚lÖ"PÊÀPöƒ 'A38.«à&è÷Ác0†Á+0>€)‚ð¢A*¤™BÖ#äùBÁP8 ÅCICùШ*‡ª Pô tº]‡z¡‡Ð 4½…¾ÀLé°lχaO8Ž„—ÁIpœÂ[àJ¸>7Á—à›ð}x~O"!#Jˆ6bŽ8"ÞH(‡$"Bd RŒT 5HÒŠt"w‘dùŒÁahÆã‚ ÀDaؘ ÌÌfL¦Ó„éÀÜÅ b&0ß±T¬:ÖëŒebc“°ÙØ"lö0ö ö ö>vû‡Ã)á q¸\,.· ··׈kÃõâ†p“x<^oŠwŇâYx¾¿  ?ŒÿD ´Ö?BOXO¨ %\ Ü!Œ¦ˆrD}¢31”È!æK‰‡ˆ­ÄÛÄaâIždHr%E’RHëH•¤ÒÒÒ;2™¬Cv"/"'“ È•ääkäAògŠÅ„âMYJS¶PŽPÚ()ï¨TªÕƒGQ·P먗©Ï¨Ÿdh22LŽÌZ™j™&™;2¯e‰²ú²ž²Ëeód+dOÉÞ–—#ÊÈy˱äÖÈU˕뗛”§É[ɇʧËo–?*]~T¯` à«ÀQ(T8¨pYaˆ†ÐtiÞ46míí m˜Ž£Ò™ôz ý8½›>¡¨ h«­˜£X­x^q@ Q2Pb*¥)•*TêSú2Ocžç<î¼MóæÝ™÷QYMÙC™«\¬Ü¨|_ù‹ CÅW%Ue«J³ÊSUŒª‰ê"ÕlÕ½ªWTÇÕèj.jlµbµ“jÔauõpõUêÕ»Ô'545ü5»4.kŒk*izh¦hn×¼ 9¦EÓrÓJÖÚ®uQë%C‘áÉHcT2:ÚêÚÚbíÚÝÚS:†:Q:ëuužê’tuu·ë¶ëNèié-ÔË׫×{¤OÔwÔçéïÔïÔÿh`hc°Ñ Ù`ÔPÙi˜gXoøÄˆjän”aTctÏgìhœj¼Ç¸Ç6±3á™T›Ü6…MíM“M÷˜öšaÍœÌøf5fýæsOó,ózóA %‹`‹õͯçëÍ›¿u~çüï–v–i–‡,[)XZ­·jµzkmbͶ®¶¾gCµñ³YkÓbóÆÖÔ–k»×öÍn¡ÝF»v»oööBûû1=‡x‡ÝýŽtÇ0Ç͎ל°N^NkÎ9}v¶w9ŸtþÓÅÜ%Õå¨ËèÃ܇ ¹ê¸²\¸¸1ÜâÝö» ¸k»³ÜkÜŸ{èzp<{Œx{¦xó|íeé%ô:ãõÑÛÙ{µw›âãïSìÓí«àå[åûÌOÇ/ɯÞoÂßΕ[6 (`k@?SƒÉfÖ1'WvQ‚"‚ª‚ž› ƒ[ n[ø$D?„Ò B™¡ÛBŸ††e„ýº·(lQõ¢áVáùá´ˆG#>DzE–F>Ž2ŠGµGËF/®‹þãS3°xþâÕ‹oƪÆ&ǶÄáã¢ãÇM.ñ]²cÉðR»¥EKû–.ËYv}¹êò´åçWÈ®`­8‰?ÿ•ʪaM&0v'L°½Ù;Ù¯8œíœ1®+·œ;’èšXž8šäš´-iŒçΫà'{'W%¿I HÙ—ò154õHêtZLZc:!=>ý,_ŸÊïX©¹2ge¯ÀTP$ÈpÎØ‘1! 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ÒAàÿIm’ì5×ÁÜIEND®B`‚myhdl-0.11/example/000077500000000000000000000000001347432460400142125ustar00rootroot00000000000000myhdl-0.11/example/arith_lib/000077500000000000000000000000001347432460400161475ustar00rootroot00000000000000myhdl-0.11/example/arith_lib/Dec.py000066400000000000000000000016431347432460400172200ustar00rootroot00000000000000import myhdl from myhdl import * from arith_utils import BEHAVIOR from PrefixAnd import PrefixAnd def Dec(width, speed, A, Z, architecture=BEHAVIOR): """ Decrementer module. width -- bitwidth of input and output speed -- SLOW, MEDIUM, or FAST performance A -- input Z -- output architecture -- BEHAVIOR or STRUCTURE architecture selection """ @instance def Behavioral(): while 1: yield A Z.next = A - 1 def Structural(): AI = Signal(intbv(0)) PO = Signal(intbv(0)) prefix = PrefixAnd(width, speed, AI, PO) @instance def logic(): while 1: yield A, PO AI.next = ~A Z.next = A ^ concat(PO[width-1:], '1') return [prefix, logic] if architecture == BEHAVIOR: return Behavioral else: return Structural() myhdl-0.11/example/arith_lib/LeadZeroDet.py000066400000000000000000000025351347432460400206700ustar00rootroot00000000000000import myhdl from myhdl import * from arith_utils import BEHAVIOR from PrefixAnd import PrefixAnd def LeadZeroDet(width, speed, A, Z, architecture=BEHAVIOR): """ Set output bit to 1 at first non-zero MSB bit in input width -- bit width speed -- SLOW, MEDIUM, or FAST performance A -- input Z -- output architecture - BEHAVIOR or STRUCTURE """ @instance def Behavioral(): while 1: yield A zv = intbv(0) for i in downrange(width): if A[i] == 1: zv[i] = 1 break Z.next = zv def Structural(): PI = Signal(intbv(0)) PO = Signal(intbv(0)) PIT = Signal(intbv(0)) POT = Signal(intbv(0)) prefix = PrefixAnd(width, speed, PIT, POT) @instance def logic(): while 1: yield PI, POT, PO, A PI.next = ~A for i in downrange(width): PIT.next[i] = PI[width-i-1] PO.next[i] = POT[width-i-1] Z.next[width-1] = A[width-1] Z.next[width-1:] = PO[width:1] & A[width-1:] return [prefix, logic] if architecture == BEHAVIOR: return Behavioral else: return Structural() myhdl-0.11/example/arith_lib/PrefixAnd.py000066400000000000000000000027211347432460400204030ustar00rootroot00000000000000import myhdl from myhdl import * from arith_utils import log2ceil from arith_utils import SLOW, MEDIUM, FAST def PrefixAnd(width, speed, PI, PO): n = width m = log2ceil(width) def fastPrefix(): PT = Signal(intbv(0)) @instance def logic(): while 1: yield PI, PT PT.next[n:] = PI for l in range(1, m+1): for k in range(2**(m-l)): for i in range(2**(l-1)): if (k*2**l + i) < n: PT.next[l*n + k*2**l + i] = \ PT[(l-1)*n + k*2**l + i] if (k*2**l + 2**(l-1) + i) < n: PT.next[l*n + k*2**l + 2**(l-1) + i] = \ PT[(l-1)*n + k*2**l + 2**(l-1) + i] & \ PT[(l-1)*n + k*2**l + 2**(l-1) - 1] PO.next = PT[(m+1)*n:m*n] return logic def slowPrefix(): PT = Signal(intbv(0)) @instance def logic(): while 1: yield PI, PT PT.next[0] = PI[0] for i in range(1, n): PT.next[i] = PI[i] & PT[i-1] PO.next = PT return logic if speed == SLOW: return slowPrefix() elif speed == FAST: return fastPrefix() else: raise NotImplementedError myhdl-0.11/example/arith_lib/README.txt000066400000000000000000000012471347432460400176510ustar00rootroot00000000000000The examples in this directory are based on VHDL code from the "arith_lib" library, Version 1.0, written by Reto Zimmerman, who holds the copyright for the original code. The project web page is at . I translated a few modules into myhdl/Python and added testbenches to verify and demonstrate myhdl modeling, as well as Python's unit test framework. The arith_lib library is useful for these purposes as it contains a (simple) behavioral architecture as well as a (sometimes complex) structural architecture for each module. The testbenches are the files called test_.py. Run them as follows: python test_.py myhdl-0.11/example/arith_lib/__init__.py000066400000000000000000000000001347432460400202460ustar00rootroot00000000000000myhdl-0.11/example/arith_lib/arith_utils.py000066400000000000000000000003021347432460400210430ustar00rootroot00000000000000SLOW, MEDIUM, FAST = range(3) BEHAVIOR, STRUCTURE = range(2) def log2ceil(n): m = 0 p = 1 for i in range(n+1): if p < n: m += 1 p *= 2 return m myhdl-0.11/example/arith_lib/test_Dec.py000066400000000000000000000032621347432460400202560ustar00rootroot00000000000000import unittest from unittest import TestCase import myhdl from myhdl import * from arith_utils import BEHAVIOR, STRUCTURE from arith_utils import SLOW, FAST from Dec import Dec import random random.seed = 1 from random import random class DecTest(TestCase): """ Decrementer unit test class """ def bench(self, width, speed, nrsamples=0): """ Decrementer test bench width -- decrementer bit width speed -- SLOW, MEDIUM or FAST nrsamples -- required number of random samples, or exhaustive test if not set (default) """ A = Signal(intbv(0)) ZS = Signal(intbv(0)) ZB = Signal(intbv(0)) beh = Dec(width, speed, A, ZB, architecture=BEHAVIOR) str = Dec(width, speed, A, ZS, architecture=STRUCTURE) @instance def stimulus(): if nrsamples: vals = [long(random()*(2**width)) for i in range(nrsamples)] else: vals = range(2**width) for i in vals: A.next = intbv(i) yield delay(10) self.assertEqual(ZS, ZB) return (beh, str, stimulus) def testDecSmallSlow(self): Simulation(self.bench(width=8, speed=SLOW)).run() def testDecLargeSlow(self): Simulation(self.bench(width=39, speed=SLOW, nrsamples=16)).run() def testDecSmallFast(self): Simulation(self.bench(width=8, speed=FAST)).run() def testDecLargeFast(self): Simulation(self.bench(width=39, speed=FAST, nrsamples=16)).run() if __name__ == "__main__": unittest.main() myhdl-0.11/example/arith_lib/test_LeadZeroDet.py000066400000000000000000000034221347432460400217230ustar00rootroot00000000000000import unittest from unittest import TestCase import myhdl from myhdl import * from arith_utils import BEHAVIOR, STRUCTURE from arith_utils import SLOW, FAST from LeadZeroDet import LeadZeroDet import random random.seed = 1 from random import random class LeadZeroDetTest(TestCase): """ Leading zeroes detector unit test class """ def bench(self, width, speed, nrsamples=0): """ Leading zeroes detector test bench width -- decrementer bit width speed -- SLOW, MEDIUM or FAST nrsamples -- required number of random samples, or exhaustive test if not set (default) """ A = Signal(intbv(0)) ZS = Signal(intbv(0)) ZB = Signal(intbv(0)) beh = LeadZeroDet(width, speed, A, ZB, architecture=BEHAVIOR) str = LeadZeroDet(width, speed, A, ZS, architecture=STRUCTURE) @instance def stimulus(): if nrsamples: vals = [long(random()*(2**width)) for i in range(nrsamples)] else: vals = range(2**width) for i in vals: A.next = intbv(i) yield delay(10) self.assertEqual(ZS, ZB) return (beh, str, stimulus) def testLeadZeroDetSmallSlow(self): Simulation(self.bench(width=8, speed=SLOW)).run() def testLeadZeroDetLargeSlow(self): Simulation(self.bench(width=39, speed=SLOW, nrsamples=16)).run() def testLeadZeroDetSmallFast(self): Simulation(self.bench(width=8, speed=FAST)).run() def testLeadZeroDetLargeFast(self): Simulation(self.bench(width=39, speed=FAST, nrsamples=16)).run() if __name__ == "__main__": unittest.main() myhdl-0.11/example/cookbook/000077500000000000000000000000001347432460400160205ustar00rootroot00000000000000myhdl-0.11/example/cookbook/README.txt000066400000000000000000000002401347432460400175120ustar00rootroot00000000000000This directory contains the code for the examples from the MyHDL Cookbook. The Cookbook itself is here: http://myhdl.jandecaluwe.com/doku.php/cookbook:intro myhdl-0.11/example/cookbook/bitonic/000077500000000000000000000000001347432460400174475ustar00rootroot00000000000000myhdl-0.11/example/cookbook/bitonic/Array8Sorter.v000066400000000000000000000470271347432460400222150ustar00rootroot00000000000000// File: Array8Sorter.v // Generated by MyHDL 1.0dev // Date: Sun May 15 11:40:06 2016 `timescale 1ns/10ps module Array8Sorter ( a0, a1, a2, a3, a4, a5, a6, a7, z0, z1, z2, z3, z4, z5, z6, z7 ); input [3:0] a0; input [3:0] a1; input [3:0] a2; input [3:0] a3; input [3:0] a4; input [3:0] a5; input [3:0] a6; input [3:0] a7; output [3:0] z0; wire [3:0] z0; output [3:0] z1; wire [3:0] z1; output [3:0] z2; wire [3:0] z2; output [3:0] z3; wire [3:0] z3; output [3:0] z4; wire [3:0] z4; output [3:0] z5; wire [3:0] z5; output [3:0] z6; wire [3:0] z6; output [3:0] z7; wire [3:0] z7; wire [3:0] sort_losort_losort_losort_feedthru_32_z; wire [3:0] sort_losort_losort_hisort_feedthru_33_z; reg [3:0] sort_losort_losort_merge_comp_24_z1; reg [3:0] sort_losort_losort_merge_comp_24_z2; wire [3:0] sort_losort_losort_merge_lomerge_feedthru_34_z; wire [3:0] sort_losort_losort_merge_hiMerge_feedthru_35_z; wire [3:0] sort_losort_hisort_losort_feedthru_36_z; wire [3:0] sort_losort_hisort_hisort_feedthru_37_z; reg [3:0] sort_losort_hisort_merge_comp_25_z1; reg [3:0] sort_losort_hisort_merge_comp_25_z2; wire [3:0] sort_losort_hisort_merge_lomerge_feedthru_38_z; wire [3:0] sort_losort_hisort_merge_hiMerge_feedthru_39_z; reg [3:0] sort_losort_merge_comp_26_z1; reg [3:0] sort_losort_merge_comp_26_z2; reg [3:0] sort_losort_merge_comp_27_z1; reg [3:0] sort_losort_merge_comp_27_z2; reg [3:0] sort_losort_merge_lomerge_comp_28_z1; reg [3:0] sort_losort_merge_lomerge_comp_28_z2; wire [3:0] sort_losort_merge_lomerge_lomerge_feedthru_40_z; wire [3:0] sort_losort_merge_lomerge_hiMerge_feedthru_41_z; reg [3:0] sort_losort_merge_hiMerge_comp_29_z1; reg [3:0] sort_losort_merge_hiMerge_comp_29_z2; wire [3:0] sort_losort_merge_hiMerge_lomerge_feedthru_42_z; wire [3:0] sort_losort_merge_hiMerge_hiMerge_feedthru_43_z; wire [3:0] sort_hisort_losort_losort_feedthru_44_z; wire [3:0] sort_hisort_losort_hisort_feedthru_45_z; reg [3:0] sort_hisort_losort_merge_comp_30_z1; reg [3:0] sort_hisort_losort_merge_comp_30_z2; wire [3:0] sort_hisort_losort_merge_lomerge_feedthru_46_z; wire [3:0] sort_hisort_losort_merge_hiMerge_feedthru_47_z; wire [3:0] sort_hisort_hisort_losort_feedthru_48_z; wire [3:0] sort_hisort_hisort_hisort_feedthru_49_z; reg [3:0] sort_hisort_hisort_merge_comp_31_z1; reg [3:0] sort_hisort_hisort_merge_comp_31_z2; wire [3:0] sort_hisort_hisort_merge_lomerge_feedthru_50_z; wire [3:0] sort_hisort_hisort_merge_hiMerge_feedthru_51_z; reg [3:0] sort_hisort_merge_comp_32_z1; reg [3:0] sort_hisort_merge_comp_32_z2; reg [3:0] sort_hisort_merge_comp_33_z1; reg [3:0] sort_hisort_merge_comp_33_z2; reg [3:0] sort_hisort_merge_lomerge_comp_34_z1; reg [3:0] sort_hisort_merge_lomerge_comp_34_z2; wire [3:0] sort_hisort_merge_lomerge_lomerge_feedthru_52_z; wire [3:0] sort_hisort_merge_lomerge_hiMerge_feedthru_53_z; reg [3:0] sort_hisort_merge_hiMerge_comp_35_z1; reg [3:0] sort_hisort_merge_hiMerge_comp_35_z2; wire [3:0] sort_hisort_merge_hiMerge_lomerge_feedthru_54_z; wire [3:0] sort_hisort_merge_hiMerge_hiMerge_feedthru_55_z; reg [3:0] sort_merge_comp_36_z1; reg [3:0] sort_merge_comp_36_z2; reg [3:0] sort_merge_comp_37_z1; reg [3:0] sort_merge_comp_37_z2; reg [3:0] sort_merge_comp_38_z1; reg [3:0] sort_merge_comp_38_z2; reg [3:0] sort_merge_comp_39_z1; reg [3:0] sort_merge_comp_39_z2; reg [3:0] sort_merge_lomerge_comp_40_z1; reg [3:0] sort_merge_lomerge_comp_40_z2; reg [3:0] sort_merge_lomerge_comp_41_z1; reg [3:0] sort_merge_lomerge_comp_41_z2; reg [3:0] sort_merge_lomerge_lomerge_comp_42_z1; reg [3:0] sort_merge_lomerge_lomerge_comp_42_z2; reg [3:0] sort_merge_lomerge_hiMerge_comp_43_z1; reg [3:0] sort_merge_lomerge_hiMerge_comp_43_z2; reg [3:0] sort_merge_hiMerge_comp_44_z1; reg [3:0] sort_merge_hiMerge_comp_44_z2; reg [3:0] sort_merge_hiMerge_comp_45_z1; reg [3:0] sort_merge_hiMerge_comp_45_z2; reg [3:0] sort_merge_hiMerge_lomerge_comp_46_z1; reg [3:0] sort_merge_hiMerge_lomerge_comp_46_z2; reg [3:0] sort_merge_hiMerge_hiMerge_comp_47_z1; reg [3:0] sort_merge_hiMerge_hiMerge_comp_47_z2; assign sort_losort_losort_losort_feedthru_32_z = a0; assign sort_losort_losort_hisort_feedthru_33_z = a1; always @(sort_losort_losort_losort_feedthru_32_z, sort_losort_losort_hisort_feedthru_33_z) begin: ARRAY8SORTER_SORT_LOSORT_LOSORT_MERGE_COMP_24_LOGIC sort_losort_losort_merge_comp_24_z1 = sort_losort_losort_losort_feedthru_32_z; sort_losort_losort_merge_comp_24_z2 = sort_losort_losort_hisort_feedthru_33_z; if ((1'b1 == (sort_losort_losort_losort_feedthru_32_z > sort_losort_losort_hisort_feedthru_33_z))) begin sort_losort_losort_merge_comp_24_z1 = sort_losort_losort_hisort_feedthru_33_z; sort_losort_losort_merge_comp_24_z2 = sort_losort_losort_losort_feedthru_32_z; end end assign sort_losort_losort_merge_lomerge_feedthru_34_z = sort_losort_losort_merge_comp_24_z1; assign sort_losort_losort_merge_hiMerge_feedthru_35_z = sort_losort_losort_merge_comp_24_z2; assign sort_losort_hisort_losort_feedthru_36_z = a2; assign sort_losort_hisort_hisort_feedthru_37_z = a3; always @(sort_losort_hisort_losort_feedthru_36_z, sort_losort_hisort_hisort_feedthru_37_z) begin: ARRAY8SORTER_SORT_LOSORT_HISORT_MERGE_COMP_25_LOGIC sort_losort_hisort_merge_comp_25_z1 = sort_losort_hisort_losort_feedthru_36_z; sort_losort_hisort_merge_comp_25_z2 = sort_losort_hisort_hisort_feedthru_37_z; if ((1'b0 == (sort_losort_hisort_losort_feedthru_36_z > sort_losort_hisort_hisort_feedthru_37_z))) begin sort_losort_hisort_merge_comp_25_z1 = sort_losort_hisort_hisort_feedthru_37_z; sort_losort_hisort_merge_comp_25_z2 = sort_losort_hisort_losort_feedthru_36_z; end end assign sort_losort_hisort_merge_lomerge_feedthru_38_z = sort_losort_hisort_merge_comp_25_z1; assign sort_losort_hisort_merge_hiMerge_feedthru_39_z = sort_losort_hisort_merge_comp_25_z2; always @(sort_losort_losort_merge_lomerge_feedthru_34_z, sort_losort_hisort_merge_lomerge_feedthru_38_z) begin: ARRAY8SORTER_SORT_LOSORT_MERGE_COMP_26_LOGIC sort_losort_merge_comp_26_z1 = sort_losort_losort_merge_lomerge_feedthru_34_z; sort_losort_merge_comp_26_z2 = sort_losort_hisort_merge_lomerge_feedthru_38_z; if ((1'b1 == (sort_losort_losort_merge_lomerge_feedthru_34_z > sort_losort_hisort_merge_lomerge_feedthru_38_z))) begin sort_losort_merge_comp_26_z1 = sort_losort_hisort_merge_lomerge_feedthru_38_z; sort_losort_merge_comp_26_z2 = sort_losort_losort_merge_lomerge_feedthru_34_z; end end always @(sort_losort_losort_merge_hiMerge_feedthru_35_z, sort_losort_hisort_merge_hiMerge_feedthru_39_z) begin: ARRAY8SORTER_SORT_LOSORT_MERGE_COMP_27_LOGIC sort_losort_merge_comp_27_z1 = sort_losort_losort_merge_hiMerge_feedthru_35_z; sort_losort_merge_comp_27_z2 = sort_losort_hisort_merge_hiMerge_feedthru_39_z; if ((1'b1 == (sort_losort_losort_merge_hiMerge_feedthru_35_z > sort_losort_hisort_merge_hiMerge_feedthru_39_z))) begin sort_losort_merge_comp_27_z1 = sort_losort_hisort_merge_hiMerge_feedthru_39_z; sort_losort_merge_comp_27_z2 = sort_losort_losort_merge_hiMerge_feedthru_35_z; end end always @(sort_losort_merge_comp_26_z1, sort_losort_merge_comp_27_z1) begin: ARRAY8SORTER_SORT_LOSORT_MERGE_LOMERGE_COMP_28_LOGIC sort_losort_merge_lomerge_comp_28_z1 = sort_losort_merge_comp_26_z1; sort_losort_merge_lomerge_comp_28_z2 = sort_losort_merge_comp_27_z1; if ((1'b1 == (sort_losort_merge_comp_26_z1 > sort_losort_merge_comp_27_z1))) begin sort_losort_merge_lomerge_comp_28_z1 = sort_losort_merge_comp_27_z1; sort_losort_merge_lomerge_comp_28_z2 = sort_losort_merge_comp_26_z1; end end assign sort_losort_merge_lomerge_lomerge_feedthru_40_z = sort_losort_merge_lomerge_comp_28_z1; assign sort_losort_merge_lomerge_hiMerge_feedthru_41_z = sort_losort_merge_lomerge_comp_28_z2; always @(sort_losort_merge_comp_26_z2, sort_losort_merge_comp_27_z2) begin: ARRAY8SORTER_SORT_LOSORT_MERGE_HIMERGE_COMP_29_LOGIC sort_losort_merge_hiMerge_comp_29_z1 = sort_losort_merge_comp_26_z2; sort_losort_merge_hiMerge_comp_29_z2 = sort_losort_merge_comp_27_z2; if ((1'b1 == (sort_losort_merge_comp_26_z2 > sort_losort_merge_comp_27_z2))) begin sort_losort_merge_hiMerge_comp_29_z1 = sort_losort_merge_comp_27_z2; sort_losort_merge_hiMerge_comp_29_z2 = sort_losort_merge_comp_26_z2; end end assign sort_losort_merge_hiMerge_lomerge_feedthru_42_z = sort_losort_merge_hiMerge_comp_29_z1; assign sort_losort_merge_hiMerge_hiMerge_feedthru_43_z = sort_losort_merge_hiMerge_comp_29_z2; assign sort_hisort_losort_losort_feedthru_44_z = a4; assign sort_hisort_losort_hisort_feedthru_45_z = a5; always @(sort_hisort_losort_losort_feedthru_44_z, sort_hisort_losort_hisort_feedthru_45_z) begin: ARRAY8SORTER_SORT_HISORT_LOSORT_MERGE_COMP_30_LOGIC sort_hisort_losort_merge_comp_30_z1 = sort_hisort_losort_losort_feedthru_44_z; sort_hisort_losort_merge_comp_30_z2 = sort_hisort_losort_hisort_feedthru_45_z; if ((1'b1 == (sort_hisort_losort_losort_feedthru_44_z > sort_hisort_losort_hisort_feedthru_45_z))) begin sort_hisort_losort_merge_comp_30_z1 = sort_hisort_losort_hisort_feedthru_45_z; sort_hisort_losort_merge_comp_30_z2 = sort_hisort_losort_losort_feedthru_44_z; end end assign sort_hisort_losort_merge_lomerge_feedthru_46_z = sort_hisort_losort_merge_comp_30_z1; assign sort_hisort_losort_merge_hiMerge_feedthru_47_z = sort_hisort_losort_merge_comp_30_z2; assign sort_hisort_hisort_losort_feedthru_48_z = a6; assign sort_hisort_hisort_hisort_feedthru_49_z = a7; always @(sort_hisort_hisort_losort_feedthru_48_z, sort_hisort_hisort_hisort_feedthru_49_z) begin: ARRAY8SORTER_SORT_HISORT_HISORT_MERGE_COMP_31_LOGIC sort_hisort_hisort_merge_comp_31_z1 = sort_hisort_hisort_losort_feedthru_48_z; sort_hisort_hisort_merge_comp_31_z2 = sort_hisort_hisort_hisort_feedthru_49_z; if ((1'b0 == (sort_hisort_hisort_losort_feedthru_48_z > sort_hisort_hisort_hisort_feedthru_49_z))) begin sort_hisort_hisort_merge_comp_31_z1 = sort_hisort_hisort_hisort_feedthru_49_z; sort_hisort_hisort_merge_comp_31_z2 = sort_hisort_hisort_losort_feedthru_48_z; end end assign sort_hisort_hisort_merge_lomerge_feedthru_50_z = sort_hisort_hisort_merge_comp_31_z1; assign sort_hisort_hisort_merge_hiMerge_feedthru_51_z = sort_hisort_hisort_merge_comp_31_z2; always @(sort_hisort_losort_merge_lomerge_feedthru_46_z, sort_hisort_hisort_merge_lomerge_feedthru_50_z) begin: ARRAY8SORTER_SORT_HISORT_MERGE_COMP_32_LOGIC sort_hisort_merge_comp_32_z1 = sort_hisort_losort_merge_lomerge_feedthru_46_z; sort_hisort_merge_comp_32_z2 = sort_hisort_hisort_merge_lomerge_feedthru_50_z; if ((1'b0 == (sort_hisort_losort_merge_lomerge_feedthru_46_z > sort_hisort_hisort_merge_lomerge_feedthru_50_z))) begin sort_hisort_merge_comp_32_z1 = sort_hisort_hisort_merge_lomerge_feedthru_50_z; sort_hisort_merge_comp_32_z2 = sort_hisort_losort_merge_lomerge_feedthru_46_z; end end always @(sort_hisort_losort_merge_hiMerge_feedthru_47_z, sort_hisort_hisort_merge_hiMerge_feedthru_51_z) begin: ARRAY8SORTER_SORT_HISORT_MERGE_COMP_33_LOGIC sort_hisort_merge_comp_33_z1 = sort_hisort_losort_merge_hiMerge_feedthru_47_z; sort_hisort_merge_comp_33_z2 = sort_hisort_hisort_merge_hiMerge_feedthru_51_z; if ((1'b0 == (sort_hisort_losort_merge_hiMerge_feedthru_47_z > sort_hisort_hisort_merge_hiMerge_feedthru_51_z))) begin sort_hisort_merge_comp_33_z1 = sort_hisort_hisort_merge_hiMerge_feedthru_51_z; sort_hisort_merge_comp_33_z2 = sort_hisort_losort_merge_hiMerge_feedthru_47_z; end end always @(sort_hisort_merge_comp_32_z1, sort_hisort_merge_comp_33_z1) begin: ARRAY8SORTER_SORT_HISORT_MERGE_LOMERGE_COMP_34_LOGIC sort_hisort_merge_lomerge_comp_34_z1 = sort_hisort_merge_comp_32_z1; sort_hisort_merge_lomerge_comp_34_z2 = sort_hisort_merge_comp_33_z1; if ((1'b0 == (sort_hisort_merge_comp_32_z1 > sort_hisort_merge_comp_33_z1))) begin sort_hisort_merge_lomerge_comp_34_z1 = sort_hisort_merge_comp_33_z1; sort_hisort_merge_lomerge_comp_34_z2 = sort_hisort_merge_comp_32_z1; end end assign sort_hisort_merge_lomerge_lomerge_feedthru_52_z = sort_hisort_merge_lomerge_comp_34_z1; assign sort_hisort_merge_lomerge_hiMerge_feedthru_53_z = sort_hisort_merge_lomerge_comp_34_z2; always @(sort_hisort_merge_comp_32_z2, sort_hisort_merge_comp_33_z2) begin: ARRAY8SORTER_SORT_HISORT_MERGE_HIMERGE_COMP_35_LOGIC sort_hisort_merge_hiMerge_comp_35_z1 = sort_hisort_merge_comp_32_z2; sort_hisort_merge_hiMerge_comp_35_z2 = sort_hisort_merge_comp_33_z2; if ((1'b0 == (sort_hisort_merge_comp_32_z2 > sort_hisort_merge_comp_33_z2))) begin sort_hisort_merge_hiMerge_comp_35_z1 = sort_hisort_merge_comp_33_z2; sort_hisort_merge_hiMerge_comp_35_z2 = sort_hisort_merge_comp_32_z2; end end assign sort_hisort_merge_hiMerge_lomerge_feedthru_54_z = sort_hisort_merge_hiMerge_comp_35_z1; assign sort_hisort_merge_hiMerge_hiMerge_feedthru_55_z = sort_hisort_merge_hiMerge_comp_35_z2; always @(sort_losort_merge_lomerge_lomerge_feedthru_40_z, sort_hisort_merge_lomerge_lomerge_feedthru_52_z) begin: ARRAY8SORTER_SORT_MERGE_COMP_36_LOGIC sort_merge_comp_36_z1 = sort_losort_merge_lomerge_lomerge_feedthru_40_z; sort_merge_comp_36_z2 = sort_hisort_merge_lomerge_lomerge_feedthru_52_z; if ((1'b1 == (sort_losort_merge_lomerge_lomerge_feedthru_40_z > sort_hisort_merge_lomerge_lomerge_feedthru_52_z))) begin sort_merge_comp_36_z1 = sort_hisort_merge_lomerge_lomerge_feedthru_52_z; sort_merge_comp_36_z2 = sort_losort_merge_lomerge_lomerge_feedthru_40_z; end end always @(sort_losort_merge_lomerge_hiMerge_feedthru_41_z, sort_hisort_merge_lomerge_hiMerge_feedthru_53_z) begin: ARRAY8SORTER_SORT_MERGE_COMP_37_LOGIC sort_merge_comp_37_z1 = sort_losort_merge_lomerge_hiMerge_feedthru_41_z; sort_merge_comp_37_z2 = sort_hisort_merge_lomerge_hiMerge_feedthru_53_z; if ((1'b1 == (sort_losort_merge_lomerge_hiMerge_feedthru_41_z > sort_hisort_merge_lomerge_hiMerge_feedthru_53_z))) begin sort_merge_comp_37_z1 = sort_hisort_merge_lomerge_hiMerge_feedthru_53_z; sort_merge_comp_37_z2 = sort_losort_merge_lomerge_hiMerge_feedthru_41_z; end end always @(sort_losort_merge_hiMerge_lomerge_feedthru_42_z, sort_hisort_merge_hiMerge_lomerge_feedthru_54_z) begin: ARRAY8SORTER_SORT_MERGE_COMP_38_LOGIC sort_merge_comp_38_z1 = sort_losort_merge_hiMerge_lomerge_feedthru_42_z; sort_merge_comp_38_z2 = sort_hisort_merge_hiMerge_lomerge_feedthru_54_z; if ((1'b1 == (sort_losort_merge_hiMerge_lomerge_feedthru_42_z > sort_hisort_merge_hiMerge_lomerge_feedthru_54_z))) begin sort_merge_comp_38_z1 = sort_hisort_merge_hiMerge_lomerge_feedthru_54_z; sort_merge_comp_38_z2 = sort_losort_merge_hiMerge_lomerge_feedthru_42_z; end end always @(sort_losort_merge_hiMerge_hiMerge_feedthru_43_z, sort_hisort_merge_hiMerge_hiMerge_feedthru_55_z) begin: ARRAY8SORTER_SORT_MERGE_COMP_39_LOGIC sort_merge_comp_39_z1 = sort_losort_merge_hiMerge_hiMerge_feedthru_43_z; sort_merge_comp_39_z2 = sort_hisort_merge_hiMerge_hiMerge_feedthru_55_z; if ((1'b1 == (sort_losort_merge_hiMerge_hiMerge_feedthru_43_z > sort_hisort_merge_hiMerge_hiMerge_feedthru_55_z))) begin sort_merge_comp_39_z1 = sort_hisort_merge_hiMerge_hiMerge_feedthru_55_z; sort_merge_comp_39_z2 = sort_losort_merge_hiMerge_hiMerge_feedthru_43_z; end end always @(sort_merge_comp_36_z1, sort_merge_comp_38_z1) begin: ARRAY8SORTER_SORT_MERGE_LOMERGE_COMP_40_LOGIC sort_merge_lomerge_comp_40_z1 = sort_merge_comp_36_z1; sort_merge_lomerge_comp_40_z2 = sort_merge_comp_38_z1; if ((1'b1 == (sort_merge_comp_36_z1 > sort_merge_comp_38_z1))) begin sort_merge_lomerge_comp_40_z1 = sort_merge_comp_38_z1; sort_merge_lomerge_comp_40_z2 = sort_merge_comp_36_z1; end end always @(sort_merge_comp_37_z1, sort_merge_comp_39_z1) begin: ARRAY8SORTER_SORT_MERGE_LOMERGE_COMP_41_LOGIC sort_merge_lomerge_comp_41_z1 = sort_merge_comp_37_z1; sort_merge_lomerge_comp_41_z2 = sort_merge_comp_39_z1; if ((1'b1 == (sort_merge_comp_37_z1 > sort_merge_comp_39_z1))) begin sort_merge_lomerge_comp_41_z1 = sort_merge_comp_39_z1; sort_merge_lomerge_comp_41_z2 = sort_merge_comp_37_z1; end end always @(sort_merge_lomerge_comp_40_z1, sort_merge_lomerge_comp_41_z1) begin: ARRAY8SORTER_SORT_MERGE_LOMERGE_LOMERGE_COMP_42_LOGIC sort_merge_lomerge_lomerge_comp_42_z1 = sort_merge_lomerge_comp_40_z1; sort_merge_lomerge_lomerge_comp_42_z2 = sort_merge_lomerge_comp_41_z1; if ((1'b1 == (sort_merge_lomerge_comp_40_z1 > sort_merge_lomerge_comp_41_z1))) begin sort_merge_lomerge_lomerge_comp_42_z1 = sort_merge_lomerge_comp_41_z1; sort_merge_lomerge_lomerge_comp_42_z2 = sort_merge_lomerge_comp_40_z1; end end assign z0 = sort_merge_lomerge_lomerge_comp_42_z1; assign z1 = sort_merge_lomerge_lomerge_comp_42_z2; always @(sort_merge_lomerge_comp_40_z2, sort_merge_lomerge_comp_41_z2) begin: ARRAY8SORTER_SORT_MERGE_LOMERGE_HIMERGE_COMP_43_LOGIC sort_merge_lomerge_hiMerge_comp_43_z1 = sort_merge_lomerge_comp_40_z2; sort_merge_lomerge_hiMerge_comp_43_z2 = sort_merge_lomerge_comp_41_z2; if ((1'b1 == (sort_merge_lomerge_comp_40_z2 > sort_merge_lomerge_comp_41_z2))) begin sort_merge_lomerge_hiMerge_comp_43_z1 = sort_merge_lomerge_comp_41_z2; sort_merge_lomerge_hiMerge_comp_43_z2 = sort_merge_lomerge_comp_40_z2; end end assign z2 = sort_merge_lomerge_hiMerge_comp_43_z1; assign z3 = sort_merge_lomerge_hiMerge_comp_43_z2; always @(sort_merge_comp_36_z2, sort_merge_comp_38_z2) begin: ARRAY8SORTER_SORT_MERGE_HIMERGE_COMP_44_LOGIC sort_merge_hiMerge_comp_44_z1 = sort_merge_comp_36_z2; sort_merge_hiMerge_comp_44_z2 = sort_merge_comp_38_z2; if ((1'b1 == (sort_merge_comp_36_z2 > sort_merge_comp_38_z2))) begin sort_merge_hiMerge_comp_44_z1 = sort_merge_comp_38_z2; sort_merge_hiMerge_comp_44_z2 = sort_merge_comp_36_z2; end end always @(sort_merge_comp_37_z2, sort_merge_comp_39_z2) begin: ARRAY8SORTER_SORT_MERGE_HIMERGE_COMP_45_LOGIC sort_merge_hiMerge_comp_45_z1 = sort_merge_comp_37_z2; sort_merge_hiMerge_comp_45_z2 = sort_merge_comp_39_z2; if ((1'b1 == (sort_merge_comp_37_z2 > sort_merge_comp_39_z2))) begin sort_merge_hiMerge_comp_45_z1 = sort_merge_comp_39_z2; sort_merge_hiMerge_comp_45_z2 = sort_merge_comp_37_z2; end end always @(sort_merge_hiMerge_comp_44_z1, sort_merge_hiMerge_comp_45_z1) begin: ARRAY8SORTER_SORT_MERGE_HIMERGE_LOMERGE_COMP_46_LOGIC sort_merge_hiMerge_lomerge_comp_46_z1 = sort_merge_hiMerge_comp_44_z1; sort_merge_hiMerge_lomerge_comp_46_z2 = sort_merge_hiMerge_comp_45_z1; if ((1'b1 == (sort_merge_hiMerge_comp_44_z1 > sort_merge_hiMerge_comp_45_z1))) begin sort_merge_hiMerge_lomerge_comp_46_z1 = sort_merge_hiMerge_comp_45_z1; sort_merge_hiMerge_lomerge_comp_46_z2 = sort_merge_hiMerge_comp_44_z1; end end assign z4 = sort_merge_hiMerge_lomerge_comp_46_z1; assign z5 = sort_merge_hiMerge_lomerge_comp_46_z2; always @(sort_merge_hiMerge_comp_44_z2, sort_merge_hiMerge_comp_45_z2) begin: ARRAY8SORTER_SORT_MERGE_HIMERGE_HIMERGE_COMP_47_LOGIC sort_merge_hiMerge_hiMerge_comp_47_z1 = sort_merge_hiMerge_comp_44_z2; sort_merge_hiMerge_hiMerge_comp_47_z2 = sort_merge_hiMerge_comp_45_z2; if ((1'b1 == (sort_merge_hiMerge_comp_44_z2 > sort_merge_hiMerge_comp_45_z2))) begin sort_merge_hiMerge_hiMerge_comp_47_z1 = sort_merge_hiMerge_comp_45_z2; sort_merge_hiMerge_hiMerge_comp_47_z2 = sort_merge_hiMerge_comp_44_z2; end end assign z6 = sort_merge_hiMerge_hiMerge_comp_47_z1; assign z7 = sort_merge_hiMerge_hiMerge_comp_47_z2; endmodule myhdl-0.11/example/cookbook/bitonic/bitonic.py000066400000000000000000000045221347432460400214530ustar00rootroot00000000000000import subprocess import myhdl from myhdl import * from myhdl.conversion import analyze DESCENDING, ASCENDING = False, True @block def comp(a1, a2, z1, z2, dir): @always_comb def logic(): z1.next = a1 z2.next = a2 if dir == (a1 > a2): z1.next = a2 z2.next = a1 return logic @block def feedthru(a, z): @always_comb def logic(): z.next = a return logic @block def bitonicMerge(a, z, dir): n = len(a) k = n//2 w = len(a[0]) if n > 1: t = [Signal(intbv(0)[w:]) for i in range(n)] comps = [comp(a[i], a[i+k], t[i], t[i+k], dir) for i in range(k)] lomerge = bitonicMerge(t[:k], z[:k], dir) himerge = bitonicMerge(t[k:], z[k:], dir) lomerge.name = "lomerge" himerge.name = "hiMerge" return comps, lomerge, himerge else: return feedthru(a[0], z[0]) @block def bitonicSort(a, z, dir): n = len(a) k = n//2 w = len(a[0]) if n > 1: t = [Signal(intbv(0)[w:]) for i in range(n)] losort = bitonicSort(a[:k], t[:k], ASCENDING) hisort = bitonicSort(a[k:], t[k:], DESCENDING) merge = bitonicMerge(t, z, dir) losort.name = "losort" hisort.name = "hisort" merge.name = "merge" return losort, hisort, merge else: return feedthru(a[0], z[0]) @block def Array8Sorter(a0, a1, a2, a3, a4, a5, a6, a7, z0, z1, z2, z3, z4, z5, z6, z7): a = [a0, a1, a2, a3, a4, a5, a6, a7] z = [z0, z1, z2, z3, z4, z5, z6, z7] sort = bitonicSort(a, z, ASCENDING) sort.name = "sort" return sort def Array8Sorter_v(a0, a1, a2, a3, a4, a5, a6, a7, z0, z1, z2, z3, z4, z5, z6, z7): analyze.simulator = 'iverilog' toVerilog(Array8Sorter(a0, a1, a2, a3, a4, a5, a6, a7, z0, z1, z2, z3, z4, z5, z6, z7)) analyze(Array8Sorter(a0, a1, a2, a3, a4, a5, a6, a7, z0, z1, z2, z3, z4, z5, z6, z7)) # cmd = "cver -q +loadvpi=../../../cosimulation/cver/myhdl_vpi:vpi_compat_bootstrap " + \ # "Array8Sorter.v tb_Array8Sorter.v" subprocess.call("iverilog -o Array8Sorter.o Array8Sorter.v tb_Array8Sorter.v", shell=True) cmd = "vvp -m ../../../cosimulation/icarus/myhdl.vpi Array8Sorter.o" return Cosimulation(cmd, **locals()) myhdl-0.11/example/cookbook/bitonic/ori.v000066400000000000000000000470271347432460400204410ustar00rootroot00000000000000// File: Array8Sorter.v // Generated by MyHDL 1.0dev // Date: Sat Mar 19 15:40:10 2016 `timescale 1ns/10ps module Array8Sorter ( a0, a1, a2, a3, a4, a5, a6, a7, z0, z1, z2, z3, z4, z5, z6, z7 ); input [3:0] a0; input [3:0] a1; input [3:0] a2; input [3:0] a3; input [3:0] a4; input [3:0] a5; input [3:0] a6; input [3:0] a7; output [3:0] z0; wire [3:0] z0; output [3:0] z1; wire [3:0] z1; output [3:0] z2; wire [3:0] z2; output [3:0] z3; wire [3:0] z3; output [3:0] z4; wire [3:0] z4; output [3:0] z5; wire [3:0] z5; output [3:0] z6; wire [3:0] z6; output [3:0] z7; wire [3:0] z7; wire [3:0] sort_losort_losort_losort_feedthru_32_z; wire [3:0] sort_losort_losort_hisort_feedthru_33_z; reg [3:0] sort_losort_losort_merge_comp_24_z1; reg [3:0] sort_losort_losort_merge_comp_24_z2; wire [3:0] sort_losort_losort_merge_lomerge_feedthru_34_z; wire [3:0] sort_losort_losort_merge_hiMerge_feedthru_35_z; wire [3:0] sort_losort_hisort_losort_feedthru_36_z; wire [3:0] sort_losort_hisort_hisort_feedthru_37_z; reg [3:0] sort_losort_hisort_merge_comp_25_z1; reg [3:0] sort_losort_hisort_merge_comp_25_z2; wire [3:0] sort_losort_hisort_merge_lomerge_feedthru_38_z; wire [3:0] sort_losort_hisort_merge_hiMerge_feedthru_39_z; reg [3:0] sort_losort_merge_comp_26_z1; reg [3:0] sort_losort_merge_comp_26_z2; reg [3:0] sort_losort_merge_comp_27_z1; reg [3:0] sort_losort_merge_comp_27_z2; reg [3:0] sort_losort_merge_lomerge_comp_28_z1; reg [3:0] sort_losort_merge_lomerge_comp_28_z2; wire [3:0] sort_losort_merge_lomerge_lomerge_feedthru_40_z; wire [3:0] sort_losort_merge_lomerge_hiMerge_feedthru_41_z; reg [3:0] sort_losort_merge_hiMerge_comp_29_z1; reg [3:0] sort_losort_merge_hiMerge_comp_29_z2; wire [3:0] sort_losort_merge_hiMerge_lomerge_feedthru_42_z; wire [3:0] sort_losort_merge_hiMerge_hiMerge_feedthru_43_z; wire [3:0] sort_hisort_losort_losort_feedthru_44_z; wire [3:0] sort_hisort_losort_hisort_feedthru_45_z; reg [3:0] sort_hisort_losort_merge_comp_30_z1; reg [3:0] sort_hisort_losort_merge_comp_30_z2; wire [3:0] sort_hisort_losort_merge_lomerge_feedthru_46_z; wire [3:0] sort_hisort_losort_merge_hiMerge_feedthru_47_z; wire [3:0] sort_hisort_hisort_losort_feedthru_48_z; wire [3:0] sort_hisort_hisort_hisort_feedthru_49_z; reg [3:0] sort_hisort_hisort_merge_comp_31_z1; reg [3:0] sort_hisort_hisort_merge_comp_31_z2; wire [3:0] sort_hisort_hisort_merge_lomerge_feedthru_50_z; wire [3:0] sort_hisort_hisort_merge_hiMerge_feedthru_51_z; reg [3:0] sort_hisort_merge_comp_32_z1; reg [3:0] sort_hisort_merge_comp_32_z2; reg [3:0] sort_hisort_merge_comp_33_z1; reg [3:0] sort_hisort_merge_comp_33_z2; reg [3:0] sort_hisort_merge_lomerge_comp_34_z1; reg [3:0] sort_hisort_merge_lomerge_comp_34_z2; wire [3:0] sort_hisort_merge_lomerge_lomerge_feedthru_52_z; wire [3:0] sort_hisort_merge_lomerge_hiMerge_feedthru_53_z; reg [3:0] sort_hisort_merge_hiMerge_comp_35_z1; reg [3:0] sort_hisort_merge_hiMerge_comp_35_z2; wire [3:0] sort_hisort_merge_hiMerge_lomerge_feedthru_54_z; wire [3:0] sort_hisort_merge_hiMerge_hiMerge_feedthru_55_z; reg [3:0] sort_merge_comp_36_z1; reg [3:0] sort_merge_comp_36_z2; reg [3:0] sort_merge_comp_37_z1; reg [3:0] sort_merge_comp_37_z2; reg [3:0] sort_merge_comp_38_z1; reg [3:0] sort_merge_comp_38_z2; reg [3:0] sort_merge_comp_39_z1; reg [3:0] sort_merge_comp_39_z2; reg [3:0] sort_merge_lomerge_comp_40_z1; reg [3:0] sort_merge_lomerge_comp_40_z2; reg [3:0] sort_merge_lomerge_comp_41_z1; reg [3:0] sort_merge_lomerge_comp_41_z2; reg [3:0] sort_merge_lomerge_lomerge_comp_42_z1; reg [3:0] sort_merge_lomerge_lomerge_comp_42_z2; reg [3:0] sort_merge_lomerge_hiMerge_comp_43_z1; reg [3:0] sort_merge_lomerge_hiMerge_comp_43_z2; reg [3:0] sort_merge_hiMerge_comp_44_z1; reg [3:0] sort_merge_hiMerge_comp_44_z2; reg [3:0] sort_merge_hiMerge_comp_45_z1; reg [3:0] sort_merge_hiMerge_comp_45_z2; reg [3:0] sort_merge_hiMerge_lomerge_comp_46_z1; reg [3:0] sort_merge_hiMerge_lomerge_comp_46_z2; reg [3:0] sort_merge_hiMerge_hiMerge_comp_47_z1; reg [3:0] sort_merge_hiMerge_hiMerge_comp_47_z2; assign sort_losort_losort_losort_feedthru_32_z = a0; assign sort_losort_losort_hisort_feedthru_33_z = a1; always @(sort_losort_losort_losort_feedthru_32_z, sort_losort_losort_hisort_feedthru_33_z) begin: ARRAY8SORTER_SORT_LOSORT_LOSORT_MERGE_COMP_24_LOGIC sort_losort_losort_merge_comp_24_z1 = sort_losort_losort_losort_feedthru_32_z; sort_losort_losort_merge_comp_24_z2 = sort_losort_losort_hisort_feedthru_33_z; if ((1'b1 == (sort_losort_losort_losort_feedthru_32_z > sort_losort_losort_hisort_feedthru_33_z))) begin sort_losort_losort_merge_comp_24_z1 = sort_losort_losort_hisort_feedthru_33_z; sort_losort_losort_merge_comp_24_z2 = sort_losort_losort_losort_feedthru_32_z; end end assign sort_losort_losort_merge_lomerge_feedthru_34_z = sort_losort_losort_merge_comp_24_z1; assign sort_losort_losort_merge_hiMerge_feedthru_35_z = sort_losort_losort_merge_comp_24_z2; assign sort_losort_hisort_losort_feedthru_36_z = a2; assign sort_losort_hisort_hisort_feedthru_37_z = a3; always @(sort_losort_hisort_losort_feedthru_36_z, sort_losort_hisort_hisort_feedthru_37_z) begin: ARRAY8SORTER_SORT_LOSORT_HISORT_MERGE_COMP_25_LOGIC sort_losort_hisort_merge_comp_25_z1 = sort_losort_hisort_losort_feedthru_36_z; sort_losort_hisort_merge_comp_25_z2 = sort_losort_hisort_hisort_feedthru_37_z; if ((1'b0 == (sort_losort_hisort_losort_feedthru_36_z > sort_losort_hisort_hisort_feedthru_37_z))) begin sort_losort_hisort_merge_comp_25_z1 = sort_losort_hisort_hisort_feedthru_37_z; sort_losort_hisort_merge_comp_25_z2 = sort_losort_hisort_losort_feedthru_36_z; end end assign sort_losort_hisort_merge_lomerge_feedthru_38_z = sort_losort_hisort_merge_comp_25_z1; assign sort_losort_hisort_merge_hiMerge_feedthru_39_z = sort_losort_hisort_merge_comp_25_z2; always @(sort_losort_losort_merge_lomerge_feedthru_34_z, sort_losort_hisort_merge_lomerge_feedthru_38_z) begin: ARRAY8SORTER_SORT_LOSORT_MERGE_COMP_26_LOGIC sort_losort_merge_comp_26_z1 = sort_losort_losort_merge_lomerge_feedthru_34_z; sort_losort_merge_comp_26_z2 = sort_losort_hisort_merge_lomerge_feedthru_38_z; if ((1'b1 == (sort_losort_losort_merge_lomerge_feedthru_34_z > sort_losort_hisort_merge_lomerge_feedthru_38_z))) begin sort_losort_merge_comp_26_z1 = sort_losort_hisort_merge_lomerge_feedthru_38_z; sort_losort_merge_comp_26_z2 = sort_losort_losort_merge_lomerge_feedthru_34_z; end end always @(sort_losort_losort_merge_hiMerge_feedthru_35_z, sort_losort_hisort_merge_hiMerge_feedthru_39_z) begin: ARRAY8SORTER_SORT_LOSORT_MERGE_COMP_27_LOGIC sort_losort_merge_comp_27_z1 = sort_losort_losort_merge_hiMerge_feedthru_35_z; sort_losort_merge_comp_27_z2 = sort_losort_hisort_merge_hiMerge_feedthru_39_z; if ((1'b1 == (sort_losort_losort_merge_hiMerge_feedthru_35_z > sort_losort_hisort_merge_hiMerge_feedthru_39_z))) begin sort_losort_merge_comp_27_z1 = sort_losort_hisort_merge_hiMerge_feedthru_39_z; sort_losort_merge_comp_27_z2 = sort_losort_losort_merge_hiMerge_feedthru_35_z; end end always @(sort_losort_merge_comp_26_z1, sort_losort_merge_comp_27_z1) begin: ARRAY8SORTER_SORT_LOSORT_MERGE_LOMERGE_COMP_28_LOGIC sort_losort_merge_lomerge_comp_28_z1 = sort_losort_merge_comp_26_z1; sort_losort_merge_lomerge_comp_28_z2 = sort_losort_merge_comp_27_z1; if ((1'b1 == (sort_losort_merge_comp_26_z1 > sort_losort_merge_comp_27_z1))) begin sort_losort_merge_lomerge_comp_28_z1 = sort_losort_merge_comp_27_z1; sort_losort_merge_lomerge_comp_28_z2 = sort_losort_merge_comp_26_z1; end end assign sort_losort_merge_lomerge_lomerge_feedthru_40_z = sort_losort_merge_lomerge_comp_28_z1; assign sort_losort_merge_lomerge_hiMerge_feedthru_41_z = sort_losort_merge_lomerge_comp_28_z2; always @(sort_losort_merge_comp_26_z2, sort_losort_merge_comp_27_z2) begin: ARRAY8SORTER_SORT_LOSORT_MERGE_HIMERGE_COMP_29_LOGIC sort_losort_merge_hiMerge_comp_29_z1 = sort_losort_merge_comp_26_z2; sort_losort_merge_hiMerge_comp_29_z2 = sort_losort_merge_comp_27_z2; if ((1'b1 == (sort_losort_merge_comp_26_z2 > sort_losort_merge_comp_27_z2))) begin sort_losort_merge_hiMerge_comp_29_z1 = sort_losort_merge_comp_27_z2; sort_losort_merge_hiMerge_comp_29_z2 = sort_losort_merge_comp_26_z2; end end assign sort_losort_merge_hiMerge_lomerge_feedthru_42_z = sort_losort_merge_hiMerge_comp_29_z1; assign sort_losort_merge_hiMerge_hiMerge_feedthru_43_z = sort_losort_merge_hiMerge_comp_29_z2; assign sort_hisort_losort_losort_feedthru_44_z = a4; assign sort_hisort_losort_hisort_feedthru_45_z = a5; always @(sort_hisort_losort_losort_feedthru_44_z, sort_hisort_losort_hisort_feedthru_45_z) begin: ARRAY8SORTER_SORT_HISORT_LOSORT_MERGE_COMP_30_LOGIC sort_hisort_losort_merge_comp_30_z1 = sort_hisort_losort_losort_feedthru_44_z; sort_hisort_losort_merge_comp_30_z2 = sort_hisort_losort_hisort_feedthru_45_z; if ((1'b1 == (sort_hisort_losort_losort_feedthru_44_z > sort_hisort_losort_hisort_feedthru_45_z))) begin sort_hisort_losort_merge_comp_30_z1 = sort_hisort_losort_hisort_feedthru_45_z; sort_hisort_losort_merge_comp_30_z2 = sort_hisort_losort_losort_feedthru_44_z; end end assign sort_hisort_losort_merge_lomerge_feedthru_46_z = sort_hisort_losort_merge_comp_30_z1; assign sort_hisort_losort_merge_hiMerge_feedthru_47_z = sort_hisort_losort_merge_comp_30_z2; assign sort_hisort_hisort_losort_feedthru_48_z = a6; assign sort_hisort_hisort_hisort_feedthru_49_z = a7; always @(sort_hisort_hisort_losort_feedthru_48_z, sort_hisort_hisort_hisort_feedthru_49_z) begin: ARRAY8SORTER_SORT_HISORT_HISORT_MERGE_COMP_31_LOGIC sort_hisort_hisort_merge_comp_31_z1 = sort_hisort_hisort_losort_feedthru_48_z; sort_hisort_hisort_merge_comp_31_z2 = sort_hisort_hisort_hisort_feedthru_49_z; if ((1'b0 == (sort_hisort_hisort_losort_feedthru_48_z > sort_hisort_hisort_hisort_feedthru_49_z))) begin sort_hisort_hisort_merge_comp_31_z1 = sort_hisort_hisort_hisort_feedthru_49_z; sort_hisort_hisort_merge_comp_31_z2 = sort_hisort_hisort_losort_feedthru_48_z; end end assign sort_hisort_hisort_merge_lomerge_feedthru_50_z = sort_hisort_hisort_merge_comp_31_z1; assign sort_hisort_hisort_merge_hiMerge_feedthru_51_z = sort_hisort_hisort_merge_comp_31_z2; always @(sort_hisort_losort_merge_lomerge_feedthru_46_z, sort_hisort_hisort_merge_lomerge_feedthru_50_z) begin: ARRAY8SORTER_SORT_HISORT_MERGE_COMP_32_LOGIC sort_hisort_merge_comp_32_z1 = sort_hisort_losort_merge_lomerge_feedthru_46_z; sort_hisort_merge_comp_32_z2 = sort_hisort_hisort_merge_lomerge_feedthru_50_z; if ((1'b0 == (sort_hisort_losort_merge_lomerge_feedthru_46_z > sort_hisort_hisort_merge_lomerge_feedthru_50_z))) begin sort_hisort_merge_comp_32_z1 = sort_hisort_hisort_merge_lomerge_feedthru_50_z; sort_hisort_merge_comp_32_z2 = sort_hisort_losort_merge_lomerge_feedthru_46_z; end end always @(sort_hisort_losort_merge_hiMerge_feedthru_47_z, sort_hisort_hisort_merge_hiMerge_feedthru_51_z) begin: ARRAY8SORTER_SORT_HISORT_MERGE_COMP_33_LOGIC sort_hisort_merge_comp_33_z1 = sort_hisort_losort_merge_hiMerge_feedthru_47_z; sort_hisort_merge_comp_33_z2 = sort_hisort_hisort_merge_hiMerge_feedthru_51_z; if ((1'b0 == (sort_hisort_losort_merge_hiMerge_feedthru_47_z > sort_hisort_hisort_merge_hiMerge_feedthru_51_z))) begin sort_hisort_merge_comp_33_z1 = sort_hisort_hisort_merge_hiMerge_feedthru_51_z; sort_hisort_merge_comp_33_z2 = sort_hisort_losort_merge_hiMerge_feedthru_47_z; end end always @(sort_hisort_merge_comp_32_z1, sort_hisort_merge_comp_33_z1) begin: ARRAY8SORTER_SORT_HISORT_MERGE_LOMERGE_COMP_34_LOGIC sort_hisort_merge_lomerge_comp_34_z1 = sort_hisort_merge_comp_32_z1; sort_hisort_merge_lomerge_comp_34_z2 = sort_hisort_merge_comp_33_z1; if ((1'b0 == (sort_hisort_merge_comp_32_z1 > sort_hisort_merge_comp_33_z1))) begin sort_hisort_merge_lomerge_comp_34_z1 = sort_hisort_merge_comp_33_z1; sort_hisort_merge_lomerge_comp_34_z2 = sort_hisort_merge_comp_32_z1; end end assign sort_hisort_merge_lomerge_lomerge_feedthru_52_z = sort_hisort_merge_lomerge_comp_34_z1; assign sort_hisort_merge_lomerge_hiMerge_feedthru_53_z = sort_hisort_merge_lomerge_comp_34_z2; always @(sort_hisort_merge_comp_32_z2, sort_hisort_merge_comp_33_z2) begin: ARRAY8SORTER_SORT_HISORT_MERGE_HIMERGE_COMP_35_LOGIC sort_hisort_merge_hiMerge_comp_35_z1 = sort_hisort_merge_comp_32_z2; sort_hisort_merge_hiMerge_comp_35_z2 = sort_hisort_merge_comp_33_z2; if ((1'b0 == (sort_hisort_merge_comp_32_z2 > sort_hisort_merge_comp_33_z2))) begin sort_hisort_merge_hiMerge_comp_35_z1 = sort_hisort_merge_comp_33_z2; sort_hisort_merge_hiMerge_comp_35_z2 = sort_hisort_merge_comp_32_z2; end end assign sort_hisort_merge_hiMerge_lomerge_feedthru_54_z = sort_hisort_merge_hiMerge_comp_35_z1; assign sort_hisort_merge_hiMerge_hiMerge_feedthru_55_z = sort_hisort_merge_hiMerge_comp_35_z2; always @(sort_losort_merge_lomerge_lomerge_feedthru_40_z, sort_hisort_merge_lomerge_lomerge_feedthru_52_z) begin: ARRAY8SORTER_SORT_MERGE_COMP_36_LOGIC sort_merge_comp_36_z1 = sort_losort_merge_lomerge_lomerge_feedthru_40_z; sort_merge_comp_36_z2 = sort_hisort_merge_lomerge_lomerge_feedthru_52_z; if ((1'b1 == (sort_losort_merge_lomerge_lomerge_feedthru_40_z > sort_hisort_merge_lomerge_lomerge_feedthru_52_z))) begin sort_merge_comp_36_z1 = sort_hisort_merge_lomerge_lomerge_feedthru_52_z; sort_merge_comp_36_z2 = sort_losort_merge_lomerge_lomerge_feedthru_40_z; end end always @(sort_losort_merge_lomerge_hiMerge_feedthru_41_z, sort_hisort_merge_lomerge_hiMerge_feedthru_53_z) begin: ARRAY8SORTER_SORT_MERGE_COMP_37_LOGIC sort_merge_comp_37_z1 = sort_losort_merge_lomerge_hiMerge_feedthru_41_z; sort_merge_comp_37_z2 = sort_hisort_merge_lomerge_hiMerge_feedthru_53_z; if ((1'b1 == (sort_losort_merge_lomerge_hiMerge_feedthru_41_z > sort_hisort_merge_lomerge_hiMerge_feedthru_53_z))) begin sort_merge_comp_37_z1 = sort_hisort_merge_lomerge_hiMerge_feedthru_53_z; sort_merge_comp_37_z2 = sort_losort_merge_lomerge_hiMerge_feedthru_41_z; end end always @(sort_losort_merge_hiMerge_lomerge_feedthru_42_z, sort_hisort_merge_hiMerge_lomerge_feedthru_54_z) begin: ARRAY8SORTER_SORT_MERGE_COMP_38_LOGIC sort_merge_comp_38_z1 = sort_losort_merge_hiMerge_lomerge_feedthru_42_z; sort_merge_comp_38_z2 = sort_hisort_merge_hiMerge_lomerge_feedthru_54_z; if ((1'b1 == (sort_losort_merge_hiMerge_lomerge_feedthru_42_z > sort_hisort_merge_hiMerge_lomerge_feedthru_54_z))) begin sort_merge_comp_38_z1 = sort_hisort_merge_hiMerge_lomerge_feedthru_54_z; sort_merge_comp_38_z2 = sort_losort_merge_hiMerge_lomerge_feedthru_42_z; end end always @(sort_losort_merge_hiMerge_hiMerge_feedthru_43_z, sort_hisort_merge_hiMerge_hiMerge_feedthru_55_z) begin: ARRAY8SORTER_SORT_MERGE_COMP_39_LOGIC sort_merge_comp_39_z1 = sort_losort_merge_hiMerge_hiMerge_feedthru_43_z; sort_merge_comp_39_z2 = sort_hisort_merge_hiMerge_hiMerge_feedthru_55_z; if ((1'b1 == (sort_losort_merge_hiMerge_hiMerge_feedthru_43_z > sort_hisort_merge_hiMerge_hiMerge_feedthru_55_z))) begin sort_merge_comp_39_z1 = sort_hisort_merge_hiMerge_hiMerge_feedthru_55_z; sort_merge_comp_39_z2 = sort_losort_merge_hiMerge_hiMerge_feedthru_43_z; end end always @(sort_merge_comp_36_z1, sort_merge_comp_38_z1) begin: ARRAY8SORTER_SORT_MERGE_LOMERGE_COMP_40_LOGIC sort_merge_lomerge_comp_40_z1 = sort_merge_comp_36_z1; sort_merge_lomerge_comp_40_z2 = sort_merge_comp_38_z1; if ((1'b1 == (sort_merge_comp_36_z1 > sort_merge_comp_38_z1))) begin sort_merge_lomerge_comp_40_z1 = sort_merge_comp_38_z1; sort_merge_lomerge_comp_40_z2 = sort_merge_comp_36_z1; end end always @(sort_merge_comp_37_z1, sort_merge_comp_39_z1) begin: ARRAY8SORTER_SORT_MERGE_LOMERGE_COMP_41_LOGIC sort_merge_lomerge_comp_41_z1 = sort_merge_comp_37_z1; sort_merge_lomerge_comp_41_z2 = sort_merge_comp_39_z1; if ((1'b1 == (sort_merge_comp_37_z1 > sort_merge_comp_39_z1))) begin sort_merge_lomerge_comp_41_z1 = sort_merge_comp_39_z1; sort_merge_lomerge_comp_41_z2 = sort_merge_comp_37_z1; end end always @(sort_merge_lomerge_comp_40_z1, sort_merge_lomerge_comp_41_z1) begin: ARRAY8SORTER_SORT_MERGE_LOMERGE_LOMERGE_COMP_42_LOGIC sort_merge_lomerge_lomerge_comp_42_z1 = sort_merge_lomerge_comp_40_z1; sort_merge_lomerge_lomerge_comp_42_z2 = sort_merge_lomerge_comp_41_z1; if ((1'b1 == (sort_merge_lomerge_comp_40_z1 > sort_merge_lomerge_comp_41_z1))) begin sort_merge_lomerge_lomerge_comp_42_z1 = sort_merge_lomerge_comp_41_z1; sort_merge_lomerge_lomerge_comp_42_z2 = sort_merge_lomerge_comp_40_z1; end end assign z0 = sort_merge_lomerge_lomerge_comp_42_z1; assign z1 = sort_merge_lomerge_lomerge_comp_42_z2; always @(sort_merge_lomerge_comp_40_z2, sort_merge_lomerge_comp_41_z2) begin: ARRAY8SORTER_SORT_MERGE_LOMERGE_HIMERGE_COMP_43_LOGIC sort_merge_lomerge_hiMerge_comp_43_z1 = sort_merge_lomerge_comp_40_z2; sort_merge_lomerge_hiMerge_comp_43_z2 = sort_merge_lomerge_comp_41_z2; if ((1'b1 == (sort_merge_lomerge_comp_40_z2 > sort_merge_lomerge_comp_41_z2))) begin sort_merge_lomerge_hiMerge_comp_43_z1 = sort_merge_lomerge_comp_41_z2; sort_merge_lomerge_hiMerge_comp_43_z2 = sort_merge_lomerge_comp_40_z2; end end assign z2 = sort_merge_lomerge_hiMerge_comp_43_z1; assign z3 = sort_merge_lomerge_hiMerge_comp_43_z2; always @(sort_merge_comp_36_z2, sort_merge_comp_38_z2) begin: ARRAY8SORTER_SORT_MERGE_HIMERGE_COMP_44_LOGIC sort_merge_hiMerge_comp_44_z1 = sort_merge_comp_36_z2; sort_merge_hiMerge_comp_44_z2 = sort_merge_comp_38_z2; if ((1'b1 == (sort_merge_comp_36_z2 > sort_merge_comp_38_z2))) begin sort_merge_hiMerge_comp_44_z1 = sort_merge_comp_38_z2; sort_merge_hiMerge_comp_44_z2 = sort_merge_comp_36_z2; end end always @(sort_merge_comp_37_z2, sort_merge_comp_39_z2) begin: ARRAY8SORTER_SORT_MERGE_HIMERGE_COMP_45_LOGIC sort_merge_hiMerge_comp_45_z1 = sort_merge_comp_37_z2; sort_merge_hiMerge_comp_45_z2 = sort_merge_comp_39_z2; if ((1'b1 == (sort_merge_comp_37_z2 > sort_merge_comp_39_z2))) begin sort_merge_hiMerge_comp_45_z1 = sort_merge_comp_39_z2; sort_merge_hiMerge_comp_45_z2 = sort_merge_comp_37_z2; end end always @(sort_merge_hiMerge_comp_44_z1, sort_merge_hiMerge_comp_45_z1) begin: ARRAY8SORTER_SORT_MERGE_HIMERGE_LOMERGE_COMP_46_LOGIC sort_merge_hiMerge_lomerge_comp_46_z1 = sort_merge_hiMerge_comp_44_z1; sort_merge_hiMerge_lomerge_comp_46_z2 = sort_merge_hiMerge_comp_45_z1; if ((1'b1 == (sort_merge_hiMerge_comp_44_z1 > sort_merge_hiMerge_comp_45_z1))) begin sort_merge_hiMerge_lomerge_comp_46_z1 = sort_merge_hiMerge_comp_45_z1; sort_merge_hiMerge_lomerge_comp_46_z2 = sort_merge_hiMerge_comp_44_z1; end end assign z4 = sort_merge_hiMerge_lomerge_comp_46_z1; assign z5 = sort_merge_hiMerge_lomerge_comp_46_z2; always @(sort_merge_hiMerge_comp_44_z2, sort_merge_hiMerge_comp_45_z2) begin: ARRAY8SORTER_SORT_MERGE_HIMERGE_HIMERGE_COMP_47_LOGIC sort_merge_hiMerge_hiMerge_comp_47_z1 = sort_merge_hiMerge_comp_44_z2; sort_merge_hiMerge_hiMerge_comp_47_z2 = sort_merge_hiMerge_comp_45_z2; if ((1'b1 == (sort_merge_hiMerge_comp_44_z2 > sort_merge_hiMerge_comp_45_z2))) begin sort_merge_hiMerge_hiMerge_comp_47_z1 = sort_merge_hiMerge_comp_45_z2; sort_merge_hiMerge_hiMerge_comp_47_z2 = sort_merge_hiMerge_comp_44_z2; end end assign z6 = sort_merge_hiMerge_hiMerge_comp_47_z1; assign z7 = sort_merge_hiMerge_hiMerge_comp_47_z2; endmodule myhdl-0.11/example/cookbook/bitonic/tb_Array8Sorter.v000066400000000000000000000012401347432460400226650ustar00rootroot00000000000000module tb_Array8Sorter; reg [3:0] a0; reg [3:0] a1; reg [3:0] a2; reg [3:0] a3; reg [3:0] a4; reg [3:0] a5; reg [3:0] a6; reg [3:0] a7; wire [3:0] z0; wire [3:0] z1; wire [3:0] z2; wire [3:0] z3; wire [3:0] z4; wire [3:0] z5; wire [3:0] z6; wire [3:0] z7; initial begin $from_myhdl( a0, a1, a2, a3, a4, a5, a6, a7 ); $to_myhdl( z0, z1, z2, z3, z4, z5, z6, z7 ); end Array8Sorter dut( a0, a1, a2, a3, a4, a5, a6, a7, z0, z1, z2, z3, z4, z5, z6, z7 ); endmodule myhdl-0.11/example/cookbook/bitonic/test_bitonic.py000066400000000000000000000015031347432460400225060ustar00rootroot00000000000000from random import randrange import myhdl from myhdl import * from bitonic import Array8Sorter, Array8Sorter_v @block def bench(): n = 8 w = 4 a0, a1, a2, a3, a4, a5, a6, a7 = inputs = [Signal(intbv(0)[w:]) for i in range(n)] z0, z1, z2, z3, z4, z5, z6, z7 = outputs = [Signal(intbv(0)[w:]) for i in range(n)] inst = Array8Sorter_v(a0, a1, a2, a3, a4, a5, a6, a7, z0, z1, z2, z3, z4, z5, z6, z7) @instance def check(): for i in range(100): data = [randrange(2**w) for i in range(n)] for i in range(n): inputs[i].next = data[i] yield delay(10) data.sort() assert data == outputs return inst, check def test_bench(): bench().run_sim() if __name__ == '__main__': test_bench() myhdl-0.11/example/cookbook/bitonic/tmp.v000066400000000000000000000470271347432460400204500ustar00rootroot00000000000000// File: Array8Sorter.v // Generated by MyHDL 1.0dev // Date: Sat Mar 19 15:39:54 2016 `timescale 1ns/10ps module Array8Sorter ( a0, a1, a2, a3, a4, a5, a6, a7, z0, z1, z2, z3, z4, z5, z6, z7 ); input [3:0] a0; input [3:0] a1; input [3:0] a2; input [3:0] a3; input [3:0] a4; input [3:0] a5; input [3:0] a6; input [3:0] a7; output [3:0] z0; wire [3:0] z0; output [3:0] z1; wire [3:0] z1; output [3:0] z2; wire [3:0] z2; output [3:0] z3; wire [3:0] z3; output [3:0] z4; wire [3:0] z4; output [3:0] z5; wire [3:0] z5; output [3:0] z6; wire [3:0] z6; output [3:0] z7; wire [3:0] z7; wire [3:0] sort_losort_losort_losort_feedthru_34_z; wire [3:0] sort_losort_losort_hisort_feedthru_35_z; reg [3:0] sort_losort_losort_merge_comp_26_z1; reg [3:0] sort_losort_losort_merge_comp_26_z2; wire [3:0] sort_losort_losort_merge_lomerge_feedthru_36_z; wire [3:0] sort_losort_losort_merge_hiMerge_feedthru_37_z; wire [3:0] sort_losort_hisort_losort_feedthru_38_z; wire [3:0] sort_losort_hisort_hisort_feedthru_39_z; reg [3:0] sort_losort_hisort_merge_comp_27_z1; reg [3:0] sort_losort_hisort_merge_comp_27_z2; wire [3:0] sort_losort_hisort_merge_lomerge_feedthru_40_z; wire [3:0] sort_losort_hisort_merge_hiMerge_feedthru_41_z; reg [3:0] sort_losort_merge_comp_28_z1; reg [3:0] sort_losort_merge_comp_28_z2; reg [3:0] sort_losort_merge_comp_29_z1; reg [3:0] sort_losort_merge_comp_29_z2; reg [3:0] sort_losort_merge_lomerge_comp_30_z1; reg [3:0] sort_losort_merge_lomerge_comp_30_z2; wire [3:0] sort_losort_merge_lomerge_lomerge_feedthru_42_z; wire [3:0] sort_losort_merge_lomerge_hiMerge_feedthru_43_z; reg [3:0] sort_losort_merge_hiMerge_comp_31_z1; reg [3:0] sort_losort_merge_hiMerge_comp_31_z2; wire [3:0] sort_losort_merge_hiMerge_lomerge_feedthru_44_z; wire [3:0] sort_losort_merge_hiMerge_hiMerge_feedthru_45_z; wire [3:0] sort_hisort_losort_losort_feedthru_46_z; wire [3:0] sort_hisort_losort_hisort_feedthru_47_z; reg [3:0] sort_hisort_losort_merge_comp_32_z1; reg [3:0] sort_hisort_losort_merge_comp_32_z2; wire [3:0] sort_hisort_losort_merge_lomerge_feedthru_48_z; wire [3:0] sort_hisort_losort_merge_hiMerge_feedthru_49_z; wire [3:0] sort_hisort_hisort_losort_feedthru_50_z; wire [3:0] sort_hisort_hisort_hisort_feedthru_51_z; reg [3:0] sort_hisort_hisort_merge_comp_33_z1; reg [3:0] sort_hisort_hisort_merge_comp_33_z2; wire [3:0] sort_hisort_hisort_merge_lomerge_feedthru_52_z; wire [3:0] sort_hisort_hisort_merge_hiMerge_feedthru_53_z; reg [3:0] sort_hisort_merge_comp_34_z1; reg [3:0] sort_hisort_merge_comp_34_z2; reg [3:0] sort_hisort_merge_comp_35_z1; reg [3:0] sort_hisort_merge_comp_35_z2; reg [3:0] sort_hisort_merge_lomerge_comp_36_z1; reg [3:0] sort_hisort_merge_lomerge_comp_36_z2; wire [3:0] sort_hisort_merge_lomerge_lomerge_feedthru_54_z; wire [3:0] sort_hisort_merge_lomerge_hiMerge_feedthru_55_z; reg [3:0] sort_hisort_merge_hiMerge_comp_37_z1; reg [3:0] sort_hisort_merge_hiMerge_comp_37_z2; wire [3:0] sort_hisort_merge_hiMerge_lomerge_feedthru_56_z; wire [3:0] sort_hisort_merge_hiMerge_hiMerge_feedthru_57_z; reg [3:0] sort_merge_comp_38_z1; reg [3:0] sort_merge_comp_38_z2; reg [3:0] sort_merge_comp_39_z1; reg [3:0] sort_merge_comp_39_z2; reg [3:0] sort_merge_comp_40_z1; reg [3:0] sort_merge_comp_40_z2; reg [3:0] sort_merge_comp_41_z1; reg [3:0] sort_merge_comp_41_z2; reg [3:0] sort_merge_lomerge_comp_42_z1; reg [3:0] sort_merge_lomerge_comp_42_z2; reg [3:0] sort_merge_lomerge_comp_43_z1; reg [3:0] sort_merge_lomerge_comp_43_z2; reg [3:0] sort_merge_lomerge_lomerge_comp_44_z1; reg [3:0] sort_merge_lomerge_lomerge_comp_44_z2; reg [3:0] sort_merge_lomerge_hiMerge_comp_45_z1; reg [3:0] sort_merge_lomerge_hiMerge_comp_45_z2; reg [3:0] sort_merge_hiMerge_comp_46_z1; reg [3:0] sort_merge_hiMerge_comp_46_z2; reg [3:0] sort_merge_hiMerge_comp_47_z1; reg [3:0] sort_merge_hiMerge_comp_47_z2; reg [3:0] sort_merge_hiMerge_lomerge_comp_48_z1; reg [3:0] sort_merge_hiMerge_lomerge_comp_48_z2; reg [3:0] sort_merge_hiMerge_hiMerge_comp_49_z1; reg [3:0] sort_merge_hiMerge_hiMerge_comp_49_z2; assign sort_losort_losort_losort_feedthru_34_z = a0; assign sort_losort_losort_hisort_feedthru_35_z = a1; always @(sort_losort_losort_losort_feedthru_34_z, sort_losort_losort_hisort_feedthru_35_z) begin: ARRAY8SORTER_SORT_LOSORT_LOSORT_MERGE_COMP_26_LOGIC sort_losort_losort_merge_comp_26_z1 = sort_losort_losort_losort_feedthru_34_z; sort_losort_losort_merge_comp_26_z2 = sort_losort_losort_hisort_feedthru_35_z; if ((1'b1 == (sort_losort_losort_losort_feedthru_34_z > sort_losort_losort_hisort_feedthru_35_z))) begin sort_losort_losort_merge_comp_26_z1 = sort_losort_losort_hisort_feedthru_35_z; sort_losort_losort_merge_comp_26_z2 = sort_losort_losort_losort_feedthru_34_z; end end assign sort_losort_losort_merge_lomerge_feedthru_36_z = sort_losort_losort_merge_comp_26_z1; assign sort_losort_losort_merge_hiMerge_feedthru_37_z = sort_losort_losort_merge_comp_26_z2; assign sort_losort_hisort_losort_feedthru_38_z = a2; assign sort_losort_hisort_hisort_feedthru_39_z = a3; always @(sort_losort_hisort_losort_feedthru_38_z, sort_losort_hisort_hisort_feedthru_39_z) begin: ARRAY8SORTER_SORT_LOSORT_HISORT_MERGE_COMP_27_LOGIC sort_losort_hisort_merge_comp_27_z1 = sort_losort_hisort_losort_feedthru_38_z; sort_losort_hisort_merge_comp_27_z2 = sort_losort_hisort_hisort_feedthru_39_z; if ((1'b0 == (sort_losort_hisort_losort_feedthru_38_z > sort_losort_hisort_hisort_feedthru_39_z))) begin sort_losort_hisort_merge_comp_27_z1 = sort_losort_hisort_hisort_feedthru_39_z; sort_losort_hisort_merge_comp_27_z2 = sort_losort_hisort_losort_feedthru_38_z; end end assign sort_losort_hisort_merge_lomerge_feedthru_40_z = sort_losort_hisort_merge_comp_27_z1; assign sort_losort_hisort_merge_hiMerge_feedthru_41_z = sort_losort_hisort_merge_comp_27_z2; always @(sort_losort_losort_merge_lomerge_feedthru_36_z, sort_losort_hisort_merge_lomerge_feedthru_40_z) begin: ARRAY8SORTER_SORT_LOSORT_MERGE_COMP_28_LOGIC sort_losort_merge_comp_28_z1 = sort_losort_losort_merge_lomerge_feedthru_36_z; sort_losort_merge_comp_28_z2 = sort_losort_hisort_merge_lomerge_feedthru_40_z; if ((1'b1 == (sort_losort_losort_merge_lomerge_feedthru_36_z > sort_losort_hisort_merge_lomerge_feedthru_40_z))) begin sort_losort_merge_comp_28_z1 = sort_losort_hisort_merge_lomerge_feedthru_40_z; sort_losort_merge_comp_28_z2 = sort_losort_losort_merge_lomerge_feedthru_36_z; end end always @(sort_losort_losort_merge_hiMerge_feedthru_37_z, sort_losort_hisort_merge_hiMerge_feedthru_41_z) begin: ARRAY8SORTER_SORT_LOSORT_MERGE_COMP_29_LOGIC sort_losort_merge_comp_29_z1 = sort_losort_losort_merge_hiMerge_feedthru_37_z; sort_losort_merge_comp_29_z2 = sort_losort_hisort_merge_hiMerge_feedthru_41_z; if ((1'b1 == (sort_losort_losort_merge_hiMerge_feedthru_37_z > sort_losort_hisort_merge_hiMerge_feedthru_41_z))) begin sort_losort_merge_comp_29_z1 = sort_losort_hisort_merge_hiMerge_feedthru_41_z; sort_losort_merge_comp_29_z2 = sort_losort_losort_merge_hiMerge_feedthru_37_z; end end always @(sort_losort_merge_comp_28_z1, sort_losort_merge_comp_29_z1) begin: ARRAY8SORTER_SORT_LOSORT_MERGE_LOMERGE_COMP_30_LOGIC sort_losort_merge_lomerge_comp_30_z1 = sort_losort_merge_comp_28_z1; sort_losort_merge_lomerge_comp_30_z2 = sort_losort_merge_comp_29_z1; if ((1'b1 == (sort_losort_merge_comp_28_z1 > sort_losort_merge_comp_29_z1))) begin sort_losort_merge_lomerge_comp_30_z1 = sort_losort_merge_comp_29_z1; sort_losort_merge_lomerge_comp_30_z2 = sort_losort_merge_comp_28_z1; end end assign sort_losort_merge_lomerge_lomerge_feedthru_42_z = sort_losort_merge_lomerge_comp_30_z1; assign sort_losort_merge_lomerge_hiMerge_feedthru_43_z = sort_losort_merge_lomerge_comp_30_z2; always @(sort_losort_merge_comp_28_z2, sort_losort_merge_comp_29_z2) begin: ARRAY8SORTER_SORT_LOSORT_MERGE_HIMERGE_COMP_31_LOGIC sort_losort_merge_hiMerge_comp_31_z1 = sort_losort_merge_comp_28_z2; sort_losort_merge_hiMerge_comp_31_z2 = sort_losort_merge_comp_29_z2; if ((1'b1 == (sort_losort_merge_comp_28_z2 > sort_losort_merge_comp_29_z2))) begin sort_losort_merge_hiMerge_comp_31_z1 = sort_losort_merge_comp_29_z2; sort_losort_merge_hiMerge_comp_31_z2 = sort_losort_merge_comp_28_z2; end end assign sort_losort_merge_hiMerge_lomerge_feedthru_44_z = sort_losort_merge_hiMerge_comp_31_z1; assign sort_losort_merge_hiMerge_hiMerge_feedthru_45_z = sort_losort_merge_hiMerge_comp_31_z2; assign sort_hisort_losort_losort_feedthru_46_z = a4; assign sort_hisort_losort_hisort_feedthru_47_z = a5; always @(sort_hisort_losort_losort_feedthru_46_z, sort_hisort_losort_hisort_feedthru_47_z) begin: ARRAY8SORTER_SORT_HISORT_LOSORT_MERGE_COMP_32_LOGIC sort_hisort_losort_merge_comp_32_z1 = sort_hisort_losort_losort_feedthru_46_z; sort_hisort_losort_merge_comp_32_z2 = sort_hisort_losort_hisort_feedthru_47_z; if ((1'b1 == (sort_hisort_losort_losort_feedthru_46_z > sort_hisort_losort_hisort_feedthru_47_z))) begin sort_hisort_losort_merge_comp_32_z1 = sort_hisort_losort_hisort_feedthru_47_z; sort_hisort_losort_merge_comp_32_z2 = sort_hisort_losort_losort_feedthru_46_z; end end assign sort_hisort_losort_merge_lomerge_feedthru_48_z = sort_hisort_losort_merge_comp_32_z1; assign sort_hisort_losort_merge_hiMerge_feedthru_49_z = sort_hisort_losort_merge_comp_32_z2; assign sort_hisort_hisort_losort_feedthru_50_z = a6; assign sort_hisort_hisort_hisort_feedthru_51_z = a7; always @(sort_hisort_hisort_losort_feedthru_50_z, sort_hisort_hisort_hisort_feedthru_51_z) begin: ARRAY8SORTER_SORT_HISORT_HISORT_MERGE_COMP_33_LOGIC sort_hisort_hisort_merge_comp_33_z1 = sort_hisort_hisort_losort_feedthru_50_z; sort_hisort_hisort_merge_comp_33_z2 = sort_hisort_hisort_hisort_feedthru_51_z; if ((1'b0 == (sort_hisort_hisort_losort_feedthru_50_z > sort_hisort_hisort_hisort_feedthru_51_z))) begin sort_hisort_hisort_merge_comp_33_z1 = sort_hisort_hisort_hisort_feedthru_51_z; sort_hisort_hisort_merge_comp_33_z2 = sort_hisort_hisort_losort_feedthru_50_z; end end assign sort_hisort_hisort_merge_lomerge_feedthru_52_z = sort_hisort_hisort_merge_comp_33_z1; assign sort_hisort_hisort_merge_hiMerge_feedthru_53_z = sort_hisort_hisort_merge_comp_33_z2; always @(sort_hisort_losort_merge_lomerge_feedthru_48_z, sort_hisort_hisort_merge_lomerge_feedthru_52_z) begin: ARRAY8SORTER_SORT_HISORT_MERGE_COMP_34_LOGIC sort_hisort_merge_comp_34_z1 = sort_hisort_losort_merge_lomerge_feedthru_48_z; sort_hisort_merge_comp_34_z2 = sort_hisort_hisort_merge_lomerge_feedthru_52_z; if ((1'b0 == (sort_hisort_losort_merge_lomerge_feedthru_48_z > sort_hisort_hisort_merge_lomerge_feedthru_52_z))) begin sort_hisort_merge_comp_34_z1 = sort_hisort_hisort_merge_lomerge_feedthru_52_z; sort_hisort_merge_comp_34_z2 = sort_hisort_losort_merge_lomerge_feedthru_48_z; end end always @(sort_hisort_losort_merge_hiMerge_feedthru_49_z, sort_hisort_hisort_merge_hiMerge_feedthru_53_z) begin: ARRAY8SORTER_SORT_HISORT_MERGE_COMP_35_LOGIC sort_hisort_merge_comp_35_z1 = sort_hisort_losort_merge_hiMerge_feedthru_49_z; sort_hisort_merge_comp_35_z2 = sort_hisort_hisort_merge_hiMerge_feedthru_53_z; if ((1'b0 == (sort_hisort_losort_merge_hiMerge_feedthru_49_z > sort_hisort_hisort_merge_hiMerge_feedthru_53_z))) begin sort_hisort_merge_comp_35_z1 = sort_hisort_hisort_merge_hiMerge_feedthru_53_z; sort_hisort_merge_comp_35_z2 = sort_hisort_losort_merge_hiMerge_feedthru_49_z; end end always @(sort_hisort_merge_comp_34_z1, sort_hisort_merge_comp_35_z1) begin: ARRAY8SORTER_SORT_HISORT_MERGE_LOMERGE_COMP_36_LOGIC sort_hisort_merge_lomerge_comp_36_z1 = sort_hisort_merge_comp_34_z1; sort_hisort_merge_lomerge_comp_36_z2 = sort_hisort_merge_comp_35_z1; if ((1'b0 == (sort_hisort_merge_comp_34_z1 > sort_hisort_merge_comp_35_z1))) begin sort_hisort_merge_lomerge_comp_36_z1 = sort_hisort_merge_comp_35_z1; sort_hisort_merge_lomerge_comp_36_z2 = sort_hisort_merge_comp_34_z1; end end assign sort_hisort_merge_lomerge_lomerge_feedthru_54_z = sort_hisort_merge_lomerge_comp_36_z1; assign sort_hisort_merge_lomerge_hiMerge_feedthru_55_z = sort_hisort_merge_lomerge_comp_36_z2; always @(sort_hisort_merge_comp_34_z2, sort_hisort_merge_comp_35_z2) begin: ARRAY8SORTER_SORT_HISORT_MERGE_HIMERGE_COMP_37_LOGIC sort_hisort_merge_hiMerge_comp_37_z1 = sort_hisort_merge_comp_34_z2; sort_hisort_merge_hiMerge_comp_37_z2 = sort_hisort_merge_comp_35_z2; if ((1'b0 == (sort_hisort_merge_comp_34_z2 > sort_hisort_merge_comp_35_z2))) begin sort_hisort_merge_hiMerge_comp_37_z1 = sort_hisort_merge_comp_35_z2; sort_hisort_merge_hiMerge_comp_37_z2 = sort_hisort_merge_comp_34_z2; end end assign sort_hisort_merge_hiMerge_lomerge_feedthru_56_z = sort_hisort_merge_hiMerge_comp_37_z1; assign sort_hisort_merge_hiMerge_hiMerge_feedthru_57_z = sort_hisort_merge_hiMerge_comp_37_z2; always @(sort_losort_merge_lomerge_lomerge_feedthru_42_z, sort_hisort_merge_lomerge_lomerge_feedthru_54_z) begin: ARRAY8SORTER_SORT_MERGE_COMP_38_LOGIC sort_merge_comp_38_z1 = sort_losort_merge_lomerge_lomerge_feedthru_42_z; sort_merge_comp_38_z2 = sort_hisort_merge_lomerge_lomerge_feedthru_54_z; if ((1'b1 == (sort_losort_merge_lomerge_lomerge_feedthru_42_z > sort_hisort_merge_lomerge_lomerge_feedthru_54_z))) begin sort_merge_comp_38_z1 = sort_hisort_merge_lomerge_lomerge_feedthru_54_z; sort_merge_comp_38_z2 = sort_losort_merge_lomerge_lomerge_feedthru_42_z; end end always @(sort_losort_merge_lomerge_hiMerge_feedthru_43_z, sort_hisort_merge_lomerge_hiMerge_feedthru_55_z) begin: ARRAY8SORTER_SORT_MERGE_COMP_39_LOGIC sort_merge_comp_39_z1 = sort_losort_merge_lomerge_hiMerge_feedthru_43_z; sort_merge_comp_39_z2 = sort_hisort_merge_lomerge_hiMerge_feedthru_55_z; if ((1'b1 == (sort_losort_merge_lomerge_hiMerge_feedthru_43_z > sort_hisort_merge_lomerge_hiMerge_feedthru_55_z))) begin sort_merge_comp_39_z1 = sort_hisort_merge_lomerge_hiMerge_feedthru_55_z; sort_merge_comp_39_z2 = sort_losort_merge_lomerge_hiMerge_feedthru_43_z; end end always @(sort_losort_merge_hiMerge_lomerge_feedthru_44_z, sort_hisort_merge_hiMerge_lomerge_feedthru_56_z) begin: ARRAY8SORTER_SORT_MERGE_COMP_40_LOGIC sort_merge_comp_40_z1 = sort_losort_merge_hiMerge_lomerge_feedthru_44_z; sort_merge_comp_40_z2 = sort_hisort_merge_hiMerge_lomerge_feedthru_56_z; if ((1'b1 == (sort_losort_merge_hiMerge_lomerge_feedthru_44_z > sort_hisort_merge_hiMerge_lomerge_feedthru_56_z))) begin sort_merge_comp_40_z1 = sort_hisort_merge_hiMerge_lomerge_feedthru_56_z; sort_merge_comp_40_z2 = sort_losort_merge_hiMerge_lomerge_feedthru_44_z; end end always @(sort_losort_merge_hiMerge_hiMerge_feedthru_45_z, sort_hisort_merge_hiMerge_hiMerge_feedthru_57_z) begin: ARRAY8SORTER_SORT_MERGE_COMP_41_LOGIC sort_merge_comp_41_z1 = sort_losort_merge_hiMerge_hiMerge_feedthru_45_z; sort_merge_comp_41_z2 = sort_hisort_merge_hiMerge_hiMerge_feedthru_57_z; if ((1'b1 == (sort_losort_merge_hiMerge_hiMerge_feedthru_45_z > sort_hisort_merge_hiMerge_hiMerge_feedthru_57_z))) begin sort_merge_comp_41_z1 = sort_hisort_merge_hiMerge_hiMerge_feedthru_57_z; sort_merge_comp_41_z2 = sort_losort_merge_hiMerge_hiMerge_feedthru_45_z; end end always @(sort_merge_comp_38_z1, sort_merge_comp_40_z1) begin: ARRAY8SORTER_SORT_MERGE_LOMERGE_COMP_42_LOGIC sort_merge_lomerge_comp_42_z1 = sort_merge_comp_38_z1; sort_merge_lomerge_comp_42_z2 = sort_merge_comp_40_z1; if ((1'b1 == (sort_merge_comp_38_z1 > sort_merge_comp_40_z1))) begin sort_merge_lomerge_comp_42_z1 = sort_merge_comp_40_z1; sort_merge_lomerge_comp_42_z2 = sort_merge_comp_38_z1; end end always @(sort_merge_comp_39_z1, sort_merge_comp_41_z1) begin: ARRAY8SORTER_SORT_MERGE_LOMERGE_COMP_43_LOGIC sort_merge_lomerge_comp_43_z1 = sort_merge_comp_39_z1; sort_merge_lomerge_comp_43_z2 = sort_merge_comp_41_z1; if ((1'b1 == (sort_merge_comp_39_z1 > sort_merge_comp_41_z1))) begin sort_merge_lomerge_comp_43_z1 = sort_merge_comp_41_z1; sort_merge_lomerge_comp_43_z2 = sort_merge_comp_39_z1; end end always @(sort_merge_lomerge_comp_42_z1, sort_merge_lomerge_comp_43_z1) begin: ARRAY8SORTER_SORT_MERGE_LOMERGE_LOMERGE_COMP_44_LOGIC sort_merge_lomerge_lomerge_comp_44_z1 = sort_merge_lomerge_comp_42_z1; sort_merge_lomerge_lomerge_comp_44_z2 = sort_merge_lomerge_comp_43_z1; if ((1'b1 == (sort_merge_lomerge_comp_42_z1 > sort_merge_lomerge_comp_43_z1))) begin sort_merge_lomerge_lomerge_comp_44_z1 = sort_merge_lomerge_comp_43_z1; sort_merge_lomerge_lomerge_comp_44_z2 = sort_merge_lomerge_comp_42_z1; end end assign z0 = sort_merge_lomerge_lomerge_comp_44_z1; assign z1 = sort_merge_lomerge_lomerge_comp_44_z2; always @(sort_merge_lomerge_comp_42_z2, sort_merge_lomerge_comp_43_z2) begin: ARRAY8SORTER_SORT_MERGE_LOMERGE_HIMERGE_COMP_45_LOGIC sort_merge_lomerge_hiMerge_comp_45_z1 = sort_merge_lomerge_comp_42_z2; sort_merge_lomerge_hiMerge_comp_45_z2 = sort_merge_lomerge_comp_43_z2; if ((1'b1 == (sort_merge_lomerge_comp_42_z2 > sort_merge_lomerge_comp_43_z2))) begin sort_merge_lomerge_hiMerge_comp_45_z1 = sort_merge_lomerge_comp_43_z2; sort_merge_lomerge_hiMerge_comp_45_z2 = sort_merge_lomerge_comp_42_z2; end end assign z2 = sort_merge_lomerge_hiMerge_comp_45_z1; assign z3 = sort_merge_lomerge_hiMerge_comp_45_z2; always @(sort_merge_comp_38_z2, sort_merge_comp_40_z2) begin: ARRAY8SORTER_SORT_MERGE_HIMERGE_COMP_46_LOGIC sort_merge_hiMerge_comp_46_z1 = sort_merge_comp_38_z2; sort_merge_hiMerge_comp_46_z2 = sort_merge_comp_40_z2; if ((1'b1 == (sort_merge_comp_38_z2 > sort_merge_comp_40_z2))) begin sort_merge_hiMerge_comp_46_z1 = sort_merge_comp_40_z2; sort_merge_hiMerge_comp_46_z2 = sort_merge_comp_38_z2; end end always @(sort_merge_comp_39_z2, sort_merge_comp_41_z2) begin: ARRAY8SORTER_SORT_MERGE_HIMERGE_COMP_47_LOGIC sort_merge_hiMerge_comp_47_z1 = sort_merge_comp_39_z2; sort_merge_hiMerge_comp_47_z2 = sort_merge_comp_41_z2; if ((1'b1 == (sort_merge_comp_39_z2 > sort_merge_comp_41_z2))) begin sort_merge_hiMerge_comp_47_z1 = sort_merge_comp_41_z2; sort_merge_hiMerge_comp_47_z2 = sort_merge_comp_39_z2; end end always @(sort_merge_hiMerge_comp_46_z1, sort_merge_hiMerge_comp_47_z1) begin: ARRAY8SORTER_SORT_MERGE_HIMERGE_LOMERGE_COMP_48_LOGIC sort_merge_hiMerge_lomerge_comp_48_z1 = sort_merge_hiMerge_comp_46_z1; sort_merge_hiMerge_lomerge_comp_48_z2 = sort_merge_hiMerge_comp_47_z1; if ((1'b1 == (sort_merge_hiMerge_comp_46_z1 > sort_merge_hiMerge_comp_47_z1))) begin sort_merge_hiMerge_lomerge_comp_48_z1 = sort_merge_hiMerge_comp_47_z1; sort_merge_hiMerge_lomerge_comp_48_z2 = sort_merge_hiMerge_comp_46_z1; end end assign z4 = sort_merge_hiMerge_lomerge_comp_48_z1; assign z5 = sort_merge_hiMerge_lomerge_comp_48_z2; always @(sort_merge_hiMerge_comp_46_z2, sort_merge_hiMerge_comp_47_z2) begin: ARRAY8SORTER_SORT_MERGE_HIMERGE_HIMERGE_COMP_49_LOGIC sort_merge_hiMerge_hiMerge_comp_49_z1 = sort_merge_hiMerge_comp_46_z2; sort_merge_hiMerge_hiMerge_comp_49_z2 = sort_merge_hiMerge_comp_47_z2; if ((1'b1 == (sort_merge_hiMerge_comp_46_z2 > sort_merge_hiMerge_comp_47_z2))) begin sort_merge_hiMerge_hiMerge_comp_49_z1 = sort_merge_hiMerge_comp_47_z2; sort_merge_hiMerge_hiMerge_comp_49_z2 = sort_merge_hiMerge_comp_46_z2; end end assign z6 = sort_merge_hiMerge_hiMerge_comp_49_z1; assign z7 = sort_merge_hiMerge_hiMerge_comp_49_z2; endmodule myhdl-0.11/example/cookbook/dff/000077500000000000000000000000001347432460400165575ustar00rootroot00000000000000myhdl-0.11/example/cookbook/dff/dff.py000066400000000000000000000014521347432460400176720ustar00rootroot00000000000000import myhdl from myhdl import * from myhdl.conversion import analyze def dff(q, d, clk): @always(clk.posedge) def logic(): q.next = d return logic from random import randrange def test_dff(): q, d, clk = [Signal(bool(0)) for i in range(3)] dff_inst = dff(q, d, clk) @always(delay(10)) def clkgen(): clk.next = not clk @always(clk.negedge) def stimulus(): d.next = randrange(2) return dff_inst, clkgen, stimulus def simulate(timesteps): traceSignals.timescale = "1ps" tb = traceSignals(test_dff) sim = Simulation(tb) sim.run(timesteps) sim.quit() simulate(2000) def convert(): q, d, clk = [Signal(bool(0)) for i in range(3)] toVerilog(dff, q, d, clk) analyze(dff, q, d, clk) convert() myhdl-0.11/example/cookbook/dff/test_dff.jpg000066400000000000000000001242131347432460400210620ustar00rootroot00000000000000ÿØÿàJFIFHHÿþCreated with The GIMPÿÛC    $.' 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î¾²~ÅssYþ¶®Mxÿž½"íýÓËô×Ï<úAÛÛŸ•¹é õä™ë}¬®! …k â ô@éWåWêezõH¾»v³H‚ÌHÃbÍ-kNµh$©H)B‚’ òã®B†«ó=½Ý®:kaƒ:é6TI7ì¾Ãò¶ÝBœHRT’pRH$wkÙ¬0ÌXíGŽÓl°Òm´„¥ €vÿÙmyhdl-0.11/example/cookbook/dffa/000077500000000000000000000000001347432460400167205ustar00rootroot00000000000000myhdl-0.11/example/cookbook/dffa/dffa.py000066400000000000000000000021301347432460400201660ustar00rootroot00000000000000import myhdl from myhdl import * def dffa(q, d, clk, rst): @always(clk.posedge, rst.negedge) def logic(): if rst == 0: q.next = 0 else: q.next = d return logic from random import randrange def test_dffa(): q, d, clk, rst = [Signal(bool(0)) for i in range(4)] dffa_inst = dffa(q, d, clk, rst) @always(delay(10)) def clkgen(): clk.next = not clk @always(clk.negedge) def stimulus(): d.next = randrange(2) @instance def rstgen(): yield delay(5) rst.next = 1 while True: yield delay(randrange(500, 1000)) rst.next = 0 yield delay(randrange(80, 140)) rst.next = 1 return dffa_inst, clkgen, stimulus, rstgen def simulate(timesteps): tb = traceSignals(test_dffa) sim = Simulation(tb) sim.run(timesteps) sim.quit() simulate(20000) def convert(): q, d, clk, rst = [Signal(bool(0)) for i in range(4)] toVerilog(dffa, q, d, clk, rst) conversion.analyze(dffa, q, d, clk, rst) convert() myhdl-0.11/example/cookbook/dffa/test_dffa.jpg000066400000000000000000001304441347432460400213670ustar00rootroot00000000000000ÿØÿàJFIFHHÿþCreated with The GIMPÿÛC    $.' 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This module computes the sine and cosine of an input angle. The floating point numbers are represented as integers by scaling them up with a factor corresponding to the number of bits after the point. Ports: ----- cos_z0: cosine of the input angle sin_z0: sine of the input angle done: output flag indicating completion of the computation z0: input angle; -pi/2 <= z0 <= pi/2 start: input that starts the computation on a posedge clock: clock input reset: reset input """ # angle input bit width W = len(z0) # angle input z0 represents number between -pi/2 and pi/2 # scaling factor corresponds to the nr of bits after the point M = 2 ** (W-2) # nr of iterations equals nr of significant input bits N = W-1 # calculate X0 An = 1.0 for i in range(N): An *= (sqrt(1 + 2**(-2*i))) # X0 X0 = int(round(M*1/An)) # tuple with elementary angles angles = tuple([int(round(M*atan(2**(-i)))) for i in range(N)]) # iterative cordic processor @instance def processor(): x = intbv(0, min=sin_z0.min, max=sin_z0.max) y = intbv(0, min=sin_z0.min, max=sin_z0.max) z = intbv(0, min=z0.min, max=z0.max) dx = intbv(0, min=sin_z0.min, max=sin_z0.max) dy = intbv(0, min=sin_z0.min, max=sin_z0.max) dz = intbv(0, min=z0.min, max=z0.max) i = intbv(0, min=0, max=N) state = t_State.WAITING while True: yield clock.posedge, reset.posedge if reset: state = t_State.WAITING cos_z0.next = 1 sin_z0.next = 0 done.next = False x[:] = 0 y[:] = 0 z[:] = 0 i[:] = 0 else: if state == t_State.WAITING: if start: x[:] = X0 y[:] = 0 z[:] = z0 i[:] = 0 done.next = False state = t_State.CALCULATING elif state == t_State.CALCULATING: dx[:] = y >> i dy[:] = x >> i dz[:] = angles[int(i)] if (z >= 0): x -= dx y += dy z -= dz else: x += dx y -= dy z += dz if i == N-1: cos_z0.next = x sin_z0.next = y state = t_State.WAITING done.next = True else: i += 1 return processor def SineComputer_v(cos_z0, sin_z0, done, z0, start, clock, reset): toVerilog(SineComputer, cos_z0, sin_z0, done, z0, start, clock, reset) conversion.analyze(SineComputer, cos_z0, sin_z0, done, z0, start, clock, reset) cmd = "cver -q +loadvpi=./myhdl_vpi:vpi_compat_bootstrap " + \ "SineComputer.v tb_SineComputer.v" return Cosimulation(cmd, **locals()) ## cmd = "iverilog SineComputer.v tb_SineComputer.v" ## import os ## os.system(cmd) ## return Cosimulation("vvp -m ./myhdl.vpi a.out", **locals()) myhdl-0.11/example/cookbook/sinecomp/test_SineComputer.py000066400000000000000000000043471347432460400236730ustar00rootroot00000000000000from math import pi, sin, cos, log import random import myhdl from myhdl import * from SineComputer import SineComputer, SineComputer_v def bench(fractionSize, errorMargin, nrTests=100): """ Test bench for SineComputer. fractionSize: number of bits after the point errorMargin: margin for rounding errors on result nrTests: number of tests vectors """ # scaling factor to represent floats as integers M = 2**fractionSize # maximum angle ZMAX = int(round(M*pi/2)) # error margin shorthand D = errorMargin # signals cos_z0 = Signal(intbv(0, min=-D, max=M+D)) sin_z0 = Signal(intbv(0, min=-M-D, max=M+D)) z0 = Signal(intbv(0, min=-ZMAX, max=ZMAX+1)) done = Signal(False) start = Signal(False) clock = Signal(bool(0)) reset = Signal(True) # design under test # dut = SineComputer(cos_z0, sin_z0, done, z0, start, clock, reset) dut = SineComputer_v(cos_z0, sin_z0, done, z0, start, clock, reset) # clock generator @always(delay(10)) def clockgen(): clock.next = not clock # test vector setup testAngles = [-pi/2, -pi/4, 0.0, pi/4, pi/2] testAngles.extend([random.uniform(-pi/2, pi/2) for i in range(nrTests)]) ## testAngles.extend([random.uniform(-0.01, 0.01) for i in range(nrTests)]) ## testAngles.extend([random.uniform(pi/2-0.01, pi/2) for i in range(nrTests)]) ## testAngles.extend([random.uniform(-pi/2, -pi/2+0.01) for i in range(nrTests)]) # actual test @instance def check(): yield clock.negedge reset.next = False for z in testAngles: yield clock.negedge z0.next = int(round(M*z)) start.next = True yield clock.negedge start.next = False yield done.posedge exp_cos_z0 = int(round(cos(z)*M)) exp_sin_z0 = int(round(sin(z)*M)) assert abs(cos_z0 - exp_cos_z0) < D assert abs(sin_z0 - exp_sin_z0) < D raise StopSimulation return dut, clockgen, check def test_bench(): fractionSize = 18 errorMargin = fractionSize tb = bench(fractionSize, errorMargin) sim = Simulation(tb) sim.run() if __name__ == '__main__': test_bench() myhdl-0.11/example/cookbook/stopwatch/000077500000000000000000000000001347432460400200345ustar00rootroot00000000000000myhdl-0.11/example/cookbook/stopwatch/StopWatch.py000066400000000000000000000025621347432460400223270ustar00rootroot00000000000000import myhdl from myhdl import * from TimeCount import TimeCount from bcd2led import bcd2led def StopWatch(tens_led, ones_led, tenths_led, startstop, reset, clock): """ 3 digit stopwatch with seconds and tenths of a second. tens_led: 7 segment led for most significant digit of the seconds ones_led: 7 segment led for least significant digit of the seconds tenths_led: 7 segment led for tenths of a second startstop: input that starts or stops the stopwatch on a posedge reset: reset input clock: 10Hz clock input """ tens, ones, tenths = [Signal(intbv(0)[4:]) for i in range(3)] timecount_inst = TimeCount(tens, ones, tenths, startstop, reset, clock) bcd2led_tens = bcd2led(tens_led, tens, clock) bcd2led_ones = bcd2led(ones_led, ones, clock) bcd2led_tenths = bcd2led(tenths_led, tenths, clock) return timecount_inst, bcd2led_tens, bcd2led_ones, bcd2led_tenths def convert(): tens_led, ones_led, tenths_led = [Signal(intbv(0)[7:]) for i in range(3)] startstop, reset, clock = [Signal(bool(0)) for i in range(3)] toVerilog(StopWatch, tens_led, ones_led, tenths_led, startstop, reset, clock) conversion.analyze(StopWatch, tens_led, ones_led, tenths_led, startstop, reset, clock) convert() myhdl-0.11/example/cookbook/stopwatch/TimeCount.py000066400000000000000000000031511347432460400223150ustar00rootroot00000000000000import myhdl from myhdl import * def TimeCount(tens, ones, tenths, startstop, reset, clock): """ 3 digit time counter in seconds and tenths of a second. tens: most significant digit of the seconds ones: least significant digit of the seconds tenths: tenths of a second startstop: input that starts or stops the counter on posedge reset: reset input clock: 10Hz clock input """ @instance def logic(): seen = False counting = False while True: yield clock.posedge, reset.posedge if reset: tens.next = 0 ones.next = 0 tenths.next = 0 seen = False counting = False else: if startstop and not seen: seen = True counting = not counting elif not startstop: seen = False if counting: if tenths == 9: tenths.next = 0 if ones == 9: ones.next = 0 if tens == 5: tens.next = 0 else: tens.next = tens + 1 else: ones.next = ones + 1 else: tenths.next = tenths + 1 return logic myhdl-0.11/example/cookbook/stopwatch/bcd2led.py000066400000000000000000000012111347432460400217000ustar00rootroot00000000000000import seven_segment import myhdl from myhdl import * code = [None] * 10 for key, val in seven_segment.encoding.items(): if 0 <= key <= 9: code[key] = int(val, 2) code = tuple(code) def bcd2led(led, bcd, clock): """ bcd to seven segment led convertor. led: seven segment led output bcd: bcd input clock: clock input """ @always(clock.posedge) def logic(): led.next = code[int(bcd)] return logic def convert(): led = Signal(intbv(0)[7:]) bcd = Signal(intbv(0)[4:]) clock = Signal(False) toVerilog(bcd2led, led, bcd, clock) toVHDL(bcd2led, led, bcd, clock) convert() myhdl-0.11/example/cookbook/stopwatch/seven_segment.py000066400000000000000000000006101347432460400232450ustar00rootroot00000000000000# 7 segment encoding # 0 # --- # 5 | | 1 # --- <- 6 # 4 | | 2 # --- # 3 encoding = {0: "1000000", 1: "1111001", 2: "0100100", 3: "0110000", 4: "0011001", 5: "0010010", 6: "0000010", 7: "1111000", 8: "0000000", 9: "0010000" } myhdl-0.11/example/cookbook/stopwatch/test_TimeCount.py000066400000000000000000000042411347432460400233550ustar00rootroot00000000000000from random import randrange import myhdl from myhdl import * from TimeCount import TimeCount LOW, HIGH = bool(0), bool(1) MAX_COUNT = 6 * 10 * 10 PERIOD = 10 def bench(): """ Unit test for time counter. """ tens, ones, tenths = [Signal(intbv(0)[4:]) for i in range(3)] startstop, reset, clock = [Signal(LOW) for i in range(3)] dut = TimeCount(tens, ones, tenths, startstop, reset, clock) count = Signal(0) counting = Signal(False) @always(delay(PERIOD//2)) def clkgen(): clock.next = not clock ## @always(reset.posedge) ## def clear(): ## counting.next = False ## count.next = 0 ## @always(startstop.posedge) ## def go(): ## counting.next = not counting @always(startstop.posedge, reset.posedge) def action(): if reset: counting.next = False count.next = 0 else: counting.next = not counting @always(clock.posedge) def counter(): if counting: count.next = (count + 1) % MAX_COUNT @always(clock.negedge) def monitor(): assert ((tens*100) + (ones*10) + tenths) == count @instance def stimulus(): for maxInterval in (100*PERIOD, 2*MAX_COUNT*PERIOD): for sig in (reset, startstop, reset, startstop, startstop, reset, startstop, startstop, startstop, reset, startstop, reset, startstop, startstop, startstop): yield delay(randrange(10*PERIOD, maxInterval)) yield clock.negedge # sync to avoid race condition sig.next = HIGH yield delay(100) sig.next = LOW raise StopSimulation return dut, clkgen, action, counter, monitor, stimulus def test_bench(): sim = Simulation(bench()) sim.run() def convert(): tens, ones, tenths = [Signal(intbv(0)[4:]) for i in range(3)] startstop, reset, clock = [Signal(LOW) for i in range(3)] toVerilog(TimeCount, tens, ones, tenths, startstop, reset, clock) toVHDL(TimeCount, tens, ones, tenths, startstop, reset, clock) convert() myhdl-0.11/example/cookbook/stopwatch/test_bcd2led.py000066400000000000000000000013521347432460400227450ustar00rootroot00000000000000from random import randrange import seven_segment import myhdl from myhdl import * from bcd2led import bcd2led PERIOD = 10 def bench(): led = Signal(intbv(0)[7:]) bcd = Signal(intbv(0)[4:]) clock = Signal(bool(0)) dut = bcd2led(led, bcd, clock) @always(delay(PERIOD//2)) def clkgen(): clock.next = not clock @instance def check(): for i in range(100): bcd.next = randrange(10) yield clock.posedge yield clock.negedge expected = int(seven_segment.encoding[int(bcd)], 2) assert led == expected raise StopSimulation return dut, clkgen, check def test_bench(): sim = Simulation(bench()) sim.run() myhdl-0.11/example/manual/000077500000000000000000000000001347432460400154675ustar00rootroot00000000000000myhdl-0.11/example/manual/ClkDriver.py000066400000000000000000000005231347432460400177260ustar00rootroot00000000000000from myhdl import block, delay, instance @block def ClkDriver(clk, period=20): lowTime = int(period / 2) highTime = period - lowTime @instance def drive_clk(): while True: yield delay(lowTime) clk.next = 1 yield delay(highTime) clk.next = 0 return drive_clk myhdl-0.11/example/manual/FramerCtrl.v000066400000000000000000000031101347432460400177120ustar00rootroot00000000000000// File: FramerCtrl.v // Generated by MyHDL 1.0dev // Date: Mon Feb 15 21:03:52 2016 `timescale 1ns/10ps module FramerCtrl ( SOF, state, syncFlag, clk, reset_n ); // Framing control FSM. // // SOF -- start-of-frame output bit // state -- FramerState output // syncFlag -- sync pattern found indication input // clk -- clock input // reset_n -- active low reset output SOF; reg SOF; output [2:0] state; reg [2:0] state; input syncFlag; input clk; input reset_n; reg [7:0] index; always @(posedge clk, negedge reset_n) begin: FRAMERCTRL_FSM if ((reset_n == 1'b0)) begin SOF <= 0; index <= 0; state <= 3'b001; end else begin index <= ((index + 1) % 8); SOF <= 0; casez (state) 3'b??1: begin index <= 1; if (syncFlag) begin state <= 3'b010; end end 3'b?1?: begin if ((index == 0)) begin if (syncFlag) begin state <= 3'b100; end else begin state <= 3'b001; end end end 3'b1??: begin if ((index == 0)) begin if ((!syncFlag)) begin state <= 3'b001; end end SOF <= ($signed({1'b0, index}) == (8 - 1)); end default: begin $finish; end endcase end end endmodule myhdl-0.11/example/manual/FramerCtrl.vhd000066400000000000000000000041171347432460400202360ustar00rootroot00000000000000-- File: FramerCtrl.vhd -- Generated by MyHDL 1.0dev -- Date: Mon Feb 15 21:03:52 2016 package pck_FramerCtrl is attribute enum_encoding: string; type t_enum_t_State_1 is ( SEARCH, CONFIRM, SYNC ); attribute enum_encoding of t_enum_t_State_1: type is "001 010 100"; end package pck_FramerCtrl; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use std.textio.all; use work.pck_myhdl_10.all; use work.pck_FramerCtrl.all; entity FramerCtrl is port ( SOF: out std_logic; state: inout t_enum_t_State_1; syncFlag: in std_logic; clk: in std_logic; reset_n: in std_logic ); end entity FramerCtrl; -- Framing control FSM. -- -- SOF -- start-of-frame output bit -- state -- FramerState output -- syncFlag -- sync pattern found indication input -- clk -- clock input -- reset_n -- active low reset architecture MyHDL of FramerCtrl is signal index: unsigned(7 downto 0); begin FRAMERCTRL_FSM: process (clk, reset_n) is begin if (reset_n = '0') then SOF <= '0'; index <= to_unsigned(0, 8); state <= SEARCH; elsif rising_edge(clk) then index <= ((index + 1) mod 8); SOF <= '0'; case state is when SEARCH => index <= to_unsigned(1, 8); if bool(syncFlag) then state <= CONFIRM; end if; when CONFIRM => if (index = 0) then if bool(syncFlag) then state <= SYNC; else state <= SEARCH; end if; end if; when SYNC => if (index = 0) then if (not bool(syncFlag)) then state <= SEARCH; end if; end if; SOF <= stdl(signed(resize(index, 9)) = (8 - 1)); when others => assert False report "End of Simulation" severity Failure; end case; end if; end process FRAMERCTRL_FSM; end architecture MyHDL; myhdl-0.11/example/manual/GrayInc.py000066400000000000000000000020321347432460400173720ustar00rootroot00000000000000import myhdl from myhdl import * from bin2gray2 import bin2gray from inc import Inc def GrayInc(graycnt, enable, clock, reset, width): bincnt = Signal(modbv(0)[width:]) inc_1 = Inc(bincnt, enable, clock, reset) bin2gray_1 = bin2gray(B=bincnt, G=graycnt, width=width) return inc_1, bin2gray_1 def GrayIncReg(graycnt, enable, clock, reset, width): graycnt_comb = Signal(modbv(0)[width:]) gray_inc_1 = GrayInc(graycnt_comb, enable, clock, reset, width) @always(clock.posedge) def reg_1(): graycnt.next = graycnt_comb return gray_inc_1, reg_1 def main(): width = 8 graycnt = Signal(modbv(0)[width:]) enable = Signal(bool()) clock = Signal(bool()) reset = ResetSignal(0, active=0, isasync=True) toVerilog(GrayIncReg, graycnt, enable, clock, reset, width) toVHDL(GrayIncReg, graycnt, enable, clock, reset, width) if __name__ == '__main__': main() myhdl-0.11/example/manual/Hello.py000066400000000000000000000002731347432460400171060ustar00rootroot00000000000000from myhdl import block, always, now @block def Hello(clk, to="World!"): @always(clk.posedge) def say_hello(): print("%s Hello %s" % (now(), to)) return say_hello myhdl-0.11/example/manual/Makefile000066400000000000000000000001161347432460400171250ustar00rootroot00000000000000all: python run_all.py clean: - rm *.o *.out *.v *.vhd *.pyc *~ *.vcd* \#* myhdl-0.11/example/manual/bin2gray.py000066400000000000000000000003461347432460400175610ustar00rootroot00000000000000from myhdl import block, always_comb @block def bin2gray(B, G): """ Gray encoder. B -- binary input G -- Gray encoded output """ @always_comb def logic(): G.next = (B>>1) ^ B return logic myhdl-0.11/example/manual/bin2gray.v000066400000000000000000000004541347432460400173760ustar00rootroot00000000000000// File: bin2gray.v // Generated by MyHDL 1.0dev // Date: Mon May 23 16:09:27 2016 `timescale 1ns/10ps module bin2gray ( B, G ); // Gray encoder. // // B -- binary input // G -- Gray encoded output input [7:0] B; output [7:0] G; wire [7:0] G; assign G = ((B >>> 1) ^ B); endmodule myhdl-0.11/example/manual/bin2gray.vhd000066400000000000000000000010001347432460400176760ustar00rootroot00000000000000-- File: bin2gray.vhd -- Generated by MyHDL 1.0dev -- Date: Mon May 23 16:09:27 2016 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use std.textio.all; use work.pck_myhdl_10.all; entity bin2gray is port ( B: in unsigned(7 downto 0); G: out unsigned(7 downto 0) ); end entity bin2gray; -- Gray encoder. -- -- B -- binary input -- G -- Gray encoded output architecture MyHDL of bin2gray is begin G <= (shift_right(B, 1) xor B); end architecture MyHDL; myhdl-0.11/example/manual/bin2gray2.py000066400000000000000000000011341347432460400176370ustar00rootroot00000000000000import myhdl from myhdl import * def bin2gray(B, G, width): """ Gray encoder. B -- input intbv signal, binary encoded G -- output intbv signal, gray encoded width -- bit width """ @always_comb def logic(): Bext = intbv(0)[width+1:] Bext[:] = B for i in range(width): G.next[i] = Bext[i+1] ^ Bext[i] return logic def main(): width = 8 B = Signal(intbv(0)[width:]) G = Signal(intbv(0)[width:]) toVerilog(bin2gray, B, G, width) toVHDL(bin2gray, B, G, width) if __name__ == '__main__': main() myhdl-0.11/example/manual/bin2gray_dummy.py000066400000000000000000000002471347432460400207740ustar00rootroot00000000000000from myhdl import block @block def bin2gray(B, G): # DUMMY PLACEHOLDER """ Gray encoder. B -- binary input G -- Gray encoded output """ pass myhdl-0.11/example/manual/bin2gray_wrong.py000066400000000000000000000003761347432460400210000ustar00rootroot00000000000000from myhdl import block, always_comb @block def bin2gray(B, G): # INCORRECT IMPLEMENTATION """ Gray encoder. B -- binary input G -- Gray encoded output """ @always_comb def logic(): G.next = B[0] return logic myhdl-0.11/example/manual/conv_inc.py000066400000000000000000000006421347432460400176410ustar00rootroot00000000000000from myhdl import toVerilog, toVHDL, Signal, ResetSignal, modbv from inc import inc ACTIVE_LOW, INACTIVE_HIGH = 0, 1 # conversion m = 8 count = Signal(modbv(0)[m:]) enable = Signal(bool(0)) clock = Signal(bool(0)) reset = ResetSignal(0, active=0, isasync=True) inc_inst = inc(count, enable, clock, reset) inc_inst = toVerilog(inc, count, enable, clock, reset) inc_inst = toVHDL(inc, count, enable, clock, reset) myhdl-0.11/example/manual/convert_bin2gray.py000066400000000000000000000004001347432460400213100ustar00rootroot00000000000000from myhdl import Signal, intbv from bin2gray import bin2gray def convert(hdl, width=8): B = Signal(intbv(0)[width:]) G = Signal(intbv(0)[width:]) inst = bin2gray(B, G) inst.convert(hdl=hdl) convert(hdl='Verilog') convert(hdl='VHDL') myhdl-0.11/example/manual/convert_gray_inc_reg.py000066400000000000000000000006511347432460400222330ustar00rootroot00000000000000from myhdl import Signal, ResetSignal, modbv from gray_inc_reg import gray_inc_reg def convert_gray_inc_reg(hdl, width=8): graycnt = Signal(modbv(0)[width:]) enable = Signal(bool()) clock = Signal(bool()) reset = ResetSignal(0, active=0, isasync=True) inst = gray_inc_reg(graycnt, enable, clock, reset, width) inst.convert(hdl) convert_gray_inc_reg(hdl='Verilog') convert_gray_inc_reg(hdl='VHDL') myhdl-0.11/example/manual/convert_inc.py000066400000000000000000000006421347432460400203540ustar00rootroot00000000000000from myhdl import Signal, ResetSignal, modbv from inc import inc def convert_inc(hdl): """Convert inc block to Verilog or VHDL.""" m = 8 count = Signal(modbv(0)[m:]) enable = Signal(bool(0)) clock = Signal(bool(0)) reset = ResetSignal(0, active=0, isasync=True) inc_1 = inc(count, enable, clock, reset) inc_1.convert(hdl=hdl) convert_inc(hdl='Verilog') convert_inc(hdl='VHDL') myhdl-0.11/example/manual/custom.py000066400000000000000000000012221347432460400173500ustar00rootroot00000000000000import myhdl from myhdl import * def inc_comb(nextCount, count, n): @always(count) def logic(): # do nothing here pass nextCount.driven = "wire" return logic inc_comb.verilog_code =\ """ assign $nextCount = ($count + 1) % $n; """ inc_comb.vhdl_code =\ """ $nextCount <= ($count + 1) mod $n; """ def main(): m = 8 n = 2 ** m count = Signal(intbv(0)[m:]) nextCount = Signal(intbv(0)[m:]) toVerilog(inc_comb, nextCount, count, n) toVHDL(inc_comb, nextCount, count, n) if __name__ == '__main__': main() myhdl-0.11/example/manual/fifo.py000066400000000000000000000054751347432460400167770ustar00rootroot00000000000000import sys import traceback import myhdl from myhdl import * class Error(Exception): pass def fifo(dout, din, re, we, empty, full, clk, maxFilling=sys.maxint): """ Synchronous fifo model based on a list. Ports: dout -- data out din -- data in re -- read enable we -- write enable empty -- empty indication flag full -- full indication flag clk -- clock input Optional parameter: maxFilling -- maximum fifo filling, "infinite" by default """ memory = [] @always(clk.posedge) def access(): if we: memory.insert(0, din.val) if re: dout.next = memory.pop() filling = len(memory) empty.next = (filling == 0) full.next = (filling == maxFilling) return access def fifo2(dout, din, re, we, empty, full, clk, maxFilling=sys.maxint): """ Synchronous fifo model based on a list. Ports: dout -- data out din -- data in re -- read enable we -- write enable empty -- empty indication flag full -- full indication flag clk -- clock input Optional parameter: maxFilling -- maximum fifo filling, "infinite" by default """ memory = [] @always(clk.posedge) def access(): if we: memory.insert(0, din.val) if re: try: dout.next = memory.pop() except IndexError: raise Exception("Underflow -- Read from empty fifo") filling = len(memory) empty.next = (filling == 0) full.next = (filling == maxFilling) if filling > maxFilling: raise Exception("Overflow -- Max filling %s exceeded" % maxFilling) return access dout, din, re, we, empty, full, clk = args = [Signal(0) for i in range(7)] dut = fifo2(dout, din, re, we, empty, full, clk, maxFilling=3) def clkGen(): while 1: yield delay(10) clk.next = not clk def read(): yield clk.negedge re.next = 1 yield clk.posedge yield delay(1) re.next = 0 def write(data): yield clk.negedge din.next = data we.next = 1 yield clk.posedge yield delay(1) we.next = 0 def report(): print("dout: %s empty: %s full: %s" % (hex(dout), empty, full)) def test(): yield write(0x55) report() yield write(0x77) report() yield write(0x11) report() yield join(write(0x22), read()) report() yield join(write(0x33), read()) report() yield read() report() yield read() report() yield read() report() yield read() report() yield read() raise StopSimulation sim = Simulation(clkGen(), test(), dut) def main(): try: sim.run() except: traceback.print_exc() if __name__ == '__main__': main() myhdl-0.11/example/manual/fsm.py000066400000000000000000000026501347432460400166310ustar00rootroot00000000000000from myhdl import block, always_seq, Signal, intbv, enum ACTIVE_LOW = 0 FRAME_SIZE = 8 t_state = enum('SEARCH', 'CONFIRM', 'SYNC') @block def framer_ctrl(sof, state, sync_flag, clk, reset_n): """ Framing control FSM. sof -- start-of-frame output bit state -- FramerState output sync_flag -- sync pattern found indication input clk -- clock input reset_n -- active low reset """ index = Signal(intbv(0, min=0, max=FRAME_SIZE)) # position in frame @always_seq(clk.posedge, reset=reset_n) def FSM(): if reset_n == ACTIVE_LOW: sof.next = 0 index.next = 0 state.next = t_state.SEARCH else: index.next = (index + 1) % FRAME_SIZE sof.next = 0 if state == t_state.SEARCH: index.next = 1 if sync_flag: state.next = t_state.CONFIRM elif state == t_state.CONFIRM: if index == 0: if sync_flag: state.next = t_state.SYNC else: state.next = t_state.SEARCH elif state == t_state.SYNC: if index == 0: if not sync_flag: state.next = t_state.SEARCH sof.next = (index == FRAME_SIZE-1) else: raise ValueError("Undefined state") return FSM myhdl-0.11/example/manual/fsm2.py000066400000000000000000000050141347432460400167100ustar00rootroot00000000000000import myhdl from myhdl import * # SEARCH, CONFIRM, SYNC = range(3) ACTIVE_LOW = 0 FRAME_SIZE = 8 t_State = enum('SEARCH', 'CONFIRM', 'SYNC') def FramerCtrl(SOF, state, syncFlag, clk, reset_n): """ Framing control FSM. SOF -- start-of-frame output bit state -- FramerState output syncFlag -- sync pattern found indication input clk -- clock input reset_n -- active low reset """ index = Signal(0) # position in frame @instance def FSM(): while 1: yield posedge(clk), negedge(reset_n) if reset_n == ACTIVE_LOW: SOF.next = 0 index.next = 0 state.next = t_State.SEARCH else: index.next = (index + 1) % FRAME_SIZE SOF.next = 0 if state == t_State.SEARCH: index.next = 1 if syncFlag: state.next = t_State.CONFIRM elif state == t_State.CONFIRM: if index == 0: if syncFlag: state.next = t_State.SYNC else: state.next = t_State.SEARCH elif state == t_State.SYNC: if index == 0: if not syncFlag: state.next = t_State.SEARCH SOF.next = (index == FRAME_SIZE-1) else: raise ValueError("Undefined state") # FSM_1 = FSM() return FSM def testbench(): SOF = Signal(bool(0)) syncFlag = Signal(bool(0)) clk = Signal(bool(0)) reset_n = Signal(bool(1)) state = Signal(t_State.SEARCH) framectrl = FramerCtrl(SOF, state, syncFlag, clk, reset_n) @instance def clkgen(): while 1: yield delay(10) clk.next = not clk @instance def stimulus(): for i in range(3): yield clk.posedge for n in (12, 8, 8, 4): syncFlag.next = 1 yield clk.posedge syncFlag.next = 0 for i in range(n-1): yield clk.posedge raise StopSimulation return framectrl, clkgen, stimulus def main(): traceSignals.name = "fsm2" tb_fsm = traceSignals(testbench) sim = Simulation(tb_fsm) sim.run() if __name__ == '__main__': main() myhdl-0.11/example/manual/fsm3.py000066400000000000000000000034501347432460400167130ustar00rootroot00000000000000import os path = os.path import myhdl from myhdl import * # SEARCH, CONFIRM, SYNC = range(3) ACTIVE_LOW = bool(0) FRAME_SIZE = 8 t_State = enum('SEARCH', 'CONFIRM', 'SYNC', encoding="one_hot") @block def FramerCtrl(SOF, state, syncFlag, clk, reset_n): """ Framing control FSM. SOF -- start-of-frame output bit state -- FramerState output syncFlag -- sync pattern found indication input clk -- clock input reset_n -- active low reset """ index = Signal(intbv(0)[8:]) # position in frame @always(clk.posedge, reset_n.negedge) def FSM(): if reset_n == ACTIVE_LOW: SOF.next = 0 index.next = 0 state.next = t_State.SEARCH else: index.next = (index + 1) % FRAME_SIZE SOF.next = 0 if state == t_State.SEARCH: index.next = 1 if syncFlag: state.next = t_State.CONFIRM elif state == t_State.CONFIRM: if index == 0: if syncFlag: state.next = t_State.SYNC else: state.next = t_State.SEARCH elif state == t_State.SYNC: if index == 0: if not syncFlag: state.next = t_State.SEARCH SOF.next = (index == FRAME_SIZE-1) else: raise ValueError("Undefined state") return FSM def main(): SOF = Signal(bool(0)) syncFlag = Signal(bool(0)) clk = Signal(bool(0)) reset_n = Signal(bool(1)) state = Signal(t_State.SEARCH) toVerilog(FramerCtrl(SOF, state, syncFlag, clk, reset_n)) toVHDL(FramerCtrl(SOF, state, syncFlag, clk, reset_n)) if __name__ == '__main__': main() myhdl-0.11/example/manual/gray_inc.py000066400000000000000000000005071347432460400176360ustar00rootroot00000000000000from myhdl import block, Signal, modbv from bin2gray import bin2gray from inc import inc @block def gray_inc(graycnt, enable, clock, reset, width): bincnt = Signal(modbv(0)[width:]) inc_0 = inc(bincnt, enable, clock, reset) bin2gray_0 = bin2gray(B=bincnt, G=graycnt) return inc_0, bin2gray_0 myhdl-0.11/example/manual/gray_inc_reg.py000066400000000000000000000006231347432460400204720ustar00rootroot00000000000000from myhdl import block, always_seq, Signal, modbv from gray_inc import gray_inc @block def gray_inc_reg(graycnt, enable, clock, reset, width): graycnt_comb = Signal(modbv(0)[width:]) gray_inc_0 = gray_inc(graycnt_comb, enable, clock, reset, width) @always_seq(clock.posedge, reset=reset) def reg_0(): graycnt.next = graycnt_comb return gray_inc_0, reg_0 myhdl-0.11/example/manual/gray_inc_reg.v000066400000000000000000000015331347432460400203100ustar00rootroot00000000000000// File: gray_inc_reg.v // Generated by MyHDL 1.0dev // Date: Thu Jun 23 19:06:43 2016 `timescale 1ns/10ps module gray_inc_reg ( graycnt, enable, clock, reset ); output [7:0] graycnt; reg [7:0] graycnt; input enable; input clock; input reset; wire [7:0] graycnt_comb; reg [7:0] gray_inc_1_bincnt; always @(posedge clock, negedge reset) begin: GRAY_INC_REG_GRAY_INC_1_INC_1_SEQ if (reset == 0) begin gray_inc_1_bincnt <= 0; end else begin if (enable) begin gray_inc_1_bincnt <= (gray_inc_1_bincnt + 1); end end end assign graycnt_comb = ((gray_inc_1_bincnt >>> 1) ^ gray_inc_1_bincnt); always @(posedge clock, negedge reset) begin: GRAY_INC_REG_REG_0 if (reset == 0) begin graycnt <= 0; end else begin graycnt <= graycnt_comb; end end endmodule myhdl-0.11/example/manual/gray_inc_reg.vhd000066400000000000000000000023001347432460400206150ustar00rootroot00000000000000-- File: gray_inc_reg.vhd -- Generated by MyHDL 1.0dev -- Date: Thu Jun 23 19:06:43 2016 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use std.textio.all; use work.pck_myhdl_10.all; entity gray_inc_reg is port ( graycnt: out unsigned(7 downto 0); enable: in std_logic; clock: in std_logic; reset: in std_logic ); end entity gray_inc_reg; architecture MyHDL of gray_inc_reg is signal graycnt_comb: unsigned(7 downto 0); signal gray_inc_1_bincnt: unsigned(7 downto 0); begin GRAY_INC_REG_GRAY_INC_1_INC_1_SEQ: process (clock, reset) is begin if (reset = '0') then gray_inc_1_bincnt <= to_unsigned(0, 8); elsif rising_edge(clock) then if bool(enable) then gray_inc_1_bincnt <= (gray_inc_1_bincnt + 1); end if; end if; end process GRAY_INC_REG_GRAY_INC_1_INC_1_SEQ; graycnt_comb <= (shift_right(gray_inc_1_bincnt, 1) xor gray_inc_1_bincnt); GRAY_INC_REG_REG_0: process (clock, reset) is begin if (reset = '0') then graycnt <= to_unsigned(0, 8); elsif rising_edge(clock) then graycnt <= graycnt_comb; end if; end process GRAY_INC_REG_REG_0; end architecture MyHDL; myhdl-0.11/example/manual/greetings.py000066400000000000000000000010101347432460400200200ustar00rootroot00000000000000from myhdl import block, Signal from ClkDriver import ClkDriver from Hello import Hello @block def Greetings(): clk1 = Signal(0) clk2 = Signal(0) clkdriver_1 = ClkDriver(clk1) # positional and default association clkdriver_2 = ClkDriver(clk=clk2, period=19) # named association hello_1 = Hello(clk=clk1) # named and default association hello_2 = Hello(to="MyHDL", clk=clk2) # named association return clkdriver_1, clkdriver_2, hello_1, hello_2 inst = Greetings() inst.run_sim(50) myhdl-0.11/example/manual/hec.py000066400000000000000000000012451347432460400166020ustar00rootroot00000000000000from myhdl import intbv, concat COSET = 0x55 def calculateHec(header): """ Return hec for an ATM header, represented as an intbv. The hec polynomial is 1 + x + x**2 + x**8. """ hec = intbv(0) for bit in header[32:]: hec[8:] = concat(hec[7:2], bit ^ hec[1] ^ hec[7], bit ^ hec[0] ^ hec[7], bit ^ hec[7] ) return hec ^ COSET headers = ( 0x00000000, 0x01234567, 0xbac6f4ca ) def main(): for header in headers: print(hex(calculateHec(intbv(header)))) if __name__ == '__main__': main() myhdl-0.11/example/manual/hello1.py000066400000000000000000000003311347432460400172220ustar00rootroot00000000000000from myhdl import block, delay, always, now @block def HelloWorld(): @always(delay(10)) def say_hello(): print("%s Hello World!" % now()) return say_hello inst = HelloWorld() inst.run_sim(30) myhdl-0.11/example/manual/hello2.py000066400000000000000000000005131347432460400172250ustar00rootroot00000000000000from myhdl import block, Signal, delay, always, now @block def HelloWorld(): clk = Signal(0) @always(delay(10)) def drive_clk(): clk.next = not clk @always(clk.posedge) def say_hello(): print("%s Hello World!" % now()) return drive_clk, say_hello inst = HelloWorld() inst.run_sim(50) myhdl-0.11/example/manual/inc.py000066400000000000000000000006031347432460400166110ustar00rootroot00000000000000from myhdl import block, always_seq @block def inc(count, enable, clock, reset): """ Incrementer with enable. count -- output enable -- control input, increment when 1 clock -- clock input reset -- asynchronous reset input """ @always_seq(clock.posedge, reset=reset) def seq(): if enable: count.next = count + 1 return seq myhdl-0.11/example/manual/inc.v000066400000000000000000000011511347432460400164250ustar00rootroot00000000000000// File: inc.v // Generated by MyHDL 1.0dev // Date: Sun May 22 18:46:37 2016 `timescale 1ns/10ps module inc ( count, enable, clock, reset ); // Incrementer with enable. // // count -- output // enable -- control input, increment when 1 // clock -- clock input // reset -- asynchronous reset input output [7:0] count; reg [7:0] count; input enable; input clock; input reset; always @(posedge clock, negedge reset) begin: INC_SEQ if (reset == 0) begin count <= 0; end else begin if (enable) begin count <= (count + 1); end end end endmodule myhdl-0.11/example/manual/inc.vhd000066400000000000000000000015241347432460400167450ustar00rootroot00000000000000-- File: inc.vhd -- Generated by MyHDL 1.0dev -- Date: Sun May 22 18:46:37 2016 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use std.textio.all; use work.pck_myhdl_10.all; entity inc is port ( count: inout unsigned(7 downto 0); enable: in std_logic; clock: in std_logic; reset: in std_logic ); end entity inc; -- Incrementer with enable. -- -- count -- output -- enable -- control input, increment when 1 -- clock -- clock input -- reset -- asynchronous reset input architecture MyHDL of inc is begin INC_SEQ: process (clock, reset) is begin if (reset = '0') then count <= to_unsigned(0, 8); elsif rising_edge(clock) then if bool(enable) then count <= (count + 1); end if; end if; end process INC_SEQ; end architecture MyHDL; myhdl-0.11/example/manual/inc_comb.v000066400000000000000000000004231347432460400174260ustar00rootroot00000000000000// File: inc_comb.v // Generated by MyHDL 0.8dev // Date: Fri Dec 21 15:02:39 2012 `timescale 1ns/10ps module inc_comb ( nextCount, count ); output [7:0] nextCount; wire [7:0] nextCount; input [7:0] count; assign nextCount = (count + 1) % 256; endmodule myhdl-0.11/example/manual/inc_comb.vhd000066400000000000000000000007071347432460400177470ustar00rootroot00000000000000-- File: inc_comb.vhd -- Generated by MyHDL 0.8dev -- Date: Fri Dec 21 15:02:39 2012 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use std.textio.all; use work.pck_myhdl_08.all; entity inc_comb is port ( nextCount: out unsigned(7 downto 0); count: in unsigned(7 downto 0) ); end entity inc_comb; architecture MyHDL of inc_comb is begin nextCount <= (count + 1) mod 256; end architecture MyHDL; myhdl-0.11/example/manual/mux.py000066400000000000000000000005301347432460400166500ustar00rootroot00000000000000from myhdl import block, always_comb, Signal @block def mux(z, a, b, sel): """ Multiplexer. z -- mux output a, b -- data inputs sel -- control input: select a if asserted, otherwise b """ @always_comb def comb(): if sel == 1: z.next = a else: z.next = b return comb myhdl-0.11/example/manual/mux2.py000066400000000000000000000014461347432460400167410ustar00rootroot00000000000000from myhdl import Signal, Simulation, delay, always_comb def Mux(z, a, b, sel): """ Multiplexer. z -- mux output a, b -- data inputs sel -- control input: select a if asserted, otherwise b """ @always_comb def muxLogic(): if sel == 1: z.next = a else: z.next = b return muxLogic from random import randrange z, a, b, sel = [Signal(0) for i in range(4)] mux_1 = Mux(z, a, b, sel) def test(): print "z a b sel" for i in range(8): a.next, b.next, sel.next = randrange(8), randrange(8), randrange(2) yield delay(10) print "%s %s %s %s" % (z, a, b, sel) test_1 = test() def main(): sim = Simulation(mux_1, test_1) sim.run() if __name__ == '__main__': main() myhdl-0.11/example/manual/next_gray_code.py000066400000000000000000000003001347432460400210240ustar00rootroot00000000000000def nextLn(Ln): """ Return Gray code Ln+1, given Ln. """ Ln0 = ['0' + codeword for codeword in Ln] Ln1 = ['1' + codeword for codeword in Ln] Ln1.reverse() return Ln0 + Ln1 myhdl-0.11/example/manual/pck_myhdl_07.vhd000066400000000000000000000066241347432460400204620ustar00rootroot00000000000000-- File: pck_myhdl_07.vhd -- Generated by MyHDL 0.7 -- Date: Sun Dec 19 16:52:33 2010 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package pck_myhdl_07 is attribute enum_encoding: string; function to_std_logic (arg: boolean) return std_logic; function to_std_logic (arg: integer) return std_logic; function to_unsigned (arg: boolean; size: natural) return unsigned; function to_signed (arg: boolean; size: natural) return signed; function to_integer(arg: boolean) return integer; function to_integer(arg: std_logic) return integer; function to_unsigned (arg: std_logic; size: natural) return unsigned; function to_signed (arg: std_logic; size: natural) return signed; function to_boolean (arg: std_logic) return boolean; function to_boolean (arg: unsigned) return boolean; function to_boolean (arg: signed) return boolean; function to_boolean (arg: integer) return boolean; function "-" (arg: unsigned) return signed; end pck_myhdl_07; package body pck_myhdl_07 is function to_std_logic (arg: boolean) return std_logic is begin if arg then return '1'; else return '0'; end if; end function to_std_logic; function to_std_logic (arg: integer) return std_logic is begin if arg /= 0 then return '1'; else return '0'; end if; end function to_std_logic; function to_unsigned (arg: boolean; size: natural) return unsigned is variable res: unsigned(size-1 downto 0) := (others => '0'); begin if arg then res(0):= '1'; end if; return res; end function to_unsigned; function to_signed (arg: boolean; size: natural) return signed is variable res: signed(size-1 downto 0) := (others => '0'); begin if arg then res(0) := '1'; end if; return res; end function to_signed; function to_integer(arg: boolean) return integer is begin if arg then return 1; else return 0; end if; end function to_integer; function to_integer(arg: std_logic) return integer is begin if arg = '1' then return 1; else return 0; end if; end function to_integer; function to_unsigned (arg: std_logic; size: natural) return unsigned is variable res: unsigned(size-1 downto 0) := (others => '0'); begin res(0):= arg; return res; end function to_unsigned; function to_signed (arg: std_logic; size: natural) return signed is variable res: signed(size-1 downto 0) := (others => '0'); begin res(0) := arg; return res; end function to_signed; function to_boolean (arg: std_logic) return boolean is begin return arg = '1'; end function to_boolean; function to_boolean (arg: unsigned) return boolean is begin return arg /= 0; end function to_boolean; function to_boolean (arg: signed) return boolean is begin return arg /= 0; end function to_boolean; function to_boolean (arg: integer) return boolean is begin return arg /= 0; end function to_boolean; function "-" (arg: unsigned) return signed is begin return - signed(resize(arg, arg'length+1)); end function "-"; end pck_myhdl_07; myhdl-0.11/example/manual/pck_myhdl_10.vhd000066400000000000000000000103721347432460400204470ustar00rootroot00000000000000-- File: pck_myhdl_10.vhd -- Generated by MyHDL 1.0dev -- Date: Thu Jun 23 19:06:43 2016 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package pck_myhdl_10 is attribute enum_encoding: string; function stdl (arg: boolean) return std_logic; function stdl (arg: integer) return std_logic; function to_unsigned (arg: boolean; size: natural) return unsigned; function to_signed (arg: boolean; size: natural) return signed; function to_integer(arg: boolean) return integer; function to_integer(arg: std_logic) return integer; function to_unsigned (arg: std_logic; size: natural) return unsigned; function to_signed (arg: std_logic; size: natural) return signed; function bool (arg: std_logic) return boolean; function bool (arg: unsigned) return boolean; function bool (arg: signed) return boolean; function bool (arg: integer) return boolean; function "-" (arg: unsigned) return signed; function tern_op(cond: boolean; if_true: std_logic; if_false: std_logic) return std_logic; function tern_op(cond: boolean; if_true: unsigned; if_false: unsigned) return unsigned; function tern_op(cond: boolean; if_true: signed; if_false: signed) return signed; end pck_myhdl_10; package body pck_myhdl_10 is function stdl (arg: boolean) return std_logic is begin if arg then return '1'; else return '0'; end if; end function stdl; function stdl (arg: integer) return std_logic is begin if arg /= 0 then return '1'; else return '0'; end if; end function stdl; function to_unsigned (arg: boolean; size: natural) return unsigned is variable res: unsigned(size-1 downto 0) := (others => '0'); begin if arg then res(0):= '1'; end if; return res; end function to_unsigned; function to_signed (arg: boolean; size: natural) return signed is variable res: signed(size-1 downto 0) := (others => '0'); begin if arg then res(0) := '1'; end if; return res; end function to_signed; function to_integer(arg: boolean) return integer is begin if arg then return 1; else return 0; end if; end function to_integer; function to_integer(arg: std_logic) return integer is begin if arg = '1' then return 1; else return 0; end if; end function to_integer; function to_unsigned (arg: std_logic; size: natural) return unsigned is variable res: unsigned(size-1 downto 0) := (others => '0'); begin res(0):= arg; return res; end function to_unsigned; function to_signed (arg: std_logic; size: natural) return signed is variable res: signed(size-1 downto 0) := (others => '0'); begin res(0) := arg; return res; end function to_signed; function bool (arg: std_logic) return boolean is begin return arg = '1'; end function bool; function bool (arg: unsigned) return boolean is begin return arg /= 0; end function bool; function bool (arg: signed) return boolean is begin return arg /= 0; end function bool; function bool (arg: integer) return boolean is begin return arg /= 0; end function bool; function "-" (arg: unsigned) return signed is begin return - signed(resize(arg, arg'length+1)); end function "-"; function tern_op(cond: boolean; if_true: std_logic; if_false: std_logic) return std_logic is begin if cond then return if_true; else return if_false; end if; end function tern_op; function tern_op(cond: boolean; if_true: unsigned; if_false: unsigned) return unsigned is begin if cond then return if_true; else return if_false; end if; end function tern_op; function tern_op(cond: boolean; if_true: signed; if_false: signed) return signed is begin if cond then return if_true; else return if_false; end if; end function tern_op; end pck_myhdl_10; myhdl-0.11/example/manual/queue.py000066400000000000000000000017201347432460400171650ustar00rootroot00000000000000from __future__ import generators import myhdl from myhdl import * def trigger(event): event.next = not event class queue: def __init__(self): self.l = [] self.sync = Signal(0) self.item = None def put(self,item): # non time-consuming method self.l.append(item) trigger(self.sync) def get(self): # time-consuming method if not self.l: yield self.sync self.item = self.l.pop(0) q = queue() def Producer(q): yield delay(120) for i in range(5): print "%s: PUT item %s" % (now(), i) q.put(i) yield delay(max(5, 45 - 10*i)) def Consumer(q): yield delay(100) while 1: print "%s: TRY to get item" % now() yield q.get() print "%s: GOT item %s" % (now(), q.item) yield delay(30) def main(): P = Producer(q) C = Consumer(q) sim = Simulation(P, C) sim.run() if __name__ == '__main__': main() myhdl-0.11/example/manual/ram.py000066400000000000000000000012641347432460400166230ustar00rootroot00000000000000import myhdl from myhdl import * def ram(dout, din, addr, we, clk, depth=128): """ Ram model """ mem = [Signal(intbv(0)[8:]) for i in range(depth)] @always(clk.posedge) def write(): if we: mem[addr].next = din @always_comb def read(): dout.next = mem[addr] return write, read dout = Signal(intbv(0)[8:]) dout_v = Signal(intbv(0)[8:]) din = Signal(intbv(0)[8:]) addr = Signal(intbv(0)[7:]) we = Signal(bool(0)) clk = Signal(bool(0)) def main(): toVerilog.name = 'ram_1' toVerilog(ram, dout, din, addr, we, clk) toVHDL(ram, dout, din, addr, we, clk) if __name__ == '__main__': main() myhdl-0.11/example/manual/ram.vhd000066400000000000000000000014411347432460400167510ustar00rootroot00000000000000-- File: ram.vhd -- Generated by MyHDL 0.8dev -- Date: Fri Dec 21 15:02:39 2012 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use std.textio.all; use work.pck_myhdl_08.all; entity ram is port ( dout: out unsigned(7 downto 0); din: in unsigned(7 downto 0); addr: in unsigned(6 downto 0); we: in std_logic; clk: in std_logic ); end entity ram; -- Ram model architecture MyHDL of ram is type t_array_mem is array(0 to 128-1) of unsigned(7 downto 0); signal mem: t_array_mem; begin RAM_WRITE: process (clk) is begin if rising_edge(clk) then if bool(we) then mem(to_integer(addr)) <= din; end if; end if; end process RAM_WRITE; dout <= mem(to_integer(addr)); end architecture MyHDL; myhdl-0.11/example/manual/ram_1.v000066400000000000000000000006701347432460400166600ustar00rootroot00000000000000// File: ram_1.v // Generated by MyHDL 0.8dev // Date: Fri Dec 21 15:02:39 2012 `timescale 1ns/10ps module ram_1 ( dout, din, addr, we, clk ); // Ram model output [7:0] dout; wire [7:0] dout; input [7:0] din; input [6:0] addr; input we; input clk; reg [7:0] mem [0:128-1]; always @(posedge clk) begin: RAM_1_WRITE if (we) begin mem[addr] <= din; end end assign dout = mem[addr]; endmodule myhdl-0.11/example/manual/rom.py000066400000000000000000000006411347432460400166370ustar00rootroot00000000000000import myhdl from myhdl import * CONTENT = (17, 134, 52, 9) def rom(dout, addr, CONTENT): """ ROM model """ @always_comb def read(): dout.next = CONTENT[int(addr)] return read dout = Signal(intbv(0)[8:]) addr = Signal(intbv(0)[4:]) CONTENT = (17, 134, 52, 9) def main(): toVerilog(rom, dout, addr, CONTENT) toVHDL(rom, dout, addr, CONTENT) if __name__ == '__main__': main() myhdl-0.11/example/manual/rom.v000066400000000000000000000005721347432460400164570ustar00rootroot00000000000000// File: rom.v // Generated by MyHDL 0.8dev // Date: Fri Dec 21 15:02:39 2012 `timescale 1ns/10ps module rom ( dout, addr ); // ROM model output [7:0] dout; reg [7:0] dout; input [3:0] addr; always @(addr) begin: ROM_READ case (addr) 0: dout = 17; 1: dout = 134; 2: dout = 52; default: dout = 9; endcase end endmodule myhdl-0.11/example/manual/rom.vhd000066400000000000000000000012271347432460400167710ustar00rootroot00000000000000-- File: rom.vhd -- Generated by MyHDL 0.8dev -- Date: Fri Dec 21 15:02:39 2012 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use std.textio.all; use work.pck_myhdl_08.all; entity rom is port ( dout: out unsigned(7 downto 0); addr: in unsigned(3 downto 0) ); end entity rom; -- ROM model architecture MyHDL of rom is begin ROM_READ: process (addr) is begin case to_integer(addr) is when 0 => dout <= "00010001"; when 1 => dout <= "10000110"; when 2 => dout <= "00110100"; when others => dout <= "00001001"; end case; end process ROM_READ; end architecture MyHDL; myhdl-0.11/example/manual/rs232.py000066400000000000000000000053731347432460400167240ustar00rootroot00000000000000from __future__ import generators import sys from random import randrange from myhdl import Signal, Simulation, StopSimulation, \ intbv, delay, negedge, join T_9600 = int(1e9 / 9600) T_10200 = int(1e9 / 10200) def rs232_tx(tx, data, duration=T_9600): """ Simple rs232 transmitter procedure. tx -- serial output data data -- input data byte to be transmitted duration -- transmit bit duration """ print "-- Transmitting %s --" % hex(data) print "TX: start bit" tx.next = 0 yield delay(duration) for i in range(8): print "TX: %s" % data[i] tx.next = data[i] yield delay(duration) print "TX: stop bit" tx.next = 1 yield delay(duration) MAX_TIMEOUT = sys.maxint def rs232_rx(rx, data, duration=T_9600, timeout=MAX_TIMEOUT): """ Simple rs232 receiver procedure. rx -- serial input data data -- data received duration -- receive bit duration """ # wait on start bit until timeout yield rx.negedge, delay(timeout) if rx == 1: raise StopSimulation, "RX time out error" # sample in the middle of the bit duration yield delay(duration // 2) print "RX: start bit" for i in range(8): yield delay(duration) print "RX: %s" % rx data[i] = rx yield delay(duration) print "RX: stop bit" print "-- Received %s --" % hex(data) testvals = (0xc5, 0x3a, 0x4b) def stimulus(): tx = Signal(1) for val in testvals: txData = intbv(val) yield rs232_tx(tx, txData) def test(): tx = Signal(1) rx = tx rxData = intbv(0) for val in testvals: txData = intbv(val) yield rs232_rx(rx, rxData), rs232_tx(tx, txData) def testTimeout(): tx = Signal(1) rx = Signal(1) rxData = intbv(0) for val in testvals: txData = intbv(val) yield rs232_rx(rx, rxData, timeout=4*T_9600-1), rs232_tx(tx, txData) def testNoJoin(): tx = Signal(1) rx = tx rxData = intbv(0) for val in testvals: txData = intbv(val) yield rs232_rx(rx, rxData), rs232_tx(tx, txData, duration=T_10200) def testJoin(): tx = Signal(1) rx = tx rxData = intbv(0) for val in testvals: txData = intbv(val) yield join(rs232_rx(rx, rxData), rs232_tx(tx, txData, duration=T_10200)) def main(): print "\n\n## stimulus ##\n" Simulation(stimulus()).run() print "\n\n## test ##\n" Simulation(test()).run() print "\n\n## testTimeout ##\n" Simulation(testTimeout()).run() print "\n\n## testNoJoin ##\n" Simulation(testNoJoin()).run() print "\n\n## testJoin ##\n" Simulation(testJoin()).run() if __name__ == '__main__': main() myhdl-0.11/example/manual/run_all.py000066400000000000000000000012031347432460400174710ustar00rootroot00000000000000modules = ('hello1', 'hello2', 'greetings', 'bin2gray', 'bin2gray2', 'GrayInc', 'hec', 'rs232', 'mux', 'mux2', 'inc', 'fsm', 'fsm2', 'fsm3', 'queue', 'sparseMemory', 'fifo', 'rom', 'ram', 'custom', ) for n in modules: m = __import__(n) info = "* %s.py *" % m.__name__ print() print('*' * len(info)) print("* %s.py *" % m.__name__) print('*' * len(info)) if hasattr(m, 'main'): m.main() myhdl-0.11/example/manual/shadow.py000066400000000000000000000022111347432460400173220ustar00rootroot00000000000000import myhdl from myhdl import * from random import randrange def arbiter(grant_vector, request_vector): @always_comb def logic(): grant_vector.next = 0 for i in range(len(request_vector)): if request_vector[i] == 1: grant_vector.next[i] = 1 break return logic def check(): M = 8 request_list = [Signal(bool()) for i in range(M)] request_vector = ConcatSignal(*reversed(request_list)) grant_vector = Signal(intbv(0)[M:]) grant_list = [grant_vector(i) for i in range(M)] arb = arbiter(grant_vector, request_vector) @instance def stimulus(): for i in range(100): for j in range(M): request_list[j].next = randrange(2) yield delay(10) if 1 in request_list: assert grant_list.index(1) == request_list.index(1) assert grant_list.count(0) == M-1 #print bin(grant_vector, 8), bin(request_vector, 8) raise StopSimulation() return arb, stimulus sim = Simulation(check()) sim.run() myhdl-0.11/example/manual/sparseMemory.py000066400000000000000000000043741347432460400205370ustar00rootroot00000000000000import traceback import myhdl from myhdl import * class Error(Exception): pass def sparseMemory(dout, din, addr, we, en, clk): """ Sparse memory model based on a dictionary. Ports: dout -- data out din -- data in addr -- address bus we -- write enable: write if 1, read otherwise en -- interface enable: enabled if 1 clk -- clock input """ memory = {} @always(clk.posedge) def access(): if en: if we: memory[addr.val] = din.val else: dout.next = memory[addr.val] return access def sparseMemory2(dout, din, addr, we, en, clk): """ Sparse memory model based on a dictionary. Ports: dout -- data out din -- data in addr -- address bus we -- write enable: write if 1, read otherwise en -- interface enable: enabled if 1 clk -- clock input """ memory = {} @always(clk.posedge) def access(): if en: if we: memory[addr.val] = din.val else: try: dout.next = memory[addr.val] except KeyError: raise Error, "Uninitialized address %s" % hex(addr) return access dout, din, addr, we, en, clk = args = [Signal(0) for i in range(6)] dut = sparseMemory2(*args) def clkGen(): while 1: yield delay(10) clk.next = not clk def read(address): yield clk.negedge en.next = 1 we.next = 0 addr.next = address yield clk.posedge yield delay(1) en.next = 0 we.next = 0 def write(data, address): yield clk.negedge addr.next = address din.next = data en.next = 1 we.next = 1 yield clk.posedge en.next = 0 we.next = 0 def test(): yield write(0x55, 0x55) yield write(0x77, 0x77) yield write(0x111, 0x111) yield read(0x77) print hex(dout) yield read(0x55) print hex(dout) yield read(0x33) raise StopSimulation sim = Simulation(clkGen(), test(), dut) def main(): try: sim.run() except: traceback.print_exc() if __name__ == '__main__': main() myhdl-0.11/example/manual/test_bin2gray.py000066400000000000000000000011231347432460400206120ustar00rootroot00000000000000from myhdl import block, Signal, intbv, delay, instance, bin from bin2gray import bin2gray @block def testbench(width): B = Signal(intbv(0)[width:]) G = Signal(intbv(0)[width:]) dut = bin2gray(B, G) dut.config_sim(trace=True) @instance def stimulus(): for i in range(2**width): B.next = intbv(i) yield delay(10) print("B: " + bin(B, width) + "| G: " + bin(G, width)) return dut, stimulus def main(): tb = testbench(width=3) # tb.config_sim(trace=True) tb.run_sim() if __name__ == '__main__': main() myhdl-0.11/example/manual/test_fsm.py000066400000000000000000000016171347432460400176720ustar00rootroot00000000000000import myhdl from myhdl import block, always, instance, Signal, ResetSignal, delay, StopSimulation from fsm import framer_ctrl, t_state ACTIVE_LOW = 0 @block def testbench(): sof = Signal(bool(0)) sync_flag = Signal(bool(0)) clk = Signal(bool(0)) reset_n = ResetSignal(1, active=ACTIVE_LOW, isasync=True) state = Signal(t_state.SEARCH) frame_ctrl_0 = framer_ctrl(sof, state, sync_flag, clk, reset_n) @always(delay(10)) def clkgen(): clk.next = not clk @instance def stimulus(): for i in range(3): yield clk.negedge for n in (12, 8, 8, 4): sync_flag.next = 1 yield clk.negedge sync_flag.next = 0 for i in range(n-1): yield clk.negedge raise StopSimulation() return frame_ctrl_0, clkgen, stimulus tb = testbench() tb.config_sim(trace=True) tb.run_sim() myhdl-0.11/example/manual/test_gray_original.py000066400000000000000000000016331347432460400217310ustar00rootroot00000000000000import unittest from myhdl import Simulation, Signal, delay, intbv, bin from bin2gray import bin2gray from next_gray_code import nextLn MAX_WIDTH = 11 class TestOriginalGrayCode(unittest.TestCase): def testOriginalGrayCode(self): """Check that the code is an original Gray code.""" Rn = [] def stimulus(B, G, n): for i in range(2**n): B.next = intbv(i) yield delay(10) Rn.append(bin(G, width=n)) Ln = ['0', '1'] # n == 1 for w in range(2, MAX_WIDTH): Ln = nextLn(Ln) del Rn[:] B = Signal(intbv(0)[w:]) G = Signal(intbv(0)[w:]) dut = bin2gray(B, G) stim = stimulus(B, G, w) sim = Simulation(dut, stim) sim.run(quiet=1) self.assertEqual(Ln, Rn) if __name__ == '__main__': unittest.main(verbosity=2) myhdl-0.11/example/manual/test_gray_properties.py000066400000000000000000000027571347432460400223310ustar00rootroot00000000000000import unittest from myhdl import Simulation, Signal, delay, intbv, bin from bin2gray import bin2gray MAX_WIDTH = 11 class TestGrayCodeProperties(unittest.TestCase): def testSingleBitChange(self): """Check that only one bit changes in successive codewords.""" def test(B, G): w = len(B) G_Z = Signal(intbv(0)[w:]) B.next = intbv(0) yield delay(10) for i in range(1, 2**w): G_Z.next = G B.next = intbv(i) yield delay(10) diffcode = bin(G ^ G_Z) self.assertEqual(diffcode.count('1'), 1) self.runTests(test) def testUniqueCodeWords(self): """Check that all codewords occur exactly once.""" def test(B, G): w = len(B) actual = [] for i in range(2**w): B.next = intbv(i) yield delay(10) actual.append(int(G)) actual.sort() expected = list(range(2**w)) self.assertEqual(actual, expected) self.runTests(test) def runTests(self, test): """Helper method to run the actual tests.""" for w in range(1, MAX_WIDTH): B = Signal(intbv(0)[w:]) G = Signal(intbv(0)[w:]) dut = bin2gray(B, G) check = test(B, G) sim = Simulation(dut, check) sim.run(quiet=1) if __name__ == '__main__': unittest.main(verbosity=2) myhdl-0.11/example/manual/test_inc.py000066400000000000000000000021321347432460400176470ustar00rootroot00000000000000import random from myhdl import block, always, instance, Signal, \ ResetSignal, modbv, delay, StopSimulation from inc import inc random.seed(1) randrange = random.randrange ACTIVE_LOW, INACTIVE_HIGH = 0, 1 @block def testbench(): m = 3 count = Signal(modbv(0)[m:]) enable = Signal(bool(0)) clock = Signal(bool(0)) reset = ResetSignal(0, active=0, isasync=True) inc_1 = inc(count, enable, clock, reset) HALF_PERIOD = delay(10) @always(HALF_PERIOD) def clockGen(): clock.next = not clock @instance def stimulus(): reset.next = ACTIVE_LOW yield clock.negedge reset.next = INACTIVE_HIGH for i in range(16): enable.next = min(1, randrange(3)) yield clock.negedge raise StopSimulation() @instance def monitor(): print("enable count") yield reset.posedge while 1: yield clock.posedge yield delay(1) print(" %s %s" % (int(enable), count)) return clockGen, stimulus, inc_1, monitor tb = testbench() tb.run_sim() myhdl-0.11/example/manual/test_mux.py000066400000000000000000000010511347432460400177060ustar00rootroot00000000000000import random from myhdl import block, instance, Signal, intbv, delay from mux import mux random.seed(5) randrange = random.randrange @block def test_mux(): z, a, b, sel = [Signal(intbv(0)) for i in range(4)] mux_1 = mux(z, a, b, sel) @instance def stimulus(): print("z a b sel") for i in range(12): a.next, b.next, sel.next = randrange(8), randrange(8), randrange(2) yield delay(10) print("%s %s %s %s" % (z, a, b, sel)) return mux_1, stimulus tb = test_mux() tb.run_sim() myhdl-0.11/example/rs232/000077500000000000000000000000001347432460400150655ustar00rootroot00000000000000myhdl-0.11/example/rs232/README.txt000066400000000000000000000010121347432460400165550ustar00rootroot00000000000000The examples in this directory are based on code from the book "Writing Testbenches", 1st edition, by Janick Bergeron. Files rs232_rx.py and rs232_tx.py contain my translations into myhdl/Python of Sample 5-48 and 5-57 in the book. The copyright of the original Samples is held by Janick Bergeron. I added a test bench, test_rs232.py, to verify the translation into myhdl/Python, and to demonstrate some possibilities of myhdl and the Python unit test framework. Run the test bench as follows: python test_rs232.py myhdl-0.11/example/rs232/rs232_rx.py000066400000000000000000000015231347432460400170240ustar00rootroot00000000000000import myhdl from myhdl import * from rs232_util import sec, parity, ParityError, StopBitError def rs232_rx(rx, actual, cfg): """ rs232 receiver. rx -- serial input data actual -- data actually received cfg -- rs232_util.Config configuration object """ @instance def logic(): data = intbv(0) period = int(1*sec / cfg.baud_rate) yield rx.posedge yield delay(period // 2) data[7] = 0 for i in downrange(cfg.n_bits): yield delay(period) data[i] = rx if cfg.parity is not None: yield delay(period) if rx != parity(data, cfg.parity): raise ParityError yield delay(period) if rx != 0: raise StopBitError actual[8:] = data return logic myhdl-0.11/example/rs232/rs232_tx.py000066400000000000000000000020571347432460400170310ustar00rootroot00000000000000import operator import myhdl from myhdl import * from rs232_util import reduceXor, sec, ODD, EVEN, MARK, SPACE def rs232_tx(tx, data, cfg): """ rs232 transmitter. tx -- serial output data data -- input data byte to be transmitted cfg -- rs232_util.Config configuration object """ duration = delay(int(1*sec / cfg.baud_rate)) @instance def logic(): tx.next = 1 yield duration for i in downrange(cfg.n_bits): tx.next = data[i] yield duration if cfg.parity is not None: if cfg.n_bits == 7: data[7] = 0 if cfg.parity == ODD: tx.next = not reduceXor(data[8:]) elif cfg.parity == EVEN: tx.next = reduceXor(data[8:]) elif cfg.parity == MARK: tx.next = 1 elif cfg.parity == SPACE: tx.next = 0 yield duration tx.next = 0 for i in range(cfg.n_stops): yield duration return logic myhdl-0.11/example/rs232/rs232_util.py000066400000000000000000000022361347432460400173520ustar00rootroot00000000000000import operator sec = 1e9 ODD, EVEN, MARK, SPACE = range(4) class Error(Exception): pass class ParityError(Error): pass class StopBitError(Error): pass class Config(object): """ rs232 configuration object. Attributes: baud_rate -- baud_rate in bits per second n_bits -- number of data bits: 7 or 8 n_stops -- number of stop bits: 1 or 2 parity -- parity configuration: None, ODD, EVEN, MARK or SPACE """ __slots__ = ("baud_rate", "n_bits", "n_stops", "parity") def __init__(self, baud_rate=9600, n_bits=8, n_stops=1, parity=None): """ Return new Config object with actual or default parameters """ self.baud_rate = baud_rate self.n_bits = n_bits self.n_stops = n_stops self.parity = parity def parity(data, cfg): """ Return data parity as configured """ if cfg == ODD: return not reduceXor(data[8:]) elif cfg== EVEN: return reduceXor(data[8:]) elif cfg == MARK: return 1 elif cfg == SPACE: return 0 def reduceXor(bv): """ Return reduction xor of all bits in bv """ return reduce(operator.xor, [b for b in bv]) myhdl-0.11/example/rs232/test_rs232.py000066400000000000000000000077531347432460400173650ustar00rootroot00000000000000import sys from random import randrange import unittest from unittest import TestCase from rs232_rx import rs232_rx from myhdl import Simulation, Signal, intbv, join from rs232_tx import rs232_tx from rs232_util import Config, EVEN, ODD, ParityError, Error class rs232Test(TestCase): """ rs232 functional unit test """ def default(self): tx = Signal(intbv(0)) rx = tx actual = intbv(0) cfg = Config() for i in range(256): data = intbv(i) yield join(rs232_tx(tx, data, cfg), rs232_rx(rx, actual, cfg)) self.assertEqual(data, actual) def testDefault(self): """ Check default case """ Simulation(self.default()).run(quiet=1) def oddParity(self): tx = Signal(intbv(0)) rx = tx actual = intbv(0) cfg = Config(parity=ODD) for i in range(256): data = intbv(i) yield join(rs232_tx(tx, data, cfg), rs232_rx(rx, actual, cfg)) self.assertEqual(data, actual) def testOddParity(self): """ Check odd parity """ Simulation(self.oddParity()).run(quiet=1) def sevenBitsEvenParity(self): tx = Signal(intbv(0)) rx = tx actual = intbv(0) cfg = Config(parity=EVEN, n_bits=7) cfg_rx = Config(parity=EVEN, n_bits=7) for i in range(256): data = intbv(i) yield join(rs232_tx(tx, data, cfg), rs232_rx(rx, actual, cfg_rx)) self.assertEqual(data, actual) def testSevenBitsEvenParity(self): """ Check 7 bits with even parity """ Simulation(self.sevenBitsEvenParity()).run(quiet=1) def ParityError(self): tx = Signal(intbv(0)) rx = tx actual = intbv(0) cfg_rx = Config(parity=ODD) cfg_tx = Config(parity=EVEN) data = intbv(randrange(256)) yield join(rs232_tx(tx, data, cfg_tx), rs232_rx(rx, actual, cfg_rx)) def testParityError(self): """ Expect a parity error """ try: Simulation(self.ParityError()).run(quiet=1) except ParityError: pass else: self.fail("Expected parity error") class rs232Characterize(TestCase): """ rs232 baud rate characterization test """ def bench(self, tx_baud_rate): tx = Signal(intbv(0)) rx = tx actual = intbv(0) cfg_tx = Config(baud_rate=tx_baud_rate) cfg_rx = Config() for i in range(256): data = intbv(i) yield join(rs232_tx(tx, data, cfg_tx), rs232_rx(rx, actual, cfg_rx)) if not data == actual: raise Error def testCharacterize(self): """ Find min/max tx baud rate tolerance by simulation """ coarseOffset = 100 fineOffset = 5 tx_baud_rate = 9600 try: while 1: tx_baud_rate += coarseOffset Simulation(self.bench(tx_baud_rate)).run(quiet=1) except Error: pass while 1: try: tx_baud_rate -= fineOffset Simulation(self.bench(tx_baud_rate)).run(quiet=1) except Error: continue else: print "Max tx baudrate: %s" % tx_baud_rate break tx_baud_rate = 9600 try: while 1: tx_baud_rate -= coarseOffset Simulation(self.bench(tx_baud_rate)).run(quiet=1) except Error: pass while 1: try: tx_baud_rate += fineOffset Simulation(self.bench(tx_baud_rate)).run(quiet=1) except Error: continue else: print "Min tx baudrate: %s" % tx_baud_rate break if __name__ == "__main__": testRunner = unittest.TextTestRunner(verbosity=2) unittest.main(testRunner=testRunner) myhdl-0.11/example/uart_tx/000077500000000000000000000000001347432460400157005ustar00rootroot00000000000000myhdl-0.11/example/uart_tx/uart_tx.py000066400000000000000000000052741347432460400177500ustar00rootroot00000000000000import myhdl from myhdl import * def uart_tx(tx_bit, tx_valid, tx_byte, tx_clk, tx_rst): index = Signal(intbv(0, min=0, max=8)) st = enum('IDLE', 'START', 'DATA') state = Signal(st.IDLE) @always(tx_clk.posedge, tx_rst.negedge) def fsm(): if tx_rst == 0: tx_bit.next = 1 index.next = 0 state.next = st.IDLE else: if state == st.IDLE: tx_bit.next = 1 if tx_valid: # a pulse state.next = st.START elif state == st.START: tx_bit.next = 0 index.next = 7 state.next = st.DATA elif state == st.DATA: tx_bit.next = tx_byte[index] if index == 0: state.next = st.IDLE else: index.next = index - 1 return fsm def uart_tx_2(tx_bit, tx_valid, tx_byte, tx_clk, tx_rst): index = Signal(intbv(0, min=0, max=8)) st = enum('IDLE', 'START', 'DATA') state = Signal(st.IDLE) @always_seq(tx_clk.posedge, reset=tx_rst) def fsm(): if state == st.IDLE: tx_bit.next = 1 if tx_valid: # a pulse state.next = st.START elif state == st.START: tx_bit.next = 0 index.next = 7 state.next = st.DATA elif state == st.DATA: tx_bit.next = tx_byte[index] if index == 0: state.next = st.IDLE else: index.next = index - 1 return fsm def tb(uart_tx): tx_bit = Signal(bool(1)) tx_valid = Signal(bool(0)) tx_byte = Signal(intbv(0)[8:]) tx_clk = Signal(bool(0)) # tx_rst = Signal(bool(1)) tx_rst = ResetSignal(1, active=0, isasync=True) uart_tx_inst = uart_tx(tx_bit, tx_valid, tx_byte, tx_clk, tx_rst) # toVerilog(uart_tx, tx_bit, tx_valid, tx_byte, tx_clk, tx_rst) @always(delay(10)) def clk_gen(): tx_clk.next = not tx_clk @instance def stimulus(): tx_rst.next = 1 yield delay(100) tx_rst.next = 0 yield delay(100) tx_rst.next = 1 yield delay(100) for v in (0x00, 0xff, 0x55, 0xaa): yield tx_clk.negedge tx_byte.next = v tx_valid.next = 1 yield tx_clk.negedge tx_valid.next = 0 yield delay(16 * 20) raise StopSimulation return clk_gen, stimulus, uart_tx_inst sim = Simulation(traceSignals(tb, uart_tx_2)) sim.run() myhdl-0.11/myhdl/000077500000000000000000000000001347432460400136745ustar00rootroot00000000000000myhdl-0.11/myhdl/_Cosimulation.py000066400000000000000000000146171347432460400170640ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Module that provides the Cosimulation class """ from __future__ import absolute_import import sys import os #import shlex import subprocess from myhdl._intbv import intbv from myhdl import _simulator, CosimulationError from myhdl._compat import set_inheritable, string_types, to_bytes, to_str _MAXLINE = 4096 class _error: pass _error.DuplicateSigNames = "Duplicate signal name in myhdl vpi call" _error.SigNotFound = "Signal not found in Cosimulation arguments" _error.TimeZero = "myhdl vpi call when not at time 0" _error.NoCommunication = "No signals communicating to myhdl" _error.SimulationEnd = "Premature simulation end" _error.OSError = "OSError" class Cosimulation(object): """ Cosimulation class. """ def __init__(self, exe="", **kwargs): """ Construct a cosimulation object. """ rt, wt = os.pipe() rf, wf = os.pipe() # Disable inheritance for ends that we don't want the child to have set_inheritable(rt, False) set_inheritable(wf, False) # Enable inheritance for child ends set_inheritable(wt, True) set_inheritable(rf, True) self._rt = rt self._wf = wf self._fromSignames = fromSignames = [] self._fromSizes = fromSizes = [] self._fromSigs = fromSigs = [] self._toSignames = toSignames = [] self._toSizes = toSizes = [] self._toSigs = toSigs = [] self._toSigDict = toSigDict = {} self._hasChange = 0 self._getMode = 1 env = os.environ.copy() # In Windows the FDs aren't inheritable when using Popen, # only the HANDLEs are if sys.platform != "win32": env['MYHDL_TO_PIPE'] = str(wt) env['MYHDL_FROM_PIPE'] = str(rf) else: import msvcrt env['MYHDL_TO_PIPE'] = str(msvcrt.get_osfhandle(wt)) env['MYHDL_FROM_PIPE'] = str(msvcrt.get_osfhandle(rf)) if isinstance(exe, string_types): # exe = shlex.split(exe) exe = exe.split(' ') try: sp = subprocess.Popen(exe, env=env, close_fds=False) except OSError as e: raise CosimulationError(_error.OSError, str(e)) self._child = sp os.close(wt) os.close(rf) while 1: s = to_str(os.read(rt, _MAXLINE)) if not s: raise CosimulationError(_error.SimulationEnd) e = s.split() if e[0] == "FROM": if int(e[1]) != 0: raise CosimulationError(_error.TimeZero, "$from_myhdl") for i in range(2, len(e) - 1, 2): n = e[i] if n in fromSignames: raise CosimulationError(_error.DuplicateSigNames, n) if not n in kwargs: raise CosimulationError(_error.SigNotFound, n) fromSignames.append(n) fromSigs.append(kwargs[n]) fromSizes.append(int(e[i + 1])) os.write(wf, b"OK") elif e[0] == "TO": if int(e[1]) != 0: raise CosimulationError(_error.TimeZero, "$to_myhdl") for i in range(2, len(e) - 1, 2): n = e[i] if n in toSignames: raise CosimulationError(_error.DuplicateSigNames, n) if not n in kwargs: raise CosimulationError(_error.SigNotFound, n) toSignames.append(n) toSigs.append(kwargs[n]) toSigDict[n] = kwargs[n] toSizes.append(int(e[i + 1])) os.write(wf, b"OK") elif e[0] == "START": if not toSignames: raise CosimulationError(_error.NoCommunication) os.write(wf, b"OK") break else: raise CosimulationError("Unexpected cosim input") def _get(self): if not self._getMode: return buf = to_str(os.read(self._rt, _MAXLINE)) if not buf: raise CosimulationError(_error.SimulationEnd) e = buf.split() for i in range(1, len(e), 2): s, v = self._toSigDict[e[i]], e[i + 1] if v in 'zZ': next = None elif v in 'xX': next = s._init else: try: next = int(v, 16) if s._nrbits and s._min is not None and s._min < 0: if next >= (1 << (s._nrbits - 1)): next |= (-1 << s._nrbits) except ValueError: next = intbv(0) s.next = next self._getMode = 0 def _put(self, time): buflist = [] buf = repr(time) if buf[-1] == 'L': buf = buf[:-1] # strip trailing L buflist.append(buf) if self._hasChange: self._hasChange = 0 for s in self._fromSigs: v = int(s._val) # signed support if s._nrbits and v < 0: v += (1 << s._nrbits) buf = hex(v)[2:] if buf[-1] == 'L': buf = buf[:-1] # strip trailing L buflist.append(buf) os.write(self._wf, to_bytes(" ".join(buflist))) self._getMode = 1 def _waiter(self): sigs = tuple(self._fromSigs) while 1: yield sigs self._hasChange = 1 myhdl-0.11/myhdl/_ShadowSignal.py000066400000000000000000000246411347432460400167770ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2015 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Module that provides the ShadowSignal classes """ from __future__ import absolute_import import warnings from copy import deepcopy from myhdl._compat import long from myhdl._Signal import _Signal from myhdl._Waiter import _SignalWaiter, _SignalTupleWaiter from myhdl._intbv import intbv from myhdl._simulator import _siglist from myhdl._bin import bin # shadow signals class _ShadowSignal(_Signal): __slots__ = ('_waiter', ) def __init__(self, val): _Signal.__init__(self, val) # self._driven = True # set this in conversion analyzer # remove next attribute assignment @_Signal.next.setter def next(self, val): raise AttributeError("ShadowSignals are readonly") class _SliceSignal(_ShadowSignal): __slots__ = ('_sig', '_left', '_right') def __init__(self, sig, left, right=None): # XXX error checks if right is None: _ShadowSignal.__init__(self, sig[left]) else: _ShadowSignal.__init__(self, sig[left:right]) self._sig = sig self._left = left self._right = right if right is None: gen = self._genfuncIndex() else: gen = self._genfuncSlice() self._waiter = _SignalWaiter(gen) def _genfuncIndex(self): sig, index = self._sig, self._left set_next = _Signal.next.fset while 1: set_next(self, sig[index]) yield sig def _genfuncSlice(self): sig, left, right = self._sig, self._left, self._right set_next = _Signal.next.fset while 1: set_next(self, sig[left:right]) yield sig def _setName(self, hdl): if self._right is None: if hdl == 'Verilog': self._name = "%s[%s]" % (self._sig._name, self._left) else: self._name = "%s(%s)" % (self._sig._name, self._left) else: if hdl == 'Verilog': self._name = "%s[%s-1:%s]" % (self._sig._name, self._left, self._right) else: self._name = "%s(%s-1 downto %s)" % (self._sig._name, self._left, self._right) def _markRead(self): self._read = True self._sig._read = True def _markUsed(self): self._used = True self._sig._used = True def toVerilog(self): if self._right is None: return "assign %s = %s[%s];" % (self._name, self._sig._name, self._left) else: return "assign %s = %s[%s-1:%s];" % (self._name, self._sig._name, self._left, self._right) def toVHDL(self): if self._right is None: return "%s <= %s(%s);" % (self._name, self._sig._name, self._left) else: return "%s <= %s(%s-1 downto %s);" % (self._name, self._sig._name, self._left, self._right) class ConcatSignal(_ShadowSignal): __slots__ = ('_args', '_sigargs', '_initval') def __init__(self, *args): assert len(args) >= 2 self._args = args self._sigargs = sigargs = [] nrbits = 0 val = 0 for a in args: if isinstance(a, intbv): w = a._nrbits v = a._val elif isinstance(a, _Signal): sigargs.append(a) w = a._nrbits if isinstance(a._val, intbv): v = a._val._val else: v = a._val elif isinstance(a, bool): w = 1 v = a elif isinstance(a, str): w = len(a) v = long(a, 2) else: raise TypeError("ConcatSignal: inappropriate argument type: %s" % type(a)) nrbits += w val = val << w | v & (long(1) << w) - 1 self._initval = val ini = intbv(val)[nrbits:] _ShadowSignal.__init__(self, ini) gen = self.genfunc() self._waiter = _SignalTupleWaiter(gen) def genfunc(self): set_next = _Signal.next.fset args = self._args sigargs = self._sigargs nrbits = self._nrbits newval = intbv(self._initval)[nrbits:] while 1: hi = nrbits for a in args: if isinstance(a, bool): w = 1 else: w = len(a) lo = hi - w # note: 'a in sigargs' is equivalence check, not identity if isinstance(a, _Signal): if isinstance(a._val, intbv): newval[hi:lo] = a[w:] else: newval[hi:lo] = a hi = lo set_next(self, newval) yield sigargs def _markRead(self): self._read = True for s in self._sigargs: s._markRead() def _markUsed(self): self._used = True for s in self._sigargs: s._markUsed() def toVHDL(self): lines = [] ini = intbv(self._initval)[self._nrbits:] hi = self._nrbits for a in self._args: if isinstance(a, bool): w = 1 else: w = len(a) lo = hi - w if w == 1: if isinstance(a, _Signal): if a._type == bool: # isinstance(a._type , bool): <- doesn't work lines.append("%s(%s) <= %s;" % (self._name, lo, a._name)) else: lines.append("%s(%s) <= %s(0);" % (self._name, lo, a._name)) else: lines.append("%s(%s) <= '%s';" % (self._name, lo, bin(ini[lo]))) else: if isinstance(a, _Signal): lines.append("%s(%s-1 downto %s) <= %s;" % (self._name, hi, lo, a._name)) else: lines.append('%s(%s-1 downto %s) <= "%s";' % (self._name, hi, lo, bin(ini[hi:lo], w))) hi = lo return "\n".join(lines) def toVerilog(self): lines = [] ini = intbv(self._initval)[self._nrbits:] hi = self._nrbits for a in self._args: if isinstance(a, bool): w = 1 else: w = len(a) lo = hi - w if w == 1: if isinstance(a, _Signal): if a._type == bool: lines.append("assign %s[%s] = %s;" % (self._name, lo, a._name)) else: lines.append("assign %s[%s] = %s[0];" % (self._name, lo, a._name)) else: lines.append("assign %s[%s] = 'b%s;" % (self._name, lo, bin(ini[lo]))) else: if isinstance(a, _Signal): lines.append("assign %s[%s-1:%s] = %s;" % (self._name, hi, lo, a._name)) else: lines.append("assign %s[%s-1:%s] = 'b%s;" % (self._name, hi, lo, bin(ini[hi:lo], w))) hi = lo return "\n".join(lines) # Tristate signal class BusContentionWarning(UserWarning): pass warnings.filterwarnings('always', r".*", BusContentionWarning) # def Tristate(val, delay=None): # """ Return a new Tristate(default or delay 0) or DelayedTristate """ # if delay is not None: # if delay < 0: # raise TypeError("Signal: delay should be >= 0") # return _DelayedTristate(val, delay) # else: # return _Tristate(val) def TristateSignal(val): return _TristateSignal(val) class _TristateSignal(_ShadowSignal): __slots__ = ('_drivers', '_orival') def __init__(self, val): self._drivers = [] # construct normally to set type / size info right _ShadowSignal.__init__(self, val) self._orival = deepcopy(val) # keep for drivers # reset signal values to None self._next = self._val = self._init = None self._waiter = _SignalTupleWaiter(self._resolve()) def driver(self): d = _TristateDriver(self) self._drivers.append(d) return d def _resolve(self): # set_next = _ShadowSignal._set_next senslist = self._drivers while 1: yield senslist res = None for d in senslist: if res is None: res = d._val elif d._val is not None: warnings.warn("Bus contention", category=BusContentionWarning) res = None break self._next = res _siglist.append(self) def toVerilog(self): lines = [] for d in self._drivers: if d._driven: lines.append("assign %s = %s;" % (self._name, d._name)) return "\n".join(lines) def toVHDL(self): lines = [] for d in self._drivers: if d._driven: lines.append("%s <= %s;" % (self._name, d._name)) return "\n".join(lines) class _TristateDriver(_Signal): __slots__ = ('_sig',) def __init__(self, sig): _Signal.__init__(self, sig._orival) # reset signal values to None self._next = self._val = self._init = None self._sig = sig @_Signal.next.setter def next(self, val): if isinstance(val, _Signal): val = val._val if val is None: self._next = None else: # restore original value to cater for intbv handler self._next = self._sig._orival self._setNextVal(val) _siglist.append(self) myhdl-0.11/myhdl/_Signal.py000066400000000000000000000426601347432460400156320ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2011 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Module that provides the Signal class and related objects. This module provides the following objects: Signal -- class to model hardware signals posedge -- callable to model a rising edge on a signal in a yield statement negedge -- callable to model a falling edge on a signal in a yield statement """ from __future__ import absolute_import from __future__ import print_function from copy import copy, deepcopy from myhdl._compat import integer_types, long from myhdl import _simulator as sim from myhdl._simulator import _futureEvents from myhdl._simulator import _siglist from myhdl._simulator import _signals from myhdl._intbv import intbv from myhdl._bin import bin # from myhdl._enum import EnumItemType _schedule = _futureEvents.append def _isListOfSigs(obj): """ Check if obj is a non-empty list of signals. """ if isinstance(obj, list) and len(obj) > 0: for e in obj: if not isinstance(e, _Signal): return False return True else: return False class _WaiterList(list): def purge(self): if self: self[:] = [w for w in self if not w.hasRun] class _PosedgeWaiterList(_WaiterList): def __init__(self, sig): self.sig = sig def _toVerilog(self): return "posedge %s" % self.sig._name def _toVHDL(self): return "rising_edge(%s)" % self.sig._name class _NegedgeWaiterList(_WaiterList): def __init__(self, sig): self.sig = sig def _toVerilog(self): return "negedge %s" % self.sig._name def _toVHDL(self): return "falling_edge(%s)" % self.sig._name def posedge(sig): """ Return a posedge trigger object """ return sig.posedge def negedge(sig): """ Return a negedge trigger object """ return sig.negedge # signal factory function def Signal(val=None, delay=None): """ Return a new _Signal (default or delay 0) or DelayedSignal """ if delay is not None: if delay < 0: raise TypeError("Signal: delay should be >= 0") return _DelayedSignal(val, delay) else: return _Signal(val) class _Signal(object): """ _Signal class. Properties: val -- current value (read-only) next -- next value (read-write) """ __slots__ = ('_next', '_val', '_min', '_max', '_type', '_init', '_eventWaiters', '_posedgeWaiters', '_negedgeWaiters', '_code', '_tracing', '_nrbits', '_checkVal', '_setNextVal', '_copyVal2Next', '_printVcd', '_driven', '_read', '_name', '_used', '_inList', '_waiter', 'toVHDL', 'toVerilog', '_slicesigs', '_numeric' ) def __init__(self, val=None): """ Construct a signal. val -- initial value """ self._init = deepcopy(val) self._val = deepcopy(val) self._next = deepcopy(val) self._min = self._max = None self._name = self._driven = None self._read = self._used = False self._inList = False self._nrbits = 0 self._numeric = True self._printVcd = self._printVcdStr if isinstance(val, bool): self._type = bool self._setNextVal = self._setNextBool self._printVcd = self._printVcdBit self._nrbits = 1 elif isinstance(val, integer_types): self._type = integer_types self._setNextVal = self._setNextInt elif isinstance(val, intbv): self._type = intbv self._min = val._min self._max = val._max self._nrbits = val._nrbits self._setNextVal = self._setNextIntbv if self._nrbits: self._printVcd = self._printVcdVec else: self._printVcd = self._printVcdHex else: self._type = type(val) if isinstance(val, EnumItemType): self._setNextVal = self._setNextNonmutable else: self._setNextVal = self._setNextMutable if hasattr(val, '_nrbits'): self._nrbits = val._nrbits self._eventWaiters = _WaiterList() self._posedgeWaiters = _PosedgeWaiterList(self) self._negedgeWaiters = _NegedgeWaiterList(self) self._code = "" self._slicesigs = [] self._tracing = 0 _signals.append(self) def _clear(self): del self._eventWaiters[:] del self._posedgeWaiters[:] del self._negedgeWaiters[:] self._val = deepcopy(self._init) self._next = deepcopy(self._init) self._name = self._driven = None self._read = False # dont clear self._used self._inList = False self._numeric = True for s in self._slicesigs: s._clear() def _update(self): val, next = self._val, self._next if val != next: waiters = self._eventWaiters[:] del self._eventWaiters[:] if not val and next: waiters.extend(self._posedgeWaiters[:]) del self._posedgeWaiters[:] elif not next and val: waiters.extend(self._negedgeWaiters[:]) del self._negedgeWaiters[:] if next is None: self._val = None elif isinstance(val, intbv): self._val._val = next._val elif isinstance(val, (integer_types, EnumItemType)): self._val = next else: self._val = deepcopy(next) if self._tracing: self._printVcd() return waiters else: return [] # support for the 'val' attribute @property def val(self): return self._val # support for the 'next' attribute @property def next(self): # if self._next is self._val: # self._next = deepcopy(self._val) _siglist.append(self) return self._next @next.setter def next(self, val): if isinstance(val, _Signal): val = val._val self._setNextVal(val) _siglist.append(self) # support for the 'posedge' attribute @property def posedge(self): return self._posedgeWaiters # support for the 'negedge' attribute @property def negedge(self): return self._negedgeWaiters # support for the 'min' and 'max' attribute @property def max(self): return self._max @property def min(self): return self._min # support for the 'driven' attribute @property def driven(self): return self._driven @driven.setter def driven(self, val): if not val in ("reg", "wire", True): raise ValueError('Expected value "reg", "wire", or True, got "%s"' % val) self._driven = val # support for the 'read' attribute @property def read(self): return self._read @read.setter def read(self, val): if not val in (True, ): raise ValueError('Expected value True, got "%s"' % val) self._markRead() def _markRead(self): self._read = True # 'used' attribute def _markUsed(self): self._used = True # set next methods def _setNextBool(self, val): if isinstance(val, intbv): val = val._val if not val in (0, 1): raise ValueError("Expected boolean value, got %s (%s)" % (repr(val), type(val))) self._next = val def _setNextInt(self, val): if isinstance(val, intbv): val = val._val elif not isinstance(val, (integer_types, intbv)): raise TypeError("Expected int or intbv, got %s" % type(val)) self._next = val def _setNextIntbv(self, val): if isinstance(val, intbv): val = val._val elif not isinstance(val, integer_types): raise TypeError("Expected int or intbv, got %s" % type(val)) self._next._val = val self._next._handleBounds() def _setNextNonmutable(self, val): if not isinstance(val, self._type): raise TypeError("Expected %s, got %s" % (self._type, type(val))) self._next = val def _setNextMutable(self, val): if not isinstance(val, self._type): raise TypeError("Expected %s, got %s" % (self._type, type(val))) self._next = deepcopy(val) # vcd print methods def _printVcdStr(self): print("s%s %s" % (str(self._val), self._code), file=sim._tf) def _printVcdHex(self): if self._val is None: print("sz %s" % self._code, file=sim._tf) else: print("s%s %s" % (hex(self._val), self._code), file=sim._tf) def _printVcdBit(self): if self._val is None: print("z%s" % self._code, file=sim._tf) else: print("%d%s" % (self._val, self._code), file=sim._tf) def _printVcdVec(self): if self._val is None: print("b%s %s" % ('z' * self._nrbits, self._code), file=sim._tf) else: print("b%s %s" % (bin(self._val, self._nrbits), self._code), file=sim._tf) ### use call interface for shadow signals ### def __call__(self, left, right=None): s = _SliceSignal(self, left, right) self._slicesigs.append(s) return s ### operators for which delegation to current value is appropriate ### def __hash__(self): raise TypeError("Signals are unhashable") def __bool__(self): return bool(self._val) __nonzero__ = __bool__ # length def __len__(self): return self._nrbits # return len(self._val) # indexing and slicing methods def __getitem__(self, key): return self._val[key] # integer-like methods def __add__(self, other): if isinstance(other, _Signal): return self._val + other._val else: return self._val + other def __radd__(self, other): return other + self._val def __sub__(self, other): if isinstance(other, _Signal): return self._val - other._val else: return self._val - other def __rsub__(self, other): return other - self._val def __mul__(self, other): if isinstance(other, _Signal): return self._val * other._val else: return self._val * other def __rmul__(self, other): return other * self._val def __truediv__(self, other): if isinstance(other, _Signal): return self._val / other._val else: return self._val / other def __rtruediv__(self, other): return other / self._val def __floordiv__(self, other): if isinstance(other, _Signal): return self._val // other._val else: return self._val // other def __rfloordiv__(self, other): return other // self._val def __mod__(self, other): if isinstance(other, _Signal): return self._val % other._val else: return self._val % other def __rmod__(self, other): return other % self._val # XXX divmod def __pow__(self, other): if isinstance(other, _Signal): return self._val ** other._val else: return self._val ** other def __rpow__(self, other): return other ** self._val def __lshift__(self, other): if isinstance(other, _Signal): return self._val << other._val else: return self._val << other def __rlshift__(self, other): return other << self._val def __rshift__(self, other): if isinstance(other, _Signal): return self._val >> other._val else: return self._val >> other def __rrshift__(self, other): return other >> self._val def __and__(self, other): if isinstance(other, _Signal): return self._val & other._val else: return self._val & other def __rand__(self, other): return other & self._val def __or__(self, other): if isinstance(other, _Signal): return self._val | other._val else: return self._val | other def __ror__(self, other): return other | self._val def __xor__(self, other): if isinstance(other, _Signal): return self._val ^ other._val else: return self._val ^ other def __rxor__(self, other): return other ^ self._val def __neg__(self): return -self._val def __pos__(self): return +self._val def __abs__(self): return abs(self._val) def __invert__(self): return ~self._val # conversions def __int__(self): return int(self._val) def __long__(self): return long(self._val) def __float__(self): return float(self._val) def __oct__(self): return oct(self._val) def __hex__(self): return hex(self._val) def __index__(self): return int(self._val) # comparisons def __eq__(self, other): return self.val == other def __ne__(self, other): return self.val != other def __lt__(self, other): return self.val < other def __le__(self, other): return self.val <= other def __gt__(self, other): return self.val > other def __ge__(self, other): return self.val >= other # method lookup delegation def __getattr__(self, attr): return getattr(self._val, attr) # representation def __str__(self): if self._name: return self._name else: return str(self._val) def __repr__(self): return "Signal(" + repr(self._val) + ")" def _toVerilog(self): return self._name # augmented assignment not supported def _augm(self): raise TypeError("Signal object doesn't support augmented assignment") __iadd__ = __isub__ = __imul__ = __ipow__ = __imod__ = _augm __ior__ = __iand__ = __ixor__ = __irshift__ = __ilshift__ = _augm __itruediv__ = __ifloordiv__ = _augm # index and slice assignment not supported def __setitem__(self, key, val): raise TypeError("Signal object doesn't support item/slice assignment") # continues assignment support def assign(self, sig): self.driven = "wire" def genFunc(): while 1: self.next = sig._val yield sig self._waiter = _SignalWaiter(genFunc()) def toVHDL(): return "%s <= %s;" % (self._name, sig._name) def toVerilog(): return "assign %s = %s;" % (self._name, sig._name) self.toVHDL = toVHDL self.toVerilog = toVerilog class _DelayedSignal(_Signal): __slots__ = ('_nextZ', '_delay', '_timeStamp', ) def __init__(self, val=None, delay=1): """ Construct a new DelayedSignal. Automatically invoked through the Signal new method. val -- initial value delay -- non-zero delay value """ _Signal.__init__(self, val) self._nextZ = val self._delay = delay self._timeStamp = 0 def _update(self): if self._next != self._nextZ: self._timeStamp = sim._time self._nextZ = self._next t = sim._time + self._delay _schedule((t, _SignalWrap(self, self._next, self._timeStamp))) return [] def _apply(self, next, timeStamp): val = self._val if timeStamp == self._timeStamp and val != next: waiters = self._eventWaiters[:] del self._eventWaiters[:] if not val and next: waiters.extend(self._posedgeWaiters[:]) del self._posedgeWaiters[:] elif not next and val: waiters.extend(self._negedgeWaiters[:]) del self._negedgeWaiters[:] self._val = copy(next) if self._tracing: self._printVcd() return waiters else: return [] # support for the 'delay' attribute @property def delay(self): return self._delay @delay.setter def delay(self, delay): self._delay = delay class _SignalWrap(object): def __init__(self, sig, next, timeStamp): self.sig = sig self.next = next self.timeStamp = timeStamp def apply(self): return self.sig._apply(self.next, self.timeStamp) # for export SignalType = _Signal # avoid circular imports from myhdl._ShadowSignal import _SliceSignal from myhdl._Waiter import _SignalWaiter from myhdl._enum import EnumItemType myhdl-0.11/myhdl/_Simulation.py000066400000000000000000000206441347432460400165370ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Module that provides the Simulation class """ from __future__ import absolute_import from __future__ import print_function import os from operator import itemgetter from types import GeneratorType from myhdl import StopSimulation, _SuspendSimulation from myhdl import _simulator, SimulationError from myhdl._Cosimulation import Cosimulation from myhdl._simulator import _signals, _siglist, _futureEvents from myhdl._Waiter import _Waiter from myhdl._Waiter import _inferWaiter from myhdl._Waiter import _SignalTupleWaiter from myhdl._util import _printExcInfo from myhdl._instance import _Instantiator from myhdl._block import _Block schedule = _futureEvents.append class _error: pass _error.ArgType = "Inappriopriate argument type" _error.MultipleCosim = "Only a single cosimulator argument allowed" _error.DuplicatedArg = "Duplicated argument" # flatten Block objects out def _flatten(*args): arglist = [] for arg in args: if isinstance(arg, _Block): arg = arg.subs if isinstance(arg, (list, tuple, set)): for item in arg: arglist.extend(_flatten(item)) else: arglist.append(arg) return arglist _error.MultipleSim = "Only a single Simulation instance is allowed" class Simulation(object): """ Simulation class. Methods: run -- run a simulation for some duration """ _no_of_instances = 0 def __init__(self, *args): """ Construct a simulation object. *args -- list of arguments. Each argument is a generator or a nested sequence of generators. """ _simulator._time = 0 arglist = _flatten(*args) self._waiters, self._cosims = _makeWaiters(arglist) if Simulation._no_of_instances > 0: raise SimulationError(_error.MultipleSim) Simulation._no_of_instances += 1 self._finished = False del _futureEvents[:] del _siglist[:] def _finalize(self): cosims = self._cosims if cosims: for cosim in cosims: os.close(cosim._rt) os.close(cosim._wf) cosim._child.wait() if _simulator._tracing: _simulator._tracing = 0 _simulator._tf.close() # clean up for potential new run with same signals for s in _signals: s._clear() Simulation._no_of_instances = 0 self._finished = True def quit(self): self._finalize() def run(self, duration=None, quiet=0): """ Run the simulation for some duration. duration -- specified simulation duration (default: forever) quiet -- don't print StopSimulation messages (default: off) """ # If the simulation is already finished, raise StopSimulation immediately # From this point it will propagate to the caller, that can catch it. if self._finished: raise StopSimulation("Simulation has already finished") waiters = self._waiters maxTime = None if duration: stop = _Waiter(None) stop.hasRun = 1 maxTime = _simulator._time + duration schedule((maxTime, stop)) cosims = self._cosims t = _simulator._time actives = {} tracing = _simulator._tracing tracefile = _simulator._tf exc = [] _pop = waiters.pop _append = waiters.append _extend = waiters.extend while 1: try: for s in _siglist: _extend(s._update()) del _siglist[:] while waiters: waiter = _pop() try: waiter.next(waiters, actives, exc) except StopIteration: continue if cosims: any_cosim_changes = False for cosim in cosims: any_cosim_changes = \ any_cosim_changes or cosim._hasChange for cosim in cosims: cosim._get() if _siglist or any_cosim_changes: # It should be safe to _put a cosim with no changes # because _put with the same values should be # idempotent. We need to _put them all here because # otherwise we can desync _get/_put. for cosim in cosims: cosim._put(t) continue elif _siglist: continue if actives: for wl in actives.values(): wl.purge() actives = {} # at this point it is safe to potentially suspend a simulation if exc: raise exc[0] # future events if _futureEvents: if t == maxTime: raise _SuspendSimulation( "Simulated %s timesteps" % duration) _futureEvents.sort(key=itemgetter(0)) t = _simulator._time = _futureEvents[0][0] if tracing: print("#%s" % t, file=tracefile) if cosims: for cosim in cosims: cosim._put(t) while _futureEvents: newt, event = _futureEvents[0] if newt == t: if isinstance(event, _Waiter): _append(event) else: _extend(event.apply()) del _futureEvents[0] else: break else: raise StopSimulation("No more events") except _SuspendSimulation: if not quiet: _printExcInfo() if tracing: tracefile.flush() return 1 except StopSimulation: if not quiet: _printExcInfo() self._finalize() self._finished = True return 0 except Exception as e: if tracing: tracefile.flush() # if the exception came from a yield, make sure we can resume if exc and e is exc[0]: pass # don't finalize else: self._finalize() # now reraise the exepction raise def _makeWaiters(arglist): waiters = [] ids = set() cosims = [] for arg in arglist: if isinstance(arg, GeneratorType): waiters.append(_inferWaiter(arg)) elif isinstance(arg, _Instantiator): waiters.append(arg.waiter) elif isinstance(arg, Cosimulation): cosims.append(arg) waiters.append(_SignalTupleWaiter(arg._waiter())) elif isinstance(arg, _Waiter): waiters.append(arg) elif arg == True: pass else: raise SimulationError(_error.ArgType, str(type(arg))) if id(arg) in ids: raise SimulationError(_error.DuplicatedArg) ids.add(id(arg)) # add waiters for shadow signals for sig in _signals: if hasattr(sig, '_waiter'): waiters.append(sig._waiter) return waiters, cosims myhdl-0.11/myhdl/_Waiter.py000066400000000000000000000202041347432460400156360ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2009 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Module that provides the _Waiter class """ from __future__ import absolute_import from types import GeneratorType import ast import inspect from myhdl._util import _dedent from myhdl._delay import delay from myhdl._join import join from myhdl._Signal import _Signal, _WaiterList, posedge, negedge from myhdl import _simulator from myhdl._simulator import _futureEvents schedule = _futureEvents.append class _Waiter(object): __slots__ = ('caller', 'generator', 'hasRun', 'nrTriggers', 'semaphore') def __init__(self, generator, caller=None): self.caller = caller self.generator = generator self.hasRun = 0 self.nrTriggers = 1 self.semaphore = 0 def next(self, waiters, actives, exc): if self.hasRun: raise StopIteration if self.semaphore: self.semaphore -= 1 raise StopIteration if self.nrTriggers == 1: clone = self else: self.hasRun = 1 clone = _Waiter(self.generator, self.caller) try: clause = next(self.generator) except StopIteration: if self.caller: waiters.append(self.caller) raise # again if isinstance(clause, _WaiterList): clauses = (clause,) elif isinstance(clause, (tuple, list)): clone.nrTriggers = len(clause) if clause: clauses = clause else: clauses = (None,) elif isinstance(clause, join): clone.semaphore = len(clause._args) - 1 clauses = clause._args else: clauses = (clause,) nr = len(clauses) for clause in clauses: if isinstance(clause, _WaiterList): clause.append(clone) if nr > 1: actives[id(clause)] = clause elif isinstance(clause, _Signal): wl = clause._eventWaiters wl.append(clone) if nr > 1: actives[id(wl)] = wl elif isinstance(clause, delay): t = _simulator._time schedule((t + clause._time, clone)) elif isinstance(clause, GeneratorType): waiters.append(_Waiter(clause, clone)) elif isinstance(clause, _Instantiator): waiters.append(_Waiter(clause.gen, clone)) elif isinstance(clause, join): waiters.append(_Waiter(clause._generator(), clone)) elif clause is None: waiters.append(clone) elif isinstance(clause, Exception): waiters.append(clone) if not exc: exc.append(clause) else: raise TypeError("yield clause %s has type %s" % (repr(clause), type(clause))) class _DelayWaiter(_Waiter): __slots__ = ('generator') def __init__(self, generator): self.generator = generator def next(self, waiters, actives, exc): clause = next(self.generator) schedule((_simulator._time + clause._time, self)) class _EdgeWaiter(_Waiter): __slots__ = ('generator', 'hasRun') def __init__(self, generator): self.generator = generator self.hasRun = 0 def next(self, waiters, actives, exc): clause = next(self.generator) clause.append(self) class _EdgeTupleWaiter(_Waiter): __slots__ = ('generator', 'hasRun') def __init__(self, generator): self.generator = generator self.hasRun = 0 def next(self, waiters, actives, exc): if self.hasRun: raise StopIteration clauses = next(self.generator) self.hasRun = 1 clone = _EdgeTupleWaiter(self.generator) for clause in clauses: clause.append(clone) actives[id(clause)] = clause class _SignalWaiter(_Waiter): __slots__ = ('generator', 'hasRun') def __init__(self, generator): self.generator = generator self.hasRun = 0 def next(self, waiters, actives, exc): clause = next(self.generator) clause._eventWaiters.append(self) class _SignalTupleWaiter(_Waiter): __slots__ = ('generator', 'hasRun') def __init__(self, generator): self.generator = generator self.hasRun = 0 def next(self, waiters, actives, exc): if self.hasRun: raise StopIteration clauses = next(self.generator) self.hasRun = 1 clone = _SignalTupleWaiter(self.generator) for clause in clauses: wl = clause._eventWaiters wl.append(clone) actives[id(wl)] = wl #_kind = enum("SIGNAL_TUPLE", "EDGE_TUPLE", "SIGNAL", "EDGE", "DELAY", "UNDEFINED") class _kind(object): SIGNAL_TUPLE = 1 EDGE_TUPLE = 2 SIGNAL = 3 EDGE = 4 DELAY = 5 UNDEFINED = 6 def _inferWaiter(gen): f = gen.gi_frame s = inspect.getsource(f) s = _dedent(s) root = ast.parse(s) root.symdict = f.f_globals.copy() root.symdict.update(f.f_locals) # print ast.dump(root) v = _YieldVisitor(root) v.visit(root) if v.kind == _kind.EDGE_TUPLE: return _EdgeTupleWaiter(gen) if v.kind == _kind.SIGNAL_TUPLE: return _SignalTupleWaiter(gen) if v.kind == _kind.DELAY: return _DelayWaiter(gen) if v.kind == _kind.EDGE: return _EdgeWaiter(gen) if v.kind == _kind.SIGNAL: return _SignalWaiter(gen) # default return _Waiter(gen) class _YieldVisitor(ast.NodeVisitor): def __init__(self, root): self.kind = None self.root = root def visit_Yield(self, node): self.visit(node.value) if not hasattr(node.value, 'kind'): self.kind = _kind.UNDEFINED elif not self.kind: self.kind = node.value.kind elif self.kind != node.value.kind: self.kind = _kind.UNDEFINED def visit_Tuple(self, node): kind = None for elt in node.elts: self.visit(elt) if not hasattr(elt, 'kind'): kind = _kind.UNDEFINED elif not kind: kind = elt.kind elif kind != elt.kind: kind = _kind.UNDEFINED if kind == _kind.SIGNAL: node.kind = _kind.SIGNAL_TUPLE elif kind == _kind.EDGE: node.kind = _kind.EDGE_TUPLE else: node.kind = _kind.UNDEFINED def visit_Call(self, node): fn = node.func if not isinstance(fn, ast.Name): node.kind = _kind.UNDEFINED return self.visit(fn) node.kind = fn.kind def visit_Name(self, node): n = node.id node.kind = _kind.UNDEFINED if n in self.root.symdict: obj = self.root.symdict[n] if isinstance(obj, _Signal): node.kind = _kind.SIGNAL elif obj is delay: node.kind = _kind.DELAY elif obj is posedge or obj is negedge: node.kind = _kind.EDGE def visit_Attribute(self, node): node.kind = _kind.UNDEFINED if node.attr in ('posedge', 'negedge'): node.kind = _kind.EDGE # avoid problems with recursive imports from myhdl._instance import _Instantiator myhdl-0.11/myhdl/__init__.py000066400000000000000000000124421347432460400160100ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2015 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ myhdl package initialization. This module provides the following myhdl objects: Simulation -- simulation class StopSimulation -- exception that stops a simulation now -- function that returns the current time Signal -- factory function to model hardware signals SignalType -- Signal base class ConcatSignal -- factory function that models a concatenation shadow signal TristateSignal -- factory function that models a tristate shadow signal delay -- callable to model delay in a yield statement posedge -- callable to model a rising edge on a signal in a yield statement negedge -- callable to model a falling edge on a signal in a yield statement join -- callable to join clauses in a yield statement intbv -- mutable integer class with bit vector facilities modbv -- modular bit vector class downrange -- function that returns a downward range bin -- returns a binary string representation. The optional width specifies the desired string width: padding of the sign-bit is used. concat -- function to concat ints, bitstrings, bools, intbvs, Signals -- returns an intbv instances -- function that returns all instances defined in a function always -- always_comb -- decorator that returns an input-sensitive generator always_seq -- ResetSignal -- enum -- function that returns an enumeration type traceSignals -- function that enables signal tracing in a VCD file toVerilog -- function that converts a design to Verilog """ from __future__ import absolute_import from __future__ import print_function __version__ = "0.11" class StopSimulation(Exception): """ Basic exception to stop a Simulation """ pass class _SuspendSimulation(Exception): """ Basic exception to suspend a Simulation """ pass class Error(Exception): def __init__(self, kind, msg="", info=""): self.kind = kind self.msg = msg self.info = info def __str__(self): s = "%s%s" % (self.info, self.kind) if self.msg: s += ": %s" % self.msg return s class AlwaysError(Error): pass class AlwaysCombError(Error): pass class InstanceError(Error): pass class BlockError(Error): pass class BlockInstanceError(Error): pass class CosimulationError(Error): pass class ExtractHierarchyError(Error): pass class SimulationError(Error): pass class TraceSignalsError(Error): pass class ConversionError(Error): pass class ToVerilogError(ConversionError): pass class ToVHDLError(ConversionError): pass class ConversionWarning(UserWarning): pass class ToVerilogWarning(ConversionWarning): pass class ToVHDLWarning(ConversionWarning): pass # warnings.filterwarnings('always', r".*", ToVerilogWarning) # def showwarning(message, category, filename, lineno, *args): # print("** %s: %s" % (category.__name__, message), file=sys.stderr) #warnings.showwarning = showwarning from ._bin import bin from ._concat import concat from ._intbv import intbv from ._modbv import modbv from ._join import join from ._Signal import posedge, negedge, Signal, SignalType from ._ShadowSignal import ConcatSignal from ._ShadowSignal import TristateSignal from ._simulator import now from ._delay import delay from ._Cosimulation import Cosimulation from ._Simulation import Simulation from ._misc import instances, downrange from ._always_comb import always_comb from ._always_seq import always_seq, ResetSignal from ._always import always from ._instance import instance from ._block import block from ._enum import enum, EnumType, EnumItemType from ._traceSignals import traceSignals from myhdl import conversion from .conversion import toVerilog from .conversion import toVHDL from ._tristate import Tristate __all__ = ["bin", "concat", "intbv", "modbv", "join", "posedge", "negedge", "Signal", "SignalType", "ConcatSignal", "TristateSignal", "now", "delay", "downrange", "StopSimulation", "Cosimulation", "Simulation", "instances", "instance", "block", "always_comb", "always_seq", "ResetSignal", "always", "enum", "EnumType", "EnumItemType", "traceSignals", "toVerilog", "toVHDL", "conversion", "Tristate" ] myhdl-0.11/myhdl/_always.py000066400000000000000000000106041347432460400157060ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Module with the always function. """ from __future__ import absolute_import from types import FunctionType from myhdl import AlwaysError from myhdl._util import _isGenFunc from myhdl._delay import delay from myhdl._Signal import _Signal from myhdl._Signal import _WaiterList from myhdl._Waiter import _Waiter, _SignalWaiter, _SignalTupleWaiter, \ _DelayWaiter, _EdgeWaiter, _EdgeTupleWaiter from myhdl._instance import _Instantiator, _getCallInfo class _error: pass _error.DecArgType = "decorator argument should be a Signal, edge, or delay" _error.ArgType = "decorated object should be a classic (non-generator) function" _error.NrOfArgs = "decorated function should not have arguments" _error.DecNrOfArgs = "decorator should have arguments" def _get_sigdict(sigs, symdict): """Lookup signals in caller namespace and return sigdict Lookup signals in then namespace of a caller. This is used to add signal arguments from an instantiator decorator to the instance. 0: this function 1: the instantiator decorator 2: the module function that defines instances """ sigdict = {} for n, v in symdict.items(): for s in sigs: if s is v: sigdict[n] = s return sigdict def always(*args): callinfo = _getCallInfo() sigargs = [] for arg in args: if isinstance(arg, _Signal): arg._read = True arg._used = True sigargs.append(arg) elif isinstance(arg, _WaiterList): arg.sig._read = True arg.sig._used = True sigargs.append(arg.sig) elif not isinstance(arg, delay): raise AlwaysError(_error.DecArgType) sigdict = _get_sigdict(sigargs, callinfo.symdict) def _always_decorator(func): if not isinstance(func, FunctionType): raise AlwaysError(_error.ArgType) if _isGenFunc(func): raise AlwaysError(_error.ArgType) if func.__code__.co_argcount > 0: raise AlwaysError(_error.NrOfArgs) return _Always(func, args, callinfo=callinfo, sigdict=sigdict) return _always_decorator class _Always(_Instantiator): def __init__(self, func, senslist, callinfo, sigdict=None): self.func = func self.senslist = tuple(senslist) super(_Always, self).__init__(self.genfunc, callinfo=callinfo) # update sigdict with decorator signal arguments if sigdict is not None: self.sigdict.update(sigdict) @property def funcobj(self): return self.func def _waiter(self): # infer appropriate waiter class # first infer base type of arguments for t in (_Signal, _WaiterList, delay): if isinstance(self.senslist[0], t): bt = t for s in self.senslist[1:]: if not isinstance(s, bt): bt = None break # now set waiter class w = _Waiter if bt is delay: w = _DelayWaiter elif len(self.senslist) == 1: if bt is _Signal: w = _SignalWaiter elif bt is _WaiterList: w = _EdgeWaiter else: if bt is _Signal: w = _SignalTupleWaiter elif bt is _WaiterList: w = _EdgeTupleWaiter return w def genfunc(self): senslist = self.senslist if len(senslist) == 1: senslist = senslist[0] func = self.func while 1: yield senslist func() myhdl-0.11/myhdl/_always_comb.py000066400000000000000000000057061347432460400167150ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2009 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Module with the always_comb function. """ from __future__ import absolute_import from types import FunctionType from myhdl import AlwaysCombError from myhdl._Signal import _Signal, _isListOfSigs from myhdl._util import _isGenFunc from myhdl._instance import _getCallInfo from myhdl._always import _Always class _error: pass _error.ArgType = "always_comb argument should be a classic function" _error.NrOfArgs = "always_comb argument should be a function without arguments" _error.Scope = "always_comb argument should be a local function" _error.SignalAsInout = "signal (%s) used as inout in always_comb function argument" _error.EmbeddedFunction = "embedded functions in always_comb function argument not supported" _error.EmptySensitivityList = "sensitivity list is empty" def always_comb(func): callinfo = _getCallInfo() if not isinstance(func, FunctionType): raise AlwaysCombError(_error.ArgType) if _isGenFunc(func): raise AlwaysCombError(_error.ArgType) if func.__code__.co_argcount > 0: raise AlwaysCombError(_error.NrOfArgs) c = _AlwaysComb(func, callinfo=callinfo) return c class _AlwaysComb(_Always): def __init__(self, func, callinfo): senslist = [] super(_AlwaysComb, self).__init__(func, senslist, callinfo=callinfo) inouts = self.inouts | self.inputs.intersection(self.outputs) if inouts: raise AlwaysCombError(_error.SignalAsInout % inouts) if self.embedded_func: raise AlwaysCombError(_error.EmbeddedFunction) for n in self.inputs: s = self.symdict[n] if isinstance(s, _Signal): senslist.append(s) elif _isListOfSigs(s): senslist.extend(s) self.senslist = tuple(senslist) if len(self.senslist) == 0: raise AlwaysCombError(_error.EmptySensitivityList) def genfunc(self): senslist = self.senslist if len(senslist) == 1: senslist = senslist[0] func = self.func while 1: func() yield senslist myhdl-0.11/myhdl/_always_seq.py000066400000000000000000000120271347432460400165570ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2012 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Module with the always_seq decorator. """ from __future__ import absolute_import from types import FunctionType from myhdl import AlwaysError, intbv from myhdl._util import _isGenFunc from myhdl._Signal import _Signal, _WaiterList, _isListOfSigs from myhdl._always import _Always, _get_sigdict from myhdl._instance import _getCallInfo # evacuate this later AlwaysSeqError = AlwaysError class _error: pass _error.EdgeType = "first argument should be an edge" _error.ResetType = "reset argument should be a ResetSignal" _error.ArgType = "decorated object should be a classic (non-generator) function" _error.NrOfArgs = "decorated function should not have arguments" _error.SigAugAssign = "signal assignment does not support augmented assignment" _error.EmbeddedFunction = "embedded functions in always_seq function not supported" class ResetSignal(_Signal): def __init__(self, val, active, isasync): """ Construct a ResetSignal. This is to be used in conjunction with the always_seq decorator, as the reset argument. """ _Signal.__init__(self, bool(val)) self.active = bool(active) self.isasync = isasync def always_seq(edge, reset): callinfo = _getCallInfo() sigargs = [] if not isinstance(edge, _WaiterList): raise AlwaysSeqError(_error.EdgeType) edge.sig._read = True edge.sig._used = True sigargs.append(edge.sig) if reset is not None: if not isinstance(reset, ResetSignal): raise AlwaysSeqError(_error.ResetType) reset._read = True reset._used = True sigargs.append(reset) sigdict = _get_sigdict(sigargs, callinfo.symdict) def _always_seq_decorator(func): if not isinstance(func, FunctionType): raise AlwaysSeqError(_error.ArgType) if _isGenFunc(func): raise AlwaysSeqError(_error.ArgType) if func.__code__.co_argcount > 0: raise AlwaysSeqError(_error.NrOfArgs) return _AlwaysSeq(func, edge, reset, callinfo=callinfo, sigdict=sigdict) return _always_seq_decorator class _AlwaysSeq(_Always): def __init__(self, func, edge, reset, callinfo, sigdict): senslist = [edge] self.reset = reset if reset is not None: self.genfunc = self.genfunc_reset active = self.reset.active isasync = self.reset.isasync if isasync: if active: senslist.append(reset.posedge) else: senslist.append(reset.negedge) else: self.genfunc = self.genfunc_no_reset super(_AlwaysSeq, self).__init__( func, senslist, callinfo=callinfo, sigdict=sigdict) if self.inouts: raise AlwaysSeqError(_error.SigAugAssign, self.inouts) if self.embedded_func: raise AlwaysSeqError(_error.EmbeddedFunction) sigregs = self.sigregs = [] varregs = self.varregs = [] for n in self.outputs: reg = self.symdict[n] if isinstance(reg, _Signal): sigregs.append(reg) elif isinstance(reg, intbv): varregs.append((n, reg, int(reg))) else: assert _isListOfSigs(reg) for e in reg: sigregs.append(e) def reset_sigs(self): for s in self.sigregs: s.next = s._init def reset_vars(self): for v in self.varregs: # only intbv's for now _, reg, init = v reg._val = init def genfunc_reset(self): senslist = self.senslist if len(senslist) == 1: senslist = senslist[0] reset_sigs = self.reset_sigs reset_vars = self.reset_vars func = self.func while 1: yield senslist if self.reset == self.reset.active: reset_sigs() reset_vars() else: func() def genfunc_no_reset(self): senslist = self.senslist assert len(senslist) == 1 senslist = senslist[0] func = self.func while 1: yield senslist func() myhdl-0.11/myhdl/_bin.py000066400000000000000000000031711347432460400151570ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ module with the bin function. """ from myhdl._compat import long def _int2bitstring(num): if num == 0: return '0' if abs(num) == 1: return '1' bits = [] p, q = divmod(num, 2) bits.append(str(q)) while not (abs(p) == 1): p, q = divmod(p, 2) bits.append(str(q)) bits.append('1') bits.reverse() return ''.join(bits) def bin(num, width=0): """Return a binary string representation. num -- number to convert Optional parameter: width -- specifies the desired string (sign bit padding) """ num = long(num) s = _int2bitstring(num) if width: pad = '0' if num < 0: pad = '1' return (width - len(s)) * pad + s return s myhdl-0.11/myhdl/_block.py000066400000000000000000000311411347432460400154770ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2016 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Block with the @block decorator function. """ from __future__ import absolute_import, print_function import inspect #from functools import wraps import functools import myhdl from myhdl._compat import PY2 from myhdl import BlockError, BlockInstanceError, Cosimulation from myhdl._instance import _Instantiator from myhdl._util import _flatten from myhdl._extractHierarchy import (_makeMemInfo, _UserVerilogCode, _UserVhdlCode, _UserVerilogInstance, _UserVhdlInstance) from myhdl._Signal import _Signal, _isListOfSigs from weakref import WeakValueDictionary class _error: pass _error.ArgType = "%s: A block should return block or instantiator objects" _error.InstanceError = "%s: subblock %s should be encapsulated in a block decorator" class _CallInfo(object): def __init__(self, name, modctxt, symdict): self.name = name self.modctxt = modctxt self.symdict = symdict def _getCallInfo(): """Get info on the caller of a BlockInstance. A BlockInstance should be used in a block context. This function gets the required info from the caller It uses the frame stack: 0: this function 1: block instance constructor 2: the decorator function call 3: the function that defines instances 4: the caller of the block function, e.g. a BlockInstance. """ stack = inspect.stack() # caller may be undefined if instantiation from a Python module callerrec = None funcrec = stack[3] name = funcrec[3] if len(stack) > 4: callerrec = stack[4] # special case for list comprehension's extra scope in PY3 if name == '': if not PY2: funcrec = stack[4] if len(stack) > 5: callerrec = stack[5] name = funcrec[3] frame = funcrec[0] symdict = dict(frame.f_globals) symdict.update(frame.f_locals) modctxt = False if callerrec is not None: f_locals = callerrec[0].f_locals if 'self' in f_locals: modctxt = isinstance(f_locals['self'], _Block) return _CallInfo(name, modctxt, symdict) ### I don't think this is the right place for uniqueifying the name. ### This seems to me to be a conversion concern, not a block concern, and ### there should not be the corresponding global state to be maintained here. ### The name should be whatever it is, which is then uniqueified at ### conversion time. Perhaps this happens already (FIXME - check and fix) ### ~ H Gomersall 24/11/2017 _inst_name_set = set() _name_set = set() def _uniqueify_name(proposed_name): '''Creates a unique block name from the proposed name by appending a suitable number to the end. Every name this function returns is assumed to be used, so will not be returned again. ''' n = 0 while proposed_name in _name_set: proposed_name = proposed_name + '_' + str(n) n += 1 _name_set.add(proposed_name) return proposed_name class _bound_function_wrapper(object): def __init__(self, bound_func, srcfile, srcline): self.srcfile = srcfile self.srcline = srcline self.bound_func = bound_func functools.update_wrapper(self, bound_func) self.calls = 0 # register the block myhdl._simulator._blocks.append(self) self.name_prefix = None self.name = None def __call__(self, *args, **kwargs): name = ( self.name_prefix + '_' + self.bound_func.__name__ + str(self.calls)) self.calls += 1 # See concerns above about uniqueifying name = _uniqueify_name(name) return _Block(self.bound_func, self, name, self.srcfile, self.srcline, *args, **kwargs) class block(object): def __init__(self, func): self.srcfile = inspect.getsourcefile(func) self.srcline = inspect.getsourcelines(func)[0] self.func = func functools.update_wrapper(self, func) self.calls = 0 self.name = None # register the block myhdl._simulator._blocks.append(self) self.bound_functions = WeakValueDictionary() def __get__(self, instance, owner): bound_key = (id(instance), id(owner)) if bound_key not in self.bound_functions: bound_func = self.func.__get__(instance, owner) function_wrapper = _bound_function_wrapper( bound_func, self.srcfile, self.srcline) self.bound_functions[bound_key] = function_wrapper proposed_inst_name = owner.__name__ + '0' n = 1 while proposed_inst_name in _inst_name_set: proposed_inst_name = owner.__name__ + str(n) n += 1 function_wrapper.name_prefix = proposed_inst_name _inst_name_set.add(proposed_inst_name) else: function_wrapper = self.bound_functions[bound_key] bound_func = self.bound_functions[bound_key] return function_wrapper def __call__(self, *args, **kwargs): name = self.func.__name__ + str(self.calls) self.calls += 1 # See concerns above about uniqueifying name = _uniqueify_name(name) return _Block(self.func, self, name, self.srcfile, self.srcline, *args, **kwargs) class _Block(object): def __init__(self, func, deco, name, srcfile, srcline, *args, **kwargs): calls = deco.calls self.func = func self.args = args self.kwargs = kwargs self.__doc__ = func.__doc__ callinfo = _getCallInfo() self.callinfo = callinfo self.modctxt = callinfo.modctxt self.callername = callinfo.name self.symdict = None self.sigdict = {} self.memdict = {} self.name = self.__name__ = name # flatten, but keep BlockInstance objects self.subs = _flatten(func(*args, **kwargs)) self._verifySubs() self._updateNamespaces() self.verilog_code = self.vhdl_code = None self.sim = None if hasattr(deco, 'verilog_code'): self.verilog_code = _UserVerilogCode(deco.verilog_code, self.symdict, func.__name__, func, srcfile, srcline) if hasattr(deco, 'vhdl_code'): self.vhdl_code = _UserVhdlCode(deco.vhdl_code, self.symdict, func.__name__, func, srcfile, srcline) if hasattr(deco, 'verilog_instance'): self.verilog_code = _UserVerilogInstance(deco.vhdl_instance, self.symdict, func.__name__, func, srcfile, srcline) if hasattr(deco, 'vhdl_instance'): self.vhdl_code = _UserVhdlInstance(deco.vhdl_instance, self.symdict, func.__name__, func, srcfile, srcline) self._config_sim = {'trace': False} def _verifySubs(self): for inst in self.subs: if not isinstance(inst, (_Block, _Instantiator, Cosimulation)): raise BlockError(_error.ArgType % (self.name,)) if isinstance(inst, (_Block, _Instantiator)): if not inst.modctxt: raise BlockError(_error.InstanceError % (self.name, inst.callername)) def _updateNamespaces(self): # dicts to keep track of objects used in Instantiator objects usedsigdict = {} usedlosdict = {} for inst in self.subs: # the symdict of a block instance is defined by # the call context of its instantiations if isinstance(inst, Cosimulation): continue # ignore if self.symdict is None: self.symdict = inst.callinfo.symdict if isinstance(inst, _Instantiator): usedsigdict.update(inst.sigdict) usedlosdict.update(inst.losdict) if self.symdict is None: self.symdict = {} # Special case: due to attribute reference transformation, the # sigdict and losdict from Instantiator objects may contain new # references. Therefore, update the symdict with them. # To be revisited. self.symdict.update(usedsigdict) self.symdict.update(usedlosdict) # Infer sigdict and memdict, with compatibility patches from _extractHierarchy for n, v in self.symdict.items(): if isinstance(v, _Signal): self.sigdict[n] = v if n in usedsigdict: v._markUsed() if _isListOfSigs(v): m = _makeMemInfo(v) self.memdict[n] = m if n in usedlosdict: m._used = True def _inferInterface(self): from myhdl.conversion._analyze import _analyzeTopFunc intf = _analyzeTopFunc(self.func, *self.args, **self.kwargs) self.argnames = intf.argnames self.argdict = intf.argdict # Public methods # The puropse now is to define the API, optimizations later def _clear(self): """ Clear a number of 'global' attributes. This is a workaround function for cleaning up before converts. """ # workaround: elaborate again for the side effect on signal attibutes self.func(*self.args, **self.kwargs) # reset number of calls in all blocks for b in myhdl._simulator._blocks: b.calls = 0 def verify_convert(self): self._clear() return myhdl.conversion.verify(self) def analyze_convert(self): self._clear() return myhdl.conversion.analyze(self) def convert(self, hdl='Verilog', **kwargs): """Converts this BlockInstance to another HDL Args: hdl (Optional[str]): Target HDL. Defaults to Verilog path (Optional[str]): Destination folder. Defaults to current working dir. name (Optional[str]): Module and output file name. Defaults to `self.mod.__name__` trace(Optional[bool]): Verilog only. Whether the testbench should dump all signal waveforms. Defaults to False. testbench (Optional[bool]): Verilog only. Specifies whether a testbench should be created. Defaults to True. timescale(Optional[str]): Verilog only. Defaults to '1ns/10ps' """ self._clear() if hdl.lower() == 'vhdl': converter = myhdl.conversion._toVHDL.toVHDL elif hdl.lower() == 'verilog': converter = myhdl.conversion._toVerilog.toVerilog else: raise BlockInstanceError('unknown hdl %s' % hdl) conv_attrs = {} if 'name' in kwargs: conv_attrs['name'] = kwargs.pop('name') conv_attrs['directory'] = kwargs.pop('path', '') if hdl.lower() == 'verilog': conv_attrs['no_testbench'] = not kwargs.pop('testbench', True) conv_attrs['timescale'] = kwargs.pop('timescale', '1ns/10ps') conv_attrs['trace'] = kwargs.pop('trace', False) conv_attrs.update(kwargs) for k, v in conv_attrs.items(): setattr(converter, k, v) return converter(self) def config_sim(self, trace=False, **kwargs) : self._config_sim['trace'] = trace if trace: for k, v in kwargs.items() : setattr(myhdl.traceSignals, k, v) myhdl.traceSignals(self) def run_sim(self, duration=None, quiet=0): if self.sim is None: sim = self #if self._config_sim['trace']: # sim = myhdl.traceSignals(self) self.sim = myhdl._Simulation.Simulation(sim) self.sim.run(duration, quiet) def quit_sim(self): if self.sim is not None: self.sim.quit() myhdl-0.11/myhdl/_compat.py000066400000000000000000000035531347432460400156760ustar00rootroot00000000000000''' ''' import sys import types PY2 = sys.version_info[0] == 2 PYPY = hasattr(sys, 'pypy_translation_info') _identity = lambda x: x if not PY2: string_types = (str,) integer_types = (int,) long = int class_types = (type,) from io import StringIO from os import set_inheritable import builtins def to_bytes(s): return s.encode() def to_str(b): return b.decode() else: string_types = (str, unicode) integer_types = (int, long) long = long class_types = (type, types.ClassType) from cStringIO import StringIO import __builtin__ as builtins to_bytes = _identity to_str = _identity def set_inheritable(fd, inheritable): # This implementation of set_inheritable is based on a code sample in # [PEP 0446](https://www.python.org/dev/peps/pep-0446/) and on the # CPython implementation of that proposal which can be browsed [here] # (hg.python.org/releasing/3.4/file/8671f89107c8/Modules/posixmodule.c#l11130) if sys.platform == "win32": import msvcrt # import ctypes.windll.kernel32 as kernel32 import ctypes windll = ctypes.LibraryLoader(ctypes.WinDLL) SetHandleInformation = windll.kernel32.SetHandleInformation HANDLE_FLAG_INHERIT = 1 if SetHandleInformation(msvcrt.get_osfhandle(fd), HANDLE_FLAG_INHERIT, 1 if inheritable else 0) == 0: raise IOError("Failed on HANDLE_FLAG_INHERIT") else: import fcntl fd_flags = fcntl.fcntl(fd, fcntl.F_GETFD) if inheritable: fd_flags &= ~fcntl.FD_CLOEXEC else: fd_flags |= fcntl.FD_CLOEXEC fcntl.fcntl(fd, fcntl.F_SETFD, fd_flags) myhdl-0.11/myhdl/_concat.py000066400000000000000000000052401347432460400156550ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA # pylint: disable=redefined-builtin """ module with the concat function. """ from __future__ import absolute_import from myhdl._compat import integer_types from myhdl._intbv import intbv from myhdl._Signal import _Signal from myhdl._compat import long def concat(base, *args): if isinstance(base, intbv): basewidth = base._nrbits val = base._val elif isinstance(base, integer_types): if isinstance(base, bool): basewidth = 1 else: basewidth = 0 val = base elif isinstance(base, _Signal): basewidth = base._nrbits if isinstance(base._val, intbv): val = base._val._val else: val = base._val elif isinstance(base, str): basewidth = len(base) val = long(base, 2) else: raise TypeError("concat: inappropriate first argument type: %s" % type(base)) width = 0 for i, arg in enumerate(args): if isinstance(arg, intbv): w = arg._nrbits v = arg._val elif isinstance(arg, _Signal): w = arg._nrbits if isinstance(arg._val, intbv): v = arg._val._val else: v = arg._val elif isinstance(arg, bool): w = 1 v = arg elif isinstance(arg, str): w = len(arg) v = long(arg, 2) else: raise TypeError("concat: inappropriate argument type: %s" % type(arg)) if not w: raise TypeError("concat: arg on pos %d should have length" % (i + 1)) width += w val = val << w | v & (long(1) << w) - 1 if basewidth: return intbv(val, _nrbits=basewidth + width) else: return intbv(val) myhdl-0.11/myhdl/_delay.py000066400000000000000000000026651347432460400155140ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Module that provides the delay class.""" from __future__ import absolute_import from myhdl._compat import integer_types _errmsg = "arg of delay constructor should be a natural integeer" class delay(object): """ Class to model delay in yield statements. """ def __init__(self, val): """ Return a delay instance. Required parameters: val -- a natural integer representing the desired delay """ if not isinstance(val, integer_types) or val < 0: raise TypeError(_errmsg) self._time = val myhdl-0.11/myhdl/_enum.py000066400000000000000000000154031347432460400153540ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Module that implements enum. """ from __future__ import absolute_import from myhdl._bin import bin from myhdl._Signal import _Signal from myhdl._compat import string_types # from myhdl.conversion._VHDLNameValidation import _nameValid class EnumType(object): def __init__(self): raise TypeError("class EnumType is only intended for type checking on subclasses") class EnumItemType(object): def __init__(self): raise TypeError("class EnumItemType is only intended for type checking on subclasses") supported_encodings = ("binary", "one_hot", "one_cold") def enum(*names, **kwargs): # args = args encoding = kwargs.get('encoding', None) if encoding is not None and encoding not in supported_encodings: raise ValueError("Unsupported enum encoding: %s\n Supported encodings: %s" % (encoding, supported_encodings)) if encoding in ("one_hot", "one_cold"): nrbits = len(names) else: # binary as default nrbits = len(bin(len(names) - 1)) codedict = {} i = 0 for name in names: if not isinstance(name, string_types): raise TypeError() if name in codedict: raise ValueError("enum literals should be unique") if encoding == "one_hot": code = bin(1 << i, nrbits) elif encoding == "one_cold": code = bin(~(1 << i), nrbits) else: # binary as default code = bin(i, nrbits) if len(code) > nrbits: code = code[-nrbits:] codedict[name] = code i += 1 class EnumItem(EnumItemType): def __init__(self, index, name, val, type): self._index = index self._name = name self._val = val self._nrbits = type._nrbits self._nritems = type._nritems self._type = type def __hash__(self): return hash((self._type, self._index)) def __repr__(self): return "'{}'".format(self._name) # __str__ = __repr__ def __str__(self): return self._name def __int__(self): return int(self._val, 2) def __hex__(self): return hex(int(self._val, 2)) def _toVerilog(self, dontcare=False): val = self._val if dontcare: if encoding == "one_hot": val = val.replace('0', '?') elif encoding == "one_cold": val = val.replace('1', '?') return "%d'b%s" % (self._nrbits, val) def _toVHDL(self): return self._name def __copy__(self): return self def __deepcopy__(self, memo=None): return self def _notImplementedCompare(self, other): raise NotImplementedError __le__ = __ge__ = __lt__ = __gt__ = _notImplementedCompare def __eq__(self, other): if isinstance(other, _Signal): other = other._val if not isinstance(other, EnumItemType) or type(self) is not type(other): raise TypeError("Type mismatch in enum item comparison") return self is other def __ne__(self, other): if isinstance(other, _Signal): other = other._val if not isinstance(other, EnumItemType) or type(self) is not type(other): raise TypeError("Type mismatch in enum item comparison") return self is not other class Enum(EnumType): def __init__(self, names, codedict, nrbits, encoding): self.__dict__['_names'] = names self.__dict__['_nrbits'] = nrbits self.__dict__['_nritems'] = len(names) self.__dict__['_codedict'] = codedict self.__dict__['_encoding'] = encoding self.__dict__['_name'] = None for index, name in enumerate(names): val = codedict[name] self.__dict__[name] = EnumItem(index, name, val, self) def __setattr__(self, attr, val): raise AttributeError("Cannot assign to enum attributes") def __len__(self): return len(self._names) def __repr__(self): return 'enum({})'.format(",".join(["'{}'".format(n) for n in self._names])) # __str__ = __repr__ def __str__(self): return "" % ", ".join(self._names) def _setName(self, name): typename = "t_enum_%s" % name self.__dict__['_name'] = typename # _toVHDL = __str__ # def _toVHDL(self): # typename = self.__dict__['_name'] # # check if a member name conflicts with a reserved VHDL keyword # # for name in self.names: # # # watch out _nameValid() will add every name to a check-list # # # which will force you to be inventive with state names ... # # # e.g. the typical 'IDLE' can only be used once # # # so let's pre-fix the enum name # # # we could have modified _nameValid() to take a default boolean argument # # _nameValid(''.join((typename, '.', name))) # # enumtypedecl = "type %s is (\n " % typename # enumtypedecl += ",\n ".join(self._names) # enumtypedecl += "\n);" # if self._encoding is not None: # codes = " ".join([self._codedict[name] for name in self._names]) # enumtypedecl += '\nattribute enum_encoding of %s: type is "%s";' % (typename, codes) # return enumtypedecl def reftype(self): typename = self.__dict__['_name'] codes = None if self._encoding is not None: codes = " ".join([self._codedict[name] for name in self._names]) return (typename, (self._names) , codes) return Enum(names, codedict, nrbits, encoding) myhdl-0.11/myhdl/_extractHierarchy.py000066400000000000000000000306161347432460400177240ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ myhdl _extractHierarchy module. """ from __future__ import absolute_import import sys import inspect import string from myhdl import ExtractHierarchyError, ToVerilogError, ToVHDLError from myhdl._Signal import _Signal, _isListOfSigs from myhdl._util import _flatten from myhdl._util import _genfunc from myhdl._misc import _isGenSeq from myhdl._resolverefs import _resolveRefs from myhdl._getcellvars import _getCellVars _profileFunc = None class _error: pass _error.NoInstances = "No instances found" _error.InconsistentHierarchy = "Inconsistent hierarchy - are all instances returned ?" _error.InconsistentToplevel = "Inconsistent top level %s for %s - should be 1" class _Instance(object): __slots__ = ['level', 'obj', 'subs', 'sigdict', 'memdict', 'name'] def __init__(self, level, obj, subs, sigdict, memdict): self.level = level self.obj = obj self.subs = subs self.sigdict = sigdict self.memdict = memdict self.name = None _memInfoMap = {} class _MemInfo(object): __slots__ = ['mem', 'name', 'elObj', 'depth', '_used', '_driven', '_read'] def __init__(self, mem): self.mem = mem self.name = None self.depth = len(mem) self.elObj = mem[0] self._used = False self._driven = None self._read = None def _getMemInfo(mem): return _memInfoMap[id(mem)] def _makeMemInfo(mem): key = id(mem) if key not in _memInfoMap: _memInfoMap[key] = _MemInfo(mem) return _memInfoMap[key] def _isMem(mem): return id(mem) in _memInfoMap _userCodeMap = {'verilog': {}, 'vhdl': {} } class _UserCode(object): __slots__ = ['code', 'namespace', 'funcname', 'func', 'sourcefile', 'sourceline'] def __init__(self, code, namespace, funcname, func, sourcefile, sourceline): self.code = code self.namespace = namespace self.sourcefile = sourcefile self.func = func self.funcname = funcname self.sourceline = sourceline def __str__(self): try: code = self._interpolate() except: type, value, tb = sys.exc_info() info = "in file %s, function %s starting on line %s:\n " % \ (self.sourcefile, self.funcname, self.sourceline) msg = "%s: %s" % (type, value) self.raiseError(msg, info) code = "\n%s\n" % code return code def _scrub_namespace(self): for nm, obj in self.namespace.items(): if _isMem(obj): memi = _getMemInfo(obj) self.namespace[nm] = memi.name def _interpolate(self): self._scrub_namespace() return string.Template(self.code).substitute(self.namespace) class _UserCodeDepr(_UserCode): def _interpolate(self): return self.code % self.namespace class _UserVerilogCode(_UserCode): def raiseError(self, msg, info): raise ToVerilogError("Error in user defined Verilog code", msg, info) class _UserVhdlCode(_UserCode): def raiseError(self, msg, info): raise ToVHDLError("Error in user defined VHDL code", msg, info) class _UserVerilogCodeDepr(_UserVerilogCode, _UserCodeDepr): pass class _UserVhdlCodeDepr(_UserVhdlCode, _UserCodeDepr): pass class _UserVerilogInstance(_UserVerilogCode): def __str__(self): args = inspect.getargspec(self.func)[0] s = "%s %s(" % (self.funcname, self.code) sep = '' for arg in args: if arg in self.namespace and isinstance(self.namespace[arg], _Signal): signame = self.namespace[arg]._name s += sep sep = ',' s += "\n .%s(%s)" % (arg, signame) s += "\n);\n\n" return s class _UserVhdlInstance(_UserVhdlCode): def __str__(self): args = inspect.getargspec(self.func)[0] s = "%s: entity work.%s(MyHDL)\n" % (self.code, self.funcname) s += " port map (" sep = '' for arg in args: if arg in self.namespace and isinstance(self.namespace[arg], _Signal): signame = self.namespace[arg]._name s += sep sep = ',' s += "\n %s=>%s" % (arg, signame) s += "\n );\n\n" return s def _addUserCode(specs, arg, funcname, func, frame): classMap = { '__verilog__': _UserVerilogCodeDepr, '__vhdl__': _UserVhdlCodeDepr, 'verilog_code': _UserVerilogCode, 'vhdl_code': _UserVhdlCode, 'verilog_instance': _UserVerilogInstance, 'vhdl_instance': _UserVhdlInstance, } namespace = frame.f_globals.copy() namespace.update(frame.f_locals) sourcefile = inspect.getsourcefile(frame) sourceline = inspect.getsourcelines(frame)[1] for hdl in _userCodeMap: oldspec = "__%s__" % hdl codespec = "%s_code" % hdl instancespec = "%s_instance" % hdl spec = None # XXX add warning logic if instancespec in specs: spec = instancespec elif codespec in specs: spec = codespec elif oldspec in specs: spec = oldspec if spec: assert id(arg) not in _userCodeMap[hdl] code = specs[spec] _userCodeMap[hdl][id(arg)] = classMap[spec]( code, namespace, funcname, func, sourcefile, sourceline) class _CallFuncVisitor(object): def __init__(self): self.linemap = {} def visitAssign(self, node): if isinstance(node.expr, ast.CallFunc): self.lineno = None self.visit(node.expr) self.linemap[self.lineno] = node.lineno def visitName(self, node): self.lineno = node.lineno class _HierExtr(object): def __init__(self, name, dut, *args, **kwargs): global _profileFunc _memInfoMap.clear() for hdl in _userCodeMap: _userCodeMap[hdl].clear() self.skipNames = ('always_comb', 'instance', 'always_seq', '_always_seq_decorator', 'always', '_always_decorator', 'instances', 'processes', 'posedge', 'negedge') self.skip = 0 self.hierarchy = hierarchy = [] self.absnames = absnames = {} self.level = 0 _profileFunc = self.extractor sys.setprofile(_profileFunc) _top = dut(*args, **kwargs) sys.setprofile(None) if not hierarchy: raise ExtractHierarchyError(_error.NoInstances) self.top = _top # streamline hierarchy hierarchy.reverse() # walk the hierarchy to define relative and absolute names names = {} top_inst = hierarchy[0] obj, subs = top_inst.obj, top_inst.subs names[id(obj)] = name absnames[id(obj)] = name if not top_inst.level == 1: raise ExtractHierarchyError(_error.InconsistentToplevel % (top_inst.level, name)) for inst in hierarchy: obj, subs = inst.obj, inst.subs if id(obj) not in names: raise ExtractHierarchyError(_error.InconsistentHierarchy) inst.name = names[id(obj)] tn = absnames[id(obj)] for sn, so in subs: names[id(so)] = sn absnames[id(so)] = "%s_%s" % (tn, sn) if isinstance(so, (tuple, list)): for i, soi in enumerate(so): sni = "%s_%s" % (sn, i) names[id(soi)] = sni absnames[id(soi)] = "%s_%s_%s" % (tn, sn, i) def extractor(self, frame, event, arg): if event == "call": funcname = frame.f_code.co_name # skip certain functions if funcname in self.skipNames: self.skip += 1 if not self.skip: self.level += 1 elif event == "return": funcname = frame.f_code.co_name func = frame.f_globals.get(funcname) if func is None: # Didn't find a func in the global space, try the local "self" # argument and see if it has a method called *funcname* obj = frame.f_locals.get('self') if hasattr(obj, funcname): func = getattr(obj, funcname) if not self.skip: isGenSeq = _isGenSeq(arg) if isGenSeq: specs = {} for hdl in _userCodeMap: spec = "__%s__" % hdl if spec in frame.f_locals and frame.f_locals[spec]: specs[spec] = frame.f_locals[spec] spec = "%s_code" % hdl if func and hasattr(func, spec) and getattr(func, spec): specs[spec] = getattr(func, spec) spec = "%s_instance" % hdl if func and hasattr(func, spec) and getattr(func, spec): specs[spec] = getattr(func, spec) if specs: _addUserCode(specs, arg, funcname, func, frame) # building hierarchy only makes sense if there are generators if isGenSeq and arg: sigdict = {} memdict = {} symdict = frame.f_globals.copy() symdict.update(frame.f_locals) cellvars = [] # All nested functions will be in co_consts if func: local_gens = [] consts = func.__code__.co_consts for item in _flatten(arg): genfunc = _genfunc(item) if genfunc.__code__ in consts: local_gens.append(item) if local_gens: cellvarlist = _getCellVars(symdict, local_gens) cellvars.extend(cellvarlist) objlist = _resolveRefs(symdict, local_gens) cellvars.extend(objlist) # for dict in (frame.f_globals, frame.f_locals): for n, v in symdict.items(): # extract signals and memories # also keep track of whether they are used in generators # only include objects that are used in generators # if not n in cellvars: # continue if isinstance(v, _Signal): sigdict[n] = v if n in cellvars: v._markUsed() if _isListOfSigs(v): m = _makeMemInfo(v) memdict[n] = m if n in cellvars: m._used = True subs = [] for n, sub in frame.f_locals.items(): for elt in _inferArgs(arg): if elt is sub: subs.append((n, sub)) inst = _Instance(self.level, arg, subs, sigdict, memdict) self.hierarchy.append(inst) self.level -= 1 if funcname in self.skipNames: self.skip -= 1 def _inferArgs(arg): c = [arg] if isinstance(arg, (tuple, list)): c += list(arg) return c myhdl-0.11/myhdl/_getHierarchy.py000066400000000000000000000043611347432460400170270ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2016 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ myhdl _getHierarchy module. """ from __future__ import absolute_import from myhdl._extractHierarchy import _Instance from myhdl._block import _Block class _Hierarchy(object): def __init__(self, name, modinst): self.top = modinst self.hierarchy = hierarchy = [] self.absnames = absnames = {} _getHierarchyHelper(1, modinst, hierarchy) # compatibility with _extractHierarchy # walk the hierarchy to define relative and absolute names names = {} top_inst = hierarchy[0] obj, subs = top_inst.obj, top_inst.subs names[id(obj)] = name absnames[id(obj)] = name for inst in hierarchy: obj, subs = inst.obj, inst.subs inst.name = names[id(obj)] tn = absnames[id(obj)] for sn, so in subs: names[id(so)] = sn absnames[id(so)] = "%s_%s" % (tn, sn) # print (names) # print(absnames) def _getHierarchy(name, modinst): h = _Hierarchy(name, modinst) return h def _getHierarchyHelper(level, modinst, hierarchy): subs = [(s.name, s) for s in modinst.subs] inst = _Instance(level, modinst, subs, modinst.sigdict, modinst.memdict) hierarchy.append(inst) for inst in modinst.subs: if isinstance(inst, _Block): _getHierarchyHelper(level + 1, inst, hierarchy) myhdl-0.11/myhdl/_getcellvars.py000066400000000000000000000011221347432460400167140ustar00rootroot00000000000000from __future__ import absolute_import import ast from myhdl._util import _flatten class Data(): pass def _getCellVars(symdict, arg): gens = _flatten(arg) data = Data() data.symdict = symdict v = _GetCellVars(data) for gen in gens: v.visit(gen.ast) return list(data.objset) class _GetCellVars(ast.NodeVisitor): def __init__(self, data): self.data = data self.data.objset = set() def visit_Name(self, node): if node.id in self.data.symdict: self.data.objset.add(node.id) self.generic_visit(node) myhdl-0.11/myhdl/_instance.py000066400000000000000000000076311347432460400162200ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Module with the always function. """ from __future__ import absolute_import import inspect from types import FunctionType from myhdl import InstanceError from myhdl._util import _isGenFunc, _makeAST from myhdl._Waiter import _inferWaiter from myhdl._resolverefs import _AttrRefTransformer from myhdl._visitors import _SigNameVisitor class _error: pass _error.NrOfArgs = "decorated generator function should not have arguments" _error.ArgType = "decorated object should be a generator function" class _CallInfo(object): def __init__(self, name, modctxt, symdict): self.name = name self.modctxt = modctxt self.symdict = symdict def _getCallInfo(): """Get info on the caller of an Instantiator. An Instantiator should be used in a block context. This function gets the required info about the caller. It uses the frame stack: 0: this function 1: the instantiator decorator 2: the block function that defines instances 3: the caller of the block function, e.g. the BlockInstance. """ from myhdl import _block funcrec = inspect.stack()[2] name = funcrec[3] frame = funcrec[0] symdict = dict(frame.f_globals) symdict.update(frame.f_locals) modctxt = False callerrec = inspect.stack()[3] f_locals = callerrec[0].f_locals if 'self' in f_locals: modctxt = isinstance(f_locals['self'], _block._Block) return _CallInfo(name, modctxt, symdict) def instance(genfunc): callinfo = _getCallInfo() if not isinstance(genfunc, FunctionType): raise InstanceError(_error.ArgType) if not _isGenFunc(genfunc): raise InstanceError(_error.ArgType) if genfunc.__code__.co_argcount > 0: raise InstanceError(_error.NrOfArgs) return _Instantiator(genfunc, callinfo=callinfo) class _Instantiator(object): def __init__(self, genfunc, callinfo): self.callinfo = callinfo self.callername = callinfo.name self.modctxt = callinfo.modctxt self.genfunc = genfunc self.gen = genfunc() # infer symdict f = self.funcobj varnames = f.__code__.co_varnames symdict = {} for n, v in callinfo.symdict.items(): if n not in varnames: symdict[n] = v self.symdict = symdict # print modname, genfunc.__name__ tree = self.ast # print ast.dump(tree) v = _AttrRefTransformer(self) v.visit(tree) v = _SigNameVisitor(self.symdict) v.visit(tree) self.inputs = v.inputs self.outputs = v.outputs self.inouts = v.inouts self.embedded_func = v.embedded_func self.sigdict = v.sigdict self.losdict = v.losdict @property def name(self): return self.funcobj.__name__ @property def funcobj(self): return self.genfunc @property def waiter(self): return self._waiter()(self.gen) def _waiter(self): return _inferWaiter @property def ast(self): return _makeAST(self.funcobj) myhdl-0.11/myhdl/_intbv.py000066400000000000000000000412721347432460400155350ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2015 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Module with the intbv class """ from __future__ import absolute_import, division from myhdl._compat import long, integer_types, string_types, builtins from myhdl._bin import bin class intbv(object): #__slots__ = ('_val', '_min', '_max', '_nrbits', '_handleBounds') def __init__(self, val=0, min=None, max=None, _nrbits=0): if _nrbits: self._min = 0 self._max = 2**_nrbits else: self._min = min self._max = max if max is not None and min is not None: if min >= 0: _nrbits = len(bin(max - 1)) elif max <= 1: _nrbits = len(bin(min)) else: # make sure there is a leading zero bit in positive numbers _nrbits = builtins.max(len(bin(max - 1)) + 1, len(bin(min))) if isinstance(val, integer_types): self._val = val elif isinstance(val, string_types): mval = val.replace('_', '') self._val = long(mval, 2) _nrbits = len(mval) elif isinstance(val, intbv): self._val = val._val self._min = val._min self._max = val._max _nrbits = val._nrbits else: raise TypeError("intbv constructor arg should be int or string") self._nrbits = _nrbits self._handleBounds() # support for the 'min' and 'max' attribute @property def max(self): return self._max @property def min(self): return self._min def _handleBounds(self): if self._max is not None: if self._val >= self._max: raise ValueError("intbv value %s >= maximum %s" % (self._val, self._max)) if self._min is not None: if self._val < self._min: raise ValueError("intbv value %s < minimum %s" % (self._val, self._min)) def _hasFullRange(self): min, max = self._min, self._max if max <= 0: return False if min not in (0, -max): return False return max & max - 1 == 0 # hash def __hash__(self): raise TypeError("intbv objects are unhashable") # copy methods def __copy__(self): c = type(self)(self._val) c._min = self._min c._max = self._max c._nrbits = self._nrbits return c def __deepcopy__(self, visit): c = type(self)(self._val) c._min = self._min c._max = self._max c._nrbits = self._nrbits return c # iterator method def __iter__(self): if not self._nrbits: raise TypeError("Cannot iterate over unsized intbv") return iter([self[i] for i in range(self._nrbits - 1, -1, -1)]) # logical testing def __bool__(self): return bool(self._val) __nonzero__ = __bool__ # length def __len__(self): return self._nrbits # indexing and slicing methods def __getitem__(self, key): if isinstance(key, slice): i, j = key.start, key.stop if j is None: # default j = 0 j = int(j) if j < 0: raise ValueError("intbv[i:j] requires j >= 0\n" " j == %s" % j) if i is None: # default return intbv(self._val >> j) i = int(i) if i <= j: raise ValueError("intbv[i:j] requires i > j\n" " i, j == %s, %s" % (i, j)) res = intbv((self._val & (long(1) << i) - 1) >> j, _nrbits=i - j) return res else: i = int(key) res = bool((self._val >> i) & 0x1) return res def __setitem__(self, key, val): # convert val to int to avoid confusion with intbv or Signals val = int(val) if isinstance(key, slice): i, j = key.start, key.stop if j is None: # default j = 0 j = int(j) if j < 0: raise ValueError("intbv[i:j] = v requires j >= 0\n" " j == %s" % j) if i is None: # default q = self._val % (long(1) << j) self._val = val * (long(1) << j) + q self._handleBounds() return i = int(i) if i <= j: raise ValueError("intbv[i:j] = v requires i > j\n" " i, j, v == %s, %s, %s" % (i, j, val)) lim = (long(1) << (i - j)) if val >= lim or val < -lim: raise ValueError("intbv[i:j] = v abs(v) too large\n" " i, j, v == %s, %s, %s" % (i, j, val)) mask = (lim - 1) << j self._val &= ~mask self._val |= (val << j) self._handleBounds() else: i = int(key) if val == 1: self._val |= (long(1) << i) elif val == 0: self._val &= ~(long(1) << i) else: raise ValueError("intbv[i] = v requires v in (0, 1)\n" " i == %s " % i) self._handleBounds() # integer-like methods def __add__(self, other): if isinstance(other, intbv): return self._val + other._val else: return self._val + other def __radd__(self, other): return other + self._val def __sub__(self, other): if isinstance(other, intbv): return self._val - other._val else: return self._val - other def __rsub__(self, other): return other - self._val def __mul__(self, other): if isinstance(other, intbv): return self._val * other._val else: return self._val * other def __rmul__(self, other): return other * self._val def __truediv__(self, other): if isinstance(other, intbv): return self._val / other._val else: return self._val / other def __rtruediv__(self, other): return other / self._val def __floordiv__(self, other): if isinstance(other, intbv): return self._val // other._val else: return self._val // other def __rfloordiv__(self, other): return other // self._val def __mod__(self, other): if isinstance(other, intbv): return self._val % other._val else: return self._val % other def __rmod__(self, other): return other % self._val # divmod def __pow__(self, other): if isinstance(other, intbv): return self._val ** other._val else: return self._val ** other def __rpow__(self, other): return other ** self._val def __lshift__(self, other): if isinstance(other, intbv): return intbv(long(self._val) << other._val) else: return intbv(long(self._val) << other) def __rlshift__(self, other): return other << self._val def __rshift__(self, other): if isinstance(other, intbv): return intbv(self._val >> other._val) else: return intbv(self._val >> other) def __rrshift__(self, other): return other >> self._val def __and__(self, other): if isinstance(other, intbv): return intbv(self._val & other._val) else: return intbv(self._val & other) def __rand__(self, other): return intbv(other & self._val) def __or__(self, other): if isinstance(other, intbv): return intbv(self._val | other._val) else: return intbv(self._val | other) def __ror__(self, other): return intbv(other | self._val) def __xor__(self, other): if isinstance(other, intbv): return intbv(self._val ^ other._val) else: return intbv(self._val ^ other) def __rxor__(self, other): return intbv(other ^ self._val) def __iadd__(self, other): if isinstance(other, intbv): self._val += other._val else: self._val += other self._handleBounds() return self def __isub__(self, other): if isinstance(other, intbv): self._val -= other._val else: self._val -= other self._handleBounds() return self def __imul__(self, other): if isinstance(other, intbv): self._val *= other._val else: self._val *= other self._handleBounds() return self def __ifloordiv__(self, other): if isinstance(other, intbv): self._val //= other._val else: self._val //= other self._handleBounds() return self def __idiv__(self, other): raise TypeError("intbv: Augmented classic division not supported") def __itruediv__(self, other): raise TypeError("intbv: Augmented true division not supported") def __imod__(self, other): if isinstance(other, intbv): self._val %= other._val else: self._val %= other self._handleBounds() return self def __ipow__(self, other, modulo=None): # XXX why 3rd param required? # unused but needed in 2.2, not in 2.3 if isinstance(other, intbv): self._val **= other._val else: self._val **= other if not isinstance(self._val, integer_types): raise ValueError("intbv value should be integer") self._handleBounds() return self def __iand__(self, other): if isinstance(other, intbv): self._val &= other._val else: self._val &= other self._handleBounds() return self def __ior__(self, other): if isinstance(other, intbv): self._val |= other._val else: self._val |= other self._handleBounds() return self def __ixor__(self, other): if isinstance(other, intbv): self._val ^= other._val else: self._val ^= other self._handleBounds() return self def __ilshift__(self, other): self._val = long(self._val) if isinstance(other, intbv): self._val <<= other._val else: self._val <<= other self._handleBounds() return self def __irshift__(self, other): if isinstance(other, intbv): self._val >>= other._val else: self._val >>= other self._handleBounds() return self def __neg__(self): return -self._val def __pos__(self): return self._val def __abs__(self): return abs(self._val) def __invert__(self): if self._nrbits and self._min >= 0: return intbv(~self._val & (long(1) << self._nrbits) - 1) else: return intbv(~self._val) def __int__(self): return int(self._val) def __long__(self): return long(self._val) def __float__(self): return float(self._val) # XXX __complex__ seems redundant ??? (complex() works as such?) def __oct__(self): return oct(self._val) def __hex__(self): return hex(self._val) def __index__(self): return int(self._val) # comparisons def __eq__(self, other): if isinstance(other, intbv): return self._val == other._val else: return self._val == other def __ne__(self, other): if isinstance(other, intbv): return self._val != other._val else: return self._val != other def __lt__(self, other): if isinstance(other, intbv): return self._val < other._val else: return self._val < other def __le__(self, other): if isinstance(other, intbv): return self._val <= other._val else: return self._val <= other def __gt__(self, other): if isinstance(other, intbv): return self._val > other._val else: return self._val > other def __ge__(self, other): if isinstance(other, intbv): return self._val >= other._val else: return self._val >= other # representation def __str__(self): # represent in hex format, to handle VHDL long vectors v = int(self._val) nrbits = self._nrbits if nrbits: # represent negative values without minus sign # I would prefer sign extension with hex format, but to # align with Verilog $display I don't do that if v < 0: v = 2**nrbits + v w = (nrbits - 1) // 4 + 1 return "{:0{w}x}".format(v, w=w) else: return "{:x}".format(v) def __repr__(self): return "intbv(" + repr(self._val) + ")" def signed(self): ''' Return new intbv with the values interpreted as signed The intbv.signed() function will classify the value of the intbv instance either as signed or unsigned. If the value is classified as signed it will be returned unchanged as integer value. If the value is considered unsigned, the bits as specified by _nrbits will be considered as 2's complement number and returned. This feature will allow to create slices and have the sliced bits be considered a 2's complement number. The classification is based on the following possible combinations of the min and max value. ----+----+----+----+----+----+----+---- -3 -2 -1 0 1 2 3 1 min max 2 min max 3 min max 4 min max 5 min max 6 min max 7 min max 8 neither min nor max is set 9 only max is set 10 only min is set From the above cases, # 1 and 2 are considered unsigned and the signed() function will convert the value to a signed number. Decision about the sign will be done based on the msb. The msb is based on the _nrbits value. So the test will be if min >= 0 and _nrbits > 0. Then the instance is considered unsigned and the value is returned as 2's complement number. ''' # value is considered unsigned if self.min is not None and self.min >= 0 and self._nrbits: # get 2's complement value of bits msb = self._nrbits - 1 sign = ((self._val >> msb) & 0x1) > 0 # mask off the bits msb-1:lsb, they are always positive mask = (1 << msb) - 1 retVal = self._val & mask # if sign bit is set, subtract the value of the sign bit if sign: retVal -= 1 << msb else: # value is returned just as is retVal = self._val if self._nrbits: M = 2**(self._nrbits - 1) return intbv(retVal, min=-M, max=M) else: return intbv(retVal) def unsigned(self): ''' Return new intbv with the values interpreted as unsigned ''' # value is considered unsigned if self.min is not None and self.min < 0 and self._nrbits: mask = (1 << self._nrbits) - 1 retVal = self._val & mask else: # value is returned just as is retVal = self._val if self._nrbits: return intbv(retVal)[self._nrbits:] else: return intbv(retVal) myhdl-0.11/myhdl/_join.py000066400000000000000000000023331347432460400153450ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Module that provides join class """ class join(object): """ Join trigger objects to form a single trigger object. """ def __init__(self, *args): """ Construct join object *args -- list of trigger object arguments. """ self._args = args def _generator(self): yield join(*self._args) myhdl-0.11/myhdl/_misc.py000066400000000000000000000035671347432460400153530ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ MyHDL miscellaneous public objects. This module provides the following public myhdl objects: instances -- function that returns instances in a generator function downrange -- function that returns a downward range """ from __future__ import absolute_import import inspect from myhdl._Cosimulation import Cosimulation from myhdl._instance import _Instantiator def _isGenSeq(obj): from myhdl._block import _Block if isinstance(obj, (Cosimulation, _Instantiator, _Block)): return True if not isinstance(obj, (list, tuple, set)): return False # if not obj: # return False for e in obj: if not _isGenSeq(e): return False return True def instances(): f = inspect.currentframe() d = inspect.getouterframes(f)[1][0].f_locals l = [] for v in d.values(): if _isGenSeq(v): l.append(v) return l def downrange(start, stop=0, step=1): """ Return a downward range. """ return range(start - 1, stop - 1, -step) myhdl-0.11/myhdl/_modbv.py000066400000000000000000000043121347432460400155140ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2011 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Module with the modbv class """ from __future__ import absolute_import from ._intbv import intbv from ._compat import long class modbv(intbv): __slots__ = [] def _handleBounds(self): lo, hi, val = self._min, self._max, self._val if lo is not None: if val < lo or val >= hi: self._val = (val - lo) % (hi - lo) + lo def __repr__(self): return "modbv(" + repr(self._val) + ")" # indexing and slicing methods # dedicated for modbv to support "declaration by slicing" def __getitem__(self, key): if isinstance(key, slice): i, j = key.start, key.stop if j is None: # default j = 0 j = int(j) if j < 0: raise ValueError("modbv[i:j] requires j >= 0\n" " j == %s" % j) if i is None: # default return modbv(self._val >> j) i = int(i) if i <= j: raise ValueError("modbv[i:j] requires i > j\n" " i, j == %s, %s" % (i, j)) res = modbv((self._val & (long(1) << i) - 1) >> j, _nrbits=i - j) return res else: i = int(key) res = bool((self._val >> i) & 0x1) return res myhdl-0.11/myhdl/_resolverefs.py000066400000000000000000000046751347432460400167600ustar00rootroot00000000000000from __future__ import absolute_import import ast import itertools from types import FunctionType from myhdl._util import _flatten from myhdl._enum import EnumType from myhdl._Signal import SignalType class Data(): pass def _resolveRefs(symdict, arg): gens = _flatten(arg) data = Data() data.symdict = symdict v = _AttrRefTransformer(data) for gen in gens: v.visit(gen.ast) return data.objlist # TODO: Refactor this into two separate nodetransformers, since _resolveRefs # needs only the names, not the objects def _suffixer(name, used_names): suffixed_names = (name + '_renamed{0}'.format(i) for i in itertools.count()) new_names = itertools.chain([name], suffixed_names) return next(s for s in new_names if s not in used_names) class _AttrRefTransformer(ast.NodeTransformer): def __init__(self, data): self.data = data self.data.objlist = [] self.myhdl_types = (EnumType, SignalType) self.name_map = {} def visit_Attribute(self, node): self.generic_visit(node) reserved = ('next', 'posedge', 'negedge', 'max', 'min', 'val', 'signed', 'verilog_code', 'vhdl_code') if node.attr in reserved: return node # Don't handle subscripts for now. if not isinstance(node.value, ast.Name): return node # Don't handle locals if node.value.id not in self.data.symdict: return node obj = self.data.symdict[node.value.id] # Don't handle enums and functions, handle signals as long as it is a new attribute if isinstance(obj, (EnumType, FunctionType)): return node elif isinstance(obj, SignalType): if hasattr(SignalType, node.attr): return node attrobj = getattr(obj, node.attr) orig_name = node.value.id + '.' + node.attr if orig_name not in self.name_map: base_name = node.value.id + '_' + node.attr self.name_map[orig_name] = _suffixer(base_name, self.data.symdict) new_name = self.name_map[orig_name] self.data.symdict[new_name] = attrobj self.data.objlist.append(new_name) new_node = ast.Name(id=new_name, ctx=node.value.ctx) return ast.copy_location(new_node, node) def visit_FunctionDef(self, node): nodes = _flatten(node.body, node.args) for n in nodes: self.visit(n) return node myhdl-0.11/myhdl/_simulator.py000066400000000000000000000023061347432460400164250ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Simulator internals and the now function This module provides the following objects: now -- function that returns the current simulation time """ _signals = [] _blocks = [] _siglist = [] _futureEvents = [] _time = 0 _tracing = 0 _tf = None def now(): """ Return the current simulation time """ return _time myhdl-0.11/myhdl/_traceSignals.py000066400000000000000000000213041347432460400170240ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ myhdl traceSignals block. """ from __future__ import absolute_import from __future__ import print_function import sys import time import os path = os.path import shutil import warnings from myhdl import _simulator, __version__, EnumItemType from myhdl._extractHierarchy import _HierExtr from myhdl import TraceSignalsError from myhdl._ShadowSignal import _TristateSignal, _TristateDriver from myhdl._block import _Block from myhdl._getHierarchy import _getHierarchy _tracing = 0 _profileFunc = None vcdpath = '' class _error: pass _error.TopLevelName = "result of traceSignals call should be assigned to a top level name" _error.ArgType = "traceSignals first argument should be a classic function" _error.MultipleTraces = "Cannot trace multiple instances simultaneously" class _TraceSignalsClass(object): __slot__ = ("name", "directory", "filename", "timescale", "tracelists", "tracebackup" ) def __init__(self): self.name = None self.directory = None self.filename = None self.timescale = "1ns" self.tracelists = True self.tracebackup = True def __call__(self, dut, *args, **kwargs): global _tracing, vcdpath if isinstance(dut, _Block): # now we go bottom-up: so clean up and start over # TODO: consider a warning for the overruled block if _simulator._tracing: _simulator._tracing = 0 _simulator._tf.close() os.remove(vcdpath) else: # deprecated if _tracing: return dut(*args, **kwargs) # skip else: # clean start sys.setprofile(None) from myhdl.conversion import _toVerilog if _toVerilog._converting: raise TraceSignalsError("Cannot use traceSignals while converting to Verilog") if not isinstance(dut, _Block): if not callable(dut): raise TraceSignalsError(_error.ArgType, "got %s" % type(dut)) if _simulator._tracing: raise TraceSignalsError(_error.MultipleTraces) _tracing = 1 try: if self.name is None: name = dut.__name__ if isinstance(dut, _Block): name = dut.func.__name__ else: name = str(self.name) if name is None: raise TraceSignalsError(_error.TopLevelName) if self.directory is None: directory = '' else: directory = self.directory if isinstance(dut, _Block): h = _getHierarchy(name, dut) else: warnings.warn( "\n traceSignals(): Deprecated usage: See http://dev.myhdl.org/meps/mep-114.html", stacklevel=2) h = _HierExtr(name, dut, *args, **kwargs) if self.filename is None: filename = name else: filename = str(self.filename) vcdpath = os.path.join(directory, filename + ".vcd") if path.exists(vcdpath): if self.tracebackup : backup = vcdpath[:-4] + '.' + str(path.getmtime(vcdpath)) + '.vcd' shutil.copyfile(vcdpath, backup) os.remove(vcdpath) vcdfile = open(vcdpath, 'w') _simulator._tracing = 1 _simulator._tf = vcdfile _writeVcdHeader(vcdfile, self.timescale) _writeVcdSigs(vcdfile, h.hierarchy, self.tracelists) finally: _tracing = 0 return h.top traceSignals = _TraceSignalsClass() _codechars = "" for i in range(33, 127): _codechars += chr(i) _mod = len(_codechars) def _genNameCode(): n = 0 while 1: yield _namecode(n) n += 1 def _namecode(n): q, r = divmod(n, _mod) code = _codechars[r] while q > 0: q, r = divmod(q, _mod) code = _codechars[r] + code return code def _writeVcdHeader(f, timescale): print("$date", file=f) print(" %s" % time.asctime(), file=f) print("$end", file=f) print("$version", file=f) print(" MyHDL %s" % __version__, file=f) print("$end", file=f) print("$timescale", file=f) print(" %s" % timescale, file=f) print("$end", file=f) print(file=f) def _getSval(s): if isinstance(s, _TristateSignal): sval = s._orival elif isinstance(s, _TristateDriver): sval = s._sig._orival else: sval = s._val return sval def _writeVcdSigs(f, hierarchy, tracelists): curlevel = 0 namegen = _genNameCode() siglist = [] for inst in hierarchy: level = inst.level name = inst.name sigdict = inst.sigdict memdict = inst.memdict delta = curlevel - level curlevel = level assert(delta >= -1) if delta >= 0: for i in range(delta + 1): print("$upscope $end", file=f) print("$scope module %s $end" % name, file=f) for n, s in sigdict.items(): sval = _getSval(s) if sval is None: raise ValueError("%s of module %s has no initial value" % (n, name)) if not s._tracing: s._tracing = 1 s._code = next(namegen) siglist.append(s) w = s._nrbits # use real for enum strings if w: if not isinstance(sval, EnumItemType): if w == 1: print("$var reg 1 %s %s $end" % (s._code, n), file=f) else: print("$var reg %s %s %s $end" % (w, s._code, n), file=f) else: # 18-04-2014 jb # it is an enum, and as Impulse doesn't know the awkward 'real' representation yet, so let's 'degrade' it to a binary type # 30-04-2014 jb # Impulse now has a 'string'type print("$var string %s %s %s $end" % (w, s._code, n), file=f) # print "30-04-2014 jb: Representing enum as string" # leave a trace else: print("$var real 1 %s %s $end" % (s._code, n), file=f) # Memory dump by Frederik Teichert, http://teichert-ing.de, date: 2011.03.28 # The Value Change Dump standard doesn't support multidimensional arrays so # all memories are flattened and renamed. if tracelists: for n in memdict.keys(): print("$scope module {} $end" .format(n), file=f) memindex = 0 for s in memdict[n].mem: sval = _getSval(s) if sval is None: raise ValueError("%s of module %s has no initial value" % (n, name)) if not s._tracing: s._tracing = 1 s._code = next(namegen) siglist.append(s) w = s._nrbits # use real for enum strings if w and not isinstance(sval, EnumItemType): if w == 1: print("$var reg 1 %s %s(%i) $end" % (s._code, n, memindex), file=f) else: print("$var reg %s %s %s(%i) $end" % (w, s._code, n, memindex), file=f) else: print("$var real 1 %s %s(%i) $end" % (s._code, n, memindex), file=f) memindex += 1 print("$upscope $end", file=f) for i in range(curlevel): print("$upscope $end", file=f) print(file=f) print("$enddefinitions $end", file=f) print("$dumpvars", file=f) for s in siglist: s._printVcd() # initial value print("$end", file=f) myhdl-0.11/myhdl/_tristate.py000066400000000000000000000036431347432460400162520ustar00rootroot00000000000000from __future__ import absolute_import import warnings from myhdl._Signal import _Signal, _DelayedSignal from myhdl._simulator import _siglist class BusContentionWarning(UserWarning): pass warnings.filterwarnings('always', r".*", BusContentionWarning) def Tristate(val, delay=None): """ Return a new Tristate(default or delay 0) or DelayedTristate """ if delay is not None: if delay < 0: raise TypeError("Signal: delay should be >= 0") return _DelayedTristate(val, delay) else: return _Tristate(val) class _Tristate(_Signal): def __init__(self, val): self._drivers = [] super(Tristate, self).__init__(val) self._val = None def driver(self): d = _TristateDriver(self) self._drivers.append(d) return d def _resolve(self): next = None for d in self._drivers: if next is None: next = d._next elif d._next is not None: warnings.warn("Bus contention", category=BusContentionWarning) next = None break self._next = next def _update(self): self._resolve() return super(Tristate, self)._update() class _TristateDriver(_Signal): def __init__(self, bus): _Signal.__init__(self, bus._val) self._val = None self._bus = bus @_Signal.next.setter def next(self, val): if isinstance(val, _Signal): val = val._val if val is None: self._next = None else: self._setNextVal(val) _siglist.append(self._bus) class _DelayedTristate(_DelayedSignal, _Tristate): def __init__(self, val, delay=1): self._drivers = [] super(_DelayedTristate, self).__init__(val, delay) self._val = None def _update(self): self._resolve() return super(_DelayedTristate, self)._update() myhdl-0.11/myhdl/_util.py000066400000000000000000000065321347432460400153700ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2009 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Module with utilility objects for MyHDL. """ from __future__ import absolute_import from __future__ import print_function import __future__ import ast import sys import inspect from tokenize import generate_tokens, untokenize, INDENT from myhdl._compat import integer_types, StringIO def _printExcInfo(): kind, value = sys.exc_info()[:2] msg = str(kind) # msg = msg[msg.rindex('.')+1:] if str(value): msg += ": %s" % value print(msg, file=sys.stderr) _isGenFunc = inspect.isgeneratorfunction def _flatten(*args): arglist = [] for arg in args: if isinstance(arg, (list, tuple, set)): for item in arg: arglist.extend(_flatten(item)) else: arglist.append(arg) return arglist def _isTupleOfInts(obj): if not isinstance(obj, tuple): return False for e in obj: if not isinstance(e, integer_types): return False return True def _dedent(s): """Dedent python code string.""" result = [t[:2] for t in generate_tokens(StringIO(s).readline)] # set initial indent to 0 if any if result[0][0] == INDENT: result[0] = (INDENT, '') return untokenize(result) def _makeAST(f): # Need to look at the flags used to compile the original function f and # pass these same flags to the compile() function. This ensures that # syntax-changing __future__ imports like print_function work correctly. orig_f_co_flags = f.__code__.co_flags # co_flags can contain various internal flags that we can't pass to # compile(), so strip them out here valid_flags = 0 for future_feature in __future__.all_feature_names: feature = getattr(__future__, future_feature) valid_flags |= feature.compiler_flag s = inspect.getsource(f) s = _dedent(s) # use compile instead of ast.parse so that additional flags can be passed flags = ast.PyCF_ONLY_AST | (orig_f_co_flags & valid_flags) tree = compile(s, filename='', mode='exec', flags=flags, dont_inherit=True) # tree = ast.parse(s) tree.sourcefile = inspect.getsourcefile(f) tree.lineoffset = inspect.getsourcelines(f)[1] - 1 return tree def _genfunc(gen): from myhdl._always_comb import _AlwaysComb from myhdl._always_seq import _AlwaysSeq from myhdl._always import _Always if isinstance(gen, (_AlwaysComb, _AlwaysSeq, _Always)): func = gen.func else: func = gen.genfunc return func myhdl-0.11/myhdl/_visitors.py000066400000000000000000000053071347432460400162740ustar00rootroot00000000000000#pylint: disable=invalid-name import ast from myhdl._intbv import intbv from myhdl._Signal import _Signal, _isListOfSigs class _SigNameVisitor(ast.NodeVisitor): def __init__(self, symdict): self.toplevel = 1 self.symdict = symdict self.inputs = set() self.outputs = set() self.inouts = set() self.embedded_func = None self.context = 'input' self.sigdict = {} self.losdict = {} def visit_Module(self, node): for n in node.body: self.visit(n) def visit_FunctionDef(self, node): if self.toplevel: self.toplevel = 0 # skip embedded functions for n in node.body: self.visit(n) else: self.embedded_func = node.name def visit_If(self, node): if not node.orelse: if isinstance(node.test, ast.Name) and \ node.test.id == '__debug__': return # skip self.generic_visit(node) def visit_Name(self, node): n = node.id if n not in self.symdict: return s = self.symdict[n] if isinstance(s, (_Signal, intbv)) or _isListOfSigs(s): if self.context == 'input': self.inputs.add(n) elif self.context == 'output': self.outputs.add(n) elif self.context == 'inout': self.inouts.add(n) elif self.context == 'pass': pass else: print(self.context) raise AssertionError("bug in _SigNameVisitor") if isinstance(s, _Signal): self.sigdict[n] = s elif _isListOfSigs(s): self.losdict[n] = s def visit_Assign(self, node): self.context = 'output' for n in node.targets: self.visit(n) self.context = 'input' self.visit(node.value) def visit_Attribute(self, node): self.visit(node.value) def visit_Call(self, node): fn = None if isinstance(node.func, ast.Name): fn = node.func.id if fn == "len": pass else: self.generic_visit(node) def visit_Subscript(self, node): self.visit(node.value) self.context = 'input' self.visit(node.slice) def visit_AugAssign(self, node): self.context = 'inout' self.visit(node.target) self.context = 'input' self.visit(node.value) def visit_ClassDef(self, node): pass # skip def visit_Exec(self, node): pass # skip def visit_Print(self, node): self.context = 'pass' self.generic_visit(node) self.context == 'input' myhdl-0.11/myhdl/conversion/000077500000000000000000000000001347432460400160615ustar00rootroot00000000000000myhdl-0.11/myhdl/conversion/_VHDLNameValidation.py000066400000000000000000000046051347432460400221500ustar00rootroot00000000000000import warnings # from myhdl import * from myhdl import ToVHDLWarning # A list of all reserved words within VHDL which should not be used for # anything other than their own specific purpose _vhdl_keywords = ["abs", "access", "after", "alias", "all", "and", "architecture", "array", "assert", "attribute", "begin", "block", "body", "buffer", "bus", "case", "component", "configuration", "constant", "disconnect", "downto", "else", "elseif", "end", "entity", "exit", "file", "for", "function", "generate", "generic", "group", "guarded", "if", "impure", "in", "inertial", "inout", "is", "label", "library", "linkage", "literal", "loop", "map", "mod", "nand", "new", "next", "nor", "not", "null", "of", "on", "open", "or", "others", "out", "package", "port", "postponed", "procedure", "process", "pure", "range", "record", "register", "reject", "rem", "report", "return", "rol", "ror", "select", "severity", "signal", "shared", "sla", "sll", "sra", "srl", "subtype", "then", "to", "transport", "type", "unaffected", "units", "until", "use", "variable", "wait", "when", "while", "with", "xnor", "xor"]; # A list to hold all signal names being used in lowercase to raise an error # if no names are reused with different casing _usedNames = []; # Function which compares current parsed signal/entity to all keywords to # ensure reserved words are not being used for the wrong purpose def _nameValid(name): if name.lower() in _vhdl_keywords: warnings.warn("VHDL keyword used: {}".format(name), category=ToVHDLWarning) if name.startswith('_'): warnings.warn("VHDL variable names cannot start with '_': {}".format(name), category=ToVHDLWarning) if '-' in name: warnings.warn("VHDL variable names cannot contain '-': {}".format(name), category=ToVHDLWarning) if '__' in name: warnings.warn("VHDL variable names cannot contain double underscores '__': {}".format(name), category=ToVHDLWarning) if name.lower() in _usedNames: warnings.warn("Previously used name being reused: {}".format(name), category=ToVHDLWarning) _usedNames.append(name.lower()) myhdl-0.11/myhdl/conversion/__init__.py000066400000000000000000000004421347432460400201720ustar00rootroot00000000000000from __future__ import absolute_import from ._verify import verify, analyze, registerSimulator from ._toVerilog import toVerilog from ._toVHDL import toVHDL __all__ = ["verify", "analyze", "registerSimulator", "toVerilog", "toVHDL" ] myhdl-0.11/myhdl/conversion/_analyze.py000066400000000000000000001331601347432460400202410ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2013 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ MyHDL conversion analysis module. """ from __future__ import absolute_import, print_function import inspect # import compiler # from compiler import ast as astNode from types import FunctionType, MethodType import sys import re import ast from itertools import chain import myhdl import myhdl from myhdl import * from myhdl import ConversionError from myhdl._always_comb import _AlwaysComb from myhdl._always_seq import _AlwaysSeq from myhdl._always import _Always from myhdl.conversion._misc import (_error, _access, _kind, _ConversionMixin, _Label, _genUniqueSuffix, _get_argnames) from myhdl._extractHierarchy import _isMem, _getMemInfo, _UserCode from myhdl._Signal import _Signal, _WaiterList from myhdl._ShadowSignal import _ShadowSignal, _SliceSignal, _TristateDriver from myhdl._util import _flatten from myhdl._util import _isTupleOfInts from myhdl._util import _makeAST from myhdl._resolverefs import _AttrRefTransformer from myhdl._compat import builtins, integer_types, PY2 myhdlObjects = myhdl.__dict__.values() builtinObjects = builtins.__dict__.values() _enumTypeSet = set() def _makeName(n, prefixes, namedict): # trim empty prefixes prefixes = [p for p in prefixes if p] if len(prefixes) > 1: # name = '_' + '_'.join(prefixes[1:]) + '_' + n name = '_'.join(prefixes[1:]) + '_' + n else: name = n if '[' in name or ']' in name: name = "\\" + name + ' ' # print prefixes # print name return name def _analyzeSigs(hierarchy, hdl='Verilog'): curlevel = 0 siglist = [] memlist = [] prefixes = [] open, close = '[', ']' if hdl == 'VHDL': open, close = '(', ')' for inst in hierarchy: level = inst.level name = inst.name sigdict = inst.sigdict memdict = inst.memdict namedict = dict(chain(sigdict.items(), memdict.items())) delta = curlevel - level curlevel = level assert(delta >= -1) if delta > -1: # same or higher level prefixes = prefixes[:curlevel - 1] # skip processing and prefixing in context without signals # if not (sigdict or memdict): # prefixes.append("") # continue prefixes.append(name) for n, s in sigdict.items(): if s._name is not None: continue if isinstance(s, _SliceSignal): continue s._name = _makeName(n, prefixes, namedict) if not s._nrbits: raise ConversionError(_error.UndefinedBitWidth, s._name) # slice signals for sl in s._slicesigs: sl._setName(hdl) siglist.append(s) # list of signals for n, m in memdict.items(): if m.name is not None: continue m.name = _makeName(n, prefixes, namedict) memlist.append(m) # handle the case where a named signal appears in a list also by giving # priority to the list and marking the signals as unused for m in memlist: if not m._used: continue for i, s in enumerate(m.mem): s._name = "%s%s%s%s" % (m.name, open, i, close) s._used = False if s._inList: raise ConversionError(_error.SignalInMultipleLists, s._name) s._inList = True if not s._nrbits: raise ConversionError(_error.UndefinedBitWidth, s._name) if type(s.val) != type(m.elObj.val): raise ConversionError(_error.InconsistentType, s._name) if s._nrbits != m.elObj._nrbits: raise ConversionError(_error.InconsistentBitWidth, s._name) return siglist, memlist def _analyzeGens(top, absnames): genlist = [] for g in top: if isinstance(g, _UserCode): tree = g elif isinstance(g, (_AlwaysComb, _AlwaysSeq, _Always)): f = g.func tree = g.ast tree.symdict = f.__globals__.copy() tree.callstack = [] # handle free variables tree.nonlocaldict = {} if f.__code__.co_freevars: for n, c in zip(f.__code__.co_freevars, f.__closure__): obj = c.cell_contents tree.symdict[n] = obj # currently, only intbv as automatic nonlocals (until Python 3.0) if isinstance(obj, intbv): tree.nonlocaldict[n] = obj tree.name = absnames.get(id(g), str(_Label("BLOCK"))).upper() v = _AttrRefTransformer(tree) v.visit(tree) v = _FirstPassVisitor(tree) v.visit(tree) if isinstance(g, _AlwaysComb): v = _AnalyzeAlwaysCombVisitor(tree, g.senslist) elif isinstance(g, _AlwaysSeq): v = _AnalyzeAlwaysSeqVisitor(tree, g.senslist, g.reset, g.sigregs, g.varregs) else: v = _AnalyzeAlwaysDecoVisitor(tree, g.senslist) v.visit(tree) else: # @instance f = g.gen.gi_frame tree = g.ast tree.symdict = f.f_globals.copy() tree.symdict.update(f.f_locals) tree.nonlocaldict = {} tree.callstack = [] tree.name = absnames.get(id(g), str(_Label("BLOCK"))).upper() v = _AttrRefTransformer(tree) v.visit(tree) v = _FirstPassVisitor(tree) v.visit(tree) v = _AnalyzeBlockVisitor(tree) v.visit(tree) genlist.append(tree) return genlist class _FirstPassVisitor(ast.NodeVisitor, _ConversionMixin): """First pass visitor. Prune unsupported contructs, and add some useful attributes. """ def __init__(self, tree): self.tree = tree self.toplevel = True def visit_Tuple(self, node): if isinstance(node.ctx, ast.Store): self.raiseError(node, _error.NotSupported, "tuple assignment") def visit_Repr(self, node): self.raiseError(node, _error.NotSupported, "backquote") def visit_ClassDef(self, node): self.raiseError(node, _error.NotSupported, "class statement") def visit_Dict(self, node): self.raiseError(node, _error.NotSupported, "dictionary") def visit_BinOp(self, node): if isinstance(node.op, ast.Div): self.raiseError(node, _error.NotSupported, "true division - consider '//'") def visit_Ellipsis(self, node): self.raiseError(node, _error.NotSupported, "ellipsis") def visit_Exec(self, node): self.raiseError(node, _error.NotSupported, "exec statement") def visitExpression(self, node, *args): self.raiseError(node, _error.NotSupported, "Expression node") def visit_ImportFrom(self, node): self.raiseError(node, _error.NotSupported, "from statement") def visit_Global(self, node): self.raiseError(node, _error.NotSupported, "global statement") def visit_Import(self, node): self.raiseError(node, _error.NotSupported, "import statement") def visit_Lambda(self, node): self.raiseError(node, _error.NotSupported, "lambda statement") def visit_ListComp(self, node): if len(node.generators) > 1: self.raiseError(node, _error.NotSupported, "multiple for statements in list comprehension") if node.generators[0].ifs: self.raiseError(node, _error.NotSupported, "if statement in list comprehension") self.generic_visit(node) def visit_List(self, node): self.raiseError(node, _error.NotSupported, "list") def visitSliceObj(self, node): self.raiseError(node, _error.NotSupported, "slice object") # All try blocks from python 3.3+ def visit_Try(self, node): self.raiseError(node, _error.NotSupported, "try statement") # Legacy try blocks def visit_TryExcept(self, node): self.raiseError(node, _error.NotSupported, "try-except statement") def visit_TryFinally(self, node): self.raiseError(node, _error.NotSupported, "try-finally statement") def visit_Assign(self, node): if len(node.targets) > 1: self.raiseError(node, _error.NotSupported, "multiple assignments") self.visit(node.targets[0]) self.visit(node.value) def visit_Call(self, node): # ast.Call signature changed in python 3.5 # http://greentreesnakes.readthedocs.org/en/latest/nodes.html#Call if sys.version_info >= (3, 5): starargs = any(isinstance(arg, ast.Starred) for arg in node.args) kwargs = any(kw.arg is None for kw in node.keywords) else: starargs = node.starargs is not None kwargs = node.kwargs is not None if starargs: self.raiseError(node, _error.NotSupported, "extra positional arguments") if kwargs: self.raiseError(node, _error.NotSupported, "extra named arguments") self.generic_visit(node) def visit_Compare(self, node): if len(node.ops) != 1: self.raiseError(node, _error.NotSupported, "chained comparison") self.generic_visit(node) def visit_FunctionDef(self, node): if node.args.vararg or node.args.kwarg: self.raiseError(node, _error.NotSupported, "extra positional or named arguments") if not self.toplevel: self.raiseError(node, _error.NotSupported, "embedded function definition") self.toplevel = False node.argnames = _get_argnames(node) # don't visit decorator lists - they can support more than other calls # put official docstrings aside for separate processing node.doc = None if node.body and isinstance(node.body[0], ast.Expr) and \ isinstance(node.body[0].value, ast.Str): node.doc = node.body[0].value.s node.body = node.body[1:] self.visitList(node.body) def flattenIf(self, node, tests, else_, co): """ Flatten if-then-else as in compiler package.""" if node: if len(node) == 1 and \ isinstance(node[0], ast.If) and \ node[0].body[0].col_offset == co: # ugly hack to detect separate else clause elifnode = node[0] tests.append((elifnode.test, elifnode.body)) self.flattenIf(elifnode.orelse, tests, else_, co) else: else_[:] = node def visit_If(self, node): node.ignore = False if not node.orelse: test = node.test if isinstance(test, ast.Name): if test.id == '__debug__': node.ignore = True return # skip self.generic_visit(node) # add fields that match old compiler package tests = [(node.test, node.body)] else_ = [] self.flattenIf(node.orelse, tests, else_, node.body[0].col_offset) node.tests = tests node.else_ = else_ def visit_Print(self, node): if node.dest is not None: self.raiseError(node, _error.NotSupported, "printing to a file with >> syntax") if not node.nl: self.raiseError(node, _error.NotSupported, "printing without newline") def getNrBits(obj): if hasattr(obj, '_nrbits'): return obj._nrbits return None def hasType(obj, theType): if isinstance(obj, theType): return True if isinstance(obj, _Signal): if isinstance(obj._val, theType): return True return False class ReferenceStack(list): def push(self): self.append(set()) def add(self, item): self[-1].add(item) def __contains__(self, item): for s in self: if item in s: return True return False class _Ram(object): __slots__ = ['elObj', 'depth'] class _Rom(object): __slots__ = ['rom'] def __init__(self, rom): self.rom = rom re_str = re.compile(r"[^%]+") re_ConvSpec = re.compile(r"%(?P[-]?)(?P[0-9]*)(?P[sd])") class ConvSpec(object): def __init__(self, **kwargs): self.justified = "RIGHT" self.width = 0 self.conv = str if kwargs['justified'] == '-': self.justified = "LEFT" if kwargs['width']: self.width = int(kwargs['width']) if kwargs['conv'] == 'd': self.conv = int defaultConvSpec = ConvSpec(**re_ConvSpec.match(r"%s").groupdict()) def _getNritems(obj): """Return the number of items in an objects' type""" if isinstance(obj, _Signal): obj = obj._init if isinstance(obj, intbv): return obj._max - obj._min elif isinstance(obj, EnumItemType): return len(obj._type) else: raise TypeError("Unexpected type, missing final \'else:\'?") class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin): def __init__(self, tree): tree.sigdict = {} tree.vardict = {} tree.inputs = set() tree.outputs = set() # hack for assigned mems tree.outmems = set() tree.argnames = [] tree.kind = None tree.hasYield = 0 tree.hasRom = False tree.hasLos = False tree.hasPrint = False self.tree = tree self.labelStack = [] self.refStack = ReferenceStack() self.globalRefs = set() self.access = _access.INPUT self.kind = _kind.NORMAL def visit_BinOp(self, node): self.visit(node.left) self.visit(node.right) node.obj = int(-1) def visit_BoolOp(self, node): for n in node.values: self.visit(n) for n in node.values: if not hasType(n.obj, bool): self.raiseError(node, _error.NotSupported, "non-boolean argument in logical operator") node.obj = bool() def visit_UnaryOp(self, node): self.visit(node.operand) op = node.op node.obj = node.operand.obj if isinstance(op, ast.Not): node.obj = bool() elif isinstance(op, ast.UAdd): node.obj = int(-1) elif isinstance(op, ast.USub): node.obj = int(-1) def visit_Attribute(self, node): if isinstance(node.ctx, ast.Store): self.setAttr(node) else: self.getAttr(node) if node.attr == 'next': if isinstance(node.value, ast.Name): n = node.value.id obj = node.value.obj if isinstance(obj, _Signal) and isinstance(obj._init, modbv): if not obj._init._hasFullRange(): self.raiseError(node, _error.ModbvRange, n) def setAttr(self, node): if node.attr != 'next': self.raiseError(node, _error.NotSupported, "attribute assignment") self.tree.kind = _kind.TASK # self.access = _access.OUTPUT self.visit(node.value) node.obj = node.value.obj # self.access = _access.INPUT def getAttr(self, node): self.visit(node.value) node.obj = None if isinstance(node.value, ast.Name): n = node.value.id if (n not in self.tree.vardict) and (n not in self.tree.symdict): raise AssertionError("attribute target: %s" % n) obj = node.value.obj if isinstance(obj, _Signal): if node.attr == 'posedge': node.obj = obj.posedge elif node.attr == 'negedge': node.obj = obj.negedge elif node.attr in ('val', 'next'): node.obj = obj.val if isinstance(obj, (intbv, _Signal)): if node.attr == 'min': node.obj = obj.min elif node.attr == 'max': node.obj = obj.max elif node.attr == 'signed': node.obj = intbv.signed if isinstance(obj, EnumType): assert hasattr(obj, node.attr), node.attr node.obj = getattr(obj, node.attr) if obj not in _enumTypeSet: _enumTypeSet.add(obj) suf = _genUniqueSuffix.next() obj._setName(n + suf) if node.obj is None: # attribute lookup failed self.raiseError(node, _error.UnsupportedAttribute, node.attr) def visit_Assign(self, node): target, value = node.targets[0], node.value self.access = _access.OUTPUT self.visit(target) self.access = _access.INPUT # set attribute to detect a top-level rhs value.isRhs = True if isinstance(target, ast.Name): node.kind = _kind.DECLARATION self.kind = _kind.DECLARATION self.visit(value) self.kind = _kind.NORMAL n = target.id if n in self.tree.sigdict: self.raiseError(node, _error.ShadowingVar) obj = self.getObj(value) if obj is None: self.raiseError(node, _error.TypeInfer, n) if isinstance(obj, intbv): if len(obj) == 0: self.raiseError(node, _error.IntbvBitWidth, n) if isinstance(obj, modbv): if not obj._hasFullRange(): self.raiseError(node, _error.ModbvRange, n) if n in self.tree.vardict: curObj = self.tree.vardict[n] if isinstance(obj, type(curObj)): pass elif isinstance(curObj, type(obj)): self.tree.vardict[n] = obj else: self.raiseError(node, _error.TypeMismatch, n) if getNrBits(obj) != getNrBits(curObj): self.raiseError(node, _error.NrBitsMismatch, n) else: self.tree.vardict[n] = obj else: self.visit(value) def visit_AugAssign(self, node): # declare node as an rhs for type inference optimization node.isRhs = True self.access = _access.INOUT self.visit(node.target) self.access = _access.INPUT self.visit(node.value) def visit_Break(self, node): self.labelStack[-2].isActive = True def visit_Call(self, node): self.visit(node.func) f = self.getObj(node.func) node.obj = None if f is print: self.visit_Print(node) return self.access = _access.UNKNOWN for arg in node.args: self.visit(arg) for kw in node.keywords: self.visit(kw) self.access = _access.INPUT argsAreInputs = True if type(f) is type and issubclass(f, intbv): node.obj = self.getVal(node) elif f is concat: node.obj = self.getVal(node) elif f is len: self.access = _access.UNKNOWN node.obj = int(0) # XXX elif f is bool: node.obj = bool() elif f in _flatten(integer_types): node.obj = int(-1) # elif f in (posedge , negedge): # # node.obj = _EdgeDetector() elif f is ord: node.obj = int(-1) if not (isinstance(node.args[0], ast.Str) and (len(node.args[0].s) == 1)): self.raiseError(node, _error.NotSupported, "ord: expect string argument with length 1") elif f is delay: node.obj = delay(0) # suprize: identity comparison on unbound methods doesn't work in python 2.5?? elif f == intbv.signed: obj = node.func.value.obj if len(obj): M = 2 ** (len(obj) - 1) node.obj = intbv(-1, min=-M, max=M) else: node.obj = intbv(-1) elif f in myhdlObjects: pass elif f in builtinObjects: pass elif type(f) is FunctionType: argsAreInputs = False tree = _makeAST(f) fname = f.__name__ tree.name = _Label(fname) tree.symdict = f.__globals__.copy() tree.nonlocaldict = {} if fname in self.tree.callstack: self.raiseError(node, _error.NotSupported, "Recursive call") tree.callstack = self.tree.callstack[:] tree.callstack.append(fname) # handle free variables if f.__code__.co_freevars: for n, c in zip(f.__code__.co_freevars, f.__closure__): obj = c.cell_contents if not isinstance(obj, (integer_types, _Signal)): self.raiseError(node, _error.FreeVarTypeError, n) tree.symdict[n] = obj v = _FirstPassVisitor(tree) v.visit(tree) v = _AnalyzeFuncVisitor(tree, node.args, node.keywords) v.visit(tree) node.obj = tree.returnObj node.tree = tree tree.argnames = argnames = _get_argnames(tree.body[0]) # extend argument list with keyword arguments on the correct position node.args.extend([None] * len(node.keywords)) for kw in node.keywords: node.args[argnames.index(kw.arg)] = kw.value for n, arg in zip(argnames, node.args): if n in tree.outputs: self.access = _access.OUTPUT self.visit(arg) self.access = _access.INPUT if n in tree.inputs: self.visit(arg) elif type(f) is MethodType: self.raiseError(node, _error.NotSupported, "method call: '%s'" % f.__name__) else: debug_info = [e for e in ast.iter_fields(node.func)] raise AssertionError("Unexpected callable %s" % str(debug_info)) if argsAreInputs: for arg in node.args: self.visit(arg) def visit_Compare(self, node): node.obj = bool() for n in [node.left] + node.comparators: self.visit(n) op, arg = node.ops[0], node.comparators[0] # # node.expr.target = self.getObj(arg) # # arg.target = self.getObj(node.expr) # detect specialized case for the test if isinstance(op, ast.Eq) and isinstance(node.left, ast.Name): # check wether it can be a case val = arg.obj if isinstance(val, bool): val = int(val) # cast bool to int first if isinstance(val, (EnumItemType, integer_types)): node.case = (node.left, val) # check whether it can be part of an edge check n = node.left.id if n in self.tree.sigdict: sig = self.tree.sigdict[n] v = self.getValue(arg) if v is not None: if v == 0: node.edge = sig.negedge elif v == 1: node.edge = sig.posedge def visit_Num(self, node): n = node.n # assign to value attribute for backwards compatibility node.value = n if n in (0, 1): node.obj = bool(n) elif isinstance(n, int): node.obj = n else: node.obj = None def visit_Str(self, node): node.obj = node.s def visit_Continue(self, node): self.labelStack[-1].isActive = True def visit_For(self, node): node.breakLabel = _Label("BREAK") node.loopLabel = _Label("LOOP") self.labelStack.append(node.breakLabel) self.labelStack.append(node.loopLabel) self.refStack.push() self.visit(node.target) var = node.target.id self.tree.vardict[var] = int(-1) cf = node.iter self.visit(cf) self.require(node, isinstance(cf, ast.Call), "Expected (down)range call") f = self.getObj(cf.func) self.require(node, f in (range, downrange), "Expected (down)range call") for stmt in node.body: self.visit(stmt) self.refStack.pop() self.require(node, not node.orelse, "for-else not supported") self.labelStack.pop() self.labelStack.pop() def visit_FunctionDef(self, node): raise AssertionError("subclass must implement this") def visit_If(self, node): if node.ignore: return for test, suite in node.tests: self.visit(test) self.refStack.push() self.visitList(suite) self.refStack.pop() if node.else_: self.refStack.push() self.visitList(node.else_) self.refStack.pop() # check whether the if can be mapped to a (parallel) case node.isCase = node.isFullCase = False test1 = node.tests[0][0] if not hasattr(test1, 'case'): return var1, item1 = test1.case # don't infer a case if there's no elsif test if not node.tests[1:]: return choices = set() choices.add(item1) for test, suite in node.tests[1:]: if not hasattr(test, 'case'): return var, item = test.case if var.id != var1.id or type(item) is not type(item1): return if item in choices: return choices.add(item) node.isCase = True node.caseVar = var1 node.caseItem = item1 if node.else_ or (len(choices) == _getNritems(var1.obj)): node.isFullCase = True def visit_ListComp(self, node): mem = node.obj = _Ram() self.kind = _kind.DECLARATION try: self.visit(node.elt) except ConversionError as e: if e.kind == _error.UnboundLocal: pass else: raise self.kind = _kind.NORMAL mem.elObj = self.getObj(node.elt) if not isinstance(mem.elObj, intbv) or not len(mem.elObj) > 0: self.raiseError(node, _error.UnsupportedListComp) cf = node.generators[0].iter self.visit(cf) if not isinstance(cf, ast.Call): self.raiseError(node, _error.UnsupportedListComp) f = self.getObj(cf.func) if f is not range or len(cf.args) != 1: self.raiseError(node, _error.UnsupportedListComp) mem.depth = cf.args[0].obj def visit_NameConstant(self, node): node.obj = node.value def visit_Name(self, node): if isinstance(node.ctx, ast.Store): self.setName(node) else: self.getName(node) def setName(self, node): # XXX INOUT access in Store context, unlike with compiler # XXX check whether ast context is correct n = node.id if self.access == _access.INOUT: # augmented assign if n in self.tree.sigdict: sig = self.tree.sigdict[n] if isinstance(sig, _Signal): self.raiseError(node, _error.NotSupported, "Augmented signal assignment") if n in self.tree.vardict: obj = self.tree.vardict[n] # upgrade bool to int for augmented assignments if isinstance(obj, bool): obj = int(-1) self.tree.vardict[n] = obj node.obj = obj else: if n in ("__verilog__", "__vhdl__"): self.raiseError(node, _error.NotSupported, "%s in generator function" % n) if n in self.globalRefs: self.raiseError(node, _error.UnboundLocal, n) self.refStack.add(n) def getName(self, node): n = node.id node.obj = None if n not in self.refStack: if (n in self.tree.vardict) and (n not in self.tree.nonlocaldict): self.raiseError(node, _error.UnboundLocal, n) self.globalRefs.add(n) if n in self.tree.sigdict: node.obj = sig = self.tree.sigdict[n] # mark shadow signal as driven only when they are seen somewhere if isinstance(sig, _ShadowSignal): sig._driven = 'wire' # mark tristate signal as driven if its driver is seen somewhere if isinstance(sig, _TristateDriver): sig._sig._driven = 'wire' if not isinstance(sig, _Signal): # print "not a signal: %s" % n pass else: if sig._type is bool: node.edge = sig.posedge if self.access == _access.INPUT: self.tree.inputs.add(n) elif self.access == _access.OUTPUT: self.tree.kind = _kind.TASK if n in self.tree.outputs: node.kind = _kind.REG self.tree.outputs.add(n) elif self.access == _access.UNKNOWN: pass else: self.raiseError(node, _error.NotSupported, "Augmented signal assignment") if n in self.tree.vardict: obj = self.tree.vardict[n] if self.access == _access.INOUT: # probably dead code # upgrade bool to int for augmented assignments if isinstance(obj, bool): obj = int(-1) self.tree.vardict[n] = obj node.obj = obj elif n in self.tree.symdict: node.obj = self.tree.symdict[n] if _isTupleOfInts(node.obj): node.obj = _Rom(node.obj) self.tree.hasRom = True elif _isMem(node.obj): m = _getMemInfo(node.obj) if self.access == _access.INPUT: m._read = True elif self.access == _access.OUTPUT: m._driven = 'reg' self.tree.outmems.add(n) elif self.access == _access.UNKNOWN: pass else: assert False, "unexpected mem access %s %s" % (n, self.access) self.tree.hasLos = True elif isinstance(node.obj, int): node.value = node.obj if n in self.tree.nonlocaldict: # hack: put nonlocal intbv's in the vardict self.tree.vardict[n] = v = node.obj elif n in builtins.__dict__: node.obj = builtins.__dict__[n] else: self.raiseError(node, _error.UnboundLocal, n) def visit_Return(self, node): self.raiseError(node, _error.NotSupported, "return statement") def visit_Print(self, node): self.tree.hasPrint = True f = [] nr = 0 a = [] if PY2 and isinstance(node, ast.Print): node_args = node.values else: node_args = node.args for n in node_args: if isinstance(n, ast.BinOp) and isinstance(n.op, ast.Mod) and \ isinstance(n.left, ast.Str): if isinstance(n.right, ast.Tuple): a.extend(n.right.elts) else: a.append(n.right) s = n.left.s while s: if not s: break if s[:2] == "%%": f.append("%") s = s[2:] continue m = re_ConvSpec.match(s) if m: c = ConvSpec(**m.groupdict()) if c.justified != "RIGHT": self.raiseError(node, _error.UnsupportedFormatString, "format justification specification: %s" % s) if c.width != 0: self.raiseError(node, _error.UnsupportedFormatString, "format width specification: %s" % s) f.append(c) s = s[m.end():] nr += 1 continue m = re_str.match(s) if m: f.append(s[:m.end()]) s = s[m.end():] continue self.raiseError(node, _error.UnsupportedFormatString, "%s" % s) elif isinstance(n, ast.Str): f.append(n.s) else: f.append(defaultConvSpec) a.append(n) nr += 1 f.append(" ") # remove last single space if it exists if f: f.pop() node.format = f node.args = a if len(node.args) < nr: self.raiseError(node, _error.FormatString, "not enough arguments") if len(node.args) > nr: self.raiseError(node, _error.FormatString, "too many arguments") self.generic_visit(node) def visit_Subscript(self, node): if isinstance(node.slice, ast.Slice): self.accessSlice(node) else: self.accessIndex(node) def accessSlice(self, node): self.visit(node.value) node.obj = self.getObj(node.value) self.access = _access.INPUT lower, upper = node.slice.lower, node.slice.upper if lower: self.visit(lower) if upper: self.visit(upper) if isinstance(node.obj, intbv): if self.kind == _kind.DECLARATION: self.require(lower, "Expected leftmost index") leftind = self.getVal(lower) if upper: rightind = self.getVal(upper) else: rightind = 0 node.obj = node.obj[leftind:rightind] def accessIndex(self, node): self.visit(node.value) self.access = _access.INPUT self.visit(node.slice.value) if isinstance(node.value.obj, _Ram): if isinstance(node.ctx, ast.Store): self.raiseError(node, _error.ListElementAssign) else: node.obj = node.value.obj.elObj elif _isMem(node.value.obj): node.obj = node.value.obj[0] elif isinstance(node.value.obj, _Rom): node.obj = int(-1) elif isinstance(node.value.obj, intbv): node.obj = bool() else: node.obj = bool() # XXX default def visit_Tuple(self, node): self.generic_visit(node) def visit_While(self, node): node.breakLabel = _Label("BREAK") node.loopLabel = _Label("LOOP") self.labelStack.append(node.breakLabel) self.labelStack.append(node.loopLabel) self.visit(node.test) self.refStack.push() for n in node.body: self.visit(n) self.refStack.pop() y = node.body[0] if isinstance(y, ast.Expr): y = y.value if node.test.obj == True and \ isinstance(y, ast.Yield) and \ not self.tree.hasYield > 1 and \ not isinstance(self.getObj(y.value), delay): node.kind = _kind.ALWAYS self.tree.senslist = y.senslist self.require(node, not node.orelse, "while-else not supported") self.labelStack.pop() self.labelStack.pop() def visit_Yield(self, node, *args): self.tree.hasYield += 1 n = node.value self.visit(n) senslist = [] if isinstance(n, ast.Tuple): for n in n.elts: if not isinstance(n.obj, (_Signal, _WaiterList)): self.raiseError(node, _error.UnsupportedYield) senslist.append(n.obj) elif isinstance(n.obj, (_Signal, _WaiterList, delay)): senslist = [n.obj] elif _isMem(n.obj): senslist = n.obj else: self.raiseError(node, _error.UnsupportedYield) node.senslist = senslist class _AnalyzeBlockVisitor(_AnalyzeVisitor): def __init__(self, tree): _AnalyzeVisitor.__init__(self, tree) for n, v in self.tree.symdict.items(): if isinstance(v, _Signal): self.tree.sigdict[n] = v def visit_FunctionDef(self, node): self.refStack.push() for n in node.body: self.visit(n) self.tree.kind = _kind.ALWAYS for n in node.body[:-1]: if not self.getKind(n) == _kind.DECLARATION: self.tree.kind = _kind.INITIAL break if self.tree.kind == _kind.ALWAYS: w = node.body[-1] if not self.getKind(w) == _kind.ALWAYS: self.tree.kind = _kind.INITIAL self.refStack.pop() def visit_Module(self, node): self.generic_visit(node) for n in self.tree.outputs: s = self.tree.sigdict[n] if s._driven: self.raiseError(node, _error.SigMultipleDriven, n) s._driven = "reg" for n in self.tree.inputs: s = self.tree.sigdict[n] s._markRead() def visit_Return(self, node): # value should be None if node.value is None: pass elif isinstance(node.value, ast.Name) and node.value.id == "None": pass else: self.raiseError(node, _error.NotSupported, "return value other than None") class _AnalyzeAlwaysCombVisitor(_AnalyzeBlockVisitor): def __init__(self, tree, senslist): _AnalyzeBlockVisitor.__init__(self, tree) self.tree.senslist = senslist def visit_FunctionDef(self, node): self.refStack.push() for n in node.body: self.visit(n) self.tree.kind = _kind.SIMPLE_ALWAYS_COMB for n in node.body: if isinstance(n, ast.Expr) and isinstance(n.value, ast.Str): continue # skip doc strings if isinstance(n, ast.Assign) and \ isinstance(n.targets[0], ast.Attribute) and \ self.getKind(n.targets[0].value) != _kind.REG: pass else: self.tree.kind = _kind.ALWAYS_COMB return # rom access is expanded into a case statement in addition # to any always_comb that contains a list of signals # if self.tree.hasRom or self.tree.hasLos: if self.tree.hasRom: self.tree.kind = _kind.ALWAYS_COMB self.refStack.pop() def visit_Module(self, node): _AnalyzeBlockVisitor.visit_Module(self, node) if self.tree.kind == _kind.SIMPLE_ALWAYS_COMB: for n in self.tree.outputs: s = self.tree.sigdict[n] s._driven = "wire" for n in self.tree.outmems: m = _getMemInfo(self.tree.symdict[n]) m._driven = "wire" class _AnalyzeAlwaysSeqVisitor(_AnalyzeBlockVisitor): def __init__(self, tree, senslist, reset, sigregs, varregs): _AnalyzeBlockVisitor.__init__(self, tree) self.tree.senslist = senslist self.tree.reset = reset self.tree.sigregs = sigregs self.tree.varregs = varregs def visit_FunctionDef(self, node): self.refStack.push() for n in node.body: self.visit(n) self.tree.kind = _kind.ALWAYS_SEQ self.refStack.pop() class _AnalyzeAlwaysDecoVisitor(_AnalyzeBlockVisitor): def __init__(self, tree, senslist): _AnalyzeBlockVisitor.__init__(self, tree) self.tree.senslist = senslist for arg in senslist: if isinstance(arg, delay): self.raiseError(_error.NotSupported, "delay argument in @always decorator") def visit_FunctionDef(self, node): self.refStack.push() for n in node.body: self.visit(n) self.tree.kind = _kind.ALWAYS_DECO self.refStack.pop() class _AnalyzeFuncVisitor(_AnalyzeVisitor): def __init__(self, tree, args, keywords): _AnalyzeVisitor.__init__(self, tree) self.args = args self.keywords = keywords self.tree.hasReturn = False self.tree.returnObj = None def visit_FunctionDef(self, node): self.refStack.push() argnames = _get_argnames(node) for i, arg in enumerate(self.args): n = argnames[i] self.tree.symdict[n] = self.getObj(arg) self.tree.argnames.append(n) for kw in self.keywords: n = kw.arg self.tree.symdict[n] = self.getObj(kw.value) self.tree.argnames.append(n) for n, v in self.tree.symdict.items(): if isinstance(v, (_Signal, intbv)): self.tree.sigdict[n] = v for stmt in node.body: self.visit(stmt) self.refStack.pop() if self.tree.hasYield: self.raiseError(node, _error.NotSupported, "call to a generator function") if self.tree.kind == _kind.TASK: if self.tree.returnObj is not None: self.raiseError(node, _error.NotSupported, "function with side effects and return value") else: if self.tree.returnObj is None: self.raiseError(node, _error.NotSupported, "pure function without return value") def visit_Return(self, node): self.kind = _kind.DECLARATION if node.value is not None: self.visit(node.value) self.kind = _kind.NORMAL if node.value is None: obj = None elif isinstance(node.value, ast.Name) and node.value.id == 'None': obj = None elif node.value.obj is not None: obj = node.value.obj else: self.raiseError(node, _error.ReturnTypeInfer) if isinstance(obj, intbv) and len(obj) == 0: self.raiseError(node, _error.ReturnIntbvBitWidth) if self.tree.hasReturn: returnObj = self.tree.returnObj if isinstance(obj, type(returnObj)): pass elif isinstance(returnObj, type(obj)): self.tree.returnObj = obj else: self.raiseError(node, _error.ReturnTypeMismatch) if getNrBits(obj) != getNrBits(returnObj): self.raiseError(node, _error.ReturnNrBitsMismatch) else: self.tree.returnObj = obj self.tree.hasReturn = True ismethod = inspect.ismethod # inspect doc is wrong: ismethod checks both bound and unbound methods def isboundmethod(m): return ismethod(m) and m.__self__ is not None # a local function to drill down to the last interface def expandinterface(v, name, obj): for attr, attrobj in vars(obj).items(): if isinstance(attrobj, _Signal): signame = attrobj._name if not signame: signame = name + '_' + attr attrobj._name = signame v.argdict[signame] = attrobj v.argnames.append(signame) elif isinstance(attrobj, myhdl.EnumType): pass elif hasattr(attrobj, '__dict__'): # can assume is yet another interface ... expandinterface(v, name + '_' + attr, attrobj) def _analyzeTopFunc(func, *args, **kwargs): tree = _makeAST(func) v = _AnalyzeTopFuncVisitor(func, tree, *args, **kwargs) v.visit(tree) objs = [] for name, obj in v.fullargdict.items(): if not isinstance(obj, _Signal): objs.append((name, obj)) # create ports for any signal in the top instance if it was buried in an # object passed as in argument # now expand the interface objects for name, obj in objs: if hasattr(obj, '__dict__'): # must be an interface object (probably ...?) expandinterface(v, name, obj) return v class _AnalyzeTopFuncVisitor(_AnalyzeVisitor): def __init__(self, func, tree, *args, **kwargs): self.func = func self.tree = tree self.args = args self.kwargs = kwargs self.name = None self.fullargdict = {} self.argdict = {} self.argnames = [] def visit_FunctionDef(self, node): self.name = node.name self.argnames = _get_argnames(node) if isboundmethod(self.func): if not self.argnames[0] == 'self': self.raiseError(node, _error.NotSupported, "first method argument name other than 'self'") # skip self self.argnames = self.argnames[1:] i = -1 for i, arg in enumerate(self.args): n = self.argnames[i] self.fullargdict[n] = arg if isinstance(arg, _Signal): self.argdict[n] = arg if _isMem(arg): self.raiseError(node, _error.ListAsPort, n) for n in self.argnames[i + 1:]: if n in self.kwargs: arg = self.kwargs[n] self.fullargdict[n] = arg if isinstance(arg, _Signal): self.argdict[n] = arg if _isMem(arg): self.raiseError(node, _error.ListAsPort, n) self.argnames = [n for n in self.argnames if n in self.argdict] myhdl-0.11/myhdl/conversion/_misc.py000066400000000000000000000157161347432460400175370ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ myhdl toVerilog package. """ from __future__ import absolute_import import ast from myhdl import ConversionError from myhdl._compat import PY2 class _error(object): FirstArgType = "first argument should be a classic function" ArgType = "leaf cell type error" NotSupported = "Not supported" TopLevelName = "Result of toVerilog call should be assigned to a top level name" SigMultipleDriven = "Signal has multiple drivers" UndefinedBitWidth = "Signal has undefined bit width" UndrivenSignal = "Signal is not driven" UnreadSignal = "Signal is driven but not read" UnusedPort = "Port is not used" OutputPortRead = "Output port is read internally" Requirement = "Requirement violation" UnboundLocal = "Local variable may be referenced before assignment" TypeMismatch = "Type mismatch with earlier assignment" NrBitsMismatch = "Nr of bits mismatch with earlier assignment" IntbvBitWidth = "intbv object should have a bit width" #IntbvSign = "intbv's that can have negative values are not yet supported" ModbvRange = "modbv object should have full bit vector range" TypeInfer = "Can't infer variable type" ReturnTypeMismatch = "Return type mismatch" ReturnNrBitsMismatch = "Returned nr of bits mismatch" ReturnIntbvBitWidth = "Returned intbv instance should have bit width" ReturnTypeInfer = "Can't infer return type" ShadowingSignal = "Port is not used or shadowed by internal signal" ShadowingVar = "Variable has same name as a hierarchical Signal" FreeVarTypeError = "Free variable should be a Signal or an int" ExtraArguments = "Extra positional or named arguments are not supported" UnsupportedYield = "Unsupported yield statement" UnsupportedListComp = \ "Unsupported list comprehension form: should be [intbv()[n:] for i in range(m)]" ListElementAssign = \ "Can't assign to list element; use slice assignment to change its value" NotASignal = "Non-local object should be a Signal" UnsupportedType = "Object type is not supported in this context" InconsistentType = "Signal elements should have the same base type" InconsistentBitWidth = "Signal elements should have the same bit width" UnsupportedFormatString = "Unsupported format string" FormatString = "Format string error" UnsupportedAttribute = "Unsupported attribute" PortInList = "Port in list is not supported" ListAsPort = "List of signals as a port is not supported" SignalInMultipleLists = "Signal in multiple list is not supported" class _access(object): INPUT, OUTPUT, INOUT, UNKNOWN = range(4) class _kind(object): NORMAL, DECLARATION, ALWAYS, INITIAL, ALWAYS_DECO, \ ALWAYS_COMB, SIMPLE_ALWAYS_COMB, ALWAYS_SEQ, \ TASK, REG \ = range(10) class _context(object): BOOLEAN, YIELD, PRINT, SIGNED, UNKNOWN = range(5) class _ConversionMixin(object): # def getLineNo(self, node): # lineno = node.lineno # if lineno is None: # for n in node.getChildNodes(): # if n.lineno is not None: # lineno = n.lineno # break # lineno = lineno or 0 # return lineno def getLineNo(self, node): lineno = 0 if isinstance(node, (ast.stmt, ast.expr)): lineno = node.lineno return lineno def getObj(self, node): if hasattr(node, 'obj'): return node.obj return None def getTarget(self, node): if hasattr(node, 'target'): return node.target return None def getKind(self, node): if hasattr(node, 'kind'): return node.kind return None def getEdge(self, node): if hasattr(node, 'edge'): return node.edge return None def getValue(self, node): if hasattr(node, 'value'): return node.value return None def getVal(self, node): expr = ast.Expression() expr.body = node expr.lineno = node.lineno expr.col_offset = node.col_offset c = compile(expr, '', 'eval') val = eval(c, self.tree.symdict, self.tree.vardict) # val = eval(_unparse(node), self.tree.symdict, self.tree.vardict) return val def raiseError(self, node, kind, msg=""): lineno = self.getLineNo(node) info = "in file %s, line %s:\n " % \ (self.tree.sourcefile, self.tree.lineoffset + lineno) raise ConversionError(kind, msg, info) def require(self, node, test, msg=""): assert isinstance(node, ast.AST) if not test: self.raiseError(node, _error.Requirement, msg) def visitChildNodes(self, node, *args): for n in node.getChildNodes(): self.visit(n, *args) def visitList(self, nodes): for n in nodes: self.visit(n) def _LabelGenerator(): i = 1 while 1: yield "MYHDL%s" % i i += 1 _genLabel = _LabelGenerator() class _Label(object): def __init__(self, name): self.name = next(_genLabel) + '_' + name self.isActive = False def __str__(self): return str(self.name) # this can be made more sophisticated to deal with existing suffixes # also, may require reset facility class _UniqueSuffixGenerator(object): def __init__(self): self.i = 0 def reset(self): self.i = 0 def next(self): self.i += 1 return "_%s" % self.i _genUniqueSuffix = _UniqueSuffixGenerator() # check if expression is constant def _isConstant(tree, symdict): v = _namesVisitor() v.visit(tree) for name in v.names: if name not in symdict: return False if not isinstance(symdict[name], int): return False return True class _namesVisitor(ast.NodeVisitor): def __init__(self): self.names = [] def visit_Name(self, node): self.names.append(node.id) def _get_argnames(node): if PY2: return [arg.id for arg in node.args.args] else: return [arg.arg for arg in node.args.args] myhdl-0.11/myhdl/conversion/_toVHDL.py000066400000000000000000002364141347432460400177040ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2015 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ myhdl toVHDL conversion module. """ from __future__ import absolute_import from __future__ import print_function import sys import math import os import inspect from datetime import datetime # import compiler # from compiler import ast as astNode import ast from types import GeneratorType import warnings from copy import copy import string # import myhdl import myhdl # from myhdl import * from myhdl import ToVHDLError, ToVHDLWarning from myhdl._extractHierarchy import (_HierExtr, _isMem, _getMemInfo, _UserVhdlCode, _userCodeMap) from myhdl._instance import _Instantiator from myhdl._Signal import _Signal, _WaiterList, posedge, negedge from myhdl._enum import EnumType, EnumItemType from myhdl._intbv import intbv from myhdl._modbv import modbv from myhdl._simulator import now from myhdl._concat import concat from myhdl._delay import delay from myhdl._misc import downrange from myhdl._util import _flatten from myhdl._compat import integer_types, class_types, StringIO from myhdl._ShadowSignal import _TristateSignal, _TristateDriver from myhdl._block import _Block from myhdl._getHierarchy import _getHierarchy from myhdl.conversion._misc import (_error, _kind, _context, _ConversionMixin, _Label, _genUniqueSuffix, _isConstant) from myhdl.conversion._analyze import (_analyzeSigs, _analyzeGens, _analyzeTopFunc, _Ram, _Rom, _enumTypeSet) from myhdl.conversion._toVHDLPackage import _package from myhdl.conversion._VHDLNameValidation import _nameValid, _usedNames from myhdl import bin as tobin _version = myhdl.__version__.replace('.', '') _shortversion = _version.replace('dev', '') _converting = 0 _profileFunc = None _enumPortTypeSet = set() def _checkArgs(arglist): for arg in arglist: if not isinstance(arg, (GeneratorType, _Instantiator, _UserVhdlCode)): raise ToVHDLError(_error.ArgType, arg) def _flatten(*args): arglist = [] for arg in args: if isinstance(arg, _Block): if arg.vhdl_code is not None: arglist.append(arg.vhdl_code) continue else: arg = arg.subs if id(arg) in _userCodeMap['vhdl']: arglist.append(_userCodeMap['vhdl'][id(arg)]) elif isinstance(arg, (list, tuple, set)): for item in arg: arglist.extend(_flatten(item)) else: arglist.append(arg) return arglist def _makeDoc(doc, indent=''): if doc is None: return '' doc = inspect.cleandoc(doc) pre = '\n' + indent + '-- ' doc = '-- ' + doc doc = doc.replace('\n', pre) return doc class _ToVHDLConvertor(object): __slots__ = ("name", "directory", "component_declarations", "header", "no_myhdl_header", "no_myhdl_package", "library", "use_clauses", "architecture", "std_logic_ports", "initial_values" ) def __init__(self): self.name = None self.directory = None self.component_declarations = None self.header = '' self.no_myhdl_header = False self.no_myhdl_package = False self.library = "work" self.use_clauses = None self.architecture = "MyHDL" self.std_logic_ports = False self.initial_values = False def __call__(self, func, *args, **kwargs): global _converting if _converting: return func(*args, **kwargs) # skip else: # clean start sys.setprofile(None) from myhdl import _traceSignals if _traceSignals._tracing: raise ToVHDLError("Cannot use toVHDL while tracing signals") if not isinstance(func, _Block): if not callable(func): raise ToVHDLError(_error.FirstArgType, "got %s" % type(func)) # clear out the list of user declared Signal (and other?) names del _usedNames[:] _converting = 1 if self.name is None: name = func.__name__ if isinstance(func, _Block): name = func.func.__name__ else: name = str(self.name) if isinstance(func, _Block): try: h = _getHierarchy(name, func) finally: _converting = 0 else: warnings.warn( "\n toVHDL(): Deprecated usage: See http://dev.myhdl.org/meps/mep-114.html", stacklevel=2) try: h = _HierExtr(name, func, *args, **kwargs) finally: _converting = 0 if self.directory is None: directory = '' else: directory = self.directory compDecls = self.component_declarations useClauses = self.use_clauses vpath = os.path.join(directory, name + ".vhd") vfile = open(vpath, 'w') ppath = os.path.join(directory, "pck_myhdl_%s.vhd" % _shortversion) pfile = None # # write MyHDL package always during development, as it may change # pfile = None # if not os.path.isfile(ppath): # pfile = open(ppath, 'w') if not self.no_myhdl_package: pfile = open(ppath, 'w') ### initialize properly ### _genUniqueSuffix.reset() _enumTypeSet.clear() _enumPortTypeSet.clear() arglist = _flatten(h.top) _checkArgs(arglist) genlist = _analyzeGens(arglist, h.absnames) siglist, memlist = _analyzeSigs(h.hierarchy, hdl='VHDL') # print h.top _annotateTypes(genlist) # infer interface if isinstance(func, _Block): # infer interface after signals have been analyzed func._inferInterface() intf = func else: intf = _analyzeTopFunc(func, *args, **kwargs) intf.name = name # sanity checks on interface for portname in intf.argnames: s = intf.argdict[portname] if s._name is None: raise ToVHDLError(_error.ShadowingSignal, portname) if s._inList: raise ToVHDLError(_error.PortInList, portname) # add enum types to port-related set if isinstance(s._val, EnumItemType): obj = s._val._type if obj in _enumTypeSet: _enumTypeSet.remove(obj) _enumPortTypeSet.add(obj) else: assert obj in _enumPortTypeSet doc = _makeDoc(inspect.getdoc(func)) needPck = len(_enumPortTypeSet) > 0 lib = self.library arch = self.architecture stdLogicPorts = self.std_logic_ports self._convert_filter(h, intf, siglist, memlist, genlist) if pfile: _writeFileHeader(pfile, ppath) print(_package, file=pfile) pfile.close() _writeFileHeader(vfile, vpath) if needPck: _writeCustomPackage(vfile, intf) _writeModuleHeader(vfile, intf, needPck, lib, arch, useClauses, doc, stdLogicPorts) _writeFuncDecls(vfile) _writeTypeDefs(vfile) _writeSigDecls(vfile, intf, siglist, memlist) _writeCompDecls(vfile, compDecls) _convertGens(genlist, siglist, memlist, vfile) _writeModuleFooter(vfile, arch) vfile.close() # tbfile.close() ### clean-up properly ### self._cleanup(siglist, memlist) return h.top def _cleanup(self, siglist, memlist): # clean up signals for sig in siglist: sig._clear() for mem in memlist: mem.name = None for s in mem.mem: s._clear() # clean up attributes self.name = None self.component_declarations = None self.header = '' self.no_myhdl_header = False self.no_myhdl_package = False self.architecture = "MyHDL" self.std_logic_ports = False def _convert_filter(self, h, intf, siglist, memlist, genlist): # intended to be a entry point for other uses: # code checking, optimizations, etc pass toVHDL = _ToVHDLConvertor() myhdl_header = """\ -- File: $filename -- Generated by MyHDL $version -- Date: $date """ def _writeFileHeader(f, fn): vars = dict(filename=fn, version=myhdl.__version__, date=datetime.today().ctime() ) if toVHDL.header: print(string.Template(toVHDL.header).substitute(vars), file=f) if not toVHDL.no_myhdl_header: print(string.Template(myhdl_header).substitute(vars), file=f) print(file=f) def _writeEnum(f, e): typename, names, codes = e.reftype() for name in names: # watch out _nameValid() will add every name to a check-list # which will force you to be inventive with state names ... # e.g. the typical 'IDLE' can only be used once # so let's pre-fix the enum name # we could have modified _nameValid() to take a default boolean argument _nameValid(''.join((typename, '.', name))) enumtypedecl = "type %s is (\n\t" % typename enumtypedecl += ",\n\t".join(names) enumtypedecl += "\n\t);\n" if codes is not None: enumtypedecl += 'attribute enum_encoding of %s: type is "%s";\n' % (typename, codes) f.write('{}'.format(enumtypedecl)) def _writeCustomPackage(f, intf): print(file=f) print("package pck_%s is" % intf.name, file=f) print(file=f) print("attribute enum_encoding: string;", file=f) print(file=f) sortedList = list(_enumPortTypeSet) sortedList.sort(key=lambda x: x._name) for t in sortedList: # print(" %s" % t._toVHDL(), file=f) _writeEnum(f, t) print(file=f) print("end package pck_%s;" % intf.name, file=f) print(file=f) portConversions = [] def _writeModuleHeader(f, intf, needPck, lib, arch, useClauses, doc, stdLogicPorts): print("library IEEE;", file=f) print("use IEEE.std_logic_1164.all;", file=f) print("use IEEE.numeric_std.all;", file=f) print("use std.textio.all;", file=f) print(file=f) if lib != "work": print("library %s;" % lib, file=f) if useClauses is not None: f.write(useClauses) f.write("\n") else: print("use %s.pck_myhdl_%s.all;" % (lib, _shortversion), file=f) print(file=f) if needPck: print("use %s.pck_%s.all;" % (lib, intf.name), file=f) print(file=f) print("entity %s is" % intf.name, file=f) del portConversions[:] if intf.argnames: f.write(" port (") c = '' for portname in intf.argnames: _nameValid(portname) s = intf.argdict[portname] f.write("%s" % c) c = ';' # change name to convert to std_logic, or # make sure signal name is equal to its port name convertPort = False if stdLogicPorts and s._type is intbv: s._name = portname + "_num" convertPort = True for sl in s._slicesigs: sl._setName('VHDL') else: s._name = portname r = _getRangeString(s) pt = st = _getTypeString(s) if convertPort: pt = "std_logic_vector" # # Check if VHDL keyword or reused name # _nameValid(s._name) if s._driven: if s._read: if not isinstance(s, _TristateSignal): warnings.warn("%s: %s" % (_error.OutputPortRead, portname), category=ToVHDLWarning ) f.write("\n %s: inout %s%s" % (portname, pt, r)) else: f.write("\n %s: out %s%s" % (portname, pt, r)) if convertPort: portConversions.append("%s <= %s(%s);" % (portname, pt, s._name)) s._read = True else: if not s._read: warnings.warn("%s: %s" % (_error.UnusedPort, portname), category=ToVHDLWarning ) f.write("\n %s: in %s%s" % (portname, pt, r)) if convertPort: portConversions.append("%s <= %s(%s);" % (s._name, st, portname)) s._driven = True f.write("\n );\n") print("end entity %s;" % intf.name, file=f) print(doc, file=f) print(file=f) print("architecture %s of %s is" % (arch, intf.name), file=f) print(file=f) def _writeFuncDecls(f): return # print >> f, package def _writeTypeDefs(f): f.write("\n") sortedList = list(_enumTypeSet) sortedList.sort(key=lambda x: x._name) for t in sortedList: # f.write("%s\n" % t._toVHDL()) # typename, names, codes = t.reftype() # for name in names: # # watch out _nameValid() will add every name to a check-list # # which will force you to be inventive with state names ... # # e.g. the typical 'IDLE' can only be used once # # so let's pre-fix the enum name # # we could have modified _nameValid() to take a default boolean argument # _nameValid(''.join((typename, '.', name))) # # enumtypedecl = "type %s is (\n\t" % typename # enumtypedecl += ",\n\t".join(names) # enumtypedecl += "\n\t);\n" # if codes is not None: # enumtypedecl += 'attribute enum_encoding of %s: type is "%s";\n' % (typename, codes) # f.write('{}'.format(enumtypedecl)) _writeEnum(f, t) # a final blank separator line f.write("\n") constwires = [] def _writeSigDecls(f, intf, siglist, memlist): del constwires[:] for s in siglist: if not s._used: continue if s._name in intf.argnames: continue r = _getRangeString(s) p = _getTypeString(s) # Check if VHDL keyword or reused name _nameValid(s._name) if s._driven: if not s._read and not isinstance(s, _TristateDriver): warnings.warn("%s: %s" % (_error.UnreadSignal, s._name), category=ToVHDLWarning ) # the following line implements initial value assignments sig_vhdl_obj = inferVhdlObj(s) if not toVHDL.initial_values: val_str = "" else: if isinstance(sig_vhdl_obj, vhd_std_logic): # Single bit val_str = " := '%s'" % int(s._init) elif isinstance(sig_vhdl_obj, vhd_int): val_str = " := %s" % s._init elif isinstance(sig_vhdl_obj, (vhd_signed, vhd_unsigned)): val_str = ' := %dX"%s"' % ( sig_vhdl_obj.size, str(s._init)) elif isinstance(sig_vhdl_obj, vhd_enum): val_str = ' := %s' % (s._init,) else: # default to no initial value val_str = '' print("signal %s: %s%s%s;" % (s._name, p, r, val_str), file=f) elif s._read: # the original exception # raise ToVHDLError(_error.UndrivenSignal, s._name) # changed to a warning and a continuous assignment to a wire warnings.warn("%s: %s" % (_error.UndrivenSignal, s._name), category=ToVHDLWarning ) constwires.append(s) print("signal %s: %s%s;" % (s._name, p, r), file=f) for m in memlist: if not m._used: continue # infer attributes for the case of named signals in a list for i, s in enumerate(m.mem): if not m._driven and s._driven: m._driven = s._driven if not m._read and s._read: m._read = s._read if not m._driven and not m._read: continue # Check if VHDL keyword or reused name _nameValid(m.name) r = _getRangeString(m.elObj) p = _getTypeString(m.elObj) t = "t_array_%s" % m.name if not toVHDL.initial_values: val_str = "" else: sig_vhdl_objs = [inferVhdlObj(each) for each in m.mem] if all([each._init == m.mem[0]._init for each in m.mem]): if isinstance(m.mem[0]._init, bool): val_str = ( ' := (others => \'%s\')' % str(int(m.mem[0]._init))) else: val_str = ( ' := (others => %dX"%s")' % (sig_vhdl_objs[0].size, str(m.mem[0]._init))) else: _val_str = ',\n '.join( ['%dX"%s"' % (obj.size, str(each._init)) for obj, each in zip(sig_vhdl_objs, m.mem)]) val_str = ' := (\n ' + _val_str + ')' print("type %s is array(0 to %s-1) of %s%s;" % (t, m.depth, p, r), file=f) print("signal %s: %s%s;" % (m.name, t, val_str), file=f) print(file=f) def _writeCompDecls(f, compDecls): if compDecls is not None: print(compDecls, file=f) def _writeModuleFooter(f, arch): print("end architecture %s;" % arch, file=f) def _getRangeString(s): if isinstance(s._val, EnumItemType): return '' elif s._type is bool: return '' elif s._nrbits is not None: msb = s._nrbits - 1 return "(%s downto 0)" % msb else: raise AssertionError def _getTypeString(s): if isinstance(s._val, EnumItemType): return s._val._type._name elif s._type is bool: return "std_logic" if s._min is not None and s._min < 0: return "signed " else: return 'unsigned' def _convertGens(genlist, siglist, memlist, vfile): blockBuf = StringIO() funcBuf = StringIO() for tree in genlist: if isinstance(tree, _UserVhdlCode): blockBuf.write(str(tree)) continue if tree.kind == _kind.ALWAYS: Visitor = _ConvertAlwaysVisitor elif tree.kind == _kind.INITIAL: Visitor = _ConvertInitialVisitor elif tree.kind == _kind.SIMPLE_ALWAYS_COMB: Visitor = _ConvertSimpleAlwaysCombVisitor elif tree.kind == _kind.ALWAYS_DECO: Visitor = _ConvertAlwaysDecoVisitor elif tree.kind == _kind.ALWAYS_SEQ: Visitor = _ConvertAlwaysSeqVisitor else: # ALWAYS_COMB Visitor = _ConvertAlwaysCombVisitor v = Visitor(tree, blockBuf, funcBuf) v.visit(tree) vfile.write(funcBuf.getvalue()) funcBuf.close() print("begin", file=vfile) print(file=vfile) for st in portConversions: print(st, file=vfile) print(file=vfile) for s in constwires: if s._type is bool: c = int(s._val) pre, suf = "'", "'" elif s._type is intbv: c = int(s._val) w = len(s) assert w != 0 if s._min < 0: if w <= 31: pre, suf = "to_signed(", ", %s)" % w else: pre, suf = "signed'(", ")" c = '"%s"' % tobin(c, w) else: if w <= 31: pre, suf = "to_unsigned(", ", %s)" % w else: pre, suf = "unsigned'(", ")" c = '"%s"' % tobin(c, w) else: raise ToVHDLError("Unexpected type for constant signal", s._name) print("%s <= %s%s%s;" % (s._name, pre, c, suf), file=vfile) print(file=vfile) # shadow signal assignments for s in siglist: if hasattr(s, 'toVHDL') and s._read: print(s.toVHDL(), file=vfile) # hack for slice signals in a list for m in memlist: if m._read: for s in m.mem: if hasattr(s, 'toVHDL'): print(s.toVHDL(), file=vfile) print(file=vfile) vfile.write(blockBuf.getvalue()) blockBuf.close() opmap = { ast.Add: '+', ast.Sub: '-', ast.Mult: '*', ast.Div: '/', ast.Mod: 'mod', ast.Pow: '**', ast.LShift: 'shift_left', ast.RShift: 'shift_right', ast.BitOr: 'or', ast.BitAnd: 'and', ast.BitXor: 'xor', ast.FloorDiv: '/', ast.Invert: 'not ', ast.Not: 'not ', ast.UAdd: '+', ast.USub: '-', ast.Eq: '=', ast.Gt: '>', ast.GtE: '>=', ast.Lt: '<', ast.LtE: '<=', ast.NotEq: '/=', ast.And: 'and', ast.Or: 'or', } class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin): def __init__(self, tree, buf): self.tree = tree self.buf = buf self.returnLabel = tree.name self.ind = '' self.SigAss = False self.isLhs = False self.labelStack = [] self.context = None def write(self, arg): self.buf.write("%s" % arg) def writeline(self, nr=1): for i in range(nr): self.buf.write("\n%s" % self.ind) def writeDoc(self, node): assert hasattr(node, 'doc') if node.doc is not None: doc = _makeDoc(node.doc, self.ind) self.write(doc) self.writeline() def IntRepr(self, obj): if obj >= 0: s = "%s" % int(obj) else: s = "(- %s)" % abs(int(obj)) return s def BitRepr(self, item, var): if isinstance(var._val, bool): return '\'%s\'' % tobin(item, len(var)) else: return '"%s"' % tobin(item, len(var)) def inferCast(self, vhd, ori): pre, suf = "", "" if isinstance(vhd, vhd_int): if not isinstance(ori, vhd_int): pre, suf = "to_integer(", ")" elif isinstance(vhd, vhd_unsigned): if isinstance(ori, vhd_unsigned): if vhd.size != ori.size: pre, suf = "resize(", ", %s)" % vhd.size elif isinstance(ori, vhd_signed): if vhd.size != ori.size: # note the order of resizing and casting here (otherwise bug!) pre, suf = "resize(unsigned(", "), %s)" % vhd.size else: pre, suf = "unsigned(", ")" else: pre, suf = "to_unsigned(", ", %s)" % vhd.size elif isinstance(vhd, vhd_signed): if isinstance(ori, vhd_signed): if vhd.size != ori.size: pre, suf = "resize(", ", %s)" % vhd.size elif isinstance(ori, vhd_unsigned): if vhd.size != ori.size: # I think this should be the order of resizing and casting here pre, suf = "signed(resize(", ", %s))" % vhd.size else: pre, suf = "signed(", ")" else: pre, suf = "to_signed(", ", %s)" % vhd.size elif isinstance(vhd, vhd_boolean): if not isinstance(ori, vhd_boolean): pre, suf = "bool(", ")" elif isinstance(vhd, vhd_std_logic): if not isinstance(ori, vhd_std_logic): if isinstance(ori, vhd_unsigned): pre, suf = "", "(0)" else: pre, suf = "stdl(", ")" # elif isinstance(vhd, vhd_string): # if isinstance(ori, vhd_enum): # pre, suf = "%s'image(" % ori._type._name, ")" return pre, suf def writeIntSize(self, n): # write size for large integers (beyond 32 bits signed) # with some safety margin if n >= 2 ** 30: size = int(math.ceil(math.log(n + 1, 2))) + 1 # sign bit! self.write("%s'sd" % size) def writeDeclaration(self, obj, name, kind="", dir="", endchar=";", constr=True): if isinstance(obj, EnumItemType): tipe = obj._type._name elif isinstance(obj, _Ram): tipe = "t_array_%s" % name elt = inferVhdlObj(obj.elObj).toStr(True) self.write("type %s is array(0 to %s-1) of %s;" % (tipe, obj.depth, elt)) self.writeline() else: vhd = inferVhdlObj(obj) if isinstance(vhd, vhd_enum): tipe = obj._val._type._name else: tipe = vhd.toStr(constr) if kind: kind += " " if dir: dir += " " self.write("%s%s: %s%s%s" % (kind, name, dir, tipe, endchar)) def writeDeclarations(self): if self.tree.hasPrint: self.writeline() self.write("variable L: line;") for name, obj in self.tree.vardict.items(): if isinstance(obj, _loopInt): continue # hack for loop vars self.writeline() self.writeDeclaration(obj, name, kind="variable") def indent(self): self.ind += ' ' * 4 def dedent(self): self.ind = self.ind[:-4] def visit_BinOp(self, node): if isinstance(node.op, (ast.LShift, ast.RShift)): self.shiftOp(node) elif isinstance(node.op, (ast.BitAnd, ast.BitOr, ast.BitXor)): self.BitOp(node) else: self.BinOp(node) def inferBinaryOpCast(self, node, left, right, op): ns, os = node.vhd.size, node.vhdOri.size ds = ns - os if ds > 0: if isinstance(left.vhd, vhd_vector) and isinstance(right.vhd, vhd_vector): if isinstance(op, (ast.Add, ast.Sub)): left.vhd.size = ns # in general, resize right also # for a simple name, resizing is not necessary if not isinstance(right, ast.Name): right.vhd.size = ns node.vhdOri.size = ns elif isinstance(op, ast.Mod): right.vhd.size = ns node.vhdOri.size = ns elif isinstance(op, ast.FloorDiv): left.vhd.size = ns node.vhdOri.size = ns elif isinstance(op, ast.Mult): left.vhd.size += ds node.vhdOri.size = ns else: raise AssertionError("unexpected op %s" % op) elif isinstance(left.vhd, vhd_vector) and isinstance(right.vhd, vhd_int): if isinstance(op, (ast.Add, ast.Sub, ast.Mod, ast.FloorDiv)): left.vhd.size = ns node.vhdOri.size = ns elif isinstance(op, ast.Mult): left.vhd.size += ds node.vhdOri.size = 2 * left.vhd.size else: raise AssertionError("unexpected op %s" % op) elif isinstance(left.vhd, vhd_int) and isinstance(right.vhd, vhd_vector): if isinstance(op, (ast.Add, ast.Sub, ast.Mod, ast.FloorDiv)): right.vhd.size = ns node.vhdOri.size = ns elif isinstance(op, ast.Mult): node.vhdOri.size = 2 * right.vhd.size else: raise AssertionError("unexpected op %s" % op) pre, suf = self.inferCast(node.vhd, node.vhdOri) if pre == "": pre, suf = "(", ")" return pre, suf def BinOp(self, node): pre, suf = self.inferBinaryOpCast(node, node.left, node.right, node.op) self.write(pre) self.visit(node.left) self.write(" %s " % opmap[type(node.op)]) self.visit(node.right) self.write(suf) def inferShiftOpCast(self, node, left, right, op): ns, os = node.vhd.size, node.vhdOri.size ds = ns - os if ds > 0: if isinstance(node.left.vhd, vhd_vector): left.vhd.size = ns node.vhdOri.size = ns pre, suf = self.inferCast(node.vhd, node.vhdOri) return pre, suf def shiftOp(self, node): pre, suf = self.inferShiftOpCast(node, node.left, node.right, node.op) self.write(pre) self.write("%s(" % opmap[type(node.op)]) self.visit(node.left) self.write(", ") self.visit(node.right) self.write(")") self.write(suf) def BitOp(self, node): pre, suf = self.inferCast(node.vhd, node.vhdOri) self.write(pre) self.write("(") self.visit(node.left) self.write(" %s " % opmap[type(node.op)]) self.visit(node.right) self.write(")") self.write(suf) def visit_BoolOp(self, node): if isinstance(node.vhd, vhd_std_logic): self.write("stdl") self.write("(") self.visit(node.values[0]) for n in node.values[1:]: self.write(" %s " % opmap[type(node.op)]) self.visit(n) self.write(")") def visit_UnaryOp(self, node): # in python3 a negative Num is represented as an USub of a positive Num # Fix: restore python2 behavior by a shortcut: invert value of Num, inherit # vhdl type from UnaryOp node, and visit the modified operand if isinstance(node.op, ast.USub) and isinstance(node.operand, ast.Num): node.operand.n = -node.operand.n node.operand.vhd = node.vhd self.visit(node.operand) return pre, suf = self.inferCast(node.vhd, node.vhdOri) self.write(pre) self.write("(") self.write(opmap[type(node.op)]) self.visit(node.operand) self.write(")") self.write(suf) def visit_Attribute(self, node): if isinstance(node.ctx, ast.Store): self.setAttr(node) else: self.getAttr(node) def setAttr(self, node): assert node.attr == 'next' self.SigAss = True if isinstance(node.value, ast.Name): sig = self.tree.symdict[node.value.id] self.SigAss = sig._name self.visit(node.value) node.obj = self.getObj(node.value) def getAttr(self, node): if isinstance(node.value, ast.Subscript): self.setAttr(node) return assert isinstance(node.value, ast.Name), node.value n = node.value.id if n in self.tree.symdict: obj = self.tree.symdict[n] elif n in self.tree.vardict: obj = self.tree.vardict[n] else: raise AssertionError("object not found") if isinstance(obj, _Signal): if node.attr == 'next': sig = self.tree.symdict[node.value.id] self.SigAss = obj._name self.visit(node.value) elif node.attr == 'posedge': self.write("rising_edge(") self.visit(node.value) self.write(")") elif node.attr == 'negedge': self.write("falling_edge(") self.visit(node.value) self.write(")") elif node.attr == 'val': pre, suf = self.inferCast(node.vhd, node.vhdOri) self.write(pre) self.visit(node.value) self.write(suf) if isinstance(obj, (_Signal, intbv)): if node.attr in ('min', 'max'): pre, suf = self.inferCast(node.vhd, node.vhdOri) self.write(pre) self.write("%s" % node.obj) self.write(suf) if isinstance(obj, EnumType): assert hasattr(obj, node.attr) e = getattr(obj, node.attr) self.write(e._toVHDL()) def visit_Assert(self, node): # XXX self.write("assert ") self.visit(node.test) self.indent() self.writeline() self.write('report "*** AssertionError ***"') self.writeline() self.write("severity error;") self.dedent() def visit_Assign(self, node): lhs = node.targets[0] rhs = node.value # shortcut for expansion of ROM in case statement if isinstance(node.value, ast.Subscript) and \ isinstance(node.value.slice, ast.Index) and \ isinstance(node.value.value.obj, _Rom): rom = node.value.value.obj.rom self.write("case ") self.visit(node.value.slice) self.write(" is") self.indent() size = lhs.vhd.size for i, n in enumerate(rom): self.writeline() if i == len(rom) - 1: self.write("when others => ") else: self.write("when %s => " % i) self.visit(lhs) if self.SigAss: self.write(' <= ') self.SigAss = False else: self.write(' := ') if isinstance(lhs.vhd, vhd_std_logic): self.write("'%s';" % n) elif isinstance(lhs.vhd, vhd_int): self.write("%s;" % n) else: self.write('"%s";' % tobin(n, size)) self.dedent() self.writeline() self.write("end case;") return elif isinstance(node.value, ast.ListComp): # skip list comprehension assigns for now return # default behavior convOpen, convClose = "", "" if isinstance(lhs.vhd, vhd_type): rhs.vhd = lhs.vhd self.isLhs = True self.visit(lhs) self.isLhs = False if self.SigAss: if isinstance(lhs.value, ast.Name): sig = self.tree.symdict[lhs.value.id] self.write(' <= ') self.SigAss = False else: self.write(' := ') self.write(convOpen) # node.expr.target = obj = self.getObj(node.nodes[0]) self.visit(rhs) self.write(convClose) self.write(';') def visit_AugAssign(self, node): # XXX apparently no signed context required for augmented assigns left, op, right = node.target, node.op, node.value isFunc = False pre, suf = "", "" if isinstance(op, (ast.Add, ast.Sub, ast.Mult, ast.Mod, ast.FloorDiv)): pre, suf = self.inferBinaryOpCast(node, left, right, op) elif isinstance(op, (ast.LShift, ast.RShift)): isFunc = True pre, suf = self.inferShiftOpCast(node, left, right, op) self.visit(left) self.write(" := ") self.write(pre) if isFunc: self.write("%s(" % opmap[type(op)]) self.visit(left) if isFunc: self.write(", ") else: self.write(" %s " % opmap[type(op)]) self.visit(right) if isFunc: self.write(")") self.write(suf) self.write(";") def visit_Break(self, node): self.write("exit;") def visit_Call(self, node): fn = node.func # assert isinstance(fn, astNode.Name) f = self.getObj(fn) if f is print: self.visit_Print(node) return fname = '' pre, suf = '', '' opening, closing = '(', ')' sep = ", " if f is bool: opening, closing = '', '' arg = node.args[0] arg.vhd = node.vhd elif f is len: val = self.getVal(node) self.require(node, val is not None, "cannot calculate len") pre, suf = self.inferCast(node.vhd, node.vhdOri) self.write(pre) self.write(repr(val)) self.write(suf) return elif f is now: pre, suf = self.inferCast(node.vhd, node.vhdOri) self.write(pre) self.write("(now / 1 ns)") self.write(suf) return elif f is ord: opening, closing = '', '' v = ord(node.args[0].s) node.args[0].s = v self.write(v) return elif f in integer_types: opening, closing = '', '' pre, suf = self.inferCast(node.vhd, node.vhdOri) # convert number argument to integer if isinstance(node.args[0], ast.Num): node.args[0].n = int(node.args[0].n) elif inspect.isclass(f) and issubclass(f, intbv): pre, post = "", "" arg = node.args[0] if isinstance(node.vhd, vhd_unsigned): pre, post = "to_unsigned(", ", %s)" % node.vhd.size elif isinstance(node.vhd, vhd_signed): pre, post = "to_signed(", ", %s)" % node.vhd.size self.write(pre) self.visit(arg) self.write(post) return elif f == intbv.signed: # note equality comparison # this call comes from a getattr arg = fn.value pre, suf = self.inferCast(node.vhd, node.vhdOri) opening, closing = '', '' if isinstance(arg.vhd, vhd_unsigned): opening, closing = "signed(", ")" self.write(pre) self.write(opening) self.visit(arg) self.write(closing) self.write(suf) return elif (type(f) in class_types) and issubclass(f, Exception): self.write(f.__name__) elif f in (posedge, negedge): opening, closing = ' ', '' self.write(f.__name__) elif f is delay: self.visit(node.args[0]) self.write(" * 1 ns") return elif f is concat: pre, suf = self.inferCast(node.vhd, node.vhdOri) opening, closing = "unsigned'(", ")" sep = " & " elif hasattr(node, 'tree'): pre, suf = self.inferCast(node.vhd, node.tree.vhd) fname = node.tree.name else: self.write(f.__name__) if node.args: self.write(pre) # TODO rewrite making use of fname variable self.write(fname) self.write(opening) self.visit(node.args[0]) for arg in node.args[1:]: self.write(sep) self.visit(arg) self.write(closing) self.write(suf) if hasattr(node, 'tree'): if node.tree.kind == _kind.TASK: Visitor = _ConvertTaskVisitor else: Visitor = _ConvertFunctionVisitor v = Visitor(node.tree, self.funcBuf) v.visit(node.tree) def visit_Compare(self, node): n = node.vhd ns = node.vhd.size pre, suf = "(", ")" if isinstance(n, vhd_std_logic): pre = "stdl(" elif isinstance(n, vhd_unsigned): pre, suf = "to_unsigned(", ", %s)" % ns elif isinstance(n, vhd_signed): pre, suf = "to_signed(", ", %s)" % ns self.write(pre) self.visit(node.left) op, right = node.ops[0], node.comparators[0] self.write(" %s " % opmap[type(op)]) self.visit(right) self.write(suf) def visit_Num(self, node): n = node.n if isinstance(node.vhd, vhd_std_logic): self.write("'%s'" % n) elif isinstance(node.vhd, vhd_boolean): self.write("%s" % bool(n)) # elif isinstance(node.vhd, (vhd_unsigned, vhd_signed)): # self.write('"%s"' % tobin(n, node.vhd.size)) elif isinstance(node.vhd, vhd_unsigned): if abs(n) < 2 ** 31: self.write("to_unsigned(%s, %s)" % (n, node.vhd.size)) else: self.write('unsigned\'("%s")' % tobin(n, node.vhd.size)) elif isinstance(node.vhd, vhd_signed): if abs(n) < 2 ** 31: self.write("to_signed(%s, %s)" % (n, node.vhd.size)) else: self.write('signed\'("%s")' % tobin(n, node.vhd.size)) else: if n < 0: self.write("(") self.write(n) if n < 0: self.write(")") def visit_Str(self, node): typemark = 'string' if isinstance(node.vhd, vhd_unsigned): typemark = 'unsigned' self.write("%s'(\"%s\")" % (typemark, node.s)) def visit_Continue(self, node, *args): self.write("next;") def visit_Expr(self, node): expr = node.value # docstrings on unofficial places if isinstance(expr, ast.Str): doc = _makeDoc(expr.s, self.ind) self.write(doc) return # skip extra semicolons if isinstance(expr, ast.Num): return self.visit(expr) # ugly hack to detect an orphan "task" call if isinstance(expr, ast.Call) and hasattr(expr, 'tree'): self.write(';') def visit_IfExp(self, node): # propagate the node's vhd attribute node.body.vhd = node.orelse.vhd = node.vhd self.write('tern_op(') self.write('cond => ') self.visit(node.test) self.write(', if_true => ') self.visit(node.body) self.write(', if_false => ') self.visit(node.orelse) self.write(')') def visit_For(self, node): self.labelStack.append(node.breakLabel) self.labelStack.append(node.loopLabel) var = node.target.id cf = node.iter f = self.getObj(cf.func) args = cf.args assert len(args) <= 3 self.require(node, len(args) < 3, "explicit step not supported") self.require(node, len(args) > 0, "at least one argument requested") if f is range: cmp = '<' op = 'to' oneoff = '' if len(args) == 1: start, stop, step = None, args[0], None elif len(args) == 2: start, stop, step = args[0], args[1], None else: start, stop, step = args else: # downrange cmp = '>=' op = 'downto' if len(args) == 1: start, stop, step = args[0], None, None elif len(args) == 2: start, stop, step = args[0], args[1], None else: start, stop, step = args assert step is None # if node.breakLabel.isActive: # # self.write("begin: %s" % node.breakLabel) # self.writeline() # if node.loopLabel.isActive: # # self.write("%s: " % node.loopLabel) self.write("for %s in " % var) if start is None: self.write("0") else: self.visit(start) if f is downrange: self.write("-1") self.write(" %s " % op) if stop is None: self.write("0") else: self.visit(stop) if f is range: self.write("-1") self.write(" loop") self.indent() self.visit_stmt(node.body) self.dedent() self.writeline() self.write("end loop;") # if node.breakLabel.isActive: # self.writeline() # self.write("end") self.labelStack.pop() self.labelStack.pop() def visit_FunctionDef(self, node): raise AssertionError("To be implemented in subclass") def visit_If(self, node): if node.ignore: return # only map to VHDL case if it's a full case if node.isFullCase: self.mapToCase(node) else: self.mapToIf(node) def mapToCase(self, node): var = node.caseVar obj = self.getObj(var) self.write("case ") self.visit(var) self.write(" is") self.indent() for i, (test, suite) in enumerate(node.tests): self.writeline() item = test.case[1] if isinstance(item, EnumItemType): itemRepr = item._toVHDL() elif hasattr(obj, '_nrbits'): itemRepr = self.BitRepr(item, obj) else: itemRepr = i comment = "" # potentially use default clause for last test if (i == len(node.tests) - 1) and not node.else_: self.write("when others") comment = " -- %s" % itemRepr else: self.write("when ") self.write(itemRepr) self.write(" =>%s" % comment) self.indent() self.visit_stmt(suite) self.dedent() if node.else_: self.writeline() self.write("when others =>") self.indent() self.visit_stmt(node.else_) self.dedent() self.dedent() self.writeline() self.write("end case;") def mapToIf(self, node): first = True for test, suite in node.tests: if first: ifstring = "if " first = False else: ifstring = "elsif " self.writeline() self.write(ifstring) self.visit(test) self.write(" then") self.indent() self.visit_stmt(suite) self.dedent() if node.else_: self.writeline() edges = self.getEdge(node) if edges is not None: edgeTests = [e._toVHDL() for e in edges] self.write("elsif ") self.write(" or ".join(edgeTests)) self.write(" then") else: self.write("else") self.indent() self.visit_stmt(node.else_) self.dedent() self.writeline() self.write("end if;") def visit_ListComp(self, node): pass # do nothing def visit_Module(self, node): for stmt in node.body: self.visit(stmt) def visit_NameConstant(self, node): node.id = str(node.value) self.getName(node) def visit_Name(self, node): if isinstance(node.ctx, ast.Store): self.setName(node) else: self.getName(node) def setName(self, node): self.write(node.id) def getName(self, node): n = node.id if n == 'False': if isinstance(node.vhd, vhd_std_logic): s = "'0'" else: s = "False" elif n == 'True': if isinstance(node.vhd, vhd_std_logic): s = "'1'" else: s = "True" elif n == 'None': if isinstance(node.vhd, vhd_std_logic): s = "'Z'" else: assert hasattr(node.vhd, 'size') s = '"%s"' % ('Z' * node.vhd.size) elif n in self.tree.vardict: s = n obj = self.tree.vardict[n] ori = inferVhdlObj(obj) pre, suf = self.inferCast(node.vhd, ori) s = "%s%s%s" % (pre, s, suf) elif n in self.tree.argnames: assert n in self.tree.symdict obj = self.tree.symdict[n] vhd = inferVhdlObj(obj) if isinstance(vhd, vhd_std_logic) and isinstance(node.vhd, vhd_boolean): s = "(%s = '1')" % n else: s = n elif n in self.tree.symdict: obj = self.tree.symdict[n] s = n if isinstance(obj, bool): if isinstance(node.vhd, vhd_std_logic): s = "'%s'" % int(obj) else: s = "%s" % obj elif isinstance(obj, integer_types): if isinstance(node.vhd, vhd_int): s = self.IntRepr(obj) elif isinstance(node.vhd, vhd_boolean): s = "%s" % bool(obj) elif isinstance(node.vhd, vhd_std_logic): s = "'%s'" % int(obj) elif isinstance(node.vhd, vhd_unsigned): if abs(obj) < 2 ** 31: s = "to_unsigned(%s, %s)" % (obj, node.vhd.size) else: s = 'unsigned\'("%s")' % tobin(obj, node.vhd.size) elif isinstance(node.vhd, vhd_signed): if abs(obj) < 2 ** 31: s = "to_signed(%s, %s)" % (obj, node.vhd.size) else: s = 'signed\'("%s")' % tobin(obj, node.vhd.size) elif isinstance(obj, _Signal): s = str(obj) ori = inferVhdlObj(obj) pre, suf = self.inferCast(node.vhd, ori) s = "%s%s%s" % (pre, s, suf) elif _isMem(obj): m = _getMemInfo(obj) assert m.name s = m.name elif isinstance(obj, EnumItemType): s = obj._toVHDL() elif (type(obj) in class_types) and issubclass(obj, Exception): s = n else: self.raiseError(node, _error.UnsupportedType, "%s, %s" % (n, type(obj))) else: raise AssertionError("name ref: %s" % n) self.write(s) def visit_Pass(self, node): self.write("null;") def visit_Print(self, node): argnr = 0 for s in node.format: if isinstance(s, str): self.write('write(L, string\'("%s"));' % s) else: a = node.args[argnr] argnr += 1 to_string = "to_string" if s.conv is int: a.vhd = vhd_int() else: if isinstance(a.vhdOri, vhd_vector): to_string = "to_hstring" # to_hstring correctly does sign extension # however, Verilog doesn not: therefore, interprete # print values as unsigned... a.vhd = vhd_unsigned(a.vhd.size) elif isinstance(a.vhdOri, vhd_std_logic): a.vhd = vhd_boolean() self.write("write(L, %s(" % to_string) self.visit(a) self.write("))") self.write(';') self.writeline() self.write("writeline(output, L);") def visit_Raise(self, node): self.write('assert False report "End of Simulation" severity Failure;') def visit_Return(self, node): pass def visit_Subscript(self, node): if isinstance(node.slice, ast.Slice): self.accessSlice(node) else: self.accessIndex(node) def accessSlice(self, node): if isinstance(node.value, ast.Call) and \ node.value.func.obj in (intbv, modbv) and \ _isConstant(node.value.args[0], self.tree.symdict): c = self.getVal(node)._val pre, post = "", "" if node.vhd.size <= 30: if isinstance(node.vhd, vhd_unsigned): pre, post = "to_unsigned(", ", %s)" % node.vhd.size elif isinstance(node.vhd, vhd_signed): pre, post = "to_signed(", ", %s)" % node.vhd.size else: if isinstance(node.vhd, vhd_unsigned): pre, post = "unsigned'(", ")" c = '"%s"' % tobin(c, node.vhd.size) elif isinstance(node.vhd, vhd_signed): pre, post = "signed'(", ")" c = '"%s"' % tobin(c, node.vhd.size) self.write(pre) self.write("%s" % c) self.write(post) return pre, suf = self.inferCast(node.vhd, node.vhdOri) if isinstance(node.value.vhd, vhd_signed) and isinstance(node.ctx, ast.Load): pre = pre + "unsigned(" suf = ")" + suf self.write(pre) self.visit(node.value) lower, upper = node.slice.lower, node.slice.upper # special shortcut case for [:] slice if lower is None and upper is None: self.write(suf) return self.write("(") if lower is None: self.write("%s" % node.obj._nrbits) else: self.visit(lower) self.write("-1 downto ") if upper is None: self.write("0") else: self.visit(upper) self.write(")") self.write(suf) def accessIndex(self, node): pre, suf = self.inferCast(node.vhd, node.vhdOri) self.write(pre) self.visit(node.value) self.write("(") # assert len(node.subs) == 1 self.visit(node.slice.value) self.write(")") self.write(suf) def visit_stmt(self, body): for stmt in body: self.writeline() self.visit(stmt) # ugly hack to detect an orphan "task" call if isinstance(stmt, ast.Call) and hasattr(stmt, 'tree'): self.write(';') def visit_Tuple(self, node): assert self.context != None sep = ", " tpl = node.elts self.visit(tpl[0]) for elt in tpl[1:]: self.write(sep) self.visit(elt) def visit_While(self, node): self.labelStack.append(node.breakLabel) self.labelStack.append(node.loopLabel) self.write("while ") self.visit(node.test) self.write(" loop") self.indent() self.visit_stmt(node.body) self.dedent() self.writeline() self.write("end loop") self.write(";") self.labelStack.pop() self.labelStack.pop() def visit_Yield(self, node): self.write("wait ") yieldObj = self.getObj(node.value) if isinstance(yieldObj, delay): self.write("for ") elif isinstance(yieldObj, _WaiterList): self.write("until ") else: self.write("on ") self.context = _context.YIELD self.visit(node.value) self.context = _context.UNKNOWN self.write(";") def manageEdges(self, ifnode, senslist): """ Helper method to convert MyHDL style template into VHDL style""" first = senslist[0] if isinstance(first, _WaiterList): bt = _WaiterList elif isinstance(first, _Signal): bt = _Signal elif isinstance(first, delay): bt = delay assert bt for e in senslist: if not isinstance(e, bt): self.raiseError(ifnode, "base type error in sensitivity list") if len(senslist) >= 2 and bt == _WaiterList: # ifnode = node.code.nodes[0] # print ifnode assert isinstance(ifnode, ast.If) asyncEdges = [] for test, suite in ifnode.tests: e = self.getEdge(test) if e is None: self.raiseError(ifnode, "No proper edge value test") asyncEdges.append(e) if not ifnode.else_: self.raiseError(ifnode, "No separate else clause found") edges = [] for s in senslist: for e in asyncEdges: if s is e: break else: edges.append(s) ifnode.edge = edges senslist = [s.sig for s in senslist] return senslist class _ConvertAlwaysVisitor(_ConvertVisitor): def __init__(self, tree, blockBuf, funcBuf): _ConvertVisitor.__init__(self, tree, blockBuf) self.funcBuf = funcBuf def visit_FunctionDef(self, node): self.writeDoc(node) w = node.body[-1] y = w.body[0] if isinstance(y, ast.Expr): y = y.value assert isinstance(y, ast.Yield) senslist = y.senslist senslist = self.manageEdges(w.body[1], senslist) singleEdge = (len(senslist) == 1) and isinstance(senslist[0], _WaiterList) self.write("%s: process (" % self.tree.name) if singleEdge: self.write(senslist[0].sig) else: for e in senslist[:-1]: self.write(e) self.write(', ') self.write(senslist[-1]) self.write(") is") self.indent() self.writeDeclarations() self.dedent() self.writeline() self.write("begin") self.indent() if singleEdge: self.writeline() self.write("if %s then" % senslist[0]._toVHDL()) self.indent() # assert isinstance(w.body, ast.stmt) for stmt in w.body[1:]: self.writeline() self.visit(stmt) self.dedent() if singleEdge: self.writeline() self.write("end if;") self.dedent() self.writeline() self.write("end process %s;" % self.tree.name) self.writeline(2) class _ConvertInitialVisitor(_ConvertVisitor): def __init__(self, tree, blockBuf, funcBuf): _ConvertVisitor.__init__(self, tree, blockBuf) self.funcBuf = funcBuf def visit_FunctionDef(self, node): self.writeDoc(node) self.write("%s: process is" % self.tree.name) self.indent() self.writeDeclarations() self.dedent() self.writeline() self.write("begin") self.indent() self.visit_stmt(node.body) self.writeline() self.write("wait;") self.dedent() self.writeline() self.write("end process %s;" % self.tree.name) self.writeline(2) class _ConvertAlwaysCombVisitor(_ConvertVisitor): def __init__(self, tree, blockBuf, funcBuf): _ConvertVisitor.__init__(self, tree, blockBuf) self.funcBuf = funcBuf def visit_FunctionDef(self, node): # a local function works nicely too def compressSensitivityList(senslist): ''' reduce spelled out list items like [*name*(0), *name*(1), ..., *name*(n)] to just *name*''' r = [] for item in senslist: name = item._name.split('(', 1)[0] if not name in r: # note that the list now contains names and not Signals, but we are # interested in the strings anyway ... r.append(name) return r self.writeDoc(node) senslist = compressSensitivityList(self.tree.senslist) self.write("%s: process (" % self.tree.name) for e in senslist[:-1]: self.write(e) self.write(', ') self.write(senslist[-1]) self.write(") is") self.indent() self.writeDeclarations() self.dedent() self.writeline() self.write("begin") self.indent() self.visit_stmt(node.body) self.dedent() self.writeline() self.write("end process %s;" % self.tree.name) self.writeline(2) class _ConvertSimpleAlwaysCombVisitor(_ConvertVisitor): def __init__(self, tree, blockBuf, funcBuf): _ConvertVisitor.__init__(self, tree, blockBuf) self.funcBuf = funcBuf def visit_Attribute(self, node): if isinstance(node.ctx, ast.Store): self.SigAss = True if isinstance(node.value, ast.Name): sig = self.tree.symdict[node.value.id] self.SigAss = sig._name self.visit(node.value) else: self.getAttr(node) def visit_FunctionDef(self, node, *args): self.writeDoc(node) self.visit_stmt(node.body) self.writeline(2) class _ConvertAlwaysDecoVisitor(_ConvertVisitor): def __init__(self, tree, blockBuf, funcBuf): _ConvertVisitor.__init__(self, tree, blockBuf) self.funcBuf = funcBuf def visit_FunctionDef(self, node, *args): self.writeDoc(node) assert self.tree.senslist senslist = self.tree.senslist senslist = self.manageEdges(node.body[-1], senslist) singleEdge = (len(senslist) == 1) and isinstance(senslist[0], _WaiterList) self.write("%s: process (" % self.tree.name) if singleEdge: self.write(senslist[0].sig) else: for e in senslist[:-1]: self.write(e) self.write(', ') self.write(senslist[-1]) self.write(") is") self.indent() self.writeDeclarations() self.dedent() self.writeline() self.write("begin") self.indent() if singleEdge: self.writeline() self.write("if %s then" % senslist[0]._toVHDL()) self.indent() self.visit_stmt(node.body) self.dedent() if singleEdge: self.writeline() self.write("end if;") self.dedent() self.writeline() self.write("end process %s;" % self.tree.name) self.writeline(2) def _convertInitVal(reg, init): pre, suf = '', '' if isinstance(reg, _Signal): tipe = reg._type else: assert isinstance(reg, intbv) tipe = intbv if tipe is bool: v = "'1'" if init else "'0'" elif tipe is intbv: init = int(init) # int representation vhd_tipe = 'unsigned' if reg._min is not None and reg._min < 0: vhd_tipe = 'signed' if abs(init) < 2 ** 31: v = '%sto_%s(%s, %s)%s' % (pre, vhd_tipe, init, len(reg), suf) else: v = '%s%s\'"%s"%s' % (pre, vhd_tipe, tobin(init, len(reg)), suf) else: assert isinstance(init, EnumItemType) v = init._toVHDL() return v class _ConvertAlwaysSeqVisitor(_ConvertVisitor): def __init__(self, tree, blockBuf, funcBuf): _ConvertVisitor.__init__(self, tree, blockBuf) self.funcBuf = funcBuf def visit_FunctionDef(self, node, *args): self.writeDoc(node) assert self.tree.senslist senslist = self.tree.senslist edge = senslist[0] reset = self.tree.reset isasync = reset is not None and reset.isasync sigregs = self.tree.sigregs varregs = self.tree.varregs self.write("%s: process (" % self.tree.name) self.write(edge.sig) if isasync: self.write(', ') self.write(reset) self.write(") is") self.indent() self.writeDeclarations() self.dedent() self.writeline() self.write("begin") self.indent() if not isasync: self.writeline() self.write("if %s then" % edge._toVHDL()) self.indent() if reset is not None: self.writeline() self.write("if (%s = '%s') then" % (reset, int(reset.active))) self.indent() for s in sigregs: self.writeline() self.write("%s <= %s;" % (s, _convertInitVal(s, s._init))) for v in varregs: n, reg, init = v self.writeline() self.write("%s := %s;" % (n, _convertInitVal(reg, init))) self.dedent() self.writeline() if isasync: self.write("elsif %s then" % edge._toVHDL()) else: self.write("else") self.indent() self.visit_stmt(node.body) self.dedent() if reset is not None: self.writeline() self.write("end if;") self.dedent() if not isasync: self.writeline() self.write("end if;") self.dedent() self.writeline() self.write("end process %s;" % self.tree.name) self.writeline(2) class _ConvertFunctionVisitor(_ConvertVisitor): def __init__(self, tree, funcBuf): _ConvertVisitor.__init__(self, tree, funcBuf) self.returnObj = tree.returnObj self.returnLabel = _Label("RETURN") def writeOutputDeclaration(self): self.write(self.tree.vhd.toStr(constr=False)) def writeInputDeclarations(self): endchar = "" for name in self.tree.argnames: self.write(endchar) endchar = ";" obj = self.tree.symdict[name] self.writeline() self.writeDeclaration(obj, name, dir="in", constr=False, endchar="") def visit_FunctionDef(self, node): self.write("function %s(" % self.tree.name) self.indent() self.writeInputDeclarations() self.writeline() self.write(") return ") self.writeOutputDeclaration() self.write(" is") self.writeDeclarations() self.dedent() self.writeline() self.write("begin") self.indent() self.visit_stmt(node.body) self.dedent() self.writeline() self.write("end function %s;" % self.tree.name) self.writeline(2) def visit_Return(self, node): self.write("return ") node.value.vhd = self.tree.vhd self.visit(node.value) self.write(";") class _ConvertTaskVisitor(_ConvertVisitor): def __init__(self, tree, funcBuf): _ConvertVisitor.__init__(self, tree, funcBuf) self.returnLabel = _Label("RETURN") def writeInterfaceDeclarations(self): endchar = "" for name in self.tree.argnames: self.write(endchar) endchar = ";" obj = self.tree.symdict[name] output = name in self.tree.outputs input = name in self.tree.inputs inout = input and output dir = (inout and "inout") or (output and "out") or "in" self.writeline() if isinstance(obj, _Signal): kind = 'signal' else: kind = '' self.writeDeclaration(obj, name, kind=kind, dir=dir, constr=False, endchar="") def visit_FunctionDef(self, node): self.write("procedure %s" % self.tree.name) if self.tree.argnames: self.write("(") self.indent() self.writeInterfaceDeclarations() self.write(")") self.write(" is") self.writeDeclarations() self.dedent() self.writeline() self.write("begin") self.indent() self.visit_stmt(node.body) self.dedent() self.writeline() self.write("end procedure %s;" % self.tree.name) self.writeline(2) # type inference class vhd_type(object): def __init__(self, size=0): self.size = size def __repr__(self): return "%s(%s)" % (type(self).__name__, self.size) class vhd_string(vhd_type): pass class vhd_enum(vhd_type): def __init__(self, tipe): self._type = tipe def toStr(self, constr=True): return self._type.__dict__['_name'] class vhd_std_logic(vhd_type): def __init__(self, size=0): vhd_type.__init__(self) self.size = 1 def toStr(self, constr=True): return 'std_logic' class vhd_boolean(vhd_type): def __init__(self, size=0): vhd_type.__init__(self) self.size = 1 def toStr(self, constr=True): return 'boolean' class vhd_vector(vhd_type): def __init__(self, size=0): vhd_type.__init__(self, size) class vhd_unsigned(vhd_vector): def toStr(self, constr=True): if constr: return "unsigned(%s downto 0)" % (self.size - 1) else: return "unsigned" class vhd_signed(vhd_vector): def toStr(self, constr=True): if constr: return "signed(%s downto 0)" % (self.size - 1) else: return "signed" class vhd_int(vhd_type): def toStr(self, constr=True): return "integer" class vhd_nat(vhd_int): def toStr(self, constr=True): return "natural" class _loopInt(int): pass def maxType(o1, o2): s1 = s2 = 0 if isinstance(o1, vhd_type): s1 = o1.size if isinstance(o2, vhd_type): s2 = o2.size s = max(s1, s2) if isinstance(o1, vhd_signed) or isinstance(o2, vhd_signed): return vhd_signed(s) elif isinstance(o1, vhd_unsigned) or isinstance(o2, vhd_unsigned): return vhd_unsigned(s) elif isinstance(o1, vhd_std_logic) or isinstance(o2, vhd_std_logic): return vhd_std_logic() elif isinstance(o1, vhd_int) or isinstance(o2, vhd_int): return vhd_int() else: return None def inferVhdlObj(obj): vhd = None if (isinstance(obj, _Signal) and obj._type is intbv) or \ isinstance(obj, intbv): if obj.min is None or obj.min < 0: vhd = vhd_signed(size=len(obj)) else: vhd = vhd_unsigned(size=len(obj)) elif (isinstance(obj, _Signal) and obj._type is bool) or \ isinstance(obj, bool): vhd = vhd_std_logic() elif (isinstance(obj, _Signal) and isinstance(obj._val, EnumItemType)) or\ isinstance(obj, EnumItemType): if isinstance(obj, _Signal): tipe = obj._val._type else: tipe = obj._type vhd = vhd_enum(tipe) elif isinstance(obj, integer_types): if obj >= 0: vhd = vhd_nat() else: vhd = vhd_int() # vhd = vhd_int() return vhd def maybeNegative(vhd): if isinstance(vhd, vhd_signed): return True if isinstance(vhd, vhd_int) and not isinstance(vhd, vhd_nat): return True return False class _AnnotateTypesVisitor(ast.NodeVisitor, _ConversionMixin): def __init__(self, tree): self.tree = tree def visit_FunctionDef(self, node): # don't visit arguments and decorators for stmt in node.body: self.visit(stmt) def visit_Attribute(self, node): self.generic_visit(node) node.vhd = inferVhdlObj(node.obj) node.vhdOri = copy(node.vhd) def visit_Assert(self, node): self.visit(node.test) node.test.vhd = vhd_boolean() def visit_AugAssign(self, node): self.visit(node.target) self.visit(node.value) if isinstance(node.op, (ast.BitOr, ast.BitAnd, ast.BitXor)): node.value.vhd = copy(node.target.vhd) node.vhdOri = copy(node.target.vhd) elif isinstance(node.op, (ast.RShift, ast.LShift)): node.value.vhd = vhd_int() node.vhdOri = copy(node.target.vhd) else: node.left, node.right = node.target, node.value self.inferBinOpType(node) node.vhd = copy(node.target.vhd) def visit_Call(self, node): fn = node.func # assert isinstance(fn, astNode.Name) f = self.getObj(fn) node.vhd = inferVhdlObj(node.obj) self.generic_visit(node) if f is concat: s = 0 for a in node.args: if isinstance(a, ast.Str): a.vhd = vhd_unsigned(a.vhd.size) elif isinstance(a.vhd, vhd_signed): a.vhd = vhd_unsigned(a.vhd.size) s += a.vhd.size node.vhd = vhd_unsigned(s) elif f is bool: node.vhd = vhd_boolean() elif f in _flatten(integer_types, ord): node.vhd = vhd_int() node.args[0].vhd = vhd_int() elif f in (intbv, modbv): node.vhd = vhd_int() elif f is len: node.vhd = vhd_int() elif f is now: node.vhd = vhd_nat() elif f == intbv.signed: # note equality comparison # this comes from a getattr # node.vhd = vhd_int() node.vhd = vhd_signed(fn.value.vhd.size) elif hasattr(node, 'tree'): v = _AnnotateTypesVisitor(node.tree) v.visit(node.tree) node.vhd = node.tree.vhd = inferVhdlObj(node.tree.returnObj) node.vhdOri = copy(node.vhd) def visit_Compare(self, node): node.vhd = vhd_boolean() self.generic_visit(node) left, op, right = node.left, node.ops[0], node.comparators[0] if isinstance(left.vhd, vhd_std_logic) or isinstance(right.vhd, vhd_std_logic): left.vhd = right.vhd = vhd_std_logic() elif isinstance(left.vhd, vhd_unsigned) and maybeNegative(right.vhd): left.vhd = vhd_signed(left.vhd.size + 1) elif maybeNegative(left.vhd) and isinstance(right.vhd, vhd_unsigned): right.vhd = vhd_signed(right.vhd.size + 1) node.vhdOri = copy(node.vhd) def visit_Str(self, node): node.vhd = vhd_string() node.vhdOri = copy(node.vhd) def visit_Num(self, node): if node.n < 0: node.vhd = vhd_int() else: node.vhd = vhd_nat() node.vhdOri = copy(node.vhd) def visit_For(self, node): var = node.target.id # make it possible to detect loop variable self.tree.vardict[var] = _loopInt(-1) self.generic_visit(node) def visit_NameConstant(self, node): node.vhd = inferVhdlObj(node.value) node.vhdOri = copy(node.vhd) def visit_Name(self, node): if node.id in self.tree.vardict: node.obj = self.tree.vardict[node.id] node.vhd = inferVhdlObj(node.obj) node.vhdOri = copy(node.vhd) def visit_BinOp(self, node): self.generic_visit(node) if isinstance(node.op, (ast.LShift, ast.RShift)): self.inferShiftType(node) elif isinstance(node.op, (ast.BitAnd, ast.BitOr, ast.BitXor)): self.inferBitOpType(node) elif isinstance(node.op, ast.Mod) and isinstance(node.left, ast.Str): # format string pass else: self.inferBinOpType(node) def inferShiftType(self, node): node.vhd = copy(node.left.vhd) node.right.vhd = vhd_nat() node.vhdOri = copy(node.vhd) def inferBitOpType(self, node): obj = maxType(node.left.vhd, node.right.vhd) node.vhd = node.left.vhd = node.right.vhd = obj node.vhdOri = copy(node.vhd) def inferBinOpType(self, node): left, op, right = node.left, node.op, node.right if isinstance(left.vhd, (vhd_boolean, vhd_std_logic)): left.vhd = vhd_unsigned(1) if isinstance(right.vhd, (vhd_boolean, vhd_std_logic)): right.vhd = vhd_unsigned(1) if isinstance(right.vhd, vhd_unsigned): if maybeNegative(left.vhd) or \ (isinstance(op, ast.Sub) and not hasattr(node, 'isRhs')): right.vhd = vhd_signed(right.vhd.size + 1) if isinstance(left.vhd, vhd_unsigned): if maybeNegative(right.vhd) or \ (isinstance(op, ast.Sub) and not hasattr(node, 'isRhs')): left.vhd = vhd_signed(left.vhd.size + 1) l, r = left.vhd, right.vhd ls, rs = l.size, r.size if isinstance(r, vhd_vector) and isinstance(l, vhd_vector): if isinstance(op, (ast.Add, ast.Sub)): s = max(ls, rs) elif isinstance(op, ast.Mod): s = rs elif isinstance(op, ast.FloorDiv): s = ls elif isinstance(op, ast.Mult): s = ls + rs else: raise AssertionError("unexpected op %s" % op) elif isinstance(l, vhd_vector) and isinstance(r, vhd_int): if isinstance(op, (ast.Add, ast.Sub, ast.Mod, ast.FloorDiv)): s = ls elif isinstance(op, ast.Mult): s = 2 * ls else: raise AssertionError("unexpected op %s" % op) elif isinstance(l, vhd_int) and isinstance(r, vhd_vector): if isinstance(op, (ast.Add, ast.Sub, ast.Mod, ast.FloorDiv)): s = rs elif isinstance(op, ast.Mult): s = 2 * rs else: raise AssertionError("unexpected op %s" % op) if isinstance(l, vhd_int) and isinstance(r, vhd_int): node.vhd = vhd_int() elif isinstance(l, (vhd_signed, vhd_int)) and isinstance(r, (vhd_signed, vhd_int)): node.vhd = vhd_signed(s) elif isinstance(l, (vhd_unsigned, vhd_int)) and isinstance(r, (vhd_unsigned, vhd_int)): node.vhd = vhd_unsigned(s) else: node.vhd = vhd_int() node.vhdOri = copy(node.vhd) def visit_BoolOp(self, node): self.generic_visit(node) for n in node.values: n.vhd = vhd_boolean() node.vhd = vhd_boolean() node.vhdOri = copy(node.vhd) def visit_If(self, node): if node.ignore: return self.generic_visit(node) for test, suite in node.tests: test.vhd = vhd_boolean() def visit_IfExp(self, node): self.generic_visit(node) node.test.vhd = vhd_boolean() def visit_ListComp(self, node): pass # do nothing def visit_Subscript(self, node): if isinstance(node.slice, ast.Slice): self.accessSlice(node) else: self.accessIndex(node) def accessSlice(self, node): self.generic_visit(node) lower = node.value.vhd.size t = type(node.value.vhd) # node.expr.vhd = vhd_unsigned(node.expr.vhd.size) if node.slice.lower: node.slice.lower.vhd = vhd_int() lower = self.getVal(node.slice.lower) upper = 0 if node.slice.upper: node.slice.upper.vhd = vhd_int() upper = self.getVal(node.slice.upper) if isinstance(node.ctx, ast.Store): node.vhd = t(lower - upper) else: node.vhd = vhd_unsigned(lower - upper) node.vhdOri = copy(node.vhd) def accessIndex(self, node): self.generic_visit(node) node.vhd = vhd_std_logic() # XXX default node.slice.value.vhd = vhd_int() obj = node.value.obj if isinstance(obj, list): assert len(obj) node.vhd = inferVhdlObj(obj[0]) elif isinstance(obj, _Ram): node.vhd = inferVhdlObj(obj.elObj) elif isinstance(obj, _Rom): node.vhd = vhd_int() elif isinstance(obj, intbv): node.vhd = vhd_std_logic() node.vhdOri = copy(node.vhd) def visit_UnaryOp(self, node): self.visit(node.operand) node.vhd = copy(node.operand.vhd) if isinstance(node.op, ast.Not): # postpone this optimization until initial values are written # if isinstance(node.operand.vhd, vhd_std_logic): # node.vhd = vhd_std_logic() # else: # node.vhd = node.operand.vhd = vhd_boolean() node.vhd = node.operand.vhd = vhd_boolean() elif isinstance(node.op, ast.USub): if isinstance(node.vhd, vhd_unsigned): node.vhd = vhd_signed(node.vhd.size + 1) elif isinstance(node.vhd, vhd_nat): node.vhd = vhd_int() node.vhdOri = copy(node.vhd) def visit_While(self, node): self.generic_visit(node) node.test.vhd = vhd_boolean() def _annotateTypes(genlist): for tree in genlist: if isinstance(tree, _UserVhdlCode): continue v = _AnnotateTypesVisitor(tree) v.visit(tree) myhdl-0.11/myhdl/conversion/_toVHDLPackage.py000066400000000000000000000124061347432460400211510ustar00rootroot00000000000000from __future__ import absolute_import # This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA import myhdl _version = myhdl.__version__.replace('.', '') _shortversion = _version.replace('dev', '') _package = """\ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package pck_myhdl_%(version)s is attribute enum_encoding: string; function stdl (arg: boolean) return std_logic; function stdl (arg: integer) return std_logic; function to_unsigned (arg: boolean; size: natural) return unsigned; function to_signed (arg: boolean; size: natural) return signed; function to_integer(arg: boolean) return integer; function to_integer(arg: std_logic) return integer; function to_unsigned (arg: std_logic; size: natural) return unsigned; function to_signed (arg: std_logic; size: natural) return signed; function bool (arg: std_logic) return boolean; function bool (arg: unsigned) return boolean; function bool (arg: signed) return boolean; function bool (arg: integer) return boolean; function "-" (arg: unsigned) return signed; function tern_op(cond: boolean; if_true: std_logic; if_false: std_logic) return std_logic; function tern_op(cond: boolean; if_true: unsigned; if_false: unsigned) return unsigned; function tern_op(cond: boolean; if_true: signed; if_false: signed) return signed; end pck_myhdl_%(version)s; package body pck_myhdl_%(version)s is function stdl (arg: boolean) return std_logic is begin if arg then return '1'; else return '0'; end if; end function stdl; function stdl (arg: integer) return std_logic is begin if arg /= 0 then return '1'; else return '0'; end if; end function stdl; function to_unsigned (arg: boolean; size: natural) return unsigned is variable res: unsigned(size-1 downto 0) := (others => '0'); begin if arg then res(0):= '1'; end if; return res; end function to_unsigned; function to_signed (arg: boolean; size: natural) return signed is variable res: signed(size-1 downto 0) := (others => '0'); begin if arg then res(0) := '1'; end if; return res; end function to_signed; function to_integer(arg: boolean) return integer is begin if arg then return 1; else return 0; end if; end function to_integer; function to_integer(arg: std_logic) return integer is begin if arg = '1' then return 1; else return 0; end if; end function to_integer; function to_unsigned (arg: std_logic; size: natural) return unsigned is variable res: unsigned(size-1 downto 0) := (others => '0'); begin res(0):= arg; return res; end function to_unsigned; function to_signed (arg: std_logic; size: natural) return signed is variable res: signed(size-1 downto 0) := (others => '0'); begin res(0) := arg; return res; end function to_signed; function bool (arg: std_logic) return boolean is begin return arg = '1'; end function bool; function bool (arg: unsigned) return boolean is begin return arg /= 0; end function bool; function bool (arg: signed) return boolean is begin return arg /= 0; end function bool; function bool (arg: integer) return boolean is begin return arg /= 0; end function bool; function "-" (arg: unsigned) return signed is begin return - signed(resize(arg, arg'length+1)); end function "-"; function tern_op(cond: boolean; if_true: std_logic; if_false: std_logic) return std_logic is begin if cond then return if_true; else return if_false; end if; end function tern_op; function tern_op(cond: boolean; if_true: unsigned; if_false: unsigned) return unsigned is begin if cond then return if_true; else return if_false; end if; end function tern_op; function tern_op(cond: boolean; if_true: signed; if_false: signed) return signed is begin if cond then return if_true; else return if_false; end if; end function tern_op; end pck_myhdl_%(version)s; """ % {'version' : _shortversion} myhdl-0.11/myhdl/conversion/_toVerilog.py000066400000000000000000001453561347432460400205620ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2012 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ myhdl toVerilog conversion module. """ from __future__ import absolute_import from __future__ import print_function import sys import math import os import textwrap import inspect from datetime import datetime import ast import string from types import GeneratorType from myhdl._compat import StringIO import warnings import myhdl from myhdl import * from myhdl._compat import integer_types, class_types, PY2 from myhdl import ToVerilogError, ToVerilogWarning from myhdl._extractHierarchy import (_HierExtr, _isMem, _getMemInfo, _UserVerilogCode, _userCodeMap) from myhdl._instance import _Instantiator from myhdl.conversion._misc import (_error, _kind, _context, _ConversionMixin, _Label, _genUniqueSuffix, _isConstant) from myhdl.conversion._analyze import (_analyzeSigs, _analyzeGens, _analyzeTopFunc, _Ram, _Rom) from myhdl._Signal import _Signal from myhdl._ShadowSignal import _TristateSignal, _TristateDriver from myhdl._block import _Block from myhdl._getHierarchy import _getHierarchy _converting = 0 _profileFunc = None def _checkArgs(arglist): for arg in arglist: if not isinstance(arg, (GeneratorType, _Instantiator, _UserVerilogCode)): raise ToVerilogError(_error.ArgType, arg) def _flatten(*args): arglist = [] for arg in args: if isinstance(arg, _Block): if arg.verilog_code is not None: arglist.append(arg.verilog_code) continue else: arg = arg.subs if id(arg) in _userCodeMap['verilog']: arglist.append(_userCodeMap['verilog'][id(arg)]) elif isinstance(arg, (list, tuple, set)): for item in arg: arglist.extend(_flatten(item)) else: arglist.append(arg) return arglist def _makeDoc(doc, indent=''): if doc is None: return '' doc = inspect.cleandoc(doc) pre = '\n' + indent + '// ' doc = '// ' + doc doc = doc.replace('\n', pre) return doc class _ToVerilogConvertor(object): __slots__ = ("name", "directory", "timescale", "standard", "prefer_blocking_assignments", "radix", "header", "no_myhdl_header", "no_testbench", "portmap", "trace", "initial_values" ) def __init__(self): self.name = None self.directory = None self.timescale = "1ns/10ps" self.standard = '2001' self.prefer_blocking_assignments = True self.radix = '' self.header = '' self.no_myhdl_header = False self.no_testbench = False self.trace = False self.initial_values = False def __call__(self, func, *args, **kwargs): global _converting if _converting: return func(*args, **kwargs) # skip else: # clean start sys.setprofile(None) from myhdl import _traceSignals if _traceSignals._tracing: raise ToVerilogError("Cannot use toVerilog while tracing signals") if not isinstance(func, _Block): if not callable(func): raise ToVerilogError(_error.FirstArgType, "got %s" % type(func)) _converting = 1 if self.name is None: name = func.__name__ if isinstance(func, _Block): name = func.func.__name__ else: name = str(self.name) if isinstance(func, _Block): try: h = _getHierarchy(name, func) finally: _converting = 0 else: warnings.warn( "\n toVerilog(): Deprecated usage: See http://dev.myhdl.org/meps/mep-114.html", stacklevel=2) try: h = _HierExtr(name, func, *args, **kwargs) finally: _converting = 0 if self.directory is None: directory = '' else: directory = self.directory vfilename = name + ".v" vpath = os.path.join(directory, vfilename) vfile = open(vpath, 'w') ### initialize properly ### _genUniqueSuffix.reset() arglist = _flatten(h.top) # print h.top _checkArgs(arglist) genlist = _analyzeGens(arglist, h.absnames) siglist, memlist = _analyzeSigs(h.hierarchy) _annotateTypes(genlist) # infer interface if isinstance(func, _Block): # infer interface after signals have been analyzed func._inferInterface() intf = func else: intf = _analyzeTopFunc(func, *args, **kwargs) intf.name = name doc = _makeDoc(inspect.getdoc(func)) self._convert_filter(h, intf, siglist, memlist, genlist) _writeFileHeader(vfile, vpath, self.timescale) _writeModuleHeader(vfile, intf, doc) _writeSigDecls(vfile, intf, siglist, memlist) _convertGens(genlist, vfile) _writeModuleFooter(vfile) vfile.close() # don't write testbench if module has no ports if len(intf.argnames) > 0 and not toVerilog.no_testbench: tbpath = os.path.join(directory, "tb_" + vfilename) tbfile = open(tbpath, 'w') _writeTestBench(tbfile, intf, self.trace) tbfile.close() # build portmap for cosimulation portmap = {} for n, s in intf.argdict.items(): if hasattr(s, 'driver'): portmap[n] = s.driver() else: portmap[n] = s self.portmap = portmap ### clean-up properly ### self._cleanup(siglist, memlist) return h.top def _cleanup(self, siglist, memlist): # clean up signals for sig in siglist: sig._clear() for mem in memlist: mem.name = None for s in mem.mem: s._clear() # clean up attributes self.name = None self.standard = '2001' self.prefer_blocking_assignments = True self.radix = '' self.header = "" self.no_myhdl_header = False self.no_testbench = False self.trace = False def _convert_filter(self, h, intf, siglist, memlist, genlist): # intended to be a entry point for other uses: # code checking, optimizations, etc pass toVerilog = _ToVerilogConvertor() myhdl_header = """\ // File: $filename // Generated by MyHDL $version // Date: $date """ def _writeFileHeader(f, fn, ts): vars = dict(filename=fn, version=myhdl.__version__, date=datetime.today().ctime() ) if not toVerilog.no_myhdl_header: print(string.Template(myhdl_header).substitute(vars), file=f) if toVerilog.header: print(string.Template(toVerilog.header).substitute(vars), file=f) print(file=f) print("`timescale %s" % ts, file=f) print(file=f) def _writeModuleHeader(f, intf, doc): print("module %s (" % intf.name, file=f) b = StringIO() for portname in intf.argnames: print(" %s," % portname, file=b) print(b.getvalue()[:-2], file=f) b.close() print(");", file=f) print(doc, file=f) print(file=f) for portname in intf.argnames: s = intf.argdict[portname] if s._name is None: raise ToVerilogError(_error.ShadowingSignal, portname) if s._inList: raise ToVerilogError(_error.PortInList, portname) # make sure signal name is equal to its port name s._name = portname r = _getRangeString(s) p = _getSignString(s) if s._driven: if s._read: if not isinstance(s, _TristateSignal): warnings.warn("%s: %s" % (_error.OutputPortRead, portname), category=ToVerilogWarning ) if isinstance(s, _TristateSignal): print("inout %s%s%s;" % (p, r, portname), file=f) else: print("output %s%s%s;" % (p, r, portname), file=f) if s._driven == 'reg': print("reg %s%s%s;" % (p, r, portname), file=f) else: print("wire %s%s%s;" % (p, r, portname), file=f) else: if not s._read: warnings.warn("%s: %s" % (_error.UnusedPort, portname), category=ToVerilogWarning ) print("input %s%s%s;" % (p, r, portname), file=f) print(file=f) def _writeSigDecls(f, intf, siglist, memlist): constwires = [] for s in siglist: if not s._used: continue if s._name in intf.argnames: continue r = _getRangeString(s) p = _getSignString(s) if s._driven: if not s._read and not isinstance(s, _TristateDriver): warnings.warn("%s: %s" % (_error.UnreadSignal, s._name), category=ToVerilogWarning ) k = 'wire' if s._driven == 'reg': k = 'reg' # the following line implements initial value assignments # don't initial value "wire", inital assignment to a wire # equates to a continuous assignment [reference] if not toVerilog.initial_values or k == 'wire': print("%s %s%s%s;" % (k, p, r, s._name), file=f) else: if isinstance(s._init, myhdl._enum.EnumItemType): print("%s %s%s%s = %s;" % (k, p, r, s._name, s._init._toVerilog()), file=f) else: print("%s %s%s%s = %s;" % (k, p, r, s._name, _intRepr(s._init)), file=f) elif s._read: # the original exception # raise ToVerilogError(_error.UndrivenSignal, s._name) # changed to a warning and a continuous assignment to a wire warnings.warn("%s: %s" % (_error.UndrivenSignal, s._name), category=ToVerilogWarning ) constwires.append(s) print("wire %s%s;" % (r, s._name), file=f) # print(file=f) for m in memlist: if not m._used: continue # infer attributes for the case of named signals in a list for i, s in enumerate(m.mem): if not m._driven and s._driven: m._driven = s._driven if not m._read and s._read: m._read = s._read if not m._driven and not m._read: continue r = _getRangeString(m.elObj) p = _getSignString(m.elObj) k = 'wire' initial_assignments = None if m._driven: k = m._driven if toVerilog.initial_values and not k == 'wire': if all([each._init == m.mem[0]._init for each in m.mem]): initialize_block_name = ('INITIALIZE_' + m.name).upper() _initial_assignments = ( ''' initial begin: %s integer i; for(i=0; i<%d; i=i+1) begin %s[i] = %s; end end ''' % (initialize_block_name, len(m.mem), m.name, _intRepr(m.mem[0]._init))) initial_assignments = ( textwrap.dedent(_initial_assignments)) else: val_assignments = '\n'.join( [' %s[%d] <= %s;' % (m.name, n, _intRepr(each._init)) for n, each in enumerate(m.mem)]) initial_assignments = ( 'initial begin\n' + val_assignments + '\nend') print("%s %s%s%s [0:%s-1];" % (k, p, r, m.name, m.depth), file=f) if initial_assignments is not None: print(initial_assignments, file=f) print(file=f) for s in constwires: if s._type in (bool, intbv): c = int(s.val) else: raise ToVerilogError("Unexpected type for constant signal", s._name) c_len = s._nrbits c_str = "%s" % c print("assign %s = %s'd%s;" % (s._name, c_len, c_str), file=f) # print(file=f) # shadow signal assignments for s in siglist: if hasattr(s, 'toVerilog') and s._driven: print(s.toVerilog(), file=f) print(file=f) def _writeModuleFooter(f): print("endmodule", file=f) def _writeTestBench(f, intf, trace=False): print("module tb_%s;" % intf.name, file=f) print(file=f) fr = StringIO() to = StringIO() pm = StringIO() for portname in intf.argnames: s = intf.argdict[portname] r = _getRangeString(s) if s._driven: print("wire %s%s;" % (r, portname), file=f) print(" %s," % portname, file=to) else: print("reg %s%s;" % (r, portname), file=f) print(" %s," % portname, file=fr) print(" %s," % portname, file=pm) print(file=f) print("initial begin", file=f) if trace: print(' $dumpfile("%s.vcd");' % intf.name, file=f) print(' $dumpvars(0, dut);', file=f) if fr.getvalue(): print(" $from_myhdl(", file=f) print(fr.getvalue()[:-2], file=f) print(" );", file=f) if to.getvalue(): print(" $to_myhdl(", file=f) print(to.getvalue()[:-2], file=f) print(" );", file=f) print("end", file=f) print(file=f) print("%s dut(" % intf.name, file=f) print(pm.getvalue()[:-2], file=f) print(");", file=f) print(file=f) print("endmodule", file=f) def _getRangeString(s): if s._type is bool: return '' elif s._nrbits is not None: nrbits = s._nrbits return "[%s:0] " % (nrbits - 1) else: raise AssertionError def _getSignString(s): if s._min is not None and s._min < 0: return "signed " else: return '' def _intRepr(n, radix=''): # write size for large integers (beyond 32 bits signed) # with some safety margin # XXX signed indication 's' ??? p = abs(n) size = '' num = str(p).rstrip('L') if radix == "hex" or p >= 2**30: radix = "'h" num = hex(p)[2:].rstrip('L') if p >= 2**30: size = int(math.ceil(math.log(p+1,2))) + 1 # sign bit! # if not radix: # radix = "'d" r = "%s%s%s" % (size, radix, num) if n < 0: # add brackets and sign on negative numbers r = "(-%s)" % r return r def _convertGens(genlist, vfile): blockBuf = StringIO() funcBuf = StringIO() for tree in genlist: if isinstance(tree, _UserVerilogCode): blockBuf.write(str(tree)) continue if tree.kind == _kind.ALWAYS: Visitor = _ConvertAlwaysVisitor elif tree.kind == _kind.INITIAL: Visitor = _ConvertInitialVisitor elif tree.kind == _kind.SIMPLE_ALWAYS_COMB: Visitor = _ConvertSimpleAlwaysCombVisitor elif tree.kind == _kind.ALWAYS_DECO: Visitor = _ConvertAlwaysDecoVisitor elif tree.kind == _kind.ALWAYS_SEQ: Visitor = _ConvertAlwaysSeqVisitor else: # ALWAYS_COMB Visitor = _ConvertAlwaysCombVisitor v = Visitor(tree, blockBuf, funcBuf) v.visit(tree) vfile.write(funcBuf.getvalue()) funcBuf.close() vfile.write(blockBuf.getvalue()) blockBuf.close() opmap = { ast.Add: '+', ast.Sub: '-', ast.Mult: '*', ast.Div: '/', ast.Mod: '%', ast.Pow: '**', ast.LShift: '<<', ast.RShift: '>>>', ast.BitOr: '|', ast.BitAnd: '&', ast.BitXor: '^', ast.FloorDiv: '/', ast.Invert: '~', ast.Not: '!', ast.UAdd: '+', ast.USub: '-', ast.Eq: '==', ast.Gt: '>', ast.GtE: '>=', ast.Lt: '<', ast.LtE: '<=', ast.NotEq: '!=', ast.And: '&&', ast.Or: '||', } nameconstant_map = { True: "1'b1", False: "1'b0", None: "'bz" } class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin): def __init__(self, tree, buf): self.tree = tree self.buf = buf self.returnLabel = tree.name self.ind = '' self.isSigAss = False self.okSigAss = True self.labelStack = [] self.context = _context.UNKNOWN def raiseError(self, node, kind, msg=""): lineno = self.getLineNo(node) info = "in file %s, line %s:\n " % \ (self.tree.sourcefile, self.tree.lineoffset + lineno) raise ToVerilogError(kind, msg, info) def write(self, arg): self.buf.write("%s" % arg) def writeline(self, nr=1): for i in range(nr): self.buf.write("\n%s" % self.ind) def writeDoc(self, node): assert hasattr(node, 'doc') doc = _makeDoc(node.doc, self.ind) self.write(doc) self.writeline() def indent(self): self.ind += ' ' * 4 def dedent(self): self.ind = self.ind[:-4] def IntRepr(self, n, radix=''): return _intRepr(n, radix) def writeDeclaration(self, obj, name, dir): if dir: dir = dir + ' ' if type(obj) is bool: self.write("%s%s" % (dir, name)) elif isinstance(obj, int): if dir == "input ": self.write("input %s;" % name) self.writeline() self.write("integer %s" % name) elif isinstance(obj, _Ram): self.write("reg [%s-1:0] %s [0:%s-1]" % (obj.elObj._nrbits, name, obj.depth)) elif hasattr(obj, '_nrbits'): s = "" if isinstance(obj, (intbv, _Signal)): if obj._min is not None and obj._min < 0: s = "signed " self.write("%s%s[%s-1:0] %s" % (dir, s, obj._nrbits, name)) else: raise AssertionError("var %s has unexpected type %s" % (name, type(obj))) # initialize regs # if dir == 'reg ' and not isinstance(obj, _Ram): # disable for cver if False: if isinstance(obj, EnumItemType): inival = obj._toVerilog() else: inival = int(obj) self.write(" = %s;" % inival) else: self.write(";") def writeDeclarations(self): for name, obj in self.tree.vardict.items(): self.writeline() self.writeDeclaration(obj, name, "reg") def writeAlwaysHeader(self): assert self.tree.senslist senslist = self.tree.senslist self.write("always ") self.writeSensitivityList(senslist) self.write(" begin: %s" % self.tree.name) self.indent() def writeSensitivityList(self, senslist): sep = ', ' if toVerilog.standard == '1995': sep = ' or ' self.write("@(") for e in senslist[:-1]: self.write(e._toVerilog()) self.write(sep) self.write(senslist[-1]._toVerilog()) self.write(")") def visit_BinOp(self, node): if isinstance(node.op, ast.Mod) and self.context == _context.PRINT: self.visit(node.left) self.write(", ") self.visit(node.right) else: if isinstance(node.op, ast.RShift): # Additional cast to signed of the full expression # this is apparently required by cver - not sure if it # is actually required by standard Verilog. # It shouldn't hurt however. if node.signed: self.write("$signed") self.context = None if node.signed: self.context = _context.SIGNED self.write("(") self.visit(node.left) self.write(" %s " % opmap[type(node.op)]) self.visit(node.right) self.write(")") self.context = None def checkOpWithNegIntbv(self, node, op): if op in ("+", "-", "*", "~", "&&", "||", "!"): return if isinstance(node, ast.Name): o = node.obj if isinstance(o, (_Signal, intbv)) and o.min is not None and o.min < 0: self.raiseError(node, _error.NotSupported, "negative intbv with operator %s" % op) def visit_BoolOp(self, node): self.write("(") self.visit(node.values[0]) for n in node.values[1:]: self.write(" %s " % opmap[type(node.op)]) self.visit(n) self.write(")") def visit_UnaryOp(self, node): self.write("(%s" % opmap[type(node.op)]) self.visit(node.operand) self.write(")") def visit_Attribute(self, node): if isinstance(node.ctx, ast.Store): self.setAttr(node) else: self.getAttr(node) def setAttr(self, node): assert node.attr == 'next' self.isSigAss = self.okSigAss self.visit(node.value) def getAttr(self, node): if isinstance(node.value, ast.Subscript): self.setAttr(node) return assert isinstance(node.value, ast.Name), node.value n = node.value.id if n in self.tree.symdict: obj = self.tree.symdict[n] elif n in self.tree.vardict: obj = self.tree.vardict[n] else: raise AssertionError("object not found") if isinstance(obj, _Signal): if node.attr == 'next': self.isSigAss = self.okSigAss self.visit(node.value) elif node.attr in ('posedge', 'negedge'): self.write(node.attr) self.write(' ') self.visit(node.value) elif node.attr == 'val': self.visit(node.value) if isinstance(obj, (_Signal, intbv)): if node.attr in ('min', 'max'): self.write("%s" % node.obj) if isinstance(obj, EnumType): assert hasattr(obj, node.attr) e = getattr(obj, node.attr) self.write(e._toVerilog()) def visit_Assert(self, node): self.write("if (") self.visit(node.test) self.write(" !== 1) begin") self.indent() self.writeline() self.write('$display("*** AssertionError ***");') # self.writeline() # self.write('$finish;') self.dedent() self.writeline() self.write("end") def visit_Assign(self, node): # shortcut for expansion of ROM in case statement if isinstance(node.value, ast.Subscript) and \ isinstance(node.value.slice, ast.Index) and\ isinstance(node.value.value.obj, _Rom): rom = node.value.value.obj.rom # self.write("// synthesis parallel_case full_case") # self.writeline() self.write("case (") self.visit(node.value.slice) self.write(")") self.indent() for i, n in enumerate(rom): self.writeline() if i == len(rom) - 1: self.write("default: ") else: self.write("%s: " % i) self.visit(node.targets[0]) if self.isSigAss: self.write(' <= ') self.isSigAss = False else: self.write(' = ') s = self.IntRepr(n) self.write("%s;" % s) self.dedent() self.writeline() self.write("endcase") return elif isinstance(node.value, ast.ListComp): # skip list comprehension assigns for now return # default behavior self.visit(node.targets[0]) if self.isSigAss: self.write(' <= ') self.isSigAss = False else: self.write(' = ') self.visit(node.value) self.write(';') def visit_AugAssign(self, node, *args): # XXX apparently no signed context required for augmented assigns self.visit(node.target) self.write(" = ") self.visit(node.target) self.write(" %s " % opmap[type(node.op)]) self.visit(node.value) self.write(";") def visit_Break(self, node,): self.write("disable %s;" % self.labelStack[-2]) def visit_Call(self, node): self.context = None fn = node.func # assert isinstance(fn, astNode.Name) f = self.getObj(fn) if f is print: self.visit_Print(node) return opening, closing = '(', ')' if f is bool: self.write("(") self.visit(node.args[0]) self.write(" != 0)") # self.write(" ? 1'b1 : 1'b0)") return elif f is len: val = self.getVal(node) self.require(node, val is not None, "cannot calculate len") self.write(repr(val)) return elif f is now: self.write("$time") return elif f is ord: opening, closing = '', '' node.args[0].s = str(ord(node.args[0].s)) elif f in integer_types: opening, closing = '', '' # convert number argument to integer if isinstance(node.args[0], ast.Num): node.args[0].n = int(node.args[0].n) elif f in (intbv, modbv): self.visit(node.args[0]) return elif f == intbv.signed: # note equality comparison # comes from a getattr opening, closing = '', '' if not fn.value.signed: opening, closing = "$signed(", ")" self.write(opening) self.visit(fn.value) self.write(closing) elif (type(f) in class_types) and issubclass(f, Exception): self.write(f.__name__) elif f in (posedge, negedge): opening, closing = ' ', '' self.write(f.__name__) elif f is concat: opening, closing = '{', '}' elif f is delay: self.visit(node.args[0]) return elif hasattr(node, 'tree'): self.write(node.tree.name) else: self.write(f.__name__) if node.args: self.write(opening) self.visit(node.args[0]) for arg in node.args[1:]: self.write(", ") self.visit(arg) self.write(closing) if hasattr(node, 'tree'): if node.tree.kind == _kind.TASK: Visitor = _ConvertTaskVisitor else: Visitor = _ConvertFunctionVisitor v = Visitor(node.tree, self.funcBuf) v.visit(node.tree) def visit_Compare(self, node): self.context = None if node.signed: self.context = _context.SIGNED self.write("(") self.visit(node.left) self.write(" %s " % opmap[type(node.ops[0])]) self.visit(node.comparators[0]) self.write(")") self.context = None def visit_Num(self, node): if self.context == _context.PRINT: self.write('"%s"' % node.n) else: self.write(self.IntRepr(node.n)) def visit_Str(self, node): s = node.s if self.context == _context.PRINT: self.write('"%s"' % s) elif len(s) == s.count('0') + s.count('1'): self.write("%s'b%s" % (len(s), s)) else: self.write(s) def visit_Continue(self, node): self.write("disable %s;" % self.labelStack[-1]) def visit_Expr(self, node): expr = node.value # docstrings on unofficial places if isinstance(expr, ast.Str): doc = _makeDoc(expr.s, self.ind) self.write(doc) return # skip extra semicolons if isinstance(expr, ast.Num): return self.visit(expr) # ugly hack to detect an orphan "task" call if isinstance(expr, ast.Call) and hasattr(expr, 'tree'): self.write(';') def visit_IfExp(self, node): self.visit(node.test) self.write(' ? ') self.visit(node.body) self.write(' : ') self.visit(node.orelse) def visit_For(self, node): self.labelStack.append(node.breakLabel) self.labelStack.append(node.loopLabel) var = node.target.id cf = node.iter f = self.getObj(cf.func) args = cf.args assert len(args) <= 3 if f is range: cmp = '<' op = '+' oneoff = '' if len(args) == 1: start, stop, step = None, args[0], None elif len(args) == 2: start, stop, step = args[0], args[1], None else: start, stop, step = args else: # downrange cmp = '>=' op = '-' oneoff = '-1' if len(args) == 1: start, stop, step = args[0], None, None elif len(args) == 2: start, stop, step = args[0], args[1], None else: start, stop, step = args if node.breakLabel.isActive: self.write("begin: %s" % node.breakLabel) self.writeline() self.write("for (%s=" % var) if start is None: self.write("0") else: self.visit(start) self.write("%s; %s%s" % (oneoff, var, cmp)) if stop is None: self.write("0") else: self.visit(stop) self.write("; %s=%s%s" % (var, var, op)) if step is None: self.write("1") else: v = self.getVal(step) self.require(node, v >= 0, "step should be >= 0") self.visit(step) self.write(") begin") if node.loopLabel.isActive: self.write(": %s" % node.loopLabel) self.indent() self.visit_stmt(node.body) self.dedent() self.writeline() self.write("end") if node.breakLabel.isActive: self.writeline() self.write("end") self.labelStack.pop() self.labelStack.pop() def visit_FunctionDef(self, node): raise AssertionError("To be implemented in subclass") def visit_If(self, node): if node.ignore: return if node.isCase: self.mapToCase(node) else: self.mapToIf(node) def mapToCase(self, node, *args): var = node.caseVar # self.write("// synthesis parallel_case") # if node.isFullCase: # self.write(" full_case") # self.writeline() caseType = "case" if isinstance(node.caseItem, EnumItemType): if node.caseItem._type._encoding in ('one_hot', 'one_cold'): caseType = "casez" self.write("%s (" % caseType) self.visit(var) self.write(")") self.indent() for test, suite in node.tests: self.writeline() item = test.case[1] if isinstance(item, EnumItemType): self.write(item._toVerilog(dontcare=True)) else: self.write(self.IntRepr(item, radix='hex')) self.write(": begin") self.indent() self.visit_stmt(suite) self.dedent() self.writeline() self.write("end") if node.else_: self.writeline() self.write("default: begin") self.indent() self.visit_stmt(node.else_) self.dedent() self.writeline() self.write("end") self.dedent() self.writeline() self.write("endcase") def mapToIf(self, node, *args): first = True for test, suite in node.tests: if first: ifstring = "if (" first = False else: ifstring = "else if (" self.writeline() self.write(ifstring) self.visit(test) self.write(") begin") self.indent() self.visit_stmt(suite) self.dedent() self.writeline() self.write("end") if node.else_: self.writeline() self.write("else begin") self.indent() self.visit_stmt(node.else_) self.dedent() self.writeline() self.write("end") def visitKeyword(self, node, *args): self.visit(node.expr) def visit_Module(self, node, *args): for stmt in node.body: self.visit(stmt) def visit_ListComp(self, node): pass # do nothing def visit_NameConstant(self, node): self.write(nameconstant_map[node.obj]) def visit_Name(self, node): if isinstance(node.ctx, ast.Store): self.setName(node) else: self.getName(node) def setName(self, node): self.write(node.id) def getName(self, node): n = node.id if PY2 and n in ('True', 'False', 'None'): self.visit_NameConstant(node) return addSignBit = False isMixedExpr = (not node.signed) and (self.context == _context.SIGNED) if n in self.tree.vardict: addSignBit = isMixedExpr s = n elif n in self.tree.argnames: assert n in self.tree.symdict addSignBit = isMixedExpr s = n elif n in self.tree.symdict: obj = self.tree.symdict[n] if isinstance(obj, bool): s = "1'b%s" % int(obj) elif isinstance(obj, integer_types): s = self.IntRepr(obj) elif isinstance(obj, _Signal): addSignBit = isMixedExpr s = str(obj) elif _isMem(obj): m = _getMemInfo(obj) assert m.name s = m.name elif isinstance(obj, EnumItemType): s = obj._toVerilog() elif (type(obj) in class_types) and issubclass(obj, Exception): s = n else: self.raiseError(node, _error.UnsupportedType, "%s, %s" % (n, type(obj))) else: raise AssertionError("name ref: %s" % n) if addSignBit: self.write("$signed({1'b0, ") self.write(s) if addSignBit: self.write("})") def visit_Pass(self, node): self.write("// pass") def visit_Print(self, node): argnr = 0 for s in node.format: if isinstance(s, str): self.write('$write("%s");' % s) else: a = node.args[argnr] argnr += 1 obj = a.obj if s.conv is int or isinstance(obj, int): fs = "%0d" else: fs = "%h" self.context = _context.PRINT if isinstance(obj, str): self.write('$write(') self.visit(a) self.write(');') elif (s.conv is str) and isinstance(obj, bool): self.write('if (') self.visit(a) self.write(')') self.writeline() self.write(' $write("True");') self.writeline() self.write('else') self.writeline() self.write(' $write("False");') elif isinstance(obj, EnumItemType): tipe = obj._type self.write('case (') self.visit(a) self.write(')') self.indent() for n in tipe._names: self.writeline() item = getattr(tipe, n) self.write("'b%s: " % item._val) self.write('$write("%s");' % n) self.dedent() self.writeline() self.write("endcase") else: print (type(obj), type(a)) self.write('$write("%s", ' % fs) self.visit(a) self.write(');') self.context = _context.UNKNOWN self.writeline() self.write('$write("\\n");') def visit_Raise(self, node): self.write("$finish;") def visit_Return(self, node): self.write("disable %s;" % self.returnLabel) def visit_Subscript(self, node): if isinstance(node.slice, ast.Slice): self.accessSlice(node) else: self.accessIndex(node) def accessSlice(self, node): if isinstance(node.value, ast.Call) and \ node.value.func.obj in (intbv, modbv) and \ _isConstant(node.value.args[0], self.tree.symdict): c = self.getVal(node) self.write("%s'h" % c._nrbits) self.write("%x" % c._val) return addSignBit = isinstance(node.ctx, ast.Load) and (self.context == _context.SIGNED) if addSignBit: self.write("$signed({1'b0, ") self.context = None self.visit(node.value) lower, upper = node.slice.lower, node.slice.upper # special shortcut case for [:] slice if lower is None and upper is None: return self.write("[") if lower is None: self.write("%s" % node.obj._nrbits) else: self.visit(lower) self.write("-1:") if upper is None: self.write("0") else: self.visit(upper) self.write("]") if addSignBit: self.write("})") def accessIndex(self, node): addSignBit = isinstance(node.ctx, ast.Load) and \ (not node.signed) and \ (self.context == _context.SIGNED) if addSignBit: self.write("$signed({1'b0, ") self.context = None self.visit(node.value) self.write("[") # assert len(node.subs) == 1 self.visit(node.slice.value) self.write("]") if addSignBit: self.write("})") def visit_stmt(self, body): for stmt in body: self.writeline() self.visit(stmt) # ugly hack to detect an orphan "task" call if isinstance(stmt, ast.Call) and hasattr(stmt, 'tree'): self.write(';') def visit_Tuple(self, node): assert self.context != None sep = ", " tpl = node.elts self.visit(tpl[0]) for elt in tpl[1:]: self.write(sep) self.visit(elt) def visit_While(self, node): self.labelStack.append(node.breakLabel) self.labelStack.append(node.loopLabel) if node.breakLabel.isActive: self.write("begin: %s" % node.breakLabel) self.writeline() self.write("while (") self.visit(node.test) self.write(") begin") if node.loopLabel.isActive: self.write(": %s" % node.loopLabel) self.indent() self.visit_stmt(node.body) self.dedent() self.writeline() self.write("end") if node.breakLabel.isActive: self.writeline() self.write("end") self.labelStack.pop() self.labelStack.pop() def visit_Yield(self, node): yieldObj = self.getObj(node.value) assert node.senslist senslist = node.senslist if isinstance(yieldObj, delay): self.write("# ") self.context = _context.YIELD self.visit(node.value) self.context = _context.UNKNOWN self.write(";") else: self.writeSensitivityList(senslist) self.write(";") class _ConvertAlwaysVisitor(_ConvertVisitor): def __init__(self, tree, blockBuf, funcBuf): _ConvertVisitor.__init__(self, tree, blockBuf) self.funcBuf = funcBuf def visit_FunctionDef(self, node): self.writeDoc(node) w = node.body[-1] y = w.body[0] if isinstance(y, ast.Expr): y = y.value assert isinstance(y, ast.Yield) self.writeAlwaysHeader() self.writeDeclarations() # assert isinstance(w.body, astNode.Stmt) for stmt in w.body[1:]: self.writeline() self.visit(stmt) self.dedent() self.writeline() self.write("end") self.writeline(2) class _ConvertInitialVisitor(_ConvertVisitor): def __init__(self, tree, blockBuf, funcBuf): _ConvertVisitor.__init__(self, tree, blockBuf) self.funcBuf = funcBuf def visit_FunctionDef(self, node): self.writeDoc(node) self.write("initial begin: %s" % self.tree.name) self.indent() self.writeDeclarations() self.visit_stmt(node.body) self.dedent() self.writeline() self.write("end") self.writeline(2) class _ConvertAlwaysCombVisitor(_ConvertVisitor): def __init__(self, tree, blockBuf, funcBuf): _ConvertVisitor.__init__(self, tree, blockBuf) if toVerilog.prefer_blocking_assignments: self.okSigAss = False self.funcBuf = funcBuf def visit_FunctionDef(self, node): self.writeDoc(node) self.writeAlwaysHeader() self.writeDeclarations() self.visit_stmt(node.body) self.dedent() self.writeline() self.write("end") self.writeline(2) class _ConvertSimpleAlwaysCombVisitor(_ConvertVisitor): def __init__(self, tree, blockBuf, funcBuf): _ConvertVisitor.__init__(self, tree, blockBuf) self.funcBuf = funcBuf def visit_Attribute(self, node): if isinstance(node.ctx, ast.Store): self.write("assign ") self.visit(node.value) else: self.getAttr(node) def visit_FunctionDef(self, node): self.writeDoc(node) self.visit_stmt(node.body) self.writeline(2) class _ConvertAlwaysDecoVisitor(_ConvertVisitor): def __init__(self, tree, blockBuf, funcBuf): _ConvertVisitor.__init__(self, tree, blockBuf) self.funcBuf = funcBuf def visit_FunctionDef(self, node): self.writeDoc(node) self.writeAlwaysHeader() self.writeDeclarations() self.visit_stmt(node.body) self.dedent() self.writeline() self.write("end") self.writeline(2) def _convertInitVal(reg, init): if isinstance(reg, _Signal): tipe = reg._type else: assert isinstance(reg, intbv) tipe = intbv if tipe is bool: v = '1' if init else '0' elif tipe is intbv: init = int(init) # int representation v = "%s" % init if init is not None else "'bz" else: assert isinstance(init, EnumItemType) v = init._toVerilog() return v class _ConvertAlwaysSeqVisitor(_ConvertVisitor): def __init__(self, tree, blockBuf, funcBuf): _ConvertVisitor.__init__(self, tree, blockBuf) self.funcBuf = funcBuf def visit_FunctionDef(self, node): self.writeDoc(node) self.writeAlwaysHeader() self.writeDeclarations() reset = self.tree.reset sigregs = self.tree.sigregs varregs = self.tree.varregs if reset is not None: self.writeline() self.write("if (%s == %s) begin" % (reset, int(reset.active))) self.indent() for s in sigregs: self.writeline() self.write("%s <= %s;" % (s, _convertInitVal(s, s._init))) for v in varregs: n, reg, init = v self.writeline() self.write("%s = %s;" % (n, _convertInitVal(reg, init))) self.dedent() self.writeline() self.write("end") self.writeline() self.write("else begin") self.indent() self.visit_stmt(node.body) self.dedent() if reset is not None: self.writeline() self.write("end") self.dedent() self.writeline() self.write("end") self.writeline(2) class _ConvertFunctionVisitor(_ConvertVisitor): def __init__(self, tree, funcBuf): _ConvertVisitor.__init__(self, tree, funcBuf) self.returnObj = tree.returnObj self.returnLabel = _Label("RETURN") def writeOutputDeclaration(self): obj = self.tree.returnObj self.writeDeclaration(obj, self.tree.name, dir='') def writeInputDeclarations(self): for name in self.tree.argnames: obj = self.tree.symdict[name] self.writeline() self.writeDeclaration(obj, name, "input") def visit_FunctionDef(self, node): self.write("function ") self.writeOutputDeclaration() self.indent() self.writeInputDeclarations() self.writeDeclarations() self.dedent() self.writeline() self.write("begin: %s" % self.returnLabel) self.indent() self.visit_stmt(node.body) self.dedent() self.writeline() self.write("end") self.writeline() self.write("endfunction") self.writeline(2) def visit_Return(self, node): self.write("%s = " % self.tree.name) self.visit(node.value) self.write(";") self.writeline() self.write("disable %s;" % self.returnLabel) class _ConvertTaskVisitor(_ConvertVisitor): def __init__(self, tree, funcBuf): _ConvertVisitor.__init__(self, tree, funcBuf) self.returnLabel = _Label("RETURN") def writeInterfaceDeclarations(self): for name in self.tree.argnames: obj = self.tree.symdict[name] output = name in self.tree.outputs input = name in self.tree.inputs inout = input and output dir = (inout and "inout") or (output and "output") or "input" self.writeline() self.writeDeclaration(obj, name, dir) def visit_FunctionDef(self, node): self.write("task %s;" % self.tree.name) self.indent() self.writeInterfaceDeclarations() self.writeDeclarations() self.dedent() self.writeline() self.write("begin: %s" % self.returnLabel) self.indent() self.visit_stmt(node.body) self.dedent() self.writeline() self.write("end") self.writeline() self.write("endtask") self.writeline(2) def _maybeNegative(obj): if hasattr(obj, '_min') and (obj._min is not None) and (obj._min < 0): return True if isinstance(obj, integer_types) and obj < 0: return True return False class _AnnotateTypesVisitor(ast.NodeVisitor, _ConversionMixin): def __init__(self, tree): self.tree = tree def visit_FunctionDef(self, node): # don't visit arguments and decorators for stmt in node.body: self.visit(stmt) def visit_BinOp(self, node): self.visit(node.left) self.visit(node.right) node.signed = node.left.signed or node.right.signed # special treatement of subtraction unless in a top-level rhs if isinstance(node.op, ast.Sub) and not hasattr(node, 'isRhs'): node.signed = True def visit_BoolOp(self, node): for n in node.values: self.visit(n) node.signed = False def visit_UnaryOp(self, node): self.visit(node.operand) node.signed = node.operand.signed if isinstance(node.op, ast.USub): node.obj = int(-1) if isinstance(node.operand, ast.Num): node.signed = True def visit_Attribute(self, node): if isinstance(node.ctx, ast.Store): self.setAttr(node) else: self.getAttr(node) def setAttr(self, node): self.visit(node.value) def getAttr(self, node): node.signed = False self.visit(node.value) def visit_Call(self, node): self.generic_visit(node) f = self.getObj(node.func) node.signed = False # suprize: identity comparison on unbound methods doesn't work in python 2.5?? if f == intbv.signed: node.signed = True elif hasattr(node, 'tree'): v = _AnnotateTypesVisitor(node.tree) v.visit(node.tree) node.signed = _maybeNegative(node.tree.returnObj) def visit_Compare(self, node): node.signed = False # for n in ast.iter_child_nodes(node): for n in [node.left] + node.comparators: self.visit(n) if n.signed: node.signed = True def visit_If(self, node): if node.ignore: return self.generic_visit(node) def visit_Num(self, node): node.signed = False def visit_Str(self, node): node.signed = False def visit_Name(self, node): if isinstance(node.ctx, ast.Store): self.setName(node) else: self.getName(node) def setName(self, node): pass def getName(self, node): node.signed = _maybeNegative(node.obj) def visit_Subscript(self, node): if isinstance(node.slice, ast.Slice): self.accessSlice(node) else: self.accessIndex(node) def accessSlice(self, node): node.signed = False self.generic_visit(node) def accessIndex(self, node): node.signed = _maybeNegative(node.obj) self.generic_visit(node) def visit_Tuple(self, node): node.signed = False self.generic_visit(node) def _annotateTypes(genlist): for tree in genlist: if isinstance(tree, _UserVerilogCode): continue v = _AnnotateTypesVisitor(tree) v.visit(tree) myhdl-0.11/myhdl/conversion/_verify.py000066400000000000000000000172041347432460400201020ustar00rootroot00000000000000from __future__ import absolute_import from __future__ import print_function import sys import os import tempfile import subprocess import difflib import warnings from collections import namedtuple import myhdl from myhdl._Simulation import Simulation from myhdl.conversion._toVHDL import toVHDL from myhdl.conversion._toVerilog import toVerilog from myhdl._block import _Block _version = myhdl.__version__.replace('.', '') # strip 'dev' for version _version = _version.replace('dev', '') _simulators = {} sim = namedtuple('sim', 'name hdl analyze elaborate simulate skiplines skipchars ignore') def registerSimulator(name=None, hdl=None, analyze=None, elaborate=None, simulate=None, skiplines=None, skipchars=None, ignore=None): if not isinstance(name, str) or (name.strip() == ""): raise ValueError("Invalid simulator name") if hdl not in ("VHDL", "Verilog"): raise ValueError("Invalid hdl %s" % hdl) if not isinstance(analyze, str) or (analyze.strip() == ""): raise ValueError("Invalid analyzer command") # elaborate command is optional if elaborate is not None: if not isinstance(elaborate, str) or (elaborate.strip() == ""): raise ValueError("Invalid elaborate command") if not isinstance(simulate, str) or (simulate.strip() == ""): raise ValueError("Invalid simulator command") _simulators[name] = sim(name, hdl, analyze, elaborate, simulate, skiplines, skipchars, ignore) registerSimulator( name="ghdl", hdl="VHDL", analyze="ghdl -a --std=08 --workdir=work pck_myhdl_%(version)s.vhd %(topname)s.vhd", elaborate="ghdl -e --std=08 --workdir=work %(unitname)s", simulate="ghdl -r --workdir=work %(unitname)s" ) registerSimulator( name="nvc", hdl="VHDL", analyze="nvc --work=work_nvc -a pck_myhdl_%(version)s.vhd %(topname)s.vhd", elaborate="nvc --work=work_nvc -e %(topname)s", simulate="nvc --work=work_nvc -r %(topname)s" ) registerSimulator( name="vlog", hdl="Verilog", analyze="vlog -work work_vlog %(topname)s.v", simulate='vsim work_vlog.%(topname)s -quiet -c -do "run -all; quit -f"', skiplines=6, skipchars=2, ignore=("# **", "# //", "# run -all") ) registerSimulator( name="vcom", hdl="VHDL", analyze="vcom -2008 -work work_vcom pck_myhdl_%(version)s.vhd %(topname)s.vhd", simulate='vsim work_vcom.%(topname)s -quiet -c -do "run -all; quit -f"', skiplines=6, skipchars=2, ignore=("# **", "# //", "# Time:", "# run -all") ) registerSimulator( name="iverilog", hdl="Verilog", analyze="iverilog -o %(topname)s.o %(topname)s.v", simulate="vvp %(topname)s.o" ) registerSimulator( name="cver", hdl="Verilog", analyze="cver -c -q %(topname)s.v", simulate="cver -q %(topname)s.v", skiplines=3 ) class _VerificationClass(object): __slots__ = ("simulator", "_analyzeOnly") def __init__(self, analyzeOnly=False): self.simulator = None self._analyzeOnly = analyzeOnly def __call__(self, func, *args, **kwargs): if not self.simulator: raise ValueError("No simulator specified") if self.simulator not in _simulators: raise ValueError("Simulator %s is not registered" % self.simulator) hdlsim = _simulators[self.simulator] hdl = hdlsim.hdl if hdl == 'Verilog' and toVerilog.name is not None: name = toVerilog.name elif hdl == 'VHDL' and toVHDL.name is not None: name = toVHDL.name elif isinstance(func, _Block): name = func.func.__name__ else: warnings.warn( "\n analyze()/verify(): Deprecated usage: See http://dev.myhdl.org/meps/mep-114.html", stacklevel=2) try: name = func.__name__ except: raise TypeError(str(type(func))) vals = {} vals['topname'] = name vals['unitname'] = name.lower() vals['version'] = _version analyze = hdlsim.analyze % vals elaborate = hdlsim.elaborate if elaborate is not None: elaborate = elaborate % vals simulate = hdlsim.simulate % vals skiplines = hdlsim.skiplines skipchars = hdlsim.skipchars ignore = hdlsim.ignore if isinstance(func, _Block): if hdl == "VHDL": inst = func.convert(hdl='VHDL') else: inst = func.convert(hdl='Verilog') else: if hdl == "VHDL": inst = toVHDL(func, *args, **kwargs) else: inst = toVerilog(func, *args, **kwargs) if hdl == "VHDL": if not os.path.exists("work"): os.mkdir("work") if hdlsim.name in ('vlog', 'vcom'): if not os.path.exists("work_vsim"): try: subprocess.call("vlib work_vlog", shell=True) subprocess.call("vlib work_vcom", shell=True) subprocess.call("vmap work_vlog work_vlog", shell=True) subprocess.call("vmap work_vcom work_vcom", shell=True) except: pass # print(analyze) ret = subprocess.call(analyze, shell=True) if ret != 0: print("Analysis failed", file=sys.stderr) return ret if self._analyzeOnly: print("Analysis succeeded", file=sys.stderr) return 0 f = tempfile.TemporaryFile(mode='w+t') sys.stdout = f sim = Simulation(inst) sim.run() sys.stdout = sys.__stdout__ f.flush() f.seek(0) flines = f.readlines() f.close() if not flines: print("No MyHDL simulation output - nothing to verify", file=sys.stderr) return 1 if elaborate is not None: # print(elaborate) ret = subprocess.call(elaborate, shell=True) if ret != 0: print("Elaboration failed", file=sys.stderr) return ret g = tempfile.TemporaryFile(mode='w+t') # print(simulate) ret = subprocess.call(simulate, stdout=g, shell=True) # if ret != 0: # print "Simulation run failed" # return g.flush() g.seek(0) glines = g.readlines()[skiplines:] if ignore: for p in ignore: glines = [line for line in glines if not line.startswith(p)] # limit diff window to the size of the MyHDL output # this is a hack to remove an eventual simulator postamble if len(glines) > len(flines): glines = glines[:len(flines)] glines = [line[skipchars:] for line in glines] flinesNorm = [line.lower() for line in flines] glinesNorm = [line.lower() for line in glines] g = difflib.unified_diff(flinesNorm, glinesNorm, fromfile='MyHDL', tofile=hdlsim.name) MyHDLLog = "MyHDL.log" HDLLog = hdlsim.name + ".log" try: os.remove(MyHDLLog) os.remove(HDLLog) except: pass s = "".join(g) f = open(MyHDLLog, 'w') g = open(HDLLog, 'w') d = open('diff.log', 'w') f.writelines(flines) g.writelines(glines) d.write(s) f.close() g.close() d.close() if not s: print("Conversion verification succeeded", file=sys.stderr) else: print("Conversion verification failed", file=sys.stderr) # print >> sys.stderr, s , return 1 return 0 verify = _VerificationClass(analyzeOnly=False) analyze = _VerificationClass(analyzeOnly=True) myhdl-0.11/myhdl/debug.py000066400000000000000000000010471347432460400153360ustar00rootroot00000000000000from __future__ import absolute_import from __future__ import print_function import platform from . import __version__ def print_versions(): versions = [ ("myhdl", __version__), ("Python Version", platform.python_version()), ("Python Implementation", platform.python_implementation()), ("OS", platform.platform()), ] print() print("INSTALLED VERSIONS") print("------------------") for k, v in versions: print("{}: {}".format(k, v)) if __name__ == "__main__": print_versions() myhdl-0.11/myhdl/experiments/000077500000000000000000000000001347432460400162375ustar00rootroot00000000000000myhdl-0.11/myhdl/experiments/_simrunc.c000066400000000000000000000147531347432460400202340ustar00rootroot00000000000000#include "Python.h" #include #include static PyObject *_simulator; static PyObject *_siglist; static PyObject *_futureEvents; static PyObject *_WaiterList; static PyObject *_Waiter; static PyObject *Signal; static PyObject *delay; static PyObject *StopSimulation; static PyObject *SuspendSimulation; PyObject * run(PyObject *self, PyObject *args, PyObject *kwargs) { PyObject *sim; long int duration = 0; int quiet = 0; static char *argnames[] = {"sim", "duration", "quiet", NULL}; PyObject *waiters, *waiter, *clauses, *clone, *clause; PyObject *type, *newtO, *event, *id; PyObject *actives, *values; long long int maxTime = -1; long long int t = 0; long long int ct = 0; long long int newt = 0; int nr; int len, i, j; PyObject *tO, *extl, *s, *hr, *hgl, *nt, *c, *wl, *ev, *ctO, *r, *it; if (!PyArg_ParseTupleAndKeywords(args, kwargs, "O|li", argnames, &sim, &duration, &quiet)) { return NULL; } waiters = PyObject_GetAttrString(sim, "_waiters"); tO = PyObject_GetAttrString(_simulator, "_time"); t = PyLong_AsLongLong(tO); Py_DECREF(tO); actives = PyDict_New(); for (;;) { len = PyList_Size(_siglist); for (i = 0; i < len; i++) { s = PyList_GetItem(_siglist, i); extl = PyObject_CallMethod(s, "_update", NULL); for (j = 0; j < PyList_Size(extl) ; j++) { PyList_Append(waiters, PyList_GetItem(extl, j)); } Py_DECREF(extl); } PySequence_DelSlice(_siglist, 0, len); while (PyList_Size(waiters) > 0) { waiter = PyList_GetItem(waiters, 0); Py_INCREF(waiter); PySequence_DelItem(waiters, 0); hr = PyObject_GetAttrString(waiter, "hasRun"); if (PyObject_IsTrue(hr)) { Py_DECREF(waiter); Py_DECREF(hr); continue; } Py_DECREF(hr); hgl = PyObject_CallMethod(waiter, "hasGreenLight", NULL); if (!PyObject_IsTrue(hgl)) { Py_DECREF(waiter); Py_DECREF(hgl); continue; } Py_DECREF(hgl); nt = PyObject_CallMethod(waiter, "next", NULL); if (nt == NULL) { if (PyErr_ExceptionMatches(PyExc_StopIteration)) { c = PyObject_GetAttrString(waiter, "caller"); if (c != Py_None) { PyList_Append(waiters, c); } Py_DECREF(waiter); Py_DECREF(c); continue; } else { Py_DECREF(waiter); goto exception; } } Py_DECREF(waiter); clauses = PyTuple_GetItem(nt, 0); clone = PyTuple_GetItem(nt, 1); nr = PyTuple_Size(clauses); for (i = 0; i < nr; i++) { clause = PySequence_GetItem(clauses, i); type = PyObject_Type(clause); if (type == _WaiterList) { // PyObject_Print(clause, stdout, 0); PyList_Append(clause, clone); if (nr > 1) { id = PyLong_FromVoidPtr(clause); PyDict_SetItem(actives, id, clause); Py_DECREF(id); } } else if (PyObject_IsInstance(clause, Signal)) { wl = PyObject_GetAttrString(clause, "_eventWaiters"); PyList_Append(wl, clone); if (nr > 1) { id = PyLong_FromVoidPtr(wl); PyDict_SetItem(actives, id, wl); Py_DECREF(id); } Py_DECREF(wl); } else if (type == delay) { ctO = PyObject_GetAttrString(clause, "_time"); ct = PyLong_AsLongLong(ctO); Py_DECREF(ctO); ev = PyTuple_New(2); newtO = PyLong_FromLongLong(t + ct); PyTuple_SetItem(ev, 0, newtO); Py_INCREF(clone); PyTuple_SetItem(ev, 1, clone); PyList_Append(_futureEvents, ev); Py_DECREF(ev); } else { assert(0); } // Py_DECREF(clone); Py_DECREF(type); Py_DECREF(clause); } Py_DECREF(nt); } if (PyList_Size(_siglist) > 0) { continue; } if (PyDict_Size(actives) > 0) { values = PyDict_Values(actives); for (i = 0; i < PyList_Size(values); i++) { wl = PyList_GetItem(values, i); r = PyObject_CallMethod(wl, "purge", NULL); Py_DECREF(r); } Py_DECREF(values); PyDict_Clear(actives); } // PyObject_Print(actives, stdout, 0); if (PyList_Size(_futureEvents) > 0) { r = PyObject_CallMethod(_futureEvents, "sort", NULL); Py_DECREF(r); newtO = PyTuple_GetItem(PyList_GetItem(_futureEvents, 0), 0); PyObject_SetAttrString(_simulator, "_time", newtO); t = PyLong_AsLongLong(newtO); while (PyList_Size(_futureEvents) > 0) { ev = PyList_GetItem(_futureEvents, 0); newtO = PyTuple_GetItem(ev, 0); newt = PyLong_AsLongLong(newtO); event = PyTuple_GetItem(ev, 1); if (newt == t) { type = PyObject_Type(event); if (type == _Waiter) { PyList_Append(waiters, event); } else { extl = PyObject_CallMethod(event, "apply", NULL); for (j = 0; j < PyList_Size(extl); j++) { PyList_Append(waiters, PyList_GetItem(extl, j)); } Py_DECREF(extl); } Py_DECREF(type); PySequence_DelItem(_futureEvents, 0); } else { break; } } } else { PyErr_SetString(StopSimulation, "No more events"); printf("No more events\n"); goto exception; } } assert(0); /* should not get here */ exception: if (PyErr_ExceptionMatches(StopSimulation)) { printf("Stop simulation reached \n"); PyErr_Clear(); r = PyObject_CallMethod(sim, "_finalize", NULL); Py_DECREF(r); Py_DECREF(actives); Py_DECREF(waiters); return PyInt_FromLong(0); } Py_DECREF(actives); Py_DECREF(waiters); return Py_BuildValue(""); } static PyMethodDef simruncmethods[] = { {"run", (PyCFunction)run, METH_VARARGS | METH_KEYWORDS}, {NULL, NULL, 0, NULL} }; void initsimrunc(void) { PyObject *SignalModule; PyObject *delayModule; PyObject *_WaiterModule; PyObject *utilModule; Py_InitModule("simrunc", simruncmethods); _simulator = PyImport_ImportModule("_simulator"); _siglist = PyObject_GetAttrString(_simulator, "_siglist"); _futureEvents = PyObject_GetAttrString(_simulator, "_futureEvents"); SignalModule = PyImport_ImportModule("Signal"); Signal = PyObject_GetAttrString(SignalModule, "Signal"); _WaiterList = PyObject_GetAttrString(SignalModule, "_WaiterList"); delayModule = PyImport_ImportModule("delay"); delay = PyObject_GetAttrString(delayModule, "delay"); _WaiterModule = PyImport_ImportModule("_Waiter"); _Waiter = PyObject_GetAttrString(_WaiterModule, "_Waiter"); utilModule = PyImport_ImportModule("util"); StopSimulation = PyObject_GetAttrString(utilModule, "StopSimulation"); SuspendSimulation = PyObject_GetAttrString(utilModule, "SuspendSimulation"); Py_DECREF(SignalModule); Py_DECREF(delayModule); Py_DECREF(_WaiterModule); Py_DECREF(utilModule); } myhdl-0.11/myhdl/spec/000077500000000000000000000000001347432460400146265ustar00rootroot00000000000000myhdl-0.11/myhdl/spec/Signal_spec.txt000066400000000000000000000134561347432460400176270ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA Specification for the Signal class ---------------------------------- In the following, attribute and method names starting with an underscore are intended to be "private". In other words, they are not part of the public interface of the Signal class. The private attributes and methods are for internal use or for use by a simulator object that interacts with Signal objects. In the following, a "sig" denotes an object of the Signal class. * A sig should have a read-only attribute 'val' that represents its current value. * The Signal constructor should have one mandatory parameter 'val' to initialize its current value and future value. * The Signal contractor should have an optional parameter 'delay' to specify an initial delay value for the signal. The default value is None, meaning no delay. * A sig should have a 'delay' attribute that represents its current delay. It is acceptable that this attribute is only present if the sig has been constructed with a non-zero delay. * A sig should have a 'next' attribute that represents its future value. The 'next' attribute provides both write and read access. (Read access is required to support mutable values.) * In principle, any object could be assigned to sig.next; however, for meaningful modeling its type should be "compatible" with the type of the current value. Python's ultra-dynamic nature is not useful in this case, and could in fact be the source of hard-to-trace bugs. Therefore, there should be a check that the type of the object assigned to sig.next is compatible with the type of the initial value. "Compatible" means that the type should either be a subtype of the initial type, or that the types have been designed to work transparently together by other means. In particular, int (and long) and intbv are not subtypes of each other, but they are designed to work together. * A sig has 'min' and a 'max' read-only attributes that default to None. They are possibly set to numeric values according to the initial sig constructor object. In particular, the attributes are inherited from an intbv object, and they are set for a bool object. These attributes are used to implement or complement the checks on the object assigned to sig.next. * A sig should have a number of private list attributes that can hold generators that are waiting for a particular change on the sig's value: - '_eventWaiters': generators waiting for a value change - '_posedgeWaiters': generators waiting for a change from false to true - '_negedgeWaiters': generators waiting for a change from true to false * A sig should have read-only attributes 'posedge' and 'negedge' to represent a posedge and negedge value change in yield clauses of generators. To represent an event (a value change), the sig itself is used in a yield clause. * A sig should have an '_update()' method that performs the actions required to make the future value current. When 'delay' is 0, it assigns the future value to the current value. In addition, it returns a list of waiters for which a particular value change is satisfied, and removes them from the internal lists that held them. When 'delay' is nonzero, it schedules the application of the future value in the _simulator._futureEvents list and returns an empty list. * A sig should have an '_apply(next, ...)' method that handles the application of a scheduled 'next' value. It implements inertial delay by only applying the 'next' value if there has been no change to the sig's 'next' attribute since the 'next' value was scheduled. If so, it assigns the 'next' value to the current value. In addition, it returns a list of waiters for which a particular value change is satisfied, and removes them from the internal lists that held them. * When the 'next' attribute is accessed to modify a mutable value, the change should be made to an object that is distinct from the current value object. * Whenever the 'next' attribute is accessed, a sig should be entered in the '_simulator._siglist'. A simulator can thus know which sig's need updating. * A sig should have no other public attributes than those described above. * In practice, Signals will often have numbers as their underlying values. As a matter of convenience, the special Python object methods for numeric and bitwise operators are supported on Signal objects, by delegation to the corresponding method on the underlying current value. As an exception, augmented assignment methods are not supported, as these would provide write access to the current value. The current value of a Signal object should always behave as a read-only attribute. * In addition, the special methods for logical interpretation and comparision are supported by delegation to the current value. * In addition, index access and slice access is supported by delegation to the current value. However, for the same reasons as above, index and slice assignment are not supported. myhdl-0.11/myhdl/spec/Simulation_spec.txt000066400000000000000000000102271347432460400205270ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA Specification for the Simulation class -------------------------------------- * The Simulation object constructor has an arbitrary number of arguments with each argument being a generator, or a nested sequence of generators. A nested sequence means a sequence whose elements may themselves be sequences, and so on, down to an arbitrary level. * A Simulation object has a 'run(duration=None)' method. If a duration is specified, it should be a positive integer that indicates that the simulation should run for that amount of time. If not, it should run until there are no further events. Consecutive runs for a number of durations t1, t2, ... tn should give exactly the same behavior as a single run for duration t1+t2+...+ tn. The 'run' method returns None if there are no further events, and 1 otherwise. When the simulation has run for the specified duration, the SuspendSimulation exception is raised. * A Simulation run interacts with a list of signals that need updating and a list of generators that need to run. At Simulation construction time, the signal list is empty and the generator list contains all generators that were passed as constructor parameters. * In a given timestep, all signals in the signal list are first updated. This may cause the need to run some additional generators. Then, the generators are run and the return values from their yield clauses are inspected. This may cause the need to update signals in the same timestep. As long as the signal list is not empty, the procedure is repeated. Once it is empty, the Simulation moves to the next timestep where some action may be required. Again the action may be a signal update, or a generator run. All actions from the same time step are first collected before any generator is run in the new timestep. In the new timestep, the update/run procedure is repeated as described before. * The yield clauses recognized by as Simulation may contain a number of different objects. The general format is: yield arg1, arg2, .... argn Each argument defines a trigger. When any trigger is satisfied, the generator is run again. However, any subsequent triggers that were originate from the same invocation of the yield clause, have no effect. In other words: the first trigger wins, and the others are neglected. (Note however, that another trigger could still have an effect in another invocation of that same yield clause.) Each trigger argument may be one of the following: - a delay(t) object. This specifies that the generator should run at time now() + t - a signal object. This specifies that the generator should run when the signal value changes - a posedge(signal) or negedge(signal) object. This specifies that the generator should run at the rising or falling edge on a signal. - a join object. This specifies that the generator should run when all arguments of the join have triggered. A join argument can be any of the trigger argument described int this list. - a generator. In this case, the generator is dynamically added to the list of generators to be run in the timestep. When the generator completes, the original generator is triggered. * When there are no further events, the Simulation.run method raises the StopSimulation exception. myhdl-0.11/myhdl/spec/intbv_spec.txt000066400000000000000000000100301347432460400175150ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA Specification for the intbv class --------------------------------- Hardware description languages need bit-oriented data types. The standard Python int and long types have most of the desired features, including bitwise operations and an underlying 2-s complement representation, except one: mutability. Hardware designers want to be able to set bits and slices of a bit vector. The intbv class provides such a mutable number. It is designed to work transparently as a number, with other intbv's and with ints and longs. In addition, it has indexing and slicing operations and a few other bit-oriented features. As it is mutable, it cannot be a subtype of int; so it is a separate type. * an intbv() constructor takes and int, long, intbv, or bit string as its first argument, called 'val'. The bit string works as in int(bit string, 2). * an intbv() constructor takes optional 'min' and 'max' parameters. The meaning is that the intbv's value should be in the range range(min, max). Note that the Python conventions for range bounds are followed. The 'min' and 'max' parameters default to None and are available as read-only attributes. * an intbv supports the same the numeric, comparison, bitwise and conversion operators as ints and longs. It supports mixed-type operations with ints and longs. Mixed-type numeric operations return an int or a long. Mixed-type bitwise operations return an intbv. * an intbv supports indexing operations, both to get and set a bit. * an intbv supports slicing operations, both to get and set a slice. As is customary in hardware design, and unlike Python sequences, the rightmost bit has index 0, and a slice is taken by a downward range; in other words, in [i:j], i has to be larger than j. People may object to this as it departs from standard Python sequence conventions. However, an intbv should not be seen as a sequence, but as a number in the first place: the indexing/slicing operations are borrowed to get/set individual bits in a number. It seems natural that the index of a bit should equal the power of the corresponding 2**i term in a representation of the number's value as a sum of powers of 2. This is also the standard hardware design way to look at it. * As in standard Python, ranges are half-open; however, the not-included index is the left index. Provided the downward range concept is accepted, this seems like the Pythonic way to do it. Just like with sequences, this convention avoids one-off issues in a lot of practical cases. Both indices can be left unspecified. The right index defaults to zero. The left index default means "all" bits. * When setting slices, there should be check on the input value to verify that all significant bits can be accepted by the slice. * When getting as slice, the result is a new intbv object. Its value is always positive or zero, regardless of the sign of the original intbv object. When the left index is specified, the new intbv has a defined bitwidth w=i-j. The min and max attributes of the new intbv are implicitly set to 0 and 2**w respectively. * intbv supports the iterator protocol to iterate on its bits; again, this requires a known length. myhdl-0.11/myhdl/test/000077500000000000000000000000001347432460400146535ustar00rootroot00000000000000myhdl-0.11/myhdl/test/README.txt000066400000000000000000000020311347432460400163450ustar00rootroot00000000000000Welcome to the MyHDL test directory tree. This directory contains a number of subdirectories, that contain tests for various aspects of MyHDL. * core - the MyHDL modeling core tests * conversion - tests related to conversion from MyHDL to Verilog/VHDL * bugs - tests for specific bugs that were reported and solved All test directories contain a Makefile for easy testing. However, there may be additional dependencies and requirements. Some tests require a working installation for the Verilog simulators cver or Icarus, or the VHDL simulator GHDL. In addition, some tests require a that co-simulation is properly set up. Moreover, some test dirs use the py.test unit testing framework instead of the standard Python unittest library. Please consult the README.txt file in each subdirectory for instructions. Note however that the core tests can be run with stock Python and stock MyHDL without any additional requirements. Whenever you make a code change, these are the first tests that you want to run to make sure nothing is broken. myhdl-0.11/myhdl/test/bugs/000077500000000000000000000000001347432460400156135ustar00rootroot00000000000000myhdl-0.11/myhdl/test/bugs/Makefile000066400000000000000000000003771347432460400172620ustar00rootroot00000000000000all: ghdl iverilog vlog: py.test --sim vlog vcom: py.test --sim vcom ghdl: py.test --sim ghdl iverilog: py.test --sim iverilog cver: py.test --sim cver clean: - rm *.o *.out *.v *.vhd *.pyc *~ *.vcd* *.log *_ghdl gitclean: git clean -dfx myhdl-0.11/myhdl/test/bugs/README.txt000066400000000000000000000015421347432460400173130ustar00rootroot00000000000000Requirements: * cver, icarus, GHDL or vlog/vcom (default) * py.test See the Makefile - it contains targets per simulator. Naming Tests ------------ The tests in this directory are specific to bugs/issues discovered in a release. The tests are named after the github issue number (e.g. 98, 117, etc.). When adding new bug tests create a github issue, record the github issue number, and then create a test with the issue number. Example of issue and test names: 117: test_issue_117, https://github.com/jandecaluwe/myhdl/issues/117 98: test_issue_98, https://github.com/jandecaluwe/myhdl/issues/98 40: test_issue_40, https://github.com/jandecaluwe/myhdl/issues/40 In many cases there will be large gaps in the issue number because not all issues are reported bugs (many are enhancement requests) and github shares enumeration with pull-requests. myhdl-0.11/myhdl/test/bugs/__init__.py000066400000000000000000000000001347432460400177120ustar00rootroot00000000000000myhdl-0.11/myhdl/test/bugs/test_bug_1740778.py000066400000000000000000000012321347432460400207200ustar00rootroot00000000000000from __future__ import absolute_import import sys import os path = os.path import random from random import randrange random.seed(2) import myhdl from myhdl import * from myhdl.conversion import verify ACTIVE_LOW, INACTIVE_HIGH = bool(0), bool(1) def bug_1740778 (): """ Conversion of min and max attribute. """ s = Signal(intbv(0, min=-13, max=46)) @instance def logic(): v = intbv(0, min=-15, max=45) yield delay(10) print(v.min) print(v.max) print(s.val) print(s.min) print(s.max) return logic def test_bug_1740778 (): assert verify(bug_1740778) == 0 myhdl-0.11/myhdl/test/bugs/test_bug_1835792.py000066400000000000000000000010431347432460400207210ustar00rootroot00000000000000from __future__ import absolute_import import sys import os path = os.path import random from random import randrange random.seed(2) import myhdl from myhdl import * from myhdl.conversion import verify ACTIVE_LOW, INACTIVE_HIGH = bool(0), bool(1) def bug_1835792 (): """ Semicolon conversion """ @instance def logic(): v = intbv(0, min=-15, max=45) yield delay(10) print(v.min); print(v.max); return logic def test_bug_1835792 (): assert verify(bug_1835792) == 0 myhdl-0.11/myhdl/test/bugs/test_bug_1835797.py000066400000000000000000000011121347432460400207230ustar00rootroot00000000000000from __future__ import absolute_import import sys import os path = os.path import random from random import randrange random.seed(2) import myhdl from myhdl import * from myhdl.conversion import verify ACTIVE_LOW, INACTIVE_HIGH = bool(0), bool(1) def bug_1835797(): """ Docstring in the middle. """ @instance def logic(): v = intbv(0, min=-15, max=45) """Wrongly placed docstring""" yield delay(10) print(v.min) print(v.max) return logic def test_bug_1835797(): assert verify(bug_1835797) == 0 myhdl-0.11/myhdl/test/bugs/test_bug_1837003.py000066400000000000000000000013021347432460400207020ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from myhdl import ConversionError from myhdl.conversion._misc import _error def SubFunction(xout,yout,xin,yin): @always_comb def logic(): x = 4 y = 2 xout.next = xin yout.next = yin return instances() def Function(xout,yout,x,y): return SubFunction(xout,yout,x,y) x = Signal(bool(0)) y = Signal(bool(0)) xout = Signal(bool(0)) yout = Signal(bool(0)) xin = Signal(bool(0)) yin = Signal(bool(0)) def test_bug_1837003(): try: toVerilog(SubFunction,xout,yout,x,y) except ConversionError as e: assert e.kind == _error.ShadowingVar else: assert False myhdl-0.11/myhdl/test/bugs/test_bug_28.py000066400000000000000000000005361347432460400203160ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * def bug_28(dout, channel): @always_comb def comb(): dout.next = 0x8030 + (channel << 10) return comb dout = Signal(intbv(0)[16:0]) channel = Signal(intbv(0)[4:0]) def test_bug_28(): try: toVHDL(bug_28, dout, channel) except: raise myhdl-0.11/myhdl/test/bugs/test_bug_3529686.py000066400000000000000000000011071347432460400207260ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * def bug_3529686(clr, clk, run, ack, serialout): @always(clk.posedge, clr.posedge) def fsm(): if (clr == 0): serialout.next = 0 else: if (ack == 0): serialout.next = 0 elif (run == 1): serialout.next = 1 return fsm clr, clk, run, ack, serialout = [Signal(bool()) for i in range(5)] def test_bug_3529686(): try: toVHDL(bug_3529686, clr, clk, run, ack, serialout) except: assert False myhdl-0.11/myhdl/test/bugs/test_bug_3577799.py000066400000000000000000000014501347432460400207370ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from myhdl.conversion import analyze def bug_3577799 ( clk, reset_clk, wr_data, wr, rd_data ): @instance def seq(): count = 0 while True: yield clk.posedge if reset_clk: count = 0 else: if wr: if count < depth: rd_data.next = wr_data count = count + 1 return seq depth = 8 clk = Signal(bool(0)) reset_clk = Signal(bool(0)) wr_data = Signal(intbv(0)[16:]) wr = Signal(bool(0)) rd_data = Signal(intbv(0)[16:]) def test_bug_3577799(): assert analyze(bug_3577799, clk, reset_clk, wr_data, wr, rd_data) == 0 myhdl-0.11/myhdl/test/bugs/test_bug_39.py000066400000000000000000000014521347432460400203160ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from myhdl.conversion import verify def dut(): rx = Signal(intbv(0, min=-512, max=512)) a = Signal(intbv(0, min=0, max=256)) b = Signal(intbv(0, min=0, max=256)) c = Signal(intbv(0, min=0, max=256)) d = Signal(intbv(0, min=0, max=256)) @always_comb def logic(): rx.next = a + b - (c + d) @instance def check(): a.next = 0 b.next = 0 c.next = 0 d.next = 0 for i in range(100): yield delay(10) print(rx) a.next = (a + 37) % 256 b.next = (b + 67) % 256 c.next = (c + 97) % 256 d.next = (d + 137) % 256 return logic, check def test_bug_39(): assert verify(dut) == 0 myhdl-0.11/myhdl/test/bugs/test_bug_42.py000066400000000000000000000010071347432460400203040ustar00rootroot00000000000000from __future__ import absolute_import #! /usr/bin/env python import myhdl from myhdl import * def module(sigin, sigout): # Using @always(sigin) only warns, but using @always_comp breaks. # The reason is that len(sigout) is interpreted as sigout being used as # an input. #@always(sigin) @always_comb def output(): sigout.next = sigin[len(sigout):] return output sigin = Signal(intbv(0)[2:]) sigout = Signal(intbv(0)[2:]) def test_bug_42(): toVHDL(module, sigin, sigout) myhdl-0.11/myhdl/test/bugs/test_bug_42_2.py000066400000000000000000000010271347432460400205270ustar00rootroot00000000000000from __future__ import absolute_import #! /usr/bin/env python import myhdl from myhdl import * def module(sigin, sigout): # Using @always(sigin) only warns, but using @always_comp breaks. # The reason is that len(sigout) is interpreted as sigout being used as # an input. @always(sigin) def output(): sigout.next = sigin[len(sigout):] return output sigin = Signal(intbv(0)[2:]) sigout = Signal(intbv(0)[2:]) def test_bug_42_2(): toVHDL(module, sigin, sigout) toVHDL(module, sigin, sigout) myhdl-0.11/myhdl/test/bugs/test_bug_43.py000066400000000000000000000010531347432460400203060ustar00rootroot00000000000000from __future__ import absolute_import #! /usr/bin/env python import myhdl from myhdl import * def bug_43(sigin, sigout): @always_comb def output(): # This does not generate correct VHDL code (resize is missing) sigout.next = concat(sigin[0], sigin[2]) # The following does work: tmp = concat(sigin[0], sigin[2]) sigout.next = tmp return output def test_bug_43(): sigin = Signal(intbv(0)[4:]) sigout = Signal(intbv(0)[4:]) assert conversion.analyze(bug_43, sigin, sigout) == 0 myhdl-0.11/myhdl/test/bugs/test_bug_44.py000066400000000000000000000017141347432460400203130ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * WIDTH=4 clk = Signal(bool(0)) x = Signal(modbv(0)[WIDTH:]) y = Signal(modbv(0)[WIDTH:]) z = Signal(modbv(0)[WIDTH:]) @always(delay(5)) def tb_clk_gen(): clk.next = not clk @always(clk.posedge) def inc(): y.next = x + 1 @always(clk.posedge) def dec(): z.next = x - 1 @instance def tb_stimulus(): # My logic happens on posedge, so I'll perform all checks on negedge. yield clk.negedge for x_val in range(-2**WIDTH, 2**WIDTH): #print('x_val={} x.next={}'.format(x_val, x_val % 2**WIDTH)) x.next = x_val % 2**WIDTH yield clk.negedge assert y==(x_val+1)%2**WIDTH, 'y={} but expected {}'.format(y, (x_val+1)%2**WIDTH) assert z==(x_val-1)%2**WIDTH, 'z={} but expected {}'.format(z, (x_val-1)%2**WIDTH) print('OK!') raise StopSimulation tb = instances() def test_bug_44(): print(instances()) Simulation(tb).run() myhdl-0.11/myhdl/test/bugs/test_bug_aj1s.py000066400000000000000000000007461347432460400207260ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from myhdl.conversion import verify def dut(): count = Signal(intbv(0, min=0, max=98)) @instance def seq(): count.next = 50 for i in range(300): yield delay(10) print(count) if count-1 < 0: count.next = 97 else: count.next = count-1 return seq def test_bug_aj1s(): assert verify(dut) == 0 myhdl-0.11/myhdl/test/bugs/test_bug_boolconst.py000066400000000000000000000016421347432460400220660ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * INT_CONDITION_0 = 0 INT_CONDITION_1 = 1 BOOL_CONDITION_0 = False BOOL_CONDITION_1 = True def bug_boolconst(sigin, sigout): @always_comb def output(): sigout.next = 0 if INT_CONDITION_0: sigout.next = sigin if BOOL_CONDITION_0: sigout.next = sigin if not INT_CONDITION_0: sigout.next = sigin if not BOOL_CONDITION_0: sigout.next = sigin if INT_CONDITION_1: sigout.next = sigin if BOOL_CONDITION_1: sigout.next = sigin if not INT_CONDITION_1: sigout.next = sigin if not BOOL_CONDITION_1: sigout.next = sigin return output def test_bug_boolconst(): sigin = Signal(bool()) sigout = Signal(bool()) assert conversion.analyze(bug_boolconst, sigin, sigout) == 0 myhdl-0.11/myhdl/test/bugs/test_bug_boolop.py000066400000000000000000000021271347432460400213550ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * def gray_counter (clk, reset, enable, gray_count): q = Signal(intbv(0)[10:]) no_ones_below = Signal(intbv(0)[10:]) q_msb = Signal(bool(0)) @always_seq(clk.posedge, reset=reset) def seq(): if enable: q.next[0] = not q[0] for i in range(1, 9): q.next[i] = q[i] ^ (q[i-1] and no_ones_below[i-1]) q.next[8] = q[8] ^ (q_msb and no_ones_below[7]) @always(q, no_ones_below) def comb(): q_msb.next = q[8] or q[7] no_ones_below.next[0] = 1 for j in range(1, 10): no_ones_below.next[j] = no_ones_below[j-1] and not q[j-1] gray_count.next[8:] = q[9:1] return comb, seq clk = Signal(bool(0)) reset = ResetSignal(0, active=0, isasync=True) enable = Signal(bool(0)) gray_count = Signal(intbv(0)[8:]) def test_bug_boolop(): try: toVerilog(gray_counter, clk, reset, enable, gray_count) toVHDL(gray_counter, clk, reset, enable, gray_count) except: assert False myhdl-0.11/myhdl/test/bugs/test_bug_enum_toVHDL.py000066400000000000000000000031011347432460400222000ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * # t_state = enum('WAIT_POSEDGE', 'WAIT_NEGEDGE', encoding='one_hot') t_state = enum('WAIT_POSEDGE', 'WAIT_NEGEDGE') def pcie_legacyint_next_state_logic(state_i, next_state_o, next_state_en_o, interrupt_pending_i, interrupt_assert_o): @always_comb def sm_output(): # state machine if state_i == t_state.WAIT_POSEDGE: interrupt_assert_o.next = 0 next_state_en_o .next = interrupt_pending_i next_state_o .next = t_state.WAIT_NEGEDGE elif state_i == t_state.WAIT_NEGEDGE: interrupt_assert_o.next = 1 next_state_en_o .next = not interrupt_pending_i next_state_o .next = t_state.WAIT_POSEDGE else: interrupt_assert_o.next = 0 next_state_en_o .next = 1 next_state_o .next = t_state.WAIT_POSEDGE return sm_output state = Signal(t_state.WAIT_POSEDGE) next_state = Signal(t_state.WAIT_POSEDGE) next_state_en = Signal(bool(0)) # Enable transition to next state interrupt_pending = Signal(bool(0)) interrupt_assert = Signal(bool(0)) def test_bug_enum_toVHDL(): toVHDL(pcie_legacyint_next_state_logic, state, next_state, next_state_en, interrupt_pending, interrupt_assert) if __name__ == '__main__': toVHDL(pcie_legacyint_next_state_logic, state, next_state, next_state_en, interrupt_pending, interrupt_assert) myhdl-0.11/myhdl/test/bugs/test_bug_enum_toVHDL_2.py000066400000000000000000000030511347432460400224250ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * t_state = enum('WAIT_POSEDGE', 'WAIT_NEGEDGE', encoding='one_hot') def pcie_legacyint_next_state_logic(state_i, next_state_o, next_state_en_o, interrupt_pending_i, interrupt_assert_o): @always_comb def sm_output(): # state machine if state_i == t_state.WAIT_POSEDGE: interrupt_assert_o.next = 0 next_state_en_o .next = interrupt_pending_i next_state_o .next = t_state.WAIT_NEGEDGE elif state_i == t_state.WAIT_NEGEDGE: interrupt_assert_o.next = 1 next_state_en_o .next = not interrupt_pending_i next_state_o .next = t_state.WAIT_POSEDGE else: interrupt_assert_o.next = 0 next_state_en_o .next = 1 next_state_o .next = t_state.WAIT_POSEDGE return sm_output state = Signal(t_state.WAIT_POSEDGE) next_state = Signal(t_state.WAIT_POSEDGE) next_state_en = Signal(bool(0)) # Enable transition to next state interrupt_pending = Signal(bool(0)) interrupt_assert = Signal(bool(0)) def test_bug_enum_toVHDL_2(): assert conversion.analyze(pcie_legacyint_next_state_logic, state, next_state, next_state_en, interrupt_pending, interrupt_assert) == 0 if __name__ == '__main__': toVHDL(pcie_legacyint_next_state_logic, state, next_state, next_state_en, interrupt_pending, interrupt_assert) myhdl-0.11/myhdl/test/bugs/test_issue_10.py000066400000000000000000000013021347432460400206500ustar00rootroot00000000000000from __future__ import absolute_import #!/usr/bin/python2.7-32 # -*- coding: utf-8 -*- import myhdl def unsigned(width, value=0, cls=myhdl.intbv): """Create an unsigned signal based on a bitvector with the specified width and initial value. """ return myhdl.Signal(cls(value, 0, 2**width)) def signed(width, value=0, cls=myhdl.intbv): """Create an signed signal based on a bitvector with the specified width and initial value. """ return myhdl.Signal(cls(value, -2**(width-1), 2**(width-1))) a = unsigned(4, 8) b = signed(28, -3) #print "%08X" % myhdl.concat(a, b) #print hex(myhdl.concat(a, b)) def test_issue_10(): assert myhdl.concat(a, b) == 0x8ffffffd myhdl-0.11/myhdl/test/bugs/test_issue_104.py000066400000000000000000000020151347432460400207360ustar00rootroot00000000000000from __future__ import print_function import pytest from myhdl import Simulation, delay, SimulationError, instance, now from myhdl._Simulation import _error from helpers import raises_kind def test(): @instance def tbstim(): yield delay(10) print("{0:<8d} ".format(now())) yield delay(1000) print("{0:<8d} ".format(now())) for _ in range(10): yield delay(1000) return tbstim def issue_104_quit_method(): sim = Simulation(test()) sim.run(1000) sim.run(500) sim.quit() return sim._finished def issue_104_multiple_instance(): sim1 = Simulation(test()) sim1.run(1000) # sim1 is "puased" # try and create a second, third, forth simulation instance for ii in range(4): with raises_kind(SimulationError, _error.MultipleSim): another_sim = Simulation(test()) # generating more sims should have failed sim1.run(1000) sim1.quit() def test_issue_104(): assert issue_104_quit_method() == True issue_104_multiple_instance() myhdl-0.11/myhdl/test/bugs/test_issue_10_2.py000066400000000000000000000017131347432460400210770ustar00rootroot00000000000000#!/usr/bin/python2.7-32 # -*- coding: utf-8 -*- """Failed VHDL code example """ from __future__ import absolute_import import myhdl from myhdl import * from myhdl.conversion import verify def unsigned(width, value=0, cls=intbv): """Create an unsigned signal based on a bitvector with the specified width and initial value. """ return Signal(cls(value, 0, 2**width)) def signed(width, value=0, cls=intbv): """Create an signed signal based on a bitvector with the specified width and initial value. """ return Signal(cls(value, -2**(width-1), 2**(width-1))) flags = unsigned(4) position = signed(28) def Logic(flags, position): conc = unsigned(32) @instance def doit(): flags.next = 4 position.next = 28 yield delay(10) conc.next = concat(flags, position) yield delay(10) print(conc) return doit def test_issue_10_2(): assert verify(Logic, flags, position) == 0 myhdl-0.11/myhdl/test/bugs/test_issue_117.py000066400000000000000000000031271347432460400207470ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from myhdl.conversion import analyze def issue_117(clk, sdi, pdo, sel, const=False): assert isinstance(const, (bool, intbv)) delay_reg = Signal(intbv(0)[8:]) rlen = len(pdo) plen = 1 if isinstance(const, bool) else len(const) @always(clk.posedge) def rtl(): if sel == 0: delay_reg.next = concat(const, delay_reg[rlen-plen-1:1], sdi) elif sel == 1: delay_reg.next = concat(delay_reg[rlen-1:plen+1], const, sdi) elif sel == 2: delay_reg.next = concat(delay_reg[rlen-1:plen+1], sdi, const) pdo.next = delay_reg return rtl def test_issue_117_1(): clk, sdi = [Signal(bool(0)) for _ in range(2)] pdo = Signal(intbv(0)[8:]) sel = Signal(intbv(0, min=0, max=3)) toVHDL.name = toVerilog.name = 'issue_117_1' assert analyze(issue_117, clk, sdi, pdo, sel, const=bool(0))== 0 def test_issue_117_2(): clk, sdi = [Signal(bool(0)) for _ in range(2)] pdo = Signal(intbv(0)[8:]) sel = Signal(intbv(0, min=0, max=3)) toVHDL.name = toVerilog.name = 'issue_117_2' assert analyze(issue_117, clk, sdi, pdo, sel, const=False)== 0 def test_issue_117_3(): clk, sdi = [Signal(bool(0)) for _ in range(2)] pdo = Signal(intbv(0)[8:]) sel = Signal(intbv(0, min=0, max=3)) toVHDL.name = toVerilog.name = 'issue_117_3' assert analyze(issue_117, clk, sdi, pdo, sel, const=intbv(0)[1:])== 0 if __name__ == '__main__': analyze.simulator='vlog' test_issue_117_1() myhdl-0.11/myhdl/test/bugs/test_issue_122.py000066400000000000000000000011741347432460400207430ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from myhdl.conversion import verify def issue_122(dout, i): d = i*10+1 @instance def write(): # dout[i].next = int(i) dout[i].next = i yield delay(d) print(int(dout[i])) if i == 0: return write else: inst = issue_122(dout, i-1) return write, inst def tb_issue_122(): n = 7 dout = [Signal(intbv(0, min=0, max=n+1)) for i in range(n+1)] inst = issue_122(dout, n) return inst def test_issue_122(): assert verify(tb_issue_122) == 0 myhdl-0.11/myhdl/test/bugs/test_issue_127.py000066400000000000000000000071001347432460400207430ustar00rootroot00000000000000''' Bitonic sort ''' # http://www.myhdl.org/examples/bitonic/ from __future__ import absolute_import import unittest from random import randrange from myhdl import Signal, intbv, \ always_comb, instance, \ delay, toVHDL, StopSimulation ASCENDING = True DESCENDING = False # modules def compare(a_1, a_2, z_1, z_2, direction): """ Combinatorial circuit with two input and two output signals. Sorting to 'direction'. """ @always_comb def logic(): ''' Combinatorial logic ''' if direction == (a_1 > a_2): z_1.next = a_2 z_2.next = a_1 else: z_1.next = a_1 z_2.next = a_2 return logic def feedthru(in_a, out_z): """ Equivalent of 'doing nothing'. """ @always_comb def logic(): ''' Combinatorial logic ''' out_z.next = in_a return logic def bitonic_merge(list_a, list_z, direction): """ bitonicMerge: Generates the output from the input list of signals. Recursive. """ len_list = len(list_a) half_len = len_list//2 width = len(list_a[0]) if len_list > 1: tmp = [Signal(intbv(0)[width:]) for _ in range(len_list)] comp = [compare(list_a[i], list_a[i+half_len], tmp[i], tmp[i+half_len], \ direction) for i in range(half_len)] lo_merge = bitonic_merge( tmp[:half_len], list_z[:half_len], direction ) hi_merge = bitonic_merge( tmp[half_len:], list_z[half_len:], direction ) return comp, lo_merge, hi_merge else: feed = feedthru(list_a[0], list_z[0]) return feed def bitonic_sort(list_a, list_z, direction): """ bitonicSort: Produces a bitonic sequence. Recursive. """ len_list = len(list_a) half_len = len_list//2 width = len(list_a[0]) if len_list > 1: tmp = [Signal(intbv(0)[width:]) for _ in range(len_list)] lo_sort = bitonic_sort( list_a[:half_len], tmp[:half_len], ASCENDING ) hi_sort = bitonic_sort( list_a[half_len:], tmp[half_len:], DESCENDING ) merge = bitonic_merge( tmp, list_z, direction ) return lo_sort, hi_sort, merge else: feed = feedthru(list_a[0], list_z[0]) return feed # tests def array8sorter(a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7, z_0, z_1, z_2, z_3, z_4, z_5, z_6, z_7): ''' Sort Array with 8 values ''' list_a = [a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7] list_z = [z_0, z_1, z_2, z_3, z_4, z_5, z_6, z_7] sort = bitonic_sort(list_a, list_z, ASCENDING) return sort class TestBitonicSort(unittest.TestCase): ''' Test class for bitonic sort ''' def test_sort(self): """ Check the functionality of the bitonic sort """ length = 8 width = 4 def test_impl(): ''' test implementation ''' inputs = [ Signal(intbv(0)[width:]) for _ in range(length) ] outputs = [ Signal(intbv(0)[width:]) for _ in range(length) ] z_0, z_1, z_2, z_3, z_4, z_5, z_6, z_7 = outputs a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7 = inputs inst = array8sorter(a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7, z_0, z_1, z_2, z_3, z_4, z_5, z_6, z_7) @instance def check(): ''' testbench input and validation ''' for i in range(100): data = [randrange(2**width) for i in range(length)] for i in range(length): inputs[i].next = data[i] yield delay(10) data.sort() self.assertEqual(data, outputs, 'wrong data') raise StopSimulation return inst, check # convert def test_issue_127(): ''' Convert to VHDL ''' length = 8 width = 4 sigs = [Signal(intbv(0)[width:]) for _ in range(2*length)] toVHDL(array8sorter, *sigs) myhdl-0.11/myhdl/test/bugs/test_issue_13.py000066400000000000000000000021011347432460400206510ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from myhdl.conversion import analyze def issue_13(reset, clk, d, en, q): COSET = 0x55 def calculateHec(header): """ Return hec for an ATM header, represented as an intbv. The hec polynomial is 1 + x + x**2 + x**8. """ hec = intbv(0)[8:] for ii in downrange(len(header)): bit = header[ii] hec[8:] = concat(hec[7:2], bit ^ hec[1] ^ hec[7], bit ^ hec[0] ^ hec[7], bit ^ hec[7] ) return hec ^ COSET @always_seq(clk.posedge, reset=reset) def logic(): if en: q.next = calculateHec(d) return logic def test_issue_13(): reset = ResetSignal(0, active=1, isasync=False) clk = Signal(bool(0)) d = Signal(intbv(0)[32:]) en = Signal(bool(0)) q = Signal(intbv(0)[8:]) # toVHDL.numeric_ports = False assert analyze(issue_13, reset, clk, d, en, q) == 0 myhdl-0.11/myhdl/test/bugs/test_issue_133.py000066400000000000000000000007511347432460400207450ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from myhdl.conversion import verify def issue_133(): z = Signal(False) large_signal = Signal(intbv(123456789123456, min=0, max=2**256)) @instance def check(): z.next = large_signal[10] yield delay(10) print (large_signal[31:]) print (large_signal[62:31]) print (large_signal[93:62]) return check def test_issue_133(): assert verify(issue_133) == 0 myhdl-0.11/myhdl/test/bugs/test_issue_134.py000066400000000000000000000015131347432460400207430ustar00rootroot00000000000000""" When an interface signal gets passed into a function, it can get renamed to the name of the argument. When the function is called multiple times, this causes name collisions """ from __future__ import absolute_import import pytest import myhdl from myhdl import * from myhdl.conversion import analyze class AB: def __init__(self): self.a = Signal(bool(False)) self.b = Signal(bool(False)) def invert(sigin, sigout): @always_comb def foo(): sigout.next = not sigin return foo def issue_134(ab_in, ab_out): """ Instantiate an inverter for each signal """ inverta = invert(ab_in.a, ab_out.a) invertb = invert(ab_in.b, ab_out.b) return inverta, invertb @pytest.mark.xfail def test_issue_134(): """ check for port name collision""" assert analyze(issue_134, AB(), AB()) == 0 myhdl-0.11/myhdl/test/bugs/test_issue_167.py000066400000000000000000000073441347432460400207610ustar00rootroot00000000000000''' Bitonic sort ''' # http://www.myhdl.org/examples/bitonic/ from __future__ import absolute_import import unittest from random import randrange from myhdl import Signal, intbv, \ always_comb, instance, \ delay, block, StopSimulation ASCENDING = True DESCENDING = False # modules @block def compare(a_1, a_2, z_1, z_2, direction): """ Combinatorial circuit with two input and two output signals. Sorting to 'direction'. """ @always_comb def logic(): ''' Combinatorial logic ''' if direction == (a_1 > a_2): z_1.next = a_2 z_2.next = a_1 else: z_1.next = a_1 z_2.next = a_2 return logic @block def feedthru(in_a, out_z): """ Equivalent of 'doing nothing'. """ @always_comb def logic(): ''' Combinatorial logic ''' out_z.next = in_a return logic @block def bitonic_merge(list_a, list_z, direction): """ bitonicMerge: Generates the output from the input list of signals. Recursive. """ len_list = len(list_a) half_len = len_list//2 width = len(list_a[0]) if len_list > 1: tmp = [Signal(intbv(0)[width:]) for _ in range(len_list)] comp = [compare(list_a[i], list_a[i+half_len], tmp[i], tmp[i+half_len], \ direction) for i in range(half_len)] lo_merge = bitonic_merge( tmp[:half_len], list_z[:half_len], direction ) hi_merge = bitonic_merge( tmp[half_len:], list_z[half_len:], direction ) return comp, lo_merge, hi_merge else: feed = feedthru(list_a[0], list_z[0]) return feed @block def bitonic_sort(list_a, list_z, direction): """ bitonicSort: Produces a bitonic sequence. Recursive. """ len_list = len(list_a) half_len = len_list//2 width = len(list_a[0]) if len_list > 1: tmp = [Signal(intbv(0)[width:]) for _ in range(len_list)] lo_sort = bitonic_sort( list_a[:half_len], tmp[:half_len], ASCENDING ) hi_sort = bitonic_sort( list_a[half_len:], tmp[half_len:], DESCENDING ) merge = bitonic_merge( tmp, list_z, direction ) return lo_sort, hi_sort, merge else: feed = feedthru(list_a[0], list_z[0]) return feed # tests @block def array8sorter(a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7, z_0, z_1, z_2, z_3, z_4, z_5, z_6, z_7): ''' Sort Array with 8 values ''' list_a = [a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7] list_z = [z_0, z_1, z_2, z_3, z_4, z_5, z_6, z_7] sort = bitonic_sort(list_a, list_z, ASCENDING) return sort class TestBitonicSort(unittest.TestCase): ''' Test class for bitonic sort ''' def test_sort(self): """ Check the functionality of the bitonic sort """ length = 8 width = 4 @block def test_impl(): ''' test implementation ''' inputs = [ Signal(intbv(0)[width:]) for _ in range(length) ] outputs = [ Signal(intbv(0)[width:]) for _ in range(length) ] z_0, z_1, z_2, z_3, z_4, z_5, z_6, z_7 = outputs a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7 = inputs inst = array8sorter(a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7, z_0, z_1, z_2, z_3, z_4, z_5, z_6, z_7) @instance def check(): ''' testbench input and validation ''' for i in range(100): data = [randrange(2**width) for i in range(length)] for i in range(length): inputs[i].next = data[i] yield delay(10) data.sort() self.assertEqual(data, outputs, 'wrong data') raise StopSimulation return inst, check inst = test_impl() inst.run_sim() # convert def test_issue_167(): ''' Convert to VHDL ''' length = 8 width = 4 sigs = [Signal(intbv(0)[width:]) for _ in range(2*length)] inst = array8sorter( *sigs ) inst.convert( hdl='VHDL' ) if __name__ == '__main__': test_issue_167() myhdl-0.11/myhdl/test/bugs/test_issue_169.py000066400000000000000000000020441347432460400207530ustar00rootroot00000000000000from myhdl import Signal, block, delay, instance import pytest class Test1: def __init__(self): self.clock = Signal(bool(0)) @block def test(self): @instance def func(): i = 0 while i <= 100: yield delay(10) self.clock.next = not self.clock i = i + 1 return func class Test2: def __init__(self): self.clock = Signal(bool(1)) @block def test(self): @instance def func(): i = 0 while i <= 100: yield delay(10) self.clock.next = not self.clock i = i + 1 return func @block def test_bench(): inst1 = Test1() inst2 = Test2() # Two instances are created ins1 = inst1.test() ins2 = inst2.test() return ins1, ins2 @pytest.mark.xfail def test_issue_169(): test_inst = test_bench() assert test_inst.verify_convert() == True if __name__ == '__main__': test_issue_169() myhdl-0.11/myhdl/test/bugs/test_issue_18.py000066400000000000000000000013161347432460400206650ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from myhdl.conversion import analyze def issue_18(dout, din, addr, we, clk, depth=128): """ Ram model """ mem = [Signal(intbv(0)[8:]) for i in range(depth)] @always(clk.posedge) def write(): if we: mem[addr].next = din @always_comb def read(): dout.next = mem[addr] return write, read dout = Signal(intbv(0)[8:]) dout_v = Signal(intbv(0)[8:]) din = Signal(intbv(0)[8:]) addr = Signal(intbv(0)[7:]) we = Signal(bool(0)) clk = Signal(bool(0)) def test_issue_18(): toVHDL.std_logic_ports = True assert analyze(issue_18, dout, din, addr, we, clk) == 0 myhdl-0.11/myhdl/test/bugs/test_issue_185.py000066400000000000000000000010661347432460400207540ustar00rootroot00000000000000from myhdl import * def shift_left(c, a, b): c.next = a << b @block def shifter(reset, clock, opa, opb, result): @always_seq(clock.posedge, reset = reset) def assign(): shift_left(result, opa, opb) return assign def convert(): clock = Signal(bool(0)) reset = ResetSignal(0, active=True, isasync=True) opa = Signal(intbv(0)[4:]) opb = Signal(intbv(0)[4:]) result = Signal(intbv(0)[10:]) inst = shifter(reset, clock, opa, opb, result) inst.convert(hdl='VHDL') if __name__ == '__main__': convert() myhdl-0.11/myhdl/test/bugs/test_issue_40.py000066400000000000000000000013671347432460400206660ustar00rootroot00000000000000from __future__ import absolute_import #! /usr/bin/env python import myhdl from myhdl import * def mpegChannel(clk, rst): s_tx_data_xor_mask_r = Signal(intbv(0)[1 + 31:]) @always_seq(clk.posedge, rst) def fsm_seq(): for i in range(4): if i == 0: s_tx_data_xor_mask_r.next[1 + 7:0] = 0 elif i == 1: s_tx_data_xor_mask_r.next[1 + 15:8] = 1 elif i == 2: s_tx_data_xor_mask_r.next[1 + 23:16] = 2 else: s_tx_data_xor_mask_r.next[1 + 31:24] = 3 return instances() def test_issue_40(): clk = Signal(bool(0)) rst = ResetSignal(0, active=1, isasync=True) assert conversion.analyze(mpegChannel, clk, rst) == 0 myhdl-0.11/myhdl/test/bugs/test_issue_9.py000066400000000000000000000006451347432460400206110ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * def issue_9(): t_State = enum('foo', 'bar') assert (Signal(t_State.foo) == Signal(t_State.bar)) == False assert (Signal(t_State.foo) != Signal(t_State.bar)) == True assert (Signal(t_State.foo) == Signal(t_State.foo)) == True assert (Signal(t_State.foo) != Signal(t_State.foo)) == False def test_issue_9(): issue_9() myhdl-0.11/myhdl/test/bugs/test_issue_98.py000066400000000000000000000023531347432460400206770ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from myhdl.conversion import analyze import pytest def issue_98(sda, scl, sda_i, sda_o, scl_i, scl_o): sda_d, scl_d = sda.driver(), scl.driver() @always_comb def hdl(): sda_i.next = sda sda_d.next = 0 if not sda_o else None scl_i.next = scl scl_d.next = None if not scl_o else 1 return hdl def test_issue_98_1(): sda_i, sda_o, scl_i, scl_o = [Signal(False) for i in range(4)] sda, scl = [TristateSignal(False) for i in range(2)] toVHDL.name = toVerilog.name = 'issue_98_1' assert analyze(issue_98, sda, scl, sda_i, sda_o, scl_i, scl_o) == 0 def test_issue_98_2(): sda_i, sda_o, scl_i, scl_o = [Signal(intbv(0)[2:0]) for i in range(4)] sda, scl = [TristateSignal(intbv(0)[2:0]) for i in range(2)] toVHDL.name = toVerilog.name = 'issue_98_2' assert analyze(issue_98, sda, scl, sda_i, sda_o, scl_i, scl_o) == 0 def test_issue_98_3(): sda_i, sda_o, scl_i, scl_o = [Signal(intbv(0)[1:0]) for i in range(4)] sda, scl = [TristateSignal(intbv(0)[1:0]) for i in range(2)] toVHDL.name = toVerilog.name = 'issue_98_3' assert analyze(issue_98, sda, scl, sda_i, sda_o, scl_i, scl_o) == 0 myhdl-0.11/myhdl/test/conftest.py000066400000000000000000000021051347432460400170500ustar00rootroot00000000000000import sys import py import pytest from myhdl.conversion import analyze, verify from myhdl.conversion._verify import _simulators xfail = pytest.mark.xfail all_sims = list(_simulators) if sys.version_info[0] > 2: collect_ignore = ['conversion/toVerilog/test_not_supported_py2.py'] def pytest_addoption(parser): parser.addoption("--sim", action="store", choices=all_sims, help="HDL Simulator") def pytest_configure(config): sim = config.getoption('sim') if sim is not None: verify.simulator = analyze.simulator = sim def pytest_report_header(config): sim = config.getoption('sim') if config.getoption('sim') is not None: hdr = ['Simulator: {sim}'] if not py.path.local.sysfind(sim): hdr += ['Warning: {sim} not found in PATH'] return '\n'.join(hdr).format(sim=sim) def bug(issue_no, hdl='all'): if hdl == 'all': sims = all_sims else: sims = [k for k, v in _simulators.items() if v.hdl.lower() == hdl] return xfail(verify.simulator in sims, reason='issue '+issue_no) myhdl-0.11/myhdl/test/conversion/000077500000000000000000000000001347432460400170405ustar00rootroot00000000000000myhdl-0.11/myhdl/test/conversion/Makefile000066400000000000000000000005231347432460400205000ustar00rootroot00000000000000.PHONY: all general toVerilog2 toVHDL toVerilog all: general toVerilog2 toVHDL toVerilog general: cd general; py.test --sim ghdl; py.test --sim iverilog toVerilog2: cd toVerilog2; py.test --sim iverilog toVHDL: cd toVHDL; py.test --sim ghdl toVerilog: cd toVerilog; py.test --sim iverilog gitclean: git clean -dfx myhdl-0.11/myhdl/test/conversion/__init__.py000066400000000000000000000000001347432460400211370ustar00rootroot00000000000000myhdl-0.11/myhdl/test/conversion/general/000077500000000000000000000000001347432460400204555ustar00rootroot00000000000000myhdl-0.11/myhdl/test/conversion/general/Makefile000066400000000000000000000003721347432460400221170ustar00rootroot00000000000000all: vlog vcom ghdl: py.test --sim ghdl vlog: py.test --sim vlog vcom: py.test --sim vcom iverilog: py.test --sim iverilog cver: py.test --sim cver clean: - rm *.o *.out *.v *.vhd *.pyc *~ *.vcd* *.log *_ghdl gitclean: git clean -dfx myhdl-0.11/myhdl/test/conversion/general/README.txt000066400000000000000000000003741347432460400221570ustar00rootroot00000000000000Conversion tests that should work with both VHDL and Verilog ------------------------------------------------------------ Requirements: * cver, icarus, GHDL, or vcom/vlog (default) * py.test See the Makefile - it contains targets per simulator. myhdl-0.11/myhdl/test/conversion/general/__init__.py000066400000000000000000000000001347432460400225540ustar00rootroot00000000000000myhdl-0.11/myhdl/test/conversion/general/test_ShadowSignal.py000066400000000000000000000075261347432460400244630ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * @block def bench_SliceSignal(): s = Signal(intbv(0)[8:]) a, b, c = s(7), s(5), s(0) d, e, f, g = s(8,5), s(6,3), s(8,0), s(4,3) N = len(s) @instance def check(): for i in range(N): s.next = i yield delay(10) print(int(a)) print(int(b)) print(int(c)) print(d) print(e) print(f) print(g) return check def test_SliceSignal(): assert conversion.verify(bench_SliceSignal()) == 0 @block def bench_ConcatSignal(): a = Signal(intbv(0)[5:]) b = Signal(bool(0)) c = Signal(intbv(0)[3:]) d = Signal(intbv(0)[4:]) s = ConcatSignal(a, b, c, d) I_max = 2**len(a) J_max = 2**len(b) K_max = 2**len(c) M_max = 2**len(d) @instance def check(): for i in range(I_max): for j in range(J_max): for k in range(K_max): for m in range(M_max): a.next = i b.next = j c.next = k d.next = m yield delay(10) print(s) return check def test_ConcatSignal(): assert conversion.verify(bench_ConcatSignal()) == 0 @block def bench_ConcatSignalWithConsts(): a = Signal(intbv(0)[5:]) b = Signal(bool(0)) c = Signal(intbv(0)[3:]) d = Signal(intbv(0)[4:]) e = Signal(intbv(0)[1:]) c1 = "10" c2 = intbv(3)[3:] c3 = '0' c4 = bool(1) c5 = intbv(42)[8:] # with leading zeroes s = ConcatSignal(c1, a, c2, b, c3, c, c4, d, c5, e) I_max = 2**len(a) J_max = 2**len(b) K_max = 2**len(c) M_max = 2**len(d) @instance def check(): for i in range(I_max): for j in range(J_max): for k in range(K_max): for m in range(M_max): for n in range(2**len(e)): a.next = i b.next = j c.next = k d.next = m e.next = n yield delay(10) print(s) return check def test_ConcatSignalWithConsts(): assert conversion.verify(bench_ConcatSignalWithConsts()) == 0 @block def bench_TristateSignal(): s = TristateSignal(intbv(0)[8:]) a = s.driver() b = s.driver() c = s.driver() @instance def check(): a.next = None b.next = None c.next = None yield delay(10) #print s a.next = 1 yield delay(10) print(s) a.next = None b.next = 122 yield delay(10) print(s) b.next = None c.next = 233 yield delay(10) print(s) c.next = None yield delay(10) #print s return check def test_TristateSignal(): assert conversion.verify(bench_TristateSignal()) == 0 @block def permute(x, a, mapping): p = [a(m) for m in mapping] q = ConcatSignal(*p) @always_comb def assign(): x.next = q return assign @block def bench_permute(conv=False): x = Signal(intbv(0)[3:]) a = Signal(intbv(0)[3:]) mapping = (0, 2, 1) if conv: dut = conv(permute(x, a, mapping)) else: dut = permute(x, a, mapping) @instance def stimulus(): for i in range(2**len(a)): a.next = i yield delay(10) print("%d %d" % (x, a)) assert x[2] == a[0] assert x[1] == a[2] assert x[0] == a[1] raise StopSimulation() return dut, stimulus def test_permute(): assert conversion.verify(bench_permute()) == 0 bench_permute(toVHDL) bench_permute(toVerilog) myhdl-0.11/myhdl/test/conversion/general/test_adapter.py000066400000000000000000000032241347432460400235070ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * @block def adapter(o_err, i_err, o_spec, i_spec): nomatch = Signal(bool(0)) other = Signal(bool(0)) o_err_bits = [] for s in o_spec: if s == 'other': o_err_bits.append(other) elif s == 'nomatch': o_err_bits.append(nomatch) else: bit = i_err(i_spec[s]) o_err_bits.append(bit) o_err_vec = ConcatSignal(*o_err_bits) other_bits = [] for s, i in i_spec.items(): if s in o_spec: continue bit = i_err(i) other_bits.append(bit) other_vec = ConcatSignal(*other_bits) @always_comb def assign(): nomatch.next = 0 other.next = (other_vec != 0) o_err.next = o_err_vec return assign @block def bench_adapter(hdl=None): o_spec = ('c', 'a', 'other', 'nomatch') i_spec = { 'a' : 1, 'b' : 2, 'c' : 0, 'd' : 3, 'e' : 4, 'f' : 5, } o_err = Signal(intbv(0)[4:]) i_err = Signal(intbv(0)[6:]) if hdl: dut = adapter(o_err, i_err, o_spec, i_spec).convert(hdl=hdl) else: dut = adapter(o_err, i_err, o_spec, i_spec) N = 2**len(i_err) @instance def stimulus(): for i in range(N): i_err.next = i yield delay(10) assert o_err[0] == 0 assert o_err[1] == (i_err[2] | i_err[3] | i_err[4] | i_err[5]) assert o_err[2] == i_err[1] assert o_err[3] == i_err[0] print(o_err) return dut, stimulus def test_adapter(): assert bench_adapter().verify_convert() == 0 bench_adapter('Verilog') bench_adapter('VHDL') myhdl-0.11/myhdl/test/conversion/general/test_bin2gray.py000066400000000000000000000030371347432460400236060ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path from myhdl import block, Signal, intbv, delay, instance, always_comb @block def bin2gray2(B, G, width): """ Gray encoder. B -- input intbv signal, binary encoded G -- output intbv signal, gray encoded width -- bit width """ @instance def logic(): Bext = intbv(0)[width+1:] while 1: yield B Bext[:] = B for i in range(width): G.next[i] = Bext[i+1] ^ Bext[i] return logic @block def bin2gray(B, G, width): """ Gray encoder. B -- input intbv signal, binary encoded G -- output intbv signal, gray encoded width -- bit width """ @always_comb def logic(): Bext = intbv(0)[width+1:] Bext[:] = B for i in range(width): G.next[i] = Bext[i+1] ^ Bext[i] return logic @block def bin2grayBench(width, bin2gray): B = Signal(intbv(0)[width:]) G = Signal(intbv(0)[width:]) bin2gray_inst = bin2gray(B, G, width) n = 2**width @instance def stimulus(): for i in range(n): B.next = i yield delay(10) #print "B: " + bin(B, width) + "| G_v: " + bin(G_v, width) #print bin(G, width) #print bin(G_v, width) print("%d" % G) return stimulus, bin2gray_inst def test1(): assert bin2grayBench(width=8, bin2gray=bin2gray).verify_convert() == 0 def test2(): assert bin2grayBench(width=8, bin2gray=bin2gray2).verify_convert() == 0 myhdl-0.11/myhdl/test/conversion/general/test_case.py000066400000000000000000000047031347432460400230050ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * @block def map_case4(z, a): @always_comb def logic(): if a == 0: z.next = 0 elif a == 1: z.next = 1 elif a == 2: z.next = 2 else: z.next = 3 return logic @block def map_case2(z, a): @always_comb def logic(): z.next = 0 if a == 0: z.next = 0 elif a == 1: z.next = 1 return logic @block def map_case3(z, a): @always_comb def logic(): if a == 0: z.next = 0 elif a == 1: z.next = 1 else: z.next = 2 return logic @block def map_case4_full(z, a): @always_comb def logic(): if a == 0: z.next = 0 elif a == 1: z.next = 1 elif a == 2: z.next = 2 elif a == 3: z.next = 3 return logic @block def bench_case(map_case, N): a = Signal(intbv(0)[2:]) z = Signal(intbv(0)[2:]) inst = map_case(z, a) @instance def stimulus(): for i in range(N): a.next = i yield delay(10) print(z) return stimulus, inst @block def bool_bench_case(map_case): a = Signal(False) z = Signal(intbv(0)[2:]) inst = map_case(z, a) @instance def stimulus(): for i in range(2): a.next = i yield delay(10) print(z) return stimulus, inst @block def length1_bench_case(map_case): a = Signal(intbv(0)[1:]) z = Signal(intbv(0)[2:]) inst = map_case(z, a) @instance def stimulus(): for i in range(2): a.next = i yield delay(10) print(z) return stimulus, inst def test_case4(): assert bench_case(map_case4, 4).verify_convert() == 0 def test_case2(): assert bench_case(map_case2, 2).verify_convert() == 0 def test_case3(): assert bench_case(map_case3, 3).verify_convert() == 0 def test_case4_full(): assert bench_case(map_case4_full, 4).verify_convert() == 0 def test_case2_bool(): assert bool_bench_case(map_case3).verify_convert() == 0 def test_case3_bool(): assert bool_bench_case(map_case3).verify_convert() == 0 def test_case2_single_bit(): assert length1_bench_case(map_case3).verify_convert() == 0 def test_case3_single_bit(): assert length1_bench_case(map_case3).verify_convert() == 0 myhdl-0.11/myhdl/test/conversion/general/test_class_defined_signals.py000066400000000000000000000112001347432460400263630ustar00rootroot00000000000000from myhdl import * class HDLClass(object): @block def model(self, clock, input_interface, output_interface): internal_in = Signal(False) internal_out = Signal(False) @always_comb def assignments(): internal_in.next = input_interface output_interface.next = internal_out @always(clock.posedge) def do_something(): print('something') internal_out.next = internal_in.next return do_something, assignments class InterfaceWithInstanceSignal(object): def __init__(self): self.internal_ins = [ Signal(False), Signal(False), Signal(False), Signal(False)] self.internal_outs = [ Signal(False), Signal(False), Signal(False), Signal(False)] @block def model(self, clock, input_interface, output_interface, index): internal_in = self.internal_ins[index] internal_out = self.internal_outs[index] @always_comb def assignments(): internal_in.next = input_interface output_interface.next = internal_out @always(clock.posedge) def do_something(): print('something') internal_out.next = internal_in.next return do_something, assignments @block def different_class_pipeline(clock, input_interface, output_interface): class_inst1 = HDLClass() class_inst2 = HDLClass() intermediate_interface = Signal(False) class_hdl_inst1 = class_inst1.model( clock, input_interface, intermediate_interface) class_hdl_inst2 = class_inst2.model( clock, intermediate_interface, output_interface) return class_hdl_inst1, class_hdl_inst2 @block def common_class_pipeline(clock, input_interface, output_interface): class_inst = HDLClass() intermediate_interface = Signal(False) intermediate_interface_2 = Signal(False) intermediate_interface_3 = Signal(False) class_hdl_inst1 = class_inst.model( clock, input_interface, intermediate_interface) class_hdl_inst2 = class_inst.model( clock, intermediate_interface, intermediate_interface_2) class_hdl_inst3 = class_inst.model( clock, intermediate_interface_2, intermediate_interface_3) class_hdl_inst4 = class_inst.model( clock, intermediate_interface_3, output_interface) return class_hdl_inst1, class_hdl_inst2, class_hdl_inst3, class_hdl_inst4 @block def interface_with_method_pipeline(clock, input_interface, output_interface): class_inst = InterfaceWithInstanceSignal() intermediate_interface = Signal(False) intermediate_interface_2 = Signal(False) intermediate_interface_3 = Signal(False) class_hdl_inst1 = class_inst.model( clock, input_interface, intermediate_interface, 0) class_hdl_inst2 = class_inst.model( clock, intermediate_interface, intermediate_interface_2, 1) class_hdl_inst3 = class_inst.model( clock, intermediate_interface_2, intermediate_interface_3, 2) class_hdl_inst4 = class_inst.model( clock, intermediate_interface_3, output_interface, 3) return class_hdl_inst1, class_hdl_inst2, class_hdl_inst3, class_hdl_inst4 @block def bench(class_name='different_class'): clk = Signal(False) reset = Signal(False) input_interface = Signal(False) output_interface = Signal(False) N = 20 @instance def clkgen(): clk.next = 0 for n in range(N): yield delay(10) clk.next = not clk raise StopSimulation() if class_name == 'common_class': pipeline_inst = common_class_pipeline( clk, input_interface, output_interface) elif class_name == 'interface': pipeline_inst = interface_with_method_pipeline( clk, input_interface, output_interface) elif class_name == 'different_class': pipeline_inst = different_class_pipeline( clk, input_interface, output_interface) return pipeline_inst, clkgen def test_multiple_class_single_method(): clock = Signal(False) reset = Signal(False) input_interface = Signal(False) output_interface = Signal(False) assert conversion.verify(bench()) == 0 def test_single_class_single_method(): clock = Signal(False) reset = Signal(False) input_interface = Signal(False) output_interface = Signal(False) assert conversion.verify(bench(class_name='common_class')) == 0 def test_single_interface_with_single_method(): clock = Signal(False) reset = Signal(False) input_interface = Signal(False) output_interface = Signal(False) assert conversion.verify(bench(class_name='interface')) == 0 myhdl-0.11/myhdl/test/conversion/general/test_constants.py000066400000000000000000000011021347432460400240740ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * @block def constants(v, u, x, y, z, a): b = Signal(bool(0)) c = Signal(bool(1)) d = Signal(intbv(5)[8:]) e = Signal(intbv(4, min=-3, max=9)) @always_comb def logic(): u.next = d v.next = e x.next = b y.next = c z.next = a return logic x, y, z, a = [Signal(bool(0)) for i in range(4)] u = Signal(intbv(0)[8:]) v = Signal(intbv(0, min=-3, max=9)) def test_constants(): assert constants(v, u, x, y, z, a).analyze_convert() == 0 myhdl-0.11/myhdl/test/conversion/general/test_dec.py000066400000000000000000000120001347432460400226120ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path import random from random import randrange random.seed(2) import myhdl from myhdl import * ACTIVE_LOW, INACTIVE_HIGH = 0, 1 @block def decRef(count, enable, clock, reset, n): """ Decrementer with enable. count -- output enable -- control input, decrement when 1 clock -- clock input reset -- asynchronous reset input n -- counter max value """ @instance def logic(): while 1: yield clock.posedge, reset.negedge if reset == ACTIVE_LOW: count.next = 0 else: if enable: if count == -n: count.next = n-1 else: count.next = count - 1 return logic @block def dec(count, enable, clock, reset, n): """ Decrementer with enable. count -- output enable -- control input, decrement when 1 clock -- clock input reset -- asynchronous reset input n -- counter max value """ @instance def decProcess(): while 1: yield clock.posedge, reset.negedge if reset == ACTIVE_LOW: count.next = 0 else: if enable: if count == -n: count.next = n-1 else: count.next = count - 1 return decProcess @block def decFunc(count, enable, clock, reset, n): def decFuncFunc(cnt): count_next = intbv(0, min=-n, max=n) if cnt == -n: count_next[:] = n-1 else: count_next[:] = cnt - 1 return count_next @always(clock.posedge, reset.negedge) def decFuncGen(): if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = decFuncFunc(count) return decFuncGen @block def decTask(count, enable, clock, reset, n): def decTaskFunc(cnt, enable, reset, n): if enable: if cnt == -n: cnt[:] = n-1 else: cnt[:] = cnt - 1 @instance def decTaskGen(): cnt = intbv(0, min=-n, max=n) while 1: yield clock.posedge, reset.negedge if reset == ACTIVE_LOW: cnt[:] = 0 count.next = 0 else: # print count decTaskFunc(cnt, enable, reset, n) count.next = cnt return decTaskGen @block def decTaskFreeVar(count, enable, clock, reset, n): def decTaskFunc(): if enable: if count == -n: count.next = n-1 else: count.next = count - 1 @instance def decTaskGen(): while 1: yield clock.posedge, reset.negedge if reset == ACTIVE_LOW: count.next = 0 else: # print count decTaskFunc() return decTaskGen @block def DecBench(dec): m = 8 n = 2 ** (m-1) count = Signal(intbv(0, min=-n, max=n)) count_v = Signal(intbv(0, min=-n, max=n)) enable = Signal(bool(0)) clock, reset = [Signal(bool(1)) for i in range(2)] @instance def clockGen(): yield delay(10) clock.next = 0 while 1: yield delay(10) clock.next = not clock enables = tuple([min(1, randrange(5)) for i in range(1000)]) @instance def stimulus(): reset.next = INACTIVE_HIGH yield clock.negedge reset.next = ACTIVE_LOW yield clock.negedge reset.next = INACTIVE_HIGH for i in range(1000): enable.next = 1 yield clock.negedge for i in range(len(enables)): enable.next = enables[i] yield clock.negedge raise StopSimulation @instance def check(): yield reset.negedge yield reset.posedge print(count) while 1: yield clock.posedge yield delay(1) print(count) dec_inst = dec(count, enable, clock, reset, n=n) return dec_inst, clockGen, stimulus, check def testDecRef(): assert DecBench(decRef).verify_convert() == 0 def testDec(): assert DecBench(dec).verify_convert() == 0 def testDecFunc(): assert DecBench(decFunc).verify_convert() == 0 def testDecTask(): assert DecBench(decTask).verify_convert() == 0 ## def testDecTaskFreeVar(): ## assert verify(DecBench, decTaskFreeVar) == 0 ## def testDecRef(self): ## sim = self.bench(decRef) ## sim.run(quiet=1) ## def testDec(self): ## sim = self.bench(dec) ## sim.run(quiet=1) ## def testDecFunc(self): ## sim = self.bench(decFunc) ## sim.run(quiet=1) ## signed inout in task doesn't work yet in Icarus ## def testDecTask(self): ## sim = self.bench(decTask) ## sim.run(quiet=1) ## def testDecTaskFreeVar(self): ## sim = self.bench(decTaskFreeVar) ## sim.run(quiet=1) myhdl-0.11/myhdl/test/conversion/general/test_errors.py000066400000000000000000000025361347432460400234100ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from myhdl import ConversionError from myhdl.conversion._misc import _error from myhdl.conversion import verify @block def sigAugmAssignUnsupported(z, a): @always(a) def logic(): z.next += a return logic def test_SigAugmAssignUnsupported(): z = Signal(intbv(0)[8:]) a = Signal(intbv(0)[8:]) try: verify(sigAugmAssignUnsupported(z, a)) except ConversionError as e: assert e.kind == _error.NotSupported else: assert False @block def modbvRange(z, a, b): @always(a, b) def logic(): s = modbv(0, min=0, max=35) s[:] = a + b z.next = s return logic def test_modbvRange(): z = Signal(intbv(0)[8:]) a = Signal(intbv(0)[4:]) b = Signal(intbv(0)[4:]) try: verify(modbvRange(z, a, b)) except ConversionError as e: assert e.kind == _error.ModbvRange else: assert False @block def modbvSigRange(z, a, b): @always(a, b) def logic(): z.next = a + b return logic def test_modbvSigRange(): z = Signal(modbv(0, min=0, max=42)) a = Signal(intbv(0)[4:]) b = Signal(intbv(0)[4:]) try: verify(modbvSigRange(z, a, b)) except ConversionError as e: assert e.kind == _error.ModbvRange else: assert False myhdl-0.11/myhdl/test/conversion/general/test_fsm.py000066400000000000000000000056631347432460400226650ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path import myhdl from myhdl import * # SEARCH, CONFIRM, SYNC = range(3) ACTIVE_LOW = bool(0) FRAME_SIZE = 8 t_State_b = enum('SEARCH', 'CONFIRM', 'SYNC') t_State_oh = enum('SEARCH', 'CONFIRM', 'SYNC', encoding="one_hot") t_State_oc = enum('SEARCH', 'CONFIRM', 'SYNC', encoding="one_cold") @block def FramerCtrl(SOF, state, syncFlag, clk, reset_n, t_State): """ Framing control FSM. SOF -- start-of-frame output bit state -- FramerState output syncFlag -- sync pattern found indication input clk -- clock input reset_n -- active low reset """ index = Signal(intbv(0)[8:]) # position in frame @always(clk.posedge, reset_n.negedge) def FSM(): if reset_n == ACTIVE_LOW: SOF.next = 0 index.next = 0 state.next = t_State.SEARCH else: index.next = (index + 1) % FRAME_SIZE SOF.next = 0 if state == t_State.SEARCH: index.next = 1 if syncFlag: state.next = t_State.CONFIRM elif state == t_State.CONFIRM: if index == 0: if syncFlag: state.next = t_State.SYNC else: state.next = t_State.SEARCH elif state == t_State.SYNC: if index == 0: if not syncFlag: state.next = t_State.SEARCH SOF.next = (index == FRAME_SIZE-1) else: raise ValueError("Undefined state") return FSM @block def FSMBench(FramerCtrl, t_State): SOF = Signal(bool(0)) SOF_v = Signal(bool(0)) syncFlag = Signal(bool(0)) clk = Signal(bool(0)) reset_n = Signal(bool(1)) state = Signal(t_State.SEARCH) state_v = Signal(intbv(0)[8:]) framerctrl_inst = FramerCtrl(SOF, state, syncFlag, clk, reset_n, t_State) @instance def clkgen(): clk.next = 0 reset_n.next = 1 yield delay(10) reset_n.next = 0 yield delay(10) reset_n.next = 1 yield delay(10) for i in range(1000): yield delay(10) clk.next = not clk table = (12, 8, 8, 4, 11, 8, 8, 7, 6, 8, 8) @instance def stimulus(): for i in range(3): yield clk.posedge for i in range(len(table)): n = table[i] syncFlag.next = 1 yield clk.posedge syncFlag.next = 0 for j in range(n-1): yield clk.posedge raise StopSimulation @instance def check(): yield clk.posedge while True: yield clk.negedge print("negedge") # in the end, this should work # print state return framerctrl_inst, clkgen, stimulus, check def test(): assert FSMBench(FramerCtrl, t_State_b).verify_convert() == 0 myhdl-0.11/myhdl/test/conversion/general/test_hec.py000066400000000000000000000072431347432460400226330ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path from random import randrange import myhdl from myhdl import * COSET = 0x55 def calculateHecRef(header): """ Return hec for an ATM header. Reference version. The hec polynomial is 1 + x + x**2 + x**8. """ hec = intbv(0) for bit in header[32:]: hec[8:] = concat(hec[7:2], bit ^ hec[1] ^ hec[7], bit ^ hec[0] ^ hec[7], bit ^ hec[7] ) return hec ^ COSET def calculateHecFunc(header): """ Return hec for an ATM header. Translatable version. The hec polynomial is 1 + x + x**2 + x**8. """ h = intbv(0)[8:] for i in downrange(len(header)): bit = header[i] h[:] = concat(h[7:2], bit ^ h[1] ^ h[7], bit ^ h[0] ^ h[7], bit ^ h[7] ) h ^= COSET return h def calculateHecTask(hec, header): """ Calculate hec for an ATM header. Translatable version. The hec polynomial is 1 + x + x**2 + x**8. """ h = intbv(0)[8:] for i in downrange(len(header)): bit = header[i] h[:] = concat(h[7:2], bit ^ h[1] ^ h[7], bit ^ h[0] ^ h[7], bit ^ h[7] ) h ^= COSET hec[:] = h @block def HecCalculatorPlain(hec, header): """ Hec calculation module. Plain version. """ @instance def logic(): h = intbv(0)[8:] while 1: yield header h[:] = 0 for i in downrange(len(header)): bit = header[i] h[:] = concat(h[7:2], bit ^ h[1] ^ h[7], bit ^ h[0] ^ h[7], bit ^ h[7] ) hec.next = h ^ COSET return logic def HecCalculatorFunc(hec, header): """ Hec calculation module. Version with function call. """ h = intbv(0)[8:] while 1: yield header hec.next = calculateHecFunc(header=header) def HecCalculatorTask(hec, header): """ Hec calculation module. Version with task call. """ h = intbv(0)[8:] while 1: yield header calculateHecTask(h, header) hec.next = h def HecCalculatorTask2(hec, header): """ Hec calculation module. Version with task call. """ h = intbv(0)[8:] while 1: yield header calculateHecTask(header=header, hec=h) hec.next = h def HecCalculator_v(name, hec, header): return setupCosimulation(**locals()) headers = [ 0x00000000, 0x01234567, 0xbac6f4ca ] headers.extend([randrange(2**32-1) for i in range(10)]) headers = tuple(headers) @block def HecBench(HecCalculator): hec = Signal(intbv(0)[8:]) hec_v = Signal(intbv(0)[8:]) header = Signal(intbv(-1)[32:]) heccalc_inst = HecCalculator(hec, header) @instance def stimulus(): for i in range(len(headers)): header.next = headers[i] yield delay(10) print(hec) return stimulus, heccalc_inst ## def testPlain(self): ## sim = self.bench(HecCalculatorPlain) ## Simulation(sim).run() ## def testFunc(self): ## sim = self.bench(HecCalculatorFunc) ## Simulation(sim).run() ## def testTask(self): ## sim = self.bench(HecCalculatorTask) ## Simulation(sim).run() ## def testTask2(self): ## sim = self.bench(HecCalculatorTask2) ## Simulation(sim).run() def testPlain(): assert HecBench(HecCalculatorPlain).verify_convert() == 0 myhdl-0.11/myhdl/test/conversion/general/test_inc.py000066400000000000000000000077411347432460400226500ustar00rootroot00000000000000from __future__ import absolute_import import sys import os path = os.path import random from random import randrange random.seed(2) import myhdl from myhdl import * from myhdl.conversion import verify ACTIVE_LOW, INACTIVE_HIGH = bool(0), bool(1) @block def incRef(count, enable, clock, reset, n): """ Incrementer with enable. count -- output enable -- control input, increment when 1 clock -- clock input reset -- asynchronous reset input n -- counter max value """ @instance def logic(): while 1: yield clock.posedge, reset.negedge if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = (count + 1) % n return logic @block def inc(count, enable, clock, reset, n): """ Incrementer with enable. count -- output enable -- control input, increment when 1 clock -- clock input reset -- asynchronous reset input n -- counter max value """ @always(clock.posedge, reset.negedge) def incProcess(): if reset == 0: count.next = 0 else: if enable: count.next = (count + 1) % n return incProcess @block def inc2(count, enable, clock, reset, n): @always(clock.posedge, reset.negedge) def incProcess(): if reset == ACTIVE_LOW: count.next = 0 else: if enable: if count == n-1: count.next = 0 else: count.next = count + 1 return incProcess @block def incFunc(count, enable, clock, reset, n): def incFuncFunc(cnt, enable): count_next = intbv(0, min=0, max=n) count_next[:] = cnt if enable: count_next[:] = cnt + 1 return count_next @always(clock.posedge, reset.negedge) def incFuncGen(): if reset == ACTIVE_LOW: count.next = 0 else: count.next = incFuncFunc(count, enable) return incFuncGen @block def incTask(count, enable, clock, reset, n): def incTaskFunc(cnt, enable, reset, n): if enable: cnt[:] = (cnt + 1) % n @instance def incTaskGen(): cnt = intbv(0)[8:] while 1: yield clock.posedge, reset.negedge if reset == ACTIVE_LOW: cnt[:] = 0 count.next = 0 else: # print count incTaskFunc(cnt, enable, reset, n) count.next = cnt return incTaskGen @block def incTaskFreeVar(count, enable, clock, reset, n): def incTaskFunc(): if enable: count.next = (count + 1) % n @always(clock.posedge, reset.negedge) def incTaskGen(): if reset == ACTIVE_LOW: count.next = 0 else: # print count incTaskFunc() return incTaskGen @block def IncBench(inc): NR_CYCLES = 201 m = 8 n = 2 ** m count = Signal(intbv(0)[m:]) count_v = Signal(intbv(0)[m:]) enable = Signal(bool(0)) clock, reset = [Signal(bool(0)) for i in range(2)] inc_inst = inc(count, enable, clock, reset, n=n) @instance def clockgen(): clock.next = 1 for i in range(NR_CYCLES): yield delay(10) clock.next = not clock @instance def monitor(): reset.next = 0 enable.next = 1 yield clock.negedge reset.next = 1 yield clock.negedge while True: yield clock.negedge print(count) return inc_inst, clockgen, monitor def test_incReg(): assert verify(IncBench(incRef)) == 0 def test_inc(): assert verify(IncBench(inc)) == 0 def test_inc2(): assert verify(IncBench(inc2)) == 0 def testIncTask(): assert verify(IncBench(incTask)) == 0 def testIncFunc(): assert verify(IncBench(incFunc)) == 0 myhdl-0.11/myhdl/test/conversion/general/test_initial_values.py000066400000000000000000000343211347432460400251010ustar00rootroot00000000000000from __future__ import absolute_import from random import randrange from myhdl import * import myhdl @block def initial_value_enum_bench(initial_val, **kwargs): clk = Signal(bool(0)) sig = Signal(initial_val) states = kwargs['states'] N = 20 if initial_val in (states.a, states.c): valid_states = (states.a, states.c) else: valid_states = (states.b, states.d) @instance def clkgen(): clk.next = 0 for n in range(N): yield delay(10) clk.next = not clk raise StopSimulation() @always(clk.posedge) def state_walker(): if sig == states.a: sig.next = states.c print('a') elif sig == states.c: sig.next = states.a print('c') elif sig == states.b: sig.next = states.d print('b') elif sig == states.d: sig.next = states.b print('d') if __debug__: assert sig in valid_states return state_walker, clkgen @block def bool_writer(signal, clk): @always(clk.posedge) def writer(): print(int(signal)) return writer @block def int_writer(signal, clk): @always(clk.posedge) def writer(): print(signal) return writer @block def initial_value_bench(initial_val, **kwargs): clk = Signal(bool(0)) input_signal = Signal(initial_val) if 'change_input_signal' in kwargs.keys(): change_input_signal = kwargs['change_input_signal'] else: change_input_signal = False if change_input_signal: # Make sure it doesn't overflow when changing if initial_val > 0: input_signal.val[:] = initial_val - 1 else: input_signal.val[:] = initial_val + 1 if isinstance(initial_val, bool): output_signal = Signal(not initial_val) update_val = not initial_val else: output_signal = Signal( intbv(0, min=initial_val.min, max=initial_val.max)) update_val = 0 expected_output = input_signal._init N = 10 first = [True] @instance def clkgen(): clk.next = 0 for n in range(N): yield delay(10) clk.next = not clk raise StopSimulation() @always_comb def output_driver(): output_signal.next = input_signal @always(clk.posedge) def drive_and_check(): input_signal.next = update_val if __debug__: if first[0]: assert output_signal == expected_output first[0] = False else: assert output_signal == update_val if isinstance(initial_val, bool): output_writer = bool_writer(output_signal, clk) else: output_writer = int_writer(output_signal, clk) return clkgen, output_driver, drive_and_check, output_writer @block def canonical_list_writer(output_signal_list, clk): signal_list_length = len(output_signal_list) @always(clk.posedge) def list_writer(): for i in range(signal_list_length): print(str(output_signal_list[i]._val)) canonical_list_writer.verilog_code = ''' always @(posedge $clk) begin: INITIAL_VALUE_LIST_BENCH_CANONICAL_LIST_WRITER_0_LIST_WRITER integer i; for (i=0; i<10; i=i+1) begin $$write("%h", output_signal_list[i]); $$write("\\n"); end end ''' canonical_list_writer.vhdl_code = ''' INITIAL_VALUE_BENCH_OUTPUT_WRITER: process ($clk) is variable L: line; begin if rising_edge($clk) then for i in 0 to $signal_list_length-1 loop write(L, to_hstring(unsigned(output_signal_list(i)))); writeline(output, L); end loop; end if; end process INITIAL_VALUE_BENCH_OUTPUT_WRITER; ''' return list_writer @block def bool_list_writer(output_signal_list, clk): signal_list_length = len(output_signal_list) @always(clk.posedge) def list_writer(): for i in range(signal_list_length): print(int(output_signal_list[i])) return list_writer @block def initial_value_bool_list_bench(initial_vals, **kwargs): clk = Signal(bool(0)) input_signal_list = [Signal(initial_val) for initial_val in initial_vals] output_signal_list = [ Signal(not initial_val) for initial_val in initial_vals] update_val = int(not initial_vals[0]) expected_output = [ bool(each_input._init) for each_input in input_signal_list] N = 10 first = [True] signal_list_length = len(initial_vals) @instance def clkgen(): clk.next = 0 for n in range(N): yield delay(10) clk.next = not clk raise StopSimulation() @always_comb def output_driver(): for i in range(signal_list_length): output_signal_list[i].next = input_signal_list[i] @always(clk.posedge) def drive_and_check(): for i in range(signal_list_length): input_signal_list[i].next = update_val if __debug__: if first[0]: for i in range(signal_list_length): assert output_signal_list[i] == expected_output[i] first[0] = False else: for i in range(signal_list_length): assert output_signal_list[i] == update_val output_writer = bool_list_writer(output_signal_list, clk) return clkgen, output_driver, drive_and_check, output_writer @block def assign_output(input_signal, output_signal): @always_comb def assignment(): output_signal.next = input_signal return assignment @block def initial_value_list_bench(initial_vals, **kwargs): clk = Signal(bool(0)) input_signal_list = [Signal(initial_val) for initial_val in initial_vals] if len(initial_vals[0]) == 1: output_signal_list = [ Signal(intbv(not initial_val, min=0, max=2)) for initial_val in initial_vals] update_val = int(not initial_vals[0]) else: output_signal_list = [ Signal(intbv(0, min=initial_val.min, max=initial_val.max)) for initial_val in initial_vals] update_val = 0 expected_output = [each_input._init for each_input in input_signal_list] N = 10 first = [True] signal_list_length = len(initial_vals) @instance def clkgen(): clk.next = 0 for n in range(N): yield delay(10) clk.next = not clk raise StopSimulation() # We assign each of the output drivers independently. # This forces the output to be a wire (where appropriate) so we can # check this type is handled properly too. output_drivers = [] for input_signal, output_signal in zip( input_signal_list, output_signal_list): output_drivers.append(assign_output(input_signal, output_signal)) @always(clk.posedge) def drive_and_check(): for i in range(signal_list_length): input_signal_list[i].next = update_val if __debug__: if first[0]: for i in range(signal_list_length): assert output_signal_list[i] == expected_output[i] first[0] = False else: for i in range(signal_list_length): assert output_signal_list[i] == update_val output_writer = canonical_list_writer(output_signal_list, clk) return clkgen, output_drivers, drive_and_check, output_writer @block def initial_value_mem_convert_bench(): clock = Signal(bool(0)) reset = ResetSignal(0, active=0, isasync=True) wr = Signal(bool(0)) wrd = Signal(intbv(0, min=0, max=32)) rdd = Signal(intbv(0, min=0, max=32)) addr = Signal(intbv(0, min=0, max=16)) inst = memory(clock, reset, wr, wrd, rdd, addr) return inst @block def memory(clock, reset, wr, wrd, rdd, addr): mem = [Signal(intbv(0, min=wrd.min, max=wrd.max)) for _ in range(addr.max)] inst_init = memory_init(mem) @always_seq(clock.posedge, reset=reset) def beh_mem(): rdd.next = mem[addr] if wr: mem[addr].next = wrd return inst_init, beh_mem @block def memory_init(mem): mem_size = len(mem) init_values = tuple([int(ss.val) for ss in mem]) with open("init_file.hex", 'w') as fp: for ii in range(mem_size): fp.write("CE \n") @instance def beh_init(): for ii in range(mem_size): mem[ii].next = init_values[ii] yield delay(10) return beh_init memory_init.verilog_code = """ initial begin $$readmemh("init_file.hex", $mem, $mem_size); end """ def runner(initial_val, tb=initial_value_bench, **kwargs): pre_toVerilog_initial_values = toVerilog.initial_values pre_toVHDL_initial_values = toVHDL.initial_values toVerilog.initial_values = True toVHDL.initial_values = True try: assert conversion.verify(tb(initial_val, **kwargs)) == 0 finally: toVerilog.initial_values = pre_toVerilog_initial_values toVHDL.initial_values = pre_toVHDL_initial_values def test_unsigned(): '''The correct initial value should be used for unsigned type signal. ''' min_val = 0 max_val = 34 initial_val = intbv( randrange(min_val, max_val), min=min_val, max=max_val) runner(initial_val) def test_signed(): '''The correct initial value should be used for signed type signal. ''' min_val = -12 max_val = 4 initial_val = intbv( randrange(min_val, max_val), min=min_val, max=max_val) runner(initial_val) def test_bool(): '''The correct initial value should be used for bool type signal. ''' initial_val = bool(randrange(0, 2)) runner(initial_val) def test_modbv(): '''The correct initial value should be used for modbv type signal. ''' initial_val = modbv(randrange(0, 2**10))[10:] runner(initial_val) def test_enum(): '''The correct initial value should be used for enum type signals. ''' states = enum('a', 'b', 'c', 'd') val1 = states.c val2 = states.b runner(val1, tb=initial_value_enum_bench, states=states) runner(val2, tb=initial_value_enum_bench, states=states) def test_long_signals(): '''The correct initial value should work with wide bitwidths (i.e. >32) ''' min_val = -(2**71) max_val = 2**71 - 1 initial_val = intbv( randrange(min_val, max_val), min=min_val, max=max_val) runner(initial_val) def test_single_length_signals(): '''The correct initial value should be used for a single length signal ''' initial_val = intbv(0, min=0, max=2) runner(initial_val) def test_unsigned_list(): '''The correct initial value should be used for unsigned type signal lists ''' min_val = 0 max_val = 34 initial_vals = [intbv( randrange(min_val, max_val), min=min_val, max=max_val) for each in range(10)] runner(initial_vals, tb=initial_value_list_bench) # All the same case initial_vals = [ intbv(randrange(min_val, max_val), min=min_val, max=max_val)] * 10 runner(initial_vals, tb=initial_value_list_bench) def test_signed_list(): '''The correct initial value should be used for signed type signal lists ''' min_val = -12 max_val = 4 initial_vals = [intbv( randrange(min_val, max_val), min=min_val, max=max_val) for each in range(10)] runner(initial_vals, tb=initial_value_list_bench) # All the same case initial_vals = [intbv( randrange(min_val, max_val), min=min_val, max=max_val)] * 10 runner(initial_vals, tb=initial_value_list_bench) def test_modbv_list(): '''The correct initial value should be used for modbv type signal lists ''' initial_vals = [ modbv(randrange(0, 2**10))[10:] for each in range(10)] runner(initial_vals, tb=initial_value_list_bench) # All the same case initial_vals = [modbv(randrange(0, 2**10))[10:]] * 10 runner(initial_vals, tb=initial_value_list_bench) def test_long_signals_list(): '''The correct initial value should work with wide bitwidths (i.e. >32) signal lists ''' min_val = -(2**71) max_val = 2**71 - 1 initial_vals = [intbv( randrange(min_val, max_val), min=min_val, max=max_val) for each in range(10)] runner(initial_vals, tb=initial_value_list_bench) # All the same case initial_vals = [intbv(2**65-50, min=min_val, max=max_val)] * 10 runner(initial_vals, tb=initial_value_list_bench) def test_bool_signals_list(): '''The correct initial value should be used for a boolean type signal lists ''' initial_vals = [False for each in range(10)] runner(initial_vals, tb=initial_value_bool_list_bench) initial_vals = [False] * 10 runner(initial_vals, tb=initial_value_bool_list_bench) def test_init_used(): '''It should be the _init attribute that is used for initialisation It should not be the current value, which should be ignored. ''' min_val = -34 max_val = 15 initial_val = intbv( randrange(min_val, max_val), min=min_val, max=max_val) runner(initial_val, change_input_signal=True) def test_memory_convert(): inst = initial_value_mem_convert_bench() # TODO: this needs to be converted to use the `block` convert # only and not modify the `toV*` but this will require # changes to `conversion.verify` and `conversion.analyze` # or a `config_conversion` function add to the `Block`. pre_xiv = toVerilog.initial_values pre_viv = toVHDL.initial_values # not using the runner, this test is setup for analyze only toVerilog.initial_values = True toVHDL.initial_values = True try: assert conversion.analyze(inst) == 0 finally: toVerilog.initial_values = pre_xiv toVHDL.initial_values = pre_viv #def test_init_used_list(): # '''It should be the _init attribute of each element in the list # that is used for initialisation # # It should not be the current value, which should be ignored. # ''' # min_val = -34 # max_val = 15 # initial_val = [intbv( # randrange(min_val, max_val), min=min_val, max=max_val) # for each in range(10)] # # list_runner(initial_val, change_input_signal=True) if __name__ == "__main__": test_signed_list() myhdl-0.11/myhdl/test/conversion/general/test_intbv_signed.py000066400000000000000000000166661347432460400245600ustar00rootroot00000000000000#!/usr/bin/env python # This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run the intbv.signed() unit tests. """ from __future__ import absolute_import import myhdl from myhdl import * @block def PlainIntbv(): '''Test a plain intbv instance with .signed() ----+----+----+----+----+----+----+---- -3 -2 -1 0 1 2 3 min max min max min max min max min max min max min max neither min nor max is set only max is set only min is set ''' #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ # in the following cases the .signed() function should classify the # value of the intbv instance as unsigned and return the 2's # complement value of the bits as specified by _nrbits. # @instance def logic(): print("Plain Instance Test") yield delay(10) # intbv with positive range, pos number, and msb not set, return signed() # Expect the number to be returned a1 = intbv(0x3b, min=0, max=0x7c) b1 = a1.signed() assert b1 == 0x3b # intbv with positive range, pos number, and msb set, return signed() # test various bit patterns to see that the 2's complement # conversion works correct # Expect the number to be converted to a negative number a2 = intbv(7, min=0, max=8) b2 = a2.signed() assert b2 == -1 a3 = intbv(6, min=0, max=8) b3 = a3.signed() assert b3 == -2 a4 = intbv(5, min=0, max=8) b4 = a4.signed() assert b4 == -3 # set bit #3 and increase the range so that the set bit is considered # the sign bit. Here min = 0 # Expect to return -4 a5 = intbv(4, min=0, max=5) b5 = a5.signed() assert b5 == -4 a6 = intbv(4, min=0, max=6) b6 = a6.signed() assert b6 == -4 a7 = intbv(4, min=0, max=7) b7 = a7.signed() assert b7 == -4 a8 = intbv(4, min=0, max=8) b8 = a8.signed() assert b8 == -4 # here it is not the sign bit anymore # Expect the value to be 4 a9 = intbv(4, min=0, max=9) b9 = a9.signed() assert b9 == 4 # set bit #3 and increase the range so that the set bit is considered # the sign bit. Here min > 0 # Expect to return -4 a10 = intbv(4, min=1, max=5) b10 = a10.signed() assert b10 == -4 a11 = intbv(4, min=2, max=6) b11 = a11.signed() assert b11 == -4 a12 = intbv(4, min=3, max=7) b12 = a12.signed() assert b12 == -4 a13 = intbv(4, min=4, max=8) b13 = a13.signed() assert b13 == -4 # again with min > 0, here it is not the sign bit anymore # Expect the value to be 4 a14 = intbv(4, min=2, max=9) b14 = a14.signed() assert b14 == 4 # intbv with positive range, value = 0, return signed() # Expect the number to be returned a15 = intbv(0, min=0, max=0x8) b15 = a15.signed() assert b15 == 0 #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ # in these cases the .signed() function should classify the # value of the intbv instance as signed and return the value as is # # set bit #3 and increase the range that the set bit is actually the # msb, but due to the negative range not considered signed # Expect to return 4 a20 = intbv(4, min=-1, max=5) b20 = a20.signed() assert b20 == 4 a21 = intbv(4, min=-1, max=6) b21 = a21.signed() assert b21 == 4 a22 = intbv(4, min=-1, max=7) b22 = a22.signed() assert b22 == 4 a23 = intbv(4, min=-1, max=8) b23 = a23.signed() assert b23 == 4 # intbv with negative range, pos number, and msb set, return signed() # Expect the number to returned as is a24 = intbv(7, min=-1, max=8) b24 = a24.signed() assert b24 == 7 a25 = intbv(6, min=-1, max=8) b25 = a25.signed() assert b25 == 6 a26 = intbv(5, min=-1, max=8) b26 = a26.signed() assert b26 == 5 # intbv with symmetric (min = -max) range, pos value, msb set # return signed() # Expect value returned as is a27 = intbv(4, min=-8, max=8) b27 = a27.signed() assert b27 == 4 # intbv with symmetric (min = -max) range, neg value, # return signed() # Expect value returned as is a28 = intbv(-4, min=-8, max=8) b28 = a28.signed() assert b28 == -4 # intbv with symmetric (min=-max) range, value = 0, # return signed() # Expect value returned as is a29 = intbv(0, min=-8, max=8) b29 = a29.signed() assert b29 == 0 return logic @block def SlicedSigned(): '''Test a slice with .signed() This test can actually be simplified, as a slice will always have min=0 and max > min, which will result in an intbv instance that will be considered unsigned by the intbv.signed() function. ''' @instance def logic(): b = intbv(4, min=-8, max=8) a = intbv(4, min=-8, max=8) print("SLicedSigned test") yield delay(10) b[:] = a[4:] assert b == 4 b[:] = a[4:].signed() assert b == 4 # msb is not set with a 4 bit slice b[:] = a[3:] assert b == 4 b[:] = a[3:].signed() assert b == -4 # msb is set with 3 bits sliced return logic @block def SignedConcat(): '''Test the .signed() function with the concatenate function''' @instance def logic(): print("Signed Concat test") yield delay(10) # concat 3 bits # Expect the signed function to return a negative value a = intbv(0)[3:] a[:] = concat(True, True, True) assert a == 7 assert a.signed() == -1 assert concat(True, True, True).signed() == -1 # concat a 3 bit intbv with msb set and two bits # Expect a negative number b = intbv(5,min=0,max=8) assert concat(b, True, True).signed() == -9 return logic def test_PlainIntbv(): assert conversion.verify(PlainIntbv()) == 0 def test_SlicedSigned(): assert conversion.verify(SlicedSigned()) == 0 def test_SignedConcat(): assert conversion.verify(SignedConcat()) == 0 myhdl-0.11/myhdl/test/conversion/general/test_interfaces1.py000066400000000000000000000054441347432460400243010ustar00rootroot00000000000000from __future__ import absolute_import from myhdl import (block, Signal, ResetSignal, intbv, always_seq, instance, delay, StopSimulation, ) class MyIntf(object): def __init__(self): self.x = Signal(intbv(2, min=0, max=16)) self.y = Signal(intbv(3, min=0, max=18)) @block def one_level(clock, reset, ia, ib): @always_seq(clock.posedge, reset=reset) def rtl(): ia.x.next = ib.x + 1 ia.y.next = ib.y + 1 return rtl @block def two_level(clock, reset, ia, ib): ic, ie = MyIntf(), MyIntf() one_inst = one_level(clock, reset, ic, ie) @always_seq(clock.posedge, reset=reset) def rtl(): ia.x.next = ib.x + ic.x ia.y.next = ib.y + ic.y return one_inst, rtl @block def c_testbench_one(): clock = Signal(bool(0)) reset = ResetSignal(0, active=0, isasync=True) ia, ib = MyIntf(), MyIntf() tb_dut = one_level(clock, reset, ia, ib) @instance def tb_clk(): clock.next = False yield delay(10) while True: clock.next = not clock yield delay(10) @instance def tb_stim(): reset.next = False yield delay(17) reset.next = True yield delay(17) for ii in range(7): yield clock.posedge assert ia.x == 3 assert ia.y == 4 print("%d %d %d %d" % (ia.x, ia.y, ib.x, ib.y)) raise StopSimulation return tb_dut, tb_clk, tb_stim @block def c_testbench_two(): clock = Signal(bool(0)) reset = ResetSignal(0, active=0, isasync=True) ia, ib = MyIntf(), MyIntf() tb_dut = two_level(clock, reset, ia, ib) @instance def tb_clk(): clock.next = False yield delay(10) while True: clock.next = not clock yield delay(10) @instance def tb_stim(): reset.next = False yield delay(17) reset.next = True yield delay(17) for ii in range(7): yield clock.posedge assert ia.x == 5 assert ia.y == 7 print("%d %d %d %d" % (ia.x, ia.y, ib.x, ib.y)) raise StopSimulation return tb_dut, tb_clk, tb_stim def test_one_level_analyze(): clock = Signal(bool(0)) reset = ResetSignal(0, active=0, isasync=True) ia, ib = MyIntf(), MyIntf() inst = one_level(clock, reset, ia, ib) assert inst.analyze_convert() == 0 def test_one_level_verify(): inst = c_testbench_one() assert inst.verify_convert() == 0 def test_two_level_analyze(): clock = Signal(bool(0)) reset = ResetSignal(0, active=0, isasync=True) ia, ib = MyIntf(), MyIntf() inst = two_level(clock, reset, ia, ib) assert inst.analyze_convert() == 0 def test_two_level_verify(): inst = c_testbench_two() assert inst.verify_convert() == 0 myhdl-0.11/myhdl/test/conversion/general/test_interfaces2.py000066400000000000000000000063711347432460400243020ustar00rootroot00000000000000 from myhdl import (block, Signal, ResetSignal, intbv, always_seq, always_comb, instance, delay, StopSimulation,) class Intf(object): def __init__(self): self.x = Signal(intbv(1, min=-1111, max=1111)) self.y = Signal(intbv(2, min=-2211, max=2211)) self.z = Signal(intbv(3, min=-3311, max=3311)) @block def modify(clock, reset, a): intfa = Intf() @always_seq(clock.posedge, reset=reset) def rtl_inc(): intfa.x.next = intfa.x + 1 intfa.y.next = intfa.y + 2 intfa.z.next = intfa.z + 3 @always_comb def rtl_add(): a.x.next = intfa.x + 1 a.y.next = intfa.y + 2 a.z.next = intfa.z + 3 return rtl_inc, rtl_add @block def use_interfaces(clock, reset, a, b, c): intfa = Intf() intfaa = Intf() mod_inst = modify(clock, reset, intfaa) @always_seq(clock.posedge, reset=reset) def rtl_inc(): intfa.x.next = intfa.x - 1 intfa.y.next = intfa.y - 2 intfa.z.next = intfa.z - 3 b.x.next = b.x + 1 b.y.next = b.y + 2 b.z.next = b.z + 3 c.x.next = c.x + 1 c.y.next = c.y + 2 c.z.next = c.z + 3 @always_comb def rtl_combine(): a.x.next = intfaa.x + 1 a.y.next = intfaa.y + 2 a.z.next = intfaa.z + 3 return mod_inst, rtl_inc, rtl_combine @block def name_conflict_after_replace(clock, reset, a, a_x): a_x_0 = [Signal(intbv(0)[len(a_x):]) for _ in range(8)] @always_seq(clock.posedge, reset=reset) def logic(): a.x.next = a_x a_x.next = a_x_0[1] return logic def test_name_conflict_after_replace(): clock = Signal(False) reset = ResetSignal(0, active=0, isasync=False) a = Intf() a_x = Signal(intbv(0)[len(a.x):]) inst = name_conflict_after_replace(clock, reset, a, a_x) assert inst.analyze_convert() == 0 @block def c_testbench(): clock = Signal(bool(0)) reset = ResetSignal(0, active=0, isasync=False) a, b, c = Intf(), Intf(), Intf() tb_dut = use_interfaces(clock, reset, a, b, c) @instance def tb_clk(): clock.next = False yield delay(10) while True: clock.next = not clock yield delay(10) @instance def tb_stim(): reset.next = False yield delay(23) reset.next = True yield delay(33) for ii in range(17): print("a: x=%d y=%d z=%d" % (a.x, a.y, a.z,)) print("b: x=%d y=%d z=%d" % (b.x, b.y, b.z,)) print("c: x=%d y=%d z=%d" % (c.x, c.y, c.z,)) yield clock.posedge raise StopSimulation return tb_dut, tb_clk, tb_stim def test_name_conflicts_analyze(): clock = Signal(bool(0)) reset = ResetSignal(0, active=0, isasync=False) a, b, c = Intf(), Intf(), Intf() inst = use_interfaces(clock, reset, a, b, c) assert inst.analyze_convert() == 0 def test_name_conflicts_verify(): inst = c_testbench() assert inst.verify_convert() == 0 if __name__ == '__main__': clock = Signal(False) reset = ResetSignal(0, active=0, isasync=False) a = Intf() a_x = Signal(intbv(0)[len(a.x):]) inst = name_conflict_after_replace(clock, reset, a, a_x) inst.convert() inst.convert(hdl='VHDL') myhdl-0.11/myhdl/test/conversion/general/test_interfaces3.py000066400000000000000000000113441347432460400242770ustar00rootroot00000000000000from __future__ import absolute_import import sys import myhdl from myhdl import (block, Signal, ResetSignal, intbv, always_comb, always_seq, instance, delay, StopSimulation, ) class Intf1: def __init__(self, x): self.x = Signal(intbv(0, min=x.min, max=x.max)) class Intf2: def __init__(self, y): self.y = Signal(intbv(0, min=y.min, max=y.max)) class ZBus: def __init__(self, z): self.z = Signal(intbv(0, min=z.min, max=z.max)) class Intf3: def __init__(self, z): self.z = ZBus(z) class IntfWithConstant1: def __init__(self): self.const1 = 707 self.const2 = 3 class IntfWithConstant2: def __init__(self): self.a = 9 self.b = 10 self.c = 1729 self.more_constants = IntfWithConstant1() @block def assign(y, x): @always_comb def beh_assign(): y.next = x return beh_assign @block def assign_intf(x, y): @always_comb def rtl(): x.x.next = y.y return rtl @block def top_assign(x, y, z): """ This module does not test top-level interfaces, it only tests intermediate interfaces. """ i1, i2 = Intf1(x), Intf2(y) inst1 = assign(x, i1.x) # x = i1.x inst2 = assign(i2.y, y) # i2.y = y inst3 = assign_intf(i1, i2) return myhdl.instances() @block def c_testbench_one(): x, y, z = [Signal(intbv(0, min=-8, max=8)) for _ in range(3)] tb_dut = top_assign(x, y, z) @instance def tb_stim(): y.next = 3 yield delay(10) print("x: %d" % (x,)) assert x == 3 return tb_dut, tb_stim @block def multi_comb(x, y, z): @always_comb def rtl(): x.x.next = y.y + z.z.z return rtl @block def top_multi_comb(x, y, z): """ This module does not test top-level interfaces, it only tests intermediate interfaces. """ intf = Intf1(x), Intf2(y), Intf3(z) x.assign(intf[0].x) intf[1].y.assign(y) intf[2].z.z.assign(z) inst = multi_comb(*intf) return inst @block def c_testbench_two(): x, y, z = [Signal(intbv(0, min=-8, max=8)) for _ in range(3)] tb_dut = top_multi_comb(x, y, z) @instance def tb_stim(): y.next = 3 z.next = 2 yield delay(10) print("x: %d" % (x,)) assert x == 5 return tb_dut, tb_stim @block def top_const(clock, reset, x, y, intf): @always_seq(clock.posedge, reset=reset) def rtl1(): v = intf.a**3 + intf.b**3 x.next = v - intf.c @always_comb def rtl2(): y.next = x + intf.more_constants.const1 - \ intf.more_constants.const2*235 - 2 return rtl1, rtl2 @block def c_testbench_three(): """ this will test the use of constants in an inteface as well as top-level interface conversion. """ clock = Signal(bool(0)) reset = ResetSignal(0, active=0, isasync=True) x = Signal(intbv(3, min=-5000, max=5000)) y = Signal(intbv(4, min=-200, max=200)) intf = IntfWithConstant2() tbdut = top_const(clock, reset, x, y, intf) @instance def tbclk(): clock.next = False while True: yield delay(3) clock.next = not clock @instance def tbstim(): reset.next = reset.active yield delay(33) reset.next = not reset.active yield clock.posedge yield clock.posedge print("x: %d" % (x,)) print("y: %d" % (y,)) assert x == 0 assert y == 0 raise StopSimulation return tbdut, tbclk, tbstim def test_one_analyze(): x, y, z = [Signal(intbv(0, min=-8, max=8)) for _ in range(3)] # fool name check in convertor # to be reviewed x._name = 'x' y._name = 'y' z._name = 'z' inst = top_assign(x, y, z) assert inst.analyze_convert() == 0 def test_one_verify(): inst = c_testbench_one() assert inst.verify_convert() == 0 def test_two_analyze(): x, y, z = [Signal(intbv(0, min=-8, max=8)) for _ in range(3)] # fool name check in converter # to be reviewed x._name = 'x' y._name = 'y' z._name = 'z' inst = top_multi_comb(x, y, z) assert inst.analyze_convert() == 0 def test_two_verify(): inst = c_testbench_two() assert inst.verify_convert() == 0 def test_three_analyze(): clock = Signal(bool(0)) reset = ResetSignal(0, active=0, isasync=True) x = Signal(intbv(3, min=-5000, max=5000)) y = Signal(intbv(4, min=-200, max=200)) intf = IntfWithConstant2() inst = top_const(clock, reset, x, y, intf) assert inst.analyze_convert() == 0 def test_three_verify(): inst = c_testbench_three() assert inst.verify_convert() == 0 myhdl-0.11/myhdl/test/conversion/general/test_interfaces4.py000066400000000000000000000105171347432460400243010ustar00rootroot00000000000000 import sys import myhdl from myhdl import (block, Signal, ResetSignal, modbv, always_seq, concat, instance, delay, StopSimulation) from myhdl.conversion import analyze, verify """ This set of tests exercises a peculiar scenario where an expanded interface Signal is flagged as having multiple drivers. This appears to be a name collision in the name expansion and was introduced in 08519b4. """ class Intf1(object): def __init__(self): self.sig1 = Signal(bool(0)) self.sig2 = Signal(bool(0)) self.sig3 = Signal(modbv(0)[8:]) class Intf2(object): def __init__(self): self.sig1 = Signal(bool(0)) self.sig2 = Signal(bool(0)) self.sig3 = Signal(modbv(0)[8:]) self.intf = Intf1() @block def use_nested_intf(clock, reset, intf1, intf2): sig1 = Signal(bool(0)) sig2 = Signal(bool(0)) @always_seq(clock.posedge, reset) def proc(): if intf1.sig1: sig1.next = True sig2.next = False else: sig1.next = False sig2.next = True intf2.sig1.next = sig1 intf2.sig2.next = sig2 or intf1.sig2 intf2.sig3.next = ~intf1.sig3 intf2.intf.sig1.next = intf2.sig2 intf2.intf.sig2.next = intf2.intf.sig1 return proc @block def something_peculiar(clock, reset, intf1, intf2): @always_seq(clock.posedge, reset) def proc(): # remove the if/else and leave just the line in the # if clause the error does not occur, inlcude the if/else # and the error occurs if intf1.sig3 > 0: # remove no error intf2.sig1.next = not intf1.sig1 intf2.sig2.next = not intf1.sig2 intf2.sig3.next = intf1.sig3 + intf2.sig3 else: # remove no error intf2.sig3.next = 0 # remove no error return proc @block def interfaces_top(clock, reset, sdi, sdo, nested): intf1, intf2, intf3 = Intf1(), Intf2(), Intf1() inst1 = use_nested_intf(clock, reset, intf1, intf2) inst2 = something_peculiar(clock, reset, intf2, intf3) @always_seq(clock.posedge, reset) def assigns(): intf1.sig1.next = sdi intf1.sig2.next = not sdi intf1.sig3.next = concat(intf1.sig3[7:1], sdi) sdo.next = intf3.sig1 | intf3.sig2 | intf3.sig3[2] nested.next = intf2.intf.sig2 return inst1, inst2, assigns @block def c_testbench_one(): """ yet another interface test. This test is used to expose a particular bug that was discovered during the development of interface conversion. The structure used in this example caused and invalid multiple driver error. """ clock = Signal(bool(0)) reset = ResetSignal(0, active=1, isasync=False) sdi = Signal(bool(0)) sdo = Signal(bool(0)) nested = Signal(bool()) tbdut = interfaces_top(clock, reset, sdi, sdo, nested) @instance def tbclk(): clock.next = False while True: yield delay(3) clock.next = not clock # there is an issue when using bools with variables and # VHDL conversion, this might be an expected limitation? # expected = (False, False, False, True, True, True, # False, True, False, True) # use a tuple-of-ints instead of the above tuple-of-bools expected = (0, 0, 0, 1, 1, 1, 0, 1, 0, 1) ra = reset.active @instance def tbstim(): sdi.next = False reset.next = ra yield delay(13) reset.next = not ra yield clock.posedge for ii in range(10): print("sdi: %d, sdo: %d, nested: %d" % (sdi, sdo, nested)) expected_bit = expected[ii] assert sdo == expected_bit sdi.next = not sdi yield clock.posedge raise StopSimulation return tbclk, tbstim, tbdut def test_one_testbench(): inst = c_testbench_one() inst.run_sim() def test_one_analyze(): clock = Signal(bool(0)) reset = ResetSignal(0, active=1, isasync=False) sdi = Signal(bool(0)) sdo = Signal(bool(0)) nested = Signal(bool(0)) assert analyze(interfaces_top(clock, reset, sdi, sdo, nested)) == 0 def test_one_verify(): assert verify(c_testbench_one()) == 0 def test_conversion(): inst = c_testbench_one() inst.convert(hdl='Verilog') inst.convert(hdl='VHDL') myhdl-0.11/myhdl/test/conversion/general/test_listofsigs.py000066400000000000000000000157601347432460400242650ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from myhdl import ConversionError from myhdl.conversion._misc import _error N = 8 M= 2**N ### A first case that already worked with 5.0 list of signal constraints ### @block def intbv2list(): """Conversion between intbv and list of boolean signals.""" a = Signal(intbv(0)[N:]) b = [Signal(bool(0)) for i in range(len(a))] z = Signal(intbv(0)[N:]) @always(a) def extract(): for i in range(len(a)): b[i].next = a[i] @always(*b) def assemble(): for i in range(len(b)): z.next[i] = b[i] @instance def stimulus(): for i in range(M): a.next = i yield delay(10) assert z == a print(a) raise StopSimulation return extract, assemble, stimulus # test def test_intbv2list(): assert conversion.verify(intbv2list()) == 0 ### A number of cases with relaxed constraints, for various decorator types ### @block def inv1(z, a): @always(a) def logic(): z.next = not a return logic @block def inv2(z, a): @always_comb def logic(): z.next = not a return logic @block def inv3(z, a): @instance def logic(): while True: yield a z.next = not a return logic @block def inv4(z, a): @instance def logic(): while True: yield a yield delay(1) z.next = not a return logic @block def case1(z, a, inv): b = [Signal(bool(1)) for i in range(len(a))] c = [Signal(bool(0)) for i in range(len(a))] @always(a) def extract(): for i in range(len(a)): b[i].next = a[i] inst = [None] * len(b) for i in range(len(b)): inst[i] = inv(c[i], b[i]) @always(*c) def assemble(): for i in range(len(c)): z.next[i] = c[i] return extract, inst, assemble @block def case2(z, a, inv): b = [Signal(bool(1)) for i in range(len(a))] c = [Signal(bool(0)) for i in range(len(a))] @always_comb def extract(): for i in range(len(a)): b[i].next = a[i] inst = [None] * len(b) for i in range(len(b)): inst[i] = inv(c[i], b[i]) @always_comb def assemble(): for i in range(len(c)): z.next[i] = c[i] return extract, inst, assemble @block def case3(z, a, inv): b = [Signal(bool(1)) for i in range(len(a))] c = [Signal(bool(0)) for i in range(len(a))] @instance def extract(): while True: yield a for i in range(len(a)): b[i].next = a[i] inst = [None] * len(b) for i in range(len(b)): inst[i] = inv(c[i], b[i]) @instance def assemble(): while True: yield c for i in range(len(c)): z.next[i] = c[i] return extract, inst, assemble @block def case4(z, a, inv): b = [Signal(bool(1)) for i in range(len(a))] c = [Signal(bool(0)) for i in range(len(a))] @instance def extract(): while True: yield a yield delay(1) for i in range(len(a)): b[i].next = a[i] inst = [None] * len(b) for i in range(len(b)): inst[i] = inv(c[i], b[i]) @instance def assemble(): while True: yield c yield delay(1) for i in range(len(c)): z.next[i] = c[i] return extract, inst, assemble @block def processlist(case, inv): """Extract list from intbv, do some processing, reassemble.""" a = Signal(intbv(1)[N:]) z = Signal(intbv(0)[N:]) case_inst = case(z, a, inv) @instance def stimulus(): for i in range(M): yield delay(10) a.next = i yield delay(10) assert z == ~a print(z) raise StopSimulation return case_inst, stimulus # functional tests def test_processlist11(): assert conversion.verify(processlist(case1, inv1)) == 0 def test_processlist12(): assert conversion.verify(processlist(case1, inv2))== 0 def test_processlist22(): assert conversion.verify(processlist(case2, inv2))== 0 def test_processlist33(): assert conversion.verify(processlist(case3, inv3))== 0 def test_processlist44(): assert conversion.verify(processlist(case4, inv4))== 0 # signed and unsigned @block def unsigned(): z = Signal(intbv(0)[8:]) a = [Signal(intbv(0)[8:]) for i in range(3)] @always_comb def logic(): z.next = a[1] + a[2] @instance def stimulus(): a[0].next = 2 a[1].next = 5 yield delay(10) print(z) return logic, stimulus def test_unsigned(): conversion.verify(unsigned()) @block def signed(): z = Signal(intbv(0, min=-10, max=34)) a = [Signal(intbv(0, min=-5, max=17)) for i in range(3)] @always_comb def logic(): z.next = a[1] + a[2] @instance def stimulus(): a[0].next = 2 a[1].next = -5 yield delay(10) print(z) return logic, stimulus def test_signed(): conversion.verify(signed()) @block def mixed(): z = Signal(intbv(0, min=0, max=34)) a = [Signal(intbv(0, min=-11, max=17)) for i in range(3)] b = [Signal(intbv(0)[5:]) for i in range(3)] @always_comb def logic(): z.next = a[1] + b[2] @instance def stimulus(): a[0].next = -6 b[2].next = 15 yield delay(10) print(z) return logic, stimulus def test_mixed(): conversion.verify(mixed()) ### error tests # port in list @block def portInList(z, a, b): m = [a, b] @always_comb def logic(): z.next = m[0] + m[1] return logic def test_portInList(): z, a, b = [Signal(intbv(0)[8:]) for i in range(3)] try: inst = conversion.analyze(portInList(z, a, b)) except ConversionError as e: assert e.kind == _error.PortInList else: assert False # signal in multiple lists @block def sigInMultipleLists(): z, a, b = [Signal(intbv(0)[8:]) for i in range(3)] m1 = [a, b] m2 = [a, b] @always_comb def logic(): z.next = m1[0] + m2[1] return logic def test_sigInMultipleLists(): try: inst = conversion.analyze(sigInMultipleLists()) except ConversionError as e: assert e.kind == _error.SignalInMultipleLists else: assert False # list of signals as port @block def my_register(clk, inp, outp): @always(clk.posedge) def my_register_impl(): for index in range(len(inp)): outp[index].next = inp[index] return my_register_impl def test_listAsPort(): count = 3 clk = Signal(False) inp = [Signal(intbv(0)[8:0]) for index in range(count)] outp = [Signal(intbv(0)[8:0]) for index in range(count)] try: inst = conversion.analyze(my_register(clk, inp, outp)) except ConversionError as e: assert e.kind == _error.ListAsPort else: assert False myhdl-0.11/myhdl/test/conversion/general/test_loops.py000066400000000000000000000201631347432460400232240ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path from random import randrange import myhdl from myhdl import * from myhdl.conversion import verify, analyze from myhdl import ConversionError from myhdl.conversion._misc import _error @block def ForLoopError1(a, out): @instance def logic(): while 1: yield a var = 0 for i in (1, 2, 3): if a[i] == 1: var += 1 out.next = var return logic @block def ForLoopError2(a, out): @instance def logic(): while 1: yield a var = 0 for i in list((1, 2, 3)): if a[i] == 1: var += 1 out.next = var return logic @block def ForLoop1(a, out): @instance def logic(): while 1: yield a var = 0 for i in downrange(len(a)): if a[i] == 1: var += 1 out.next = var return logic @block def ForLoop2(a, out): @instance def logic(): while 1: yield a var = 0 for i in downrange(len(a), 5): if a[i] == 1: var += 1 out.next = var return logic @block def ForLoop3(a, out): @instance def logic(): while 1: yield a var = 0 for i in downrange(len(a), 3, 2): if a[i] == 1: var += 1 out.next = var return logic @block def ForLoop4(a, out): @instance def logic(): while 1: yield a var = 0 for i in range(len(a)): if a[i] == 1: var += 1 out.next = var return logic @block def ForLoop5(a, out): @instance def logic(): while 1: yield a var = 0 for i in range(6, len(a)): if a[i] == 1: var += 1 out.next = var return logic @block def ForLoop6(a, out): @instance def logic(): while 1: yield a var = 0 for i in range(5, len(a), 3): if a[i] == 1: var += 1 out.next = var return logic @block def ForContinueLoop(a, out): @instance def logic(): while 1: yield a var = 0 for i in downrange(len(a)): if a[i] == 0: continue var += 1 out.next = var return logic @block def ForBreakLoop(a, out): @instance def logic(): while 1: yield a out.next = 0 for i in downrange(len(a)): if a[i] == 1: out.next = i break return logic @block def ForBreakContinueLoop(a, out): @instance def logic(): while 1: yield a out.next = 0 for i in downrange(len(a)): if a[i] == 0: continue out.next = i break return logic @block def NestedForLoop1(a, out): @instance def logic(): while 1: yield a var = 0 for i in downrange(len(a)): if a[i] == 0: continue else: for j in downrange(i): if a[j] == 0: var +=1 break out.next = var return logic @block def NestedForLoop2(a, out): @instance def logic(): while 1: yield a var = 0 out.next = 0 for i in downrange(len(a)): if a[i] == 0: continue else: for j in downrange(i-1): if a[j] == 0: pass else: out.next = j break break return logic def ReturnFromFunction(a): for i in downrange(len(a)): if a[i] == 1: return i return 0 @block def FunctionCall(a, out): @instance def logic(): while 1: yield a out.next = ReturnFromFunction(a) return logic # During the following check, I noticed that non-blocking assignments # are not scheduled when a task is disabled in Icarus. Apparently # this is one of the many vague areas in the Verilog standard. def ReturnFromTask(a, out): for i in downrange(len(a)): if a[i] == 1: out[:] = i return out[:] = 23 # to notice it @block def TaskCall(a, out): @instance def logic(): var = intbv(0)[8:] while 1: yield a ReturnFromTask(a, var) out.next = var return logic @block def WhileLoop(a, out): @instance def logic(): while 1: yield a var = 0 i = len(a)-1 while i >= 0: if a[i] == 1: var += 1 i -= 1 out.next = var return logic @block def WhileContinueLoop(a, out): @instance def logic(): while 1: yield a var = 0 i = len(a)-1 while i >= 0: if a[i] == 0: i -= 1 continue var += 1 i -= 1 out.next = var return logic @block def WhileBreakLoop(a, out): @instance def logic(): while 1: yield a var = 0 i = len(a)-1 out.next = 0 while i >= 0: if a[i] == 1: out.next = i break i -= 1 return logic @block def WhileBreakContinueLoop(a, out): @instance def logic(): while 1: yield a var = 0 i = len(a)-1 out.next = 0 while i >= 0: if a[i] == 0: i -= 1 continue out.next = i break return logic @block def LoopBench(LoopTest): a = Signal(intbv(-1)[16:]) z = Signal(intbv(0)[16:]) looptest_inst = LoopTest(a, z) data = tuple([randrange(2**min(i, 16)) for i in range(100)]) @instance def stimulus(): for i in range(100): a.next = data[i] yield delay(10) print(z) return stimulus, looptest_inst def testForLoopError1(): try: analyze(LoopBench(ForLoopError1)) except ConversionError as e: assert e.kind == _error.Requirement else: assert False def testForLoopError2(): try: analyze(LoopBench(ForLoopError2)) except ConversionError as e: assert e.kind == _error.Requirement else: assert False def testForLoop1(): assert verify(LoopBench(ForLoop1)) == 0 def testForLoop2(): assert verify(LoopBench(ForLoop2)) == 0 def testForLoop4(): assert verify(LoopBench(ForLoop4)) == 0 def testForLoop5(): assert verify(LoopBench(ForLoop5)) == 0 # for loop 3 and 6 can't work in vhdl def testForContinueLoop(): assert verify(LoopBench(ForContinueLoop)) == 0 def testForBreakLoop(): assert verify(LoopBench(ForBreakLoop)) == 0 def testForBreakContinueLoop(): assert verify(LoopBench(ForBreakContinueLoop))== 0 def testNestedForLoop1(): assert verify(LoopBench(NestedForLoop1)) == 0 def testNestedForLoop2(): assert verify(LoopBench(NestedForLoop2)) == 0 def testWhileLoop(): assert verify(LoopBench(FunctionCall)) == 0 ## def testTaskCall(self): ## sim = self.bench(TaskCall) ## Simulation(sim).run() def testWhileLoop(): assert verify(LoopBench(WhileLoop)) == 0 def testWhileContinueLoop(): assert verify(LoopBench(WhileContinueLoop)) == 0 def testWhileBreakLoop(): assert verify(LoopBench(WhileBreakLoop)) == 0 def testWhileBreakContinueLoop(): assert verify(LoopBench(WhileBreakContinueLoop)) == 0 myhdl-0.11/myhdl/test/conversion/general/test_method.py000066400000000000000000000104661347432460400233550ustar00rootroot00000000000000from __future__ import absolute_import import sys import myhdl from myhdl import * from myhdl.conversion import verify class HdlObj(object): def __init__(self): pass @block def method_func(self, clk, srst, x, y): z = Signal(intbv(0, min=y.min, max=y.max)) ifx = self._mfunc(x, z) @always(clk.posedge) def hdl(): if srst: y.next = 0 else: y.next = x + z # x + (x+1) return hdl, ifx @block def _mfunc(self, x, y): @always_comb def _hdl(): y.next = x + 1 return _hdl @block def _func(x,y): @always_comb def _hdl(): y.next = x + 1 return _hdl class HdlObjObj(object): def __init__(self): pass @block def method_func(self, clk, srst, x, y): z1 = Signal(intbv(0, min=y.min, max=y.max)) z2 = Signal(intbv(0, min=y.min, max=y.max)) hobj = HdlObj() ifx1 = hobj._mfunc(x, z1) ifx2 = _func(x, z2) @always(clk.posedge) def hdl(): if srst: y.next = 0 else: y.next = x + z1 + (z1 - z2) return hdl, ifx1, ifx2 class HdlObjAttrSimple(object): def __init__(self): self.AConstant = 3 @block def method_func(self, clk, srst, x, y): # limitation for class method conversion, the object attributes # can only be used/accessed during elaboration. AConstant = int(self.AConstant) @always(clk.posedge) def hdl(): if srst: y.next = 0 else: y.next = x + (x+1) + AConstant - 3 return hdl class HdlObjAttr(object): def __init__(self, clk, srst, x, y): self.clk = clk self.srst = srst self.x = x self.y = y self.z = Signal(intbv(0, min=y.min, max=y.max)) self.hobj = HdlObj() @block def method_func(self): ifx = self.hobj._mfunc(self.x, self.z) @always(self.clk.posedge) def hdl(): if self.srst: self.y.next = 0 else: self.y.next = self.x + self.z return hdl, ifx @block def ObjBench(hObj): clk = Signal(False) srst = Signal(False) x = Signal(intbv(0, min=0, max=16)) y = Signal(intbv(0, min=0, max=16)) if hObj == HdlObjAttr: hdlobj_inst = hObj(clk, srst, x, y) hdl_inst = hdlobj_inst.method_func() elif hObj == HdlObjAttrSimple: hdlobj_inst = hObj() hdl_inst = hdlobj_inst.method_func(clk, srst, x, y) elif hObj == HdlObj or hObj == HdlObjObj: hdlobj_inst = hObj() hdl_inst = hdlobj_inst.method_func(clk, srst, x, y) else: raise StandardError("Incorrect hOjb %s" % (type(hObj), str(hObj))) @instance def tb_clkgen(): clk.next = False srst.next = False yield delay(10) srst.next = True yield delay(10) srst.next = False yield delay(10) for i in range(1000): yield delay(10) clk.next = not clk xtable = (1,2,3,4,5,6) ytable = (3,5,7,9,11,13) @instance def tb_stimulus(): for ii in range(30): yield clk.posedge assert len(xtable) == len(ytable) for ii in range(len(xtable)): nx = xtable[ii] ny = ytable[ii] x.next = nx yield clk.posedge yield clk.posedge print("x %d y %d" % (x, y)) assert x == nx assert y == ny raise StopSimulation return hdl_inst, tb_clkgen, tb_stimulus def test_hdlobj(): assert verify(ObjBench(HdlObj)) == 0 def test_hdlobjobj(): assert verify(ObjBench(HdlObjObj)) == 0 def test_hdlobjattrsimple(): assert verify(ObjBench(HdlObjAttrSimple)) == 0 #def test_hdlobjattr(): # # object attributes currently not supported, these # # tests are for class method conversion only and not # # class attribute conversion. When (if) class attribute # # is supported remove this test. # assert verify(ObjBench, HdlObjAttr) == 1 if __name__ == '__main__': Simulation(ObjBench(HdlObj)).run() Simulation(ObjBench(HdlObjAttrSimple)).run() Simulation(ObjBench(HdlObjAttr)).run() myhdl-0.11/myhdl/test/conversion/general/test_nonlocal.py000066400000000000000000000024251347432460400236760ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path import myhdl from myhdl import * def NonlocalBench(): ALL_ONES = 2**7-1 ONE = 1 qout = Signal(intbv(ONE)[8:]) init = Signal(bool(0)) clk = Signal(bool(0)) reset = ResetSignal(0, active=1, isasync=True) q = intbv(ONE)[8:] @always_seq(clk.posedge, reset=reset) def scrambler(): if init: q[8:1] = ALL_ONES else: q[0] = q[7] ^ q[6] q[8:1] = q[7:0] qout.next = q[8:1] @instance def clkgen(): clk.next = 1 while True: yield delay(10) clk.next = not clk @instance def stimulus(): reset.next = 0 init.next = 0 yield clk.negedge reset.next = 1 yield clk.negedge print(qout) assert qout == ONE reset.next = 0 for i in range(100): yield clk.negedge print(qout) init.next = 1 yield clk.negedge assert qout == ALL_ONES print(qout) init.next = 0 for i in range(300): print(qout) raise StopSimulation() return scrambler, clkgen, stimulus def test_nonlocal(): assert conversion.verify(NonlocalBench) == 0 myhdl-0.11/myhdl/test/conversion/general/test_numass.py000066400000000000000000000024611347432460400233770ustar00rootroot00000000000000from __future__ import absolute_import from random import randrange import myhdl from myhdl import * @block def NumassBench(): p = Signal(intbv(1)[8:]) q = Signal(intbv(1)[40:]) r = Signal(intbv(1, min=-256, max=256)) s = Signal(intbv(1, min=-2**40, max=2**40)) PBIGINT = randrange(2**34, 2**40) NBIGINT = -randrange(2**34, 2**40) @instance def check(): p.next = 0 q.next = 0 r.next = 0 s.next = 0 yield delay(10) print("%d %d %d %d" % (p, q, r, s)) p.next = 1 q.next = 1 r.next = 1 s.next = 1 yield delay(10) print("%d %d %d %d" % (p, q, r, s)) p.next = 2 q.next = 2 r.next = -2 s.next = -2 yield delay(10) print("%d %d %d %d" % (p, q, r, s)) p.next = 255 q.next = 246836311517 r.next = 255 s.next = -246836311517 yield delay(10) print("%d %d %d %d %d %d" % (p, q[40:20], q[20:0], r ,s[41:20], s[20:0])) p.next = 254 q.next = PBIGINT r.next = -256 s.next = NBIGINT yield delay(10) print("%d %d %d %d %d %d" % (p, q[40:20], q[20:0], r ,s[41:20], s[20:0])) return check def test_numass(): assert conversion.verify(NumassBench()) == 0 myhdl-0.11/myhdl/test/conversion/general/test_print.py000066400000000000000000000105061347432460400232240ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from myhdl import ConversionError from myhdl.conversion._misc import _error t_State = enum("START", "RUN", "STOP") def PrintBench(): si1 = Signal(intbv(0)[8:]) si2 = Signal(intbv(0, min=-10, max=12)) sb = Signal(bool(0)) @instance def logic(): i1 = intbv(0)[8:] i2 = intbv(0, min=-10, max=12) b = bool(1) state = t_State.START i1[:] = 10 si1.next = 11 i2[:] = -7 si2.next = -5 yield delay(10) print('') print(i1) print(i2) print("%d %d" % (i1, i2)) print(si1) print(si2) yield delay(10) print("This is a test") yield delay(10) print(int(b)) print(int(sb)) yield delay(10) print("i1 is %s" % i1) yield delay(10) print("i1 is %s, i2 is %s" % (i1, i2)) print("i1 %s i2 %s b %s si1 %s si2 %s" % (i1, i2, b, si1, si2)) print("i1 %d i2 %d b %d si1 %d si2 %d" % (i1, i2, b, si1, si2)) print(b) #print "%% %s" % i1 yield delay(10) print(state) print("the state is %s" % state) print("the state is %s" % (state,)) print("i1 is %s and the state is %s" % (i1, state)) # ord test yield delay(10) print(ord('y')) print(ord('2')) # signed yield delay(10) print(i1.signed()) print(i2.signed()) print(si1.signed()) print(si2.signed()) return logic def testPrint(): assert conversion.verify(PrintBench) == 0 def PrintLongVectorsBench(): N84 = 84 M84 = 2**N84-1 N85 = 85 M85 = 2**N85-1 N86 = 86 M86 = 2**N86-1 N87 = 87 M87 = 2**N87-1 si1 = Signal(intbv(0)[N87:]) si2 = Signal(intbv(0, min=-M85, max=M86)) @instance def logic(): i1 = intbv(0)[N85:] i2 = intbv(0, min=-M86, max=M85) si1.next = 0 si2.next = 0 yield delay(10) print("%s %s %s %s" % (i1, i2, si1, si2)) i1[:] = M84 i2[:] = -1 si1.next = M85 si2.next = -1 yield delay(10) print("%s %s %s %s" % (i1, i2, si1, si2)) i1[:] = 596854 i2[:] = -4954502 si1.next = 232434 si2.next = -3434355 yield delay(10) print("%s %s %s %s" % (i1, i2, si1, si2)) return logic def testPrintLongVectors(): assert conversion.verify(PrintLongVectorsBench) == 0 def testPrint(): assert conversion.verify(PrintBench) == 0 # format string errors and unsupported features def PrintError1(): @instance def logic(): i1 = intbv(12)[8:] yield delay(10) print("floating point %f end" % i1) return logic def testPrintError1(): try: conversion.verify(PrintError1) except ConversionError as e: assert e.kind == _error.UnsupportedFormatString else: assert False def PrintError2(): @instance def logic(): i1 = intbv(12)[8:] yield delay(10) print("begin %s %s end" % i1) return logic def testPrintError2(): try: conversion.verify(PrintError2) except ConversionError as e: assert e.kind == _error.FormatString else: assert False def PrintError3(): @instance def logic(): i1 = intbv(12)[8:] i2 = intbv(13)[8:] yield delay(10) print("begin %s end" % (i1, i2)) return logic def testPrintError3(): try: conversion.verify(PrintError3) except ConversionError as e: assert e.kind == _error.FormatString else: assert False def PrintError4(): @instance def logic(): i1 = intbv(12)[8:] yield delay(10) print("%10s" % i1) return logic def testPrintError4(): try: conversion.verify(PrintError4) except ConversionError as e: assert e.kind == _error.UnsupportedFormatString else: assert False def PrintError5(): @instance def logic(): i1 = intbv(12)[8:] yield delay(10) print("%-10s" % i1) return logic def testPrintError5(): try: conversion.verify(PrintError5) except ConversionError as e: assert e.kind == _error.UnsupportedFormatString else: assert False myhdl-0.11/myhdl/test/conversion/general/test_ram.py000066400000000000000000000063141347432460400226510ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path import unittest import myhdl from myhdl import * @block def ram1(dout, din, addr, we, clk, depth=128): """ Simple ram model """ @instance def logic(): mem = [intbv(0)[8:] for i in range(depth)] a = intbv(0)[8:] while 1: yield clk.posedge if we: ad = int(addr) mem[int(addr)][:] = din dout.next = mem[int(addr)] return logic @block def ram_clocked(dout, din, addr, we, clk, depth=128): """ Ram model """ mem = [Signal(intbv(0)[8:]) for i in range(depth)] @instance def access(): while 1: yield clk.posedge if we: mem[int(addr)].next = din dout.next = mem[int(addr)] return access @block def ram_deco1(dout, din, addr, we, clk, depth=128): """ Ram model """ mem = [Signal(intbv(0)[8:]) for i in range(depth)] @instance def write(): while True: yield clk.posedge if we: mem[int(addr)].next = din @always_comb def read(): dout.next = mem[int(addr)] return write, read @block def ram_deco2(dout, din, addr, we, clk, depth=128): """ Ram model """ mem = [Signal(intbv(0)[8:]) for i in range(depth)] @always(clk.posedge) def write(): if we: mem[int(addr)].next = din @always_comb def read(): dout.next = mem[int(addr)] return write, read @block def ram2(dout, din, addr, we, clk, depth=128): memL = [Signal(intbv()[len(dout):]) for i in range(depth)] @instance def wrLogic() : while 1: yield clk.posedge if we: memL[int(addr)].next = din @instance def rdLogic() : while 1: yield clk.posedge dout.next = memL[int(addr)] return wrLogic, rdLogic @block def RamBench(ram, depth=128): dout = Signal(intbv(0)[8:]) dout_v = Signal(intbv(0)[8:]) din = Signal(intbv(0)[8:]) addr = Signal(intbv(0)[7:]) we = Signal(bool(0)) clk = Signal(bool(0)) mem_inst = ram(dout, din, addr, we, clk, depth) @instance def stimulus(): for i in range(depth): yield clk.negedge din.next = i addr.next = i we.next = True yield clk.negedge we.next = False for i in range(depth): addr.next = i yield clk.posedge yield delay(1) assert dout == i print(dout) raise StopSimulation() @instance def clkgen(): clk.next = 1 while True: yield delay(10) clk.next = not clk return clkgen, stimulus, mem_inst def testram_deco1(): assert conversion.verify(RamBench(ram_deco1)) == 0 def testram_deco2(): assert conversion.verify(RamBench(ram_deco2)) == 0 def testram_clocked(): assert conversion.verify(RamBench(ram_clocked)) == 0 def test2(): assert conversion.verify(RamBench(ram2)) == 0 def test1(): assert conversion.verify(RamBench(ram1)) == 0 myhdl-0.11/myhdl/test/conversion/general/test_randscrambler.py000066400000000000000000000051101347432460400247020ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path import unittest from unittest import TestCase import random from random import randrange random.seed(2) import time import myhdl from myhdl import * from myhdl.conversion import verify N = 8 M = 2 ** N DEPTH = 5 @block def xor(z, a, b, c): @instance def logic(): while 1: yield a, b, c z.next = a ^ b ^ c return logic def randOthers(i, n): l = list(range(n)) l.remove(i) random.shuffle(l) return l[0], l[1] @block def randscrambler(ol, il, stage=0): """ Recursive hierarchy of random xor gates. An invented module to check hierarchy with toVerilog. """ sl1 = [Signal(bool()) for i in range(N)] sl2 = [Signal(bool()) for i in range(N)] i1 = [None] * N i2 = [None] * N if stage < DEPTH: for i in range(N): j, k = randOthers(i, N) i1[i] = xor(sl1[i], il[i], il[j], il[k]) rs = randscrambler(sl2, sl1, stage=stage+1) for i in range(N): j, k = randOthers(i, N) i2[i] = xor(ol[i], sl2[i], sl2[j], sl2[k]) return i1, i2, rs else: for i in range(N): j, k = randOthers(i, N) i1[i] = xor(ol[i], il[i], il[j], il[k]) return i1 @block def randscrambler_top(o7, o6, o5, o4, o3, o2, o1, o0, i7, i6, i5, i4, i3, i2, i1, i0): sl1 = [i7, i6, i5, i4, i3, i2, i1, i0] sl2 = [o7, o6, o5, o4, o3, o2, o1, o0] rs = randscrambler(sl2, sl1, stage=0) return rs o7, o6, o5, o4, o3, o2, o1, o0 = [Signal(bool()) for i in range(N)] i7, i6, i5, i4, i3, i2, i1, i0 = [Signal(bool()) for i in range(N)] v7, v6, v5, v4, v3, v2, v1, v0 = [Signal(bool()) for i in range(N)] @block def randscramblerBench(): @instance def stimulus(): a = modbv(0)[N:] z = intbv(0)[N:] for i in range(100): a[:] += 97 i7.next = a[7] i6.next = a[6] i5.next = a[5] i4.next = a[4] i3.next = a[3] i2.next = a[2] i1.next = a[1] i0.next = a[0] yield delay(10) z[7] = o7 z[6] = o6 z[5] = o5 z[4] = o4 z[3] = o3 z[2] = o2 z[1] = o1 z[0] = o0 print (a) print (z) rs = randscrambler_top( o7, o6, o5, o4, o3, o2, o1, o0, i7, i6, i5, i4, i3, i2, i1, i0 ) return rs, stimulus def test_randscramber(): assert conversion.verify(randscramblerBench()) == 0 myhdl-0.11/myhdl/test/conversion/general/test_rom.py000066400000000000000000000034351347432460400226700ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path from random import randrange import myhdl from myhdl import * D = 256 ROM = tuple([randrange(D) for i in range(D)]) @block def rom1(dout, addr, clk): @instance def rdLogic() : while 1: yield clk.posedge dout.next = ROM[int(addr)] return rdLogic @block def rom2(dout, addr, clk): theROM = ROM @instance def rdLogic() : while 1: yield clk.posedge dout.next = theROM[int(addr)] return rdLogic @block def rom3(dout, addr, clk): @instance def rdLogic() : tmp = intbv(0)[8:] while 1: yield addr tmp[:] = ROM[int(addr)] dout.next = tmp return rdLogic @block def rom4(dout, addr, clk): @always_comb def read(): dout.next = ROM[int(addr)] return read @block def RomBench(rom): dout = Signal(intbv(0)[8:]) addr = Signal(intbv(1)[8:]) clk = Signal(bool(0)) rom_inst = rom(dout, addr, clk) @instance def stimulus(): for i in range(D): addr.next = i yield clk.negedge yield clk.posedge yield delay(1) if __debug__: assert dout == ROM[i] print(dout) raise StopSimulation() @instance def clkgen(): clk.next = 1 while 1: yield delay(10) clk.next = not clk return clkgen, stimulus, rom_inst def test1(): assert conversion.verify(RomBench(rom1)) == 0 def test2(): assert conversion.verify(RomBench(rom2)) == 0 def test3(): assert conversion.verify(RomBench(rom3)) == 0 def test4(): assert conversion.verify(RomBench(rom4)) == 0 myhdl-0.11/myhdl/test/conversion/general/test_set_dir.py000066400000000000000000000062361347432460400235260ustar00rootroot00000000000000import os import myhdl from myhdl import * from tempfile import mkdtemp from shutil import rmtree import myhdl _version = myhdl.__version__.replace('.','') _shortversion = _version.replace('dev','') @block def simple_dir_model(din, dout, clk): """ Simple convertible model """ @always(clk.posedge) def register(): dout.next = din return register def test_toVHDL_set_dir(): '''In order that a developer can define where in the project hierarchy any generated VHDL files should be placed, it should be possible to set a directory attribute on toVHDL controlling this. ''' tmp_dir = mkdtemp() din = Signal(intbv(0)[5:]) dout = Signal(intbv(0)[5:]) clock = Signal(bool(0)) try: toVHDL.directory = tmp_dir toVHDL(simple_dir_model(din, dout, clock)) assert os.path.exists(os.path.join(tmp_dir, 'simple_dir_model.vhd')) finally: toVHDL.directory = None rmtree(tmp_dir) def test_toVHDL_myhdl_package_set_dir(): '''In order that the MyHDL package files are located in the same place as the generated VHDL files, when the directory attribute of toVHDL is set, this location should be used for the generated MyHDL package files. ''' tmp_dir = mkdtemp() din = Signal(intbv(0)[5:]) dout = Signal(intbv(0)[5:]) clock = Signal(bool(0)) try: toVHDL.directory = tmp_dir toVHDL(simple_dir_model(din, dout, clock)) assert os.path.exists( os.path.join(tmp_dir, "pck_myhdl_%s.vhd" % _shortversion)) finally: toVHDL.directory = None rmtree(tmp_dir) def test_toVerilog_set_dir(): '''In order that a developer can define where in the project hierarchy any generated Verilog files should be placed, it should be possible to set a directory attribute on toVerilog controlling this. ''' tmp_dir = mkdtemp() din = Signal(intbv(0)[5:]) dout = Signal(intbv(0)[5:]) clock = Signal(bool(0)) no_testbench_state = toVerilog.no_testbench toVerilog.no_testbench = True try: toVerilog.directory = tmp_dir toVerilog(simple_dir_model(din, dout, clock)) assert os.path.exists(os.path.join(tmp_dir, 'simple_dir_model.v')) finally: toVerilog.directory = None toVerilog.no_testbench = no_testbench_state rmtree(tmp_dir) def test_toVerilog_testbench_set_dir(): '''In order that generated Verilog test bench files are located in the same place as the Verilog files, when the directory attribute of toVerilog is set, this location should be used for the generated test bench files. ''' tmp_dir = mkdtemp() din = Signal(intbv(0)[5:]) dout = Signal(intbv(0)[5:]) clock = Signal(bool(0)) no_testbench_state = toVerilog.no_testbench toVerilog.no_testbench = False try: toVerilog.directory = tmp_dir toVerilog(simple_dir_model(din, dout, clock)) assert os.path.exists(os.path.join(tmp_dir, 'tb_simple_dir_model.v')) finally: toVerilog.directory = None toVerilog.no_testbench = no_testbench_state rmtree(tmp_dir) myhdl-0.11/myhdl/test/conversion/general/test_ternary.py000066400000000000000000000030621347432460400235530ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path import unittest import myhdl from myhdl import * @block def ternary1(dout, clk, rst): @always(clk.posedge, rst.negedge) def logic(): if rst == 0: dout.next = 0 else: dout.next = (dout + 1) if dout < 127 else 0 return logic @block def ternary2(dout, clk, rst): dout_d = Signal(intbv(0)[len(dout):]) @always(clk.posedge, rst.negedge) def logic(): if rst == 0: dout.next = 0 else: dout.next = dout_d @always_comb def comb(): dout_d.next = (dout + 1) if dout < 127 else 0 return logic, comb @block def TernaryBench(ternary): dout = Signal(intbv(0)[8:]) clk = Signal(bool(0)) rst = Signal(bool(0)) ternary_inst = ternary(dout, clk, rst) @instance def stimulus(): rst.next = 1 clk.next = 0 yield delay(10) rst.next = 0 yield delay(10) rst.next = 1 yield delay(10) for i in range(1000): clk.next = 1 yield delay(10) assert dout == (i + 1) % 128 print(dout) clk.next = 0 yield delay(10) raise StopSimulation() return stimulus, ternary_inst # uncomment when we have a VHDL-2008 compliant simulator def test_ternary1(): toVHDL.name = 'ternary1' assert conversion.verify(TernaryBench(ternary1)) == 0 def test_ternary2(): toVHDL.name = 'ternary2' assert conversion.verify(TernaryBench(ternary2)) == 0 myhdl-0.11/myhdl/test/conversion/general/test_toplevel_interfaces.py000066400000000000000000000077621347432460400261370ustar00rootroot00000000000000''' Created on 23 aug. 2018 @author: josy ''' from __future__ import print_function from myhdl import Signal, intbv, block, always_comb, always_seq, ResetSignal, instance, \ delay, StopSimulation # making up something sensible or even useful class EncoderUD(object): def __init__(self): self.up = Signal(bool(0)) self.down = Signal(bool(0)) self.zero = Signal(bool(0)) class TableXY(object): def __init__(self): self.x = EncoderUD() self.y = EncoderUD() class Cartesian2D(object): def __init__(self): self.x = Signal(intbv(0, -2 ** 15, 2 ** 15)) self.y = Signal(intbv(0, -2 ** 15, 2 ** 15)) @block def Encoder(Clk, Reset, Encoder, Position): lpos = Signal(intbv(0, -2 ** 15, 2 ** 15)) @always_seq(Clk.posedge, reset=Reset) def synch(): if Encoder.zero: lpos.next = 0 elif Encoder.up and not Encoder.down: if lpos < 2 ** 15: lpos.next = lpos + 1 elif not Encoder.up and Encoder.down: if lpos > -2 ** 15: lpos.next = lpos - 1 @always_comb def comb(): Position.next = lpos return synch, comb @block def XYTable(Clk, Reset, Table, Position): ''' Encoding the X,Y position of an XY Table using two Encoders Clk, Reset: as usual Table: an TableXY() object giving us the input Position: an Cartesian2D() object telling us the position ''' pos = Cartesian2D() tablex = Encoder(Clk, Reset, Table.x, pos.x) tablex.name = 'Table_X' tabley = Encoder(Clk, Reset, Table.y, pos.y) tabley.name = 'Table_Y' @always_comb def assign(): Position.x.next = pos.x Position.y.next = pos.y return tablex, tabley, assign def test_top_level_interfaces_analyze(): Clk = Signal(bool(0)) Reset = ResetSignal(0, 1, True) Table = TableXY() Position = Cartesian2D() dfc = XYTable(Clk, Reset, Table, Position) assert dfc.analyze_convert() == 0 @block def tb_top_level_interfaces(): Clk = Signal(bool(0)) Reset = ResetSignal(0, 1, False) Table = TableXY() Position = Cartesian2D() tb_dut = XYTable(Clk, Reset, Table, Position) xul = tuple([0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1]) xdl = tuple([0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1]) yul = tuple([0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1]) ydl = tuple([0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1]) tCK = 20 tReset = int(tCK * 3.5) @instance def tb_clk(): Clk.next = False yield delay(int(tCK // 2)) while True: Clk.next = not Clk yield delay(int(tCK // 2)) @instance def tb_stim(): Table.x.up.next = 0 Table.x.down.next = 0 Table.y.up.next = 0 Table.y.down.next = 0 Reset.next = 1 yield delay(tReset) Reset.next = 0 yield Clk.negedge for i in range(len(xul)): yield Clk.negedge Table.x.up.next = xul[i] Table.x.down.next = xdl[i] Table.y.up.next = yul[i] Table.y.down.next = ydl[i] yield Clk.posedge print("%d: %d %d" % (i, Position.x, Position.y)) yield Clk.posedge Table.x.zero.next = 1 Table.y.zero.next = 1 yield Clk.posedge Table.x.zero.next = 0 Table.y.zero.next = 0 yield Clk.posedge assert Position.x == 0 assert Position.y == 0 raise StopSimulation return tb_dut, tb_clk, tb_stim def test_top_level_interfaces_verify(): inst = tb_top_level_interfaces() assert inst.verify_convert() == 0 if __name__ == '__main__': Clk = Signal(bool(0)) Reset = ResetSignal(0, 1, True) Table = TableXY() Position = Cartesian2D() dft = tb_top_level_interfaces() dft.run_sim() dfc = XYTable(Clk, Reset, Table, Position) dfc.name = 'XYTable' dfc.convert('Verilog') dfc.convert('VHDL') myhdl-0.11/myhdl/test/conversion/general/test_toplevel_method.py000066400000000000000000000061341347432460400252640ustar00rootroot00000000000000from __future__ import absolute_import import sys import myhdl from myhdl import * from myhdl import ConversionError from myhdl.conversion._misc import _error class HdlObj(object): def __init__(self): pass @block def method_func(self, clk, srst, x, y): z = Signal(intbv(0, min=y.min, max=y.max)) ifx = self._mfunc(x, z) @always(clk.posedge) def hdl(): if srst: y.next = 0 else: y.next = x + z # x + (x+1) return hdl, ifx @block def _mfunc(self, x, y): @always_comb def _hdl(): y.next = x + 1 return _hdl @block def _func(x,y): @always_comb def _hdl(): y.next = x + 1 return _hdl class HdlObjObj(object): def __init__(self): pass @block def method_func(self, clk, srst, x, y): z1 = Signal(intbv(0, min=y.min, max=y.max)) z2 = Signal(intbv(0, min=y.min, max=y.max)) hobj = HdlObj() ifx1 = hobj._mfunc(x, z1) ifx2 = _func(x, z2) @always(clk.posedge) def hdl(): if srst: y.next = 0 else: y.next = x + z1 + (z1 - z2) return hdl, ifx1, ifx2 class HdlObjAttrSimple(object): def __init__(self): self.Constant = 3 @block def method_func(self, clk, srst, x, y): # limitation for class method conversion, the object attributes # can only be used/accessed during elaboration. Constant = int(self.Constant) @always(clk.posedge) def hdl(): if srst: y.next = 0 else: y.next = x + (x+1) + Constant - 3 return hdl class HdlObjNotSelf(object): def __init__(this): pass @block def method_func(this, clk, srst, x, y): @always(clk.posedge) def hdl(): if srst: y.next = 0 else: y.next = x + 1 return hdl def test_hdlobj(): clk = Signal(False) srst = Signal(False) x = Signal(intbv(0, min=0, max=16)) y = Signal(intbv(0, min=0, max=16)) hdlobj_inst = HdlObj() hdlobj_inst.method_func(clk, srst, x, y).analyze_convert() def test_hdlobjobj(): clk = Signal(False) srst = Signal(False) x = Signal(intbv(0, min=0, max=16)) y = Signal(intbv(0, min=0, max=16)) hdlobj_inst = HdlObjObj() hdlobj_inst.method_func(clk, srst, x, y).analyze_convert() def test_hdlobjattrsimple(): clk = Signal(False) srst = Signal(False) x = Signal(intbv(0, min=0, max=16)) y = Signal(intbv(0, min=0, max=16)) hdlobj_inst = HdlObjAttrSimple() hdlobj_inst.method_func(clk, x, srst, y).analyze_convert() def test_hdlobjnotself(): clk = Signal(False) srst = Signal(False) x = Signal(intbv(0, min=0, max=16)) y = Signal(intbv(0, min=0, max=16)) hdlobj_inst = HdlObjNotSelf() try: hdlobj_inst.method_func(clk, x, srst, y).analyze_convert() except ConversionError as e: assert e.kind == _error.NotSupported else: assert False myhdl-0.11/myhdl/test/conversion/toVHDL/000077500000000000000000000000001347432460400201405ustar00rootroot00000000000000myhdl-0.11/myhdl/test/conversion/toVHDL/Makefile000066400000000000000000000002331347432460400215760ustar00rootroot00000000000000all: vcom vcom: py.test --sim vcom ghdl: py.test --sim ghdl clean: - rm *.o *.out *.v *.vhd *.pyc *~ *.vcd* *.log *_ghdl gitclean: git clean -dfx myhdl-0.11/myhdl/test/conversion/toVHDL/README.txt000066400000000000000000000001651347432460400216400ustar00rootroot00000000000000VHDL-specific conversion tests ------------------------------ Requirements: * GHDL or vcom (default) * py.test myhdl-0.11/myhdl/test/conversion/toVHDL/__init__.py000066400000000000000000000000001347432460400222370ustar00rootroot00000000000000myhdl-0.11/myhdl/test/conversion/toVHDL/test_custom.py000066400000000000000000000162131347432460400230660ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path import random from random import randrange random.seed(2) import myhdl from myhdl import * from myhdl import ConversionError from myhdl.conversion._misc import _error ACTIVE_LOW, INACTIVE_HIGH = 0, 1 @block def incRef(count, enable, clock, reset, n): """ Incrementer with enable. count -- output enable -- control input, increment when 1 clock -- clock input reset -- asynchronous reset input n -- counter max value """ @instance def logic(): while 1: yield clock.posedge, reset.negedge if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = (count + 1) % n return logic @block def incGen(count, enable, clock, reset, n): """ Generator with vhdl_code is not permitted """ @instance def logic(): incGen.vhdl_code = "Template string" while 1: yield clock.posedge, reset.negedge if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = (count + 1) % n return logic @block def inc(count, enable, clock, reset, n): """ Incrementer with enable. count -- output enable -- control input, increment when 1 clock -- clock input reset -- asynchronous reset input n -- counter max value """ @always(clock.posedge, reset.negedge) def incProcess(): # make it fail in conversion import types if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = (count + 1) % n count.driven = "reg" inc.vhdl_code = \ """ process ($clock, $reset) begin if ($reset = '0') then $count <= (others => '0'); elsif rising_edge($clock) then if ($enable = '1') then $count <= ($count + 1) mod $n; end if; end if; end process; """ return incProcess @block def incErr(count, enable, clock, reset, n): @always(clock.posedge, reset.negedge) def incProcess(): # make it fail in conversion import types if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = (count + 1) % n count.driven = "reg" incErr.vhdl_code = \ """ always @(posedge $clock, negedge $reset) begin if ($reset == 0) begin $count <= 0; end else begin if ($enable) begin $count <= ($countq + 1) %% $n; end end end """ return incProcess @block def inc_comb(nextCount, count, n): @always_comb def logic(): # make if fail in conversion import types nextCount.next = (count + 1) % n nextCount.driven = "wire" inc_comb.vhdl_code =\ """ $nextCount <= ($count + 1) mod $n; """ return logic @block def inc_seq(count, nextCount, enable, clock, reset): @always(clock.posedge, reset.negedge) def logic(): # make if fail in conversion import types if reset == ACTIVE_LOW: count.next = 0 else: if (enable): count.next = nextCount count.driven = True inc_seq.vhdl_code = \ """ process ($clock, $reset) begin if ($reset = '0') then $count <= (others => '0'); elsif rising_edge($clock) then if ($enable = '1') then $count <= $nextCount; end if; end if; end process; """ return logic @block def inc2(count, enable, clock, reset, n): nextCount = Signal(intbv(0, min=0, max=n)) comb = inc_comb(nextCount, count, n) seq = inc_seq(count, nextCount, enable, clock, reset) return comb, seq @block def inc3(count, enable, clock, reset, n): inc2_inst = inc2(count, enable, clock, reset, n) return inc2_inst class ClassIncrementer(object): @block def inc(self, count, enable, clock, reset, n): """ Incrementer with enable. count -- output enable -- control input, increment when 1 clock -- clock input reset -- asynchronous reset input n -- counter max value """ @always(clock.posedge, reset.negedge) def incProcess(): # make it fail in conversion import types if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = (count + 1) % n count.driven = "reg" self.inc.vhdl_code = \ """ process ($clock, $reset) begin if ($reset = '0') then $count <= (others => '0'); elsif rising_edge($clock) then if ($enable = '1') then $count <= ($count + 1) mod $n; end if; end if; end process; """ return incProcess @block def clockGen(clock): @instance def logic(): clock.next = 1 while 1: yield delay(10) clock.next = not clock return logic NRTESTS = 1000 ENABLES = tuple([min(1, randrange(5)) for i in range(NRTESTS)]) @block def stimulus(enable, clock, reset): @instance def logic(): reset.next = INACTIVE_HIGH yield clock.negedge reset.next = ACTIVE_LOW yield clock.negedge reset.next = INACTIVE_HIGH for i in range(NRTESTS): enable.next = 1 yield clock.negedge for i in range(NRTESTS): enable.next = ENABLES[i] yield clock.negedge raise StopSimulation return logic @block def check(count, enable, clock, reset, n): @instance def logic(): expect = 0 yield reset.posedge # assert count == expect print(count) while 1: yield clock.posedge if enable: expect = (expect + 1) % n yield delay(1) # print "%d count %s expect %s count_v %s" % (now(), count, expect, count_v) # assert count == expect print(count) return logic @block def customBench(inc): m = 8 n = 2 ** m count = Signal(intbv(0)[m:]) enable = Signal(bool(0)) clock, reset = [Signal(bool(1)) for i in range(2)] inc_inst = inc(count, enable, clock, reset, n=n) clk_1 = clockGen(clock) st_1 = stimulus(enable, clock, reset) ch_1 = check(count, enable, clock, reset, n=n) return inc_inst, clk_1, st_1, ch_1 def testIncRef(): assert conversion.verify(customBench(incRef)) == 0 def testInc(): assert conversion.verify(customBench(inc)) == 0 def testInc2(): assert conversion.verify(customBench(inc2)) == 0 def testInc3(): assert conversion.verify(customBench(inc3)) == 0 def testIncGen(): try: assert conversion.verify(customBench(incGen)) == 0 except ConversionError as e: pass else: assert False def testIncErr(): try: assert conversion.verify(customBench(incErr)) == 0 except ConversionError as e: pass else: assert False def testMethodInc(): incrementer = ClassIncrementer() assert conversion.verify(customBench(incrementer.inc)) == 0 myhdl-0.11/myhdl/test/conversion/toVHDL/test_enum.py000066400000000000000000000027341347432460400225230ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from random import randrange bitwise_op = enum('BW_AND', 'BW_ANDN', 'BW_OR', 'BW_XOR') def bitwise(a, b, op): r = intbv(0)[8:] if op == bitwise_op.BW_AND: r[:] = a & b elif op == bitwise_op.BW_ANDN: r[:] = (~a) & b elif op == bitwise_op.BW_OR: r[:] = a | b elif op == bitwise_op.BW_XOR: r[:] = a ^ b return r def LogicUnit(a, b, c, op): @always_comb def operate(): c.next = bitwise(a,b,op) return operate def bench_enum(): clock = Signal(False) a, b, c = [Signal(intbv(0)[8:]) for i in range(3)] op = Signal(bitwise_op.BW_AND) logic_unit = LogicUnit(a=a, b=b, c=c, op=op) @instance def clockgen(): clock.next = 1 while 1: yield delay(10) clock.next = not clock @instance def stimulus(): a.next = 0xaa b.next = 0x55 yield clock.posedge print('a=%s b=%s' % (a, b)) op.next = bitwise_op.BW_AND yield clock.posedge print(c) op.next = bitwise_op.BW_ANDN yield clock.posedge print(c) op.next = bitwise_op.BW_OR yield clock.posedge print(c) op.next = bitwise_op.BW_XOR yield clock.posedge print(c) raise StopSimulation return instances() def test_enum(): assert conversion.verify(bench_enum) == 0 myhdl-0.11/myhdl/test/conversion/toVHDL/test_keywords.py000066400000000000000000000112661347432460400234260ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from myhdl import ToVHDLWarning import pytest import tempfile import shutil import sys import string import importlib import os from keyword import kwlist as python_kwlist import warnings _vhdl_keywords = ["abs", "access", "after", "alias", "all", "and", "architecture", "array", "assert", "attribute", "begin", "block", "body", "buffer", "bus", "case", "component", "configuration", "constant", "disconnect", "downto", "else", "elseif", "end", "entity", "exit", "file", "for", "function", "generate", "generic", "group", "guarded", "if", "impure", "in", "inertial", "inout", "is", "label", "library", "linkage", "literal", "loop", "map", "mod", "nand", "new", "next", "nor", "not", "null", "of", "on", "open", "or", "others", "out", "package", "port", "postponed", "procedure", "process", "pure", "range", "record", "register", "reject", "rem", "report", "return", "rol", "ror", "select", "severity", "signal", "shared", "sla", "sll", "sra", "srl", "subtype", "then", "to", "transport", "type", "unaffected", "units", "until", "use", "variable", "wait", "when", "while", "with", "xnor", "xor"]; keyword_code = """ from myhdl import * @block def invalid_import_keyword(input_sig, output_sig): ${keyword} = Signal(False) @always_comb def do_something(): ${keyword}.next = input_sig and input_sig @always_comb def something_else(): output_sig.next = ${keyword} return do_something, something_else """ @block def invalid_signal_underscore(input_sig, output_sig): _foo = Signal(bool(0)) @always_comb def do_something(): _foo.next = input_sig and input_sig @always_comb def something_else(): output_sig.next = _foo return do_something, something_else @block def invalid_function_underscore(clock, input_sig, output_sig): ttt = Signal(bool(0)) block1 = invalid_signal_underscore(input_sig, ttt) @always(clock.posedge) def do_something(): output_sig.next = ttt return block1, do_something @block def valid(input_sig, output_sig): @always_comb def do_something(): output_sig.next = input_sig return do_something def test_multiple_conversion(): sig_1 = Signal(True) sig_2 = Signal(True) a_block = valid(sig_1, sig_2) # conversions with keyword should fail with warnings.catch_warnings() as w: warnings.simplefilter('error') a_block.convert(hdl='VHDL') a_block.convert(hdl='VHDL') def test_invalid_keyword_name(): sig_1 = Signal(True) sig_2 = Signal(True) temp_directory = tempfile.mkdtemp() sys.path.append(temp_directory) keyword_template = string.Template(keyword_code) try: for keyword in _vhdl_keywords: if keyword in python_kwlist: continue fd, full_filename = tempfile.mkstemp( suffix='.py', dir=temp_directory) os.write(fd, keyword_template.substitute(keyword=keyword).encode('utf-8')) os.close(fd) module_name = os.path.basename(full_filename)[:-3] # chop off .py keyword_import = importlib.import_module(module_name) a_block = keyword_import.invalid_import_keyword(sig_1, sig_2) with pytest.warns(ToVHDLWarning): a_block.convert(hdl='VHDL') finally: sys.path.pop() shutil.rmtree(temp_directory) def test_invalid_signal_underscore_name(): sig_1 = Signal(True) sig_2 = Signal(True) a_block = invalid_signal_underscore(sig_1, sig_2) # Multiple conversions of a valid block should pass without warning with pytest.warns(ToVHDLWarning): a_block.convert(hdl='VHDL') def test_invalid_function_underscore_name(): sig_1 = Signal(True) sig_2 = Signal(True) clock = Signal(True) a_block = invalid_function_underscore(clock, sig_1, sig_2) # Multiple conversions of a valid block should pass without warning with pytest.warns(ToVHDLWarning): a_block.convert(hdl='VHDL') if __name__ == '__main__': sig_1 = Signal(True) sig_2 = Signal(True) a_block = invalid_signal_underscore(sig_1, sig_2) a_block.convert(hdl='VHDL') clock = Signal(True) a_block = invalid_function_underscore(clock, sig_1, sig_2) # Multiple conversions of a valid block should pass without warning a_block.convert(hdl='VHDL') myhdl-0.11/myhdl/test/conversion/toVHDL/test_loops.py000066400000000000000000000020551347432460400227070ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path from random import randrange import myhdl from myhdl import * from myhdl.conversion import verify, analyze from myhdl import ConversionError from myhdl.conversion._misc import _error def ForLoopError1(a, out): @instance def logic(): while 1: yield a var = 0 for i in range(1, 4, 3): if a[i] == 1: var += 1 out.next = var return logic def LoopBench(LoopTest): a = Signal(intbv(-1)[16:]) z = Signal(intbv(0)[16:]) looptest_inst = LoopTest(a, z) data = tuple([randrange(2**min(i, 16)) for i in range(100)]) @instance def stimulus(): for i in range(100): a.next = data[i] yield delay(10) print(z) return stimulus, looptest_inst def testForLoopError1(): try: analyze(LoopBench, ForLoopError1) except ConversionError as e: assert e.kind == _error.Requirement else: assert False myhdl-0.11/myhdl/test/conversion/toVHDL/test_newcustom.py000066400000000000000000000140521347432460400235770ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path import random from random import randrange random.seed(2) import myhdl from myhdl import * from myhdl import ConversionError from myhdl.conversion._misc import _error ACTIVE_LOW, INACTIVE_HIGH = 0, 1 def incRef(count, enable, clock, reset, n): """ Incrementer with enable. count -- output enable -- control input, increment when 1 clock -- clock input reset -- asynchronous reset input n -- counter max value """ @instance def logic(): while 1: yield clock.posedge, reset.negedge if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = (count + 1) % n return logic def incGen(count, enable, clock, reset, n): """ Generator with __vhdl__ is not permitted """ @instance def logic(): incGen.vhdl_code = "Template string" while 1: yield clock.posedge, reset.negedge if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = (count + 1) % n return logic def inc(count, enable, clock, reset, n): """ Incrementer with enable. count -- output enable -- control input, increment when 1 clock -- clock input reset -- asynchronous reset input n -- counter max value """ @always(clock.posedge, reset.negedge) def incProcess(): # make it fail in conversion import types if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = (count + 1) % n count.driven = "reg" inc.vhdl_code = \ """ process ($clock, $reset) begin if ($reset = '0') then $count <= (others => '0'); elsif rising_edge($clock) then if ($enable = '1') then $count <= ($count + 1) mod $n; end if; end if; end process; """ return incProcess def incErr(count, enable, clock, reset, n): @always(clock.posedge, reset.negedge) def incProcess(): # make it fail in conversion import types if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = (count + 1) % n count.driven = "reg" incErr.vhdl_code = \ """ always @(posedge $clock, negedge $reset) begin if ($reset == 0) begin $count <= 0; end else begin if ($enable) begin $count <= ($countq + 1) %% $n; end end end """ return incProcess def inc_comb(nextCount, count, n): @always_comb def logic(): # make if fail in conversion import types nextCount.next = (count + 1) % n nextCount.driven = "wire" inc_comb.vhdl_code =\ """ $nextCount <= ($count + 1) mod $n; """ return logic def inc_seq(count, nextCount, enable, clock, reset): @always(clock.posedge, reset.negedge) def logic(): if reset == ACTIVE_LOW: count.next = 0 else: if (enable): count.next = nextCount count.driven = True inc_seq.vhdl_code = \ """ process ($clock, $reset) begin if ($reset = '0') then $count <= (others => '0'); elsif rising_edge($clock) then if ($enable = '1') then $count <= $nextCount; end if; end if; end process; """ return logic def inc2(count, enable, clock, reset, n): nextCount = Signal(intbv(0, min=0, max=n)) comb = inc_comb(nextCount, count, n) seq = inc_seq(count, nextCount, enable, clock, reset) return comb, seq def inc3(count, enable, clock, reset, n): inc2_inst = inc2(count, enable, clock, reset, n) return inc2_inst def clockGen(clock): @instance def logic(): clock.next = 1 while 1: yield delay(10) clock.next = not clock return logic NRTESTS = 1000 ENABLES = tuple([min(1, randrange(5)) for i in range(NRTESTS)]) def stimulus(enable, clock, reset): @instance def logic(): reset.next = INACTIVE_HIGH yield clock.negedge reset.next = ACTIVE_LOW yield clock.negedge reset.next = INACTIVE_HIGH for i in range(NRTESTS): enable.next = 1 yield clock.negedge for i in range(NRTESTS): enable.next = ENABLES[i] yield clock.negedge raise StopSimulation return logic def check(count, enable, clock, reset, n): @instance def logic(): expect = 0 yield reset.posedge # assert count == expect print(count) while 1: yield clock.posedge if enable: expect = (expect + 1) % n yield delay(1) # print "%d count %s expect %s count_v %s" % (now(), count, expect, count_v) # assert count == expect print(count) return logic def customBench(inc): m = 8 n = 2 ** m count = Signal(intbv(0)[m:]) enable = Signal(bool(0)) clock, reset = [Signal(bool(1)) for i in range(2)] inc_inst = inc(count, enable, clock, reset, n=n) clk_1 = clockGen(clock) st_1 = stimulus(enable, clock, reset) ch_1 = check(count, enable, clock, reset, n=n) return inc_inst, clk_1, st_1, ch_1 def testIncRef(): assert conversion.verify(customBench, incRef) == 0 def testInc(): assert conversion.verify(customBench, inc) == 0 def testInc2(): assert conversion.verify(customBench, inc2) == 0 def testInc3(): assert conversion.verify(customBench, inc3) == 0 def testIncGen(): try: assert conversion.verify(customBench, incGen) == 0 except ConversionError as e: pass else: assert False def testIncErr(): try: assert conversion.verify(customBench, incErr) == 0 except ConversionError as e: pass else: assert False myhdl-0.11/myhdl/test/conversion/toVHDL/test_ops.py000066400000000000000000000301341347432460400223530ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path import random from random import randrange random.seed(2) import myhdl from myhdl import * from myhdl.conversion import verify NRTESTS = 10 def binaryOps( Bitand, Bitor, Bitxor, FloorDiv, LeftShift, Modulo, Mul, Pow, RightShift, Sub, Sum, EQ, NE, LT, GT, LE, GE, Booland, Boolor, left, right): @instance def logic(): while 1: yield left, right Bitand.next = left & right Bitor.next = left | right Bitxor.next = left ^ right FloorDiv.next = 0 if right != 0: FloorDiv.next = left // right ## if left < 256 and right < 40: LeftShift.next = 0 if left < 256 and right < 26: # fails in ghdl for > 26 LeftShift.next = left << right Modulo.next = 0 if right != 0: Modulo.next = left % right Mul.next = left * right # Icarus doesn't support ** yet #if left < 256 and right < 40: # Pow.next = left ** right ## Pow.next = 0 RightShift.next = left >> right Sub.next = 0 if left >= right: Sub.next = left - right Sum.next = left + right EQ.next = left == right NE.next = left != right LT.next = left < right GT.next = left > right LE.next = left <= right GE.next = left >= right Booland.next = bool(left) and bool(right) Boolor.next = bool(left) or bool(right) return logic def binaryBench(m, n): M = 2**m N = 2**n P = min(M, N) seqP = tuple(range(P)) seqM = tuple([randrange(M) for i in range(NRTESTS)]) seqN = tuple([randrange(N) for i in range(NRTESTS)]) left = Signal(intbv(0)[m:]) right = Signal(intbv(0)[n:]) Bitand = Signal(intbv(0)[max(m, n):]) Bitor = Signal(intbv(0)[max(m, n):]) Bitxor = Signal(intbv(0)[max(m, n):]) FloorDiv = Signal(intbv(0)[m:]) LeftShift = Signal(intbv(0)[64:]) Modulo = Signal(intbv(0)[m:]) Mul = Signal(intbv(0)[m+n:]) Pow = Signal(intbv(0)[64:]) RightShift = Signal(intbv(0)[m:]) Sub = Signal(intbv(0)[max(m, n):]) Sum = Signal(intbv(0)[max(m, n)+1:]) EQ, NE, LT, GT, LE, GE = [Signal(bool()) for i in range(6)] Booland, Boolor = [Signal(bool()) for i in range(2)] binops = binaryOps(Bitand, Bitor, Bitxor, FloorDiv, LeftShift, Modulo, Mul, Pow, RightShift, Sub, Sum, EQ, NE, LT, GT, LE, GE, Booland, Boolor, left, right) @instance def stimulus(): left.next = 1 right.next = 1 yield delay(10) left.next = 0 right.next = 0 yield delay(10) left.next = 0 right.next = N-1 yield delay(10) left.next = M-1 right.next = 0 yield delay(10) left.next = M-1 right.next = N-1 for i in range(len(seqP)): left.next = seqP[i] right.next = seqP[i] yield delay(10) for i in range(NRTESTS): left.next = seqM[i] right.next = seqN[i] yield delay(10) # raise StopSimulation @instance def check(): while True: yield left, right yield delay(1) print(Bitand) print(Bitor) print(Bitxor) print(FloorDiv) print(LeftShift) # print Pow, Pow_v print(Modulo) print(RightShift) print(Mul) print(Sub) print(Sum) print(int(EQ)) print(int(NE)) print(int(LT)) print(int(GT)) print(int(LE)) print(int(GE)) print(int(Booland)) print(int(Boolor)) return binops, stimulus, check def checkBinary(m, n): assert verify(binaryBench, m, n) == 0 def testBinary(): for m, n in ((4, 4,), (5, 3), (2, 6), (8, 7)): # for m, n in ((2, 6),): yield checkBinary, m, n def multiOps( Bitand, Bitor, Bitxor, Booland, Boolor, argm, argn, argp): @instance def logic(): while 1: yield argm, argn, argp Bitand.next = argm & argn & argp Bitor.next = argm | argn | argp Bitxor.next = argm ^ argn ^ argp Booland.next = bool(argm) and bool(argn) and bool(argp) Boolor.next = bool(argm) and bool(argn) and bool(argp) return logic def multiBench(m, n, p): M = 2**m N = 2**n P = 2**p Q = min(M, N, P) seqQ = tuple(range(1, Q)) seqM = tuple([randrange(M) for i in range(NRTESTS)]) seqN = tuple([randrange(N) for i in range(NRTESTS)]) seqP = tuple([randrange(P) for i in range(NRTESTS)]) argm = Signal(intbv(0)[m:]) argn = Signal(intbv(0)[n:]) argp = Signal(intbv(0)[p:]) Bitand = Signal(intbv(0)[max(m, n, p):]) Bitor = Signal(intbv(0)[max(m, n, p):]) Bitxor = Signal(intbv(0)[max(m, n, p):]) Booland, Boolor = [Signal(bool()) for i in range(2)] multiops = multiOps(Bitand, Bitor, Bitxor, Booland, Boolor, argm, argn, argp) @instance def stimulus(): for i in range(len(seqQ)): argm.next = seqQ[i] argn.next = seqQ[i] argp.next = seqQ[i] yield delay(10) for i in range(NRTESTS): argm.next = seqM[i] argn.next = seqN[i] argp.next = seqP[i] yield delay(10) ## for j, k, l in ((0, 0, 0), (0, 0, P-1), (0, N-1, P-1), ## (M-1, 0, 0), (M-1, 0, P-1), (M-1, N-1, 0), ## (0, N-1, 0), (M-1, N-1, P-1)): ## argm.next = j ## argn.next = k ## argp.next = l ## yield delay(10) @instance def check(): while 1: yield argm, argn, argp yield delay(1) print(Bitand) print(Bitor) print(Bitxor) print(int(Booland)) print(int(Boolor)) return multiops, stimulus, check def checkMultiOps(m, n, p): assert verify(multiBench, m, n, p) == 0 def testMultiOps(): for m, n, p in ((4, 4, 4,), (5, 3, 2), (3, 4, 6), (3, 7, 4)): yield checkMultiOps, m, n, p def unaryOps( Not_kw, Invert, UnaryAdd, UnarySub, arg): @instance def logic(): while 1: yield arg Not_kw.next = not arg Invert.next = ~arg # unary operators not supported ? #UnaryAdd.next = +arg # UnarySub.next = --arg return logic def unaryBench(m): M = 2**m seqM = tuple([randrange(M) for i in range(NRTESTS)]) arg = Signal(intbv(0)[m:]) Not_kw = Signal(bool(0)) Invert = Signal(intbv(0)[m:]) UnaryAdd = Signal(intbv(0)[m:]) UnarySub = Signal(intbv(0)[m:]) unaryops = unaryOps(Not_kw, Invert, UnaryAdd, UnarySub, arg) @instance def stimulus(): for i in range(NRTESTS): arg.next = seqM[i] yield delay(10) raise StopSimulation @instance def check(): while 1: yield arg yield delay(1) print(int(Not_kw)) print(Invert) # check unary operator support in vhdl # print UnaryAdd # print UnarySub return unaryops, stimulus, check def checkUnaryOps(m): assert verify(unaryBench, m) == 0 def testUnaryOps(): for m in (4, 7): yield checkUnaryOps, m def augmOps( Bitand, Bitor, Bitxor, FloorDiv, LeftShift, Modulo, Mul, RightShift, Sub, Sum, left, right): @instance def logic(): # var = intbv(0)[min(64, len(left) + len(right)):] var = intbv(0)[len(left) + len(right):] var2 = intbv(0)[64:] while True: yield left, right var[:] = left var &= right Bitand.next = var var[:] = left var |= right Bitor.next = var var[:] = left var ^= left Bitxor.next = var FloorDiv.next = 0 if right != 0: var[:] = left var //= right FloorDiv.next = var Sub.next = 0 if left >= right: var[:] = left var -= right Sub.next = var var[:] = left var += right Sum.next = var LeftShift.next = 0 if left < 256 and right < 26: var2[:] = left var2 <<= right LeftShift.next = var2 Modulo.next = 0 if right != 0: var[:] = left var %= right Modulo.next = var var[:] = left var *= right Mul.next = var var[:] = left var >>= right RightShift.next = var return logic def augmBench(m, n): M = 2**m N = 2**n seqM = tuple([randrange(M) for i in range(NRTESTS)]) seqN = tuple([randrange(N) for i in range(NRTESTS)]) left = Signal(intbv(0)[m:]) right = Signal(intbv(0)[n:]) Bitand = Signal(intbv(0)[max(m, n):]) Bitor = Signal(intbv(0)[max(m, n):]) Bitxor = Signal(intbv(0)[max(m, n):]) FloorDiv = Signal(intbv(0)[m:]) LeftShift = Signal(intbv(0)[64:]) Modulo = Signal(intbv(0)[m:]) Mul = Signal(intbv(0)[m+n:]) RightShift = Signal(intbv(0)[m:]) Sub = Signal(intbv(0)[max(m, n):]) Sum = Signal(intbv(0)[max(m, n)+1:]) augmops = augmOps( Bitand, Bitor, Bitxor, FloorDiv, LeftShift, Modulo, Mul, RightShift, Sub, Sum, left, right) @instance def stimulus(): left.next = 1 right.next = 1 yield delay(10) left.next = 0 right.next = 0 yield delay(10) left.next = 0 right.next = N-1 yield delay(10) left.next = M-1 right.next = 0 yield delay(10) left.next = M-1 right.next = N-1 for i in range(NRTESTS): left.next = seqM[i] right.next = seqN[i] yield delay(10) @instance def check(): while True: yield left, right yield delay(1) print(Bitand) print(Bitor) print(Bitxor) print(Sub) print(Sum) print(FloorDiv) print(LeftShift) print(Modulo) print(Mul) print(RightShift) return augmops, stimulus, check def checkAugmOps(m, n): assert verify(augmBench, m, n) == 0 def testAugmOps(): for m, n in ((4, 4,), (5, 3), (2, 6), (8, 7)): yield checkAugmOps, m, n myhdl-0.11/myhdl/test/conversion/toVHDL/test_signed.py000066400000000000000000000317051347432460400230300ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path import random from random import randrange import myhdl from myhdl import * from myhdl.conversion import verify NRTESTS = 10 def binaryOps( Bitand, ## Bitor, ## Bitxor, ## FloorDiv, LeftShift, Modulo, Mul, ## Pow, RightShift, Sub, Sum, Sum1, Sum2, Sum3, EQ, NE, LT, GT, LE, GE, BoolAnd, BoolOr, left, right, aBit): @instance def logic(): while 1: yield left, right, aBit ## Bitand.next = left & right ## Bitor.next = left | right ## Bitxor.next = left ^ right ## if right != 0: ## FloorDiv.next = left // right # Keep left shifts smaller than 2** 31 for VHDL's to_integer LeftShift.next = 0 if left < 256 and right < 22 and right >= 0: LeftShift.next = left << right ## if right != 0: ## Modulo.next = left % right Mul.next = left * right ## # Icarus doesn't support ** yet ## #if left < 256 and right < 22: ## # Pow.next = left ** right ## Pow.next = 0 ## if right >= -0: ## RightShift.next = left >> right ## RightShift.next = left Sub.next = left - right Sum.next = left + right Sum1.next = left + right[2:] Sum2.next = left + right[1] Sum3.next = left + aBit EQ.next = left == right NE.next = left != right LT.next = left < right GT.next = left > right LE.next = left <= right GE.next = left >= right BoolAnd.next = bool(left) and bool(right) BoolOr.next = bool(left) or bool(right) return logic def binaryBench(Ll, Ml, Lr, Mr): seqL = [] seqR = [] for i in range(NRTESTS): seqL.append(randrange(Ll, Ml)) seqR.append(randrange(Lr, Mr)) for j, k in ((Ll, Lr), (Ml-1, Mr-1), (Ll, Mr-1), (Ml-1, Lr)): seqL.append(j) seqR.append(k) seqL = tuple(seqL) seqR = tuple(seqR) aBit = Signal(bool(0)) left = Signal(intbv(Ll, min=Ll, max=Ml)) right = Signal(intbv(Lr, min=Lr, max=Mr)) M = 2**14 Bitand = Signal(intbv(0, min=-2**17, max=2**17)) ## Bitand_v = Signal(intbv(0, min=-2**17, max=2**17)) ## Bitor = Signal(intbv(0)[max(m, n):]) ## Bitor_v = Signal(intbv(0)[max(m, n):]) ## Bitxor = Signal(intbv(0)[max(m, n):]) ## Bitxor_v = Signal(intbv(0)[max(m, n):]) ## FloorDiv = Signal(intbv(0)[m:]) ## FloorDiv_v = Signal(intbv(0)[m:]) LeftShift = Signal(intbv(0, min=-2**64, max=2**64)) Modulo = Signal(intbv(0)[M:]) Mul = Signal(intbv(0, min=-2**17, max=2**17)) ## Pow = Signal(intbv(0)[64:]) RightShift = Signal(intbv(0, min=-M, max=M)) Sub, Sub1, Sub2, Sub3 = [Signal(intbv(min=-M, max=M)) for i in range(4)] Sum, Sum1, Sum2, Sum3 = [Signal(intbv(min=-M, max=M)) for i in range(4)] EQ, NE, LT, GT, LE, GE = [Signal(bool()) for i in range(6)] BoolAnd, BoolOr = [Signal(bool()) for i in range(2)] binops = binaryOps( Bitand, ## Bitor, ## Bitxor, ## FloorDiv, LeftShift, Modulo, Mul, ## Pow, RightShift, Sub, Sum, Sum1, Sum2, Sum3, EQ, NE, LT, GT, LE, GE, BoolAnd, BoolOr, left, right, aBit) @instance def stimulus(): for i in range(len(seqL)): left.next = seqL[i] right.next = seqR[i] yield delay(10) @instance def check(): while 1: yield left, right aBit.next = not aBit yield delay(1) #print "%s %s %s %s" % (left, right, Mul, Mul_v) #print "%s %s %s %s" % (left, right, bin(Mul), bin(Mul_v)) #print "%s %s %s %s" % (left, right, Sum, Sum_v) #print "%s %s %s %s" % (left, right, bin(Sum), bin(Sum_v)) ## print left ## print right ## print bin(left) ## print bin(right) ## print bin(Bitand) ## print bin(Bitand_v) ## print Bitand ## print Bitand_v ## self.assertEqual(Bitand, Bitand_v) #w = len(Bitand) #self.assertEqual(bin(Bitand, w), bin(Bitand_v,w )) ## self.assertEqual(Bitor, Bitor_v) ## self.assertEqual(Bitxor, Bitxor_v) ## ## self.assertEqual(FloorDiv, FloorDiv_v) print(LeftShift) # print Modulo print(Mul) # self.assertEqual(Pow, Pow_v) print(RightShift) print(Sub) print(Sum) print(Sum1) print(Sum2) print(Sum3) print(int(EQ)) print(int(NE)) print(int(LT)) print(int(GT)) print(int(LE)) print(int(GE)) print(int(BoolAnd)) print(int(BoolOr)) return binops, stimulus, check def checkBinaryOps( Ll, Ml, Lr, Mr): assert verify(binaryBench, Ll, Ml, Lr, Mr ) == 0 def testBinaryOps(): for Ll, Ml, Lr, Mr in ( (-254, 236, 0, 4), (-128, 128, -128, 128), (-53, 25, -23, 123), (-23, 145, -66, 12), (23, 34, -34, -16), (-54, -20, 45, 73), (-25, -12, -123, -66), ): yield checkBinaryOps, Ll, Ml, Lr, Mr def unaryOps( BoolNot, Invert, UnaryAdd, UnarySub, arg): @instance def logic(): while 1: yield arg # BoolNot.next = not arg Invert.next = ~arg # UnaryAdd.next = +arg UnarySub.next = --arg return logic def unaryBench( m): M = 2**m seqM = tuple([i for i in range(-M, M)]) arg = Signal(intbv(0, min=-M, max=+M)) BoolNot = Signal(bool(0)) Invert = Signal(intbv(0, min=-M, max=+M)) UnaryAdd = Signal(intbv(0, min=-M, max=+M)) UnarySub = Signal(intbv(0, min=-M, max=+M)) unaryops = unaryOps( BoolNot, Invert, UnaryAdd, UnarySub, arg) @instance def stimulus(): for i in range(len(seqM)): arg.next = seqM[i] yield delay(10) raise StopSimulation @instance def check(): while 1: yield arg yield delay(1) # print BoolNot print(Invert) # print UnaryAdd print(UnarySub) return unaryops, stimulus, check def checkUnaryOps(m): assert verify(unaryBench, m) == 0 def testUnaryOps(): for m in (4, 7): yield checkUnaryOps, m def augmOps( ## Bitand, ## Bitor, ## Bitxor, ## FloorDiv, LeftShift, ## Modulo, Mul, RightShift, Sub, Sum, left, right): M = 2**17 N = 2**64 @instance def logic(): var = intbv(0, min=-M, max=+M) var2 = intbv(0, min=-N, max=+N) while 1: yield left, right ## var[:] = left ## var &= right ## Bitand.next = var ## var[:] = left ## var |= right ## Bitor.next = var ## var[:] = left ## var ^= left ## Bitxor.next = var ## if right != 0: ## var[:] = left ## var //= right ## FloorDiv.next = var LeftShift.next = 0 if left < 256 and right < 22 and right >= 0: var2[:] = left var2 <<= right LeftShift.next = var2 ## if right != 0: ## var[:] = left ## var %= right ## Modulo.next = var var[:] = left var *= right Mul.next = var var[:] = left RightShift.next = 0 if right >= 0: var >>= right RightShift.next = var var[:] = left var -= right Sub.next = var var[:] = left var += right Sum.next = var return logic def augmBench( Ll, Ml, Lr, Mr): M = 2**17 seqL = [] seqR = [] for i in range(NRTESTS): seqL.append(randrange(Ll, Ml)) seqR.append(randrange(Lr, Mr)) for j, k in ((Ll, Lr), (Ml-1, Mr-1), (Ll, Mr-1), (Ml-1, Lr)): seqL.append(j) seqR.append(k) seqL = tuple(seqL) seqR = tuple(seqR) left = Signal(intbv(Ll, min=Ll, max=Ml)) right = Signal(intbv(Lr, min=Lr, max=Mr)) ## Bitand = Signal(intbv(0)[max(m, n):]) ## Bitor = Signal(intbv(0)[max(m, n):]) ## Bitxor = Signal(intbv(0)[max(m, n):]) ## FloorDiv = Signal(intbv(0)[m:]) LeftShift = Signal(intbv(0, min=-2**64, max=2**64)) ## Modulo = Signal(intbv(0)[m:]) Mul = Signal(intbv(0, min=-M, max=+M)) RightShift = Signal(intbv(0, min=-M, max=+M)) Sub = Signal(intbv(0, min=-M, max=+M)) Sum = Signal(intbv(0, min=-M, max=+M)) augmops = augmOps( ## Bitand, ## Bitor, ## Bitxor, ## FloorDiv, LeftShift, ## Modulo, Mul, RightShift, Sub, Sum, left, right) @instance def stimulus(): for i in range(len(seqL)): left.next = seqL[i] right.next = seqR[i] yield delay(10) @instance def check(): while 1: yield left, right yield delay(1) # print "%s %s %s %s" % (left, right, Or, Or_v) ## self.assertEqual(Bitand, Bitand_v) ## self.assertEqual(Bitor, Bitor_v) ## self.assertEqual(Bitxor, Bitxor_v) ## self.assertEqual(FloorDiv, FloorDiv_v) print(LeftShift) ## self.assertEqual(Modulo, Modulo_v) print(Mul) print(RightShift) print(Sub) print(Sum) return augmops, stimulus, check def checkAugmOps( Ll, Ml, Lr, Mr): assert verify(augmBench, Ll, Ml, Lr, Mr) == 0 def testAugmOps(): for Ll, Ml, Lr, Mr in ( (-254, 236, 0, 4), (-128, 128, -128, 128), (-53, 25, -23, 123), (-23, 145, -66, 12), (23, 34, -34, -16), (-54, -20, 45, 73), (-25, -12, -123, -66), ): yield checkAugmOps, Ll, Ml, Lr, Mr def expressions(a, b, clk): c = Signal(intbv(0, min=0, max=47)) e = Signal(bool()) @instance def logic(): d = intbv(0, min=-23, max=43) d[:] = -17 c.next = 5 yield clk.posedge a.next = c + 1 b.next = c + 1 yield clk.posedge a.next = c + -10 b.next = c + -1 yield clk.posedge a.next = c < -10 b.next = c < -1 yield clk.posedge a.next = d + c b.next = d >= c yield clk.posedge ## a.next = d & c ## b.next = c + (d & c) yield clk.posedge a.next = d + -c b.next = c + (-d) yield clk.posedge a.next = -d yield clk.posedge a.next = -c yield clk.posedge c.next = 46 yield clk.posedge a.next = ~d + 1 b.next = ~c + 1 yield clk.posedge a.next = ~c + 1 b.next = ~d + 1 yield clk.posedge raise StopSimulation return logic def expressionsBench(): a = Signal(intbv(0, min=-34, max=47)) b = Signal(intbv(0, min=0, max=47)) clk = Signal(bool()) expr = expressions(a, b, clk) @instance def check(): while 1: yield clk.posedge yield delay(1) print(int(a)) print(int(b)) @instance def clkgen(): while True: yield delay(10) clk.next = not clk return expr, check, clkgen def testExpressions(): assert verify(expressionsBench) == 0 myhdl-0.11/myhdl/test/conversion/toVerilog/000077500000000000000000000000001347432460400210125ustar00rootroot00000000000000myhdl-0.11/myhdl/test/conversion/toVerilog/Makefile000066400000000000000000000000761347432460400224550ustar00rootroot00000000000000all: py.test clean: - rm *.o *.out *.v *.pyc *~ *.vcd* \#* myhdl-0.11/myhdl/test/conversion/toVerilog/README.txt000066400000000000000000000005121347432460400225060ustar00rootroot00000000000000Original tests for conversion to Verilog ---------------------------------------- Requirements: * cver or icarus * co-simulation with the target simulator enabled icarus is setup by default. You can change that by going into util.py and using the cver definitions for the functions setupCosimulation and verilogCompile. myhdl-0.11/myhdl/test/conversion/toVerilog/__init__.py000066400000000000000000000000001347432460400231110ustar00rootroot00000000000000myhdl-0.11/myhdl/test/conversion/toVerilog/test_GrayInc.py000066400000000000000000000050171347432460400237620ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path import unittest from random import randrange import myhdl from myhdl import * from .test_bin2gray import bin2gray from .test_inc import inc from .util import setupCosimulation ACTIVE_LOW, INACTIVE_HIGH = 0, 1 def GrayInc(graycnt, enable, clock, reset, width): bincnt = Signal(intbv(0)[width:]) inc_1 = inc(bincnt, enable, clock, reset, n=2**width) bin2gray_1 = bin2gray(B=bincnt, G=graycnt, width=width) return inc_1, bin2gray_1 def GrayIncReg(graycnt, enable, clock, reset, width): graycnt_comb = Signal(intbv(0)[width:]) gray_inc_1 = GrayInc(graycnt_comb, enable, clock, reset, width) @always(clock.posedge) def reg_1(): graycnt.next = graycnt_comb return gray_inc_1, reg_1 width = 8 graycnt = Signal(intbv(0)[width:]) enable, clock, reset = [Signal(bool()) for i in range(3)] # GrayIncReg(graycnt, enable, clock, reset, width) def GrayIncReg_v(name, graycnt, enable, clock, reset, width): return setupCosimulation(**locals()) graycnt_v = Signal(intbv(0)[width:]) class TestGrayInc(unittest.TestCase): def clockGen(self): while 1: yield delay(10) clock.next = not clock def stimulus(self): reset.next = ACTIVE_LOW yield negedge(clock) reset.next = INACTIVE_HIGH for i in range(1000): enable.next = 1 yield clock.negedge for i in range(1000): enable.next = min(1, randrange(5)) yield clock.negedge raise StopSimulation def check(self): yield reset.posedge self.assertEqual(graycnt, graycnt_v) while 1: yield clock.posedge yield delay(1) # print "%d graycnt %s %s" % (now(), graycnt, graycnt_v) self.assertEqual(graycnt, graycnt_v) def bench(self): gray_inc_reg_1 = toVerilog(GrayIncReg, graycnt, enable, clock, reset, width) gray_inc_reg_v = GrayIncReg_v(GrayIncReg.__name__, graycnt_v, enable, clock, reset, width) clk_1 = self.clockGen() st_1 = self.stimulus() ch_1 = self.check() sim = Simulation(gray_inc_reg_1, gray_inc_reg_v, clk_1, st_1, ch_1) return sim def test(self): """ Check gray inc operation """ sim = self.bench() sim.run(quiet=1) if __name__ == '__main__': unittest.main() myhdl-0.11/myhdl/test/conversion/toVerilog/test_NotSupported.py000066400000000000000000000217511347432460400250770ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path import unittest import myhdl from myhdl import * from myhdl import ConversionError from myhdl.conversion._misc import _error class TestNotSupported(unittest.TestCase): def check(self, *args): try: i = toVerilog(*args) except ConversionError as e: self.assertEqual(e.kind, _error.NotSupported) except: self.fail() else: self.fail() def nocheck(self, *args): i = toVerilog(*args) def testAssList(self): a = Signal(bool()) z = Signal(bool()) def g(z, a): @instance def logic(): while 1: yield a z.next = 1 [p, q] = 1, 2 return logic self.check(g, z, a) def testAssTuple(self): a = Signal(bool()) z = Signal(bool()) def g(z, a): @instance def logic(): while 1: yield a z.next = 1 p, q = 1, 2 return logic self.check(g, z, a) def testClass(self): a = Signal(bool()) z = Signal(bool()) def g(z, a): @instance def logic(): while 1: yield a z.next = 1 class c: pass return logic self.check(g, z, a) def testDict(self): a = Signal(bool()) z = Signal(bool()) def g(z, a): @instance def logic(): while 1: yield a z.next = 1 d = {} return logic self.check(g, z, a) def testDiv(self): a = Signal(bool()) z = Signal(bool()) def g(z, a): @instance def logic(): while 1: yield a z.next = z / a return logic self.check(g, z, a) def testFrom(self): a = Signal(bool()) z = Signal(bool()) def g(z, a): @instance def logic(): while 1: yield a z.next = 1 from os import path return logic self.check(g, z, a) def testFunction(self): a = Signal(bool()) z = Signal(bool()) def g(z, a): @instance def logic(): while 1: yield a z.next = 1 def f(): pass return logic self.check(g, z, a) def testGlobal(self): a = Signal(bool()) z = Signal(bool()) def g(z, a): @instance def logic(): while 1: yield a z.next = 1 global e return logic self.check(g, z, a) def testImport(self): a = Signal(bool()) z = Signal(bool()) def g(z, a): @instance def logic(): while 1: yield a z.next = 1 import os return logic self.check(g, z, a) def testLambda(self): a = Signal(bool()) z = Signal(bool()) def g(z, a): @instance def logic(): while 1: yield a z.next = 1 lambda: 1 return logic self.check(g, z, a) def testListCompIf(self): a = Signal(bool()) z = Signal(bool()) def g(z, a): @instance def logic(): while 1: yield a z.next = 1 l = [i for i in range(5) if i > 1] return logic self.check(g, z, a) def testList(self): a = Signal(bool()) z = Signal(bool()) def g(z, a): @instance def logic(): while 1: yield a z.next = 1 l = [1, 2, 3] return logic self.check(g, z, a) ## def testPower(self): ## a = Signal(bool()) ## z = Signal(bool()) ## def g(z, a): ## while 1: ## yield a ## z.next = 2 ** 8 ## self.check(g, z, a) ## def testReturn(self): ## a = Signal(bool()) ## z = Signal(bool()) ## def g(z, a): ## while 1: ## yield a ## z.next = 1 ## return ## self.check(g, z, a) def testTryExcept(self): a = Signal(bool()) z = Signal(bool()) def g(z, a): @instance def logic(): while 1: yield a z.next = 1 try: pass except: pass return logic self.check(g, z, a) def testTryFinally(self): a = Signal(bool()) z = Signal(bool()) def g(z, a): @instance def logic(): while 1: yield a z.next = 1 try: pass finally: pass return logic self.check(g, z, a) def testChainedCompare(self): a, b, c = [Signal(bool()) for i in range(3)] z = Signal(bool()) def g(z, a, b, c): @instance def logic(): while 1: yield a, b, c z.next = a <= b < c return logic self.check(g, z, a, b, c) ## def testShortcutAnd(self): ## a, b = [Signal(bool()) for i in range(2)] ## z = Signal(bool()) ## def g(z, a, b): ## while 1: ## yield a ## if a: ## pass ## else: ## z.next = a and b ## self.check(g, z, a, b) ## def testShortcutOr(self): ## a, b, c = [Signal(bool()) for i in range(3)] ## z = Signal(bool()) ## def g(z, a, b): ## while 1: ## yield a ## if a: ## pass ## else: ## z.next = a < (b or c) ## self.check(g, z, a, b) def testNonBoolArgAnd(self): a = Signal(bool()) b = intbv(0)[2:] z = Signal(bool()) def g(z, a, b): @instance def logic(): while 1: yield a if a: pass else: z.next = a and b return logic self.check(g, z, a, b) def testNonBoolArgOr(self): a = Signal(bool()) b = intbv(0)[2:] c = Signal(bool()) z = Signal(bool()) def g(z, a, b): @instance def logic(): while 1: yield a if a: pass else: z.next = a < (b or c) return logic self.check(g, z, a, b) def testExtraArguments(self): a, b, c = [Signal(bool()) for i in range(3)] c = [1, 2] def g(a, *args): return a def f(a, b, c, *args): @instance def logic(): g(a, b) yield a return logic self.check(f, a, b, c) def testExtraPositionalArgsInCall(self): a, b, c = [Signal(bool()) for i in range(3)] c = [1] d = {'b':2} def h(b): return b def g(a): @instance def logic(): h(*c) yield a return logic def f(a, b, c): return g(a) x = self.check(f, a, b, c) def testExtraNamedArgsInCall(self): a, b, c = [Signal(bool()) for i in range(3)] c = [1] d = {'b':2} def h(b): return b def g(a): @instance def logic(): h(**d) yield a return logic def f(a, b, c): return g(a) x = self.check(f, a, b, c) class TestMisc(unittest.TestCase): def test(self): a, b, c = [Signal(bool()) for i in range(3)] c = [1] d = {'a':2} def h(b): return b def g(a): @instance def logic(): h(a) yield a return logic def f(a, b, c): return g(a) f(a, b, c) x = toVerilog(f, a, b, c) if __name__ == '__main__': unittest.main() myhdl-0.11/myhdl/test/conversion/toVerilog/test_RandomScrambler.py000066400000000000000000000072561347432460400255100ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path import unittest from unittest import TestCase import random from random import randrange random.seed(2) import time import myhdl from myhdl import * from .util import setupCosimulation N = 8 M = 2 ** N DEPTH = 5 @block def XorGate(z, a, b, c): @instance def logic(): while 1: yield a, b, c z.next = a ^ b ^ c return logic def randOthers(i, n): l = list(range(n)) l.remove(i) random.shuffle(l) return l[0], l[1] @block def RandomScramblerModule(ol, il, stage=0): """ Recursive hierarchy of random xor gates. An invented module to check hierarchy with toVerilog. """ sl1 = [Signal(bool()) for i in range(N)] sl2 = [Signal(bool()) for i in range(N)] i1 = [None] * N i2 = [None] * N if stage < DEPTH: for i in range(N): j, k = randOthers(i, N) i1[i] = XorGate(sl1[i], il[i], il[j], il[k]) rs = RandomScramblerModule(sl2, sl1, stage=stage+1) for i in range(N): j, k = randOthers(i, N) i2[i] = XorGate(ol[i], sl2[i], sl2[j], sl2[k]) return i1, i2, rs else: for i in range(N): j, k = randOthers(i, N) i1[i] = XorGate(ol[i], il[i], il[j], il[k]) return i1 @block def RandomScrambler(o7, o6, o5, o4, o3, o2, o1, o0, i7, i6, i5, i4, i3, i2, i1, i0): sl1 = [i7, i6, i5, i4, i3, i2, i1, i0] sl2 = [o7, o6, o5, o4, o3, o2, o1, o0] rs = RandomScramblerModule(sl2, sl1, stage=0) return rs o7, o6, o5, o4, o3, o2, o1, o0 = [Signal(bool()) for i in range(N)] i7, i6, i5, i4, i3, i2, i1, i0 = [Signal(bool()) for i in range(N)] v7, v6, v5, v4, v3, v2, v1, v0 = [Signal(bool()) for i in range(N)] def RandomScrambler_v(name, o7, o6, o5, o4, o3, o2, o1, o0, i7, i6, i5, i4, i3, i2, i1, i0): return setupCosimulation(**locals()) class TestRandomScrambler(TestCase): def stimulus(self): input = intbv(0) output = intbv(0) output_v = intbv(0) for i in range(100): # while 1: input[:] = randrange(M) i7.next = input[7] i6.next = input[6] i5.next = input[5] i4.next = input[4] i3.next = input[3] i2.next = input[2] i1.next = input[1] i0.next = input[0] yield delay(10) output[7] = o7 output[6] = o6 output[5] = o5 output[4] = o4 output[3] = o3 output[2] = o2 output[1] = o1 output[0] = o0 output_v[7] = o7 output_v[6] = o6 output_v[5] = o5 output_v[4] = o4 output_v[3] = o3 output_v[2] = o2 output_v[1] = o1 output_v[0] = o0 ## print output ## print output_v ## print input self.assertEqual(output, output_v) def test(self): rs = toVerilog(RandomScrambler( o7, o6, o5, o4, o3, o2, o1, o0, i7, i6, i5, i4, i3, i2, i1, i0 )) # time.sleep(1) rs_v = RandomScrambler_v(RandomScrambler.__name__, v7, v6, v5, v4, v3, v2, v1, v0, i7, i6, i5, i4, i3, i2, i1, i0 ) sim = Simulation(rs, self.stimulus(), rs_v) sim.run() if __name__ == '__main__': unittest.main() myhdl-0.11/myhdl/test/conversion/toVerilog/test_always_comb.py000066400000000000000000000075561347432460400247400ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run the unit tests for always_comb """ from __future__ import absolute_import import random from random import randrange # random.seed(3) # random, but deterministic import os from os import path import unittest from unittest import TestCase import myhdl from myhdl import * from .util import setupCosimulation QUIET = 1 def design1(a, b, c, d, p, q, r): def logic(): p.next = a | b return always_comb(logic) def design2(a, b, c, d, p, q, r): def logic(): p.next = a | b q.next = c & d r.next = a ^ c return always_comb(logic) def design3(a, b, c, d, p, q, r): def logic(): if a: p.next = c | b q.next = c & d r.next = d ^ c return always_comb(logic) def design4(a, b, c, d, p, q, r): def logic(): p.next = a | b q.next = c & d r.next = a ^ c q.next = c | d return always_comb(logic) def design5(a, b, c, d, p, q, r): def logic(): p.next = a | b q.next = c & d r.next = a ^ c q.next[0] = c | d return always_comb(logic) def design_v(name, a, b, c, d, p, q, r): return setupCosimulation(**locals()) class AlwaysCombSimulationTest(TestCase): def bench(self, design): clk = Signal(0) a = Signal(bool(0)) b = Signal(bool(0)) c = Signal(bool(0)) d = Signal(bool(0)) k = Signal(intbv(0)[8:]) p = Signal(bool(0)) q = Signal(intbv(0)[8:]) r = Signal(bool(0)) p_v = Signal(bool(0)) q_v = Signal(intbv(0)[8:]) r_v = Signal(bool(0)) vectors = [intbv(j) for i in range(50) for j in range(16)] random.shuffle(vectors) design_inst = toVerilog(design, a, b, c, d, p, q, r) design_v_inst = design_v(design.__name__, a, b, c, d, p_v, q_v, r_v) def clkGen(): while 1: yield delay(10) clk.next ^= 1 def stimulus(): for v in vectors: a.next = v[0] b.next = v[1] c.next = v[2] d.next = v[3] k.next = v yield clk.posedge yield clk.negedge # print p, q, r self.assertEqual(p, p_v) self.assertEqual(q, q_v) self.assertEqual(r, r_v) raise StopSimulation("always_comb simulation test") return design_inst, design_v_inst, clkGen(), stimulus() def test1(self): Simulation(self.bench(design1)).run(quiet=QUIET) def test2(self): Simulation(self.bench(design2)).run(quiet=QUIET) def test3(self): Simulation(self.bench(design3)).run(quiet=QUIET) def test4(self): Simulation(self.bench(design4)).run(quiet=QUIET) def test5(self): Simulation(self.bench(design5)).run(quiet=QUIET) if __name__ == "__main__": unittest.main() myhdl-0.11/myhdl/test/conversion/toVerilog/test_beh.py000066400000000000000000000055451347432460400231720ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path import unittest from unittest import TestCase import random from random import randrange random.seed(2) import myhdl from myhdl import * from .util import setupCosimulation ACTIVE_LOW, INACTIVE_HIGH = 0, 1 def behRef(count, enable, clock, reset, n): @instance def logic(): while 1: if reset == ACTIVE_LOW: yield reset.posedge for i in range(20): yield clock.posedge if enable: count.next = i j = 1 while j < 25: if enable: yield clock.posedge yield clock.posedge count.next = 2 * j j += 1 return logic objfile = "beh_inst.o" analyze_cmd = "iverilog -o %s beh_inst.v tb_beh_inst.v" % objfile simulate_cmd = "vvp -m ../../../cosimulation/icarus/myhdl.vpi %s" % objfile def beh_v(name, count, enable, clock, reset): return setupCosimulation(**locals()) class TestBeh(TestCase): def clockGen(self, clock): while 1: yield delay(10) clock.next = not clock def stimulus(self, enable, clock, reset): reset.next = INACTIVE_HIGH yield clock.negedge reset.next = ACTIVE_LOW yield clock.negedge reset.next = INACTIVE_HIGH for i in range(1000): enable.next = 1 yield clock.negedge for i in range(1000): enable.next = min(1, randrange(5)) yield clock.negedge raise StopSimulation def check(self, count, count_v, enable, clock, reset, n): yield reset.posedge self.assertEqual(count, count_v) while 1: yield clock.posedge yield delay(1) # print "%d count %s count_v %s" % (now(), count, count_v) self.assertEqual(count, count_v) def bench(self, beh): m = 8 n = 2 ** m count = Signal(intbv(0)[m:]) count_v = Signal(intbv(0)[m:]) enable = Signal(bool(0)) clock, reset = [Signal(bool()) for i in range(2)] beh_inst = toVerilog(beh, count, enable, clock, reset, n=n) # beh_inst = beh(count, enable, clock, reset, n=n) beh_inst_v = beh_v(beh.__name__, count_v, enable, clock, reset) clk_1 = self.clockGen(clock) st_1 = self.stimulus(enable, clock, reset) ch_1 = self.check(count, count_v, enable, clock, reset, n=n) sim = Simulation(beh_inst, beh_inst_v, clk_1, st_1, ch_1) # sim = Simulation(beh_inst, clk_1, st_1, ch_1) return sim def testBehRef(self): sim = self.bench(behRef) sim.run(quiet=1) if __name__ == '__main__': unittest.main() myhdl-0.11/myhdl/test/conversion/toVerilog/test_bin2gray.py000066400000000000000000000045341347432460400241460ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path import unittest from unittest import TestCase import myhdl from myhdl import * from .util import setupCosimulation def bin2gray2(B, G, width): """ Gray encoder. B -- input intbv signal, binary encoded G -- output intbv signal, gray encoded width -- bit width """ @instance def logic(): Bext = intbv(0)[width+1:] while 1: yield B Bext[:] = B for i in range(width): G.next[i] = Bext[i+1] ^ Bext[i] return logic def bin2gray(B, G, width): """ Gray encoder. B -- input intbv signal, binary encoded G -- output intbv signal, gray encoded width -- bit width """ @always_comb def logic(): Bext = intbv(0)[width+1:] Bext[:] = B for i in range(width): G.next[i] = Bext[i+1] ^ Bext[i] return logic objfile = "bin2gray.o" analyze_cmd = "iverilog -o %s bin2gray_inst.v tb_bin2gray_inst.v" % objfile simulate_cmd = "vvp -m ../../../cosimulation/icarus/myhdl.vpi %s" % objfile def bin2gray_v(B, G): if path.exists(objfile): os.remove(objfile) os.system(analyze_cmd) return Cosimulation(simulate_cmd, **locals()) def bin2gray_v(name, B, G): return setupCosimulation(**locals()) class TestBin2Gray(TestCase): def bench(self, width, bin2gray): B = Signal(intbv(0)[width:]) G = Signal(intbv(0)[width:]) G_v = Signal(intbv(0)[width:]) bin2gray_inst = toVerilog(bin2gray, B, G, width) # bin2gray_inst = bin2gray(B, G, width) bin2gray_v_inst = bin2gray_v(bin2gray.__name__, B, G_v) def stimulus(): for i in range(2**width): B.next = intbv(i) yield delay(10) #print "B: " + bin(B, width) + "| G_v: " + bin(G_v, width) #print bin(G, width) #print bin(G_v, width) self.assertEqual(G, G_v) return bin2gray_v_inst, stimulus(), bin2gray_inst def test1(self): sim = self.bench(width=8, bin2gray=bin2gray) Simulation(sim).run() def test2(self): sim = self.bench(width=8, bin2gray=bin2gray2) Simulation(sim).run() if __name__ == '__main__': unittest.main() myhdl-0.11/myhdl/test/conversion/toVerilog/test_bugreports.py000066400000000000000000000046351347432460400246270ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from .util import verilogCompile ############################# # bug report (Tom Dillon) # conflicts in reg/wire names ############################# width = 8 def add(x,a,b) : def logic() : x.next = a + b L0 = always_comb(logic) return L0 def add3(x,a,b,c) : x0 = Signal(intbv(0,min=-2**(width-1),max=2**(width-1))) A0 = add(x0,a,b) A1 = add(x,x0,c) return instances() def TestModule(x,a,b,c,d,e) : x0 = Signal(intbv(0,min=-2**(width-1),max=2**(width-1))) A0 = add3(x0,a,b,c) A1 = add3(x,x0,d,e) return instances() def test(): x,a,b,c,d,e = [Signal(intbv(0,min=-2**(width-1),max=2**(width-1))) for i in range(6)] toVerilog(TestModule, x,a,b,c,d,e) verilogCompile(TestModule.__name__) test() ############################## # Bug report (Tom Dillon) # Conflicts in reg/wire names ############################### def add(x,a,b) : def logic() : x.next = a + b L0 = always_comb(logic) return L0 def add4(x,a,b,c,d) : xL = [Signal(intbv(0,min=-2**(width+2),max=2**(width+2))) for i in range(2)] #xl0 = Signal(intbv(0,min=-2**(width+2),max=2**(width+2))) #xl1 = Signal(intbv(0,min=-2**(width+2),max=2**(width+2))) A0 = add(xL[0],a,b) A1 = add(xL[1],xL[0],c) A2 = add(x, xL[1],d) return instances() def TestModule(x,a,b,c,d,e): x0 = Signal(intbv(0,min=-2**(width+2),max=2**(width+2))) A0 = add4(x0,a,b,c,d) A1 = add4(x,x0,e,a,b) return instances() def test(): width = 8 x,a,b,c,d,e = [Signal(intbv(0,min=-2**(width-1),max=2**(width-1))) for i in range(6)] toVerilog(TestModule, x,a,b,c,d,e) verilogCompile(TestModule.__name__) test() ################################### # Bug report (George Pantazopoulos) # case variable name in embedded FSM #################################### from .test_fsm import FramerCtrl @block def mid(SOF, clk, reset_n): t_State = enum('SEARCH', 'CONFIRM', 'SYNC') syncFlag = Signal(bool(0)) state = Signal(t_State.SEARCH) fsm_1 = FramerCtrl(SOF, state, syncFlag, clk, reset_n, t_State) return fsm_1 @block def top(SOF, clk, reset_n): mid_1 = mid(SOF, clk, reset_n) return mid_1 def test(): clk = Signal(bool(0)) reset_n = Signal(bool(1)) SOF = Signal(bool(0)) top(SOF, clk, reset_n).convert() verilogCompile(top.__name__) test() myhdl-0.11/myhdl/test/conversion/toVerilog/test_custom.py000066400000000000000000000202751347432460400237430ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path import unittest from unittest import TestCase import random from random import randrange random.seed(2) import myhdl from myhdl import * from .util import setupCosimulation from myhdl import ConversionError from myhdl.conversion._misc import _error ACTIVE_LOW, INACTIVE_HIGH = 0, 1 @block def incRef(count, enable, clock, reset, n): """ Incrementer with enable. count -- output enable -- control input, increment when 1 clock -- clock input reset -- asynchronous reset input n -- counter max value """ @instance def logic(): while 1: yield clock.posedge, reset.negedge if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = (count + 1) % n return logic @block def incGen(count, enable, clock, reset, n): """ Generator with verilog_code is not permitted """ @instance def logic(): incGen.verilog_code = "Template string" while 1: yield clock.posedge, reset.negedge if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = (count + 1) % n return logic @block def inc(count, enable, clock, reset, n): """ Incrementer with enable. count -- output enable -- control input, increment when 1 clock -- clock input reset -- asynchronous reset input n -- counter max value """ @always(clock.posedge, reset.negedge) def incProcess(): # make it fail in conversion import types if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = (count + 1) % n count.driven = "reg" inc.verilog_code = \ """ always @(posedge $clock, negedge $reset) begin if (reset == 0) begin $count <= 0; end else begin if (enable) begin $count <= ($count + 1) % $n; end end end """ return incProcess @block def incErr(count, enable, clock, reset, n): @always(clock.posedge, reset.negedge) def incProcess(): # make it fail in conversion import types if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = (count + 1) % n count.driven = "reg" incErr.verilog_code = \ """ always @(posedge $clock, negedge $reset) begin if (reset == 0) begin $count <= 0; end else begin if (enable) begin $count <= ($countq + 1) % $n; end end end """ return incProcess @block def inc_comb(nextCount, count, n): @always_comb def logic(): # make if fail in conversion import types nextCount.next = (count + 1) % n nextCount.driven = "wire" inc_comb.verilog_code =\ """ assign $nextCount = ($count + 1) % $n; """ return logic @block def inc_seq(count, nextCount, enable, clock, reset): @always(clock.posedge, reset.negedge) def logic(): # make it fail in conversion import types if reset == ACTIVE_LOW: count.next = 0 else: if (enable): count.next = nextCount count.driven = "reg" inc_seq.verilog_code = \ """ always @(posedge $clock, negedge $reset) begin if (reset == 0) begin $count <= 0; end else begin if (enable) begin $count <= $nextCount; end end end """ return logic @block def inc2(count, enable, clock, reset, n): nextCount = Signal(intbv(0, min=0, max=n)) comb = inc_comb(nextCount, count, n) seq = inc_seq(count, nextCount, enable, clock, reset) return comb, seq @block def inc3(count, enable, clock, reset, n): inc2_inst = inc2(count, enable, clock, reset, n) return inc2_inst class ClassIncrementer(object): @block def inc(self, count, enable, clock, reset, n): """ Incrementer with enable. count -- output enable -- control input, increment when 1 clock -- clock input reset -- asynchronous reset input n -- counter max value """ @always(clock.posedge, reset.negedge) def incProcess(): # make it fail in conversion import types if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = (count + 1) % n count.driven = "reg" self.inc.verilog_code = \ """ always @(posedge $clock, negedge $reset) begin if (reset == 0) begin $count <= 0; end else begin if (enable) begin $count <= ($count + 1) % $n; end end end """ return incProcess def inc_v(name, count, enable, clock, reset): return setupCosimulation(**locals()) class TestInc(TestCase): def clockGen(self, clock): while 1: yield delay(10) clock.next = not clock def stimulus(self, enable, clock, reset): reset.next = INACTIVE_HIGH yield clock.negedge reset.next = ACTIVE_LOW yield clock.negedge reset.next = INACTIVE_HIGH for i in range(1000): enable.next = 1 yield clock.negedge for i in range(1000): enable.next = min(1, randrange(5)) yield clock.negedge raise StopSimulation def check(self, count, count_v, enable, clock, reset, n): expect = 0 yield reset.posedge self.assertEqual(count, expect) self.assertEqual(count, count_v) while 1: yield clock.posedge if enable: expect = (expect + 1) % n yield delay(1) # print "%d count %s expect %s count_v %s" % (now(), count, expect, count_v) self.assertEqual(count, expect) self.assertEqual(count, count_v) def bench(self, incRef, incVer): m = 8 n = 2 ** m count = Signal(intbv(0)[m:]) count_v = Signal(intbv(0)[m:]) enable = Signal(bool(0)) clock, reset = [Signal(bool()) for i in range(2)] inc_inst_ref = incRef(count, enable, clock, reset, n=n) inc_inst = toVerilog(incVer(count, enable, clock, reset, n=n)) # inc_inst = inc(count, enable, clock, reset, n=n) inc_inst_v = inc_v(incVer.__name__, count_v, enable, clock, reset) clk_1 = self.clockGen(clock) st_1 = self.stimulus(enable, clock, reset) ch_1 = self.check(count, count_v, enable, clock, reset, n=n) sim = Simulation(inc_inst_ref, inc_inst_v, clk_1, st_1, ch_1) return sim def testIncRefIncRef(self): """ Check increment operation """ sim = self.bench(incRef, incRef) sim.run(quiet=1) def testIncRefInc(self): sim = self.bench(incRef, inc) sim.run(quiet=1) def testIncInc(self): sim = self.bench(inc, inc) sim.run(quiet=1) def testIncRefInc2(self): sim = self.bench(incRef, inc2) sim.run(quiet=1) def testIncRefInc3(self): sim = self.bench(incRef, inc3) sim.run(quiet=1) def testIncGen(self): m = 8 n = 2 ** m count_v = Signal(intbv(0)[m:]) enable = Signal(bool(0)) clock, reset = [Signal(bool()) for i in range(2)] try: inc_inst = toVerilog(incGen(count_v, enable, clock, reset, n=n)) except ConversionError as e: self.assertEqual(e.kind, _error.NotSupported) else: self.fail() def testIncErr(self): m = 8 n = 2 ** m count_v = Signal(intbv(0)[m:]) enable = Signal(bool(0)) clock, reset = [Signal(bool()) for i in range(2)] try: inc_inst = toVerilog(incErr(count_v, enable, clock, reset, n=n)) except ConversionError as e: pass else: self.fail() def testMethodIncInc(self): incrementer = ClassIncrementer() sim = self.bench(incRef, incrementer.inc) sim.run(quiet=1) if __name__ == '__main__': unittest.main() myhdl-0.11/myhdl/test/conversion/toVerilog/test_dec.py000066400000000000000000000132661347432460400231660ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path import unittest from unittest import TestCase import random from random import randrange random.seed(2) import myhdl from myhdl import * from .util import setupCosimulation ACTIVE_LOW, INACTIVE_HIGH = 0, 1 def decRef(count, enable, clock, reset, n): """ Decrementer with enable. count -- output enable -- control input, decrement when 1 clock -- clock input reset -- asynchronous reset input n -- counter max value """ @instance def logic(): while 1: yield clock.posedge, reset.negedge if reset == ACTIVE_LOW: count.next = 0 else: if enable: if count == -n: count.next = n-1 else: count.next = count - 1 return logic def dec(count, enable, clock, reset, n): """ Decrementer with enable. count -- output enable -- control input, decrement when 1 clock -- clock input reset -- asynchronous reset input n -- counter max value """ @instance def decProcess(): while 1: yield clock.posedge, reset.negedge if reset == ACTIVE_LOW: count.next = 0 else: if enable: if count == -n: count.next = n-1 else: count.next = count - 1 return decProcess def decFunc(count, enable, clock, reset, n): def decFuncFunc(cnt): count_next = intbv(0, min=-n, max=n) if count == -n: count_next[:] = n-1 else: count_next[:] = cnt - 1 return count_next @always(clock.posedge, reset.negedge) def decFuncGen(): if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = decFuncFunc(count) return decFuncGen def decTask(count, enable, clock, reset, n): def decTaskFunc(cnt, enable, reset, n): if enable: if cnt == -n: cnt.next = n-1 else: cnt.next = cnt - 1 @instance def decTaskGen(): cnt = intbv(0, min=-n, max=n) while 1: yield clock.posedge, reset.negedge if reset == ACTIVE_LOW: cnt[:] = 0 count.next = 0 else: # print count decTaskFunc(cnt, enable, reset, n) count.next = cnt return decTaskGen def decTaskFreeVar(count, enable, clock, reset, n): def decTaskFunc(): if enable: if count == -n: count.next = n-1 else: count.next = count - 1 @instance def decTaskGen(): while 1: yield clock.posedge, reset.negedge if reset == ACTIVE_LOW: count.next = 0 else: # print count decTaskFunc() return decTaskGen def dec_v(name, count, enable, clock, reset): return setupCosimulation(**locals()) class TestDec(TestCase): def clockGen(self, clock): while 1: yield delay(10) clock.next = not clock def stimulus(self, enable, clock, reset): reset.next = INACTIVE_HIGH yield clock.negedge reset.next = ACTIVE_LOW yield clock.negedge reset.next = INACTIVE_HIGH for i in range(1000): enable.next = 1 yield clock.negedge for i in range(1000): enable.next = min(1, randrange(5)) yield clock.negedge raise StopSimulation def check(self, count, count_v, enable, clock, reset, n): expect = 0 yield reset.posedge self.assertEqual(count, expect) self.assertEqual(count, count_v) while 1: yield clock.posedge if enable: if expect == -n: expect = n-1 else: expect -= 1 yield delay(1) # print "%d count %s expect %s count_v %s" % (now(), count, expect, count_v) self.assertEqual(count, expect) self.assertEqual(count, count_v) def bench(self, dec): m = 8 n = 2 ** (m-1) count = Signal(intbv(0, min=-n, max=n)) count_v = Signal(intbv(0, min=-n, max=n)) enable = Signal(bool(0)) clock, reset = [Signal(bool()) for i in range(2)] dec_inst_ref = decRef(count, enable, clock, reset, n=n) dec_inst = toVerilog(dec, count, enable, clock, reset, n=n) # dec_inst = dec(count, enable, clock, reset, n=n) dec_inst_v = dec_v(dec.__name__, count_v, enable, clock, reset) clk_1 = self.clockGen(clock) st_1 = self.stimulus(enable, clock, reset) ch_1 = self.check(count, count_v, enable, clock, reset, n=n) sim = Simulation(dec_inst_ref, dec_inst_v, clk_1, st_1, ch_1) return sim def testDecRef(self): sim = self.bench(decRef) sim.run(quiet=1) def testDec(self): sim = self.bench(dec) sim.run(quiet=1) def testDecFunc(self): sim = self.bench(decFunc) sim.run(quiet=1) ## signed inout in task doesn't work yet in Icarus ## def testDecTask(self): ## sim = self.bench(decTask) ## sim.run(quiet=1) def testDecTaskFreeVar(self): sim = self.bench(decTaskFreeVar) sim.run(quiet=0) if __name__ == '__main__': unittest.main() myhdl-0.11/myhdl/test/conversion/toVerilog/test_edge.py000066400000000000000000000053371347432460400233370ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path import unittest from unittest import TestCase import random from random import randrange random.seed(2) import myhdl from myhdl import * from .util import setupCosimulation ACTIVE_LOW, INACTIVE_HIGH = 0, 1 def edge1(flag, sig, clock): sig_Z1 = Signal(bool(0)) @always(clock.posedge) def detect(): sig_Z1.next = sig flag.next = False if sig and not sig_Z1: flag.next = True return detect def edge2(flag, sig, clock): sig_Z1 = Signal(bool(0)) @always(clock.posedge) def detect(): sig_Z1.next = sig flag.next = sig and not sig_Z1 return detect def edge3(flag, sig, clock): @instance def detect(): sig_Z1 = False while True: yield clock.posedge flag.next = sig and not sig_Z1 sig_Z1 = sig.val return detect def edge4(flag, sig, clock): @instance def detect(): sig_Z1 = False while True: yield clock.posedge flag.next = sig and not sig_Z1 sig_Z1 = bool(sig) return detect def edge_v(name, flag, sig, clock): return setupCosimulation(**locals()) class TestEdge(TestCase): def bench(self, edge): clock = Signal(bool(0)) sig = Signal(bool(0)) flag = Signal(bool(0)) sig_Z1 = Signal(bool(0)) sig_Z2 = Signal(bool(0)) @always(delay(10)) def clockgen(): clock.next = not clock @instance def stimulus(): yield clock.negedge for i in range(100): sig.next = randrange(2) yield clock.negedge raise StopSimulation @always(clock.posedge) def delayline(): sig_Z1.next = sig sig_Z2.next = sig_Z1 @always(clock.negedge) def check(): expected = sig_Z1 and not sig_Z2 self.assertEqual(flag, expected) edge_inst = toVerilog(edge, flag, sig, clock) edge_inst_v = edge_v(edge.__name__, flag, sig, clock) return clockgen, stimulus, delayline, check, edge_inst_v def testEdge1(self): sim = Simulation(self.bench(edge1)) sim.run(quiet=1) def testEdge2(self): sim = Simulation(self.bench(edge2)) sim.run(quiet=1) def testEdge3(self): sim = Simulation(self.bench(edge3)) sim.run(quiet=1) def testEdge4(self): sim = Simulation(self.bench(edge4)) sim.run(quiet=1) if __name__ == '__main__': unittest.main() myhdl-0.11/myhdl/test/conversion/toVerilog/test_errors.py000066400000000000000000000325431347432460400237460ustar00rootroot00000000000000from __future__ import absolute_import from __future__ import print_function import os path = os.path import unittest from unittest import TestCase import random from random import randrange random.seed(2) import myhdl from myhdl import * from myhdl import ConversionError from myhdl.conversion._misc import _error ACTIVE_LOW, INACTIVE_HIGH = 0, 1 def freeVarTypeError(count, enable, clock, reset, n): cnt = intbv(0)[8:] def incTaskFunc(): if enable: cnt[:] = (cnt + 1) % n @instance def incTaskGen(): while 1: yield clock.posedge, reset.negedge if reset == ACTIVE_LOW: cnt[:]= 0 else: incTaskFunc() return incTaskGen def multipleDrivenSignal(count, enable, clock, reset, n): @instance def incTaskGen(): while 1: yield clock.posedge, reset.negedge if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = (count + 1) % n return incTaskGen, incTaskGen def shadowingSignal(count, enable, clock, reset, n): count = Signal(intbv(0)[8:]) @instance def incTaskGen(): while 1: yield clock.posedge, reset.negedge if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = (count + 1) % n return incTaskGen def internalSignal(count, enable, clock, reset, n): @instance def logic(): a = Signal(bool()) while 1: yield clock.posedge, reset.negedge if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = (count + 1) % n return logic def undefinedBitWidthSignal(count, enable, clock, reset, n): count = Signal(intbv(0)) @instance def incTaskGen(): while 1: yield clock.posedge, reset.negedge if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = (count + 1) % n return incTaskGen def yieldObject1(count, enable, clock, reset, n): @instance def logic(): while 1: yield clock.posedge, delay(5) if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = (count + 1) % n return logic def g1(clock): yield clock.posedge def g2(reset): yield reset.negedge def yieldObject2(count, enable, clock, reset, n): @instance def logic(): while 1: yield g1(clock), g2(reset) if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = (count + 1) % n return logic def f1(n): if n == 0: return 0 else: return f1(n-1) def f2(n): if n == 0: return 1 else: return f3(n-1) def f3(n): if n == 0: return 1 else: return f2(n-1) def recursion1(count, enable, clock, reset, n): @instance def logic(): while 1: yield clock.posedge, reset.negedge if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = f1(n) return logic def recursion2(count, enable, clock, reset, n): @instance def logic(): while 1: yield clock.posedge, reset.negedge if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = f2(n) return logic def h1(n): pass # return None def functionNoReturnVal(count, enable, clock, reset, n): @instance def logic(): while 1: yield clock.posedge, reset.negedge if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = h1(n) return logic def h2(cnt): cnt[:] = cnt + 1 return 1 def taskReturnVal(count, enable, clock, reset, n): @instance def logic(): cnt = intbv(0)[8:] while 1: yield clock.posedge, reset.negedge if reset == ACTIVE_LOW: count.next = 0 else: if enable: h2(cnt) count.next = count + 1 return logic def listComp1(count, enable, clock, reset, n): @instance def logic(): mem = [intbv(0)[8:] for i in range(4) for j in range(5)] while 1: yield clock.posedge, reset.negedge count.next = count + 1 return logic def listComp2(count, enable, clock, reset, n): @instance def logic(): mem = [intbv(0)[8:] for i in downrange(4)] while 1: yield clock.posedge, reset.negedge count.next = count + 1 return logic def listComp3(count, enable, clock, reset, n): @instance def logic(): mem = [intbv(0)[8:] for i in range(1, 4)] while 1: yield clock.posedge, reset.negedge count.next = count + 1 return logic def listComp4(count, enable, clock, reset, n): @instance def logic(): mem = [intbv(0) for i in range(4)] while 1: yield clock.posedge, reset.negedge count.next = count + 1 return logic def listComp5(count, enable, clock, reset, n): @instance def logic(): mem = [i for i in range(4)] while 1: yield clock.posedge, reset.negedge count.next = count + 1 return logic def undefinedBitWidthMem(count, enable, clock, reset, n): mem = [Signal(intbv(0)[8:]) for i in range(8)] mem[7] = Signal(intbv(0)) @instance def f(): while 1: yield clock.posedge, reset.negedge count.next = mem[0] + 1 return f def inconsistentTypeMem(count, enable, clock, reset, n): mem = [Signal(intbv(0)[8:]) for i in range(8)] mem[3] = Signal(bool()) @instance def f(): while 1: yield clock.posedge, reset.negedge count.next = mem[0] + 1 return f def inconsistentBitWidthMem(count, enable, clock, reset, n): mem = [Signal(intbv(0)[8:]) for i in range(8)] mem[4] = Signal(intbv(0)[7:]) @instance def f(): while 1: yield clock.posedge, reset.negedge count.next = mem[0] + 1 return f ## def listElementNotUnique(count, enable, clock, reset, n): ## mem = [Signal(intbv(0)[8:]) for i in range(8)] ## mem2 = mem[4:] ## def f(): ## while 1: ## yield clock.posedge, reset.negedge ## count.next = mem[0] + mem2[1] ## return f() class TestErr(TestCase): def clockGen(self, clock): while 1: yield delay(10) clock.next = not clock def stimulus(self, enable, clock, reset): reset.next = INACTIVE_HIGH yield clock.negedge reset.next = ACTIVE_LOW yield clock.negedge reset.next = INACTIVE_HIGH for i in range(1000): enable.next = 1 yield clock.negedge for i in range(1000): enable.next = min(1, randrange(5)) yield clock.negedge raise StopSimulation def check(self, count, count_v, enable, clock, reset, n): expect = 0 yield reset.posedge self.assertEqual(count, expect) self.assertEqual(count, count_v) while 1: yield clock.posedge if enable: expect = (expect + 1) % n yield delay(1) # print "%d count %s expect %s count_v %s" % (now(), count, expect, count_v) self.assertEqual(count, expect) self.assertEqual(count, count_v) def bench(self, err): m = 8 n = 2 ** m count = Signal(intbv(0)[m:]) count_v = Signal(intbv(0)[m:]) enable = Signal(bool(0)) clock, reset = [Signal(bool()) for i in range(2)] err_inst = toVerilog(err, count, enable, clock, reset, n=n) clk_1 = self.clockGen(clock) st_1 = self.stimulus(enable, clock, reset) ch_1 = self.check(count, count_v, enable, clock, reset, n=n) sim = Simulation(err_inst, clk_1, st_1, ch_1) return sim def testInternalSignal(self): try: self.bench(internalSignal) except ConversionError as e: self.assertEqual(e.kind, _error.TypeInfer) else: self.fail() def testMultipleDrivenSignal(self): try: self.bench(multipleDrivenSignal) except ConversionError as e: self.assertEqual(e.kind, _error.SigMultipleDriven) else: self.fail() def testShadowingSignal(self): try: self.bench(shadowingSignal) except ConversionError as e: self.assertEqual(e.kind, _error.ShadowingSignal) else: self.fail() def testUndefinedBitWidthSignal(self): try: self.bench(undefinedBitWidthSignal) except ConversionError as e: self.assertEqual(e.kind, _error.UndefinedBitWidth) else: self.fail() def testFreeVarTypeError(self): try: self.bench(freeVarTypeError) except ConversionError as e: self.assertEqual(e.kind, _error.FreeVarTypeError) else: self.fail() ## def testNegIntbv(self): ## try: ## self.bench(negIntbv) ## except ConversionError, e: ## self.assertEqual(e.kind, _error.IntbvSign) ## else: ## self.fail() def testYield1(self): try: self.bench(yieldObject1) except ConversionError as e: self.assertEqual(e.kind, _error.UnsupportedYield) else: self.fail() def testYield2(self): try: self.bench(yieldObject2) except ConversionError as e: self.assertEqual(e.kind, _error.NotSupported) else: self.fail() def testRecursion1(self): try: self.bench(recursion1) except ConversionError as e: self.assertEqual(e.kind, _error.NotSupported) else: self.fail() def testRecursion2(self): try: self.bench(recursion2) except ConversionError as e: self.assertEqual(e.kind, _error.NotSupported) else: self.fail() def testFunctionNoReturnVal(self): try: self.bench(functionNoReturnVal) except ConversionError as e: self.assertEqual(e.kind, _error.NotSupported) else: self.fail() def testTaskReturnVal(self): try: self.bench(taskReturnVal) except ConversionError as e: self.assertEqual(e.kind, _error.NotSupported) else: self.fail() def testListComp1(self): try: self.bench(listComp1) except ConversionError as e: self.assertEqual(e.kind, _error.NotSupported) else: self.fail() def testListComp2(self): try: self.bench(listComp2) except ConversionError as e: self.assertEqual(e.kind, _error.UnsupportedListComp) else: self.fail() def testListComp3(self): try: self.bench(listComp3) except ConversionError as e: self.assertEqual(e.kind, _error.UnsupportedListComp) else: self.fail() def testListComp4(self): try: self.bench(listComp4) except ConversionError as e: self.assertEqual(e.kind, _error.UnsupportedListComp) else: self.fail() def testListComp5(self): try: self.bench(listComp5) except ConversionError as e: self.assertEqual(e.kind, _error.UnsupportedListComp) else: self.fail() def testUndefinedBitWidthMem(self): try: self.bench(undefinedBitWidthMem) except ConversionError as e: self.assertEqual(e.kind, _error.UndefinedBitWidth) else: self.fail() def testInconsistentTypeMem(self): try: self.bench(inconsistentTypeMem) except ConversionError as e: self.assertEqual(e.kind, _error.InconsistentType) else: self.fail() def testInconsistentBitWidthMem(self): try: self.bench(inconsistentBitWidthMem) except ConversionError as e: self.assertEqual(e.kind, _error.InconsistentBitWidth) else: self.fail() ## def testListElementNotUnique(self): ## try: ## self.bench(listElementNotUnique) ## except ConversionError, e: ## self.assertEqual(e.kind, _error.ListElementNotUnique) ## else: ## self.fail() if __name__ == '__main__': unittest.main() myhdl-0.11/myhdl/test/conversion/toVerilog/test_fsm.py000066400000000000000000000156261347432460400232220ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path import unittest from unittest import TestCase import myhdl from myhdl import * from .util import setupCosimulation # SEARCH, CONFIRM, SYNC = range(3) ACTIVE_LOW = 0 FRAME_SIZE = 8 t_State_b = enum('SEARCH', 'CONFIRM', 'SYNC') t_State_oh = enum('SEARCH', 'CONFIRM', 'SYNC', encoding="one_hot") t_State_oc = enum('SEARCH', 'CONFIRM', 'SYNC', encoding="one_cold") @block def FramerCtrl(SOF, state, syncFlag, clk, reset_n, t_State): """ Framing control FSM. SOF -- start-of-frame output bit state -- FramerState output syncFlag -- sync pattern found indication input clk -- clock input reset_n -- active low reset """ index = Signal(intbv(0)[8:]) # position in frame @always(clk.posedge, reset_n.negedge) def FSM(): if reset_n == ACTIVE_LOW: SOF.next = 0 index.next = 0 state.next = t_State.SEARCH else: index.next = (index + 1) % FRAME_SIZE SOF.next = 0 if state == t_State.SEARCH: index.next = 1 if syncFlag: state.next = t_State.CONFIRM elif state == t_State.CONFIRM: if index == 0: if syncFlag: state.next = t_State.SYNC else: state.next = t_State.SEARCH elif state == t_State.SYNC: if index == 0: if not syncFlag: state.next = t_State.SEARCH SOF.next = (index == FRAME_SIZE-1) else: raise ValueError("Undefined state") return FSM @block def FramerCtrl_alt(SOF, state, syncFlag, clk, reset_n, t_State): """ Framing control FSM. SOF -- start-of-frame output bit state -- FramerState output syncFlag -- sync pattern found indication input clk -- clock input reset_n -- active low reset """ @instance def FSM(): index = intbv(0)[8:] # position in frame state_var = t_State.SEARCH while 1: yield clk.posedge, reset_n.negedge if reset_n == ACTIVE_LOW: SOF.next = 0 index[:] = 0 state_var = t_State.SEARCH state.next = t_State.SEARCH else: SOF_var = 0 if state == t_State.SEARCH: index[:] = 0 if syncFlag: state_var = t_State.CONFIRM elif state == t_State.CONFIRM: if index == 0: if syncFlag: state_var = t_State.SYNC else: state_var = t_State.SEARCH elif state == t_State.SYNC: if index == 0: if not syncFlag: state_var = t_State.SEARCH SOF_var = (index == FRAME_SIZE-1) else: raise ValueError("Undefined state") index[:]= (index + 1) % FRAME_SIZE SOF.next = SOF_var state.next = state_var return FSM @block def FramerCtrl_ref(SOF, state, syncFlag, clk, reset_n, t_State): """ Framing control FSM. SOF -- start-of-frame output bit state -- FramerState output syncFlag -- sync pattern found indication input clk -- clock input reset_n -- active low reset """ @instance def logic(): index = intbv(0, min=0, max=8) # position in frame while 1: yield clk.posedge, reset_n.negedge if reset_n == ACTIVE_LOW: SOF.next = 0 index[:] = 0 state.next = t_State.SEARCH else: SOF.next = 0 if state == t_State.SEARCH: index[:] = 0 if syncFlag: state.next = t_State.CONFIRM elif state == t_State.CONFIRM: if index == 0: if syncFlag: state.next = t_State.SYNC else: state.next = t_State.SEARCH elif state == t_State.SYNC: if index == 0: if not syncFlag: state.next = t_State.SEARCH SOF.next = (index == FRAME_SIZE-1) else: raise ValueError("Undefined state") index[:]= (index + 1) % FRAME_SIZE return logic @block def FramerCtrl_v(name, SOF, state, syncFlag, clk, reset_n): return setupCosimulation(**locals()) class FramerCtrlTest(TestCase): @block def bench(self, FramerCtrl, t_State): SOF = Signal(bool(0)) SOF_v = Signal(bool(0)) syncFlag = Signal(bool(0)) clk = Signal(bool(0)) reset_n = Signal(bool(1)) state = Signal(t_State.SEARCH) state_v = Signal(intbv(0)[8:]) framerctrl_ref_inst = FramerCtrl_ref(SOF, state, syncFlag, clk, reset_n, t_State) framerctrl_inst = FramerCtrl(SOF, state, syncFlag, clk, reset_n, t_State).convert() framerctrl_v_inst = FramerCtrl_v(FramerCtrl.__name__, SOF_v, state_v, syncFlag, clk, reset_n) @instance def clkgen(): reset_n.next = 1 yield delay(10) reset_n.next = 0 yield delay(10) reset_n.next = 1 yield delay(10) while 1: yield delay(10) clk.next = not clk @instance def stimulus(): for i in range(3): yield clk.posedge for n in (12, 8, 8, 4, 11, 8, 8, 7, 6, 8, 8): syncFlag.next = 1 yield clk.posedge syncFlag.next = 0 for i in range(n-1): yield clk.posedge raise StopSimulation @instance def check(): while 1: yield clk.negedge self.assertEqual(SOF, SOF_v) self.assertEqual(eval(hex(state)), eval(hex(state_v))) # print "MyHDL: %s %s" % (SOF, hex(state)) # print "Verilog: %s %s" % (SOF_v, hex(state_v)) return framerctrl_ref_inst, framerctrl_v_inst, clkgen, stimulus, check def testRef(self): for t_State in (t_State_b, t_State_oc, t_State_oh): tb_fsm = self.bench(FramerCtrl_ref, t_State) tb_fsm.run_sim() def testAlt(self): for t_State in (t_State_b, t_State_oc, t_State_oh): tb_fsm = self.bench(FramerCtrl_alt, t_State) tb_fsm.run_sim() def testDoc(self): tb_fsm = self.bench(FramerCtrl, t_State_oh) tb_fsm.run_sim() if __name__ == '__main__': unittest.main() myhdl-0.11/myhdl/test/conversion/toVerilog/test_hec.py000066400000000000000000000104611347432460400231640ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path import unittest from random import randrange import myhdl from myhdl import * from .util import setupCosimulation COSET = 0x55 def calculateHecRef(header): """ Return hec for an ATM header. Reference version. The hec polynomial is 1 + x + x**2 + x**8. """ hec = intbv(0) for bit in header[32:]: hec[8:] = concat(hec[7:2], bit ^ hec[1] ^ hec[7], bit ^ hec[0] ^ hec[7], bit ^ hec[7] ) return hec ^ COSET def calculateHecFunc(header): """ Return hec for an ATM header. Translatable version. The hec polynomial is 1 + x + x**2 + x**8. """ h = intbv(0)[8:] for i in downrange(len(header)): bit = header[i] h[:] = concat(h[7:2], bit ^ h[1] ^ h[7], bit ^ h[0] ^ h[7], bit ^ h[7] ) h ^= COSET return h def calculateHecTask(hec, header): """ Calculate hec for an ATM header. Translatable version. The hec polynomial is 1 + x + x**2 + x**8. """ h = intbv(0)[8:] for i in downrange(len(header)): bit = header[i] h[:] = concat(h[7:2], bit ^ h[1] ^ h[7], bit ^ h[0] ^ h[7], bit ^ h[7] ) h ^= COSET hec[:] = h def HecCalculatorPlain(hec, header): """ Hec calculation module. Plain version. """ @instance def logic(): h = intbv(0)[8:] while 1: yield header h[:] = 0 for i in downrange(len(header)): bit = header[i] h[:] = concat(h[7:2], bit ^ h[1] ^ h[7], bit ^ h[0] ^ h[7], bit ^ h[7] ) hec.next = h ^ COSET return logic def HecCalculatorFunc(hec, header=1): """ Hec calculation module. Version with function call. """ @instance def logic(): h = intbv(0)[8:] while 1: yield header hec.next = calculateHecFunc(header=header) return logic def HecCalculatorTask(hec, header): """ Hec calculation module. Version with task call. """ @instance def logic(): h = intbv(0)[8:] while 1: yield header calculateHecTask(h, header) hec.next = h return logic def HecCalculatorTask2(hec, header): """ Hec calculation module. Version with task call. """ @instance def logic(): h = intbv(0)[8:] while 1: yield header calculateHecTask(header=header, hec=h) hec.next = h return logic def HecCalculator_v(name, hec, header): return setupCosimulation(**locals()) headers = [ 0x00000000, 0x01234567, 0xbac6f4ca ] headers.extend([randrange(2**32-1) for i in range(10)]) class TestHec(unittest.TestCase): def bench(self, HecCalculator): hec = Signal(intbv(0)[8:]) hec_v = Signal(intbv(0)[8:]) header = Signal(intbv(-1)[32:]) heccalc_inst = toVerilog(HecCalculator, hec, header) # heccalc_inst = HecCalculator(hec, header) heccalc_v_inst = HecCalculator_v(HecCalculator.__name__, hec_v, header) def stimulus(): for h in headers: header.next = h yield delay(10) hec_ref = calculateHecRef(header) # print "hec: %s hec_v: %s" % (hex(hec), hex(hec_v)) self.assertEqual(hec, hec_ref) self.assertEqual(hec, hec_v) return stimulus(), heccalc_inst, heccalc_v_inst def testPlain(self): sim = self.bench(HecCalculatorPlain) Simulation(sim).run() def testFunc(self): sim = self.bench(HecCalculatorFunc) Simulation(sim).run() def testTask(self): sim = self.bench(HecCalculatorTask) Simulation(sim).run() def testTask2(self): sim = self.bench(HecCalculatorTask2) Simulation(sim).run() if __name__ == '__main__': unittest.main() myhdl-0.11/myhdl/test/conversion/toVerilog/test_inc.py000066400000000000000000000121371347432460400232000ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path import unittest from unittest import TestCase import random from random import randrange random.seed(2) import myhdl from myhdl import * from .util import setupCosimulation ACTIVE_LOW, INACTIVE_HIGH = 0, 1 def incRef(count, enable, clock, reset, n): """ Incrementer with enable. count -- output enable -- control input, increment when 1 clock -- clock input reset -- asynchronous reset input n -- counter max value """ @instance def logic(): while 1: yield clock.posedge, reset.negedge if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = (count + 1) % n return logic def inc(count, enable, clock, reset, n): """ Incrementer with enable. count -- output enable -- control input, increment when 1 clock -- clock input reset -- asynchronous reset input n -- counter max value """ @always(clock.posedge, reset.negedge) def incProcess(): if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = (count + 1) % n return incProcess def inc2(count, enable, clock, reset, n): @always(clock.posedge, reset.negedge) def incProcess(): if reset == ACTIVE_LOW: count.next = 0 else: if enable: if count == n-1: count.next = 0 else: count.next = count + 1 return incProcess def incTask(count, enable, clock, reset, n): def incTaskFunc(cnt, enable, reset, n): if enable: cnt[:] = (cnt + 1) % n @instance def incTaskGen(): cnt = intbv(0)[8:] while 1: yield clock.posedge, reset.negedge if reset == ACTIVE_LOW: cnt[:] = 0 count.next = 0 else: # print count incTaskFunc(cnt, enable, reset, n) count.next = cnt return incTaskGen def incTaskFreeVar(count, enable, clock, reset, n): def incTaskFunc(): if enable: count.next = (count + 1) % n @always(clock.posedge, reset.negedge) def incTaskGen(): if reset == ACTIVE_LOW: count.next = 0 else: # print count incTaskFunc() return incTaskGen def inc_v(name, count, enable, clock, reset): return setupCosimulation(**locals()) class TestInc(TestCase): def clockGen(self, clock): while 1: yield delay(10) clock.next = not clock def stimulus(self, enable, clock, reset): reset.next = INACTIVE_HIGH yield clock.negedge reset.next = ACTIVE_LOW yield clock.negedge reset.next = INACTIVE_HIGH for i in range(1000): enable.next = 1 yield clock.negedge for i in range(1000): enable.next = min(1, randrange(5)) yield clock.negedge raise StopSimulation def check(self, count, count_v, enable, clock, reset, n): expect = 0 yield reset.posedge self.assertEqual(count, expect) self.assertEqual(count, count_v) while 1: yield clock.posedge if enable: expect = (expect + 1) % n yield delay(1) # print "%d count %s expect %s count_v %s" % (now(), count, expect, count_v) self.assertEqual(count, expect) self.assertEqual(count, count_v) def bench(self, inc): m = 8 n = 2 ** m count = Signal(intbv(0)[m:]) count_v = Signal(intbv(0)[m:]) enable = Signal(bool(0)) clock, reset = [Signal(bool()) for i in range(2)] inc_inst_ref = incRef(count, enable, clock, reset, n=n) inc_inst = toVerilog(inc, count, enable, clock, reset, n=n) # inc_inst = inc(count, enable, clock, reset, n=n) inc_inst_v = inc_v(inc.__name__, count_v, enable, clock, reset) clk_1 = self.clockGen(clock) st_1 = self.stimulus(enable, clock, reset) ch_1 = self.check(count, count_v, enable, clock, reset, n=n) sim = Simulation(inc_inst_ref, inc_inst_v, clk_1, st_1, ch_1) return sim def testIncRef(self): """ Check increment operation """ sim = self.bench(incRef) sim.run(quiet=1) def testInc(self): """ Check increment operation """ sim = self.bench(inc) sim.run(quiet=1) def testInc2(self): """ Check increment operation """ sim = self.bench(inc2) sim.run(quiet=1) def testIncTask(self): sim = self.bench(incTask) sim.run(quiet=1) def testIncTaskFreeVar(self): sim = self.bench(incTaskFreeVar) sim.run(quiet=1) if __name__ == '__main__': unittest.main() myhdl-0.11/myhdl/test/conversion/toVerilog/test_inc_initial.py000066400000000000000000000061631347432460400247130ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path import unittest from unittest import TestCase import random from random import randrange random.seed(2) import myhdl from myhdl import * from .util import setupCosimulation ACTIVE_LOW, INACTIVE_HIGH = 0, 1 def inc_initial(count, enable, clock, reset, n): """ Incrementer with enable. count -- output enable -- control input, increment when 1 clock -- clock input reset -- asynchronous reset input n -- counter max value """ @instance def logic(): for i in range(100): yield clock.posedge, reset.negedge if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = (count + 1) % n raise StopSimulation return logic objfile = "inc_initial_1.o" analyze_cmd = "iverilog -o %s inc_initial_1.v tb_inc_initial_1.v" % objfile simulate_cmd = "vvp -m ../../../cosimulation/icarus/myhdl.vpi %s" % objfile def top(name, count, enable, clock, reset, n, arch="myhdl"): if arch == "verilog": return setupCosimulation(**locals()) if path.exists(objfile): os.remove(objfile) os.system(analyze_cmd) return Cosimulation(simulate_cmd, **locals()) else: inc_initial_inst = inc_initial(count, enable, clock, reset, n) return inc_initial_inst class TestInc_initial(TestCase): def clockGen(self, clock): while 1: yield delay(10) clock.next = not clock def stimulus(self, enable, clock, reset): reset.next = ACTIVE_LOW yield negedge(clock) reset.next = INACTIVE_HIGH for i in range(1000): enable.next = min(1, randrange(5)) yield negedge(clock) raise StopSimulation def check(self, count, count_v, enable, clock, reset, n): expect = 0 yield reset.posedge self.assertEqual(count, expect) self.assertEqual(count, count_v) while 1: yield clock.posedge if enable: expect = (expect + 1) % n yield delay(1) self.assertEqual(count, expect) self.assertEqual(count, count_v) def bench(self): m = 8 n = 2 ** m count = Signal(intbv(0)[m:]) count_v = Signal(intbv(0)[m:]) enable, clock, reset = [Signal(bool()) for i in range(3)] inc_initial_1 = toVerilog(top, top.__name__, count, enable, clock, reset, n=n) inc_initial_v = top(top.__name__, count_v, enable, clock, reset, n=n, arch='verilog') clk_1 = self.clockGen(clock) st_1 = self.stimulus(enable, clock, reset) ch_1 = self.check(count, count_v, enable, clock, reset, n=n) sim = Simulation(inc_initial_1, inc_initial_v, clk_1, st_1, ch_1) return sim def test(self): """ Check increment operation """ sim = self.bench() sim.run(quiet=1) if __name__ == '__main__': unittest.main() myhdl-0.11/myhdl/test/conversion/toVerilog/test_infer.py000066400000000000000000000156401347432460400235340ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path import unittest from random import randrange import myhdl from myhdl import * from myhdl import ConversionError from myhdl.conversion._misc import _error from .util import setupCosimulation b = c = 2 def UnboundError1(a, out): @instance def logic(): while 1: yield a out.next = a + b b = 1 return logic def UnboundError2(a, out): @instance def logic(): while 1: yield a if a == 1: c = 1 else: out.next = c return logic def UnboundError3(a, out): @instance def logic(): while 1: yield a out.next = a + d d = 1 return logic def UnboundError4(a, out): @instance def logic(): while 1: yield a if a == 1: e = 1 else: out.next = e return logic def InferError1(a, out): @instance def logic(): yield a b = 2 b = intbv(0)[5:] b[:] = 4 out.next = b return logic def InferError2(a, out): @instance def logic(): yield a c = intbv(0)[5:] c[:] = 4 c = intbv(0)[4:] c[:] = 4 out.next = c return logic enumType = enum("a", "b", "c") def InferError3(a, out): @instance def logic(): yield a d = enumType.a d = 4 out.next = b return logic def InferError4(a, out): @instance def logic(): h = intbv(0) yield a out.next = h return logic def InferError5Func(a): h = intbv(0)[5:] if a: return h else: return 1 def InferError5(a, out): @instance def logic(): yield a out.next = InferError5Func(a) return logic def InferError6Func(a): if a: return intbv(0) else: return intbv(1) def InferError6(a, out): @instance def logic(): yield a out.next = InferError6Func(a) return logic def InferError7Func(a): if a: return intbv(0)[5:] else: return intbv(0xff)[7:2] def InferError7(a, out): @instance def logic(): yield a out.next = InferError7Func(a) return logic class TestErrors(unittest.TestCase): def check(self, *args): try: i = toVerilog(*args) except ConversionError as e: self.assertEqual(e.kind, _error.NotSupported) except: self.fail() else: self.fail() def check(self, Infertest, err): a = Signal(intbv(-1)[16:]) out_v = Signal(intbv(0)[16:]) out = Signal(intbv(0)[16:]) try: infertest_inst = toVerilog(Infertest, a, out) except ConversionError as e: self.assertEqual(e.kind, err) except: self.fail() else: self.fail() def nocheck(self, Infertest, err=None): a = Signal(intbv(-1)[16:]) out_v = Signal(intbv(0)[16:]) out = Signal(intbv(0)[16:]) infertest_inst = toVerilog(Infertest, a, out) def testUnboundError1(self): sim = self.check(UnboundError1, _error.UnboundLocal) def testUnboundError2(self): sim = self.check(UnboundError2, _error.UnboundLocal) def testUnboundError3(self): sim = self.check(UnboundError3, _error.UnboundLocal) def testUnboundError4(self): sim = self.check(UnboundError4, _error.UnboundLocal) def testInferError1(self): sim = self.check(InferError1, _error.TypeMismatch) def testInferError2(self): sim = self.check(InferError2, _error.NrBitsMismatch) def testInferError3(self): sim = self.check(InferError3, _error.TypeMismatch) def testInferError4(self): sim = self.check(InferError4, _error.IntbvBitWidth) def testInferError5(self): sim = self.check(InferError5, _error.ReturnTypeMismatch) def testInferError6(self): sim = self.check(InferError6, _error.ReturnIntbvBitWidth) def testInferError7(self): sim = self.nocheck(InferError7, _error.ReturnIntbvBitWidth) def Infer1(a, out): @instance def logic(): while 1: yield a c = 5 c = a < 4 c = bool(0) c = False c = not a c = True out.next = c return logic def Infer2(a, out): @instance def logic(): while 1: yield a c = a < 4 c = bool(0) c = False c = not a c = True c = 5 out.next = c return logic def Infer3Func(a): if True: return a > 0 else: return 5 def Infer3(a, out): @instance def logic(): while 1: yield a out.next = Infer3Func(a) return logic def Infer4Func(a): while 1: if True: return 6 else: return a < 3 def Infer4(a, out): @instance def logic(): while 1: yield a out.next = Infer4Func(a) return logic def Infer5(a, out): @instance def logic(): while 1: yield a c = a + 1 c = a - 1 c = a * 3 c = a // 2 c = a << 2 c = a >> 2 c = a % 16 c = + a c = -( - a) c = ~(-3) c = not a c = 5 & 4 c = 5 | 2 c = 6 ^ 3 c = bool(a) and 1 out.next = c return logic def Infertest_v(name, a, out): return setupCosimulation(**locals()) class TestInfer(unittest.TestCase): def bench(self, Infertest): a = Signal(intbv()[16:]) out_v = Signal(intbv(0)[16:]) out = Signal(intbv(0)[16:]) infertest_inst = toVerilog(Infertest, a, out) # infertest_inst = Infertest(hec, header) infertest_v_inst = Infertest_v(Infertest.__name__, a, out_v) def stimulus(): a.next = 1 yield delay(10) # print "%s %s" % (out, out_v) self.assertEqual(out, out_v) raise StopSimulation return stimulus(), infertest_inst, infertest_v_inst def testInfer1(self): sim = self.bench(Infer1) Simulation(sim).run() def testInfer2(self): sim = self.bench(Infer2) Simulation(sim).run() def testInfer3(self): sim = self.bench(Infer3) Simulation(sim).run() def testInfer4(self): sim = self.bench(Infer4) Simulation(sim).run() def testInfer5(self): sim = self.bench(Infer5) Simulation(sim).run() if __name__ == '__main__': unittest.main() myhdl-0.11/myhdl/test/conversion/toVerilog/test_loops.py000066400000000000000000000203541347432460400235630ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path import unittest from random import randrange import myhdl from myhdl import * from .util import setupCosimulation def ForLoop1(a, out): @instance def logic(): while 1: yield a var = 0 for i in downrange(len(a)): if a[i] == 1: var += 1 out.next = var return logic def ForLoop2(a, out): @instance def logic(): while 1: yield a var = 0 for i in downrange(len(a), 5): if a[i] == 1: var += 1 out.next = var return logic def ForLoop3(a, out): @instance def logic(): while 1: yield a var = 0 for i in downrange(len(a), 3, 2): if a[i] == 1: var += 1 out.next = var return logic def ForLoop4(a, out): @instance def logic(): while 1: yield a var = 0 for i in range(len(a)): if a[i] == 1: var += 1 out.next = var return logic def ForLoop5(a, out): @instance def logic(): while 1: yield a var = 0 for i in range(6, len(a)): if a[i] == 1: var += 1 out.next = var return logic def ForLoop6(a, out): @instance def logic(): while 1: yield a var = 0 for i in range(5, len(a), 3): if a[i] == 1: var += 1 out.next = var return logic def ForContinueLoop(a, out): @instance def logic(): while 1: yield a var = 0 for i in downrange(len(a)): if a[i] == 0: continue var += 1 out.next = var return logic def ForBreakLoop(a, out): @instance def logic(): while 1: yield a out.next = 0 for i in downrange(len(a)): if a[i] == 1: out.next = i break return logic def ForBreakContinueLoop(a, out): @instance def logic(): while 1: yield a out.next = 0 for i in downrange(len(a)): if a[i] == 0: continue out.next = i break return logic def NestedForLoop1(a, out): @instance def logic(): while 1: yield a var = 0 for i in downrange(len(a)): if a[i] == 0: continue else: for j in downrange(i): if a[j] == 0: var +=1 break out.next = var return logic def NestedForLoop2(a, out): @instance def logic(): while 1: yield a var = 0 out.next = 0 for i in downrange(len(a)): if a[i] == 0: continue else: for j in downrange(i-1): if a[j] == 0: pass else: out.next = j break break return logic def ReturnFromFunction(a): for i in downrange(len(a)): if a[i] == 1: return i return 0 def FunctionCall(a, out): @instance def logic(): while 1: yield a out.next = ReturnFromFunction(a) return logic # During the following check, I noticed that non-blocking assignments # are not scheduled when a task is disabled in Icarus. Apparently # this is one of the many vague areas in the Verilog standard. def ReturnFromTask(a, out): for i in downrange(len(a)): if a[i] == 1: out[:] = i return out[:] = 23 # to notice it def TaskCall(a, out): @instance def logic(): var = intbv(0)[8:] while 1: yield a ReturnFromTask(a, var) out.next = var return logic def WhileLoop(a, out): @instance def logic(): while 1: yield a var = 0 i = len(a)-1 while i >= 0: if a[i] == 1: var += 1 i -= 1 out.next = var return logic def WhileContinueLoop(a, out): @instance def logic(): while 1: yield a var = 0 i = len(a)-1 while i >= 0: if a[i] == 0: i -= 1 continue var += 1 i -= 1 out.next = var return logic def WhileBreakLoop(a, out): @instance def logic(): while 1: yield a var = 0 i = len(a)-1 out.next = 0 while i >= 0: if a[i] == 1: out.next = i break i -= 1 return logic def WhileBreakContinueLoop(a, out): @instance def logic(): while 1: yield a var = 0 i = len(a)-1 out.next = 0 while i >= 0: if a[i] == 0: i -= 1 continue out.next = i break return logic def LoopTest_v(name, a, out): return setupCosimulation(**locals()) class TestLoops(unittest.TestCase): def bench(self, LoopTest): a = Signal(intbv(-1)[16:]) out_v = Signal(intbv(0)[16:]) out = Signal(intbv(0)[16:]) looptest_inst = toVerilog(LoopTest, a, out) # looptest_inst = LoopTest(hec, header) looptest_v_inst = LoopTest_v(LoopTest.__name__, a, out_v) def stimulus(): for i in range(100): a.next = randrange(2**min(i, 16)) yield delay(10) # print "%s %s" % (out, out_v) self.assertEqual(out, out_v) return stimulus(), looptest_inst, looptest_v_inst def testForLoop1(self): sim = self.bench(ForLoop1) Simulation(sim).run() def testForLoop2(self): sim = self.bench(ForLoop2) Simulation(sim).run() def testForLoop3(self): sim = self.bench(ForLoop3) Simulation(sim).run() def testForLoop4(self): sim = self.bench(ForLoop4) Simulation(sim).run() def testForLoop5(self): sim = self.bench(ForLoop5) Simulation(sim).run() def testForLoop6(self): sim = self.bench(ForLoop6) Simulation(sim).run() def testForContinueLoop(self): sim = self.bench(ForContinueLoop) Simulation(sim).run() def testForBreakLoop(self): sim = self.bench(ForBreakLoop) Simulation(sim).run() def testForBreakContinueLoop(self): sim = self.bench(ForBreakContinueLoop) Simulation(sim).run() def testNestedForLoop1(self): sim = self.bench(NestedForLoop1) Simulation(sim).run() def testNestedForLoop2(self): sim = self.bench(NestedForLoop2) Simulation(sim).run() def testNestedForLoop2(self): sim = self.bench(NestedForLoop2) Simulation(sim).run() def testFunctionCall(self): sim = self.bench(FunctionCall) Simulation(sim).run() def testTaskCall(self): sim = self.bench(TaskCall) Simulation(sim).run() def testWhileLoop(self): sim = self.bench(WhileLoop) Simulation(sim).run() def testWhileContinueLoop(self): sim = self.bench(WhileContinueLoop) Simulation(sim).run() def testWhileBreakLoop(self): sim = self.bench(WhileBreakLoop) Simulation(sim).run() def testWhileBreakContinueLoop(self): sim = self.bench(WhileBreakContinueLoop) Simulation(sim).run() if __name__ == '__main__': unittest.main() myhdl-0.11/myhdl/test/conversion/toVerilog/test_misc.py000066400000000000000000000073061347432460400233640ustar00rootroot00000000000000from __future__ import absolute_import import unittest import os path = os.path from random import randrange import myhdl from myhdl import * from .util import setupCosimulation ### test of constant wire support ### # example from Frank Palazollo def or_gate(a,b,c): @instance def logic(): while 1: c.next = a | b yield a, b return logic def my_bundle(p,q): r = Signal(bool(0)) gen_or = or_gate(p,r,q) return instances() # additional level of hierarchy def ConstWire2(p, q): r = Signal(bool(1)) s = Signal(bool(1)) inst1 = my_bundle(p, r) inst2 = or_gate(r, s, q) return inst1, inst2 def adder(a, b, c): @instance def logic(): while 1: yield a, b c.next = a + b return logic def ConstWire3(p, q): t = Signal(intbv(17)[5:]) adder_inst = adder(p, t, q) return instances() def ConstWire_v(name, p, q): return setupCosimulation(**locals()) class TestConstWires(unittest.TestCase): def benchBool(self, ConstWire): p = Signal(bool(0)) q = Signal(bool(0)) q_v = Signal(bool(0)) constwire_inst = toVerilog(ConstWire, p, q) constwire_v_inst = ConstWire_v(ConstWire.__name__, p, q_v) def stimulus(): for i in range(100): p.next = randrange(2) yield delay(10) self.assertEqual(q, q_v) return stimulus(), constwire_inst, constwire_v_inst def testConstWire1(self): sim = self.benchBool(my_bundle) Simulation(sim).run() def testConstWire2(self): sim = self.benchBool(ConstWire2) Simulation(sim).run() def benchIntbv(self, ConstWire): p = Signal(intbv(0)[8:]) q = Signal(intbv(0)[8:]) q_v = Signal(intbv(0)[8:]) constwire_inst = toVerilog(ConstWire, p, q) constwire_v_inst = ConstWire_v(ConstWire.__name__, p, q_v) def stimulus(): for i in range(100): p.next = i yield delay(10) self.assertEqual(q, q_v) return stimulus(), constwire_inst, constwire_v_inst def testConstWire3(self): sim = self.benchIntbv(ConstWire3) Simulation(sim).run() ### tests of code ignore facility during translation ### def adderRef(a, b, c): @instance def logic(): while 1: yield a, b c.next = a + b return logic def adderDebug(a, b, c): @instance def logic(): while 1: yield a, b if __debug__: import string c.next = a + b return logic def Ignorecode_v(name, a, b, c): return setupCosimulation(**locals()) class TestIgnoreCode(unittest.TestCase): def bench(self, adder): a = Signal(intbv(0)[8:]) b = Signal(intbv(0)[8:]) c = Signal(intbv(0)[9:]) c_v = Signal(intbv(0)[9:]) ignorecode_inst = toVerilog(adder, a, b, c) # ignorecode_inst = adder(a, b, c) ignorecode_v_inst = Ignorecode_v(adder.__name__, a, b, c_v) def stimulus(): for i in range(100): a.next = randrange(2**8) b.next = randrange(2**8) yield delay(10) self.assertEqual(c, c_v) return stimulus(), ignorecode_inst, ignorecode_v_inst def testAdderRef(self): sim = self.bench(adderRef) Simulation(sim).run() def testAdderDebug(self): sim = self.bench(adderDebug) Simulation(sim).run() if __name__ == '__main__': unittest.main() myhdl-0.11/myhdl/test/conversion/toVerilog/test_newcustom.py000066400000000000000000000163761347432460400244640ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path import unittest from unittest import TestCase import random from random import randrange random.seed(2) import myhdl from myhdl import * from .util import setupCosimulation from myhdl import ConversionError from myhdl.conversion._misc import _error ACTIVE_LOW, INACTIVE_HIGH = 0, 1 def incRef(count, enable, clock, reset, n): """ Incrementer with enable. count -- output enable -- control input, increment when 1 clock -- clock input reset -- asynchronous reset input n -- counter max value """ @instance def logic(): while 1: yield clock.posedge, reset.negedge if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = (count + 1) % n return logic def incGen(count, enable, clock, reset, n): """ Generator with __verilog__ is not permitted """ @instance def logic(): incGen.verilog_code = "Template string" while 1: yield clock.posedge, reset.negedge if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = (count + 1) % n return logic def inc(count, enable, clock, reset, n): """ Incrementer with enable. count -- output enable -- control input, increment when 1 clock -- clock input reset -- asynchronous reset input n -- counter max value """ @always(clock.posedge, reset.negedge) def incProcess(): # make it fail in conversion import types if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = (count + 1) % n count.driven = "reg" inc.verilog_code = \ """ always @(posedge $clock, negedge $reset) begin if (reset == 0) begin $count <= 0; end else begin if (enable) begin $count <= ($count + 1) % $n; end end end """ return incProcess def incErr(count, enable, clock, reset, n): @always(clock.posedge, reset.negedge) def incProcess(): # make it fail in conversion import types if reset == ACTIVE_LOW: count.next = 0 else: if enable: count.next = (count + 1) % n count.driven = "reg" incErr.verilog_code = \ """ always @(posedge $clock, negedge $reset) begin if (reset == 0) begin $count <= 0; end else begin if (enable) begin $count <= ($countq + 1) % $n; end end end """ return incProcess def inc_comb(nextCount, count, n): @always_comb def logic(): # make if fail in conversion import types nextCount.next = (count + 1) % n nextCount.driven = "wire" inc_comb.verilog_code =\ """ assign $nextCount = ($count + 1) % $n; """ return logic def inc_seq(count, nextCount, enable, clock, reset): @always(clock.posedge, reset.negedge) def logic(): if reset == ACTIVE_LOW: count.next = 0 else: if (enable): count.next = nextCount count.driven = "reg" inc_seq.verilog_code = \ """ always @(posedge $clock, negedge $reset) begin if (reset == 0) begin $count <= 0; end else begin if (enable) begin $count <= $nextCount; end end end """ # return nothing - cannot be simulated return [] def inc2(count, enable, clock, reset, n): nextCount = Signal(intbv(0, min=0, max=n)) comb = inc_comb(nextCount, count, n) seq = inc_seq(count, nextCount, enable, clock, reset) return comb, seq def inc3(count, enable, clock, reset, n): inc2_inst = inc2(count, enable, clock, reset, n) return inc2_inst def inc_v(name, count, enable, clock, reset): return setupCosimulation(**locals()) class TestInc(TestCase): def clockGen(self, clock): while 1: yield delay(10) clock.next = not clock def stimulus(self, enable, clock, reset): reset.next = INACTIVE_HIGH yield clock.negedge reset.next = ACTIVE_LOW yield clock.negedge reset.next = INACTIVE_HIGH for i in range(1000): enable.next = 1 yield clock.negedge for i in range(1000): enable.next = min(1, randrange(5)) yield clock.negedge raise StopSimulation def check(self, count, count_v, enable, clock, reset, n): expect = 0 yield reset.posedge self.assertEqual(count, expect) self.assertEqual(count, count_v) while 1: yield clock.posedge if enable: expect = (expect + 1) % n yield delay(1) # print "%d count %s expect %s count_v %s" % (now(), count, expect, count_v) self.assertEqual(count, expect) self.assertEqual(count, count_v) def bench(self, incRef, incVer): m = 8 n = 2 ** m count = Signal(intbv(0)[m:]) count_v = Signal(intbv(0)[m:]) enable = Signal(bool(0)) clock, reset = [Signal(bool()) for i in range(2)] inc_inst_ref = incRef(count, enable, clock, reset, n=n) inc_inst = toVerilog(incVer, count, enable, clock, reset, n=n) # inc_inst = inc(count, enable, clock, reset, n=n) inc_inst_v = inc_v(incVer.__name__, count_v, enable, clock, reset) clk_1 = self.clockGen(clock) st_1 = self.stimulus(enable, clock, reset) ch_1 = self.check(count, count_v, enable, clock, reset, n=n) sim = Simulation(inc_inst_ref, inc_inst_v, clk_1, st_1, ch_1) return sim def testIncRefIncRef(self): """ Check increment operation """ sim = self.bench(incRef, incRef) sim.run(quiet=1) def testIncRefInc(self): sim = self.bench(incRef, inc) sim.run(quiet=1) def testIncInc(self): sim = self.bench(inc, inc) sim.run(quiet=1) def testIncRefInc2(self): sim = self.bench(incRef, inc2) sim.run(quiet=1) def testIncRefInc3(self): sim = self.bench(incRef, inc3) sim.run(quiet=1) def testIncGen(self): m = 8 n = 2 ** m count_v = Signal(intbv(0)[m:]) enable = Signal(bool(0)) clock, reset = [Signal(bool()) for i in range(2)] try: inc_inst = toVerilog(incGen, count_v, enable, clock, reset, n=n) except ConversionError as e: self.assertEqual(e.kind, _error.NotSupported) else: self.fail() def testIncErr(self): m = 8 n = 2 ** m count_v = Signal(intbv(0)[m:]) enable = Signal(bool(0)) clock, reset = [Signal(bool()) for i in range(2)] try: inc_inst = toVerilog(incErr, count_v, enable, clock, reset, n=n) except ConversionError as e: pass else: self.fail() if __name__ == '__main__': unittest.main() myhdl-0.11/myhdl/test/conversion/toVerilog/test_not_supported_py2.py000066400000000000000000000014301347432460400261200ustar00rootroot00000000000000import pytest from myhdl import instance, Signal, toVerilog, ConversionError from myhdl.conversion._misc import _error from helpers import raises_kind def check(*args): with raises_kind(ConversionError, _error.NotSupported): toVerilog(*args) def test_Backquote(): a = Signal(bool()) z = Signal(bool()) def g(z, a): @instance def logic(): while 1: yield a z.next = 1 `a` return logic check(g, z, a) def testExec(): a = Signal(bool()) z = Signal(bool()) def g(z, a): @instance def logic(): while 1: yield a z.next = 1 exec "1 + 2" in globals , locals return logic check(g, z, a) myhdl-0.11/myhdl/test/conversion/toVerilog/test_ops.py000066400000000000000000000423151347432460400232310ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path import unittest from unittest import TestCase import random from random import randrange random.seed(2) import myhdl from myhdl import * from .util import setupCosimulation def binaryOps( Bitand, Bitor, Bitxor, FloorDiv, LeftShift, Mod, Mul, Pow, RightShift, Sub, Sum, EQ, NE, LT, GT, LE, GE, And, Or, left, right): @instance def logic(): while 1: yield left, right Bitand.next = left & right Bitor.next = left | right Bitxor.next = left ^ right if right != 0: FloorDiv.next = left // right if left < 256 and right < 40: LeftShift.next = left << right if right != 0: Mod.next = left % right Mul.next = left * right # Icarus doesn't support ** yet #if left < 256 and right < 40: # Pow.next = left ** right Pow.next = 0 RightShift.next = left >> right if left >= right: Sub.next = left - right Sum.next = left + right EQ.next = left == right NE.next = left != right LT.next = left < right GT.next = left > right LE.next = left <= right GE.next = left >= right And.next = bool(left) and bool(right) Or.next = bool(left) or bool(right) return logic def binaryOps_v(name, Bitand, Bitor, Bitxor, FloorDiv, LeftShift, Mod, Mul, Pow, RightShift, Sub, Sum, EQ, NE, LT, GT, LE, GE, And, Or, left, right): return setupCosimulation(**locals()) class TestBinaryOps(TestCase): def binaryBench(self, m, n): M = 2**m N = 2**n left = Signal(intbv(0)[m:]) right = Signal(intbv(0)[n:]) Bitand = Signal(intbv(0)[max(m, n):]) Bitand_v = Signal(intbv(0)[max(m, n):]) Bitor = Signal(intbv(0)[max(m, n):]) Bitor_v = Signal(intbv(0)[max(m, n):]) Bitxor = Signal(intbv(0)[max(m, n):]) Bitxor_v = Signal(intbv(0)[max(m, n):]) FloorDiv = Signal(intbv(0)[m:]) FloorDiv_v = Signal(intbv(0)[m:]) LeftShift = Signal(intbv(0)[64:]) LeftShift_v = Signal(intbv(0)[64:]) Mod = Signal(intbv(0)[m:]) Mod_v = Signal(intbv(0)[m:]) Mul = Signal(intbv(0)[m+n:]) Mul_v = Signal(intbv(0)[m+n:]) Pow = Signal(intbv(0)[64:]) Pow_v = Signal(intbv(0)[64:]) RightShift = Signal(intbv(0)[m:]) RightShift_v = Signal(intbv(0)[m:]) Sub = Signal(intbv(0)[max(m, n):]) Sub_v = Signal(intbv(0)[max(m, n):]) Sum = Signal(intbv(0)[max(m, n)+1:]) Sum_v = Signal(intbv(0)[max(m, n)+1:]) EQ, NE, LT, GT, LE, GE = [Signal(bool()) for i in range(6)] EQ_v, NE_v, LT_v, GT_v, LE_v, GE_v = [Signal(bool()) for i in range(6)] And, Or = [Signal(bool()) for i in range(2)] And_v, Or_v, = [Signal(bool()) for i in range(2)] binops = toVerilog(binaryOps, Bitand, Bitor, Bitxor, FloorDiv, LeftShift, Mod, Mul, Pow, RightShift, Sub, Sum, EQ, NE, LT, GT, LE, GE, And, Or, left, right) binops_v = binaryOps_v(binaryOps.__name__, Bitand_v, Bitor_v, Bitxor_v, FloorDiv_v, LeftShift_v, Mod_v, Mul_v, Pow_v, RightShift_v, Sub_v, Sum_v, EQ_v, NE_v, LT_v, GT_v, LE_v, GE_v, And_v, Or_v, left, right) def stimulus(): for i in range(min(M, N)): # print i left.next = intbv(i) right.next = intbv(i) yield delay(10) for i in range(100): left.next = randrange(M) right.next = randrange(N) yield delay(10) for j, k in ((0, 0), (0, N-1), (M-1, 0), (M-1, N-1)): left.next = j right.next = k yield delay(10) def check(): while 1: yield left, right yield delay(1) # print "%s %s %s %s" % (left, right, Or, Or_v) self.assertEqual(Bitand, Bitand_v) self.assertEqual(Bitor, Bitor_v) self.assertEqual(Bitxor, Bitxor_v) self.assertEqual(FloorDiv, FloorDiv_v) self.assertEqual(LeftShift, LeftShift_v) self.assertEqual(Mod, Mod_v) self.assertEqual(Mul, Mul_v) # self.assertEqual(Pow, Pow_v) self.assertEqual(RightShift, RightShift_v) self.assertEqual(Sub, Sub_v) self.assertEqual(Sum, Sum_v) self.assertEqual(EQ, EQ_v) self.assertEqual(NE, NE_v) self.assertEqual(LT, LT_v) self.assertEqual(GT, GT_v) self.assertEqual(LE, LE_v) self.assertEqual(GE, GE_v) self.assertEqual(And, And_v) self.assertEqual(Or, Or_v) return binops, binops_v, stimulus(), check() def testBinaryOps(self): for m, n in ((4, 4,), (5, 3), (2, 6), (8, 7)): sim = self.binaryBench(m, n) Simulation(sim).run() def multiOps( Bitand, Bitor, Bitxor, And, Or, argm, argn, argp): @instance def logic(): while 1: yield argm, argn, argp Bitand.next = argm & argn & argp Bitor.next = argm | argn | argp Bitxor.next = argm ^ argn ^ argp And.next = bool(argm) and bool(argn) and bool(argp) Or.next = bool(argm) and bool(argn) and bool(argp) return logic def multiOps_v( name, Bitand, Bitor, Bitxor, And, Or, argm, argn, argp): return setupCosimulation(**locals()) class TestMultiOps(TestCase): def multiBench(self, m, n, p): M = 2**m N = 2**n P = 2**p argm = Signal(intbv(0)[m:]) argn = Signal(intbv(0)[n:]) argp = Signal(intbv(0)[p:]) Bitand = Signal(intbv(0)[max(m, n, p):]) Bitand_v = Signal(intbv(0)[max(m, n, p):]) Bitor = Signal(intbv(0)[max(m, n, p):]) Bitor_v = Signal(intbv(0)[max(m, n, p):]) Bitxor = Signal(intbv(0)[max(m, n, p):]) Bitxor_v = Signal(intbv(0)[max(m, n, p):]) And, Or = [Signal(bool()) for i in range(2)] And_v, Or_v, = [Signal(bool()) for i in range(2)] multiops = toVerilog(multiOps, Bitand, Bitor, Bitxor, And, Or, argm, argn, argp) multiops_v = multiOps_v(multiOps.__name__, Bitand_v, Bitor_v, Bitxor_v, And_v, Or_v, argm, argn, argp) def stimulus(): for i in range(min(M, N, P)): # print i argm.next = intbv(i) argn.next = intbv(i) argp.next = intbv(i) yield delay(10) for i in range(100): argm.next = randrange(M) argn.next = randrange(N) argp.next = randrange(P) yield delay(10) for j, k, l in ((0, 0, 0), (0, 0, P-1), (0, N-1, P-1), (M-1, 0, 0), (M-1, 0, P-1), (M-1, N-1, 0), (0, N-1, 0), (M-1, N-1, P-1)): argm.next = j argn.next = k argp.next = l yield delay(10) def check(): while 1: yield argm, argn, argp yield delay(1) # print "%s %s %s %s %s" % (argm, argn, argp, Bitxor, Bitxor_v) self.assertEqual(Bitand, Bitand_v) self.assertEqual(Bitor, Bitor_v) self.assertEqual(Bitxor, Bitxor_v) self.assertEqual(And, And_v) self.assertEqual(Or, Or_v) return multiops, multiops_v, stimulus(), check() def testMultiOps(self): for m, n, p in ((4, 4, 4,), (5, 3, 2), (3, 4, 6), (3, 7, 4)): sim = self.multiBench(m, n, p) Simulation(sim).run() def unaryOps( Not, Invert, UnaryAdd, UnarySub, arg): @instance def logic(): while 1: yield arg Not.next = not arg Invert.next = ~arg UnaryAdd.next = +arg UnarySub.next = --arg return logic def unaryOps_v(name, Not, Invert, UnaryAdd, UnarySub, arg): return setupCosimulation(**locals()) class TestUnaryOps(TestCase): def unaryBench(self, m): M = 2**m arg = Signal(intbv(0)[m:]) Not = Signal(bool(0)) Not_v = Signal(bool(0)) Invert = Signal(intbv(0)[m:]) Invert_v = Signal(intbv(0)[m:]) UnaryAdd = Signal(intbv(0)[m:]) UnaryAdd_v = Signal(intbv(0)[m:]) UnarySub = Signal(intbv(0)[m:]) UnarySub_v = Signal(intbv(0)[m:]) unaryops = toVerilog(unaryOps, Not, Invert, UnaryAdd, UnarySub, arg) unaryops_v = unaryOps_v(unaryOps.__name__, Not_v, Invert_v, UnaryAdd_v, UnarySub_v, arg) def stimulus(): for i in range(M): arg.next = intbv(i) yield delay(10) for i in range(100): arg.next = randrange(M) yield delay(10) raise StopSimulation def check(): while 1: yield arg yield delay(1) self.assertEqual(Not, Not_v) self.assertEqual(Invert, Invert_v) self.assertEqual(UnaryAdd, UnaryAdd_v) self.assertEqual(UnarySub, UnarySub_v) return unaryops, unaryops_v, stimulus(), check() def testUnaryOps(self): for m in (4, 7): sim = self.unaryBench(m) Simulation(sim).run() def augmOps( Bitand, Bitor, Bitxor, FloorDiv, LeftShift, Mod, Mul, RightShift, Sub, Sum, left, right): @instance def logic(): var = intbv(0)[max(64, len(left) + len(right)):] while 1: yield left, right var[:] = left var &= right Bitand.next = var var[:] = left var |= right Bitor.next = var var[:] = left var ^= left Bitxor.next = var if right != 0: var[:] = left var //= right FloorDiv.next = var if left < 256 and right < 40: var[:] = left var <<= right LeftShift.next = var if right != 0: var[:] = left var %= right Mod.next = var var[:] = left var *= right Mul.next = var var[:] = left var >>= right RightShift.next = var if left >= right: var[:] = left var -= right Sub.next = var var[:] = left var += right Sum.next = var return logic def augmOps_v( name, Bitand, Bitor, Bitxor, FloorDiv, LeftShift, Mod, Mul, RightShift, Sub, Sum, left, right): return setupCosimulation(**locals()) class TestAugmOps(TestCase): def augmBench(self, m, n): M = 2**m N = 2**n left = Signal(intbv(0)[m:]) right = Signal(intbv(0)[n:]) Bitand = Signal(intbv(0)[max(m, n):]) Bitand_v = Signal(intbv(0)[max(m, n):]) Bitor = Signal(intbv(0)[max(m, n):]) Bitor_v = Signal(intbv(0)[max(m, n):]) Bitxor = Signal(intbv(0)[max(m, n):]) Bitxor_v = Signal(intbv(0)[max(m, n):]) FloorDiv = Signal(intbv(0)[m:]) FloorDiv_v = Signal(intbv(0)[m:]) LeftShift = Signal(intbv(0)[64:]) LeftShift_v = Signal(intbv(0)[64:]) Mod = Signal(intbv(0)[m:]) Mod_v = Signal(intbv(0)[m:]) Mul = Signal(intbv(0)[m+n:]) Mul_v = Signal(intbv(0)[m+n:]) RightShift = Signal(intbv(0)[m:]) RightShift_v = Signal(intbv(0)[m:]) Sub = Signal(intbv(0)[max(m, n):]) Sub_v = Signal(intbv(0)[max(m, n):]) Sum = Signal(intbv(0)[max(m, n)+1:]) Sum_v = Signal(intbv(0)[max(m, n)+1:]) augmops = toVerilog(augmOps, Bitand, Bitor, Bitxor, FloorDiv, LeftShift, Mod, Mul, RightShift, Sub, Sum, left, right) augmops_v = augmOps_v( augmOps.__name__, Bitand_v, Bitor_v, Bitxor_v, FloorDiv_v, LeftShift_v, Mod_v, Mul_v, RightShift_v, Sub_v, Sum_v, left, right) def stimulus(): for i in range(min(M, N)): # print i left.next = intbv(i) right.next = intbv(i) yield delay(10) for i in range(100): left.next = randrange(M) right.next = randrange(N) yield delay(10) for j, k in ((0, 0), (0, N-1), (M-1, 0), (M-1, N-1)): left.next = j right.next = k yield delay(10) def check(): while 1: yield left, right yield delay(1) # print "%s %s %s %s" % (left, right, Or, Or_v) self.assertEqual(Bitand, Bitand_v) self.assertEqual(Bitor, Bitor_v) self.assertEqual(Bitxor, Bitxor_v) self.assertEqual(FloorDiv, FloorDiv_v) self.assertEqual(LeftShift, LeftShift_v) self.assertEqual(Mod, Mod_v) self.assertEqual(Mul, Mul_v) self.assertEqual(RightShift, RightShift_v) self.assertEqual(Sub, Sub_v) self.assertEqual(Sum, Sum_v) return augmops, augmops_v, stimulus(), check() def testAugmOps(self): for m, n in ((4, 4,), (5, 3), (2, 6), (8, 7)): sim = self.augmBench(m, n) Simulation(sim).run() if __name__ == '__main__': unittest.main() myhdl-0.11/myhdl/test/conversion/toVerilog/test_ram.py000066400000000000000000000077501347432460400232130ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path import unittest from unittest import TestCase import myhdl from myhdl import * from .util import setupCosimulation def ram(dout, din, addr, we, clk, depth=128): """ Simple ram model """ @instance def logic(): mem = [intbv(0)[8:] for i in range(depth)] a = intbv(0)[8:] # ad = 1 while 1: yield clk.posedge if we: ad = int(addr) mem[int(addr)][:] = din # a = din.val # a[2] = din dout.next = mem[int(addr)] return logic def ram_clocked(dout, din, addr, we, clk, depth=128): """ Ram model """ mem = [Signal(intbv(0)[8:]) for i in range(depth)] @instance def access(): while 1: yield clk.posedge if we: mem[int(addr)].next = din dout.next = mem[int(addr)] return access def ram_deco1(dout, din, addr, we, clk, depth=128): """ Ram model """ mem = [Signal(intbv(0)[8:]) for i in range(depth)] @instance def write(): while 1: yield clk.posedge if we: mem[int(addr)].next = din @always_comb def read(): dout.next = mem[int(addr)] return write, read def ram_deco2(dout, din, addr, we, clk, depth=128): """ Ram model """ mem = [Signal(intbv(0)[8:]) for i in range(depth)] @always(clk.posedge) def write(): if we: mem[int(addr)].next = din @always_comb def read(): dout.next = mem[int(addr)] return write, read def ram2(dout, din, addr, we, clk, depth=128): # memL = [intbv(0,min=dout._min,max=dout._max) for i in range(depth)] memL = [Signal(intbv()[len(dout):]) for i in range(depth)] @instance def wrLogic() : while 1: yield clk.posedge if we: memL[int(addr)].next = din @instance def rdLogic() : while 1: yield clk.posedge dout.next = memL[int(addr)] return wrLogic, rdLogic def ram_v(name, dout, din, addr, we, clk, depth=4): return setupCosimulation(**locals()) class TestMemory(TestCase): def bench(self, ram, depth=128): dout = Signal(intbv(0)[8:]) dout_v = Signal(intbv(0)[8:]) din = Signal(intbv(0)[8:]) addr = Signal(intbv(0)[7:]) we = Signal(bool(0)) clk = Signal(bool(0)) # mem_inst = ram(dout, din, addr, we, clk, depth) mem_inst = toVerilog(ram, dout, din, addr, we, clk, depth) mem_v_inst = ram_v(ram.__name__, dout_v, din, addr, we, clk, depth) def stimulus(): for i in range(depth): din.next = i addr.next = i we.next = True yield clk.negedge we.next = False for i in range(depth): addr.next = i yield clk.negedge yield clk.posedge yield delay(1) #print dout #print dout_v self.assertEqual(dout, i) # self.assertEqual(dout, dout_v) raise StopSimulation() def clkgen(): while 1: yield delay(10) clk.next = not clk return clkgen(), stimulus(), mem_inst, mem_v_inst def test1(self): sim = self.bench(ram) Simulation(sim).run() def test2(self): sim = self.bench(ram2) Simulation(sim).run() def testram_clocked(self): sim = self.bench(ram_clocked) Simulation(sim).run() def testram_deco1(self): sim = self.bench(ram_deco1) Simulation(sim).run() def testram_deco2(self): sim = self.bench(ram_deco2) Simulation(sim).run() if __name__ == '__main__': unittest.main() myhdl-0.11/myhdl/test/conversion/toVerilog/test_rom.py000066400000000000000000000044721347432460400232270ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path import unittest from unittest import TestCase from random import randrange import myhdl from myhdl import * from .util import setupCosimulation D = 256 ROM = tuple([randrange(D) for i in range(D)]) # ROM = [randrange(256) for i in range(256)] def rom1(dout, addr, clk): @instance def rdLogic() : while 1: yield clk.posedge dout.next = ROM[int(addr)] return rdLogic def rom2(dout, addr, clk): theROM = ROM @instance def rdLogic() : while 1: yield clk.posedge dout.next = theROM[int(addr)] return rdLogic def rom3(dout, addr, clk): @instance def rdLogic() : tmp = intbv(0)[8:] while 1: yield addr tmp[:] = ROM[int(addr)] dout.next = tmp return rdLogic def rom4(dout, addr, clk): @always_comb def read(): dout.next = ROM[int(addr)] return read def rom_v(name, dout, addr, clk): return setupCosimulation(**locals()) class TestRom(TestCase): def bench(self, rom): dout = Signal(intbv(0)[8:]) dout_v = Signal(intbv(0)[8:]) addr = Signal(intbv(1)[8:]) clk = Signal(bool(0)) # rom_inst = rom(dout, din, addr, we, clk, depth) rom_inst = toVerilog(rom, dout, addr, clk) rom_v_inst = rom_v(rom.__name__, dout_v, addr, clk) def stimulus(): for i in range(D): addr.next = i yield clk.negedge yield clk.posedge yield delay(1) self.assertEqual(dout, ROM[i]) self.assertEqual(dout, dout_v) raise StopSimulation() def clkgen(): while 1: yield delay(10) clk.next = not clk return clkgen(), stimulus(), rom_inst, rom_v_inst def test1(self): sim = self.bench(rom1) Simulation(sim).run() def test2(self): sim = self.bench(rom2) Simulation(sim).run() def test3(self): sim = self.bench(rom3) Simulation(sim).run() def test4(self): sim = self.bench(rom4) Simulation(sim).run() if __name__ == '__main__': unittest.main() myhdl-0.11/myhdl/test/conversion/toVerilog/test_signed.py000066400000000000000000000445141347432460400237040ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path import unittest from unittest import TestCase import random from random import randrange random.seed(2) import myhdl from myhdl import * from .util import setupCosimulation def binaryOps( ## Bitand, ## Bitor, ## Bitxor, ## FloorDiv, LeftShift, ## Mod, Mul, ## Pow, RightShift, Sub, Sum, Sum1, Sum2, Sum3, EQ, NE, LT, GT, LE, GE, And, Or, left, right, bit): @instance def logic(): while 1: yield left, right ## Bitand.next = left & right ## Bitor.next = left | right ## Bitxor.next = left ^ right ## if right != 0: ## FloorDiv.next = left // right if left < 256 and right < 40 and right >= 0: LeftShift.next = left << right ## if right != 0: ## Mod.next = left % right Mul.next = left * right ## # Icarus doesn't support ** yet ## #if left < 256 and right < 40: ## # Pow.next = left ** right ## Pow.next = 0 if right >= -0: RightShift.next = left >> right ## RightShift.next = left Sub.next = left - right Sum.next = left + right Sum1.next = left + right[2:] Sum2.next = left + right[1] Sum3.next = left + bit EQ.next = left == right NE.next = left != right LT.next = left < right GT.next = left > right LE.next = left <= right GE.next = left >= right And.next = bool(left) and bool(right) Or.next = bool(left) or bool(right) return logic def binaryOps_v(name, ## Bitand, ## Bitor, ## Bitxor, ## FloorDiv, LeftShift, ## Mod, Mul, ## Pow, RightShift, Sub, Sum, Sum1, Sum2, Sum3, EQ, NE, LT, GT, LE, GE, And, Or, left, right, bit): return setupCosimulation(**locals()) class TestBinaryOps(TestCase): def binaryBench(self, Ll, Ml, Lr, Mr): bit = Signal(bool(0)) left = Signal(intbv(Ll, min=Ll, max=Ml)) right = Signal(intbv(Lr, min=Lr, max=Mr)) M = 2**14 ## Bitand = Signal(intbv(0, min=-2**17, max=2**17)) ## Bitand_v = Signal(intbv(0, min=-2**17, max=2**17)) ## Bitor = Signal(intbv(0)[max(m, n):]) ## Bitor_v = Signal(intbv(0)[max(m, n):]) ## Bitxor = Signal(intbv(0)[max(m, n):]) ## Bitxor_v = Signal(intbv(0)[max(m, n):]) ## FloorDiv = Signal(intbv(0)[m:]) ## FloorDiv_v = Signal(intbv(0)[m:]) LeftShift = Signal(intbv(0, min=-2**64, max=2**64)) LeftShift_v = Signal(intbv(0, min=-2**64, max=2**64)) ## Mod = Signal(intbv(0)[m:]) ## Mod_v = Signal(intbv(0)[m:]) Mul = Signal(intbv(0, min=-2**17, max=2**17)) Mul_v = Signal(intbv(0, min=-2**17, max=2**17)) ## Pow = Signal(intbv(0)[64:]) ## Pow_v = Signal(intbv(0)[64:]) RightShift = Signal(intbv(0, min=-M, max=M)) RightShift_v = Signal(intbv(0, min=-M, max=M)) Sub, Sub1, Sub2, Sub3 = [Signal(intbv(min=-M, max=M)) for i in range(4)] Sub_v, Sub1_v, Sub2_v, Sub3_v = [Signal(intbv(min=-M, max=M)) for i in range(4)] Sum, Sum1, Sum2, Sum3 = [Signal(intbv(min=-M, max=M)) for i in range(4)] Sum_v, Sum1_v, Sum2_v, Sum3_v = [Signal(intbv(min=-M, max=M)) for i in range(4)] EQ, NE, LT, GT, LE, GE = [Signal(bool()) for i in range(6)] EQ_v, NE_v, LT_v, GT_v, LE_v, GE_v = [Signal(bool()) for i in range(6)] And, Or = [Signal(bool()) for i in range(2)] And_v, Or_v, = [Signal(bool()) for i in range(2)] binops = toVerilog(binaryOps, ## Bitand, ## Bitor, ## Bitxor, ## FloorDiv, LeftShift, ## Mod, Mul, ## Pow, RightShift, Sub, Sum, Sum1, Sum2, Sum3, EQ, NE, LT, GT, LE, GE, And, Or, left, right, bit) binops_v = binaryOps_v(binaryOps.__name__, ## Bitand_v, ## Bitor_v, ## Bitxor_v, ## FloorDiv_v, LeftShift_v, ## Mod_v, Mul_v, ## Pow_v, RightShift_v, Sub_v, Sum_v, Sum1_v, Sum2_v, Sum3_v, EQ_v, NE_v, LT_v, GT_v, LE_v, GE_v, And_v, Or_v, left, right, bit) def stimulus(): for i in range(100): # bit.next = False left.next = randrange(Ll, Ml) right.next = randrange(Lr, Mr) yield delay(10) for j, k in ((Ll, Lr), (Ml-1, Mr-1), (Ll, Mr-1), (Ml-1, Lr)): left.next = j right.next = k yield delay(10) def check(): while 1: yield left, right bit.next = not bit yield delay(1) #print "%s %s %s %s" % (left, right, Mul, Mul_v) #print "%s %s %s %s" % (left, right, bin(Mul), bin(Mul_v)) #print "%s %s %s %s" % (left, right, Sum, Sum_v) #print "%s %s %s %s" % (left, right, bin(Sum), bin(Sum_v)) ## print left ## print right ## print bin(left) ## print bin(right) ## print bin(Bitand) ## print bin(Bitand_v) ## print Bitand ## print Bitand_v ## self.assertEqual(Bitand, Bitand_v) #w = len(Bitand) #self.assertEqual(bin(Bitand, w), bin(Bitand_v,w )) ## self.assertEqual(Bitor, Bitor_v) ## self.assertEqual(Bitxor, Bitxor_v) ## self.assertEqual(FloorDiv, FloorDiv_v) self.assertEqual(LeftShift, LeftShift_v) ## self.assertEqual(Mod, Mod_v) self.assertEqual(Mul, Mul_v) # self.assertEqual(Pow, Pow_v) self.assertEqual(RightShift, RightShift_v) self.assertEqual(Sub, Sub_v) self.assertEqual(Sum, Sum_v) self.assertEqual(Sum1, Sum1_v) self.assertEqual(Sum2, Sum2_v) self.assertEqual(Sum3, Sum3_v) self.assertEqual(EQ, EQ_v) self.assertEqual(NE, NE_v) self.assertEqual(LT, LT_v) self.assertEqual(GT, GT_v) self.assertEqual(LE, LE_v) self.assertEqual(GE, GE_v) self.assertEqual(And, And_v) self.assertEqual(Or, Or_v) return binops, binops_v, stimulus(), check() def testBinaryOps(self): for Ll, Ml, Lr, Mr in ( (-254, 236, 0, 4), (-128, 128, -128, 128), (-53, 25, -23, 123), (-23, 145, -66, 12), (23, 34, -34, -16), (-54, -20, 45, 73), (-25, -12, -123, -66), ): sim = self.binaryBench(Ll, Ml, Lr, Mr) Simulation(sim).run() def unaryOps( Not, Invert, UnaryAdd, UnarySub, arg): @instance def logic(): while 1: yield arg Not.next = not arg Invert.next = ~arg UnaryAdd.next = +arg UnarySub.next = --arg return logic def unaryOps_v(name, Not, Invert, UnaryAdd, UnarySub, arg): return setupCosimulation(**locals()) class TestUnaryOps(TestCase): def unaryBench(self, m): M = 2**m arg = Signal(intbv(0, min=-M, max=+M)) Not = Signal(bool(0)) Not_v = Signal(bool(0)) Invert = Signal(intbv(0, min=-M, max=+M)) Invert_v = Signal(intbv(0, min=-M, max=+M)) UnaryAdd = Signal(intbv(0, min=-M, max=+M)) UnaryAdd_v = Signal(intbv(0, min=-M, max=+M)) UnarySub = Signal(intbv(0, min=-M, max=+M)) UnarySub_v = Signal(intbv(0, min=-M, max=+M)) unaryops = toVerilog(unaryOps, Not, Invert, UnaryAdd, UnarySub, arg) unaryops_v = unaryOps_v(unaryOps.__name__, Not_v, Invert_v, UnaryAdd_v, UnarySub_v, arg) def stimulus(): for i in range(-M, M): arg.next = intbv(i) yield delay(10) for i in range(100): arg.next = randrange(-M, M) yield delay(10) raise StopSimulation def check(): while 1: yield arg yield delay(1) self.assertEqual(Not, Not_v) self.assertEqual(Invert, Invert_v) self.assertEqual(UnaryAdd, UnaryAdd_v) self.assertEqual(UnarySub, UnarySub_v) return unaryops, unaryops_v, stimulus(), check() def testUnaryOps(self): for m in (4, 7): sim = self.unaryBench(m) Simulation(sim).run() def augmOps( ## Bitand, ## Bitor, ## Bitxor, ## FloorDiv, LeftShift, ## Mod, Mul, RightShift, Sub, Sum, left, right): @instance def logic(): var = intbv(0, min=-2**17, max=+2**17) var2 = intbv(0, min=-2**64, max=+2**64) while 1: yield left, right ## var[:] = left ## var &= right ## Bitand.next = var ## var[:] = left ## var |= right ## Bitor.next = var ## var[:] = left ## var ^= left ## Bitxor.next = var ## if right != 0: ## var[:] = left ## var //= right ## FloorDiv.next = var if left < 256 and right < 40 and right >= 0: var2[:] = left var2 <<= right LeftShift.next = var2 ## if right != 0: ## var[:] = left ## var %= right ## Mod.next = var var[:] = left var *= right Mul.next = var var[:] = left if right >= 0: var >>= right RightShift.next = var var[:] = left var -= right Sub.next = var var[:] = left var += right Sum.next = var return logic def augmOps_v( name, ## Bitand, ## Bitor, ## Bitxor, ## FloorDiv, LeftShift, ## Mod, Mul, RightShift, Sub, Sum, left, right): return setupCosimulation(**locals()) class TestAugmOps(TestCase): def augmBench(self, Ll, Ml, Lr, Mr): left = Signal(intbv(Ll, min=Ll, max=Ml)) right = Signal(intbv(Lr, min=Lr, max=Mr)) M = 2**17 ## Bitand = Signal(intbv(0)[max(m, n):]) ## Bitand_v = Signal(intbv(0)[max(m, n):]) ## Bitor = Signal(intbv(0)[max(m, n):]) ## Bitor_v = Signal(intbv(0)[max(m, n):]) ## Bitxor = Signal(intbv(0)[max(m, n):]) ## Bitxor_v = Signal(intbv(0)[max(m, n):]) ## FloorDiv = Signal(intbv(0)[m:]) ## FloorDiv_v = Signal(intbv(0)[m:]) LeftShift = Signal(intbv(0, min=-2**64, max=2**64)) LeftShift_v = Signal(intbv(0, min=-2**64, max=2**64)) ## Mod = Signal(intbv(0)[m:]) ## Mod_v = Signal(intbv(0)[m:]) Mul = Signal(intbv(0, min=-M, max=+M)) Mul_v = Signal(intbv(0, min=-M, max=+M)) RightShift = Signal(intbv(0, min=-M, max=+M)) RightShift_v = Signal(intbv(0, min=-M, max=+M)) Sub = Signal(intbv(0, min=-M, max=+M)) Sub_v = Signal(intbv(0, min=-M, max=+M)) Sum = Signal(intbv(0, min=-M, max=+M)) Sum_v = Signal(intbv(0, min=-M, max=+M)) augmops = toVerilog(augmOps, ## Bitand, ## Bitor, ## Bitxor, ## FloorDiv, LeftShift, ## Mod, Mul, RightShift, Sub, Sum, left, right) augmops_v = augmOps_v( augmOps.__name__, ## Bitand_v, ## Bitor_v, ## Bitxor_v, ## FloorDiv_v, LeftShift_v, ## Mod_v, Mul_v, RightShift_v, Sub_v, Sum_v, left, right) def stimulus(): for i in range(100): left.next = randrange(Ll, Ml) right.next = randrange(Lr, Mr) yield delay(10) for j, k in ((Ll, Lr), (Ml-1, Mr-1), (Ll, Mr-1), (Ml-1, Lr)): left.next = j right.next = k yield delay(10) def check(): while 1: yield left, right yield delay(1) # print "%s %s %s %s" % (left, right, Or, Or_v) ## self.assertEqual(Bitand, Bitand_v) ## self.assertEqual(Bitor, Bitor_v) ## self.assertEqual(Bitxor, Bitxor_v) ## self.assertEqual(FloorDiv, FloorDiv_v) ## self.assertEqual(LeftShift, LeftShift_v) ## self.assertEqual(Mod, Mod_v) self.assertEqual(Mul, Mul_v) self.assertEqual(RightShift, RightShift_v) self.assertEqual(Sub, Sub_v) self.assertEqual(Sum, Sum_v) return augmops, augmops_v, stimulus(), check() def testAugmOps(self): for Ll, Ml, Lr, Mr in ( (-254, 236, 0, 4), (-128, 128, -128, 128), (-53, 25, -23, 123), (-23, 145, -66, 12), (23, 34, -34, -16), (-54, -20, 45, 73), (-25, -12, -123, -66), ): sim = self.augmBench(Ll, Ml, Lr, Mr) Simulation(sim).run() def expressions(a, b, clk): c = Signal(intbv(0, min=0, max=47)) e = Signal(bool()) @instance def logic(): d = intbv(0, min=-23, max=43) d[:] = -17 c.next = 5 yield clk.posedge a.next = c + 1 b.next = c + 1 yield clk.posedge a.next = c + -10 b.next = c + -1 yield clk.posedge a.next = c < -10 b.next = c < -1 yield clk.posedge a.next = d + c b.next = d >= c yield clk.posedge # a.next = d & c # b.next = c + (d & c) yield clk.posedge a.next = d + -c b.next = c + (-d) yield clk.posedge a.next = -d yield clk.posedge a.next = -c yield clk.posedge c.next = 46 yield clk.posedge a.next = ~d + 1 b.next = ~c + 1 yield clk.posedge a.next = ~c + 1 b.next = ~d + 1 yield clk.posedge raise StopSimulation return logic def expressions_v(a, b, clk): return setupCosimulation(**locals()) class TestExpressions(TestCase): def bench(self): a, a_v = [Signal(intbv(0, min=-34, max=47)) for i in range(2)] b, b_v = [Signal(intbv(0, min=0, max=47)) for i in range(2)] clk = Signal(bool()) expr = toVerilog(expressions, a, b, clk) expr_v = toVerilog(expressions, a_v, b_v, clk) @instance def check(): while 1: yield clk.posedge yield delay(1) self.assertEqual(a, a_v) # print a # print a_v self.assertEqual(b, b_v) @always(delay(10)) def clkgen(): clk.next = not clk return expr, expr_v, check, clkgen def testExpressions(self): sim = self.bench() Simulation(sim).run() if __name__ == '__main__': unittest.main() myhdl-0.11/myhdl/test/conversion/toVerilog/test_tristate.py000066400000000000000000000042071347432460400242650ustar00rootroot00000000000000import os path = os.path import unittest import myhdl from myhdl import * from .util import setupCosimulation def tristate_obuf(A, Y, OE): '''three-state output buffer''' Y_d = Y.driver() @always_comb def hdl(): Y_d.next = A if OE else None return hdl class OBuf(object): def __init__(self): self.Y = TristateSignal(True) self.A = Signal(False) self.OE = Signal(False) def interface(self): return self.A, self.Y, self.OE def tristate_obuf_i(obuf): '''three-state output buffer, using interface''' # Caveat: A local name of the interface signals must be declared, # Otherwise, _HierExtr.extract() will not add them to symdict # and conversion will fail. A, Y, OE = obuf.interface() Y_d = Y.driver() @always_comb def hdl(): Y_d.next = A if OE else None return hdl class TestTristate(unittest.TestCase): def bench(self, obuf=None): if obuf: toVerilog(tristate_obuf_i, obuf) A, Y, OE = obuf.interface() else: Y = TristateSignal(True) A = Signal(True) OE = Signal(False) toVerilog(tristate_obuf, A, Y, OE) inst = setupCosimulation(name='tristate_obuf', **toVerilog.portmap) #inst = tristate_obuf(A, Y, OE) @instance def stimulus(): yield delay(1) #print now(), A, OE, Y self.assertEqual(Y, None) OE.next = True yield delay(1) #print now(), A, OE, Y self.assertEqual(Y, A) A.next = not A yield delay(1) #print now(), A, OE, Y self.assertEqual(Y, A) OE.next = False yield delay(1) #print now(), A, OE, Y self.assertEqual(Y, None) raise StopSimulation return instances() def testOBuf(self): sim = Simulation(self.bench()) sim.run() def testOBufInterface(self): obuf = OBuf() sim = Simulation(self.bench(obuf)) sim.run() if __name__ == '__main__': unittest.main() myhdl-0.11/myhdl/test/conversion/toVerilog/util.py000066400000000000000000000023271347432460400223450ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path import subprocess import myhdl from myhdl import * # Icarus def setupCosimulationIcarus(**kwargs): name = kwargs['name'] objfile = "%s.o" % name if path.exists(objfile): os.remove(objfile) analyze_cmd = ['iverilog', '-o', objfile, '%s.v' %name, 'tb_%s.v' % name] subprocess.call(analyze_cmd) simulate_cmd = ['vvp', '-m', '../../../../cosimulation/icarus/myhdl.vpi', objfile] return Cosimulation(simulate_cmd, **kwargs) # cver def setupCosimulationCver(**kwargs): name = kwargs['name'] cmd = "cver -q +loadvpi=../../../../cosimulation/cver/myhdl_vpi:vpi_compat_bootstrap " + \ "%s.v tb_%s.v " % (name, name) return Cosimulation(cmd, **kwargs) def verilogCompileIcarus(name): objfile = "%s.o" % name if path.exists(objfile): os.remove(objfile) analyze_cmd = "iverilog -o %s %s.v tb_%s.v" % (objfile, name, name) os.system(analyze_cmd) def verilogCompileCver(name): cmd = "cver -c %s.v" % name os.system(cmd) setupCosimulation = setupCosimulationIcarus #setupCosimulation = setupCosimulationCver verilogCompile = verilogCompileIcarus #verilogCompile = verilogCompileCver myhdl-0.11/myhdl/test/conversion/toVerilog2/000077500000000000000000000000001347432460400210745ustar00rootroot00000000000000myhdl-0.11/myhdl/test/conversion/toVerilog2/Makefile000066400000000000000000000002351347432460400225340ustar00rootroot00000000000000all: vlog vlog: py.test --sim vlog iverilog: py.test --sim iverilog cver: py.test --sim cver clean: - rm *.o *.out *.v *.vhd *.pyc *~ *.vcd* *.log myhdl-0.11/myhdl/test/conversion/toVerilog2/README.txt000066400000000000000000000002721347432460400225730ustar00rootroot00000000000000Verilog-specific conversion tests --------------------------------- Requirements: * cver, icarus or vlog (default) * py.test See the Makefile - it contains targets per simulator. myhdl-0.11/myhdl/test/conversion/toVerilog2/__init__.py000066400000000000000000000000001347432460400231730ustar00rootroot00000000000000myhdl-0.11/myhdl/test/conversion/toVerilog2/test_loops.py000066400000000000000000000020721347432460400236420ustar00rootroot00000000000000from __future__ import absolute_import import os path = os.path from random import randrange import myhdl from myhdl import * from myhdl.conversion import verify, analyze from myhdl import ConversionError from myhdl.conversion._misc import _error def ForLoopError1(a, out): @instance def logic(): while 1: yield a var = 0 for i in range(1, 4, -1): if a[i] == 1: var += 1 out.next = var return logic def LoopBench(LoopTest): a = Signal(intbv(-1)[16:]) z = Signal(intbv(0)[16:]) looptest_inst = LoopTest(a, z) data = tuple([randrange(2**min(i, 16)) for i in range(100)]) @instance def stimulus(): for i in range(100): a.next = data[i] yield delay(10) print(z) return stimulus, looptest_inst def testForLoopError1(): try: analyze(LoopBench, ForLoopError1) except ConversionError as e: assert e.kind == _error.Requirement else: assert False myhdl-0.11/myhdl/test/core/000077500000000000000000000000001347432460400156035ustar00rootroot00000000000000myhdl-0.11/myhdl/test/core/Makefile000066400000000000000000000000451347432460400172420ustar00rootroot00000000000000all: py.test clean: - rm *.pyc *~ myhdl-0.11/myhdl/test/core/__init__.py000066400000000000000000000000001347432460400177020ustar00rootroot00000000000000myhdl-0.11/myhdl/test/core/setuptools-20.3.1.zip000066400000000000000000026035201347432460400212770ustar00rootroot00000000000000PK#KGH¡·€8m9setuptools-20.3.1/bootstrap.pyTÁŽã ½óV/i¥Yö^©—½íuµ·ÑÑনX Mó÷ë„fÚÍôRZÞ³ŸŸ7› û}‚ˆ©óÉ9AG°.4¥@Û˜¤1¨è錀öªƒ³-Úô:Uî]Œúh%GÀ«»à*f®·P»¶•VEÏ”$¸.i‹Ðkcàè\Š)HO)èθZ¶ÊÇjDŒ$´ÚêVÀ¦ù¡íÉÒëä”a”i³ŠN¿ØœEÉ<Œg ¹¬§PœmȦ[ïBË)Ë1á-õ¤z¹êŽ>¸cdŒÍ"ESäÂç Uµ}^•މì0‘—Þ¦‹÷ngÁðr»/öm"‰ ½ %¦¶µé /ë‹lP(™äûø#/cÄuÆÌ´iDÀY? Ôg¬/0¶-æ"nÔÙXþÿ”—a™aS„wšB|Ž_æÂ‹¼:a˜ VèÑ’ßõ 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setuptools-20.3.1/setuptools.egg-info/dependency_links.txtPKÁYrH1—„ 6¤‹· setuptools-20.3.1/setuptools.egg-info/entry_points.txtPKÁYrHÖB.l`2.¤cº setuptools-20.3.1/setuptools.egg-info/PKG-INFOPKÁYrHÜÎiGL2¤Ë setuptools-20.3.1/setuptools.egg-info/requires.txtPKÃYrH»zàæÓ1¤²Ë setuptools-20.3.1/setuptools.egg-info/SOURCES.txtPKÁYrH0\‘(&3¤çÏ setuptools-20.3.1/setuptools.egg-info/top_level.txtPK¡J[H“×2.¤`Ð setuptools-20.3.1/setuptools.egg-info/zip-safePK#KGH„ÆŒ8·_ &¤¯Ð setuptools-20.3.1/tests/manual_test.pyPK2ªÔ myhdl-0.11/myhdl/test/core/test_Cosimulation.py000066400000000000000000000175401347432460400216710ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run unit tests for Cosimulation """ from __future__ import absolute_import import gc import os import random import sys if sys.platform == "win32": import msvcrt from myhdl import Signal from myhdl._compat import to_bytes from myhdl._Cosimulation import Cosimulation, CosimulationError, _error if __name__ != '__main__': from helpers import raises_kind random.seed(1) # random, but deterministic MAXLINE = 4096 exe = "python {0} ".format(os.path.abspath(__file__)) fromSignames = ['a', 'bb', 'ccc'] fromSizes = [1, 11, 63] fromVals = [0x2, 0x43, 0x24] fromSigs = {} for s, v in zip(fromSignames, fromVals): fromSigs[s] = Signal(v) toSignames = ['d', 'ee', 'fff', 'g'] toSizes = [32, 12, 3, 6] toSigs = {} for s in toSignames: toSigs[s] = Signal(0) toVals = [0x3, 0x45, 0x14, 0x12] toXVals = ["X00", "FZ3", "34XZ", "56U"] allSigs = fromSigs.copy() allSigs.update(toSigs) def wtrf(): if sys.platform != "win32": wt = int(os.environ['MYHDL_TO_PIPE']) rf = int(os.environ['MYHDL_FROM_PIPE']) else: wt = msvcrt.open_osfhandle(int(os.environ['MYHDL_TO_PIPE']), os.O_APPEND | os.O_TEXT) rf = msvcrt.open_osfhandle(int(os.environ['MYHDL_FROM_PIPE']), os.O_RDONLY | os.O_TEXT) return wt, rf class TestCosimulation: def setup_method(self, method): gc.collect() def testWrongExe(self): with raises_kind(CosimulationError, _error.OSError): Cosimulation('bla -x 45') def testFromSignals(self): cosim = Cosimulation(exe + "cosimFromSignals", **allSigs) assert cosim._fromSignames == fromSignames assert cosim._fromSizes == fromSizes @staticmethod def cosimFromSignals(): wt, rf = wtrf() buf = "FROM 00 " for s, w in zip(fromSignames, fromSizes): buf += "%s %s " % (s, w) os.write(wt, to_bytes(buf)) os.read(rf, MAXLINE) os.write(wt, b"TO 0000 a 1") os.read(rf, MAXLINE) os.write(wt, b"START") os.read(rf, MAXLINE) def testToSignals(self): cosim = Cosimulation(exe + "cosimToSignals", **toSigs) assert cosim._fromSignames == [] assert cosim._fromSizes == [] assert cosim._toSignames == toSignames assert cosim._toSizes == toSizes @staticmethod def cosimToSignals(): wt, rf = wtrf() buf = "TO 00 " for s, w in zip(toSignames, toSizes): buf += "%s %s " % (s, w) os.write(wt, to_bytes(buf)) os.read(rf, MAXLINE) os.write(wt, b"FROM 0000") os.read(rf, MAXLINE) os.write(wt, b"START") os.read(rf, MAXLINE) def testFromToSignals(self): cosim = Cosimulation(exe + "cosimFromToSignals", **allSigs) assert cosim._fromSignames == fromSignames assert cosim._fromSizes == fromSizes assert cosim._toSignames == toSignames assert cosim._toSizes == toSizes @staticmethod def cosimFromToSignals(): wt, rf = wtrf() buf = "FROM 00 " for s, w in zip(fromSignames, fromSizes): buf += "%s %s " % (s, w) os.write(wt, to_bytes(buf)) os.read(rf, MAXLINE) buf = "TO 00 " for s, w in zip(toSignames, toSizes): buf += "%s %s " % (s, w) os.write(wt, to_bytes(buf)) os.read(rf, MAXLINE) os.write(wt, b"START") os.read(rf, MAXLINE) def testTimeZero(self): with raises_kind(CosimulationError, _error.TimeZero): Cosimulation(exe + "cosimTimeZero", **allSigs) @staticmethod def cosimTimeZero(): wt, rf = wtrf() buf = "TO 01 " for s, w in zip(fromSignames, fromSizes): buf += "%s %s " % (s, w) os.write(wt, to_bytes(buf)) def testNoComm(self): with raises_kind(CosimulationError, _error.NoCommunication): Cosimulation(exe + "cosimNoComm", **allSigs) @staticmethod def cosimNoComm(): wt, rf = wtrf() os.write(wt, b"FROM 0000") os.read(rf, MAXLINE) os.write(wt, b"TO 0000") os.read(rf, MAXLINE) os.write(wt, b"START ") os.read(rf, MAXLINE) def testFromSignalsDupl(self): with raises_kind(CosimulationError, _error.DuplicateSigNames): Cosimulation(exe + "cosimFromSignalsDupl", **allSigs) @staticmethod def cosimFromSignalsDupl(): wt, rf = wtrf() buf = "FROM 00 " for s, w in zip(fromSignames, fromSizes): buf += "%s %s " % (s, w) buf += "bb 5" os.write(wt, to_bytes(buf)) def testToSignalsDupl(self): with raises_kind(CosimulationError, _error.DuplicateSigNames): Cosimulation(exe + "cosimToSignalsDupl", **allSigs) @staticmethod def cosimToSignalsDupl(): wt, rf = wtrf() buf = "TO 00 " for s, w in zip(toSignames, toSizes): buf += "%s %s " % (s, w) buf += "fff 6" os.write(wt, to_bytes(buf)) def testFromSignalVals(self): cosim = Cosimulation(exe + "cosimFromSignalVals", **allSigs) os.read(cosim._rt, MAXLINE) cosim._hasChange = 1 cosim._put(0) @staticmethod def cosimFromSignalVals(): wt, rf = wtrf() buf = "FROM 00 " for s, w in zip(fromSignames, fromSizes): buf += "%s %s " % (s, w) os.write(wt, to_bytes(buf)) os.read(rf, MAXLINE) os.write(wt, b"TO 0000 a 1") os.read(rf, MAXLINE) os.write(wt, b"START") os.read(rf, MAXLINE) os.write(wt, b"DUMMY") s = os.read(rf, MAXLINE) vals = [int(e, 16) for e in s.split()[1:]] assert vals == fromVals def testToSignalVals(self): cosim = Cosimulation(exe + "cosimToSignalVals", **allSigs) for n in toSignames: assert toSigs[n].next == 0 cosim._get() for n, v in zip(toSignames, toVals): assert toSigs[n].next == v os.write(cosim._wf, b"DUMMY") cosim._getMode = 1 cosim._get() for n in toSignames: assert toSigs[n].next == 0 @staticmethod def cosimToSignalVals(): wt, rf = wtrf() buf = "FROM 00 " for s, w in zip(fromSignames, fromSizes): buf += "%s %s " % (s, w) os.write(wt, to_bytes(buf)) os.read(rf, MAXLINE) buf = "TO 00 " for s, w in zip(toSignames, toSizes): buf += "%s %s " % (s, w) os.write(wt, to_bytes(buf)) os.read(rf, MAXLINE) os.write(wt, b"START") os.read(rf, MAXLINE) buf = "0 " for s, v in zip(toSignames, toVals): buf += s buf += " " buf += hex(v)[2:] buf += " " os.write(wt, to_bytes(buf)) os.read(rf, MAXLINE) buf = "0 " for s, v in zip(toSignames, toXVals): buf += s buf += " " buf += v buf += " " os.write(wt, to_bytes(buf)) if __name__ == "__main__": getattr(TestCosimulation, sys.argv[1])() myhdl-0.11/myhdl/test/core/test_ShadowSignal.py000066400000000000000000000133251347432460400216030ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from myhdl._compat import long def bench_SliceSignal(): s = Signal(intbv(0)[8:]) a, b, c = s(7), s(5), s(0) d, e, f, g = s(8,5), s(6,3), s(8,0), s(4,3) @instance def check(): for i in range(2**len(s)): s.next = i yield delay(10) assert s[7] == a assert s[5] == b assert s[0] == c assert s[8:5] == d assert s[6:3] == e assert s[8:0] == f assert s[4:3] == g return check def test_SliceSignal(): Simulation(bench_SliceSignal()).run() def bench_SliceSlicedSignal(): s = Signal(intbv(0)[8:]) a, b = s(8,4), s(4,0) aa, ab = a(4,2), a(2,0) ba, bb = b(4,2), b(2,0) @instance def check(): for i in range(2**len(s)): s.next = i yield delay(10) assert s[8:6] == aa assert s[6:4] == ab assert s[4:2] == ba assert s[2:0] == bb return check def test_SliceSlicedSignal(): Simulation(bench_SliceSlicedSignal()).run() def bench_ConcatSignal(): a = Signal(intbv(0)[5:]) b = Signal(bool(0)) c = Signal(intbv(0)[3:]) d = Signal(intbv(0)[4:]) s = ConcatSignal(a, b, c, d) @instance def check(): for i in range(2**len(a)): for j in (0, 1): for k in range(2**len(c)): for m in range(2**len(d)): a.next = i b.next = j c.next = k d.next = m yield delay(10) assert s[13:8] == a assert s[7] == b assert s[7:4] == c assert s[4:] == d return check def test_ConcatSignal(): Simulation(bench_ConcatSignal()).run() def bench_ConcatSignalWithConsts(): a = Signal(intbv(0)[5:]) b = Signal(bool(0)) c = Signal(intbv(0)[3:]) d = Signal(intbv(0)[4:]) e = Signal(intbv(0)[1:]) c1 = "10" c2 = '0' c3 = intbv(5)[3:] c4 = bool(1) c5 = intbv(42)[8:] # with leading zeroes s = ConcatSignal(c1, a, c2, b, c3, c, c4, d, c5, e) @instance def check(): for i in range(2**len(a)): for j in (0, 1): for k in range(2**len(c)): for m in range(2**len(d)): for n in range(2**len(e)): a.next = i b.next = j c.next = k d.next = m e.next = n yield delay(10) assert s[29:27] == long(c1, 2) assert s[27:22] == a assert s[21] == long(c2, 2) assert s[20] == b assert s[20:17] == c3 assert s[17:14] == c assert s[13] == c4 assert s[13:9] == d assert s[9:1] == c5 assert s[1:] == e return check def test_ConcatSignalWithConsts(): Simulation(bench_ConcatSignalWithConsts()).run() def bench_ConcatSignalWithNegs(): Am = 2**(5-1) Cm = 2**(3-1) Dm = 2**(4-1) a = Signal(intbv(-1, min=-Am, max=Am)) b = Signal(bool(0)) c = Signal(intbv(-1, min=-Cm, max=Cm)) d = Signal(intbv(-1, min=-Dm, max=Dm)) s = ConcatSignal(a, b, c, d) @instance def check(): for i in range(-Am, Am): for j in (0, 1): for k in range(-Cm, Cm): for m in range(-Dm, Dm): a.next = i b.next = j c.next = k d.next = m yield delay(10) assert s[13:8] == a[len(a):] assert s[7] == b assert s[7:4] == c[len(c):] assert s[4:] == d[len(d):] return check def test_ConcatSignalWithNegs(): Simulation(bench_ConcatSignalWithNegs()).run() def bench_ConcatConcatedSignal(): aa = Signal(intbv(0)[2:0]) ab = Signal(intbv(0)[2:0]) a = ConcatSignal(aa,ab) ba = Signal(intbv(0)[2:0]) bb = Signal(intbv(0)[2:0]) b = ConcatSignal(ba,bb) s = ConcatSignal(a,b) @instance def check(): for iaa in range(2**len(aa)): for iab in range(2**len(ab)): for iba in range(2**len(ba)): for ibb in range(2**len(bb)): aa.next = iaa ab.next = iab ba.next = iba bb.next = ibb yield delay(10) assert s[8:6] == aa assert s[6:4] == ab assert s[4:2] == ba assert s[2:0] == bb return check def test_ConcatConcatedSignal(): Simulation(bench_ConcatConcatedSignal()).run() def bench_TristateSignal(): s = TristateSignal(intbv(0)[8:]) a = s.driver() b = s.driver() c = s.driver() @instance def check(): assert s == None a.next = 1 yield delay(10) assert s == a a.next = None b.next = 122 yield delay(10) assert s == b b.next = None c.next = 233 yield delay(10) assert s == c c.next = None yield delay(10) assert s == None return check def test_TristateSignal(): Simulation(bench_TristateSignal()).run() myhdl-0.11/myhdl/test/core/test_Signal.py000066400000000000000000000441021347432460400204320ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run the unit tests for Signal """ from __future__ import absolute_import import copy import operator import random import sys from random import randrange import pytest from myhdl import Signal, intbv from myhdl._compat import long from myhdl._simulator import _siglist random.seed(1) # random, but deterministic maxint = sys.maxsize class TestSig: def setup_method(self, method): self.vals = [0, 0, 1, 1, 1, 2, 3, 5, intbv(0), intbv(1), intbv(2)] self.nexts = [0, 1, 1, 0, 1, 0, 4, 5, intbv(1), intbv(0), intbv(0)] self.vals += [intbv(0), intbv(1), intbv(0), intbv(1), 2 ] self.nexts += [intbv(0), intbv(1), 1 , 0 , intbv(3) ] self.vals += [ [1,2,3], (1,2,3), {1:1, 2:2}, (0, [2, 3], (1, 2)) ] self.nexts += [ [4,5,6], (4,5,5), {3:3, 4:4}, (1, (0, 1), [2, 3]) ] self.vals += [bool(0), bool(1), bool(0), bool(1), bool(0), bool(1)] self.nexts += [bool(0), bool(1), bool(1), bool(0), 1 , 0 ] self.sigs = [Signal(i) for i in self.vals] self.incompatibleVals = [ [3, 4], (1, 2), 3 , intbv(0), [1] ] self.incompatibleNexts = [ 4 , 3 , "3", (0) , intbv(1) ] self.incompatibleSigs = [Signal(i) for i in self.incompatibleVals] self.eventWaiters = [object() for i in range(3)] self.posedgeWaiters = [object() for i in range(5)] self.negedgeWaiters = [object() for i in range(7)] def testValAttrReadOnly(self): """ val attribute should not be writable""" s1 = Signal(1) with pytest.raises(AttributeError): s1.val = 1 def testDrivenAttrValue(self): """ driven attribute only accepts value 'reg' or 'wire' """ s1 = Signal(1) with pytest.raises(ValueError): s1.driven = "signal" def testPosedgeAttrReadOnly(self): """ posedge attribute should not be writable""" s1 = Signal(1) with pytest.raises(AttributeError): s1.posedge = 1 def testNegedgeAttrReadOnly(self): """ negedge attribute should not be writable""" s1 = Signal(1) with pytest.raises(AttributeError): s1.negedge = 1 def testInitDefault(self): """ initial value is None by default """ s1 = Signal() assert s1 == None def testInitialization(self): """ initial val and next should be equal """ for s in self.sigs: assert s.val == s.next def testUpdate(self): """ _update() should assign next into val """ for s, n in zip(self.sigs, self.nexts): cur = copy.copy(s.val) s.next = n # assigning to next should not change current value ... assert s.val == cur s._update() assert s.val == n def testNextType(self): """ sig.next = n should fail on access if type(n) incompatible """ i = 0 for s in (self.sigs + self.incompatibleSigs): for n in (self.vals + self.incompatibleVals): assert isinstance(s.val, s._type) if isinstance(s.val, (int, long, intbv)): t = (int, long, intbv) else: t = s._type if not isinstance(n, t): i += 1 with pytest.raises((TypeError, ValueError)): oldval = s.val s.next = n assert i >= len(self.incompatibleSigs), "Nothing tested %s" %i def testAfterUpdate(self): """ updated val and next should be equal but not identical """ for s, n in zip(self.sigs, self.nexts): s.next = n s._update() assert s.val == s.next def testModify(self): """ Modifying mutable next should be on a copy """ for s in self.sigs: mutable = 0 try: hash(s.val) except TypeError: mutable = 1 if not mutable: continue if type(s.val) is list: s.next.append(1) elif type(s.val) is dict: s.next[3] = 5 else: s.next # plain read access assert s.val is not s.next, repr(s.val) def testUpdatePosedge(self): """ update on posedge should return event and posedge waiters """ s1 = Signal(1) s1.next = 0 s1._update() s1.next = 1 s1._eventWaiters = self.eventWaiters[:] s1._posedgeWaiters = self.posedgeWaiters[:] s1._negedgeWaiters = self.negedgeWaiters[:] waiters = s1._update() expected = self.eventWaiters + self.posedgeWaiters assert set(waiters) == set(expected) assert s1._eventWaiters == [] assert s1._posedgeWaiters == [] assert s1._negedgeWaiters == self.negedgeWaiters def testUpdateNegedge(self): """ update on negedge should return event and negedge waiters """ s1 = Signal(1) s1.next = 1 s1._update() s1.next = 0 s1._eventWaiters = self.eventWaiters[:] s1._posedgeWaiters = self.posedgeWaiters[:] s1._negedgeWaiters = self.negedgeWaiters[:] waiters = s1._update() expected = self.eventWaiters + self.negedgeWaiters assert set(waiters) == set(expected) assert s1._eventWaiters == [] assert s1._posedgeWaiters == self.posedgeWaiters assert s1._negedgeWaiters == [] def testUpdateEvent(self): """ update on non-edge event should return event waiters """ s1 = Signal(1) s1.next = 4 s1._update() s1.next = 5 s1._eventWaiters = self.eventWaiters[:] s1._posedgeWaiters = self.posedgeWaiters[:] s1._negedgeWaiters = self.negedgeWaiters[:] waiters = s1._update() expected = self.eventWaiters assert set(waiters) == set(expected) assert s1._eventWaiters == [] assert s1._posedgeWaiters == self.posedgeWaiters assert s1._negedgeWaiters == self.negedgeWaiters def testUpdateNoEvent(self): """ update without value change should not return event waiters """ s1 = Signal(1) s1.next = 4 s1._update() s1.next = 4 s1._eventWaiters = self.eventWaiters[:] s1._posedgeWaiters = self.posedgeWaiters[:] s1._negedgeWaiters = self.negedgeWaiters[:] waiters = s1._update() assert waiters == [] assert s1._eventWaiters == self.eventWaiters assert s1._posedgeWaiters == self.posedgeWaiters assert s1._negedgeWaiters == self.negedgeWaiters def testNextAccess(self): """ each next attribute access puts a sig in a global siglist """ del _siglist[:] s = [None] * 4 for i in range(len(s)): s[i] = Signal(i) s[1].next # read access s[2].next = 1 s[2].next s[3].next = 0 s[3].next = 1 s[3].next = 3 for i in range(len(s)): assert _siglist.count(s[i]) == i class TestSignalAsNum: def seqSetup(self, imin, imax, jmin=0, jmax=None): seqi = [imin, imin, 12, 34] seqj = [jmin, 12 , jmin, 34] if not imax and not jmax: l = 2222222222222222222222222222 seqi.append(l) seqj.append(l) # first some smaller ints for n in range(100): ifirstmax = jfirstmax = 100000 if imax: ifirstmax = min(imax, ifirstmax) if jmax: jfirstmax = min(jmax, jfirstmax) i = randrange(imin, ifirstmax) j = randrange(jmin, jfirstmax) seqi.append(i) seqj.append(j) # then some potentially longs for n in range(100): if not imax: i = randrange(maxint) + randrange(maxint) else: i = randrange(imin, imax) if not jmax: j = randrange(maxint) + randrange(maxint) else: j = randrange(jmin, jmax) seqi.append(i) seqj.append(j) self.seqi = seqi self.seqj = seqj def binaryCheck(self, op, imin=0, imax=None, jmin=0, jmax=None): self.seqSetup(imin=imin, imax=imax, jmin=jmin, jmax=jmax) for i, j in zip(self.seqi, self.seqj): bi = Signal(long(i)) bj = Signal(long(j)) ref = op(long(i), j) r1 = op(bi, j) r2 = op(long(i), bj) r3 = op(bi, bj) assert type(r1) == type(ref) assert type(r2) == type(ref) assert type(r3) == type(ref) assert r1 == ref assert r2 == ref assert r3 == ref def augmentedAssignCheck(self, op, imin=0, imax=None, jmin=0, jmax=None): self.seqSetup(imin=imin, imax=imax, jmin=jmin, jmax=jmax) for i, j in zip(self.seqi, self.seqj): bj = Signal(j) ref = long(i) ref = op(ref, j) r1 = bi1 = Signal(i) with pytest.raises(TypeError): r1 = op(r1, j) r2 = long(i) r2 = op(r2, bj) r3 = bi3 = Signal(i) with pytest.raises(TypeError): r3 = op(r3, bj) assert r2 == ref def unaryCheck(self, op, imin=0, imax=None): self.seqSetup(imin=imin, imax=imax) for i in self.seqi: bi = Signal(i) ref = op(i) r1 = op(bi) assert type(r1) == type(ref) assert r1 == ref def conversionCheck(self, op, imin=0, imax=None): self.seqSetup(imin=imin, imax=imax) for i in self.seqi: bi = Signal(i) ref = op(i) r1 = op(bi) assert type(r1) == type(ref) assert r1 == ref def comparisonCheck(self, op, imin=0, imax=None, jmin=0, jmax=None): self.seqSetup(imin=imin, imax=imax, jmin=jmin, jmax=jmax) for i, j in zip(self.seqi, self.seqj): bi = Signal(i) bj = Signal(j) ref = op(i, j) r1 = op(bi, j) r2 = op(i, bj) r3 = op(bi, bj) assert r1 == ref assert r2 == ref assert r3 == ref def testAdd(self): self.binaryCheck(operator.add) def testSub(self): self.binaryCheck(operator.sub) def testMul(self): self.binaryCheck(operator.mul, imax=maxint) # XXX doesn't work for long i??? def testFloorDiv(self): self.binaryCheck(operator.floordiv, jmin=1) def testMod(self): self.binaryCheck(operator.mod, jmin=1) def testPow(self): self.binaryCheck(pow, jmax=64) def testLShift(self): self.binaryCheck(operator.lshift, jmax=256) def testRShift(self): self.binaryCheck(operator.rshift, jmax=256) def testAnd(self): self.binaryCheck(operator.and_) def testOr(self): self.binaryCheck(operator.or_) def testXor(self): self.binaryCheck(operator.xor) def testIAdd(self): self.augmentedAssignCheck(operator.iadd) def testISub(self): self.augmentedAssignCheck(operator.isub) def testIMul(self): self.augmentedAssignCheck(operator.imul, imax=maxint) # XXX doesn't work for long i??? def testIFloorDiv(self): self.augmentedAssignCheck(operator.ifloordiv, jmin=1) def testIMod(self): self.augmentedAssignCheck(operator.imod, jmin=1) def testIPow(self): self.augmentedAssignCheck(operator.ipow, jmax=64) def testIAnd(self): self.augmentedAssignCheck(operator.iand) def testIOr(self): self.augmentedAssignCheck(operator.ior) def testIXor(self): self.augmentedAssignCheck(operator.ixor) def testILShift(self): self.augmentedAssignCheck(operator.ilshift, jmax=256) def testIRShift(self): self.augmentedAssignCheck(operator.irshift, jmax=256) def testNeg(self): self.unaryCheck(operator.neg) def testNeg(self): self.unaryCheck(operator.pos) def testAbs(self): self.unaryCheck(operator.abs) def testInvert(self): self.unaryCheck(operator.inv) def testInt(self): self.conversionCheck(int, imax=maxint) def testLong(self): self.conversionCheck(long) def testFloat(self): self.conversionCheck(float) # XXX __complex__ seems redundant ??? (complex() works as such?) def testOct(self): self.conversionCheck(oct) def testHex(self): self.conversionCheck(hex) def testLt(self): self.comparisonCheck(operator.lt) def testLe(self): self.comparisonCheck(operator.le) def testGt(self): self.comparisonCheck(operator.gt) def testGe(self): self.comparisonCheck(operator.ge) def testEq(self): self.comparisonCheck(operator.eq) def testNe(self): self.comparisonCheck(operator.ne) def getItem(s, i): ext = '0' * (i-len(s)+1) exts = ext + s si = len(exts)-1-i return exts[si] def getSlice(s, i, j): ext = '0' * (i-len(s)+1) exts = ext + s si = len(exts)-i sj = len(exts)-j return exts[si:sj] class TestSignalIntBvIndexing: def seqsSetup(self): seqs = ["0", "1", "000", "111", "010001", "110010010", "011010001110010"] seqs.extend(["0101010101", "1010101010", "00000000000", "11111111111111"]) seqs.append("11100101001001101000101011011101001101") seqs.append("00101011101001011111010100010100100101010001001") self.seqs = seqs seqv = ["0", "1", "10", "101", "1111", "1010"] seqv.extend(["11001", "00111010", "100111100"]) seqv.append("0110101001111010101110011010011") seqv.append("1101101010101101010101011001101101001100110011") self.seqv = seqv def testGetItem(self): self.seqsSetup() for s in self.seqs: n = long(s, 2) sbv = Signal(intbv(n)) sbvi = Signal(intbv(~n)) for i in range(len(s)+20): ref = long(getItem(s, i), 2) res = sbv[i] resi = sbvi[i] assert res == ref assert type(res) == bool assert resi == ref^1 assert type(resi) == bool def testGetSlice(self): self.seqsSetup() for s in self.seqs: n = long(s, 2) sbv = Signal(intbv(n)) sbvi = Signal(intbv(~n)) for i in range(1, len(s)+20): for j in range(0,len(s)+20): try: res = sbv[i:j] resi = sbvi[i:j] except ValueError: assert i<=j continue ref = long(getSlice(s, i, j), 2) assert res == ref assert type(res) == intbv mask = (2**(i-j))-1 assert resi == ref ^ mask assert type(resi) == intbv def testSetItem(self): sbv = Signal(intbv(5)) with pytest.raises(TypeError): sbv[1] = 1 def testSetSlice(self): sbv = Signal(intbv(5)) with pytest.raises(TypeError): sbv[1:0] = 1 class TestSignalNrBits: def testBool(self): if type(bool) is not type : # bool not a type in 2.2 return s = Signal(bool()) assert s._nrbits == 1 def testIntbvSlice(self): for n in range(1, 40): for m in range(0, n): s = Signal(intbv()[n:m]) assert s._nrbits == n-m def testIntbvBounds(self): for n in range(1, 40): s = Signal(intbv(min=-(2**n))) assert s._nrbits == 0 s = Signal(intbv(max=2**n)) assert s._nrbits == 0 s = Signal(intbv(min=0, max=2**n)) assert s._nrbits == n s = Signal(intbv(1, min=1, max=2**n)) assert s._nrbits == n s = Signal(intbv(min=0, max=2**n+1)) assert s._nrbits == n+1 s = Signal(intbv(min=-(2**n), max=2**n-1)) assert s._nrbits == n+1 s = Signal(intbv(min=-(2**n), max=1)) assert s._nrbits == n+1 s = Signal(intbv(min=-(2**n)-1, max=2**n-1)) assert s._nrbits == n+2 class TestSignalBoolBounds: def testSignalBoolBounds(self): if type(bool) is not type: # bool not a type in 2.2 return s = Signal(bool()) s.next = 1 s.next = 0 for v in (-1, -8, 2, 5): with pytest.raises(ValueError): s.next = v class TestSignalIntbvBounds: def testSliceAssign(self): s = Signal(intbv(min=-24, max=34)) for i in (-24, -2, 13, 33): for k in (6, 9, 10): s.next[:] = 0 s.next[k:] = i assert s.next == i for i in (-25, -128, 34, 35, 229): for k in (0, 9, 10): with pytest.raises(ValueError): s.next[k:] = i s = Signal(intbv(5)[8:]) for v in (0, 2**8-1, 100): s.next[:] = v for v in (-1, 2**8, -10, 1000): with pytest.raises(ValueError): s.next[:] = v myhdl-0.11/myhdl/test/core/test_Simulation.py000066400000000000000000000603221347432460400213430ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run unit tests for Simulation """ from __future__ import absolute_import import random from random import randrange from unittest import TestCase from myhdl import (Signal, Simulation, SimulationError, StopSimulation, delay, intbv, join, now) from myhdl._Simulation import _error from helpers import raises_kind random.seed(1) # random, but deterministic QUIET=1 class Shared: pass class SimArgs(TestCase): """ Simulation arguments """ def test1(self): with raises_kind(SimulationError, _error.ArgType): Simulation(None) def test2(self): def g(): yield delay(10) i = g() with raises_kind(SimulationError, _error.DuplicatedArg): Simulation(i, i) class YieldNone(TestCase): """ Basic test of yield None behavior """ def test1(self): def stimulus(): a = Signal(0) yield delay(10) a.next = 1 yield None assert a.val == 0 assert now() == 10 yield delay(0) assert a.val == 1 assert now() == 10 Simulation(stimulus()).run(quiet=QUIET) def test2(self): def stimulus(): a = Signal(0) yield delay(10) a.next = 1 assert a.val == 0 assert now() == 10 yield None a.next = 0 assert a.val == 0 assert now() == 10 yield None a.next = 1 assert a.val == 0 assert now() == 10 yield delay(0) assert a.val == 1 assert now() == 10 Simulation(stimulus()).run(quiet=QUIET) def test3(self): def stimulus(): a = Signal(0) yield delay(10) a.next = 1 yield None, delay(10) assert a.val == 0 assert now() == 10 yield delay(0) assert a.val == 1 assert now() == 10 Simulation(stimulus()).run(quiet=QUIET) def test4(self): def stimulus(): a = Signal(0) yield delay(10) def gen(): yield delay(20) a.next = 1 yield None, gen() assert a.val == 0 assert now() == 10 yield delay(25) assert a.val == 1 Simulation(stimulus()).run(quiet=QUIET) class JoinMix(TestCase): """ Test of joins mixed with other clauses """ def test1(self): def stimulus(): a = Signal(0) def gen(): yield join(delay(10), delay(20)) yield gen(), delay(5) assert now() == 5 yield a raise AssertionError("Incorrect run") # should not get here Simulation(stimulus()).run(quiet=QUIET) def test2(self): def stimulus(): a = Signal(0) yield join(delay(10), delay(20)), delay(5) assert now() == 5 yield a raise AssertionError("Incorrect run") # should not get here Simulation(stimulus()).run(quiet=QUIET) def stimulus(self, a, b, c, d): yield delay(5) a.next = 1 yield delay(5) a.next = 0 b.next = 1 yield delay(5) a.next = 1 b.next = 0 c.next = 1 yield delay(5) a.next = 0 b.next = 1 c.next = 0 d.next = 1 def test3(self): a, b, c, d = [Signal(0) for i in range(4)] def response(): yield join(a, b, c, d) assert now() == 20 Simulation(self.stimulus(a, b, c, d), response()).run(quiet=QUIET) def test4(self): a, b, c, d = [Signal(0) for i in range(4)] def response(): yield join(a, b), join(c, d) assert now() == 10 Simulation(self.stimulus(a, b, c, d), response()).run(quiet=QUIET) def test5(self): a, b, c, d = [Signal(0) for i in range(4)] def response(): yield join(a), b, join(c, d) assert now() == 5 Simulation(self.stimulus(a, b, c, d), response()).run(quiet=QUIET) def test6(self): a, b, c, d = [Signal(0) for i in range(4)] def response(): yield join(a, delay(20)), b, join(c, d) assert now() == 10 Simulation(self.stimulus(a, b, c, d), response()).run(quiet=QUIET) def test7(self): a, b, c, d = [Signal(0) for i in range(4)] def response(): yield join(a, delay(30)), join(c, d) assert now() == 20 Simulation(self.stimulus(a, b, c, d), response()).run(quiet=QUIET) def test8(self): a, b, c, d = [Signal(0) for i in range(4)] def response(): yield join(a, a.negedge) assert now() == 10 Simulation(self.stimulus(a, b, c, d), response()).run(quiet=QUIET) def test9(self): a, b, c, d = [Signal(0) for i in range(4)] def response(): yield join(a, a.negedge, c.posedge) assert now() == 15 Simulation(self.stimulus(a, b, c, d), response()).run(quiet=QUIET) def test10(self): a, b, c, d = [Signal(0) for i in range(4)] def response(): yield join(a, a) assert now() == 5 Simulation(self.stimulus(a, b, c, d), response()).run(quiet=QUIET) def test11(self): a, b, c, d = [Signal(0) for i in range(4)] def response(): yield join(a, b.posedge, b.negedge, a) assert now() == 15 Simulation(self.stimulus(a, b, c, d), response()).run(quiet=QUIET) class JoinedGen(TestCase): """ Basic test of yielding joined concurrent generators """ def bench(self): clk = Signal(0) sig1 = Signal(0) sig2 = Signal(0) td = 10 def gen(s, n): for i in range(n-1): yield delay(td) s.next = 1 yield delay(td) for i in range(10): offset = now() n0 = randrange(1, 50) n1 = randrange(1, 50) n2 = randrange(1, 50) sig1.next = 0 sig2.next = 0 yield join(delay(n0*td), gen(sig1, n1), gen(sig2, n2)) assert sig1.val == 1 assert sig2.val == 1 assert now() == offset + td * max(n0, n1, n2) raise StopSimulation("Joined concurrent generator yield") def testYieldJoinedGen(self): Simulation(self.bench()).run(quiet=QUIET) class SignalUpdateFirst(TestCase): """ Check that signal updates are done first, as in VHDL """ def bench(self): Q = Signal(0, delay=9) R = Signal(0, delay=10) S = Signal(0, delay=11) def process(): Q.next = 0 R.next = 0 S.next = 0 yield delay(50) Q.next = 1 R.next = 1 S.next = 1 yield delay(10) assert Q.val == 1 # control assert R.val == 1 # actual check assert S.val == 0 # control yield delay(1) assert Q.val == 1 # control assert R.val == 1 # control assert S.val == 1 # control raise StopSimulation("Signal update test") return process() def testSignalUpdateFirst(self): Simulation(self.bench()).run(quiet=QUIET) class YieldZeroDelay(TestCase): """ Basic test of yielding a zero delay """ def bench(self): clk = Signal(0) sig1 = Signal(0) sig2 = Signal(0) td = 10 def gen(s, n): s.next = 0 for i in range(n): yield delay(td) s.next = 1 for i in range(100): offset = now() n1 = randrange(2, 10) n2 = randrange(n1+1, 20) # n2 > n1 yield delay(0), gen(sig1, n1), gen(sig2, n2) assert sig1.val == 0 assert sig2.val == 0 assert now() == offset + 0 yield sig1.posedge assert sig2.val == 0 assert now() == offset + n1*td yield sig2.posedge assert now() == offset + n2*td raise StopSimulation("Zero delay yield") def testYieldZeroDelay(self): Simulation(self.bench()).run(quiet=QUIET) class YieldConcurrentGen(TestCase): """ Basic test of yielding concurrent generators """ def bench(self): clk = Signal(0) sig1 = Signal(0) sig2 = Signal(0) td = 10 def gen(s, n): s.next = 0 for i in range(n): yield delay(td) s.next = 1 for i in range(100): offset = now() n1 = randrange(2, 10) n2 = randrange(n1+1, 20) # n2 > n1 yield delay(td), gen(sig1, n1), gen(sig2, n2) assert sig1.val == 0 assert sig2.val == 0 assert now() == offset + td yield sig1.posedge assert sig2.val == 0 assert now() == offset + n1*td yield sig2.posedge assert now() == offset + n2*td raise StopSimulation("Concurrent generator yield") def testYieldConcurrentGen(self): Simulation(self.bench()).run(quiet=QUIET) class YieldGen(TestCase): """ Basic test of yielding generators """ def bench(self): clk = Signal(0) shared = Shared() shared.cnt = 0 shared.i = 0 expected = [] nlists = [] expectedCnt = 0 for i in range(300): l = [] for j in range(randrange(1, 6)): e = randrange(0, 5) l.append(e) expectedCnt += e expected.append(expectedCnt) nlists.append(l) def clkGen(): while 1: yield delay(10) clk.next = 1 yield delay(10) clk.next = 0 def task(nlist): n = nlist.pop(0) for i in range(n): yield clk.posedge shared.cnt += 1 assert shared.cnt == expected[shared.i] shared.i += 1 if nlist: yield task(nlist) def module(): for nlist in nlists: yield task(nlist) assert shared.cnt == expected[-1] raise StopSimulation("Generator yield") return(module(), clkGen()) def testYieldGen(self): Simulation(self.bench()).run(quiet=QUIET) class DeltaCycleOrder(TestCase): """ Check that delta cycle order does not matter """ def bench(self, function): clk = Signal(0) a = Signal(0) b = Signal(0) c = Signal(0) d = Signal(0) z = Signal(0) delta = [Signal(0) for i in range(4)] inputs = Signal(intbv(0)) s = [a, b, c, d] vectors = [intbv(j) for i in range(8) for j in range(16)] random.shuffle(vectors) index = list(range(4)) def clkGen(): while 1: yield delay(10) clk.next ^= 1 def deltaGen(): while 1: yield clk delta[0].next = clk.val yield delta[0] for i in range(1, 4): delta[i].next = delta[i-1].val yield delta[i] def inGen(i): while 1: yield delta[i].posedge s[index[i]].next = inputs.val[index[i]] def logic(): while 1: # yield a, b, c, d z.next = function(a.val, b.val, c.val, d.val) yield a, b, c, d def stimulus(): for v in vectors: inputs.next = v random.shuffle(index) yield clk.posedge yield clk.posedge assert z.val == function(v[0], v[1], v[2], v[3]) raise StopSimulation("Delta cycle order") inputGen = [inGen(i) for i in range(4)] instance = [clkGen(), deltaGen(), logic(), stimulus(), inputGen] return instance def testAnd(self): def andFunction(a, b, c, d): return a & b & c & d Simulation(self.bench(andFunction)).run(quiet=QUIET) def testOr(self): def orFunction(a, b, c, d): return a | b | c | d Simulation(self.bench(orFunction)).run(quiet=QUIET) def testXor(self): def xorFunction(a, b, c, d): return a ^ b ^ c ^ d Simulation(self.bench(xorFunction)).run(quiet=QUIET) def testMux(self): def muxFunction(a, b, c, d): if c: return a else: return b Simulation(self.bench(muxFunction)).run(quiet=QUIET) def testLogic(self): def function(a, b, c, d): return not (a & (not b)) | ((not c) & d) Simulation(self.bench(function)).run(quiet=QUIET) class DeltaCycleRace(TestCase): """ Check that delta cycle races are like in VHDL """ def bench(self): uprange = range(300) msig = Signal(uprange[0]) ssig = [Signal(uprange[-1]) for i in range(2)] dsig = [Signal(uprange[0]) for i in range(2)] clk = Signal(0) deltaClk = Signal(0) shared = Shared() shared.t = now() def clkGen(): for i in uprange[:-1]: yield delay(10) clk.next = 1 yield delay(10) clk.next = 0 def deltaClkGen(): while 1: yield clk deltaClk.next = clk.val def master(): i = 0 while 1: yield clk.posedge msig.next = uprange[i+1] assert msig.val == uprange[i] shared.t = now() i += 1 def slave(ssig): """ Double-check proper operation """ i = 0 while 1: yield clk.posedge ssig.next = msig.val assert ssig.val == uprange[i-1] i += 1 def deltaSlave(dsig): """ Expect delta cycle races """ i = 0 while 1: yield deltaClk.posedge dsig.next = msig.val assert now() == shared.t assert dsig.val == uprange[i] i += 1 return (slave(ssig[1]), deltaSlave(dsig[1]), master(), clkGen(), deltaClkGen(), slave(ssig[0]), deltaSlave(dsig[0])) def testDeltaCycleRace(self): """ Check delta cycle races """ bench = self.bench() Simulation(bench).run(quiet=QUIET) class DelayLine(TestCase): """ Check that delay lines work properly """ def bench(self): uprange = range(500) sig_Z = [Signal(uprange[-i]) for i in range(7)] clk = Signal(0) def clkGen(): for i in uprange[:-1]: yield delay(10) clk.next = 1 yield delay(10) clk.next = 0 def delayElement(n, i): sig_Z[n].next = sig_Z[n-1].val assert sig_Z[n].val == uprange[i-n] def stage(n): i = 0 while 1: yield clk.posedge delayElement(n, i) i += 1 def stage012(): i = 0 while 1: yield clk.posedge delayElement(1, i) sig_Z[0].next = uprange[i+1] delayElement(2, i) i += 1 return [stage(6), stage(4), clkGen(), stage(3), stage012(), stage(5)] def testZeroDelay(self): """ Zero delay behavior """ bench = self.bench() Simulation(bench).run(quiet=QUIET) def initSignal(waveform): interval, val, sigdelay = waveform[0] if sigdelay: return Signal(val=val, delay=sigdelay) else: return Signal(val=val) def isPosedge(oldval, val): return not oldval and val def isNegedge(oldval, val): return oldval and not val def isEvent(oldval, val): return oldval != val def isEdge(oldval, val): return isPosedge(oldval, val) or isNegedge(oldval, val) def getExpectedTimes(waveform, eventCheck): interval, val, sigdelay = waveform[0] # print waveform[0] expected = [] time = interval oldval = val i = 1 while i < len(waveform): interval, val, sigdelay = waveform[i] # print waveform[i] time += interval # check future events within inertial delay interval j = i+1 inctime = 0 while j < len(waveform) and inctime + waveform[j][0] < sigdelay: inctime += waveform[j][0] newval = waveform[j][1] newsigdelay = waveform[j][2] if newval != val: # cancel event break else: # same vals if inctime + newsigdelay < sigdelay: # special case: there is a later event, with same val, # but smaller delay: presumably, this should win, # so cancel the present one break j += 1 else: # if event was not cancelled by a break if eventCheck(oldval, val): expected.append(time + sigdelay) # print expected[-1] oldval = val i += 1 # print expected return expected class Waveform(TestCase): """ Test of all sorts of event response in a waveform """ waveform = [] duration = 0 sigdelay = 0 for i in range(2000): interval = randrange(0, 150) val = randrange(0, 4) waveform.append((interval, val, sigdelay)) duration = interval + duration def stimulus(self): for interval, val, sigdelay in self.waveform: yield delay(interval) self.sig.next = val if sigdelay: self.sig.delay = sigdelay def response(self, clause, expected): assert len(expected) > 100 # we should test something i = 0 while 1: yield clause assert now() == expected[i] i += 1 def setUp(self): self.sig = initSignal(self.waveform) def runSim(self, sim): sim.run(quiet=QUIET) def testPosedge(self): """ Posedge waveform test """ s = self.sig stimulus = self.stimulus() expected = getExpectedTimes(self.waveform, isPosedge) response = self.response(clause=s.posedge, expected=expected) self.runSim(Simulation(stimulus, response)) assert self.duration <= now() def testNegedge(self): """ Negedge waveform test """ s = self.sig stimulus = self.stimulus() expected = getExpectedTimes(self.waveform, isNegedge) response = self.response(clause=s.negedge, expected=expected) self.runSim(Simulation(stimulus, response)) assert self.duration <= now() def testEdge(self): """ Edge waveform test """ s = self.sig stimulus = self.stimulus() expected = getExpectedTimes(self.waveform, isEdge) response = self.response(clause=(s.negedge, s.posedge), expected=expected) self.runSim(Simulation(stimulus, response)) assert self.duration <= now() def testEvent(self): """ Event waveform test """ s = self.sig stimulus = self.stimulus() expected = getExpectedTimes(self.waveform, isEvent) # print expected response = self.response(clause=s, expected=expected) self.runSim(Simulation(stimulus, response)) assert self.duration <= now() def testRedundantEvents(self): """ Redundant event waveform test """ s = self.sig stimulus = self.stimulus() expected = getExpectedTimes(self.waveform, isEvent) response = self.response(clause=(s,) * 6, expected=expected) self.runSim(Simulation(stimulus, response)) assert self.duration <= now() def testRedundantEventAndEdges(self): """ Redundant edge waveform test """ s = self.sig stimulus = self.stimulus() expected = getExpectedTimes(self.waveform, isEvent) response = self.response(clause=(s, s.negedge, s.posedge), expected=expected) self.runSim(Simulation(stimulus, response)) assert self.duration <= now() def testRedundantPosedges(self): """ Redundant posedge waveform test """ s = self.sig stimulus = self.stimulus() expected = getExpectedTimes(self.waveform, isPosedge) response = self.response(clause=(s.posedge,) * 3, expected=expected) self.runSim(Simulation(stimulus, response)) assert self.duration <= now() def testRedundantNegedges(self): """ Redundant negedge waveform test """ s = self.sig stimulus = self.stimulus() expected = getExpectedTimes(self.waveform, isNegedge) response = self.response(clause=(s.negedge,) * 9, expected=expected) self.runSim(Simulation(stimulus, response)) assert self.duration <= now() class WaveformSigDelay(Waveform): """ Repeat waveform tests with a delayed signal """ waveform = [] duration = 0 sigdelay = 0 for i in range(2000): interval = randrange(20, 150) val = randrange(0, 4) sigdelay = randrange(1, 20) waveform.append((interval, val, sigdelay)) duration += interval class WaveformInertialDelay(Waveform): """ Repeat waveform tests to check inertial delay """ waveform = [] duration = 0 sigdelay = 0 for i in range(2000): interval = randrange(3, 10) val = randrange(0, 3) sigdelay = randrange(1, 5) waveform.append((interval, val, sigdelay)) duration += interval class WaveformInertialDelayStress(Waveform): """ Repeat waveform tests to stress inertial delay """ waveform = [] duration = 0 sigdelay = 0 for i in range(2000): interval = randrange(1, 3) val = randrange(0, 3) sigdelay = randrange(1, 3) waveform.append((interval, val, sigdelay)) duration += interval class SimulationRunMethod(Waveform): """ Basic test of run method of Simulation object """ def runSim(self, sim): duration = randrange(1, 300) while sim.run(duration, quiet=QUIET): duration = randrange(1, 300) class TimeZeroEvents(TestCase): """ Check events at time 0 """ def bench(self, sig, next, clause, timeout=1): val = sig.val def stimulus(): sig.next = next yield delay(10) def response(): yield clause, delay(timeout) assert now() == 0 assert sig.val == next return [stimulus(), response()] def testEvent(self): """ Event at time 0 """ s = Signal(0) testBench = self.bench(sig=s, next=1, clause=s) Simulation(testBench).run(quiet=QUIET) def testPosedge(self): """ Posedge at time 0 """ s = Signal(0) testBench = self.bench(sig=s, next=1, clause=s.posedge) Simulation(testBench).run(quiet=QUIET) def testNegedge(self): """ Negedge at time 0 """ s = Signal(1) testBench = self.bench(sig=s, next=0, clause=s.negedge) Simulation(testBench).run(quiet=QUIET) myhdl-0.11/myhdl/test/core/test_always.py000066400000000000000000000106521347432460400205200ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this librardy; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run the unit tests for the @always decorator """ from __future__ import absolute_import from random import randrange from myhdl import (AlwaysError, Signal, Simulation, StopSimulation, delay, instances, intbv, now) from myhdl._always import _error, always from myhdl._Waiter import (_DelayWaiter, _EdgeTupleWaiter, _EdgeWaiter, _SignalTupleWaiter, _SignalWaiter, _Waiter) from helpers import raises_kind # random.seed(3) # random, but deterministic QUIET=1 def g(): pass x = Signal(0) class TestAlwaysCompilation: def testArgIsFunction(self): h = 5 with raises_kind(AlwaysError, _error.ArgType): always(delay(3))(h) def testArgIsNormalFunction(self): with raises_kind(AlwaysError, _error.ArgType): @always(delay(3)) def h(): yield None def testArgHasNoArgs(self): with raises_kind(AlwaysError, _error.NrOfArgs): @always(delay(3)) def h(n): return n def testDecArgType1(self): with raises_kind(AlwaysError, _error.DecArgType): @always def h(n): return n def testDecArgType2(self): with raises_kind(AlwaysError, _error.DecArgType): @always(g) def h(n): return n def SignalFunc1(a, b, c, d, r): @always(a) def logic(): r.next = a + b + c + d return logic def SignalTupleFunc1(a, b, c, d, r): @always(a, b, c) def logic(): r.next = a + b + c + d return logic def DelayFunc(a, b, c, d, r): @always(delay(3)) def logic(): r.next = a + b + c + d return logic def EdgeFunc1(a, b, c, d, r): @always(c.posedge) def logic(): r.next = a + b + c + d return logic def EdgeTupleFunc1(a, b, c, d, r): @always(c.posedge, d.negedge) def logic(): r.next = a + b + c + d return logic def GeneralFunc(a, b, c, d, r): @always(c.posedge, d) def logic(): r.next = a + b + c + d return logic class TestInferWaiter: def bench(self, MyHDLFunc, waiterType): a, b, c, d, r, s = [Signal(intbv(0)) for i in range(6)] inst_r = MyHDLFunc(a, b, c, d, r) assert type(inst_r.waiter) == waiterType inst_s = MyHDLFunc(a, b, c, d, s) def stimulus(): for i in range(1000): yield delay(randrange(1, 10)) if randrange(2): a.next = randrange(32) if randrange(2): b.next = randrange(32) c.next = randrange(2) d.next = randrange(2) raise StopSimulation def check(): while 1: yield a, b, c, r, s assert r == s return inst_r, _Waiter(inst_s.gen), _Waiter(stimulus()), _Waiter(check()) def testSignal1(self): sim = Simulation(self.bench(SignalFunc1, _SignalWaiter)) sim.run() def testSignalTuple1(self): sim = Simulation(self.bench(SignalTupleFunc1, _SignalTupleWaiter)) sim.run() def testDelay(self): sim = Simulation(self.bench(DelayFunc, _DelayWaiter)) sim.run() def testEdge1(self): sim = Simulation(self.bench(EdgeFunc1, _EdgeWaiter)) sim.run() def testEdgeTuple1(self): sim = Simulation(self.bench(EdgeTupleFunc1, _EdgeTupleWaiter)) sim.run() def testGeneral(self): sim = Simulation(self.bench(GeneralFunc, _Waiter)) sim.run() myhdl-0.11/myhdl/test/core/test_always_comb.py000066400000000000000000000244601347432460400215220ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run the unit tests for always_comb """ from __future__ import absolute_import import random from random import randrange from myhdl import (AlwaysCombError, Signal, Simulation, StopSimulation, delay, instances, intbv, now) from myhdl._always_comb import _error, always_comb from myhdl._Waiter import _SignalTupleWaiter, _SignalWaiter, _Waiter from helpers import raises_kind # random.seed(3) # random, but deterministic QUIET=1 def g(): pass x = Signal(0) class TestAlwaysCombCompilation: def testArgIsFunction(self): h = 5 with raises_kind(AlwaysCombError, _error.ArgType): always_comb(h) def testArgIsNormalFunction(self): def h(): yield None with raises_kind(AlwaysCombError, _error.ArgType): always_comb(h) def testArgHasNoArgs(self): def h(n): return n with raises_kind(AlwaysCombError, _error.NrOfArgs): always_comb(h) ## def testScope(self): ## try: ## always_comb(g) ## except AlwaysCombError, e: ## self.assertEqual(e.kind, _error.Scope) ## else: ## self.fail() def testInfer1(self): a, b, c, d = [Signal(0) for i in range(4)] u = 1 def h(): c.next = a v = u g = always_comb(h).gen i = g.gi_frame.f_locals['self'] expected = set(['a']) assert i.inputs == expected def testInfer2(self): a, b, c, d = [Signal(0) for i in range(4)] u = 1 def h(): c.next = x g = a g = always_comb(h).gen i = g.gi_frame.f_locals['self'] expected = set(['a', 'x']) assert i.inputs == expected def testInfer3(self): a, b, c, d = [Signal(0) for i in range(4)] u = 1 def h(): c.next = a + x + u a = 1 g = always_comb(h).gen i = g.gi_frame.f_locals['self'] expected = set(['x']) assert i.inputs == expected def testInfer4(self): a, b, c, d = [Signal(0) for i in range(4)] u = 1 def h(): c.next = a + x + u x = 1 g = always_comb(h).gen i = g.gi_frame.f_locals['self'] expected = set(['a']) assert i.inputs == expected def testInfer5(self): a, b, c, d = [Signal(0) for i in range(4)] def h(): c.next += 1 a += 1 with raises_kind(AlwaysCombError, _error.SignalAsInout % set('c')): g = always_comb(h).gen def testInfer6(self): a, b, c, d = [Signal(0) for i in range(4)] def h(): c.next = a x.next = c with raises_kind(AlwaysCombError, _error.SignalAsInout % set('c')): g = always_comb(h).gen def testInfer7(self): a, b, c, d = [Signal(0) for i in range(4)] def h(): c.next[a:0] = x[b:0] g = always_comb(h).gen i = g.gi_frame.f_locals['self'] expected = set(['a', 'b', 'x']) assert i.inputs == expected def testInfer8(self): a, b, c, d = [Signal(0) for i in range(4)] u = 1 def h(): v = 2 c.next[8:1+a+v] = x[4:b*3+u] g = always_comb(h).gen i = g.gi_frame.f_locals['self'] expected = set(['a', 'b', 'x']) assert i.inputs == expected def testInfer9(self): a, b, c, d = [Signal(0) for i in range(4)] def h(): c.next[a-1] = x[b-1] g = always_comb(h).gen i = g.gi_frame.f_locals['self'] expected = set(['a', 'b', 'x']) assert i.inputs == expected def testInfer10(self): a, b, c, d = [Signal(0) for i in range(4)] def f(x, y, z): return 0 def h(): c.next = f(a, 2*b, d*x) g = always_comb(h).gen i = g.gi_frame.f_locals['self'] expected = set(['a', 'b', 'd', 'x']) assert i.inputs == expected def testEmbeddedFunction(self): a, b, c, d = [Signal(0) for i in range(4)] u = 1 def h(): def g(): e = b return e c.next = x g = a with raises_kind(AlwaysCombError, _error.EmbeddedFunction): g = always_comb(h) class TestAlwaysCombSimulation1: def bench(self, function): clk = Signal(0) a = Signal(0) b = Signal(0) c = Signal(0) d = Signal(0) z = Signal(0) vectors = [intbv(j) for i in range(32) for j in range(16)] random.shuffle(vectors) def combFunc(): if __debug__: f = x x.next = function(a, b, c, d) comb = always_comb(combFunc) def clkGen(): while 1: yield delay(10) clk.next ^= 1 def logic(): while 1: z.next = function(a, b, c, d) yield a, b, c, d def stimulus(): for v in vectors: a.next = v[0] b.next = v[1] c.next = v[2] d.next = v[3] yield clk.posedge yield clk.negedge assert x == z raise StopSimulation("always_comb simulation test") return instances() def testAnd(self): def andFunction(a, b, c, d): return a & b & c & d Simulation(self.bench(andFunction)).run(quiet=QUIET) def testOr(self): def orFunction(a, b, c, d): return a | b | c | d Simulation(self.bench(orFunction)).run(quiet=QUIET) def testXor(self): def xorFunction(a, b, c, d): return a ^ b ^ c ^ d Simulation(self.bench(xorFunction)).run(quiet=QUIET) def testMux(self): def muxFunction(a, b, c, d): if c: return a else: return b Simulation(self.bench(muxFunction)).run(quiet=QUIET) def testLogic(self): def function(a, b, c, d): return not (a & (not b)) | ((not c) & d) Simulation(self.bench(function)).run(quiet=QUIET) class TestAlwaysCombSimulation2: def bench(self, funcName="and"): clk = Signal(0) a = Signal(0) b = Signal(0) c = Signal(0) d = Signal(0) k = Signal(0) z = Signal(0) x = Signal(0) vectors = [intbv(j) for i in range(32) for j in range(16)] random.shuffle(vectors) def andFunc(): x.next = a & b & c & d def andGenFunc(): while 1: z.next = a & b & c & d yield a, b, c, d def orFunc(): x.next = a | b | c | d def orGenFunc(): while 1: z.next = a | b | c | d yield a, b, c, d def logicFunc(): x.next = not (a & (not b)) | ((not c) & d) def logicGenFunc(): while 1: z.next = not (a & (not b)) | ((not c) & d) yield a, b, c, d def incFunc(): x.next = k + 1 def incGenFunc(): while 1: z.next = k + 1 yield k combFunc = eval(funcName + "Func") comb = always_comb(combFunc) genFunc = eval(funcName + "GenFunc") gen = genFunc() def clkGen(): while 1: yield delay(10) clk.next ^= 1 def stimulus(): for v in vectors: a.next = v[0] b.next = v[1] c.next = v[2] d.next = v[3] k.next = v yield clk.posedge yield clk.negedge assert x == z raise StopSimulation("always_comb simulation test") return comb, gen, clkGen(), stimulus() def testAnd(self): Simulation(self.bench("and")).run(quiet=QUIET) def testOr(self): Simulation(self.bench("or")).run(quiet=QUIET) def testLogic(self): Simulation(self.bench("logic")).run(quiet=QUIET) def testInc(self): Simulation(self.bench("inc")).run(quiet=QUIET) def SignalGen1(a, b, c, d, r): @always_comb def logic(): r.next = a return logic def SignalTupleGen1(a, b, c, d, r): @always_comb def logic(): r.next = a + b + c return logic class TestInferWaiter: def bench(self, MyHDLFunc, waiterType): a, b, c, d, r, s = [Signal(intbv(0)) for i in range(6)] inst_r = MyHDLFunc(a, b, c, d, r) assert type(inst_r.waiter) == waiterType inst_s = MyHDLFunc(a, b, c, d, s) def stimulus(): for i in range(1000): yield delay(randrange(1, 10)) if randrange(2): a.next = randrange(32) if randrange(2): b.next = randrange(32) c.next = randrange(2) d.next = randrange(2) raise StopSimulation def check(): while 1: yield a, b, c, r, s assert r == s return inst_r, _Waiter(inst_s.gen), _Waiter(stimulus()), _Waiter(check()) def testSignal1(self): sim = Simulation(self.bench(SignalGen1, _SignalWaiter)) sim.run() def testSignalTuple1(self): sim = Simulation(self.bench(SignalTupleGen1, _SignalTupleWaiter)) sim.run() myhdl-0.11/myhdl/test/core/test_always_seq.py000066400000000000000000000022431347432460400213650ustar00rootroot00000000000000import myhdl from myhdl import * from myhdl import Signal from myhdl._always_seq import AlwaysSeqError, _error, always_seq from helpers import raises_kind def test_clock(): """ check the edge parameter """ # should fail without a valid Signal clock = Signal(bool(0)) reset = ResetSignal(0, active=0, isasync=True) with raises_kind(AlwaysSeqError, _error.EdgeType): @always_seq(clock, reset=reset) def logic1(): pass # should work with a valid Signal clock = Signal(bool(0)) try: @always_seq(clock.posedge, reset=reset) def logic2(): pass except: assert False def test_reset(): """ check the reset parameter """ # should fail without a valid ResetSignal clock = Signal(bool(0)) reset = Signal(bool(0)) with raises_kind(AlwaysSeqError, _error.ResetType): @always_seq(clock.posedge, reset=reset) def logic(): pass # should work with a valid Signal reset = ResetSignal(0, active=0, isasync=True) try: @always_seq(clock.posedge, reset=reset) def logic2(): pass except: assert False myhdl-0.11/myhdl/test/core/test_bin.py000066400000000000000000000054051347432460400177700ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run the unit tests for bin """ from __future__ import absolute_import import random import sys from random import randrange from myhdl import bin from myhdl._compat import long random.seed(1) # random, but deterministic SIZE = 100 def _int2bitstring(num): if num == 0: return '0' if abs(num) == 1: return '1' return _int2bitstring(num // 2) + _int2bitstring(num % 2) def binref(num, width=0): """Return a binary string representation. num -- number to convert Optional parameter: width -- specifies the desired string (sign bit padding) """ num = long(num) s = _int2bitstring(num) if width: pad = '0' if num < 0: pad = '1' return (width - len(s)) * pad + s return s class TestBin: def testSmall(self): for i in range(-65, 65): assert bin(i) == binref(i) def testSmallWidth(self): for i in range(-65, 65): w = randrange(1, 8) assert bin(i, w) == binref(i, w) def testRandomInt(self): for j in range(SIZE): i = randrange(-sys.maxsize, sys.maxsize) assert bin(i) == binref(i) def testRandomIntWidth(self): for j in range(SIZE): w = randrange(1, 1000) i = randrange(-sys.maxsize, sys.maxsize) assert bin(i, w) == binref(i, w) def testRandomLong(self): for j in range(SIZE): k = randrange(sys.maxsize) i = k + sys.maxsize assert bin(i) == binref(i) i = -k - sys.maxsize assert bin(i) == binref(i) def testRandomLongWith(self): for j in range(SIZE): w = randrange(1, 1000) k = randrange(sys.maxsize) i = k + sys.maxsize assert bin(i, w) == binref(i, w) i = -k - sys.maxsize assert bin(i, w) == binref(i, w) myhdl-0.11/myhdl/test/core/test_concat.py000066400000000000000000000210051347432460400204610ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run the concatunit tests. """ from __future__ import absolute_import import operator import random from functools import reduce import pytest from myhdl._compat import long from myhdl._concat import concat from myhdl._intbv import intbv from myhdl._Signal import Signal random.seed(2) # random, but deterministic class TestConcat: bases = ("0", "1", "10101", "01010", "110", "011", "1001000100001011111000") extslist = [ ["0"], ["1"], ["00"], ["11"], ["000"], ["111"], ["1010101010"], ["0", "1"], ["1", "0"], ["1", "01", "10"], ["11111", "001001"], ["110001111101110", "10101110111001001", "111001101000101010"], ["1100", "1", "01001", "0", "10", "01", "0", "0", "11", "1" ] ] def ConcatToSizedBase(self, bases, extslist): for base, basestr in zip(bases, self.bases): for exts, extstr in zip(extslist, self.extslist): bv = concat(base, *exts) refstr = basestr + reduce(operator.add, extstr) reflen = len(refstr) ref = long(refstr, 2) assert bv == ref assert len(bv) == reflen def ConcatToUnsizedBase(self, bases, extslist): for base, basestr in zip(bases, self.bases): for exts, extstr in zip(extslist, self.extslist): bv = concat(base, *exts) refstr = basestr + reduce(operator.add, extstr) ref = long(refstr, 2) assert bv == ref assert len(bv) == 0 def testConcatStringsToString(self): bases = self.bases extslist = self.extslist self.ConcatToSizedBase(bases, extslist) def testConcatStringsToInt(self): bases = [long(base, 2) for base in self.bases] extslist = self.extslist self.ConcatToUnsizedBase(bases, extslist) def testConcatStringsToSignalInt(self): bases = [Signal(long(base, 2)) for base in self.bases] extslist = self.extslist self.ConcatToUnsizedBase(bases, extslist) def testConcatStringsToIntbv(self): bases = [intbv(base) for base in self.bases] extslist = self.extslist self.ConcatToSizedBase(bases, extslist) def testConcatStringsToSignalIntbv(self): bases = [Signal(intbv(base)) for base in self.bases] extslist = self.extslist self.ConcatToSizedBase(bases, extslist) def testConcatStringsToBool(self): if type(bool) is not type: return bases = [] for base in self.bases: if len(base) == 1: bases.append(bool(int(base))) else: bases.append(intbv(base)) extslist = self.extslist self.ConcatToSizedBase(bases, extslist) def testConcatStringsToSignalBool(self): if type(bool) is not type: return bases = [] for base in self.bases: if len(base) == 1: bases.append(Signal(bool(int(base)))) else: bases.append(intbv(base)) extslist = self.extslist self.ConcatToSizedBase(bases, extslist) def testConcatIntbvsToIntbv(self): bases = [intbv(base) for base in self.bases] extslist = [] for exts in self.extslist: extslist.append([intbv(ext) for ext in exts]) self.ConcatToSizedBase(bases, extslist) def testConcatSignalIntbvsToIntbv(self): bases = [intbv(base) for base in self.bases] extslist = [] for exts in self.extslist: extslist.append([Signal(intbv(ext)) for ext in exts]) self.ConcatToSizedBase(bases, extslist) def testConcatIntbvsToSignalIntbv(self): bases = [Signal(intbv(base)) for base in self.bases] extslist = [] for exts in self.extslist: extslist.append([intbv(ext) for ext in exts]) self.ConcatToSizedBase(bases, extslist) def testConcatSignalIntbvsToSignalIntbv(self): bases = [Signal(intbv(base)) for base in self.bases] extslist = [] for exts in self.extslist: extslist.append([Signal(intbv(ext)) for ext in exts]) self.ConcatToSizedBase(bases, extslist) def testConcatIntbvsToInt(self): bases = [long(base, 2) for base in self.bases] extslist = [] for exts in self.extslist: extslist.append([intbv(ext) for ext in exts]) self.ConcatToUnsizedBase(bases, extslist) def testConcatSignalIntbvsToInt(self): bases = [long(base, 2) for base in self.bases] extslist = [] for exts in self.extslist: extslist.append([Signal(intbv(ext)) for ext in exts]) self.ConcatToUnsizedBase(bases, extslist) def testConcatIntbvsToSignalInt(self): bases = [Signal(long(base, 2)) for base in self.bases] extslist = [] for exts in self.extslist: extslist.append([intbv(ext) for ext in exts]) self.ConcatToUnsizedBase(bases, extslist) def testConcatSignalIntbvsToSignalInt(self): bases = [Signal(long(base, 2)) for base in self.bases] extslist = [] for exts in self.extslist: extslist.append([Signal(intbv(ext)) for ext in exts]) self.ConcatToUnsizedBase(bases, extslist) def testConcatIntbvsBoolsToIntbv(self): if type(bool) is not type: return bases = [intbv(base) for base in self.bases] extslist = [] for exts in self.extslist: newexts = [] for ext in exts: if len(ext) == 1: newexts.append(bool(int(ext))) else: newexts.append(intbv(ext)) extslist.append(newexts) self.ConcatToSizedBase(bases, extslist) def testConcatMixToSizedBase(self): bases = [] for base in self.bases: seq = (base, intbv(base), Signal(intbv(base))) bases.append(random.choice(seq)) extslist = [] for exts in self.extslist: newexts = [] for ext in exts: seq = (ext, intbv(ext), Signal(intbv(ext))) newexts.append(random.choice(seq)) extslist.append(newexts) self.ConcatToSizedBase(bases, extslist) def testConcatMixToUnsizedBase(self): bases = [] for base in self.bases: seq = (long(base, 2), Signal(long(base, 2))) bases.append(random.choice(seq)) extslist = [] for exts in self.extslist: newexts = [] for ext in exts: seq = (ext, intbv(ext), Signal(intbv(ext))) newexts.append(random.choice(seq)) extslist.append(newexts) self.ConcatToUnsizedBase(bases, extslist) def testConcatMixBoolToSizedBase(self): if type(bool) is not type: return bases = [] for base in self.bases: seq = (base, intbv(base), Signal(intbv(base))) bases.append(random.choice(seq)) extslist = [] for exts in self.extslist: newexts = [] for ext in exts: if len(ext) == 1: seq = (ext, bool(int(ext)), Signal(bool(int(ext)))) else: seq = (ext, intbv(ext), Signal(intbv(ext))) newexts.append(random.choice(seq)) extslist.append(newexts) self.ConcatToSizedBase(bases, extslist) def testWrongType(self): a = intbv(4) with pytest.raises(TypeError): concat(a, 5) def testUnsizedConcat(self): a = intbv(4) b = intbv(5) with pytest.raises(TypeError): concat(a, b) myhdl-0.11/myhdl/test/core/test_enum.py000066400000000000000000000050651347432460400201660ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run the unit tests for enum """ from __future__ import absolute_import import copy import random import pytest from myhdl import enum random.seed(1) # random, but deterministic t_State = enum("SEARCH", "CONFIRM", "SYNC") t_Homograph = enum("SEARCH", "CONFIRM", "SYNC") t_incomplete = enum("SEARCH", "CONFIRM") class TestEnum: def testUniqueLiterals(self): with pytest.raises(ValueError): t_State = enum("SEARCH", "CONFIRM", "SEARCH") def testWrongAttr(self): with pytest.raises(AttributeError): t_State.TYPO def testAttrAssign(self): with pytest.raises(AttributeError): t_State.SEARCH = 4 def testWrongAttrAssign(self): with pytest.raises(AttributeError): t_State.TYPO = 4 def testHomograph(self): assert t_State is not t_Homograph def testHomographLiteral(self): assert t_State.SEARCH is not t_Homograph.SEARCH def testItemCopy(self): e = copy.deepcopy(t_State.SEARCH) assert e == t_State.SEARCH assert e != t_State.CONFIRM ## Adding test coverage for encoding in enum def testItemNotDeepCopy(self): e = copy.copy(t_State.SEARCH) assert e == t_State.SEARCH assert e != t_State.CONFIRM def testWrongEncoding(self): def logic1(encoding): t_State = enum("SEARCH", "CONFIRM", "SYNC",encoding=encoding) with pytest.raises(ValueError): logic1(encoding) def testNotStringtype(self): with pytest.raises(TypeError): t_State = enum("SEARCH", 1, "SYNC") def testEnumLength(self): l = len(t_State) assert l == len(t_State) myhdl-0.11/myhdl/test/core/test_inferWaiter.py000066400000000000000000000126621347432460400215020ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run the unit tests for inferWaiter """ from __future__ import absolute_import import random from random import randrange from types import GeneratorType import myhdl from myhdl import * from myhdl._Waiter import (_DelayWaiter, _EdgeTupleWaiter, _EdgeWaiter, _inferWaiter, _SignalTupleWaiter, _SignalWaiter, _Waiter) random.seed(1) # random, but deterministic QUIET=1 def SignalFunc1(a, b, c, d, r): @instance def logic(): while 1: yield a r.next = a + b + c return logic def SignalFunc2(a, b, c, d, r): def logic(a, r): while 1: yield a r.next = a - b + c return logic(a, r) def SignalTupleFunc1(a, b, c, d, r): @instance def logic(): while 1: yield a, b, c r.next = a + b + c return logic def SignalTupleFunc2(a, b, c, d, r): def logic(a, r): while 1: yield a, b, c r.next = a - b + c return logic(a, r) def DelayFunc(a, b, c, d, r): @instance def logic(): while 1: yield delay(3) r.next = a + b + c return logic def EdgeFunc1(a, b, c, d, r): @instance def logic(): while 1: yield c.posedge r.next = a + b + c return logic def EdgeFunc2(a, b, c, d, r): def logic(c, r): while 1: yield c.negedge r.next = a + b + c if a > 5: yield c.posedge r.next = a - b -c else: r.next = a + b - c return logic(c, r) def EdgeTupleFunc1(a, b, c, d, r): @instance def logic(): while 1: yield c.posedge, d.negedge r.next = a + b + c return logic def EdgeTupleFunc2(a, b, c, d, r): def logic(c, r): while 1: yield c.negedge, d.posedge r.next = a + b + c if a > 5: yield c.posedge, d.negedge r.next = a - b -c else: r.next = a + b - c return logic(c, r) def GeneralFunc(a, b, c, d, r): def logic(c, r): while 1: yield c.negedge, d.posedge r.next = a + b + c if a > 5: yield c, d.negedge r.next = a - b -c else: r.next = a + b - c return logic(c, r) class TestInferWaiter: def bench(self, genFunc, waiterType): a, b, c, d, r, s = [Signal(intbv(0)) for i in range(6)] gen_inst_r = genFunc(a, b, c, d, r) if not isinstance(gen_inst_r, GeneratorType): # decorator type gen_inst_r = gen_inst_r.gen assert type(_inferWaiter(gen_inst_r)) == waiterType gen_inst_s = genFunc(a, b, c, d, s) if not isinstance(gen_inst_s, GeneratorType): # decorator type gen_inst_s = gen_inst_s.gen def stimulus(): for i in range(1000): yield delay(randrange(1, 10)) if randrange(2): a.next = randrange(32) if randrange(2): b.next = randrange(32) c.next = randrange(2) d.next = randrange(2) raise StopSimulation def check(): while 1: yield a, b, c, r, s assert r == s return gen_inst_r, _Waiter(gen_inst_s), _Waiter(stimulus()), _Waiter(check()) def testSignal1(self): sim = Simulation(self.bench(SignalFunc1, _SignalWaiter)) sim.run() def testSignal2(self): sim = Simulation(self.bench(SignalFunc2, _SignalWaiter)) sim.run() def testSignalTuple1(self): sim = Simulation(self.bench(SignalTupleFunc1, _SignalTupleWaiter)) sim.run() def testSignalTuple2(self): sim = Simulation(self.bench(SignalTupleFunc2, _SignalTupleWaiter)) sim.run() def testDelay(self): sim = Simulation(self.bench(DelayFunc, _DelayWaiter)) sim.run() def testEdge1(self): sim = Simulation(self.bench(EdgeFunc1, _EdgeWaiter)) sim.run() def testEdge2(self): sim = Simulation(self.bench(EdgeFunc2, _EdgeWaiter)) sim.run() def testEdgeTuple1(self): sim = Simulation(self.bench(EdgeTupleFunc1, _EdgeTupleWaiter)) sim.run() def testEdgeTuple2(self): sim = Simulation(self.bench(EdgeTupleFunc2, _EdgeTupleWaiter)) sim.run() def testGeneral(self): sim = Simulation(self.bench(GeneralFunc, _Waiter)) sim.run() myhdl-0.11/myhdl/test/core/test_instance.py000066400000000000000000000033341347432460400210230ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run the unit tests for instance """ from __future__ import absolute_import from myhdl import (InstanceError, Signal, Simulation, StopSimulation, delay, instances, intbv, now) from myhdl._instance import _error, instance from helpers import raises_kind # random.seed(3) # random, but deterministic QUIET=1 def g(): pass x = Signal(0) class TestInstanceCompilation: def testArgIsFunction(self): h = 5 with raises_kind(InstanceError, _error.ArgType): instance(h) def testArgIsGeneratorFunction(self): with raises_kind(InstanceError, _error.ArgType): @instance def h(): return None def testArgHasNoArgs(self): with raises_kind(InstanceError, _error.NrOfArgs): @instance def h(n): yield n myhdl-0.11/myhdl/test/core/test_intbv.py000066400000000000000000000405641347432460400203470ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run the intbv unit tests. """ from __future__ import absolute_import import operator import random import sys from copy import copy, deepcopy from random import randrange import pytest from myhdl._compat import integer_types, long from myhdl._intbv import intbv random.seed(2) # random, but deterministic maxint = sys.maxsize class TestIntbvInit: def testDefaultValue(self): assert intbv() == 0 def getItem(s, i): ext = '0' * (i-len(s)+1) exts = ext + s si = len(exts)-1-i return exts[si] def getSlice(s, i, j): ext = '0' * (i-len(s)+1) exts = ext + s si = len(exts)-i sj = len(exts)-j return exts[si:sj] def getSliceLeftOpen(s, j): ext = '0' * (j-len(s)+1) exts = ext + s if j: return exts[:-j] else: return exts def setItem(s, i, val): ext = '0' * (i-len(s)+1) exts = ext + s si = len(exts)-1-i return exts[:si] + val + exts[si+1:] def setSlice(s, i, j, val): ext = '0' * (i-len(s)+1) exts = ext + s si = len(exts)-i sj = len(exts)-j return exts[:si] + val[si-sj:] + exts[sj:] def setSliceLeftOpen(s, j, val): ext = '0' * (j-len(s)+1) exts = ext + s if j: return val + exts[-j:] else: return val class TestIntBvIndexing: def seqsSetup(self): seqs = ["0", "1", "000", "111", "010001", "110010010", "011010001110010"] seqs.extend(["0101010101", "1010101010", "00000000000", "11111111111111"]) seqs.append("11100101001001101000101011011101001101") seqs.append("00101011101001011111010100010100100101010001001") self.seqs = seqs seqv = ["0", "1", "10", "101", "1111", "1010"] seqv.extend(["11001", "00111010", "100111100"]) seqv.append("0110101001111010101110011010011") seqv.append("1101101010101101010101011001101101001100110011") self.seqv = seqv def testGetItem(self): self.seqsSetup() for s in self.seqs: n = long(s, 2) bv = intbv(n) bvi = intbv(~n) for i in range(len(s)+20): ref = long(getItem(s, i), 2) res = bv[i] resi = bvi[i] assert res == ref assert type(res) == bool assert resi == ref^1 assert type(resi) == bool def testGetSlice(self): self.seqsSetup() for s in self.seqs: n = long(s, 2) bv = intbv(n) bvi = intbv(~n) for i in range(1, len(s)+20): for j in range(0,len(s)+20): try: res = bv[i:j] resi = bvi[i:j] except ValueError: assert i<=j continue ref = long(getSlice(s, i, j), 2) assert res == ref assert type(res) == intbv mask = (2**(i-j))-1 assert resi == ref ^ mask assert type(resi) == intbv def testGetSliceLeftOpen(self): self.seqsSetup() for s in self.seqs: n = long(s, 2) bv = intbv(n) bvi = intbv(~n) for j in range(0,len(s)+20): res = bv[:j] resi = bvi[:j] ref = long(getSliceLeftOpen(s, j), 2) assert res == ref assert type(res) == intbv assert resi+ref == -1 assert type(res) == intbv def testSetItem(self): self.seqsSetup() for s in self.seqs: n = long(s, 2) for it in (int, intbv): for i in range(len(s)+20): # print i bv0 = intbv(n) bv1 = intbv(n) bv0i = intbv(~n) bv1i = intbv(~n) bv0[i] = it(0) bv1[i] = it(1) bv0i[i] = it(0) bv1i[i] = it(1) ref0 = long(setItem(s, i, '0'), 2) ref1 = long(setItem(s, i, '1'), 2) ref0i = ~long(setItem(s, i, '1'), 2) ref1i = ~long(setItem(s, i, '0'), 2) assert bv0 == ref0 assert bv1 == ref1 assert bv0i == ref0i assert bv1i == ref1i def testSetSlice(self): self.seqsSetup() toggle = 0 for s in self.seqs: n = long(s, 2) for i in range(1, len(s)+5): for j in range(0, len(s)+5): for v in self.seqv: ext = '0' * (i-j -len(v)) extv = ext + v bv = intbv(n) bvi = intbv(~n) val = long(v, 2) toggle ^= 1 if toggle: val = intbv(val) try: bv[i:j] = val except ValueError: assert i<=j or val >= 2**(i-j) continue else: ref = long(setSlice(s, i, j, extv), 2) assert bv == ref mask = (2**(i-j))-1 vali = val ^ mask try: bvi[i:j] = vali except ValueError: assert vali >= 2**(i-j) continue else: refi = ~long(setSlice(s, i, j, extv), 2) assert bvi == refi def testSetSliceLeftOpen(self): self.seqsSetup() toggle = 0 for s in self.seqs: n = long(s, 2) for j in range(0, len(s)+5): for v in self.seqv: bv = intbv(n) bvi = intbv(~n) val = long(v, 2) toggle ^= 1 if toggle: val = intbv(val) bv[:j] = val bvi[:j] = -1-val ref = long(setSliceLeftOpen(s, j, v), 2) assert bv == ref refi = ~long(setSliceLeftOpen(s, j, v), 2) assert bvi == refi class TestIntBvAsInt: def seqSetup(self, imin, imax, jmin=0, jmax=None): seqi = [imin, imin, 12, 34] seqj = [jmin, 12 , jmin, 34] if not imax and not jmax: l = 2222222222222222222222222222 seqi.append(l) seqj.append(l) # first some smaller ints for n in range(100): ifirstmax = jfirstmax = 100000 if imax: ifirstmax = min(imax, ifirstmax) if jmax: jfirstmax = min(jmax, jfirstmax) i = randrange(imin, ifirstmax) j = randrange(jmin, jfirstmax) seqi.append(i) seqj.append(j) # then some potentially longs for n in range(100): if not imax: i = randrange(maxint) + randrange(maxint) else: i = randrange(imin, imax) if not jmax: j = randrange(maxint) + randrange(maxint) else: j = randrange(jmin, jmax) seqi.append(i) seqj.append(j) self.seqi = seqi self.seqj = seqj def binaryCheck(self, op, imin=0, imax=None, jmin=0, jmax=None): self.seqSetup(imin=imin, imax=imax, jmin=jmin, jmax=jmax) for i, j in zip(self.seqi, self.seqj): bi = intbv(long(i)) bj = intbv(j) ref = op(long(i), j) r1 = op(bi, j) r2 = op(long(i), bj) r3 = op(bi, bj) #self.assertEqual(type(r1), intbv) #self.assertEqual(type(r2), intbv) #self.assertEqual(type(r3), intbv) assert r1 == ref assert r2 == ref assert r3 == ref def augmentedAssignCheck(self, op, imin=0, imax=None, jmin=0, jmax=None): self.seqSetup(imin=imin, imax=imax, jmin=jmin, jmax=jmax) for i, j in zip(self.seqi, self.seqj): bj = intbv(j) ref = long(i) ref = op(ref, j) r1 = bi1 = intbv(long(i)) r1 = op(r1, j) r2 = long(i) r2 = op(r2, bj) r3 = bi3 = intbv(long(i)) r3 = op(r3, bj) assert type(r1) == intbv assert type(r3) == intbv assert r1 == ref assert r2 == ref assert r3 == ref assert r1 is bi1 assert r3 is bi3 def unaryCheck(self, op, imin=0, imax=None): self.seqSetup(imin=imin, imax=imax) for i in self.seqi: bi = intbv(i) ref = op(i) r1 = op(bi) #self.assertEqual(type(r1), intbv) assert r1 == ref def conversionCheck(self, op, imin=0, imax=None): self.seqSetup(imin=imin, imax=imax) for i in self.seqi: bi = intbv(i) ref = op(i) r1 = op(bi) assert type(r1) == type(ref) assert r1 == ref def comparisonCheck(self, op, imin=0, imax=None, jmin=0, jmax=None): self.seqSetup(imin=imin, imax=imax, jmin=jmin, jmax=jmax) for i, j in zip(self.seqi, self.seqj): bi = intbv(i) bj = intbv(j) ref = op(i, j) r1 = op(bi, j) r2 = op(i, bj) r3 = op(bi, bj) assert r1 == ref assert r2 == ref assert r3 == ref def testAdd(self): self.binaryCheck(operator.add) def testSub(self): self.binaryCheck(operator.sub) def testMul(self): self.binaryCheck(operator.mul, imax=maxint) # XXX doesn't work for long i??? def testTrueDiv(self): self.binaryCheck(operator.truediv, jmin=1) def testFloorDiv(self): self.binaryCheck(operator.floordiv, jmin=1) def testMod(self): self.binaryCheck(operator.mod, jmin=1) def testPow(self): self.binaryCheck(pow, jmax=64) def testLShift(self): self.binaryCheck(operator.lshift, jmax=256) def testRShift(self): self.binaryCheck(operator.rshift, jmax=256) def testAnd(self): self.binaryCheck(operator.and_) def testOr(self): self.binaryCheck(operator.or_) def testXor(self): self.binaryCheck(operator.xor) def testIAdd(self): self.augmentedAssignCheck(operator.iadd) def testISub(self): self.augmentedAssignCheck(operator.isub) def testIMul(self): self.augmentedAssignCheck(operator.imul, imax=maxint) # XXX doesn't work for long i??? def testIFloorDiv(self): self.augmentedAssignCheck(operator.ifloordiv, jmin=1) def testIMod(self): self.augmentedAssignCheck(operator.imod, jmin=1) def testIPow(self): self.augmentedAssignCheck(operator.ipow, jmax=64) def testIAnd(self): self.augmentedAssignCheck(operator.iand) def testIOr(self): self.augmentedAssignCheck(operator.ior) def testIXor(self): self.augmentedAssignCheck(operator.ixor) def testILShift(self): self.augmentedAssignCheck(operator.ilshift, jmax=256) def testIRShift(self): self.augmentedAssignCheck(operator.irshift, jmax=256) def testNeg(self): self.unaryCheck(operator.neg) def testNeg(self): self.unaryCheck(operator.pos) def testAbs(self): self.unaryCheck(operator.abs) def testInvert(self): self.unaryCheck(operator.inv) def testInt(self): self.conversionCheck(int, imax=maxint) def testLong(self): self.conversionCheck(long) def testFloat(self): self.conversionCheck(float) # XXX __complex__ seems redundant ??? (complex() works as such?) def testOct(self): self.conversionCheck(oct) def testHex(self): self.conversionCheck(hex) def testLt(self): self.comparisonCheck(operator.lt) def testLe(self): self.comparisonCheck(operator.le) def testGt(self): self.comparisonCheck(operator.gt) def testGe(self): self.comparisonCheck(operator.ge) def testEq(self): self.comparisonCheck(operator.eq) def testNe(self): self.comparisonCheck(operator.ne) class TestIntbvBounds: def testConstructor(self): assert intbv(40, max=54) == 40 with pytest.raises(ValueError): intbv(40, max=27) assert intbv(25, min=16) == 25 with pytest.raises(ValueError): intbv(25, min=27) def testSliceAssign(self): a = intbv(min=-24, max=34) for i in (-24, -2, 13, 33): for k in (6, 9, 10): a[:] = 0 a[k:] = i assert a == i for i in (-25, -128, 34, 35, 229): for k in (0, 9, 10): with pytest.raises(ValueError): a[k:] = i a = intbv(5)[8:] for v in (0, 2**8-1, 100): a[:] = v for v in (-1, 2**8, -10, 1000): with pytest.raises(ValueError): a[:] = v def checkBounds(self, i, j, op): a = intbv(i) assert a == i # just to be sure try: exec("a %s long(j)" % op) except (ZeroDivisionError, ValueError): return # prune if not isinstance(a._val, integer_types): return # prune if abs(a) > maxint * maxint: return # keep it reasonable if a > i: b = intbv(i, min=i, max=a+1) for m in (i+1, a): b = intbv(i, min=i, max=m) with pytest.raises(ValueError): exec("b %s long(j)" % op) elif a < i : b = intbv(i, min=a, max=i+1) exec("b %s long(j)" % op) # should be ok for m in (a+1, i): b = intbv(i, min=m, max=i+1) with pytest.raises(ValueError): exec("b %s long(j)" % op) else: # a == i b = intbv(i, min=i, max=i+1) exec("b %s long(j)" % op) # should be ok def checkOp(self, op): for i in (0, 1, -1, 2, -2, 16, -24, 129, -234, 1025, -15660): for j in (0, 1, -1, 2, -2, 9, -15, 123, -312, 2340, -23144): self.checkBounds(i, j, op) def testIAdd(self): self.checkOp("+=") def testISub(self): self.checkOp("-=") def testIMul(self): self.checkOp("*=") def testIFloorDiv(self): self.checkOp("//=") def testIMod(self): self.checkOp("%=") def testIPow(self): self.checkOp("**=") def testIAnd(self): self.checkOp("&=") def testIOr(self): self.checkOp("|=") def testIXor(self): self.checkOp("^=") def testILShift(self): self.checkOp("<<=") def testIRShift(self): self.checkOp(">>=") class TestIntbvCopy: def testCopy(self): for n in (intbv(), intbv(34), intbv(-12, min=-15), intbv(45, max=65), intbv(23, min=2, max=47), intbv(35)[3:]): a = intbv(n) b = copy(n) c = deepcopy(n) for m in (a, b, c): assert n == m assert n._val == m._val assert n.min == m.min assert n.max == m.max assert len(n) == len(m) myhdl-0.11/myhdl/test/core/test_misc.py000066400000000000000000000033671347432460400201600ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run the unit tests for Signal """ from __future__ import absolute_import import random from myhdl import instance, instances random.seed(1) # random, but deterministic def A(n): @instance def logic(): yield None return logic def B(n): @instance def logic(): yield None return logic def C(n): A_1 = A(1) A_2 = A(2) B_1 = B(1) return A_1, A_2, B_1 g = 3 class TestInstances: def testInstances(self): @instance def D_1(): yield None d = 1 A_1 = A(1) a = [1, 2] B_1 = B(1) b = "string" C_1 = C(1) c = {} i = instances() # can't just construct an expected list; # that would become part of the instances also! assert len(i) == 4 for e in (D_1, A_1, B_1, C_1): assert e in i myhdl-0.11/myhdl/test/core/test_modbv.py000066400000000000000000000123441347432460400203270ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2011 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run the modbv unit tests. """ from __future__ import absolute_import import sys import random import pytest from random import randrange from myhdl._intbv import intbv from myhdl._modbv import modbv from myhdl._compat import integer_types, long random.seed(3) maxint=sys.maxsize class TestModbvWrap: def testWrap(self): x = modbv(0, min=-8, max=8) x[:] = x + 1 assert 1 == x x[:] = x + 2 assert 3 == x x[:] = x + 5 assert -8 == x x[:] = x + 1 assert -7 == x x[:] = x - 5 assert 4 == x x[:] = x - 4 assert 0 == x x[:] += 15 x[:] = x - 1 assert -2 == x def testInit(self): with pytest.raises(ValueError): intbv(15, min=-8, max=8) x = modbv(15, min=-8, max=8) assert -1 == x # Arbitrary boundraries support (no exception) modbv(5, min=-3, max=8) def testNoWrap(self): # Validate the base class fails for the wraps x = intbv(0, min=-8, max=8) with pytest.raises(ValueError): x[:] += 15 x = intbv(0, min=-8, max=8) with pytest.raises(ValueError): x[:] += 15 class TestModBvSlice: def BuildTestSeqs(self): imin,jmin=0,0 imax,jmax=5000,5000 seqi,seqj=[],[] #small bits for n in range(10): seqi.append(randrange(imin, imax)) seqi.append(randrange(jmin, jmax)) #large bits for n in range(10): seqi.append(randrange(imin,maxint)) seqj.append(randrange(jmin,maxint)) self.seqi=seqi self.seqj=seqj def testGetItem(self): self.BuildTestSeqs() #Testing for the __getItem__ function for i in self.seqi: ti=modbv(i) cti=modbv(~i) for n in range(len(bin(i))): chk=((i >> n) & 1) res=ti[n] resv=cti[n] assert type(res) == bool assert type(resv) == bool assert res == chk assert resv == chk^1 def testGetSlice(self): self.BuildTestSeqs() #Testing for slice ranged, both closed for i in self.seqi: ti=modbv(i) cti=modbv(~i) leni=len(bin(i)) for n in (range(leni)): s=randrange(-leni,leni) f=randrange(-leni,leni) try: val=ti[f:s] except ValueError: assert (f<=s) | (s<=0) else: chkt = (i >> s) & (2**(f-s) -1) assert val == chkt assert (val.max,val.min) == (2**(f-s),0) def testGetSliceOpen(self): self.BuildTestSeqs() #Testing for slice ranged, one of them open for i in self.seqi: ti=modbv(i) cti=modbv(~i) leni=len(bin(i)) assert ti+cti == -1 for n in (range(leni)): s=randrange(leni) f=randrange(1,leni) chkf = (i) & (2**(f) -1) chks = (i >> s) vals,cvals = ti[:s],cti[:s] valf,cvalf = ti[f:],cti[f:] assert vals+cvals == -1 #assert valf+cvalf == -1 ---test fails- why??? assert vals == modbv(chks) assert valf == modbv(chkf) def testSetSlice(self): self.BuildTestSeqs() self.seqi.extend(self.seqj) #Test the bit slice setting wrap around behaviour for i in range(1,len(self.seqi)): lenp=len(bin(self.seqi[i-1])) ti = modbv(self.seqi[i-1])[lenp:] maxp = 2**lenp vali = self.seqi[i] s=randrange(lenp-1) f=randrange(s,lenp) valp = self.seqi[i-1] maxval = (1 << (f-s))-1 try: ti[f:s] = vali except ValueError: assert maxval < vali else: bitmask = (((2**f - 1) >> s) << s ) valp = valp - (valp & bitmask) valp = (valp + ((vali << s) % maxp)) % maxp assert valp == ti myhdl-0.11/myhdl/test/core/test_signed.py000066400000000000000000000174001347432460400204670ustar00rootroot00000000000000#!/usr/bin/env python # This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run the intbv.signed() unit tests. """ from __future__ import absolute_import from random import randrange import myhdl from myhdl import * class TestIntbvSigned: '''Test cases to verify the intbv.signed() member function''' def testPlainIntbvInstance(self): '''Test a plain intbv instance with .signed() ----+----+----+----+----+----+----+---- -3 -2 -1 0 1 2 3 min max min max min max min max min max min max min max neither min nor max is set only max is set only min is set ''' #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ # in the following cases the .signed() function should classify the # value of the intbv instance as unsigned and return the 2's # complement value of the bits as specified by _nrbits. # # intbv with positive range, pos number, and msb not set, return signed() # Expect the number to be returned a = intbv(0x3b, min=0, max=0x7c) b = a.signed() assert b == 0x3b # intbv with positive range, pos number, and msb set, return signed() # test various bit patterns to see that the 2's complement # conversion works correct # Expect the number to be converted to a negative number a = intbv(7, min=0, max=8) b = a.signed() assert b == -1 a = intbv(6, min=0, max=8) b = a.signed() assert b == -2 a = intbv(5, min=0, max=8) b = a.signed() assert b == -3 # set bit #3 and increase the range so that the set bit is considered # the sign bit. Here min = 0 # Expect to return -4 a = intbv(4, min=0, max=5) b = a.signed() assert b == -4 a = intbv(4, min=0, max=6) b = a.signed() assert b == -4 a = intbv(4, min=0, max=7) b = a.signed() assert b == -4 a = intbv(4, min=0, max=8) b = a.signed() assert b == -4 # here it is not the sign bit anymore # Expect the value to be 4 a = intbv(4, min=0, max=9) b = a.signed() assert b == 4 # set bit #3 and increase the range so that the set bit is considered # the sign bit. Here min > 0 # Expect to return -4 a = intbv(4, min=1, max=5) b = a.signed() assert b == -4 a = intbv(4, min=2, max=6) b = a.signed() assert b == -4 a = intbv(4, min=3, max=7) b = a.signed() assert b == -4 a = intbv(4, min=4, max=8) b = a.signed() assert b == -4 # again with min > 0, here it is not the sign bit anymore # Expect the value to be 4 a = intbv(4, min=2, max=9) b = a.signed() assert b == 4 # intbv with positive range, value = 0, return signed() # Expect the number to be returned a = intbv(0, min=0, max=0x8) b = a.signed() assert b == 0 #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ # in these cases the .signed() function should classify the # value of the intbv instance as signed and return the value as is # # intbv without range, pos number, return signed() # Expect value to be returned as is a = intbv(8) b = a.signed() assert b == 8 # intbv without range, neg number, return signed() # Expect value to be returned as is a = intbv(-8) b = a.signed() assert b == -8 # set bit #3 and increase the range that the set bit is actually the # msb, but due to the negative range not considered signed # Expect to return 4 a = intbv(4, min=-1, max=5) b = a.signed() assert b == 4 a = intbv(4, min=-1, max=6) b = a.signed() assert b == 4 a = intbv(4, min=-1, max=7) b = a.signed() assert b == 4 a = intbv(4, min=-1, max=8) b = a.signed() assert b == 4 # intbv with negative range, pos number, and msb set, return signed() # Expect the number to returned as is a = intbv(7, min=-1, max=8) b = a.signed() assert b == 7 a = intbv(6, min=-1, max=8) b = a.signed() assert b == 6 a = intbv(5, min=-1, max=8) b = a.signed() assert b == 5 # intbv with symmetric (min = -max) range, pos value, msb set # return signed() # Expect value returned as is a = intbv(4, min=-8, max=8) b = a.signed() assert b == 4 # intbv with symmetric (min = -max) range, neg value, # return signed() # Expect value returned as is a = intbv(-4, min=-8, max=8) b = a.signed() assert b == -4 # intbv with symmetric (min=-max) range, value = 0, # return signed() # Expect value returned as is a = intbv(0, min=-8, max=8) b = a.signed() assert b == 0 def testSlicedSigned(self): '''Test a slice with .signed() This test can actually be simplified, as a slice will always have min=0 and max > min, which will result in an intbv instance that will be considered unsigned by the intbv.signed() function. ''' a = intbv(4, min=-8, max=8) b = a[4:] assert b == 4 b = a[4:].signed() assert b == 4 # msb is not set with a 4 bit slice b = a[3:] assert b == 4 b = a[3:].signed() assert b == -4 # msb is set with 3 bits sliced def testSignedConcat(self): '''Test the .signed() function with the concatenate function''' # concat 3 bits # Expect the signed function to return a negative value a = concat(True, True, True).signed() assert a == -1 # concate a 3 bit intbv with msb set and two bits # Expect a negative number b = concat(intbv(5,min=0,max=8), True, True).signed() assert b == -9 def checkInvariants(self, a): """Check invariants of signed operator.""" W = len(a) b = intbv(a.signed()) if W > 0: assert a[W:] == b[W:] assert b[:W] == -a[W-1] else: assert a == b def testRandom(self): NRTESTS = 1000 for L in (10, 1000, 2**32, 2**68): for i in range(NRTESTS): lo = randrange(-L, L) hi = randrange(lo+1, 2*L) v = randrange(lo, hi) a = intbv(v, min=lo, max=hi) self.checkInvariants(a) self.checkInvariants(Signal(a)) myhdl-0.11/myhdl/test/core/test_traceSignals.py000066400000000000000000000127071347432460400216420ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run the unit tests for traceSignals """ from __future__ import absolute_import import os import random import pytest from myhdl import block, Signal, Simulation, _simulator, delay, instance, intbv from myhdl._traceSignals import TraceSignalsError, _error, traceSignals from helpers import raises_kind random.seed(1) # random, but deterministic path = os.path QUIET=1 @block def gen(clk): @instance def logic(): while 1: yield delay(10) clk.next = not clk return logic @block def fun(): clk = Signal(bool(0)) inst = gen(clk) return inst @block def dummy(): clk = Signal(bool(0)) inst = gen(clk) return 1 @block def top(): inst = traceSignals(fun()) return inst @block def top2(): inst = [{} for i in range(4)] j = 3 inst[j-2]['key'] = traceSignals(fun()) return inst @block def top3(): inst_1 = traceSignals(fun()) inst_2 = traceSignals(fun()) return inst_1, inst_2 @block def genTristate(clk, x, y, z): xd = x.driver() yd = y.driver() zd = z.driver() @instance def ckgen(): while 1: yield delay(10) clk.next = not clk @instance def logic(): for v in [True, False, None, 0, True, None, None, 1]: yield clk.posedge xd.next = v if v is None: yd.next = zd.next = None elif v: yd.next = zd.next = 11 else: yd.next = zd.next = 0 return ckgen,logic @block def tristate(): from myhdl import TristateSignal clk = Signal(bool(0)) x = TristateSignal(True) # single bit y = TristateSignal(intbv(0)) # intbv with undefined width z = TristateSignal(intbv(0)[8:]) # intbv with fixed width inst = genTristate(clk, x, y, z) return inst @block def topTristate(): inst = traceSignals(tristate()) return inst @pytest.yield_fixture def vcd_dir(tmpdir): with tmpdir.as_cwd(): yield tmpdir if _simulator._tracing: _simulator._tf.close() _simulator._tracing = 0 class TestTraceSigs: # TODO: multiple trace handling is different now has the # calls go bottom-up. To be revisited. # def testMultipleTraces(self, vcd_dir): # with raises_kind(TraceSignalsError, _error.MultipleTraces): # dut = top3() def testArgType1(self, vcd_dir): with raises_kind(TraceSignalsError, _error.ArgType): dut = traceSignals([1, 2]) # this test is no longer relevant # def testReturnVal(self, vcd_dir): # from myhdl import ExtractHierarchyError # from myhdl._extractHierarchy import _error # kind = _error.InconsistentToplevel % (2, "dummy") # with raises_kind(ExtractHierarchyError, kind): # dut = traceSignals(dummy()) def testHierarchicalTrace1(self, vcd_dir): p = "%s.vcd" % fun.__name__ top() assert path.exists(p) def testHierarchicalTrace2(self, vcd_dir): pdut = "%s.vcd" % top.__name__ psub = "%s.vcd" % fun.__name__ dut = traceSignals(top()) assert path.exists(pdut) assert not path.exists(psub) def testTristateTrace(self, vcd_dir): sim = Simulation(topTristate()) sim.run(100, quiet=QUIET) sim.quit() def testBackupOutputFile(self, vcd_dir): p = "%s.vcd" % fun.__name__ dut = traceSignals(fun()) sim = Simulation(dut) sim.run(1000, quiet=QUIET) sim.quit() _simulator._tf.close() _simulator._tracing = 0 size = path.getsize(p) pbak = p[:-4] + '.' + str(path.getmtime(p)) + '.vcd' assert not path.exists(pbak) dut = traceSignals(fun()) _simulator._tf.close() _simulator._tracing = 0 assert path.exists(p) assert path.exists(pbak) assert path.getsize(pbak) == size assert path.getsize(p) < size def testSetDirectory(self, vcd_dir): traceSignals.directory = 'some_vcd_dir' os.mkdir(path.join(str(vcd_dir), traceSignals.directory)) pdut = "%s.vcd" % top.__name__ psub = "%s.vcd" % fun.__name__ pdutd = path.join(traceSignals.directory, "%s.vcd" % top.__name__) psubd = path.join(traceSignals.directory, "%s.vcd" % fun.__name__) dut = traceSignals(top()) _simulator._tf.close() _simulator._tracing = 0 traceSignals.directory = None assert not path.exists(pdut) assert not path.exists(psub) assert path.exists(pdutd) assert not path.exists(psubd) myhdl-0.11/myhdl/test/helpers.py000066400000000000000000000006001347432460400166630ustar00rootroot00000000000000import pytest class raises_kind(object): def __init__(self, exc, kind): self.exc = exc self.kind = kind def __enter__(self): return None def __exit__(self, *tp): __tracebackhide__ = True if tp[0] is None: pytest.fail("DID NOT RAISE") assert tp[1].kind == self.kind return issubclass(tp[0], self.exc) myhdl-0.11/pylintrc000066400000000000000000000211561347432460400143530ustar00rootroot00000000000000[MASTER] # Specify a configuration file. #rcfile= # Python code to execute, usually for sys.path manipulation such as # pygtk.require(). #init-hook= # Profiled execution. profile=no # Add files or directories to the blacklist. They should be base names, not # paths. ignore=CVS # Pickle collected data for later comparisons. persistent=yes # List of plugins (as comma separated values of python modules names) to load, # usually to register additional checkers. load-plugins= [MESSAGES CONTROL] # Enable the message, report, category or checker with the given id(s). You can # either give multiple identifier separated by comma (,) or put this option # multiple time. See also the "--disable" option for examples. #enable= # Disable the message, report, category or checker with the given id(s). You # can either give multiple identifiers separated by comma (,) or put this # option multiple times (only on the command line, not in the configuration # file where it should appear only once).You can also use "--disable=all" to # disable everything first and then reenable specific checks. For example, if # you want to run only the similarities checker, you can use "--disable=all # --enable=similarities". If you want to run only the classes checker, but have # no Warning level messages displayed, use"--disable=all --enable=classes # --disable=W" #disable= #disabled for now disable=missing-docstring,no-init,protected-access,too-few-public-methods, old-style-class, too-many-branches, redefined-builtin [REPORTS] # Set the output format. Available formats are text, parseable, colorized, msvs # (visual studio) and html. You can also give a reporter class, eg # mypackage.mymodule.MyReporterClass. output-format=text # Put messages in a separate file for each module / package specified on the # command line instead of printing them on stdout. Reports (if any) will be # written in a file name "pylint_global.[txt|html]". files-output=no # Tells whether to display a full report or only the messages reports=yes # Python expression which should return a note less than 10 (10 is the highest # note). You have access to the variables errors warning, statement which # respectively contain the number of errors / warnings messages and the total # number of statements analyzed. This is used by the global evaluation report # (RP0004). evaluation=10.0 - ((float(5 * error + warning + refactor + convention) / statement) * 10) # Add a comment according to your evaluation note. This is used by the global # evaluation report (RP0004). comment=no # Template used to display messages. This is a python new-style format string # used to format the message information. See doc for all details #msg-template= [MISCELLANEOUS] # List of note tags to take in consideration, separated by a comma. notes=FIXME,XXX,TODO [FORMAT] # Maximum number of characters on a single line. max-line-length=99 # Regexp for a line that is allowed to be longer than the limit. ignore-long-lines=^\s*(# )??$ # Allow the body of an if to be on the same line as the test if there is no # else. single-line-if-stmt=no # List of optional constructs for which whitespace checking is disabled no-space-check=trailing-comma,dict-separator # Maximum number of lines in a module max-module-lines=1000 # String used as indentation unit. This is usually " " (4 spaces) or "\t" (1 # tab). indent-string=' ' [TYPECHECK] # Tells whether missing members accessed in mixin class should be ignored. A # mixin class is detected if its name ends with "mixin" (case insensitive). ignore-mixin-members=yes # List of classes names for which member attributes should not be checked # (useful for classes with attributes dynamically set). ignored-classes=SQLObject # When zope mode is activated, add a predefined set of Zope acquired attributes # to generated-members. zope=no # List of members which are set dynamically and missed by pylint inference # system, and so shouldn't trigger E0201 when accessed. Python regular # expressions are accepted. generated-members=REQUEST,acl_users,aq_parent [VARIABLES] # Tells whether we should check for unused import in __init__ files. init-import=no # A regular expression matching the beginning of the name of dummy variables # (i.e. not used). dummy-variables-rgx=_$|dummy # List of additional names supposed to be defined in builtins. Remember that # you should avoid to define new builtins when possible. additional-builtins= [SIMILARITIES] # Minimum lines number of a similarity. min-similarity-lines=4 # Ignore comments when computing similarities. ignore-comments=yes # Ignore docstrings when computing similarities. ignore-docstrings=yes # Ignore imports when computing similarities. ignore-imports=no [BASIC] # Required attributes for module, separated by a comma required-attributes= # List of builtins function names that should not be used, separated by a comma bad-functions=map,filter,apply,input # Regular expression which should only match correct module names module-rgx=(([a-z_][a-z0-9_]*)|([A-Z][a-zA-Z0-9]+))$ # Regular expression which should only match correct module level names const-rgx=(([a-zA-Z_][a-zA-Z0-9_]*)|(__.*__))$ # Regular expression which should only match correct class names class-rgx=[A-Z_][a-zA-Z0-9]+$ # Regular expression which should only match correct function names function-rgx=[a-z_][a-zA-Z0-9_]{2,30}$ # Regular expression which should only match correct method names method-rgx=[a-z_][a-zA-Z0-9_]{2,30}$ # Regular expression which should only match correct instance attribute names attr-rgx=[a-z_][a-z0-9_]{2,30}$ # Regular expression which should only match correct argument names argument-rgx=[a-z_][a-z0-9_]{2,30}$ # Regular expression which should only match correct variable names variable-rgx=[a-z_][a-z0-9_]{0,30}$ # Regular expression which should only match correct attribute names in class # bodies class-attribute-rgx=([A-Za-z_][A-Za-z0-9_]{2,30}|(__.*__))$ # Regular expression which should only match correct list comprehension / # generator expression variable names inlinevar-rgx=[A-Za-z_][A-Za-z0-9_]*$ # Good variable names which should always be accepted, separated by a comma good-names=i,j,k,ex,Run,_ # Bad variable names which should always be refused, separated by a comma bad-names=foo,bar,baz,toto,tutu,tata # Regular expression which should only match function or class names that do # not require a docstring. no-docstring-rgx=__.*__ # Minimum line length for functions/classes that require docstrings, shorter # ones are exempt. docstring-min-length=-1 [DESIGN] # Maximum number of arguments for function / method max-args=7 # Argument names that match this expression will be ignored. Default to name # with leading underscore ignored-argument-names=_.* # Maximum number of locals for function / method body max-locals=15 # Maximum number of return / yield for function / method body max-returns=6 # Maximum number of branch for function / method body max-branches=12 # Maximum number of statements in function / method body max-statements=50 # Maximum number of parents for a class (see R0901). max-parents=7 # Maximum number of attributes for a class (see R0902). max-attributes=13 # Minimum number of public methods for a class (see R0903). min-public-methods=2 # Maximum number of public methods for a class (see R0904). max-public-methods=20 [IMPORTS] # Deprecated modules which should not be used, separated by a comma deprecated-modules=regsub,TERMIOS,Bastion,rexec # Create a graph of every (i.e. internal and external) dependencies in the # given file (report RP0402 must not be disabled) import-graph= # Create a graph of external dependencies in the given file (report RP0402 must # not be disabled) ext-import-graph= # Create a graph of internal dependencies in the given file (report RP0402 must # not be disabled) int-import-graph= [CLASSES] # List of interface methods to ignore, separated by a comma. This is used for # instance to not check methods defines in Zope's Interface base class. ignore-iface-methods=isImplementedBy,deferred,extends,names,namesAndDescriptions,queryDescriptionFor,getBases,getDescriptionFor,getDoc,getName,getTaggedValue,getTaggedValueTags,isEqualOrExtendedBy,setTaggedValue,isImplementedByInstancesOf,adaptWith,is_implemented_by # List of method names used to declare (i.e. assign) instance attributes. defining-attr-methods=__init__,__new__,setUp # List of valid names for the first argument in a class method. valid-classmethod-first-arg=cls # List of valid names for the first argument in a metaclass class method. valid-metaclass-classmethod-first-arg=mcs [EXCEPTIONS] # Exceptions that will emit a warning when being caught. Defaults to # "Exception" overgeneral-exceptions=Exception myhdl-0.11/scripts/000077500000000000000000000000001347432460400142465ustar00rootroot00000000000000myhdl-0.11/scripts/benchmark/000077500000000000000000000000001347432460400162005ustar00rootroot00000000000000myhdl-0.11/scripts/benchmark/Makefile000066400000000000000000000000701347432460400176350ustar00rootroot00000000000000 clean: -rm *.o *.pyc *.vhd *.v *.out *~; ghdl --clean myhdl-0.11/scripts/benchmark/convert.py000066400000000000000000000010361347432460400202320ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from test_lfsr24 import test_lfsr24 from test_randgen import test_randgen from test_longdiv import test_longdiv from test_timer import test_timer from timer import timer_sig, timer_var from test_findmax import test_findmax toVerilog(test_lfsr24) toVHDL(test_lfsr24) toVerilog(test_randgen) toVHDL(test_randgen) toVerilog(test_longdiv) toVHDL(test_longdiv) toVerilog(test_timer, timer_var) toVHDL(test_timer, timer_var) toVerilog(test_findmax) toVHDL(test_findmax) myhdl-0.11/scripts/benchmark/cvcrun.sh000066400000000000000000000010561347432460400200360ustar00rootroot00000000000000#!/bin/bash echo > cvcstats.dat python convert.py tests=" timer lfsr24 randgen longdiv findmax " for test in $tests do echo Test: $test >> cvcstats.dat echo ===== >> cvcstats.dat echo cvc compiled >> cvcstats.dat echo ------------ >> cvcstats.dat cvc -O +2state test_$test.v /usr/bin/time -o cvcstats.dat -a -p ./cvcsim > ${test}_cvcexe.out echo >> cvcstats.dat echo cvc interpreted >> cvcstats.dat echo --------------- >> cvcstats.dat /usr/bin/time -o cvcstats.dat -a -p cvc +interp test_$test.v > ${test}_cvcinterp.out echo >> cvcstats.dat done myhdl-0.11/scripts/benchmark/cvcstats.dat000066400000000000000000000012721347432460400205260ustar00rootroot00000000000000 Test: timer ===== cvc compiled ------------ real 2.53 user 2.51 sys 0.01 cvc interpreted --------------- real 53.49 user 53.20 sys 0.11 Test: lfsr24 ===== cvc compiled ------------ real 2.15 user 2.15 sys 0.00 cvc interpreted --------------- real 45.29 user 45.13 sys 0.07 Test: randgen ===== cvc compiled ------------ real 2.29 user 2.20 sys 0.03 cvc interpreted --------------- real 34.77 user 34.42 sys 0.15 Test: longdiv ===== cvc compiled ------------ real 0.98 user 0.97 sys 0.00 cvc interpreted --------------- real 20.56 user 20.49 sys 0.03 Test: findmax ===== cvc compiled ------------ real 2.17 user 2.16 sys 0.00 cvc interpreted --------------- real 32.35 user 32.21 sys 0.08 myhdl-0.11/scripts/benchmark/glibc_random.py000066400000000000000000000003151347432460400211710ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * def glibc_random(seed): random_word = intbv(0)[64:] random_word[:] = seed * 1103515245 + 12345 return random_word[32:] myhdl-0.11/scripts/benchmark/jitrun.sh000066400000000000000000000010451347432460400200470ustar00rootroot00000000000000#!/bin/bash echo > jitstats.dat tests=" longdiv_9 longdiv_10 longdiv_11 longdiv_12 longdiv_13 longdiv_14 longdiv_15 longdiv_16 longdiv_17 longdiv_18 " for test in $tests do echo Test: $test >> jitstats.dat echo ===== >> jitstats.dat echo python >> jitstats.dat echo ------ >> jitstats.dat /usr/bin/time -o jitstats.dat -a -p python test_$test.py > ${test}_python.out echo >> jitstats.dat echo pypy >> jitstats.dat echo ---- >> jitstats.dat /usr/bin/time -o jitstats.dat -a -p pypy test_$test.py > ${test}_pypy.out echo >> jitstats.dat done myhdl-0.11/scripts/benchmark/jitstats.dat000066400000000000000000000021121347432460400205330ustar00rootroot00000000000000 Test: longdiv_9 ===== python ------ real 1.66 user 1.63 sys 0.02 pypy ---- real 1.90 user 1.85 sys 0.05 Test: longdiv_10 ===== python ------ real 3.11 user 3.06 sys 0.03 pypy ---- real 2.18 user 2.14 sys 0.04 Test: longdiv_11 ===== python ------ real 6.05 user 6.00 sys 0.02 pypy ---- real 2.49 user 2.46 sys 0.03 Test: longdiv_12 ===== python ------ real 11.89 user 11.81 sys 0.05 pypy ---- real 3.07 user 3.02 sys 0.05 Test: longdiv_13 ===== python ------ real 23.46 user 23.32 sys 0.08 pypy ---- real 4.21 user 4.17 sys 0.03 Test: longdiv_14 ===== python ------ real 46.75 user 46.55 sys 0.09 pypy ---- real 6.33 user 6.26 sys 0.05 Test: longdiv_15 ===== python ------ real 93.94 user 93.54 sys 0.18 pypy ---- real 10.73 user 10.63 sys 0.08 Test: longdiv_16 ===== python ------ real 186.58 user 185.77 sys 0.38 pypy ---- real 19.09 user 19.00 sys 0.04 Test: longdiv_17 ===== python ------ real 373.05 user 371.43 sys 0.76 pypy ---- real 35.80 user 35.61 sys 0.10 Test: longdiv_18 ===== python ------ real 750.67 user 747.51 sys 1.43 pypy ---- real 69.35 user 69.15 sys 0.03 myhdl-0.11/scripts/benchmark/lfsr24.py000066400000000000000000000006641347432460400176740ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * def lfsr24(lfsr, enable, clock, reset): @always(clock.posedge, reset.posedge) def logic(): if reset == 1: lfsr.next = 1 else: if enable: # lfsr.next[24:1] = lfsr[23:0] lfsr.next = lfsr << 1 lfsr.next[0] = lfsr[23] ^ lfsr[22] ^ lfsr[21] ^ lfsr[16] return logic myhdl-0.11/scripts/benchmark/long_divider.py000066400000000000000000000044471347432460400212300ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * def long_divider( quotient, ready, dividend, divisor, start, clock, reset ): M = len(dividend) N = len(divisor) Q = len(quotient) assert M-N == Q st = enum("WAIT_START", "CALC") @instance def proc(): state = st.WAIT_START div = intbv(0)[N+1:] divbits = intbv(0)[Q-1:] quot = intbv(0)[Q:] count = intbv(0, min=0, max=Q) while True: yield clock.posedge, reset.posedge if reset == 1: quotient.next = 0 ready.next = 0 state = st.WAIT_START div[:] = 0 divbits[:] = 0 quot[:] = 0 else: if state == st.WAIT_START: if start: state = st.CALC ready.next = 0 quot[:] = 0 div[N+1:] = dividend[M:Q-1] divbits[:] = dividend[Q-1:] count[:] = 0 elif state == st.CALC: quot[Q:1] = quot[Q-1:] if div >= divisor: quot[0] = 1 div -= divisor else: quot[0] = 0 if count == Q-1: ready.next = 1 state = st.WAIT_START else: div[N+1:1] = div[N:] div[0] = divbits[Q-2] divbits[Q-1:1] = divbits[Q-2:] count += 1 quotient.next = quot return proc if __name__ == '__main__': quotient = Signal(intbv(0)[22:]) ready = Signal(bool()) dividend = Signal(intbv(0)[38:]) divisor = Signal(intbv(0)[16:]) start = Signal(bool()) clock = Signal(bool()) reset = Signal(bool()) toVHDL(long_divider, quotient, ready, dividend, divisor, start, clock, reset ) myhdl-0.11/scripts/benchmark/perf_inferWaiter.py000066400000000000000000000037151347432460400220530ustar00rootroot00000000000000# This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # # Copyright (C) 2003-2008 Jan Decaluwe # # The myhdl library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public License as # published by the Free Software Foundation; either version 2.1 of the # License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run the unit tests for inferWaiter """ from __future__ import absolute_import import random from random import randrange random.seed(1) # random, but deterministic import myhdl from myhdl import * from myhdl._Waiter import _SignalWaiter,_SignalTupleWaiter, _DelayWaiter, \ _EdgeWaiter, _EdgeTupleWaiter, _Waiter from test_inferWaiter import * QUIET=1 N=10 def bench(genFunc, waiterType): a, b, c, d, r, s = [Signal(intbv()) for i in range(6)] s = [Signal(intbv()) for i in range(N)] gen_inst_s = [] for i in range(N): gen_inst_s.append(waiterType(genFunc(a, b, c, d, s[i]))) def stimulus(): for i in range(5000): yield delay(randrange(1, 10)) if randrange(2): a.next = randrange(32) if randrange(2): b.next = randrange(32) c.next = randrange(2) d.next = randrange(2) raise StopSimulation() return gen_inst_s, _Waiter(stimulus()) gen = SignalGen2 waiter = _Waiter sim = Simulation(bench(gen, waiter)) sim.run() myhdl-0.11/scripts/benchmark/pypyrun.sh000066400000000000000000000005121347432460400202600ustar00rootroot00000000000000#!/bin/bash echo > pypystats.dat tests=" timer lfsr24 randgen longdiv findmax " for test in $tests do echo Test: $test >> pypystats.dat echo ===== >> pypystats.dat echo pypy >> pypystats.dat echo ---- >> pypystats.dat /usr/bin/time -o pypystats.dat -a -p pypy test_$test.py > ${test}_pypy.out echo >> pypystats.dat done myhdl-0.11/scripts/benchmark/pypystats.dat000066400000000000000000000004641347432460400207560ustar00rootroot00000000000000 Test: timer ===== pypy ---- real 37.31 user 37.25 sys 0.03 Test: lfsr24 ===== pypy ---- real 39.90 user 39.86 sys 0.01 Test: randgen ===== pypy ---- real 20.96 user 20.90 sys 0.04 Test: longdiv ===== pypy ---- real 30.57 user 30.50 sys 0.04 Test: findmax ===== pypy ---- real 16.29 user 16.24 sys 0.03 myhdl-0.11/scripts/benchmark/random_generator.py000066400000000000000000000027661347432460400221130ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * def random_generator(random_word, enable, clock, reset): W = len(random_word) @instance def logic(): lfsr = modbv(0)[64:] word = modbv(0)[W:] while True: yield clock.posedge, reset.posedge if reset == 1: random_word.next = 0 lfsr[:] = 1 else: if enable: for i in range(W): word[i] = lfsr[63] tmp0 = lfsr[63] ^ lfsr[62] ^ lfsr[60] ^ lfsr[59] lfsr <<= 1 lfsr[0] = tmp0 random_word.next = word return logic # def random_generator(random_word, enable, clock, reset): # W = len(random_word) # @instance # def logic(): # lfsr = intbv(0)[64:] # word = intbv(0)[W:] # while True: # yield clock.posedge, reset.posedge # if reset == 1: # random_word.next = 0 # lfsr[:] = 0 # lfsr[63] = 1 # else: # if enable: # for i in range(W): # word[i] = lfsr[0] # tmp63 = lfsr[0] ^ lfsr[1] ^ lfsr[3] ^ lfsr[4] # lfsr >>= 1 # lfsr[63] = tmp63 # random_word.next = word # return logic myhdl-0.11/scripts/benchmark/run.do000066400000000000000000000000251347432460400173250ustar00rootroot00000000000000run -all quit -force myhdl-0.11/scripts/benchmark/run.sh000066400000000000000000000023371347432460400173450ustar00rootroot00000000000000#!/bin/bash echo > stats.dat pypy convert.py ghdl -a --std=08 pck_myhdl_10.vhd # vlib work # vcom pck_myhdl_08dev.vhd tests=" timer lfsr24 randgen longdiv findmax " for test in $tests do echo Test: $test >> stats.dat echo ===== >> stats.dat echo python >> stats.dat echo ------ >> stats.dat /usr/bin/time -o stats.dat -a -p python test_$test.py > ${test}_python.out echo >> stats.dat echo pypy >> stats.dat echo ---- >> stats.dat /usr/bin/time -o stats.dat -a -p pypy test_$test.py > ${test}_pypy.out echo >> stats.dat echo icarus >> stats.dat echo ------ >> stats.dat iverilog test_$test.v /usr/bin/time -o stats.dat -a -p vvp a.out test_$test > ${test}_icarus.out echo >> stats.dat echo ghdl >> stats.dat echo ---- >> stats.dat ghdl -a --std=08 test_$test.vhd ghdl -e --std=08 test_$test /usr/bin/time -o stats.dat -a -p ghdl -r test_$test > ${test}_ghdl.out echo >> stats.dat # echo vlog >> stats.dat # echo ---- >> stats.dat # vlog test_$test.v # /usr/bin/time -o stats.dat -a -p vsim -c -do run.do test_$test > ${test}_vlog.out # echo >> stats.dat # # echo vcom >> stats.dat # echo ---- >> stats.dat # vcom test_$test.vhd # /usr/bin/time -o stats.dat -a -p vsim -c -do run.do test_$test > ${test}_vcom.out # echo >> stats.dat done myhdl-0.11/scripts/benchmark/run_rand.sh000066400000000000000000000020431347432460400203430ustar00rootroot00000000000000echo > stats.out ghdl -a pck_myhdl_07.vhd vcom pck_myhdl_07.vhd echo >> stat.out echo random_generator >> stats.out echo ======= >> stats.out echo pypy >> stats.out echo ---- >> stats.out /usr/bin/time -o stats.out -a -p pypy test_random_generator.py > random_pypy.out echo >> stat.out echo icarus >> stats.out echo ------ >> stats.out iverilog test_random_generator.v /usr/bin/time -o stats.out -a -p vvp a.out test_random_generator > random_vvp.out echo >> stat.out echo ghdl >> stats.out echo ---- >> stats.out ghdl -a test_random_generator.vhd ghdl -e test_random_generator /usr/bin/time -o stats.out -a -p ghdl -r test_random_generator > random_ghdl.out echo >> stat.out echo vlog >> stats.out echo ---- >> stats.out vlog test_random_generator.v /usr/bin/time -o stats.out -a -p vsim -c -do run.do test_random_generator > random_vlog.out echo >> stat.out echo vcom >> stats.out echo ---- >> stats.out vcom test_random_generator.vhd /usr/bin/time -o stats.out -a -p vsim -c -do run.do test_random_generator > random_vcom.out echo >> stat.out myhdl-0.11/scripts/benchmark/stats.dat000066400000000000000000000017341347432460400200350ustar00rootroot00000000000000 Test: timer ===== python ------ real 323.20 user 322.52 sys 0.43 pypy ---- real 35.33 user 35.27 sys 0.03 icarus ------ real 52.79 user 52.75 sys 0.00 ghdl ---- real 28.70 user 28.68 sys 0.00 Test: lfsr24 ===== python ------ real 469.81 user 469.31 sys 0.15 pypy ---- real 38.13 user 38.08 sys 0.02 icarus ------ real 39.30 user 39.27 sys 0.00 ghdl ---- real 19.33 user 19.31 sys 0.00 Test: randgen ===== python ------ real 266.29 user 266.06 sys 0.02 pypy ---- real 21.02 user 20.96 sys 0.04 icarus ------ real 96.36 user 96.28 sys 0.00 ghdl ---- real 6.26 user 6.25 sys 0.00 Test: longdiv ===== python ------ real 285.33 user 285.10 sys 0.01 pypy ---- real 27.13 user 27.06 sys 0.04 icarus ------ real 24.76 user 24.74 sys 0.00 ghdl ---- real 40.14 user 40.11 sys 0.00 Test: findmax ===== python ------ real 226.55 user 226.37 sys 0.00 pypy ---- real 18.97 user 18.93 sys 0.02 icarus ------ real 27.61 user 27.58 sys 0.00 ghdl ---- real 372.73 user 372.44 sys 0.00 myhdl-0.11/scripts/benchmark/test_findmax.py000066400000000000000000000034221347432460400212400ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from glibc_random import glibc_random def max2(z, a, b): @always_comb def logic(): if a > b: z.next = a else: z.next = b return logic def maxn(z, a): L = len(a) assert L assert L % 2 == 0 H = L // 2 W = len(a[0]) if L == 2: comp2 = max2(z, a[1], a[0]) return comp2 else: zlo = Signal(intbv(0)[W:]) zhi = Signal(intbv(0)[W:]) complo = maxn(zlo, a[H:]) comphi = maxn(zhi, a[:H]) comp2 = max2(z, zhi, zlo) return comp2, complo, comphi def test_findmax(): L = 32 W = 16 random_word = Signal(intbv(0)[L*W:]) clock = Signal(bool()) stopped = Signal(bool()) a = [Signal(intbv(0)[W:]) for i in range(L)] z = Signal(intbv(0)[W:]) dut = maxn(z, a) @instance def clockgen(): clock.next = 0 yield delay(10) while not stopped: clock.next = not clock yield delay(10) @instance def stimulus(): stopped.next = 0 yield delay(10) exp = intbv(0)[W:] val = intbv(0)[W:] random_word = intbv(0)[32:] random_word[:] = 93 for i in range(2**18): exp[:] = 0 for s in range(L): random_word[:] = glibc_random(random_word) val[:] = random_word[W:] if exp < val: exp[:] = val a[s].next = val yield clock.negedge assert z == exp stopped.next = 1 yield delay(10) return dut, clockgen, stimulus if __name__ == '__main__': sim = Simulation(test_findmax()) sim.run() myhdl-0.11/scripts/benchmark/test_findmax_sigs.py000066400000000000000000000102371347432460400222670ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from glibc_random import glibc_random def max2(z, a, b): @always_comb def logic(): if a > b: z.next = a else: z.next = b return logic def maxn(z, a): L = len(a) assert L assert L % 2 == 0 H = L // 2 W = len(a[0]) if L == 2: comp2 = max2(z, a[1], a[0]) return comp2 else: zlo = Signal(intbv(0)[W:]) zhi = Signal(intbv(0)[W:]) complo = maxn(zlo, a[H:]) comphi = maxn(zhi, a[:H]) comp2 = max2(z, zhi, zlo) return comp2, complo, comphi def test_findmax(): L = 32 W = 16 clock = Signal(bool()) stopped = Signal(bool()) a0 = Signal(intbv(0)[W:]) a1 = Signal(intbv(0)[W:]) a2 = Signal(intbv(0)[W:]) a3 = Signal(intbv(0)[W:]) a4 = Signal(intbv(0)[W:]) a5 = Signal(intbv(0)[W:]) a6 = Signal(intbv(0)[W:]) a7 = Signal(intbv(0)[W:]) a8 = Signal(intbv(0)[W:]) a9 = Signal(intbv(0)[W:]) a10 = Signal(intbv(0)[W:]) a11 = Signal(intbv(0)[W:]) a12 = Signal(intbv(0)[W:]) a13 = Signal(intbv(0)[W:]) a14 = Signal(intbv(0)[W:]) a15 = Signal(intbv(0)[W:]) a16 = Signal(intbv(0)[W:]) a17 = Signal(intbv(0)[W:]) a18 = Signal(intbv(0)[W:]) a19 = Signal(intbv(0)[W:]) a20 = Signal(intbv(0)[W:]) a21 = Signal(intbv(0)[W:]) a22 = Signal(intbv(0)[W:]) a23 = Signal(intbv(0)[W:]) a24 = Signal(intbv(0)[W:]) a25 = Signal(intbv(0)[W:]) a26 = Signal(intbv(0)[W:]) a27 = Signal(intbv(0)[W:]) a28 = Signal(intbv(0)[W:]) a29 = Signal(intbv(0)[W:]) a30 = Signal(intbv(0)[W:]) a31 = Signal(intbv(0)[W:]) a = [ a0, a1 , a2 , a3 , a4 , a5 , a6 , a7 , a8 , a9 , a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20, a21, a22, a23, a24, a25, a26, a27, a28, a29, a30, a31 ] z = Signal(intbv(0)[W:]) dut = maxn(z, a) @instance def clockgen(): clock.next = 0 yield delay(10) while not stopped: clock.next = not clock yield delay(10) @instance def stimulus(): stopped.next = 0 exp = intbv(0)[W:] val = intbv(0)[W:] v = [intbv(0)[W:] for i in range(L)] random_word = intbv(0)[32:] random_word[:] = 93 for i in range(2**18): exp[:] = 0 for s in range(L): random_word[:] = glibc_random(random_word) val[:] = random_word[W:] if exp < val: exp[:] = val v[s][:] = val a0.next = v[0] a1.next = v[1] a2.next = v[2] a3.next = v[3] a4.next = v[4] a5.next = v[5] a6.next = v[6] a7.next = v[7] a8.next = v[8] a9.next = v[9] a10.next = v[10] a11.next = v[11] a12.next = v[12] a13.next = v[13] a14.next = v[14] a15.next = v[15] a16.next = v[16] a17.next = v[17] a18.next = v[18] a19.next = v[19] a20.next = v[20] a21.next = v[21] a22.next = v[22] a23.next = v[23] a24.next = v[24] a25.next = v[25] a26.next = v[26] a27.next = v[27] a28.next = v[28] a29.next = v[29] a30.next = v[30] a31.next = v[31] yield clock.negedge assert z == exp stopped.next = 1 yield delay(10) return dut, clockgen, stimulus if __name__ == '__main__': sim = Simulation(test_findmax()) sim.run() myhdl-0.11/scripts/benchmark/test_lfsr24.py000066400000000000000000000016021347432460400207240ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from lfsr24 import lfsr24 def test_lfsr24(): lfsr = Signal(modbv(0)[24:]) enable = Signal(bool()) clock = Signal(bool()) reset = Signal(bool()) dut = lfsr24(lfsr, enable, clock, reset) @instance def stimulus(): enable.next = 0 clock.next = 0 reset.next = 0 yield delay(10) reset.next = 1 yield delay(10) reset.next = 0 enable.next = 1 for i in range(2**24 - 2): yield delay(10) clock.next = 1 yield delay(10) clock.next = 0 assert lfsr != 1 yield delay(10) clock.next = 1 yield delay(10) assert lfsr == 1 return dut, stimulus if __name__ == '__main__': tb = Simulation(test_lfsr24()) tb.run() myhdl-0.11/scripts/benchmark/test_longdiv.py000066400000000000000000000040611347432460400212540ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from glibc_random import glibc_random from long_divider import long_divider def test_longdiv(nrvectors=2**18): quotient = Signal(intbv(0)[22:]) ready = Signal(bool()) dividend = Signal(intbv(0)[38:]) divisor = Signal(intbv(0)[16:]) start = Signal(bool()) clock = Signal(bool()) reset = Signal(bool()) stopped = Signal(bool()) MAXVAL = 2**22 - 1 dut = long_divider( quotient, ready, dividend, divisor, start, clock, reset ) @instance def clockgen(): clock.next = 0 yield delay(10) while not stopped: clock.next = not clock yield delay(10) @instance def stimulus(): stopped.next = 0 yield delay(10) random_word = intbv(0)[32:] p = intbv(0)[16:] q = intbv(0)[22:] d = intbv(0)[38:] yield clock.negedge reset.next = 0 yield clock.negedge reset.next = 1 yield clock.negedge reset.next = 0 start.next = 0 yield clock.negedge random_word[:] = 94 for i in range(nrvectors): yield clock.negedge random_word[:] = glibc_random(random_word) p[:] = random_word[16:] random_word[:] = glibc_random(random_word) q[:] = random_word[22:] if p == 0: q[:] = MAXVAL d[:] = p * q dividend.next = d divisor.next = p start.next = 1 yield clock.negedge start.next = 0 yield ready.posedge """compensate for Verilog's non-determinism""" yield delay(1) #print d, p, q, quotient assert quotient == q stopped.next = 1 yield delay(10) #raise StopSimulation() return dut, clockgen, stimulus if __name__ == '__main__': sim = Simulation(test_longdiv()) sim.run() myhdl-0.11/scripts/benchmark/test_longdiv_10.py000066400000000000000000000003221347432460400215500ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from test_longdiv import test_longdiv if __name__ == '__main__': sim = Simulation(test_longdiv(nrvectors=2**10)) sim.run() myhdl-0.11/scripts/benchmark/test_longdiv_11.py000066400000000000000000000003221347432460400215510ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from test_longdiv import test_longdiv if __name__ == '__main__': sim = Simulation(test_longdiv(nrvectors=2**11)) sim.run() myhdl-0.11/scripts/benchmark/test_longdiv_12.py000066400000000000000000000003221347432460400215520ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from test_longdiv import test_longdiv if __name__ == '__main__': sim = Simulation(test_longdiv(nrvectors=2**12)) sim.run() myhdl-0.11/scripts/benchmark/test_longdiv_13.py000066400000000000000000000003221347432460400215530ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from test_longdiv import test_longdiv if __name__ == '__main__': sim = Simulation(test_longdiv(nrvectors=2**13)) sim.run() myhdl-0.11/scripts/benchmark/test_longdiv_14.py000066400000000000000000000003221347432460400215540ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from test_longdiv import test_longdiv if __name__ == '__main__': sim = Simulation(test_longdiv(nrvectors=2**14)) sim.run() myhdl-0.11/scripts/benchmark/test_longdiv_15.py000066400000000000000000000003221347432460400215550ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from test_longdiv import test_longdiv if __name__ == '__main__': sim = Simulation(test_longdiv(nrvectors=2**15)) sim.run() myhdl-0.11/scripts/benchmark/test_longdiv_16.py000066400000000000000000000003221347432460400215560ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from test_longdiv import test_longdiv if __name__ == '__main__': sim = Simulation(test_longdiv(nrvectors=2**16)) sim.run() myhdl-0.11/scripts/benchmark/test_longdiv_17.py000066400000000000000000000003221347432460400215570ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from test_longdiv import test_longdiv if __name__ == '__main__': sim = Simulation(test_longdiv(nrvectors=2**17)) sim.run() myhdl-0.11/scripts/benchmark/test_longdiv_18.py000066400000000000000000000003221347432460400215600ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from test_longdiv import test_longdiv if __name__ == '__main__': sim = Simulation(test_longdiv(nrvectors=2**18)) sim.run() myhdl-0.11/scripts/benchmark/test_longdiv_9.py000066400000000000000000000003211347432460400214770ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from test_longdiv import test_longdiv if __name__ == '__main__': sim = Simulation(test_longdiv(nrvectors=2**9)) sim.run() myhdl-0.11/scripts/benchmark/test_randgen.py000066400000000000000000000015041347432460400212270ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from random_generator import random_generator def test_randgen(): random_word = Signal(intbv(0)[31:]) enable = Signal(bool()) clock = Signal(bool()) reset = Signal(bool()) dut = random_generator(random_word, enable, clock, reset) @instance def stimulus(): enable.next = 0 clock.next = 0 reset.next = 0 yield delay(10) reset.next = 1 yield delay(10) reset.next = 0 enable.next = 1 for i in range(2**20): yield delay(10) clock.next = 1 yield delay(10) clock.next = 0 print random_word return dut, stimulus if __name__ == '__main__': tb = Simulation(test_randgen()) tb.run() myhdl-0.11/scripts/benchmark/test_timer.py000066400000000000000000000020611347432460400207300ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from timer import timer_sig, timer_var def test_timer(timer): MAXVAL = 1234 clock = Signal(bool()) reset = Signal(bool()) flag = Signal(bool()) dut = timer(flag, clock, reset, MAXVAL) @instance def clkgen(): clock.next = 0 reset.next = 0 yield delay(10) reset.next = 1 yield delay(10) reset.next = 0 yield delay(10) for i in range(2**25): clock.next = not clock yield delay(10) @instance def monitor(): count = intbv(0, min=0, max=MAXVAL+1) seen = False while True: yield clock.posedge if seen: if flag: assert count == MAXVAL else: count += 1 if flag: seen = True count[:] = 0 return dut, clkgen, monitor if __name__ == '__main__': sim = Simulation(test_timer(timer_var)) sim.run() myhdl-0.11/scripts/benchmark/test_timer_array.py000066400000000000000000000032451347432460400221330ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * from timer import timer_sig, timer_var def test_timer_array(timer): MAXVAL = 1234 clock = Signal(bool()) reset = Signal(bool()) flag0 = Signal(bool()) flag1 = Signal(bool()) flag2 = Signal(bool()) flag3= Signal(bool()) flag4 = Signal(bool()) flag5 = Signal(bool()) flag6 = Signal(bool()) flag7 = Signal(bool()) dut = [None] * 8 dut[0] = timer(flag0, clock, reset, MAXVAL) dut[1] = timer(flag1, clock, reset, MAXVAL) dut[2] = timer(flag2, clock, reset, MAXVAL) dut[3] = timer(flag3, clock, reset, MAXVAL) dut[4] = timer(flag4, clock, reset, MAXVAL) dut[5] = timer(flag5, clock, reset, MAXVAL) dut[6] = timer(flag6, clock, reset, MAXVAL) dut[7] = timer(flag7, clock, reset, MAXVAL) @instance def clkgen(): clock.next = 0 reset.next = 0 yield delay(10) reset.next = 1 yield delay(10) reset.next = 0 yield delay(10) for i in range(2**24): clock.next = not clock yield delay(10) @instance def monitor(): count = intbv(0, min=0, max=MAXVAL+1) seen = False while True: yield clock.posedge if seen: if flag0: assert count == MAXVAL else: count += 1 if flag0 or flag1 or flag2 or flag3 or flag4 or flag5 or flag6 or flag7: seen = True count[:] = 0 return dut, clkgen, monitor if __name__ == '__main__': sim = Simulation(test_timer_array(timer_var)) sim.run() myhdl-0.11/scripts/benchmark/testrun.sh000066400000000000000000000024071347432460400202430ustar00rootroot00000000000000#!/bin/bash echo > teststats.dat python convert.py ghdl -a pck_myhdl_08dev.vhd vlib work vcom pck_myhdl_08dev.vhd tests=" findmax " for test in $tests do echo Test: $test >> teststats.dat echo ===== >> teststats.dat echo python >> teststats.dat echo ------ >> teststats.dat #/usr/bin/time -o teststats.dat -a -p python test_$test.py > ${test}_python.out echo >> teststats.dat echo pypy >> teststats.dat echo ---- >> teststats.dat /usr/bin/time -o teststats.dat -a -p pypy test_$test.py > ${test}_pypy.out echo >> teststats.dat echo icarus >> teststats.dat echo ------ >> teststats.dat iverilog test_$test.v /usr/bin/time -o teststats.dat -a -p vvp a.out test_$test > ${test}_icarus.out echo >> teststats.dat echo ghdl >> teststats.dat echo ---- >> teststats.dat ghdl -a test_$test.vhd ghdl -e test_$test #/usr/bin/time -o teststats.dat -a -p ghdl -r test_$test > ${test}_ghdl.out echo >> teststats.dat echo vlog >> teststats.dat echo ---- >> teststats.dat vlog test_$test.v /usr/bin/time -o teststats.dat -a -p vsim -c -do run.do test_$test > ${test}_vlog.out echo >> teststats.dat echo vcom >> teststats.dat echo ---- >> teststats.dat vcom test_$test.vhd /usr/bin/time -o teststats.dat -a -p vsim -c -do run.do test_$test > ${test}_vcom.out echo >> teststats.dat done myhdl-0.11/scripts/benchmark/teststats.dat000066400000000000000000000003351347432460400207310ustar00rootroot00000000000000 Test: findmax ===== python ------ pypy ---- real 120.68 user 120.38 sys 0.02 icarus ------ real 55.15 user 55.00 sys 0.03 ghdl ---- vlog ---- real 18.21 user 9.88 sys 8.02 vcom ---- real 36.96 user 23.06 sys 13.44 myhdl-0.11/scripts/benchmark/timer.py000066400000000000000000000016741347432460400177020ustar00rootroot00000000000000from __future__ import absolute_import import myhdl from myhdl import * def timer_sig(flag, clock, reset, MAXVAL): count = Signal(intbv(0, min=0, max=MAXVAL+1)) @always (clock.posedge, reset.posedge) def logic(): if reset == 1: count.next = 0 else: flag.next = 0 if count == MAXVAL: flag.next = 1 count.next = 0 else: count.next = count + 1 return logic def timer_var(flag, clock, reset, MAXVAL): @instance def logic(): count = intbv(0, min=0, max=MAXVAL+1) while True: yield clock.posedge, reset.posedge if reset == 1: count[:] = 0 else: flag.next = 0 if count == MAXVAL: flag.next = 1 count[:] = 0 else: count += 1 return logic myhdl-0.11/scripts/ci.sh000077500000000000000000000016731347432460400152070ustar00rootroot00000000000000#!/bin/bash ANSI_RED=`tput setaf 1` ANSI_GREEN=`tput setaf 2` ANSI_CYAN=`tput setaf 6` ANSI_RESET=`tput sgr0` run_test() { echo -e "\n${ANSI_CYAN}running test: $@ ${ANSI_RESET}" "$@" if [ $? -ne 0 ]; then echo "${ANSI_RED}[FAILED] $@ ${ANSI_RESET}" foundError=1 else echo "${ANSI_GREEN}[PASSED] $@ ${ANSI_RESET}" fi echo } foundError=0 echo -e "Running $CI_TARGET tests\n" CI_TARGET=${CI_TARGET:-core} if [ "$CI_TARGET" == "core" ]; then run_test make -C myhdl/test/core elif [ "$CI_TARGET" == "iverilog" ]; then run_test make -C "myhdl/test/conversion/general" iverilog run_test make -C cosimulation/icarus test run_test make -C myhdl/test/conversion/toVerilog run_test make -C "myhdl/test/bugs" iverilog elif [ "$CI_TARGET" == "ghdl" ]; then run_test make -C "myhdl/test/conversion/general" ghdl run_test make -C myhdl/test/conversion/toVHDL ghdl run_test make -C "myhdl/test/bugs" ghdl fi exit $foundError myhdl-0.11/setup.cfg000066400000000000000000000000321347432460400143730ustar00rootroot00000000000000[bdist_wheel] universal=1 myhdl-0.11/setup.py000066400000000000000000000037131347432460400142750ustar00rootroot00000000000000""" myhdl's distribution and installation script. """ import ast import fnmatch import re import os import sys from collections import defaultdict if sys.version_info < (2, 6) or (3, 0) <= sys.version_info < (3, 4): raise RuntimeError("Python version 2.6, 2.7 or >= 3.4 required.") # Prefer setuptools over distutils try: from setuptools import setup except ImportError: from distutils.core import setup _version_re = re.compile(r'__version__\s+=\s+(.*)') with open('myhdl/__init__.py', 'rb') as f: version = str(ast.literal_eval(_version_re.search( f.read().decode('utf-8')).group(1))) data_root = 'share/myhdl' cosim_data = defaultdict(list) for base, dir, files in os.walk('cosimulation'): for pat in ('*.c', 'Makefile*', '*.py', '*.v', '*.txt'): good = fnmatch.filter(files, pat) if good: cosim_data[base].extend(os.path.join(base, f) for f in good) setup( name="myhdl", version=version, description="Python as a Hardware Description Language", long_description="See home page.", author="Jan Decaluwe", author_email="jan@jandecaluwe.com", url="http://www.myhdl.org", packages=['myhdl', 'myhdl.conversion'], data_files=[(os.path.join(data_root, k), v) for k, v in cosim_data.items()], license="LGPL", platforms='any', keywords="HDL ASIC FPGA hardware design", classifiers=[ 'Development Status :: 5 - Production/Stable', 'Intended Audience :: Developers', 'Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)', 'License :: OSI Approved :: GNU Lesser General Public License v2 (LGPLv2)', 'Operating System :: OS Independent', 'Programming Language :: Python', 'Programming Language :: Python :: 2', 'Programming Language :: Python :: 2.6', 'Programming Language :: Python :: 2.7', 'Programming Language :: Python :: 3', 'Programming Language :: Python :: 3.4', ] ) myhdl-0.11/tox.ini000066400000000000000000000003231347432460400140700ustar00rootroot00000000000000[tox] envlist = py27,py34 [testenv] deps = pytest-xdist commands = py.test --basetemp={envtmpdir} {posargs} [testenv:docs] whitelist_externals = make changedir = doc deps = sphinx-autobuild commands = make []