pax_global_header00006660000000000000000000000064132157033310014510gustar00rootroot0000000000000052 comment=cdcde3471d57bf05f40054d6925c4343f14a59b3 open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/000077500000000000000000000000001321570333100204035ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/.editorconfig000066400000000000000000000011361321570333100230610ustar00rootroot00000000000000# Copying and distribution of this file, with or without modification, # are permitted in any medium without royalty provided this notice is # preserved. This file is offered as-is, without any warranty. # Names of contributors must not be used to endorse or promote products # derived from this file without specific prior written permission. # EditorConfig # http://EditorConfig.org # top-most EditorConfig file root = true # LF end-of-line, insert an empty new line and UTF-8 [*] end_of_line = lf insert_final_newline = true charset = utf-8 # Tab indentation [makefile,Makefile] indent_style = tab open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/.gitignore000066400000000000000000000000131321570333100223650ustar00rootroot00000000000000/toolchain open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/.travis.yml000066400000000000000000000011671321570333100225210ustar00rootroot00000000000000# Copying and distribution of this file, with or without modification, # are permitted in any medium without royalty provided this notice is # preserved. This file is offered as-is, without any warranty. # Names of contributors must not be used to endorse or promote products # derived from this file without specific prior written permission. # See YAML format https://en.wikipedia.org/wiki/YAML # See Travis CI (Continuous Integration) https://docs.travis-ci.com/ language: c os: - linux addons: apt: packages: - cmake script: - make toolchain - make -C target_firmware - make -C target_firmware clean open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/LICENCE.TXT000066400000000000000000000034361321570333100220540ustar00rootroot00000000000000Files with a Qualcomm Atheros / Atheros licence fall under the following licence. Please see NOTICES.TXT for information about other files in this repository. ---- Copyright (c) 2013 Qualcomm Atheros, Inc. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted (subject to the limitations in the disclaimer below) provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of Qualcomm Atheros nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---- open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/Makefile000066400000000000000000000075711321570333100220550ustar00rootroot00000000000000GMP_VER=6.1.1 GMP_URL=https://ftp.gnu.org/gnu/gmp/gmp-$(GMP_VER).tar.bz2 GMP_TAR=gmp-$(GMP_VER).tar.bz2 GMP_DIR=gmp-$(GMP_VER) GMP_SUM=a8109865f2893f1373b0a8ed5ff7429de8db696fc451b1036bd7bdf95bbeffd6 MPFR_VER=3.1.4 MPFR_URL=https://ftp.gnu.org/gnu/mpfr/mpfr-$(MPFR_VER).tar.bz2 MPFR_TAR=mpfr-$(MPFR_VER).tar.bz2 MPFR_DIR=mpfr-$(MPFR_VER) MPFR_SUM=d3103a80cdad2407ed581f3618c4bed04e0c92d1cf771a65ead662cc397f7775 MPC_VER=1.0.3 MPC_URL=https://ftp.gnu.org/gnu/mpc/mpc-$(MPC_VER).tar.gz MPC_TAR=mpc-$(MPC_VER).tar.gz MPC_DIR=mpc-$(MPC_VER) MPC_SUM=617decc6ea09889fb08ede330917a00b16809b8db88c29c31bfbb49cbf88ecc3 BINUTILS_VER=2.27 BINUTILS_URL=https://ftp.gnu.org/gnu/binutils/binutils-$(BINUTILS_VER).tar.bz2 BINUTILS_TAR=binutils-$(BINUTILS_VER).tar.bz2 BINUTILS_DIR=binutils-$(BINUTILS_VER) BINUTILS_PATCHES=local/patches/binutils.patch local/patches/binutils-2.27_fixup.patch BINUTILS_SUM=369737ce51587f92466041a97ab7d2358c6d9e1b6490b3940eb09fb0a9a6ac88 GCC_VER=6.3.0 GCC_URL=https://ftp.gnu.org/gnu/gcc/gcc-$(GCC_VER)/gcc-$(GCC_VER).tar.bz2 GCC_TAR=gcc-$(GCC_VER).tar.bz2 GCC_DIR=gcc-$(GCC_VER) GCC_PATCHES=local/patches/gcc.patch local/patches/gcc-6.3.0_fixup.patch GCC_SUM=f06ae7f3f790fbf0f018f6d40e844451e6bc3b7bc96e128e63b09825c1f8b29f BASEDIR=$(shell pwd) TOOLCHAIN_DIR=$(BASEDIR)/toolchain TARGET=xtensa-elf DL_DIR=$(TOOLCHAIN_DIR)/dl BUILD_DIR=$(TOOLCHAIN_DIR)/build all: toolchain # 1: package name # 2: configure arguments # 3: make command define Common/Compile mkdir -p $(BUILD_DIR)/$($(1)_DIR) +cd $(BUILD_DIR)/$($(1)_DIR) && \ $(DL_DIR)/$($(1)_DIR)/configure \ --prefix=$(TOOLCHAIN_DIR)/inst \ $(2) && \ $(3) endef define GMP/Compile $(call Common/Compile,GMP, \ --disable-shared --enable-static, \ $(MAKE) && $(MAKE) check && $(MAKE) -j1 install \ ) endef define MPFR/Compile $(call Common/Compile,MPFR, \ --disable-shared --enable-static \ --with-gmp=$(TOOLCHAIN_DIR)/inst, \ $(MAKE) && $(MAKE) check && $(MAKE) -j1 install \ ) endef define MPC/Compile $(call Common/Compile,MPC, \ --disable-shared --enable-static \ --with-gmp=$(TOOLCHAIN_DIR)/inst \ --with-mpfr=$(TOOLCHAIN_DIR)/inst, \ $(MAKE) && $(MAKE) check && $(MAKE) -j1 install \ ) endef define BINUTILS/Compile $(call Common/Compile,BINUTILS, \ --target=$(TARGET) \ --disable-werror, \ $(MAKE) && $(MAKE) -j1 install \ ) endef define GCC/Compile $(call Common/Compile,GCC, \ --target=$(TARGET) \ --enable-languages=c \ --disable-libssp \ --disable-shared \ --disable-libquadmath \ --with-gmp=$(TOOLCHAIN_DIR)/inst \ --with-mpfr=$(TOOLCHAIN_DIR)/inst \ --with-mpc=$(TOOLCHAIN_DIR)/inst \ --with-newlib, \ $(MAKE) && $(MAKE) -j1 install \ ) endef # 1: package name # 2: dependencies on other packages define Build $(DL_DIR)/$($(1)_TAR): mkdir -p $(DL_DIR) wget -N -P $(DL_DIR) $($(1)_URL) printf "%s %s\n" $($(1)_SUM) $$@ | shasum -a 256 -c $(DL_DIR)/$($(1)_DIR)/.prepared: $(DL_DIR)/$($(1)_TAR) tar -C $(DL_DIR) -x$(if $(findstring bz2,$($(1)_TAR)),j,z)f $(DL_DIR)/$($(1)_TAR) $(if $($(1)_PATCHES), \ cat $($(1)_PATCHES) | \ patch -p1 -d $(DL_DIR)/$($(1)_DIR)) touch $$@ $(1)_DEPENDS = $(foreach pkg,$(2),$(BUILD_DIR)/$($(pkg)_DIR)/.built) $(BUILD_DIR)/$($(1)_DIR)/.built: $(DL_DIR)/$($(1)_DIR)/.prepared $$($(1)_DEPENDS) mkdir -p $(BUILD_DIR)/$($(1)_DIR) $($(1)/Compile) touch $$@ clean-dl-$(1): rm -rf $(DL_DIR)/$($(1)_DIR) toolchain: $(BUILD_DIR)/$($(1)_DIR)/.built clean-dl: clean-dl-$(1) download: $(DL_DIR)/$($(1)_DIR)/.prepared endef all: toolchain firmware toolchain-clean: rm -rf $(TOOLCHAIN_DIR)/build $(TOOLCHAIN_DIR)/inst clean-dl: download: toolchain: clean: $(MAKE) -C target_firmware clean firmware: toolchain +$(MAKE) -C target_firmware .PHONY: all toolchain-clean clean clean-dl download toolchain firmware $(eval $(call Build,GMP)) $(eval $(call Build,MPFR,GMP)) $(eval $(call Build,MPC,GMP MPFR)) $(eval $(call Build,BINUTILS)) $(eval $(call Build,GCC,MPC MPFR)) open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/NOTICE.TXT000066400000000000000000000157331321570333100217760ustar00rootroot00000000000000This NOTICE.TXT file contains certain notices of software components included with the software that QUALCOMM ATHEROS Incorporated ('Qualcomm Atheros') is required to provide you. Notwithstanding anything in the notices in this file, your use of these software components together with the Qualcomm Atheros software (Qualcomm Atheros software hereinafter referred to as 'Software') is subject to the terms of your license from Qualcomm Atheros. Compliance with all copyright laws and software license agreements included in the notice section of this file are the responsibility of the user. Except as may be granted by separate express written agreement, this file provides no license to any Qualcomm Atheros patents, trademarks, copyrights, or other intellectual property. Copyright (c) 2013 QUALCOMM ATHEROS Incorporated. All rights reserved. QUALCOMM ATHEROS® is a registered trademark and registered service mark of QUALCOMM ATHEROS Incorporated. All other trademarks and service marks are the property of their respective owners. NOTICES: /* * Copyright (c) 2005-2012 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ /* * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting * Copyright (c) 2002-2005 Atheros Communications, Inc. * Copyright (c) 2008-2010, Atheros Communications Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following NO * ''WARRANTY'' disclaimer below (''Disclaimer''), without * modification. * 2. Redistributions in binary form must reproduce at minimum a * disclaimer similar to the Disclaimer below and any redistribution * must be conditioned upon including a substantially similar * Disclaimer requirement for further binary redistribution. * 3. Neither the names of the above-listed copyright holders nor the * names of any contributors may be used to endorse or promote * product derived from this software without specific prior written * permission. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE * FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGES. */ ---- The following files are from ECoS with a GPLv2 licence with modification and linking caveats. Please see the licence below for more information: sboot/magpie_1_1/sboot/cmnos/printf/src/cmnos_printf.c target_firmware/magpie_fw_dev/target/cmnos/cmnos_printf.c target_firmware/magpie_fw_dev/target/cmnos/k2_fw_cmnos_printf.c //####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. // Copyright (C) 2002 Gary Thomas // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free // Software Foundation; either version 2 or (at your option) any later version. // // eCos is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License // for more details. // // You should have received a copy of the GNU General Public License // along with this program. If not, see . // // As a special exception, if other files instantiate templates or use macros // or inline functions from this file, or you compile this file and link it // with other works to produce a work based on this file, this file does not // by itself cause the resulting work to be covered by the GNU General Public // License. However the source code for this file must still be made available // in accordance with section (3) of the GNU General Public License. // // This exception does not invalidate any other reasons why a work based on // this file might be covered by the GNU General Public License. // // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. // at http://sources.redhat.com/ecos/ecos-license/ // ------------------------------------------- //####ECOSGPLCOPYRIGHTEND#### ---- Some of the source code is sourced from Tensilica, Inc. Although most of the files fall under the MIT licence, some of the source files generated as part of the system development have a proprietary Tensilica licence. With permission from Tensilica, Inc, these files have been relicenced under the following licence: /* * Copyright (c) 2013 Tensilica Inc. * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sublicense, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/README000066400000000000000000000051251321570333100212660ustar00rootroot00000000000000This is the firmware for the Qualcomm Atheros AR7010 and AR9271 USB 802.11n NICs. What is this exactly? --------------------- This is the firmware which resides in RAM on the AR7010/AR9271 NICs. It is used by ath9k (Linux) and athn (OpenBSD) to provide wireless services. What licence is this covered by? -------------------------------- The Qualcomm Atheros owned code is under the ClearBSD licence. The NOTICES.TXT file contains copyright notices for software which this firmware release leverages. There is some code that is based off of work done under contract but is owned by Qualcomm Atheros; the original copyright statements from that work are in NOTICES.TXT. The Tensilica code (xtos/xtensa) is distributed with permission from Tensilica, Inc., under the MIT licence. There are three ECOS source files distributed under the terms of the GPLv2, with a caveat that linking or using the source files does not bring the rest of the binary under the GPLv2. Please read the ECOS caveats in more detail. Ok, what are those NICs? ------------------------ The AR7010 is a USB/PCIe SoC with onboard RAM, ROM and flash. It comes with an external wireless chip connected via PCIe - typically an AR9280 or AR9287. The AR9271 is a USB/Wifi SoC with onboad RAM, ROM, flash and the actual wireless chip. The wireless core is an off-shoot of the AR9285. It is a single-chip solution. How do I build it? ------------------ You're in for a treat. * Install the cmake build tool (http://www.cmake.org/). Major distributions have packages for this. * For FreeBSD - install gmake and wget. * You first have to build the toolchain. * Linux: $ make toolchain * FreeBSD: $ gmake toolchain (Yes, I made this work on FreeBSD as well.) * Next, build the firmware. * Linux: $ make -C target_firmware * FreeBSD: $ gmake -C target_firmware You will end up with two .fw files - one for the AR7010 and one for the AR9271 in the target_firmware directory. You can clean the firmware build (when you wish to force a rebuild) by doing: * Linux: $ make -C target_firmware clean * FreeBSD: $ gmake -C target_firmware clean Then what? ---------- You need to then copy this into the relevant location for your operating system. Yes, this means you need a driver. No, there's no FreeBSD driver yet for this particular chipset, sorry. Where do I file bugs? --------------------- Please file bugs in github - http://github.com/qca/open-ath9k-htc-firmware/issues . Mailing lists? -------------- Here you go: http://lists.infradead.org/mailman/listinfo/ath9k_htc_fw And ath9k_htc_fw@lists.infradead.org open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/debian/000077500000000000000000000000001321570333100216255ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/debian/ath9k_htc.conf000066400000000000000000000000371321570333100243520ustar00rootroot00000000000000options ath9k_htc use_dev_fw=1 open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/debian/changelog000066400000000000000000000014361321570333100235030ustar00rootroot00000000000000open-ath9k-htc-firmware (1.4.0-97-g75b3e59+dfsg-1) unstable; urgency=medium * update to latest upstream version 1.4.0-97-g75b3e59 -- Oleksij Rempel Mon, 18 Dec 2017 09:13:38 +0000 open-ath9k-htc-firmware (1.4.0-81-gf206e56+dfsg-3) unstable; urgency=medium * Use GCC 7 -- Oleksij Rempel Tue, 12 Dec 2017 17:10:53 +0000 open-ath9k-htc-firmware (1.4.0-81-gf206e56+dfsg-2) unstable; urgency=low * Set "Auto-Built-Package: debug-symbols" for -dbgsym package. -- Oleksij Rempel Sat, 29 Apr 2017 17:41:41 +0200 open-ath9k-htc-firmware (1.4.0-81-gf206e56+dfsg-1) unstable; urgency=low * Initial Release. Closes: #751339, #711470 -- Oleksij Rempel Sun, 25 Sep 2016 17:24:10 +0000 open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/debian/compat000066400000000000000000000000031321570333100230240ustar00rootroot0000000000000010 open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/debian/control000066400000000000000000000012501321570333100232260ustar00rootroot00000000000000Source: open-ath9k-htc-firmware Maintainer: Oleksij Rempel Uploaders: Paul Fertser , Section: misc Priority: optional Build-Depends: binutils-source, bison, cmake, debhelper (>= 10), flex, gcc-7-source, libmpc-dev, Standards-Version: 4.1.2 Homepage: https://github.com/qca/open-ath9k-htc-firmware Vcs-Browser: https://github.com/olerem/firmware-ath9k-htc Vcs-Git: https://github.com/olerem/firmware-ath9k-htc Package: firmware-ath9k-htc Architecture: all Multi-Arch: foreign Depends: ${misc:Depends}, Description: QCA ath9k-htc Firmware Opensource version of QCA ath9k-htc Firmware. Supported chips are: ar9271 and ar7010 open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/debian/copyright000066400000000000000000000505401321570333100235640ustar00rootroot00000000000000Format: https://www.debian.org/doc/packaging-manuals/copyright-format/1.0/ Upstream-Name: The firmware for QCA AR7010/AR9271 802.11n USB NICs Source: https://github.com/qca/open-ath9k-htc-firmware/ Files-Excluded: sboot/* docs/* Comment: Directories sboot/ and docs/ of upstream repository contain binary objects that are useful for reference and in-depth debugging purposes only and are not needed to generate a firmware image, hence they're removed during repacking to provide a DFSG-compliant tarball of original sources. . Contents of the upstream NOTICE.TXT verbatim: . This NOTICE.TXT file contains certain notices of software components included with the software that QUALCOMM ATHEROS Incorporated ('Qualcomm Atheros') is required to provide you. Notwithstanding anything in the notices in this file, your use of these software components together with the Qualcomm Atheros software (Qualcomm Atheros software hereinafter referred to as 'Software') is subject to the terms of your license from Qualcomm Atheros. Compliance with all copyright laws and software license agreements included in the notice section of this file are the responsibility of the user. Except as may be granted by separate express written agreement, this file provides no license to any Qualcomm Atheros patents, trademarks, copyrights, or other intellectual property. . Copyright (c) 2013 QUALCOMM ATHEROS Incorporated. All rights reserved. . QUALCOMM ATHEROSâ•ť is a registered trademark and registered service mark of QUALCOMM ATHEROS Incorporated. All other trademarks and service marks are the property of their respective owners. . NOTICES: . /* * Copyright (c) 2005-2012 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ . /* * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting * Copyright (c) 2002-2005 Atheros Communications, Inc. * Copyright (c) 2008-2010, Atheros Communications Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following NO * ''WARRANTY'' disclaimer below (''Disclaimer''), without * modification. * 2. Redistributions in binary form must reproduce at minimum a * disclaimer similar to the Disclaimer below and any redistribution * must be conditioned upon including a substantially similar * Disclaimer requirement for further binary redistribution. * 3. Neither the names of the above-listed copyright holders nor the * names of any contributors may be used to endorse or promote * product derived from this software without specific prior written * permission. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE * FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGES. */ . ---- . The following files are from ECoS with a GPLv2 licence with modification and linking caveats. Please see the licence below for more information: . sboot/magpie_1_1/sboot/cmnos/printf/src/cmnos_printf.c target_firmware/magpie_fw_dev/target/cmnos/cmnos_printf.c target_firmware/magpie_fw_dev/target/cmnos/k2_fw_cmnos_printf.c . //####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. // Copyright (C) 2002 Gary Thomas // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free // Software Foundation; either version 2 or (at your option) any later version. // // eCos is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License // for more details. // // You should have received a copy of the GNU General Public License // along with this program. If not, see . // // As a special exception, if other files instantiate templates or use macros // or inline functions from this file, or you compile this file and link it // with other works to produce a work based on this file, this file does not // by itself cause the resulting work to be covered by the GNU General Public // License. However the source code for this file must still be made available // in accordance with section (3) of the GNU General Public License. // // This exception does not invalidate any other reasons why a work based on // this file might be covered by the GNU General Public License. // // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. // at http://sources.redhat.com/ecos/ecos-license/ // ------------------------------------------- //####ECOSGPLCOPYRIGHTEND#### . ---- . Some of the source code is sourced from Tensilica, Inc. . Although most of the files fall under the MIT licence, some of the source files generated as part of the system development have a proprietary Tensilica licence. . With permission from Tensilica, Inc, these files have been relicenced under the following licence: . /* * Copyright (c) 2013 Tensilica Inc. * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sublicense, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ Files: * Copyright: 2013, Qualcomm Atheros, Inc. License: BSD-3-clause-from-Qualcomm-Atheros Files: debian/* Copyright: 2016, Paul Fertser 2016, Oleksij Rempel License: GPL-2+ Files: debian/cross-toolchain.mk Copyright: 2016, Aurelien Jarno License: GPL-2+ Files: scripts/* Copyright: 2008-2010, Andy Whitcroft 2007, 2008, Andy Whitcroft (new conditions, test suite) 2005, Joel Schopp (the ugly bit) 2001, Dave Jones. (the file handling bit) License: GPL-2 Files: target_firmware/include/* Copyright: 2016, Oleksij Rempel 2013, Qualcomm Atheros, Inc. License: BSD-3-clause-from-Qualcomm-Atheros Files: target_firmware/magpie_fw_dev/target/cmnos/k2_fw_cmnos_printf.c Copyright: 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. 2002, Gary Thomas License: GPL-2+ with linking exception ------------------------------------------- This file is part of eCos, the Embedded Configurable Operating System. Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. Copyright (C) 2002 Gary Thomas . eCos is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 or (at your option) any later version. . eCos is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. . You should have received a copy of the GNU General Public License along with eCos; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. . As a special exception, if other files instantiate templates or use macros or inline functions from this file, or you compile this file and link it with other works to produce a work based on this file, this file does not by itself cause the resulting work to be covered by the GNU General Public License. However the source code for this file must still be made available in accordance with section (3) of the GNU General Public License. . This exception does not invalidate any other reasons why a work based on this file might be covered by the GNU General Public License. . Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. at http://sources.redhat.com/ecos/ecos-license/ ------------------------------------------- Files: target_firmware/magpie_fw_dev/target/hif/usb_api_main_patch.c Copyright: 2016, Oleksij Rempel 2013, Qualcomm Atheros, Inc. License: BSD-3-clause-from-Qualcomm-Atheros Files: target_firmware/magpie_fw_dev/target/inc/asf_queue.h Copyright: 1991, 1993, The Regents of the University of California. License: BSD-3-clause-from-Regents Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 4. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. . THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Files: target_firmware/magpie_fw_dev/target/inc/xtensa-elf/* Copyright: 2013, Tensilica Inc. License: Expat Files: target_firmware/magpie_fw_dev/target/inc/xtensa/* Copyright: 2013, Tensilica Inc. License: Expat Files: target_firmware/magpie_fw_dev/target/init/app_start.h Copyright: 2016, Oleksij Rempel 2013, Qualcomm Atheros, Inc. License: BSD-3-clause-from-Qualcomm-Atheros Files: target_firmware/wlan/_ieee80211.h target_firmware/wlan/ieee80211.h Copyright: 2002-2005, Sam Leffler, Errno Consulting 2001, Atsushi Onoe License: BSD-3-clause or GPL-2 Files: target_firmware/wlan/ah_osdep.h Copyright: 2013, Qualcomm Atheros, Inc. 2002-2004, Sam Leffler, Errno Consulting, Atheros License: BSD-3-clause-from-Qualcomm-Atheros Files: target_firmware/wlan/if_ath_pci.c target_firmware/wlan/if_ath_pci.h Copyright: 2013, Qualcomm Atheros, Inc. 2004, Atheros Communications, Inc. 2002-2004, Sam Leffler, Errno Consulting License: BSD-3-clause-from-Qualcomm-Atheros or GPL-2 Files: target_firmware/wlan/if_athrate.h Copyright: 2013, Qualcomm Atheros, Inc. 2004, Video54 Technologies, Inc. 2004, Sam Leffler, Errno Consulting License: BSD-3-clause-from-Qualcomm-Atheros or GPL-2 Files: target_firmware/wlan/if_llc.h Copyright: 1988, 1993, The Regents of the University of California 2013, Qualcomm Atheros, Inc. 2002-2004, Sam Leffler, Errno Consulting License: BSD-3-clause-from-Qualcomm-Atheros and BSD-4-clause-from-Regents or GPL-2 License: BSD-3-clause-from-Qualcomm-Atheros All rights reserved. . Redistribution and use in source and binary forms, with or without modification, are permitted (subject to the limitations in the disclaimer below) provided that the following conditions are met: . * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. . * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. . * Neither the name of Qualcomm Atheros nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. . NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. License: BSD-4-clause-from-Regents Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. All advertising materials mentioning features or use of this software must display the following acknowledgement: This product includes software developed by the University of California, Berkeley and its contributors. 4. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. . THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. License: BSD-3-clause All rights reserved. . Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. The name of the author may not be used to endorse or promote products derived from this software without specific prior written permission. . THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. License: Expat Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: . The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. . THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. License: GPL-2 This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License version 2, as published by the Free Software Foundation. . This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. . On Debian systems, the full text of the GNU General Public License version 2 can be found in the file `/usr/share/common-licenses/GPL-2'. License: GPL-2+ This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. . This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. . On Debian systems, the full text of the GNU General Public License version 2 can be found in the file `/usr/share/common-licenses/GPL-2'. open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/debian/cross-toolchain.mk000066400000000000000000000063101321570333100252650ustar00rootroot00000000000000# Copyright (c) 2016 Aurelien Jarno # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This makefile allows to quickly build minimalistic cross-compilers # for various targets. They only support the C language and do not # support a C library. # # Most of the code is borrowed from the openbios Debian source package # # Support multiple makes at once based on number of processors ifneq (,$(filter parallel=%,$(DEB_BUILD_OPTIONS))) njobs = -j $(patsubst parallel=%,%,$(filter parallel=%,$(DEB_BUILD_OPTIONS))) endif gcc_major_version = 7 # GCC does not build with some hardening options and anyway we do not # ship the resulting binaries in the package toolchain_build_flags = CFLAGS="-g -O2" CXXFLAGS="-g -O2" CPPFLAGS="" LDFLAGS="" target = $(filter-out %_,$(subst _,_ ,$@)) toolchain_dir = $(CURDIR)/cross-toolchain stamp = $(toolchain_dir)/stamp- binutils_src_dir = /usr/src/binutils binutils_unpack_dir = $(toolchain_dir)/binutils-source binutils_build_dir = $(toolchain_dir)/binutils-$(target) gcc_src_dir = /usr/src/gcc-$(gcc_major_version) gcc_unpack_dir = $(toolchain_dir)/gcc-source gcc_build_dir = $(toolchain_dir)/gcc-$(target) # Use only xtensa-specific patches on top of upstream version binutils_patch = local/patches/binutils.patch gcc_patch = local/patches/gcc.patch $(stamp)binutils_unpack: mkdir -p $(binutils_unpack_dir) cd $(binutils_unpack_dir) && \ tar --strip-components=1 -xf $(binutils_src_dir)/binutils-*.tar.* && \ patch -p1 < $(CURDIR)/$(binutils_patch) touch $@ $(stamp)binutils_%: $(stamp)binutils_unpack mkdir -p $(binutils_build_dir) cd $(binutils_build_dir) && \ $(binutils_unpack_dir)/configure \ --build=$(DEB_BUILD_GNU_TYPE) \ --host=$(DEB_HOST_GNU_TYPE) \ --target=$(target) \ --prefix=$(toolchain_dir) \ --disable-nls \ --disable-plugins \ $(toolchain_build_flags) $(MAKE) $(njobs) -C $(binutils_build_dir) all $(MAKE) $(njobs) -C $(binutils_build_dir) install touch $@ $(stamp)gcc_unpack: mkdir -p $(gcc_unpack_dir) cd $(gcc_unpack_dir) && \ tar --strip-components=1 -xf $(gcc_src_dir)/gcc-*.tar.* && \ patch -p1 < $(CURDIR)/$(gcc_patch) && \ patch -p2 < $(gcc_src_dir)/patches/gcc-gfdl-build.diff touch $@ $(stamp)gcc_%: $(stamp)binutils_% $(stamp)gcc_unpack mkdir -p $(gcc_build_dir) cd $(gcc_build_dir) && \ $(gcc_unpack_dir)/configure \ --build=$(DEB_BUILD_GNU_TYPE) \ --host=$(DEB_HOST_GNU_TYPE) \ --target=$(target) \ --prefix=$(toolchain_dir) \ --enable-languages="c" \ --disable-multilib \ --disable-libffi \ --disable-libgomp \ --disable-libmudflap \ --disable-libquadmath \ --disable-libssp \ --disable-nls \ --disable-shared \ --disable-threads \ --disable-tls \ --disable-plugins \ --with-gnu-as \ --with-gnu-ld \ --with-headers=no \ --without-newlib \ $(toolchain_build_flags) $(MAKE) $(njobs) -C $(gcc_build_dir) all $(MAKE) $(njobs) -C $(gcc_build_dir) install touch $@ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/debian/firmware-ath9k-htc.install000066400000000000000000000002211321570333100266160ustar00rootroot00000000000000debian/ath9k_htc.conf etc/modprobe.d/ target_firmware/htc_*.fw lib/firmware/ath9k_htc/ debian/firmware-ath9k-htc.metainfo.xml usr/share/metainfo open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/debian/firmware-ath9k-htc.metainfo.xml000066400000000000000000000027401321570333100275610ustar00rootroot00000000000000 firmware-ath9k-htc MIT firmware-ath9k-htc Opensource version of QCA ath9k-htc firmware

Opensource version of QCA ath9k-htc firmware. Supported chips are: ar9271 and ar7010.

usb:v0CF3p9271d* usb:v0CF3p1006d* usb:v0846p9030d* usb:v07D1p3A10d* usb:v13D3p3327d* usb:v13D3p3328d* usb:v13D3p3346d* usb:v13D3p3348d* usb:v13D3p3349d* usb:v13D3p3350d* usb:v04CAp4605d* usb:v040Dp3801d* usb:v0CF3pB003d* usb:v0CF3pB002d* usb:v057Cp8403d* usb:v0471p209Ed* usb:v0CF3p7015d* usb:v1668p1200d* usb:v0CF3p7010d* usb:v0846p9018d* usb:v083ApA704d* usb:v0411p017Fd* usb:v0411p0197d* usb:v04DAp3904d* usb:v0930p0A08d* usb:v0CF3p20FFd* open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/debian/rules000077500000000000000000000021741321570333100227110ustar00rootroot00000000000000#!/usr/bin/make -f include /usr/share/dpkg/pkg-info.mk include debian/cross-toolchain.mk # We build a firmware, so we do not link to the ssp libraries export DEB_BUILD_MAINT_OPTIONS = hardening=-stackprotector DVU = $(DEB_VERSION_UPSTREAM) FW_FILENAME_VER = $(if $(findstring -,$(DVU)),$(shell echo $(DVU) | sed 's/\..*/.dev.0/'),$(DVU)) %: dh $@ override_dh_auto_configure: $(stamp)gcc_xtensa-elf override_dh_clean: rm -rf $(toolchain_dir) dh_clean override_dh_auto_build-indep: CROSS_COMPILE="$(toolchain_dir)/bin/xtensa-elf-" VERBOSE=1 $(MAKE) -C target_firmware override_dh_install-indep: mv target_firmware/htc_9271.fw target_firmware/htc_9271-$(FW_FILENAME_VER).fw mv target_firmware/htc_7010.fw target_firmware/htc_7010-$(FW_FILENAME_VER).fw dh_install install -D -m 0644 target_firmware/build/k2/fw.elf debian/.debhelper/${package}/dbgsym-root/usr/lib/debug/lib/firmware/ath9k_htc/htc_9271-$(FW_FILENAME_VER).elf install -D -m 0644 target_firmware/build/magpie/fw.elf debian/.debhelper/${package}/dbgsym-root/usr/lib/debug/lib/firmware/ath9k_htc/htc_7010-$(FW_FILENAME_VER).elf dh_strip -p${package} --no-automatic-dbgsym open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/debian/source/000077500000000000000000000000001321570333100231255ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/debian/source/format000066400000000000000000000000141321570333100243330ustar00rootroot000000000000003.0 (quilt) open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/debian/upstream/000077500000000000000000000000001321570333100234655ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/debian/upstream/metadata000066400000000000000000000005031321570333100251660ustar00rootroot00000000000000Name: open-ath9k-htc-firmware Homepage: https://github.com/qca/open-ath9k-htc-firmware Bug-Database: https://github.com/qca/open-ath9k-htc-firmware/issues Contact: ath9k_htc_fw@lists.infradead.org Repository: https://github.com/qca/open-ath9k-htc-firmware Repository-Browse: https://github.com/qca/open-ath9k-htc-firmware open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/debian/watch000066400000000000000000000004051321570333100226550ustar00rootroot00000000000000version=4 opts="filenamemangle=s%(?:.*?)?v?(\d[\d.]*)\.tar\.gz%open-ath9k-htc-firmware-$1.tar.gz%, \ repacksuffix=+dfsg, \ dversionmangle=s/\+dfsg//" \ https://github.com/qca/open-ath9k-htc-firmware/tags \ (?:.*?/)?v?(\d[\d.]*)\.tar\.gz open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/local/000077500000000000000000000000001321570333100214755ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/local/patches/000077500000000000000000000000001321570333100231245ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/local/patches/binutils-2.27_fixup.patch000066400000000000000000000007051321570333100276010ustar00rootroot00000000000000diff --git a/gas/config/tc-xtensa.c b/gas/config/tc-xtensa.c index d062044..ca261ae 100644 --- a/gas/config/tc-xtensa.c +++ b/gas/config/tc-xtensa.c @@ -2228,7 +2228,7 @@ xg_reverse_shift_count (char **cnt_argp) cnt_arg = *cnt_argp; /* replace the argument with "31-(argument)" */ - new_arg = concat ("31-(", cnt_argp, ")", (char *) NULL); + new_arg = concat ("31-(", cnt_arg, ")", (char *) NULL); free (cnt_arg); *cnt_argp = new_arg; open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/local/patches/binutils.patch000066400000000000000000026533141321570333100260140ustar00rootroot00000000000000From dbca73446265ce01b8e11462c3346b25953e3399 Mon Sep 17 00:00:00 2001 From: Sujith Manoharan Date: Mon, 7 Jan 2013 15:59:53 +0530 Subject: [PATCH] binutils: AR9271/AR7010 config Signed-off-by: Sujith Manoharan --- bfd/xtensa-modules.c | 27121 +++++++++++++--------------------------------- include/xtensa-config.h | 36 +- 2 files changed, 7663 insertions(+), 19494 deletions(-) diff --git a/bfd/xtensa-modules.c b/bfd/xtensa-modules.c index 3a79fcd..4704645 100644 --- a/bfd/xtensa-modules.c +++ b/bfd/xtensa-modules.c @@ -29,14 +29,6 @@ static xtensa_sysreg_internal sysregs[] = { { "LBEG", 0, 0 }, { "LEND", 1, 0 }, { "LCOUNT", 2, 0 }, - { "BR", 4, 0 }, - { "ACCLO", 16, 0 }, - { "ACCHI", 17, 0 }, - { "M0", 32, 0 }, - { "M1", 33, 0 }, - { "M2", 34, 0 }, - { "M3", 35, 0 }, - { "PTEVADDR", 83, 0 }, { "MMID", 89, 0 }, { "DDR", 104, 0 }, { "176", 176, 0 }, @@ -47,29 +39,21 @@ static xtensa_sysreg_internal sysregs[] = { { "PRID", 235, 0 }, { "ICOUNT", 236, 0 }, { "CCOMPARE0", 240, 0 }, - { "CCOMPARE1", 241, 0 }, - { "CCOMPARE2", 242, 0 }, { "VECBASE", 231, 0 }, { "EPC1", 177, 0 }, { "EPC2", 178, 0 }, { "EPC3", 179, 0 }, { "EPC4", 180, 0 }, { "EPC5", 181, 0 }, - { "EPC6", 182, 0 }, - { "EPC7", 183, 0 }, { "EXCSAVE1", 209, 0 }, { "EXCSAVE2", 210, 0 }, { "EXCSAVE3", 211, 0 }, { "EXCSAVE4", 212, 0 }, { "EXCSAVE5", 213, 0 }, - { "EXCSAVE6", 214, 0 }, - { "EXCSAVE7", 215, 0 }, { "EPS2", 194, 0 }, { "EPS3", 195, 0 }, { "EPS4", 196, 0 }, { "EPS5", 197, 0 }, - { "EPS6", 198, 0 }, - { "EPS7", 199, 0 }, { "EXCCAUSE", 232, 0 }, { "DEPC", 192, 0 }, { "EXCVADDR", 238, 0 }, @@ -80,8 +64,6 @@ static xtensa_sysreg_internal sysregs[] = { { "PS", 230, 0 }, { "MISC0", 244, 0 }, { "MISC1", 245, 0 }, - { "MISC2", 246, 0 }, - { "MISC3", 247, 0 }, { "INTENABLE", 228, 0 }, { "DBREAKA0", 144, 0 }, { "DBREAKC0", 160, 0 }, @@ -92,19 +74,13 @@ static xtensa_sysreg_internal sysregs[] = { { "IBREAKENABLE", 96, 0 }, { "ICOUNTLEVEL", 237, 0 }, { "DEBUGCAUSE", 233, 0 }, - { "RASID", 90, 0 }, - { "ITLBCFG", 91, 0 }, - { "DTLBCFG", 92, 0 }, - { "CPENABLE", 224, 0 }, { "SCOMPARE1", 12, 0 }, - { "THREADPTR", 231, 1 }, - { "FCR", 232, 1 }, - { "FSR", 233, 1 } + { "THREADPTR", 231, 1 } }; -#define NUM_SYSREGS 74 -#define MAX_SPECIAL_REG 247 -#define MAX_USER_REG 233 +#define NUM_SYSREGS 50 +#define MAX_SPECIAL_REG 245 +#define MAX_USER_REG 231 /* Processor states. */ @@ -114,40 +90,33 @@ static xtensa_state_internal states[] = { { "PC", 32, 0 }, { "ICOUNT", 32, 0 }, { "DDR", 32, 0 }, - { "INTERRUPT", 32, 0 }, + { "INTERRUPT", 19, 0 }, { "CCOUNT", 32, 0 }, { "XTSYNC", 1, 0 }, - { "VECBASE", 22, 0 }, + { "VECBASE", 21, 0 }, { "EPC1", 32, 0 }, { "EPC2", 32, 0 }, { "EPC3", 32, 0 }, { "EPC4", 32, 0 }, { "EPC5", 32, 0 }, - { "EPC6", 32, 0 }, - { "EPC7", 32, 0 }, { "EXCSAVE1", 32, 0 }, { "EXCSAVE2", 32, 0 }, { "EXCSAVE3", 32, 0 }, { "EXCSAVE4", 32, 0 }, { "EXCSAVE5", 32, 0 }, - { "EXCSAVE6", 32, 0 }, - { "EXCSAVE7", 32, 0 }, - { "EPS2", 15, 0 }, - { "EPS3", 15, 0 }, - { "EPS4", 15, 0 }, - { "EPS5", 15, 0 }, - { "EPS6", 15, 0 }, - { "EPS7", 15, 0 }, + { "EPS2", 13, 0 }, + { "EPS3", 13, 0 }, + { "EPS4", 13, 0 }, + { "EPS5", 13, 0 }, { "EXCCAUSE", 6, 0 }, { "PSINTLEVEL", 4, 0 }, { "PSUM", 1, 0 }, { "PSWOE", 1, 0 }, - { "PSRING", 2, 0 }, { "PSEXCM", 1, 0 }, { "DEPC", 32, 0 }, { "EXCVADDR", 32, 0 }, - { "WindowBase", 4, 0 }, - { "WindowStart", 16, 0 }, + { "WindowBase", 3, 0 }, + { "WindowStart", 8, 0 }, { "PSCALLINC", 2, 0 }, { "PSOWB", 4, 0 }, { "LBEG", 32, 0 }, @@ -158,11 +127,8 @@ static xtensa_state_internal states[] = { { "LITBEN", 1, 0 }, { "MISC0", 32, 0 }, { "MISC1", 32, 0 }, - { "MISC2", 32, 0 }, - { "MISC3", 32, 0 }, - { "ACC", 40, 0 }, { "InOCDMode", 1, 0 }, - { "INTENABLE", 32, 0 }, + { "INTENABLE", 19, 0 }, { "DBREAKA0", 32, 0 }, { "DBREAKC0", 8, 0 }, { "DBREAKA1", 32, 0 }, @@ -174,34 +140,10 @@ static xtensa_state_internal states[] = { { "DEBUGCAUSE", 6, 0 }, { "DBNUM", 4, 0 }, { "CCOMPARE0", 32, 0 }, - { "CCOMPARE1", 32, 0 }, - { "CCOMPARE2", 32, 0 }, - { "ASID3", 8, 0 }, - { "ASID2", 8, 0 }, - { "ASID1", 8, 0 }, - { "INSTPGSZID4", 2, 0 }, - { "DATAPGSZID4", 2, 0 }, - { "PTBASE", 10, 0 }, - { "CPENABLE", 1, 0 }, - { "SCOMPARE1", 32, 0 }, - { "RoundMode", 2, 0 }, - { "InvalidEnable", 1, 0 }, - { "DivZeroEnable", 1, 0 }, - { "OverflowEnable", 1, 0 }, - { "UnderflowEnable", 1, 0 }, - { "InexactEnable", 1, 0 }, - { "InvalidFlag", 1, 0 }, - { "DivZeroFlag", 1, 0 }, - { "OverflowFlag", 1, 0 }, - { "UnderflowFlag", 1, 0 }, - { "InexactFlag", 1, 0 }, - { "FPreserved20", 20, 0 }, - { "FPreserved20a", 20, 0 }, - { "FPreserved5", 5, 0 }, - { "FPreserved7", 7, 0 } -}; - -#define NUM_STATES 89 + { "SCOMPARE1", 32, 0 } +}; + +#define NUM_STATES 55 /* Macros for xtensa_state numbers (for use in iclasses because the state numbers are not available when the iclass table is generated). */ @@ -219,82 +161,48 @@ static xtensa_state_internal states[] = { #define STATE_EPC3 10 #define STATE_EPC4 11 #define STATE_EPC5 12 -#define STATE_EPC6 13 -#define STATE_EPC7 14 -#define STATE_EXCSAVE1 15 -#define STATE_EXCSAVE2 16 -#define STATE_EXCSAVE3 17 -#define STATE_EXCSAVE4 18 -#define STATE_EXCSAVE5 19 -#define STATE_EXCSAVE6 20 -#define STATE_EXCSAVE7 21 -#define STATE_EPS2 22 -#define STATE_EPS3 23 -#define STATE_EPS4 24 -#define STATE_EPS5 25 -#define STATE_EPS6 26 -#define STATE_EPS7 27 -#define STATE_EXCCAUSE 28 -#define STATE_PSINTLEVEL 29 -#define STATE_PSUM 30 -#define STATE_PSWOE 31 -#define STATE_PSRING 32 -#define STATE_PSEXCM 33 -#define STATE_DEPC 34 -#define STATE_EXCVADDR 35 -#define STATE_WindowBase 36 -#define STATE_WindowStart 37 -#define STATE_PSCALLINC 38 -#define STATE_PSOWB 39 -#define STATE_LBEG 40 -#define STATE_LEND 41 -#define STATE_SAR 42 -#define STATE_THREADPTR 43 -#define STATE_LITBADDR 44 -#define STATE_LITBEN 45 -#define STATE_MISC0 46 -#define STATE_MISC1 47 -#define STATE_MISC2 48 -#define STATE_MISC3 49 -#define STATE_ACC 50 -#define STATE_InOCDMode 51 -#define STATE_INTENABLE 52 -#define STATE_DBREAKA0 53 -#define STATE_DBREAKC0 54 -#define STATE_DBREAKA1 55 -#define STATE_DBREAKC1 56 -#define STATE_IBREAKA0 57 -#define STATE_IBREAKA1 58 -#define STATE_IBREAKENABLE 59 -#define STATE_ICOUNTLEVEL 60 -#define STATE_DEBUGCAUSE 61 -#define STATE_DBNUM 62 -#define STATE_CCOMPARE0 63 -#define STATE_CCOMPARE1 64 -#define STATE_CCOMPARE2 65 -#define STATE_ASID3 66 -#define STATE_ASID2 67 -#define STATE_ASID1 68 -#define STATE_INSTPGSZID4 69 -#define STATE_DATAPGSZID4 70 -#define STATE_PTBASE 71 -#define STATE_CPENABLE 72 -#define STATE_SCOMPARE1 73 -#define STATE_RoundMode 74 -#define STATE_InvalidEnable 75 -#define STATE_DivZeroEnable 76 -#define STATE_OverflowEnable 77 -#define STATE_UnderflowEnable 78 -#define STATE_InexactEnable 79 -#define STATE_InvalidFlag 80 -#define STATE_DivZeroFlag 81 -#define STATE_OverflowFlag 82 -#define STATE_UnderflowFlag 83 -#define STATE_InexactFlag 84 -#define STATE_FPreserved20 85 -#define STATE_FPreserved20a 86 -#define STATE_FPreserved5 87 -#define STATE_FPreserved7 88 +#define STATE_EXCSAVE1 13 +#define STATE_EXCSAVE2 14 +#define STATE_EXCSAVE3 15 +#define STATE_EXCSAVE4 16 +#define STATE_EXCSAVE5 17 +#define STATE_EPS2 18 +#define STATE_EPS3 19 +#define STATE_EPS4 20 +#define STATE_EPS5 21 +#define STATE_EXCCAUSE 22 +#define STATE_PSINTLEVEL 23 +#define STATE_PSUM 24 +#define STATE_PSWOE 25 +#define STATE_PSEXCM 26 +#define STATE_DEPC 27 +#define STATE_EXCVADDR 28 +#define STATE_WindowBase 29 +#define STATE_WindowStart 30 +#define STATE_PSCALLINC 31 +#define STATE_PSOWB 32 +#define STATE_LBEG 33 +#define STATE_LEND 34 +#define STATE_SAR 35 +#define STATE_THREADPTR 36 +#define STATE_LITBADDR 37 +#define STATE_LITBEN 38 +#define STATE_MISC0 39 +#define STATE_MISC1 40 +#define STATE_InOCDMode 41 +#define STATE_INTENABLE 42 +#define STATE_DBREAKA0 43 +#define STATE_DBREAKC0 44 +#define STATE_DBREAKA1 45 +#define STATE_DBREAKC1 46 +#define STATE_IBREAKA0 47 +#define STATE_IBREAKA1 48 +#define STATE_IBREAKENABLE 49 +#define STATE_ICOUNTLEVEL 50 +#define STATE_DEBUGCAUSE 51 +#define STATE_DBNUM 52 +#define STATE_CCOMPARE0 53 +#define STATE_SCOMPARE1 54 /* Field definitions. */ @@ -303,7 +211,7 @@ static unsigned Field_t_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); return tie_t; } @@ -312,14 +220,14 @@ Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); } static unsigned Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); return tie_t; } @@ -328,14 +236,14 @@ Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); } static unsigned Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); return tie_t; } @@ -344,20491 +252,8868 @@ Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); } static unsigned -Field_t_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) +Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); return tie_t; } static void -Field_t_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) +Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); } static unsigned -Field_t_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) +Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); return tie_t; } static void -Field_t_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) +Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); } static unsigned -Field_t_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) +Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20); return tie_t; } static void -Field_t_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) +Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff) | (tie_t << 0); } static unsigned -Field_t_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) +Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); return tie_t; } static void -Field_t_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) +Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); } static unsigned -Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) +Field_s_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); return tie_t; } static void -Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); } static unsigned -Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) +Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); return tie_t; } static void -Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); } static unsigned -Field_bbi_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) +Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); return tie_t; } static void -Field_bbi_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) +Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); } static unsigned -Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) +Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); return tie_t; } static void -Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; - tie_t = (val << 20) >> 20; - insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); } static unsigned -Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) +Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16); return tie_t; } static void -Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff) | (tie_t << 0); } static unsigned -Field_imm8_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) +Field_m_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); return tie_t; } static void -Field_imm8_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) +Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); } static unsigned -Field_imm8_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) +Field_n_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); return tie_t; } static void -Field_imm8_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) +Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); } static unsigned -Field_s_Slot_inst_get (const xtensa_insnbuf insn) +Field_offset_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); return tie_t; } static void -Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); } static unsigned -Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) +Field_op0_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); return tie_t; } static void -Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); } static unsigned -Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) +Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); return tie_t; } static void -Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); } static unsigned -Field_s_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) +Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); return tie_t; } static void -Field_s_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) +Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); } static unsigned -Field_s_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) +Field_op1_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); return tie_t; } static void -Field_s_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) +Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); } static unsigned -Field_s_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) +Field_op2_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); return tie_t; } static void -Field_s_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) +Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); } static unsigned -Field_s_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) +Field_r_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); return tie_t; } static void -Field_s_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) +Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); } static unsigned -Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) +Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); return tie_t; } static void -Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); - tie_t = (val << 20) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); } static unsigned -Field_imm12b_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) +Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); return tie_t; } static void -Field_imm12b_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) +Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); - tie_t = (val << 20) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); } static unsigned -Field_imm12b_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) +Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); return tie_t; } static void -Field_imm12b_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) +Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; - tie_t = (val << 20) >> 20; - insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); } static unsigned -Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) +Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); return tie_t; } static void -Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; - tie_t = (val << 16) >> 16; - insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); } static unsigned -Field_imm16_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) +Field_sae_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); return tie_t; } static void -Field_imm16_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) +Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; - tie_t = (val << 16) >> 16; - insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); } static unsigned -Field_m_Slot_inst_get (const xtensa_insnbuf insn) +Field_sal_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); return tie_t; } static void -Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); } static unsigned -Field_m_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) +Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); return tie_t; } static void -Field_m_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) +Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); } static unsigned -Field_n_Slot_inst_get (const xtensa_insnbuf insn) +Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); return tie_t; } static void -Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); } static unsigned -Field_n_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) +Field_sas_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); return tie_t; } static void -Field_n_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) +Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); } static unsigned -Field_offset_Slot_inst_get (const xtensa_insnbuf insn) +Field_sr_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); return tie_t; } static void -Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; - tie_t = (val << 14) >> 14; - insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); } static unsigned -Field_offset_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) +Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); return tie_t; } static void -Field_offset_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) +Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; - tie_t = (val << 14) >> 14; - insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); } static unsigned -Field_op0_Slot_inst_get (const xtensa_insnbuf insn) +Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); return tie_t; } static void -Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); } static unsigned -Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) +Field_st_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); return tie_t; } static void -Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); } static unsigned -Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) +Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); return tie_t; } static void -Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); } static unsigned -Field_op1_Slot_inst_get (const xtensa_insnbuf insn) +Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); return tie_t; } static void -Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); } static unsigned -Field_op1_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) +Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); return tie_t; } static void -Field_op1_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) +Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); } static unsigned -Field_op2_Slot_inst_get (const xtensa_insnbuf insn) +Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); return tie_t; } static void -Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); } static unsigned -Field_op2_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) +Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); return tie_t; } static void -Field_op2_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) +Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); } static unsigned -Field_op2_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) +Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); return tie_t; } static void -Field_op2_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) +Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); } static unsigned -Field_r_Slot_inst_get (const xtensa_insnbuf insn) +Field_mn_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); return tie_t; } static void -Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); } static unsigned -Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) +Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); return tie_t; } static void -Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); } static unsigned -Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) +Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); return tie_t; } static void -Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); } static unsigned -Field_r_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) +Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); return tie_t; } static void -Field_r_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) +Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); } static unsigned -Field_r_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) +Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); return tie_t; } static void -Field_r_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) +Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); } static unsigned -Field_r_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) +Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); return tie_t; } static void -Field_r_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) +Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); } static unsigned -Field_r_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) +Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); return tie_t; } static void -Field_r_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) +Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); } static unsigned -Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) +Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); return tie_t; } static void -Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); } static unsigned -Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) +Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); return tie_t; } static void -Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); } static unsigned -Field_sae4_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) +Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); return tie_t; } static void -Field_sae4_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) +Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); } static unsigned -Field_sae_Slot_inst_get (const xtensa_insnbuf insn) +Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); return tie_t; } static void -Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); } static unsigned -Field_sae_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) +Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); return tie_t; } static void -Field_sae_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) +Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); } static unsigned -Field_sae_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) +Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 15) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); return tie_t; } static void -Field_sae_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) +Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x1f000) | (tie_t << 12); + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); } static unsigned -Field_sal_Slot_inst_get (const xtensa_insnbuf insn) +Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); return tie_t; } static void -Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); } static unsigned -Field_sal_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) +Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); return tie_t; } static void -Field_sal_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) +Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); } static unsigned -Field_sal_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) +Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); return tie_t; } static void -Field_sal_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) +Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); } static unsigned -Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) +Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); return tie_t; } static void -Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); } static unsigned -Field_sargt_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) +Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); return tie_t; } static void -Field_sargt_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) +Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); } static unsigned -Field_sargt_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) +Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); return tie_t; } static void -Field_sargt_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) +Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); } -static unsigned -Field_sargt_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) +static void +Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, + uint32 val ATTRIBUTE_UNUSED) { - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); - return tie_t; + /* Do nothing. */ } -static void -Field_sargt_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) +static unsigned +Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) { - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); + return 0; } static unsigned -Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) +Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) { - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - return tie_t; + return 4; } -static void -Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +static unsigned +Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) { - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + return 8; } static unsigned -Field_sas_Slot_inst_get (const xtensa_insnbuf insn) +Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) { - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; + return 12; } -static void -Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) + +/* Functional units. */ + +static xtensa_funcUnit_internal funcUnits[] = { + +}; + + +/* Register files. */ + +static xtensa_regfile_internal regfiles[] = { + { "AR", "a", 0, 32, 32 } +}; + + +/* Interfaces. */ + +static xtensa_interface_internal interfaces[] = { + +}; + + +/* Constant tables. */ + +/* constant table ai4c */ +static const unsigned CONST_TBL_ai4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + 0 +}; + +/* constant table b4c */ +static const unsigned CONST_TBL_b4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + +/* constant table b4cu */ +static const unsigned CONST_TBL_b4cu_0[] = { + 0x8000, + 0x10000, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + + +/* Instruction operands. */ + +static int +Operand_soffsetx4_decode (uint32 *valp) { - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + unsigned soffsetx4_0, offset_0; + offset_0 = *valp & 0x3ffff; + soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2); + *valp = soffsetx4_0; + return 0; } -static unsigned -Field_sas_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) +static int +Operand_soffsetx4_encode (uint32 *valp) { - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; + unsigned offset_0, soffsetx4_0; + soffsetx4_0 = *valp; + offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff; + *valp = offset_0; + return 0; } -static void -Field_sas_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_soffsetx4_ator (uint32 *valp, uint32 pc) { - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + *valp -= (pc & ~0x3); + return 0; } -static unsigned -Field_sr_Slot_inst_get (const xtensa_insnbuf insn) +static int +Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) { - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; + *valp += (pc & ~0x3); + return 0; } -static void -Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_uimm12x8_decode (uint32 *valp) { - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + unsigned uimm12x8_0, imm12_0; + imm12_0 = *valp & 0xfff; + uimm12x8_0 = imm12_0 << 3; + *valp = uimm12x8_0; + return 0; } -static unsigned -Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) +static int +Operand_uimm12x8_encode (uint32 *valp) { - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; + unsigned imm12_0, uimm12x8_0; + uimm12x8_0 = *valp; + imm12_0 = ((uimm12x8_0 >> 3) & 0xfff); + *valp = imm12_0; + return 0; } -static void -Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_simm4_decode (uint32 *valp) { - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + unsigned simm4_0, mn_0; + mn_0 = *valp & 0xf; + simm4_0 = ((int) mn_0 << 28) >> 28; + *valp = simm4_0; + return 0; } -static unsigned -Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) +static int +Operand_simm4_encode (uint32 *valp) { - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; + unsigned mn_0, simm4_0; + simm4_0 = *valp; + mn_0 = (simm4_0 & 0xf); + *valp = mn_0; + return 0; } -static void -Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED) { - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + return 0; } -static unsigned -Field_st_Slot_inst_get (const xtensa_insnbuf insn) +static int +Operand_arr_encode (uint32 *valp) { - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; + int error; + error = (*valp & ~0xf) != 0; + return error; } -static void -Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED) { - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + return 0; } -static unsigned -Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) +static int +Operand_ars_encode (uint32 *valp) { - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; + int error; + error = (*valp & ~0xf) != 0; + return error; } -static void -Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED) { - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + return 0; } -static unsigned -Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) +static int +Operand_art_encode (uint32 *valp) { - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; + int error; + error = (*valp & ~0xf) != 0; + return error; } -static void -Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) +static int +Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED) { - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; + return 0; } -static void -Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_ar0_encode (uint32 *valp) { - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); + int error; + error = (*valp & ~0x1f) != 0; + return error; } -static unsigned -Field_thi3_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) +static int +Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED) { - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); - return tie_t; + return 0; } -static void -Field_thi3_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_ar4_encode (uint32 *valp) { - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + int error; + error = (*valp & ~0x1f) != 0; + return error; } -static unsigned -Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) +static int +Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED) { - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; + return 0; } -static void -Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_ar8_encode (uint32 *valp) { - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + int error; + error = (*valp & ~0x1f) != 0; + return error; } -static unsigned -Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) +static int +Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED) { - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; + return 0; } -static void -Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_ar12_encode (uint32 *valp) { - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + int error; + error = (*valp & ~0x1f) != 0; + return error; } -static unsigned -Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) +static int +Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED) { - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; + return 0; } -static void -Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_ars_entry_encode (uint32 *valp) { - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + int error; + error = (*valp & ~0x1f) != 0; + return error; } -static unsigned -Field_mn_Slot_inst_get (const xtensa_insnbuf insn) +static int +Operand_immrx4_decode (uint32 *valp) { - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; + unsigned immrx4_0, r_0; + r_0 = *valp & 0xf; + immrx4_0 = (((0xfffffff) << 4) | r_0) << 2; + *valp = immrx4_0; + return 0; } -static void -Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_immrx4_encode (uint32 *valp) { - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); + unsigned r_0, immrx4_0; + immrx4_0 = *valp; + r_0 = ((immrx4_0 >> 2) & 0xf); + *valp = r_0; + return 0; } -static unsigned -Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) +static int +Operand_lsi4x4_decode (uint32 *valp) { - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; + unsigned lsi4x4_0, r_0; + r_0 = *valp & 0xf; + lsi4x4_0 = r_0 << 2; + *valp = lsi4x4_0; + return 0; } -static void -Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_lsi4x4_encode (uint32 *valp) { - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + unsigned r_0, lsi4x4_0; + lsi4x4_0 = *valp; + r_0 = ((lsi4x4_0 >> 2) & 0xf); + *valp = r_0; + return 0; } -static unsigned -Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) +static int +Operand_simm7_decode (uint32 *valp) { - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; + unsigned simm7_0, imm7_0; + imm7_0 = *valp & 0x7f; + simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0; + *valp = simm7_0; + return 0; } -static void -Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_simm7_encode (uint32 *valp) { - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + unsigned imm7_0, simm7_0; + simm7_0 = *valp; + imm7_0 = (simm7_0 & 0x7f); + *valp = imm7_0; + return 0; } -static unsigned -Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) +static int +Operand_uimm6_decode (uint32 *valp) { - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; + unsigned uimm6_0, imm6_0; + imm6_0 = *valp & 0x3f; + uimm6_0 = 0x4 + (((0) << 6) | imm6_0); + *valp = uimm6_0; + return 0; } -static void -Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_uimm6_encode (uint32 *valp) { - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + unsigned imm6_0, uimm6_0; + uimm6_0 = *valp; + imm6_0 = (uimm6_0 - 0x4) & 0x3f; + *valp = imm6_0; + return 0; } -static unsigned -Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) +static int +Operand_uimm6_ator (uint32 *valp, uint32 pc) { - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; + *valp -= pc; + return 0; } -static void -Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_uimm6_rtoa (uint32 *valp, uint32 pc) { - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + *valp += pc; + return 0; } -static unsigned -Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) +static int +Operand_ai4const_decode (uint32 *valp) { - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; + unsigned ai4const_0, t_0; + t_0 = *valp & 0xf; + ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf]; + *valp = ai4const_0; + return 0; } -static void -Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_ai4const_encode (uint32 *valp) { - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + unsigned t_0, ai4const_0; + ai4const_0 = *valp; + switch (ai4const_0) + { + case 0xffffffff: t_0 = 0; break; + case 0x1: t_0 = 0x1; break; + case 0x2: t_0 = 0x2; break; + case 0x3: t_0 = 0x3; break; + case 0x4: t_0 = 0x4; break; + case 0x5: t_0 = 0x5; break; + case 0x6: t_0 = 0x6; break; + case 0x7: t_0 = 0x7; break; + case 0x8: t_0 = 0x8; break; + case 0x9: t_0 = 0x9; break; + case 0xa: t_0 = 0xa; break; + case 0xb: t_0 = 0xb; break; + case 0xc: t_0 = 0xc; break; + case 0xd: t_0 = 0xd; break; + case 0xe: t_0 = 0xe; break; + default: t_0 = 0xf; break; + } + *valp = t_0; + return 0; } -static unsigned -Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) +static int +Operand_b4const_decode (uint32 *valp) { - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; + unsigned b4const_0, r_0; + r_0 = *valp & 0xf; + b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf]; + *valp = b4const_0; + return 0; } -static void -Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_b4const_encode (uint32 *valp) { - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} + unsigned r_0, b4const_0; + b4const_0 = *valp; + switch (b4const_0) + { + case 0xffffffff: r_0 = 0; break; + case 0x1: r_0 = 0x1; break; + case 0x2: r_0 = 0x2; break; + case 0x3: r_0 = 0x3; break; + case 0x4: r_0 = 0x4; break; + case 0x5: r_0 = 0x5; break; + case 0x6: r_0 = 0x6; break; + case 0x7: r_0 = 0x7; break; + case 0x8: r_0 = 0x8; break; + case 0xa: r_0 = 0x9; break; + case 0xc: r_0 = 0xa; break; + case 0x10: r_0 = 0xb; break; + case 0x20: r_0 = 0xc; break; + case 0x40: r_0 = 0xd; break; + case 0x80: r_0 = 0xe; break; + default: r_0 = 0xf; break; + } + *valp = r_0; + return 0; +} -static unsigned -Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) +static int +Operand_b4constu_decode (uint32 *valp) { - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; + unsigned b4constu_0, r_0; + r_0 = *valp & 0xf; + b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf]; + *valp = b4constu_0; + return 0; } -static void -Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_b4constu_encode (uint32 *valp) { - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + unsigned r_0, b4constu_0; + b4constu_0 = *valp; + switch (b4constu_0) + { + case 0x8000: r_0 = 0; break; + case 0x10000: r_0 = 0x1; break; + case 0x2: r_0 = 0x2; break; + case 0x3: r_0 = 0x3; break; + case 0x4: r_0 = 0x4; break; + case 0x5: r_0 = 0x5; break; + case 0x6: r_0 = 0x6; break; + case 0x7: r_0 = 0x7; break; + case 0x8: r_0 = 0x8; break; + case 0xa: r_0 = 0x9; break; + case 0xc: r_0 = 0xa; break; + case 0x10: r_0 = 0xb; break; + case 0x20: r_0 = 0xc; break; + case 0x40: r_0 = 0xd; break; + case 0x80: r_0 = 0xe; break; + default: r_0 = 0xf; break; + } + *valp = r_0; + return 0; } -static unsigned -Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) +static int +Operand_uimm8_decode (uint32 *valp) { - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; + unsigned uimm8_0, imm8_0; + imm8_0 = *valp & 0xff; + uimm8_0 = imm8_0; + *valp = uimm8_0; + return 0; } -static void -Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_uimm8_encode (uint32 *valp) { - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + unsigned imm8_0, uimm8_0; + uimm8_0 = *valp; + imm8_0 = (uimm8_0 & 0xff); + *valp = imm8_0; + return 0; } -static unsigned -Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) +static int +Operand_uimm8x2_decode (uint32 *valp) { - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; + unsigned uimm8x2_0, imm8_0; + imm8_0 = *valp & 0xff; + uimm8x2_0 = imm8_0 << 1; + *valp = uimm8x2_0; + return 0; } -static void -Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_uimm8x2_encode (uint32 *valp) { - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); + unsigned imm8_0, uimm8x2_0; + uimm8x2_0 = *valp; + imm8_0 = ((uimm8x2_0 >> 1) & 0xff); + *valp = imm8_0; + return 0; } -static unsigned -Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) +static int +Operand_uimm8x4_decode (uint32 *valp) { - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; + unsigned uimm8x4_0, imm8_0; + imm8_0 = *valp & 0xff; + uimm8x4_0 = imm8_0 << 2; + *valp = uimm8x4_0; + return 0; } -static void -Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_uimm8x4_encode (uint32 *valp) { - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); + unsigned imm8_0, uimm8x4_0; + uimm8x4_0 = *valp; + imm8_0 = ((uimm8x4_0 >> 2) & 0xff); + *valp = imm8_0; + return 0; } -static unsigned -Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) +static int +Operand_uimm4x16_decode (uint32 *valp) { - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; + unsigned uimm4x16_0, op2_0; + op2_0 = *valp & 0xf; + uimm4x16_0 = op2_0 << 4; + *valp = uimm4x16_0; + return 0; } -static void -Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_uimm4x16_encode (uint32 *valp) { - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + unsigned op2_0, uimm4x16_0; + uimm4x16_0 = *valp; + op2_0 = ((uimm4x16_0 >> 4) & 0xf); + *valp = op2_0; + return 0; } -static unsigned -Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) +static int +Operand_simm8_decode (uint32 *valp) { - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; + unsigned simm8_0, imm8_0; + imm8_0 = *valp & 0xff; + simm8_0 = ((int) imm8_0 << 24) >> 24; + *valp = simm8_0; + return 0; } -static void -Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_simm8_encode (uint32 *valp) { - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + unsigned imm8_0, simm8_0; + simm8_0 = *valp; + imm8_0 = (simm8_0 & 0xff); + *valp = imm8_0; + return 0; } -static unsigned -Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) +static int +Operand_simm8x256_decode (uint32 *valp) { - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; + unsigned simm8x256_0, imm8_0; + imm8_0 = *valp & 0xff; + simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8; + *valp = simm8x256_0; + return 0; } -static void -Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_simm8x256_encode (uint32 *valp) { - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + unsigned imm8_0, simm8x256_0; + simm8x256_0 = *valp; + imm8_0 = ((simm8x256_0 >> 8) & 0xff); + *valp = imm8_0; + return 0; } -static unsigned -Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) +static int +Operand_simm12b_decode (uint32 *valp) { - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; + unsigned simm12b_0, imm12b_0; + imm12b_0 = *valp & 0xfff; + simm12b_0 = ((int) imm12b_0 << 20) >> 20; + *valp = simm12b_0; + return 0; } -static void -Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_simm12b_encode (uint32 *valp) { - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + unsigned imm12b_0, simm12b_0; + simm12b_0 = *valp; + imm12b_0 = (simm12b_0 & 0xfff); + *valp = imm12b_0; + return 0; } -static unsigned -Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) +static int +Operand_msalp32_decode (uint32 *valp) { - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; + unsigned msalp32_0, sal_0; + sal_0 = *valp & 0x1f; + msalp32_0 = 0x20 - sal_0; + *valp = msalp32_0; + return 0; } -static void -Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_msalp32_encode (uint32 *valp) { - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 25) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); + unsigned sal_0, msalp32_0; + msalp32_0 = *valp; + sal_0 = (0x20 - msalp32_0) & 0x1f; + *valp = sal_0; + return 0; } -static unsigned -Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; +static int +Operand_op2p1_decode (uint32 *valp) +{ + unsigned op2p1_0, op2_0; + op2_0 = *valp & 0xf; + op2p1_0 = op2_0 + 0x1; + *valp = op2p1_0; + return 0; } -static void -Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_op2p1_encode (uint32 *valp) { - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 25) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); + unsigned op2_0, op2p1_0; + op2p1_0 = *valp; + op2_0 = (op2p1_0 - 0x1) & 0xf; + *valp = op2_0; + return 0; } -static unsigned -Field_imm7_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) +static int +Operand_label8_decode (uint32 *valp) { - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; + unsigned label8_0, imm8_0; + imm8_0 = *valp & 0xff; + label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24); + *valp = label8_0; + return 0; } -static void -Field_imm7_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_label8_encode (uint32 *valp) { - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); + unsigned imm8_0, label8_0; + label8_0 = *valp; + imm8_0 = (label8_0 - 0x4) & 0xff; + *valp = imm8_0; + return 0; } -static unsigned -Field_r3_Slot_inst_get (const xtensa_insnbuf insn) +static int +Operand_label8_ator (uint32 *valp, uint32 pc) { - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; + *valp -= pc; + return 0; } -static void -Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_label8_rtoa (uint32 *valp, uint32 pc) { - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + *valp += pc; + return 0; } -static unsigned -Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn) +static int +Operand_ulabel8_decode (uint32 *valp) { - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); - return tie_t; + unsigned ulabel8_0, imm8_0; + imm8_0 = *valp & 0xff; + ulabel8_0 = 0x4 + (((0) << 8) | imm8_0); + *valp = ulabel8_0; + return 0; } -static void -Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_ulabel8_encode (uint32 *valp) { - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); + unsigned imm8_0, ulabel8_0; + ulabel8_0 = *valp; + imm8_0 = (ulabel8_0 - 0x4) & 0xff; + *valp = imm8_0; + return 0; } -static unsigned -Field_rhi_Slot_inst_get (const xtensa_insnbuf insn) +static int +Operand_ulabel8_ator (uint32 *valp, uint32 pc) { - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; + *valp -= pc; + return 0; } -static void -Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) { - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + *valp += pc; + return 0; } -static unsigned -Field_t3_Slot_inst_get (const xtensa_insnbuf insn) +static int +Operand_label12_decode (uint32 *valp) { - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; + unsigned label12_0, imm12_0; + imm12_0 = *valp & 0xfff; + label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20); + *valp = label12_0; + return 0; } -static void -Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_label12_encode (uint32 *valp) { - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + unsigned imm12_0, label12_0; + label12_0 = *valp; + imm12_0 = (label12_0 - 0x4) & 0xfff; + *valp = imm12_0; + return 0; } -static unsigned -Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn) +static int +Operand_label12_ator (uint32 *valp, uint32 pc) { - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; + *valp -= pc; + return 0; } -static void -Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_label12_rtoa (uint32 *valp, uint32 pc) { - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + *valp += pc; + return 0; } -static unsigned -Field_tlo_Slot_inst_get (const xtensa_insnbuf insn) +static int +Operand_soffset_decode (uint32 *valp) { - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; + unsigned soffset_0, offset_0; + offset_0 = *valp & 0x3ffff; + soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14); + *valp = soffset_0; + return 0; } -static void -Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_soffset_encode (uint32 *valp) { - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + unsigned offset_0, soffset_0; + soffset_0 = *valp; + offset_0 = (soffset_0 - 0x4) & 0x3ffff; + *valp = offset_0; + return 0; } -static unsigned -Field_w_Slot_inst_get (const xtensa_insnbuf insn) +static int +Operand_soffset_ator (uint32 *valp, uint32 pc) { - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); - return tie_t; + *valp -= pc; + return 0; } -static void -Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_soffset_rtoa (uint32 *valp, uint32 pc) { - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); + *valp += pc; + return 0; } -static unsigned -Field_y_Slot_inst_get (const xtensa_insnbuf insn) +static int +Operand_uimm16x4_decode (uint32 *valp) { - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; + unsigned uimm16x4_0, imm16_0; + imm16_0 = *valp & 0xffff; + uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2; + *valp = uimm16x4_0; + return 0; } -static void -Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_uimm16x4_encode (uint32 *valp) { - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + unsigned imm16_0, uimm16x4_0; + uimm16x4_0 = *valp; + imm16_0 = (uimm16x4_0 >> 2) & 0xffff; + *valp = imm16_0; + return 0; } -static unsigned -Field_x_Slot_inst_get (const xtensa_insnbuf insn) +static int +Operand_uimm16x4_ator (uint32 *valp, uint32 pc) { - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); - return tie_t; + *valp -= ((pc + 3) & ~0x3); + return 0; } -static void -Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) { - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); + *valp += ((pc + 3) & ~0x3); + return 0; } -static unsigned -Field_t2_Slot_inst_get (const xtensa_insnbuf insn) +static int +Operand_immt_decode (uint32 *valp) { - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; + unsigned immt_0, t_0; + t_0 = *valp & 0xf; + immt_0 = t_0; + *valp = immt_0; + return 0; } -static void -Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_immt_encode (uint32 *valp) { - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); + unsigned t_0, immt_0; + immt_0 = *valp; + t_0 = immt_0 & 0xf; + *valp = t_0; + return 0; } -static unsigned -Field_t2_Slot_inst16a_get (const xtensa_insnbuf insn) +static int +Operand_imms_decode (uint32 *valp) { - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; + unsigned imms_0, s_0; + s_0 = *valp & 0xf; + imms_0 = s_0; + *valp = imms_0; + return 0; } -static void -Field_t2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_imms_encode (uint32 *valp) { - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); + unsigned s_0, imms_0; + imms_0 = *valp; + s_0 = imms_0 & 0xf; + *valp = s_0; + return 0; } -static unsigned -Field_t2_Slot_inst16b_get (const xtensa_insnbuf insn) +static int +Operand_tp7_decode (uint32 *valp) { - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; + unsigned tp7_0, t_0; + t_0 = *valp & 0xf; + tp7_0 = t_0 + 0x7; + *valp = tp7_0; + return 0; } -static void -Field_t2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_tp7_encode (uint32 *valp) { - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); + unsigned t_0, tp7_0; + tp7_0 = *valp; + t_0 = (tp7_0 - 0x7) & 0xf; + *valp = t_0; + return 0; } -static unsigned -Field_s2_Slot_inst_get (const xtensa_insnbuf insn) +static int +Operand_xt_wbr15_label_decode (uint32 *valp) { - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; + unsigned xt_wbr15_label_0, xt_wbr15_imm_0; + xt_wbr15_imm_0 = *valp & 0x7fff; + xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17); + *valp = xt_wbr15_label_0; + return 0; } -static void -Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_xt_wbr15_label_encode (uint32 *valp) { - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); + unsigned xt_wbr15_imm_0, xt_wbr15_label_0; + xt_wbr15_label_0 = *valp; + xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff; + *valp = xt_wbr15_imm_0; + return 0; } -static unsigned -Field_s2_Slot_inst16a_get (const xtensa_insnbuf insn) +static int +Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) { - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; + *valp -= pc; + return 0; } -static void -Field_s2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) { - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); + *valp += pc; + return 0; } -static unsigned -Field_s2_Slot_inst16b_get (const xtensa_insnbuf insn) +static int +Operand_xt_wbr18_label_decode (uint32 *valp) { - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; + unsigned xt_wbr18_label_0, xt_wbr18_imm_0; + xt_wbr18_imm_0 = *valp & 0x3ffff; + xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14); + *valp = xt_wbr18_label_0; + return 0; } -static void -Field_s2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_xt_wbr18_label_encode (uint32 *valp) { - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); + unsigned xt_wbr18_imm_0, xt_wbr18_label_0; + xt_wbr18_label_0 = *valp; + xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff; + *valp = xt_wbr18_imm_0; + return 0; } -static unsigned -Field_r2_Slot_inst_get (const xtensa_insnbuf insn) +static int +Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) { - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); - return tie_t; + *valp -= pc; + return 0; } -static void -Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +static int +Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) { - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); + *valp += pc; + return 0; } -static unsigned -Field_r2_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); - return tie_t; -} +static xtensa_operand_internal operands[] = { + { "soffsetx4", 10, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_soffsetx4_encode, Operand_soffsetx4_decode, + Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, + { "uimm12x8", 3, -1, 0, + 0, + Operand_uimm12x8_encode, Operand_uimm12x8_decode, + 0, 0 }, + { "simm4", 26, -1, 0, + 0, + Operand_simm4_encode, Operand_simm4_decode, + 0, 0 }, + { "arr", 14, 0, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_arr_encode, Operand_arr_decode, + 0, 0 }, + { "ars", 5, 0, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_ars_encode, Operand_ars_decode, + 0, 0 }, + { "*ars_invisible", 5, 0, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ars_encode, Operand_ars_decode, + 0, 0 }, + { "art", 0, 0, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_art_encode, Operand_art_decode, + 0, 0 }, + { "ar0", 37, 0, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ar0_encode, Operand_ar0_decode, + 0, 0 }, + { "ar4", 38, 0, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ar4_encode, Operand_ar4_decode, + 0, 0 }, + { "ar8", 39, 0, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ar8_encode, Operand_ar8_decode, + 0, 0 }, + { "ar12", 40, 0, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ar12_encode, Operand_ar12_decode, + 0, 0 }, + { "ars_entry", 5, 0, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_ars_entry_encode, Operand_ars_entry_decode, + 0, 0 }, + { "immrx4", 14, -1, 0, + 0, + Operand_immrx4_encode, Operand_immrx4_decode, + 0, 0 }, + { "lsi4x4", 14, -1, 0, + 0, + Operand_lsi4x4_encode, Operand_lsi4x4_decode, + 0, 0 }, + { "simm7", 34, -1, 0, + 0, + Operand_simm7_encode, Operand_simm7_decode, + 0, 0 }, + { "uimm6", 33, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_uimm6_encode, Operand_uimm6_decode, + Operand_uimm6_ator, Operand_uimm6_rtoa }, + { "ai4const", 0, -1, 0, + 0, + Operand_ai4const_encode, Operand_ai4const_decode, + 0, 0 }, + { "b4const", 14, -1, 0, + 0, + Operand_b4const_encode, Operand_b4const_decode, + 0, 0 }, + { "b4constu", 14, -1, 0, + 0, + Operand_b4constu_encode, Operand_b4constu_decode, + 0, 0 }, + { "uimm8", 4, -1, 0, + 0, + Operand_uimm8_encode, Operand_uimm8_decode, + 0, 0 }, + { "uimm8x2", 4, -1, 0, + 0, + Operand_uimm8x2_encode, Operand_uimm8x2_decode, + 0, 0 }, + { "uimm8x4", 4, -1, 0, + 0, + Operand_uimm8x4_encode, Operand_uimm8x4_decode, + 0, 0 }, + { "uimm4x16", 13, -1, 0, + 0, + Operand_uimm4x16_encode, Operand_uimm4x16_decode, + 0, 0 }, + { "simm8", 4, -1, 0, + 0, + Operand_simm8_encode, Operand_simm8_decode, + 0, 0 }, + { "simm8x256", 4, -1, 0, + 0, + Operand_simm8x256_encode, Operand_simm8x256_decode, + 0, 0 }, + { "simm12b", 6, -1, 0, + 0, + Operand_simm12b_encode, Operand_simm12b_decode, + 0, 0 }, + { "msalp32", 18, -1, 0, + 0, + Operand_msalp32_encode, Operand_msalp32_decode, + 0, 0 }, + { "op2p1", 13, -1, 0, + 0, + Operand_op2p1_encode, Operand_op2p1_decode, + 0, 0 }, + { "label8", 4, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_label8_encode, Operand_label8_decode, + Operand_label8_ator, Operand_label8_rtoa }, + { "ulabel8", 4, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_ulabel8_encode, Operand_ulabel8_decode, + Operand_ulabel8_ator, Operand_ulabel8_rtoa }, + { "label12", 3, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_label12_encode, Operand_label12_decode, + Operand_label12_ator, Operand_label12_rtoa }, + { "soffset", 10, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_soffset_encode, Operand_soffset_decode, + Operand_soffset_ator, Operand_soffset_rtoa }, + { "uimm16x4", 7, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_uimm16x4_encode, Operand_uimm16x4_decode, + Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, + { "immt", 0, -1, 0, + 0, + Operand_immt_encode, Operand_immt_decode, + 0, 0 }, + { "imms", 5, -1, 0, + 0, + Operand_imms_encode, Operand_imms_decode, + 0, 0 }, + { "tp7", 0, -1, 0, + 0, + Operand_tp7_encode, Operand_tp7_decode, + 0, 0 }, + { "xt_wbr15_label", 35, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode, + Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, + { "xt_wbr18_label", 36, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode, + Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, + { "t", 0, -1, 0, 0, 0, 0, 0, 0 }, + { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 }, + { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 }, + { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 }, + { "s", 5, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 }, + { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 }, + { "m", 8, -1, 0, 0, 0, 0, 0, 0 }, + { "n", 9, -1, 0, 0, 0, 0, 0, 0 }, + { "offset", 10, -1, 0, 0, 0, 0, 0, 0 }, + { "op0", 11, -1, 0, 0, 0, 0, 0, 0 }, + { "op1", 12, -1, 0, 0, 0, 0, 0, 0 }, + { "op2", 13, -1, 0, 0, 0, 0, 0, 0 }, + { "r", 14, -1, 0, 0, 0, 0, 0, 0 }, + { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 }, + { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 }, + { "sae", 17, -1, 0, 0, 0, 0, 0, 0 }, + { "sal", 18, -1, 0, 0, 0, 0, 0, 0 }, + { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 }, + { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 }, + { "sas", 21, -1, 0, 0, 0, 0, 0, 0 }, + { "sr", 22, -1, 0, 0, 0, 0, 0, 0 }, + { "st", 23, -1, 0, 0, 0, 0, 0, 0 }, + { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 }, + { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 }, + { "mn", 26, -1, 0, 0, 0, 0, 0, 0 }, + { "i", 27, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 }, + { "z", 32, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr15_imm", 35, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr18_imm", 36, -1, 0, 0, 0, 0, 0, 0 } +}; -static void -Field_r2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); -} + +/* Iclass table. */ -static unsigned -Field_r2_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { + { { STATE_PSEXCM }, 'o' }, + { { STATE_EPC1 }, 'i' } +}; -static void -Field_r2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); -} +static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { + { { STATE_DEPC }, 'i' } +}; -static unsigned -Field_t4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { + { { 0 /* soffsetx4 */ }, 'i' }, + { { 10 /* ar12 */ }, 'o' } +}; -static void -Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} +static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; -static unsigned -Field_t4_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { + { { 0 /* soffsetx4 */ }, 'i' }, + { { 9 /* ar8 */ }, 'o' } +}; -static void -Field_t4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} +static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; -static unsigned -Field_t4_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { + { { 0 /* soffsetx4 */ }, 'i' }, + { { 8 /* ar4 */ }, 'o' } +}; -static void -Field_t4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} +static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; -static unsigned -Field_s4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 10 /* ar12 */ }, 'o' } +}; -static void -Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); -} +static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; -static unsigned -Field_s4_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 9 /* ar8 */ }, 'o' } +}; -static void -Field_s4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); -} +static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; -static unsigned -Field_s4_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 8 /* ar4 */ }, 'o' } +}; -static void -Field_s4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); -} +static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; -static unsigned -Field_r4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { + { { 11 /* ars_entry */ }, 's' }, + { { 4 /* ars */ }, 'i' }, + { { 1 /* uimm12x8 */ }, 'i' } +}; -static void -Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} +static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' } +}; -static unsigned -Field_r4_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; -static void -Field_r4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} +static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { + { { STATE_WindowBase }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; -static unsigned -Field_r4_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { + { { 2 /* simm4 */ }, 'i' } +}; -static void -Field_r4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} +static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { + { { STATE_WindowBase }, 'm' } +}; -static unsigned -Field_t8_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { + { { 5 /* *ars_invisible */ }, 'i' } +}; -static void -Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} +static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' } +}; -static unsigned -Field_t8_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { + { { STATE_EPC1 }, 'i' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSOWB }, 'i' } +}; -static void -Field_t8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} +static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 12 /* immrx4 */ }, 'i' } +}; -static unsigned -Field_t8_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' }, + { { 12 /* immrx4 */ }, 'i' } +}; -static void -Field_t8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { + { { 6 /* art */ }, 'o' } +}; -static unsigned -Field_s8_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { + { { STATE_WindowBase }, 'i' } +}; -static void -Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { + { { 6 /* art */ }, 'i' } +}; -static unsigned -Field_s8_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_s8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { + { { STATE_WindowBase }, 'o' } +}; -static unsigned -Field_s8_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { + { { 6 /* art */ }, 'm' } +}; -static void -Field_s8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { + { { STATE_WindowBase }, 'm' } +}; -static unsigned -Field_r8_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { + { { 6 /* art */ }, 'o' } +}; -static void -Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { + { { STATE_WindowStart }, 'i' } +}; -static unsigned -Field_r8_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { + { { 6 /* art */ }, 'i' } +}; -static void -Field_r8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { + { { STATE_WindowStart }, 'o' } +}; -static unsigned -Field_r8_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { + { { 6 /* art */ }, 'm' } +}; -static void -Field_r8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { + { { STATE_WindowStart }, 'm' } +}; -static unsigned -Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; -static void -Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 17) >> 17; - insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); -} +static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 16 /* ai4const */ }, 'i' } +}; -static unsigned -Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 15 /* uimm6 */ }, 'i' } +}; -static void -Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 14) >> 14; - insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); -} +static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 13 /* lsi4x4 */ }, 'i' } +}; -static unsigned -Field_xt_wbr18_imm_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 18) | ((insn[0] << 6) >> 14); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; -static void -Field_xt_wbr18_imm_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 14) >> 14; - insn[0] = (insn[0] & ~0x3ffff00) | (tie_t << 8); -} +static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { + { { 4 /* ars */ }, 'o' }, + { { 14 /* simm7 */ }, 'i' } +}; -static unsigned -Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { + { { 5 /* *ars_invisible */ }, 'i' } +}; -static void -Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); -} +static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' }, + { { 13 /* lsi4x4 */ }, 'i' } +}; -static unsigned -Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); - return tie_t; -} +static xtensa_arg_internal Iclass_rur_threadptr_args[] = { + { { 3 /* arr */ }, 'o' } +}; -static void -Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); -} +static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'i' } +}; -static unsigned -Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); - return tie_t; -} +static xtensa_arg_internal Iclass_wur_threadptr_args[] = { + { { 6 /* art */ }, 'i' } +}; -static void -Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); -} +static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'o' } +}; -static unsigned -Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 23 /* simm8 */ }, 'i' } +}; -static void -Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); -} +static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 24 /* simm8x256 */ }, 'i' } +}; -static unsigned -Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; -static void -Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); -} +static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; -static unsigned -Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 17 /* b4const */ }, 'i' }, + { { 28 /* label8 */ }, 'i' } +}; -static void -Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); -} +static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 40 /* bbi */ }, 'i' }, + { { 28 /* label8 */ }, 'i' } +}; -static unsigned -Field_op0_s4_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 18 /* b4constu */ }, 'i' }, + { { 28 /* label8 */ }, 'i' } +}; -static void -Field_op0_s4_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); -} +static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' }, + { { 28 /* label8 */ }, 'i' } +}; -static unsigned -Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 30 /* label12 */ }, 'i' } +}; -static void -Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} +static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { + { { 0 /* soffsetx4 */ }, 'i' }, + { { 7 /* ar0 */ }, 'o' } +}; -static unsigned -Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 7 /* ar0 */ }, 'o' } +}; -static void -Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); -} +static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 6 /* art */ }, 'i' }, + { { 55 /* sae */ }, 'i' }, + { { 27 /* op2p1 */ }, 'i' } +}; -static unsigned -Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { + { { 31 /* soffset */ }, 'i' } +}; -static void -Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); -} +static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { + { { 4 /* ars */ }, 'i' } +}; -static unsigned -Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 20 /* uimm8x2 */ }, 'i' } +}; -static void -Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); -} +static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 20 /* uimm8x2 */ }, 'i' } +}; -static unsigned -Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; -static void -Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 26) >> 26; - insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12); -} +static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { + { { 6 /* art */ }, 'o' }, + { { 32 /* uimm16x4 */ }, 'i' } +}; -static unsigned -Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26); - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = { + { { STATE_LITBADDR }, 'i' }, + { { STATE_LITBEN }, 'i' } +}; -static void -Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); - tie_t = (val << 23) >> 26; - insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12); -} +static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 19 /* uimm8 */ }, 'i' } +}; -static unsigned -Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26); - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 29 /* ulabel8 */ }, 'i' } +}; -static void -Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); - tie_t = (val << 23) >> 26; - insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12); -} +static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; -static unsigned -Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26); - tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 29 /* ulabel8 */ }, 'i' } +}; -static void -Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x60) | (tie_t << 5); - tie_t = (val << 24) >> 26; - insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12); -} +static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; -static unsigned -Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26); - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { + { { 6 /* art */ }, 'o' }, + { { 25 /* simm12b */ }, 'i' } +}; -static void -Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); - tie_t = (val << 25) >> 26; - insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12); -} +static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { + { { 3 /* arr */ }, 'm' }, + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; -static unsigned -Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26); - tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 6 /* art */ }, 'i' } +}; -static void -Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x300) | (tie_t << 8); - tie_t = (val << 24) >> 26; - insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12); -} +static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { + { { 5 /* *ars_invisible */ }, 'i' } +}; -static unsigned -Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26); - tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' }, + { { 20 /* uimm8x2 */ }, 'i' } +}; -static void -Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x300) | (tie_t << 8); - tie_t = (val << 24) >> 26; - insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12); -} +static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; -static unsigned -Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26); - tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' }, + { { 19 /* uimm8 */ }, 'i' } +}; -static void -Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x200) | (tie_t << 9); - tie_t = (val << 25) >> 26; - insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12); -} +static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { + { { 4 /* ars */ }, 'i' } +}; -static unsigned -Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; -static void -Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); -} +static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { + { { 59 /* sas */ }, 'i' } +}; -static unsigned -Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; -static void -Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} +static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; -static unsigned -Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; -static void -Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} +static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; -static unsigned -Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; -static void -Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); -} +static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 6 /* art */ }, 'i' } +}; -static unsigned -Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); - tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; -static void -Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 26) >> 26; - insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); - tie_t = (val << 21) >> 27; - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); -} +static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 26 /* msalp32 */ }, 'i' } +}; -static unsigned -Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 6 /* art */ }, 'i' }, + { { 57 /* sargt */ }, 'i' } +}; -static void -Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} +static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 6 /* art */ }, 'i' }, + { { 43 /* s */ }, 'i' } +}; -static unsigned -Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { + { { STATE_XTSYNC }, 'i' } +}; -static void -Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); -} +static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { + { { 6 /* art */ }, 'o' }, + { { 43 /* s */ }, 'i' } +}; -static unsigned -Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'm' } +}; -static void -Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); - tie_t = (val << 26) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { + { { 6 /* art */ }, 'o' } +}; -static unsigned -Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { + { { STATE_LEND }, 'i' } +}; -static void -Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { + { { 6 /* art */ }, 'i' } +}; -static unsigned -Field_op0_s5_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { + { { STATE_LEND }, 'o' } +}; -static void -Field_op0_s5_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { + { { 6 /* art */ }, 'm' } +}; -static unsigned -Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { + { { STATE_LEND }, 'm' } +}; -static void -Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { + { { 6 /* art */ }, 'o' } +}; -static unsigned -Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { + { { STATE_LCOUNT }, 'i' } +}; -static void -Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { + { { 6 /* art */ }, 'i' } +}; -static unsigned -Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; -static void -Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 29) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { + { { 6 /* art */ }, 'm' } +}; -static unsigned -Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'm' } +}; -static void -Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 29) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { + { { 6 /* art */ }, 'o' } +}; -static unsigned -Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'i' } +}; -static void -Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x700) | (tie_t << 8); - tie_t = (val << 28) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { + { { 6 /* art */ }, 'i' } +}; -static unsigned -Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'o' } +}; -static void -Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x700) | (tie_t << 8); - tie_t = (val << 28) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { + { { 6 /* art */ }, 'm' } +}; -static unsigned -Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'm' } +}; -static void -Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 29) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { + { { 6 /* art */ }, 'o' } +}; -static unsigned -Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; -static void -Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x400) | (tie_t << 10); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { + { { 6 /* art */ }, 'i' } +}; -static unsigned -Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { + { { STATE_SAR }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; -static void -Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x60) | (tie_t << 5); -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { + { { 6 /* art */ }, 'm' } +}; -static unsigned -Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { + { { STATE_SAR }, 'm' } +}; -static void -Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { + { { 6 /* art */ }, 'o' } +}; -static unsigned -Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = { + { { STATE_LITBADDR }, 'i' }, + { { STATE_LITBEN }, 'i' } +}; -static void -Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x60) | (tie_t << 5); - tie_t = (val << 22) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { + { { 6 /* art */ }, 'i' } +}; -static unsigned -Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = { + { { STATE_LITBADDR }, 'o' }, + { { STATE_LITBEN }, 'o' } +}; -static void -Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { + { { 6 /* art */ }, 'm' } +}; -static unsigned -Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = { + { { STATE_LITBADDR }, 'm' }, + { { STATE_LITBEN }, 'm' } +}; -static void -Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x300) | (tie_t << 8); - tie_t = (val << 29) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = { + { { 6 /* art */ }, 'o' } +}; -static unsigned -Field_op0_s6_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 0) >> 27); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = { + { { 6 /* art */ }, 'o' } +}; -static void -Field_op0_s6_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf8000000) | (tie_t << 27); -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { + { { 6 /* art */ }, 'o' } +}; -static unsigned -Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; -static void -Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); - tie_t = (val << 24) >> 29; - insn[1] = (insn[1] & ~0x7) | (tie_t << 0); -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { + { { 6 /* art */ }, 'i' } +}; -static unsigned -Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' } +}; -static void -Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[1] = (insn[1] & ~0x7) | (tie_t << 0); -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { + { { 6 /* art */ }, 'm' } +}; -static unsigned -Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'm' }, + { { STATE_PSCALLINC }, 'm' }, + { { STATE_PSOWB }, 'm' }, + { { STATE_PSUM }, 'm' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'm' } +}; -static void -Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); - tie_t = (val << 24) >> 29; - insn[1] = (insn[1] & ~0x7) | (tie_t << 0); -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { + { { 6 /* art */ }, 'o' } +}; -static unsigned -Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); - tie_t = (val << 24) >> 29; - insn[1] = (insn[1] & ~0x7) | (tie_t << 0); -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { + { { STATE_EPC1 }, 'i' } +}; -static unsigned -Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { + { { 6 /* art */ }, 'i' } +}; -static void -Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); - tie_t = (val << 24) >> 29; - insn[1] = (insn[1] & ~0x7) | (tie_t << 0); -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { + { { STATE_EPC1 }, 'o' } +}; -static unsigned -Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { + { { 6 /* art */ }, 'm' } +}; -static void -Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); - tie_t = (val << 28) >> 29; - insn[1] = (insn[1] & ~0x7) | (tie_t << 0); -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { + { { STATE_EPC1 }, 'm' } +}; -static unsigned -Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { + { { 6 /* art */ }, 'o' } +}; -static void -Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); - tie_t = (val << 28) >> 29; - insn[1] = (insn[1] & ~0x7) | (tie_t << 0); -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { + { { STATE_EXCSAVE1 }, 'i' } +}; -static unsigned -Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { + { { 6 /* art */ }, 'i' } +}; -static void -Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); - tie_t = (val << 28) >> 29; - insn[1] = (insn[1] & ~0x7) | (tie_t << 0); -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { + { { STATE_EXCSAVE1 }, 'o' } +}; -static unsigned -Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { + { { 6 /* art */ }, 'm' } +}; -static void -Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); - tie_t = (val << 28) >> 29; - insn[1] = (insn[1] & ~0x7) | (tie_t << 0); -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { + { { STATE_EXCSAVE1 }, 'm' } +}; -static unsigned -Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { + { { 6 /* art */ }, 'o' } +}; -static void -Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); - tie_t = (val << 28) >> 29; - insn[1] = (insn[1] & ~0x7) | (tie_t << 0); -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { + { { STATE_EPC2 }, 'i' } +}; -static unsigned -Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { + { { 6 /* art */ }, 'i' } +}; -static void -Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); - tie_t = (val << 28) >> 29; - insn[1] = (insn[1] & ~0x7) | (tie_t << 0); -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { + { { STATE_EPC2 }, 'o' } +}; -static unsigned -Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { + { { 6 /* art */ }, 'm' } +}; -static void -Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); - tie_t = (val << 28) >> 29; - insn[1] = (insn[1] & ~0x7) | (tie_t << 0); -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { + { { STATE_EPC2 }, 'm' } +}; -static unsigned -Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { + { { 6 /* art */ }, 'o' } +}; -static void -Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); - tie_t = (val << 28) >> 29; - insn[1] = (insn[1] & ~0x7) | (tie_t << 0); -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { + { { STATE_EXCSAVE2 }, 'i' } +}; -static unsigned -Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { + { { 6 /* art */ }, 'i' } +}; -static void -Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); - tie_t = (val << 28) >> 29; - insn[1] = (insn[1] & ~0x7) | (tie_t << 0); -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { + { { STATE_EXCSAVE2 }, 'o' } +}; -static unsigned -Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { + { { 6 /* art */ }, 'm' } +}; -static void -Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); - tie_t = (val << 28) >> 29; - insn[1] = (insn[1] & ~0x7) | (tie_t << 0); -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { + { { STATE_EXCSAVE2 }, 'm' } +}; -static unsigned -Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { + { { 6 /* art */ }, 'o' } +}; -static void -Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); - tie_t = (val << 28) >> 29; - insn[1] = (insn[1] & ~0x7) | (tie_t << 0); -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { + { { STATE_EPC3 }, 'i' } +}; -static unsigned -Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { + { { 6 /* art */ }, 'i' } +}; -static void -Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); - tie_t = (val << 28) >> 29; - insn[1] = (insn[1] & ~0x7) | (tie_t << 0); -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { + { { STATE_EPC3 }, 'o' } +}; -static unsigned -Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { + { { 6 /* art */ }, 'm' } +}; -static void -Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); - tie_t = (val << 28) >> 29; - insn[1] = (insn[1] & ~0x7) | (tie_t << 0); -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { + { { STATE_EPC3 }, 'm' } +}; -static unsigned -Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { + { { 6 /* art */ }, 'o' } +}; -static void -Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); - tie_t = (val << 28) >> 29; - insn[1] = (insn[1] & ~0x7) | (tie_t << 0); -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { + { { STATE_EXCSAVE3 }, 'i' } +}; -static unsigned -Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { + { { 6 /* art */ }, 'i' } +}; -static void -Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); - tie_t = (val << 28) >> 29; - insn[1] = (insn[1] & ~0x7) | (tie_t << 0); -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { + { { STATE_EXCSAVE3 }, 'o' } +}; -static unsigned -Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { + { { 6 /* art */ }, 'm' } +}; -static void -Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); - tie_t = (val << 28) >> 29; - insn[1] = (insn[1] & ~0x7) | (tie_t << 0); -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { + { { STATE_EXCSAVE3 }, 'm' } +}; -static unsigned -Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { + { { 6 /* art */ }, 'o' } +}; -static void -Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); - tie_t = (val << 28) >> 29; - insn[1] = (insn[1] & ~0x7) | (tie_t << 0); -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { + { { STATE_EPC4 }, 'i' } +}; -static unsigned -Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { + { { 6 /* art */ }, 'i' } +}; -static void -Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); - tie_t = (val << 28) >> 29; - insn[1] = (insn[1] & ~0x7) | (tie_t << 0); -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { + { { STATE_EPC4 }, 'o' } +}; -static unsigned -Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); - tie_t = (tie_t << 27) | ((insn[0] << 5) >> 5); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { + { { 6 /* art */ }, 'm' } +}; -static void -Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 5) >> 5; - insn[0] = (insn[0] & ~0x7ffffff) | (tie_t << 0); - tie_t = (val << 2) >> 29; - insn[1] = (insn[1] & ~0x7) | (tie_t << 0); -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { + { { STATE_EPC4 }, 'm' } +}; -static unsigned -Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); - return tie_t; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { + { { 6 /* art */ }, 'o' } +}; -static void -Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { + { { STATE_EXCSAVE4 }, 'i' } +}; -static void -Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, - uint32 val ATTRIBUTE_UNUSED) -{ - /* Do nothing. */ -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { + { { 6 /* art */ }, 'i' } +}; -static unsigned -Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { + { { STATE_EXCSAVE4 }, 'o' } +}; -static unsigned -Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 4; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { + { { 6 /* art */ }, 'm' } +}; -static unsigned -Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 8; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { + { { STATE_EXCSAVE4 }, 'm' } +}; -static unsigned -Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 12; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { + { { 6 /* art */ }, 'o' } +}; -static unsigned -Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { + { { STATE_EPC5 }, 'i' } +}; -static unsigned -Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 1; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { + { { 6 /* art */ }, 'i' } +}; -static unsigned -Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 2; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { + { { STATE_EPC5 }, 'o' } +}; -static unsigned -Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 3; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { + { { 6 /* art */ }, 'm' } +}; -static unsigned -Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { + { { STATE_EPC5 }, 'm' } +}; -static unsigned -Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { + { { 6 /* art */ }, 'o' } +}; -static unsigned -Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { + { { STATE_EXCSAVE5 }, 'i' } +}; -static unsigned -Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { + { { 6 /* art */ }, 'i' } +}; - -/* Functional units. */ +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { + { { STATE_EXCSAVE5 }, 'o' } +}; -static xtensa_funcUnit_internal funcUnits[] = { +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { + { { 6 /* art */ }, 'm' } +}; +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { + { { STATE_EXCSAVE5 }, 'm' } }; - -/* Register files. */ +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { + { { 6 /* art */ }, 'o' } +}; -static xtensa_regfile_internal regfiles[] = { - { "AR", "a", 0, 32, 64 }, - { "MR", "m", 1, 32, 4 }, - { "BR", "b", 2, 1, 16 }, - { "FR", "f", 3, 32, 16 }, - { "BR2", "b", 2, 2, 8 }, - { "BR4", "b", 2, 4, 4 }, - { "BR8", "b", 2, 8, 2 }, - { "BR16", "b", 2, 16, 1 } +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { + { { STATE_EPS2 }, 'i' } }; - -/* Interfaces. */ +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { + { { 6 /* art */ }, 'i' } +}; -static xtensa_interface_internal interfaces[] = { +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { + { { STATE_EPS2 }, 'o' } +}; +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { + { { 6 /* art */ }, 'm' } }; - -/* Constant tables. */ +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { + { { STATE_EPS2 }, 'm' } +}; -/* constant table ai4c */ -static const unsigned CONST_TBL_ai4c_0[] = { - 0xffffffff, - 0x1, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0x9, - 0xa, - 0xb, - 0xc, - 0xd, - 0xe, - 0xf, - 0 +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { + { { 6 /* art */ }, 'o' } }; -/* constant table b4c */ -static const unsigned CONST_TBL_b4c_0[] = { - 0xffffffff, - 0x1, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0xa, - 0xc, - 0x10, - 0x20, - 0x40, - 0x80, - 0x100, - 0 +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { + { { STATE_EPS3 }, 'i' } }; -/* constant table b4cu */ -static const unsigned CONST_TBL_b4cu_0[] = { - 0x8000, - 0x10000, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0xa, - 0xc, - 0x10, - 0x20, - 0x40, - 0x80, - 0x100, - 0 +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { + { { 6 /* art */ }, 'i' } }; - -/* Instruction operands. */ - -static int -Operand_soffsetx4_decode (uint32 *valp) -{ - unsigned soffsetx4_0, offset_0; - offset_0 = *valp & 0x3ffff; - soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2); - *valp = soffsetx4_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { + { { STATE_EPS3 }, 'o' } +}; -static int -Operand_soffsetx4_encode (uint32 *valp) -{ - unsigned offset_0, soffsetx4_0; - soffsetx4_0 = *valp; - offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff; - *valp = offset_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { + { { 6 /* art */ }, 'm' } +}; -static int -Operand_soffsetx4_ator (uint32 *valp, uint32 pc) -{ - *valp -= (pc & ~0x3); - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { + { { STATE_EPS3 }, 'm' } +}; -static int -Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) -{ - *valp += (pc & ~0x3); - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { + { { 6 /* art */ }, 'o' } +}; -static int -Operand_uimm12x8_decode (uint32 *valp) -{ - unsigned uimm12x8_0, imm12_0; - imm12_0 = *valp & 0xfff; - uimm12x8_0 = imm12_0 << 3; - *valp = uimm12x8_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { + { { STATE_EPS4 }, 'i' } +}; -static int -Operand_uimm12x8_encode (uint32 *valp) -{ - unsigned imm12_0, uimm12x8_0; - uimm12x8_0 = *valp; - imm12_0 = ((uimm12x8_0 >> 3) & 0xfff); - *valp = imm12_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { + { { 6 /* art */ }, 'i' } +}; -static int -Operand_simm4_decode (uint32 *valp) -{ - unsigned simm4_0, mn_0; - mn_0 = *valp & 0xf; - simm4_0 = ((int) mn_0 << 28) >> 28; - *valp = simm4_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { + { { STATE_EPS4 }, 'o' } +}; -static int -Operand_simm4_encode (uint32 *valp) -{ - unsigned mn_0, simm4_0; - simm4_0 = *valp; - mn_0 = (simm4_0 & 0xf); - *valp = mn_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { + { { 6 /* art */ }, 'm' } +}; -static int -Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { + { { STATE_EPS4 }, 'm' } +}; -static int -Operand_arr_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0xf) != 0; - return error; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { + { { 6 /* art */ }, 'o' } +}; -static int -Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { + { { STATE_EPS5 }, 'i' } +}; -static int -Operand_ars_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0xf) != 0; - return error; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { + { { 6 /* art */ }, 'i' } +}; -static int -Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { + { { STATE_EPS5 }, 'o' } +}; -static int -Operand_art_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0xf) != 0; - return error; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { + { { 6 /* art */ }, 'm' } +}; -static int -Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { + { { STATE_EPS5 }, 'm' } +}; -static int -Operand_ar0_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3f) != 0; - return error; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { + { { 6 /* art */ }, 'o' } +}; -static int -Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { + { { STATE_EXCVADDR }, 'i' } +}; -static int -Operand_ar4_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3f) != 0; - return error; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { + { { 6 /* art */ }, 'i' } +}; -static int -Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { + { { STATE_EXCVADDR }, 'o' } +}; -static int -Operand_ar8_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3f) != 0; - return error; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { + { { 6 /* art */ }, 'm' } +}; -static int -Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { + { { STATE_EXCVADDR }, 'm' } +}; -static int -Operand_ar12_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3f) != 0; - return error; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { + { { 6 /* art */ }, 'o' } +}; -static int -Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { + { { STATE_DEPC }, 'i' } +}; -static int -Operand_ars_entry_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3f) != 0; - return error; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { + { { 6 /* art */ }, 'i' } +}; -static int -Operand_immrx4_decode (uint32 *valp) -{ - unsigned immrx4_0, r_0; - r_0 = *valp & 0xf; - immrx4_0 = (((0xfffffff) << 4) | r_0) << 2; - *valp = immrx4_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { + { { STATE_DEPC }, 'o' } +}; -static int -Operand_immrx4_encode (uint32 *valp) -{ - unsigned r_0, immrx4_0; - immrx4_0 = *valp; - r_0 = ((immrx4_0 >> 2) & 0xf); - *valp = r_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { + { { 6 /* art */ }, 'm' } +}; -static int -Operand_lsi4x4_decode (uint32 *valp) -{ - unsigned lsi4x4_0, r_0; - r_0 = *valp & 0xf; - lsi4x4_0 = r_0 << 2; - *valp = lsi4x4_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { + { { STATE_DEPC }, 'm' } +}; -static int -Operand_lsi4x4_encode (uint32 *valp) -{ - unsigned r_0, lsi4x4_0; - lsi4x4_0 = *valp; - r_0 = ((lsi4x4_0 >> 2) & 0xf); - *valp = r_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { + { { 6 /* art */ }, 'o' } +}; -static int -Operand_simm7_decode (uint32 *valp) -{ - unsigned simm7_0, imm7_0; - imm7_0 = *valp & 0x7f; - simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0; - *valp = simm7_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { + { { STATE_EXCCAUSE }, 'i' }, + { { STATE_XTSYNC }, 'i' } +}; -static int -Operand_simm7_encode (uint32 *valp) -{ - unsigned imm7_0, simm7_0; - simm7_0 = *valp; - imm7_0 = (simm7_0 & 0x7f); - *valp = imm7_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { + { { 6 /* art */ }, 'i' } +}; -static int -Operand_uimm6_decode (uint32 *valp) -{ - unsigned uimm6_0, imm6_0; - imm6_0 = *valp & 0x3f; - uimm6_0 = 0x4 + (((0) << 6) | imm6_0); - *valp = uimm6_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { + { { STATE_EXCCAUSE }, 'o' } +}; -static int -Operand_uimm6_encode (uint32 *valp) -{ - unsigned imm6_0, uimm6_0; - uimm6_0 = *valp; - imm6_0 = (uimm6_0 - 0x4) & 0x3f; - *valp = imm6_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { + { { 6 /* art */ }, 'm' } +}; -static int -Operand_uimm6_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { + { { STATE_EXCCAUSE }, 'm' } +}; -static int -Operand_uimm6_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { + { { 6 /* art */ }, 'o' } +}; -static int -Operand_ai4const_decode (uint32 *valp) -{ - unsigned ai4const_0, t_0; - t_0 = *valp & 0xf; - ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf]; - *valp = ai4const_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { + { { STATE_MISC0 }, 'i' } +}; -static int -Operand_ai4const_encode (uint32 *valp) -{ - unsigned t_0, ai4const_0; - ai4const_0 = *valp; - switch (ai4const_0) - { - case 0xffffffff: t_0 = 0; break; - case 0x1: t_0 = 0x1; break; - case 0x2: t_0 = 0x2; break; - case 0x3: t_0 = 0x3; break; - case 0x4: t_0 = 0x4; break; - case 0x5: t_0 = 0x5; break; - case 0x6: t_0 = 0x6; break; - case 0x7: t_0 = 0x7; break; - case 0x8: t_0 = 0x8; break; - case 0x9: t_0 = 0x9; break; - case 0xa: t_0 = 0xa; break; - case 0xb: t_0 = 0xb; break; - case 0xc: t_0 = 0xc; break; - case 0xd: t_0 = 0xd; break; - case 0xe: t_0 = 0xe; break; - default: t_0 = 0xf; break; - } - *valp = t_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { + { { 6 /* art */ }, 'i' } +}; -static int -Operand_b4const_decode (uint32 *valp) -{ - unsigned b4const_0, r_0; - r_0 = *valp & 0xf; - b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf]; - *valp = b4const_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { + { { STATE_MISC0 }, 'o' } +}; -static int -Operand_b4const_encode (uint32 *valp) -{ - unsigned r_0, b4const_0; - b4const_0 = *valp; - switch (b4const_0) - { - case 0xffffffff: r_0 = 0; break; - case 0x1: r_0 = 0x1; break; - case 0x2: r_0 = 0x2; break; - case 0x3: r_0 = 0x3; break; - case 0x4: r_0 = 0x4; break; - case 0x5: r_0 = 0x5; break; - case 0x6: r_0 = 0x6; break; - case 0x7: r_0 = 0x7; break; - case 0x8: r_0 = 0x8; break; - case 0xa: r_0 = 0x9; break; - case 0xc: r_0 = 0xa; break; - case 0x10: r_0 = 0xb; break; - case 0x20: r_0 = 0xc; break; - case 0x40: r_0 = 0xd; break; - case 0x80: r_0 = 0xe; break; - default: r_0 = 0xf; break; - } - *valp = r_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { + { { 6 /* art */ }, 'm' } +}; -static int -Operand_b4constu_decode (uint32 *valp) -{ - unsigned b4constu_0, r_0; - r_0 = *valp & 0xf; - b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf]; - *valp = b4constu_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { + { { STATE_MISC0 }, 'm' } +}; -static int -Operand_b4constu_encode (uint32 *valp) -{ - unsigned r_0, b4constu_0; - b4constu_0 = *valp; - switch (b4constu_0) - { - case 0x8000: r_0 = 0; break; - case 0x10000: r_0 = 0x1; break; - case 0x2: r_0 = 0x2; break; - case 0x3: r_0 = 0x3; break; - case 0x4: r_0 = 0x4; break; - case 0x5: r_0 = 0x5; break; - case 0x6: r_0 = 0x6; break; - case 0x7: r_0 = 0x7; break; - case 0x8: r_0 = 0x8; break; - case 0xa: r_0 = 0x9; break; - case 0xc: r_0 = 0xa; break; - case 0x10: r_0 = 0xb; break; - case 0x20: r_0 = 0xc; break; - case 0x40: r_0 = 0xd; break; - case 0x80: r_0 = 0xe; break; - default: r_0 = 0xf; break; - } - *valp = r_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { + { { 6 /* art */ }, 'o' } +}; -static int -Operand_uimm8_decode (uint32 *valp) -{ - unsigned uimm8_0, imm8_0; - imm8_0 = *valp & 0xff; - uimm8_0 = imm8_0; - *valp = uimm8_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { + { { STATE_MISC1 }, 'i' } +}; -static int -Operand_uimm8_encode (uint32 *valp) -{ - unsigned imm8_0, uimm8_0; - uimm8_0 = *valp; - imm8_0 = (uimm8_0 & 0xff); - *valp = imm8_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { + { { 6 /* art */ }, 'i' } +}; -static int -Operand_uimm8x2_decode (uint32 *valp) -{ - unsigned uimm8x2_0, imm8_0; - imm8_0 = *valp & 0xff; - uimm8x2_0 = imm8_0 << 1; - *valp = uimm8x2_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { + { { STATE_MISC1 }, 'o' } +}; -static int -Operand_uimm8x2_encode (uint32 *valp) -{ - unsigned imm8_0, uimm8x2_0; - uimm8x2_0 = *valp; - imm8_0 = ((uimm8x2_0 >> 1) & 0xff); - *valp = imm8_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { + { { 6 /* art */ }, 'm' } +}; -static int -Operand_uimm8x4_decode (uint32 *valp) -{ - unsigned uimm8x4_0, imm8_0; - imm8_0 = *valp & 0xff; - uimm8x4_0 = imm8_0 << 2; - *valp = uimm8x4_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { + { { STATE_MISC1 }, 'm' } +}; -static int -Operand_uimm8x4_encode (uint32 *valp) -{ - unsigned imm8_0, uimm8x4_0; - uimm8x4_0 = *valp; - imm8_0 = ((uimm8x4_0 >> 2) & 0xff); - *valp = imm8_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { + { { 6 /* art */ }, 'o' } +}; -static int -Operand_uimm4x16_decode (uint32 *valp) -{ - unsigned uimm4x16_0, op2_0; - op2_0 = *valp & 0xf; - uimm4x16_0 = op2_0 << 4; - *valp = uimm4x16_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { + { { 6 /* art */ }, 'o' } +}; -static int -Operand_uimm4x16_encode (uint32 *valp) -{ - unsigned op2_0, uimm4x16_0; - uimm4x16_0 = *valp; - op2_0 = ((uimm4x16_0 >> 4) & 0xf); - *valp = op2_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { + { { STATE_VECBASE }, 'i' } +}; -static int -Operand_simm8_decode (uint32 *valp) -{ - unsigned simm8_0, imm8_0; - imm8_0 = *valp & 0xff; - simm8_0 = ((int) imm8_0 << 24) >> 24; - *valp = simm8_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { + { { 6 /* art */ }, 'i' } +}; -static int -Operand_simm8_encode (uint32 *valp) -{ - unsigned imm8_0, simm8_0; - simm8_0 = *valp; - imm8_0 = (simm8_0 & 0xff); - *valp = imm8_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { + { { STATE_VECBASE }, 'o' } +}; -static int -Operand_simm8x256_decode (uint32 *valp) -{ - unsigned simm8x256_0, imm8_0; - imm8_0 = *valp & 0xff; - simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8; - *valp = simm8x256_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { + { { 6 /* art */ }, 'm' } +}; -static int -Operand_simm8x256_encode (uint32 *valp) -{ - unsigned imm8_0, simm8x256_0; - simm8x256_0 = *valp; - imm8_0 = ((simm8x256_0 >> 8) & 0xff); - *valp = imm8_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { + { { STATE_VECBASE }, 'm' } +}; -static int -Operand_simm12b_decode (uint32 *valp) -{ - unsigned simm12b_0, imm12b_0; - imm12b_0 = *valp & 0xfff; - simm12b_0 = ((int) imm12b_0 << 20) >> 20; - *valp = simm12b_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { + { { 43 /* s */ }, 'i' } +}; -static int -Operand_simm12b_encode (uint32 *valp) -{ - unsigned imm12b_0, simm12b_0; - simm12b_0 = *valp; - imm12b_0 = (simm12b_0 & 0xfff); - *valp = imm12b_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPC1 }, 'i' }, + { { STATE_EPC2 }, 'i' }, + { { STATE_EPC3 }, 'i' }, + { { STATE_EPC4 }, 'i' }, + { { STATE_EPC5 }, 'i' }, + { { STATE_EPS2 }, 'i' }, + { { STATE_EPS3 }, 'i' }, + { { STATE_EPS4 }, 'i' }, + { { STATE_EPS5 }, 'i' }, + { { STATE_InOCDMode }, 'm' } +}; -static int -Operand_msalp32_decode (uint32 *valp) -{ - unsigned msalp32_0, sal_0; - sal_0 = *valp & 0x1f; - msalp32_0 = 0x20 - sal_0; - *valp = msalp32_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { + { { 43 /* s */ }, 'i' } +}; -static int -Operand_msalp32_encode (uint32 *valp) -{ - unsigned sal_0, msalp32_0; - msalp32_0 = *valp; - sal_0 = (0x20 - msalp32_0) & 0x1f; - *valp = sal_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { + { { STATE_PSINTLEVEL }, 'o' } +}; -static int -Operand_op2p1_decode (uint32 *valp) -{ - unsigned op2p1_0, op2_0; - op2_0 = *valp & 0xf; - op2p1_0 = op2_0 + 0x1; - *valp = op2p1_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { + { { 6 /* art */ }, 'o' } +}; -static int -Operand_op2p1_encode (uint32 *valp) -{ - unsigned op2_0, op2p1_0; - op2p1_0 = *valp; - op2_0 = (op2p1_0 - 0x1) & 0xf; - *valp = op2_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { + { { STATE_INTERRUPT }, 'i' } +}; -static int -Operand_label8_decode (uint32 *valp) -{ - unsigned label8_0, imm8_0; - imm8_0 = *valp & 0xff; - label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24); - *valp = label8_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { + { { 6 /* art */ }, 'i' } +}; -static int -Operand_label8_encode (uint32 *valp) -{ - unsigned imm8_0, label8_0; - label8_0 = *valp; - imm8_0 = (label8_0 - 0x4) & 0xff; - *valp = imm8_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; -static int -Operand_label8_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { + { { 6 /* art */ }, 'i' } +}; -static int -Operand_label8_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_ulabel8_decode (uint32 *valp) -{ - unsigned ulabel8_0, imm8_0; - imm8_0 = *valp & 0xff; - ulabel8_0 = 0x4 + (((0) << 8) | imm8_0); - *valp = ulabel8_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; -static int -Operand_ulabel8_encode (uint32 *valp) -{ - unsigned imm8_0, ulabel8_0; - ulabel8_0 = *valp; - imm8_0 = (ulabel8_0 - 0x4) & 0xff; - *valp = imm8_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { + { { 6 /* art */ }, 'o' } +}; -static int -Operand_ulabel8_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { + { { STATE_INTENABLE }, 'i' } +}; -static int -Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { + { { 6 /* art */ }, 'i' } +}; -static int -Operand_label12_decode (uint32 *valp) -{ - unsigned label12_0, imm12_0; - imm12_0 = *valp & 0xfff; - label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20); - *valp = label12_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { + { { STATE_INTENABLE }, 'o' } +}; -static int -Operand_label12_encode (uint32 *valp) -{ - unsigned imm12_0, label12_0; - label12_0 = *valp; - imm12_0 = (label12_0 - 0x4) & 0xfff; - *valp = imm12_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { + { { 6 /* art */ }, 'm' } +}; -static int -Operand_label12_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { + { { STATE_INTENABLE }, 'm' } +}; -static int -Operand_label12_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { + { { 34 /* imms */ }, 'i' }, + { { 33 /* immt */ }, 'i' } +}; -static int -Operand_soffset_decode (uint32 *valp) -{ - unsigned soffset_0, offset_0; - offset_0 = *valp & 0x3ffff; - soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14); - *valp = soffset_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; -static int -Operand_soffset_encode (uint32 *valp) -{ - unsigned offset_0, soffset_0; - soffset_0 = *valp; - offset_0 = (soffset_0 - 0x4) & 0x3ffff; - *valp = offset_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { + { { 34 /* imms */ }, 'i' } +}; -static int -Operand_soffset_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; -static int -Operand_soffset_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { + { { 6 /* art */ }, 'o' } +}; -static int -Operand_uimm16x4_decode (uint32 *valp) -{ - unsigned uimm16x4_0, imm16_0; - imm16_0 = *valp & 0xffff; - uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2; - *valp = uimm16x4_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { + { { STATE_DBREAKA0 }, 'i' } +}; -static int -Operand_uimm16x4_encode (uint32 *valp) -{ - unsigned imm16_0, uimm16x4_0; - uimm16x4_0 = *valp; - imm16_0 = (uimm16x4_0 >> 2) & 0xffff; - *valp = imm16_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { + { { 6 /* art */ }, 'i' } +}; -static int -Operand_uimm16x4_ator (uint32 *valp, uint32 pc) -{ - *valp -= ((pc + 3) & ~0x3); - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { + { { STATE_DBREAKA0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; -static int -Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) -{ - *valp += ((pc + 3) & ~0x3); - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { + { { 6 /* art */ }, 'm' } +}; -static int -Operand_mx_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { + { { STATE_DBREAKA0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; -static int -Operand_mx_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3) != 0; - return error; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { + { { 6 /* art */ }, 'o' } +}; -static int -Operand_my_decode (uint32 *valp) -{ - *valp += 2; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { + { { STATE_DBREAKC0 }, 'i' } +}; -static int -Operand_my_encode (uint32 *valp) -{ - int error; - error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0); - *valp = *valp & 1; - return error; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { + { { 6 /* art */ }, 'i' } +}; -static int -Operand_mw_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { + { { STATE_DBREAKC0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; -static int -Operand_mw_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3) != 0; - return error; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { + { { 6 /* art */ }, 'm' } +}; -static int -Operand_mr0_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { + { { STATE_DBREAKC0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; -static int -Operand_mr0_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3) != 0; - return error; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { + { { 6 /* art */ }, 'o' } +}; -static int -Operand_mr1_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { + { { STATE_DBREAKA1 }, 'i' } +}; -static int -Operand_mr1_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3) != 0; - return error; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { + { { 6 /* art */ }, 'i' } +}; -static int -Operand_mr2_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_mr2_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3) != 0; - return error; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { + { { STATE_DBREAKA1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; -static int -Operand_mr3_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { + { { 6 /* art */ }, 'm' } +}; -static int -Operand_mr3_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3) != 0; - return error; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { + { { STATE_DBREAKA1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; -static int -Operand_immt_decode (uint32 *valp) -{ - unsigned immt_0, t_0; - t_0 = *valp & 0xf; - immt_0 = t_0; - *valp = immt_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { + { { 6 /* art */ }, 'o' } +}; -static int -Operand_immt_encode (uint32 *valp) -{ - unsigned t_0, immt_0; - immt_0 = *valp; - t_0 = immt_0 & 0xf; - *valp = t_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { + { { STATE_DBREAKC1 }, 'i' } +}; -static int -Operand_imms_decode (uint32 *valp) -{ - unsigned imms_0, s_0; - s_0 = *valp & 0xf; - imms_0 = s_0; - *valp = imms_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { + { { 6 /* art */ }, 'i' } +}; -static int -Operand_imms_encode (uint32 *valp) -{ - unsigned s_0, imms_0; - imms_0 = *valp; - s_0 = imms_0 & 0xf; - *valp = s_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { + { { STATE_DBREAKC1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; -static int -Operand_bt_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { + { { 6 /* art */ }, 'm' } +}; -static int -Operand_bt_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0xf) != 0; - return error; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { + { { STATE_DBREAKC1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; -static int -Operand_bs_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { + { { 6 /* art */ }, 'o' } +}; -static int -Operand_bs_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0xf) != 0; - return error; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { + { { STATE_IBREAKA0 }, 'i' } +}; -static int -Operand_br_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { + { { 6 /* art */ }, 'i' } +}; -static int -Operand_br_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0xf) != 0; - return error; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { + { { STATE_IBREAKA0 }, 'o' } +}; -static int -Operand_bt2_decode (uint32 *valp) -{ - *valp = *valp << 1; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { + { { 6 /* art */ }, 'm' } +}; -static int -Operand_bt2_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0x7 << 1)) != 0; - *valp = *valp >> 1; - return error; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { + { { STATE_IBREAKA0 }, 'm' } +}; -static int -Operand_bs2_decode (uint32 *valp) -{ - *valp = *valp << 1; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { + { { 6 /* art */ }, 'o' } +}; -static int -Operand_bs2_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0x7 << 1)) != 0; - *valp = *valp >> 1; - return error; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { + { { STATE_IBREAKA1 }, 'i' } +}; -static int -Operand_br2_decode (uint32 *valp) -{ - *valp = *valp << 1; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { + { { 6 /* art */ }, 'i' } +}; -static int -Operand_br2_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0x7 << 1)) != 0; - *valp = *valp >> 1; - return error; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { + { { STATE_IBREAKA1 }, 'o' } +}; -static int -Operand_bt4_decode (uint32 *valp) -{ - *valp = *valp << 2; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { + { { 6 /* art */ }, 'm' } +}; -static int -Operand_bt4_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0x3 << 2)) != 0; - *valp = *valp >> 2; - return error; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { + { { STATE_IBREAKA1 }, 'm' } +}; -static int -Operand_bs4_decode (uint32 *valp) -{ - *valp = *valp << 2; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { + { { 6 /* art */ }, 'o' } +}; -static int -Operand_bs4_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0x3 << 2)) != 0; - *valp = *valp >> 2; - return error; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { + { { STATE_IBREAKENABLE }, 'i' } +}; -static int -Operand_br4_decode (uint32 *valp) -{ - *valp = *valp << 2; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { + { { 6 /* art */ }, 'i' } +}; -static int -Operand_br4_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0x3 << 2)) != 0; - *valp = *valp >> 2; - return error; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { + { { STATE_IBREAKENABLE }, 'o' } +}; -static int -Operand_bt8_decode (uint32 *valp) -{ - *valp = *valp << 3; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { + { { 6 /* art */ }, 'm' } +}; -static int -Operand_bt8_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0x1 << 3)) != 0; - *valp = *valp >> 3; - return error; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { + { { STATE_IBREAKENABLE }, 'm' } +}; -static int -Operand_bs8_decode (uint32 *valp) -{ - *valp = *valp << 3; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { + { { 6 /* art */ }, 'o' } +}; -static int -Operand_bs8_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0x1 << 3)) != 0; - *valp = *valp >> 3; - return error; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { + { { STATE_DEBUGCAUSE }, 'i' }, + { { STATE_DBNUM }, 'i' } +}; -static int -Operand_br8_decode (uint32 *valp) -{ - *valp = *valp << 3; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { + { { 6 /* art */ }, 'i' } +}; -static int -Operand_br8_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0x1 << 3)) != 0; - *valp = *valp >> 3; - return error; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { + { { STATE_DEBUGCAUSE }, 'o' }, + { { STATE_DBNUM }, 'o' } +}; -static int -Operand_bt16_decode (uint32 *valp) -{ - *valp = *valp << 4; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { + { { 6 /* art */ }, 'm' } +}; -static int -Operand_bt16_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0 << 4)) != 0; - *valp = *valp >> 4; - return error; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { + { { STATE_DEBUGCAUSE }, 'm' }, + { { STATE_DBNUM }, 'm' } +}; -static int -Operand_bs16_decode (uint32 *valp) -{ - *valp = *valp << 4; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { + { { 6 /* art */ }, 'o' } +}; -static int -Operand_bs16_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0 << 4)) != 0; - *valp = *valp >> 4; - return error; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { + { { STATE_ICOUNT }, 'i' } +}; -static int -Operand_br16_decode (uint32 *valp) -{ - *valp = *valp << 4; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { + { { 6 /* art */ }, 'i' } +}; -static int -Operand_br16_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0 << 4)) != 0; - *valp = *valp >> 4; - return error; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'o' } +}; -static int -Operand_brall_decode (uint32 *valp) -{ - *valp = *valp << 4; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { + { { 6 /* art */ }, 'm' } +}; -static int -Operand_brall_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0 << 4)) != 0; - *valp = *valp >> 4; - return error; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'm' } +}; -static int -Operand_tp7_decode (uint32 *valp) -{ - unsigned tp7_0, t_0; - t_0 = *valp & 0xf; - tp7_0 = t_0 + 0x7; - *valp = tp7_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { + { { 6 /* art */ }, 'o' } +}; -static int -Operand_tp7_encode (uint32 *valp) -{ - unsigned t_0, tp7_0; - tp7_0 = *valp; - t_0 = (tp7_0 - 0x7) & 0xf; - *valp = t_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { + { { STATE_ICOUNTLEVEL }, 'i' } +}; -static int -Operand_xt_wbr15_label_decode (uint32 *valp) -{ - unsigned xt_wbr15_label_0, xt_wbr15_imm_0; - xt_wbr15_imm_0 = *valp & 0x7fff; - xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17); - *valp = xt_wbr15_label_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { + { { 6 /* art */ }, 'i' } +}; -static int -Operand_xt_wbr15_label_encode (uint32 *valp) -{ - unsigned xt_wbr15_imm_0, xt_wbr15_label_0; - xt_wbr15_label_0 = *valp; - xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff; - *valp = xt_wbr15_imm_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { + { { STATE_ICOUNTLEVEL }, 'o' } +}; -static int -Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { + { { 6 /* art */ }, 'm' } +}; -static int -Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { + { { STATE_ICOUNTLEVEL }, 'm' } +}; -static int -Operand_xt_wbr18_label_decode (uint32 *valp) -{ - unsigned xt_wbr18_label_0, xt_wbr18_imm_0; - xt_wbr18_imm_0 = *valp & 0x3ffff; - xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14); - *valp = xt_wbr18_label_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { + { { 6 /* art */ }, 'o' } +}; -static int -Operand_xt_wbr18_label_encode (uint32 *valp) -{ - unsigned xt_wbr18_imm_0, xt_wbr18_label_0; - xt_wbr18_label_0 = *valp; - xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff; - *valp = xt_wbr18_imm_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { + { { STATE_DDR }, 'i' } +}; -static int -Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { + { { 6 /* art */ }, 'i' } +}; -static int -Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'o' } +}; -static int -Operand_cimm8x4_decode (uint32 *valp) -{ - unsigned cimm8x4_0, imm8_0; - imm8_0 = *valp & 0xff; - cimm8x4_0 = (imm8_0 << 2) | 0; - *valp = cimm8x4_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { + { { 6 /* art */ }, 'm' } +}; -static int -Operand_cimm8x4_encode (uint32 *valp) -{ - unsigned imm8_0, cimm8x4_0; - cimm8x4_0 = *valp; - imm8_0 = (cimm8x4_0 >> 2) & 0xff; - *valp = imm8_0; - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'm' } +}; -static int -Operand_frr_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { + { { 34 /* imms */ }, 'i' } +}; -static int -Operand_frr_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0xf) != 0; - return error; -} +static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { + { { STATE_InOCDMode }, 'm' }, + { { STATE_EPC4 }, 'i' }, + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPS4 }, 'i' } +}; -static int -Operand_frs_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { + { { STATE_InOCDMode }, 'm' } +}; -static int -Operand_frs_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0xf) != 0; - return error; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { + { { 6 /* art */ }, 'i' } +}; -static int -Operand_frt_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { + { { STATE_XTSYNC }, 'o' } +}; -static int -Operand_frt_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0xf) != 0; - return error; -} +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { + { { 6 /* art */ }, 'o' } +}; -static xtensa_operand_internal operands[] = { - { "soffsetx4", 10, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_soffsetx4_encode, Operand_soffsetx4_decode, - Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, - { "uimm12x8", 3, -1, 0, - 0, - Operand_uimm12x8_encode, Operand_uimm12x8_decode, - 0, 0 }, - { "simm4", 26, -1, 0, - 0, - Operand_simm4_encode, Operand_simm4_decode, - 0, 0 }, - { "arr", 14, 0, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_arr_encode, Operand_arr_decode, - 0, 0 }, - { "ars", 5, 0, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_ars_encode, Operand_ars_decode, - 0, 0 }, - { "*ars_invisible", 5, 0, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ars_encode, Operand_ars_decode, - 0, 0 }, - { "art", 0, 0, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_art_encode, Operand_art_decode, - 0, 0 }, - { "ar0", 123, 0, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ar0_encode, Operand_ar0_decode, - 0, 0 }, - { "ar4", 124, 0, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ar4_encode, Operand_ar4_decode, - 0, 0 }, - { "ar8", 125, 0, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ar8_encode, Operand_ar8_decode, - 0, 0 }, - { "ar12", 126, 0, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ar12_encode, Operand_ar12_decode, - 0, 0 }, - { "ars_entry", 5, 0, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_ars_entry_encode, Operand_ars_entry_decode, - 0, 0 }, - { "immrx4", 14, -1, 0, - 0, - Operand_immrx4_encode, Operand_immrx4_decode, - 0, 0 }, - { "lsi4x4", 14, -1, 0, - 0, - Operand_lsi4x4_encode, Operand_lsi4x4_decode, - 0, 0 }, - { "simm7", 34, -1, 0, - 0, - Operand_simm7_encode, Operand_simm7_decode, - 0, 0 }, - { "uimm6", 33, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_uimm6_encode, Operand_uimm6_decode, - Operand_uimm6_ator, Operand_uimm6_rtoa }, - { "ai4const", 0, -1, 0, - 0, - Operand_ai4const_encode, Operand_ai4const_decode, - 0, 0 }, - { "b4const", 14, -1, 0, - 0, - Operand_b4const_encode, Operand_b4const_decode, - 0, 0 }, - { "b4constu", 14, -1, 0, - 0, - Operand_b4constu_encode, Operand_b4constu_decode, - 0, 0 }, - { "uimm8", 4, -1, 0, - 0, - Operand_uimm8_encode, Operand_uimm8_decode, - 0, 0 }, - { "uimm8x2", 4, -1, 0, - 0, - Operand_uimm8x2_encode, Operand_uimm8x2_decode, - 0, 0 }, - { "uimm8x4", 4, -1, 0, - 0, - Operand_uimm8x4_encode, Operand_uimm8x4_decode, - 0, 0 }, - { "uimm4x16", 13, -1, 0, - 0, - Operand_uimm4x16_encode, Operand_uimm4x16_decode, - 0, 0 }, - { "simm8", 4, -1, 0, - 0, - Operand_simm8_encode, Operand_simm8_decode, - 0, 0 }, - { "simm8x256", 4, -1, 0, - 0, - Operand_simm8x256_encode, Operand_simm8x256_decode, - 0, 0 }, - { "simm12b", 6, -1, 0, - 0, - Operand_simm12b_encode, Operand_simm12b_decode, - 0, 0 }, - { "msalp32", 18, -1, 0, - 0, - Operand_msalp32_encode, Operand_msalp32_decode, - 0, 0 }, - { "op2p1", 13, -1, 0, - 0, - Operand_op2p1_encode, Operand_op2p1_decode, - 0, 0 }, - { "label8", 4, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_label8_encode, Operand_label8_decode, - Operand_label8_ator, Operand_label8_rtoa }, - { "ulabel8", 4, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_ulabel8_encode, Operand_ulabel8_decode, - Operand_ulabel8_ator, Operand_ulabel8_rtoa }, - { "label12", 3, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_label12_encode, Operand_label12_decode, - Operand_label12_ator, Operand_label12_rtoa }, - { "soffset", 10, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_soffset_encode, Operand_soffset_decode, - Operand_soffset_ator, Operand_soffset_rtoa }, - { "uimm16x4", 7, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_uimm16x4_encode, Operand_uimm16x4_decode, - Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, - { "mx", 43, 1, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, - Operand_mx_encode, Operand_mx_decode, - 0, 0 }, - { "my", 42, 1, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, - Operand_my_encode, Operand_my_decode, - 0, 0 }, - { "mw", 41, 1, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_mw_encode, Operand_mw_decode, - 0, 0 }, - { "mr0", 127, 1, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_mr0_encode, Operand_mr0_decode, - 0, 0 }, - { "mr1", 128, 1, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_mr1_encode, Operand_mr1_decode, - 0, 0 }, - { "mr2", 129, 1, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_mr2_encode, Operand_mr2_decode, - 0, 0 }, - { "mr3", 130, 1, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_mr3_encode, Operand_mr3_decode, - 0, 0 }, - { "immt", 0, -1, 0, - 0, - Operand_immt_encode, Operand_immt_decode, - 0, 0 }, - { "imms", 5, -1, 0, - 0, - Operand_imms_encode, Operand_imms_decode, - 0, 0 }, - { "bt", 0, 2, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_bt_encode, Operand_bt_decode, - 0, 0 }, - { "bs", 5, 2, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_bs_encode, Operand_bs_decode, - 0, 0 }, - { "br", 14, 2, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_br_encode, Operand_br_decode, - 0, 0 }, - { "bt2", 44, 2, 2, - XTENSA_OPERAND_IS_REGISTER, - Operand_bt2_encode, Operand_bt2_decode, - 0, 0 }, - { "bs2", 45, 2, 2, - XTENSA_OPERAND_IS_REGISTER, - Operand_bs2_encode, Operand_bs2_decode, - 0, 0 }, - { "br2", 46, 2, 2, - XTENSA_OPERAND_IS_REGISTER, - Operand_br2_encode, Operand_br2_decode, - 0, 0 }, - { "bt4", 47, 2, 4, - XTENSA_OPERAND_IS_REGISTER, - Operand_bt4_encode, Operand_bt4_decode, - 0, 0 }, - { "bs4", 48, 2, 4, - XTENSA_OPERAND_IS_REGISTER, - Operand_bs4_encode, Operand_bs4_decode, - 0, 0 }, - { "br4", 49, 2, 4, - XTENSA_OPERAND_IS_REGISTER, - Operand_br4_encode, Operand_br4_decode, - 0, 0 }, - { "bt8", 50, 2, 8, - XTENSA_OPERAND_IS_REGISTER, - Operand_bt8_encode, Operand_bt8_decode, - 0, 0 }, - { "bs8", 51, 2, 8, - XTENSA_OPERAND_IS_REGISTER, - Operand_bs8_encode, Operand_bs8_decode, - 0, 0 }, - { "br8", 52, 2, 8, - XTENSA_OPERAND_IS_REGISTER, - Operand_br8_encode, Operand_br8_decode, - 0, 0 }, - { "bt16", 131, 2, 16, - XTENSA_OPERAND_IS_REGISTER, - Operand_bt16_encode, Operand_bt16_decode, - 0, 0 }, - { "bs16", 132, 2, 16, - XTENSA_OPERAND_IS_REGISTER, - Operand_bs16_encode, Operand_bs16_decode, - 0, 0 }, - { "br16", 133, 2, 16, - XTENSA_OPERAND_IS_REGISTER, - Operand_br16_encode, Operand_br16_decode, - 0, 0 }, - { "brall", 134, 2, 16, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_brall_encode, Operand_brall_decode, - 0, 0 }, - { "tp7", 0, -1, 0, - 0, - Operand_tp7_encode, Operand_tp7_decode, - 0, 0 }, - { "xt_wbr15_label", 53, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode, - Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, - { "xt_wbr18_label", 54, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode, - Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, - { "cimm8x4", 4, -1, 0, - 0, - Operand_cimm8x4_encode, Operand_cimm8x4_decode, - 0, 0 }, - { "frr", 14, 3, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_frr_encode, Operand_frr_decode, - 0, 0 }, - { "frs", 5, 3, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_frs_encode, Operand_frs_decode, - 0, 0 }, - { "frt", 0, 3, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_frt_encode, Operand_frt_decode, - 0, 0 }, - { "t", 0, -1, 0, 0, 0, 0, 0, 0 }, - { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 }, - { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 }, - { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 }, - { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 }, - { "s", 5, -1, 0, 0, 0, 0, 0, 0 }, - { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 }, - { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 }, - { "m", 8, -1, 0, 0, 0, 0, 0, 0 }, - { "n", 9, -1, 0, 0, 0, 0, 0, 0 }, - { "offset", 10, -1, 0, 0, 0, 0, 0, 0 }, - { "op0", 11, -1, 0, 0, 0, 0, 0, 0 }, - { "op1", 12, -1, 0, 0, 0, 0, 0, 0 }, - { "op2", 13, -1, 0, 0, 0, 0, 0, 0 }, - { "r", 14, -1, 0, 0, 0, 0, 0, 0 }, - { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 }, - { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 }, - { "sae", 17, -1, 0, 0, 0, 0, 0, 0 }, - { "sal", 18, -1, 0, 0, 0, 0, 0, 0 }, - { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 }, - { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 }, - { "sas", 21, -1, 0, 0, 0, 0, 0, 0 }, - { "sr", 22, -1, 0, 0, 0, 0, 0, 0 }, - { "st", 23, -1, 0, 0, 0, 0, 0, 0 }, - { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 }, - { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 }, - { "mn", 26, -1, 0, 0, 0, 0, 0, 0 }, - { "i", 27, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 }, - { "z", 32, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 }, - { "r3", 35, -1, 0, 0, 0, 0, 0, 0 }, - { "rbit2", 36, -1, 0, 0, 0, 0, 0, 0 }, - { "rhi", 37, -1, 0, 0, 0, 0, 0, 0 }, - { "t3", 38, -1, 0, 0, 0, 0, 0, 0 }, - { "tbit2", 39, -1, 0, 0, 0, 0, 0, 0 }, - { "tlo", 40, -1, 0, 0, 0, 0, 0, 0 }, - { "w", 41, -1, 0, 0, 0, 0, 0, 0 }, - { "y", 42, -1, 0, 0, 0, 0, 0, 0 }, - { "x", 43, -1, 0, 0, 0, 0, 0, 0 }, - { "t2", 44, -1, 0, 0, 0, 0, 0, 0 }, - { "s2", 45, -1, 0, 0, 0, 0, 0, 0 }, - { "r2", 46, -1, 0, 0, 0, 0, 0, 0 }, - { "t4", 47, -1, 0, 0, 0, 0, 0, 0 }, - { "s4", 48, -1, 0, 0, 0, 0, 0, 0 }, - { "r4", 49, -1, 0, 0, 0, 0, 0, 0 }, - { "t8", 50, -1, 0, 0, 0, 0, 0, 0 }, - { "s8", 51, -1, 0, 0, 0, 0, 0, 0 }, - { "r8", 52, -1, 0, 0, 0, 0, 0, 0 }, - { "xt_wbr15_imm", 53, -1, 0, 0, 0, 0, 0, 0 }, - { "xt_wbr18_imm", 54, -1, 0, 0, 0, 0, 0, 0 }, - { "op0_xt_flix64_slot0_s3", 55, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld7", 56, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld8", 57, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld9", 58, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld11", 59, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld49xt_flix64_slot0", 60, -1, 0, 0, 0, 0, 0, 0 }, - { "op0_s4", 61, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld16", 62, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld19xt_flix64_slot1", 63, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld20xt_flix64_slot1", 64, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld21xt_flix64_slot1", 65, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld22xt_flix64_slot1", 66, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld23xt_flix64_slot1", 67, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld25xt_flix64_slot1", 68, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld26xt_flix64_slot1", 69, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld28xt_flix64_slot1", 70, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld30xt_flix64_slot1", 71, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld32xt_flix64_slot1", 72, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld33xt_flix64_slot1", 73, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld35xt_flix64_slot1", 74, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld51xt_flix64_slot1", 75, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld52xt_flix64_slot1", 76, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld53xt_flix64_slot1", 77, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld54xt_flix64_slot1", 78, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld57xt_flix64_slot1", 79, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld58xt_flix64_slot1", 80, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld60xt_flix64_slot1", 81, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld62xt_flix64_slot1", 82, -1, 0, 0, 0, 0, 0, 0 }, - { "op0_s5", 83, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld36xt_flix64_slot2", 84, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld37xt_flix64_slot2", 85, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld39xt_flix64_slot2", 86, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld41xt_flix64_slot2", 87, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld42xt_flix64_slot2", 88, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld44xt_flix64_slot2", 89, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld45xt_flix64_slot2", 90, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld47xt_flix64_slot2", 91, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld63xt_flix64_slot2", 92, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld64xt_flix64_slot2", 93, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld65xt_flix64_slot2", 94, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld66xt_flix64_slot2", 95, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld68xt_flix64_slot2", 96, -1, 0, 0, 0, 0, 0, 0 }, - { "op0_s6", 97, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld70xt_flix64_slot3", 98, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld71", 99, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld72xt_flix64_slot3", 100, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld73xt_flix64_slot3", 101, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld74xt_flix64_slot3", 102, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld75xt_flix64_slot3", 103, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld76xt_flix64_slot3", 104, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld77xt_flix64_slot3", 105, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld78xt_flix64_slot3", 106, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld79xt_flix64_slot3", 107, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld80xt_flix64_slot3", 108, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld81xt_flix64_slot3", 109, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld82xt_flix64_slot3", 110, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld83xt_flix64_slot3", 111, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld84xt_flix64_slot3", 112, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld85xt_flix64_slot3", 113, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld86xt_flix64_slot3", 114, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld87xt_flix64_slot3", 115, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld88xt_flix64_slot3", 116, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld89xt_flix64_slot3", 117, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld90xt_flix64_slot3", 118, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld91xt_flix64_slot3", 119, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld92xt_flix64_slot3", 120, -1, 0, 0, 0, 0, 0, 0 }, - { "combined3e2c5767_fld93xt_flix64_slot3", 121, -1, 0, 0, 0, 0, 0, 0 }, - { "op0_xt_flix64_slot0", 122, -1, 0, 0, 0, 0, 0, 0 } +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { + { { STATE_CCOUNT }, 'i' } }; - -/* Iclass table. */ - -static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { - { { STATE_PSRING }, 'i' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_EPC1 }, 'i' } +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { + { { 6 /* art */ }, 'i' } }; -static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEPC }, 'i' } +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'o' } }; -static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { - { { 0 /* soffsetx4 */ }, 'i' }, - { { 10 /* ar12 */ }, 'o' } +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { + { { 6 /* art */ }, 'm' } }; -static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'm' } }; -static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { - { { 0 /* soffsetx4 */ }, 'i' }, - { { 9 /* ar8 */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { - { { 0 /* soffsetx4 */ }, 'i' }, - { { 8 /* ar4 */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 10 /* ar12 */ }, 'o' } +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { + { { 6 /* art */ }, 'o' } }; -static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { + { { STATE_CCOMPARE0 }, 'i' } }; -static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 9 /* ar8 */ }, 'o' } +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { + { { 6 /* art */ }, 'i' } }; -static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { + { { STATE_CCOMPARE0 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } }; -static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 8 /* ar4 */ }, 'o' } +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { + { { 6 /* art */ }, 'm' } }; -static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { + { { STATE_CCOMPARE0 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } }; -static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { - { { 11 /* ars_entry */ }, 's' }, - { { 4 /* ars */ }, 'i' }, - { { 1 /* uimm12x8 */ }, 'i' } +static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { + { { 4 /* ars */ }, 'i' } }; -static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSWOE }, 'i' }, - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' } +static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { + { { STATE_XTSYNC }, 'o' } }; -static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { +static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { { { 6 /* art */ }, 'o' }, { { 4 /* ars */ }, 'i' } }; -static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { - { { STATE_WindowBase }, 'i' }, - { { STATE_WindowStart }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { - { { 2 /* simm4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowBase }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { - { { 5 /* *ars_invisible */ }, 'i' } +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' } }; -static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSWOE }, 'i' } +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { + { { STATE_XTSYNC }, 'o' } }; -static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { - { { STATE_EPC1 }, 'i' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' }, - { { STATE_PSOWB }, 'i' } +static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { + { { 4 /* ars */ }, 'i' } }; -static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { +static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 12 /* immrx4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } + { { 4 /* ars */ }, 'i' } }; -static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { +static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { { { 6 /* art */ }, 'i' }, - { { 4 /* ars */ }, 'i' }, - { { 12 /* immrx4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowBase }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowBase }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowBase }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowStart }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowStart }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowStart }, 'm' } + { { 4 /* ars */ }, 'i' } }; -static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { +static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { { { 3 /* arr */ }, 'o' }, { { 4 /* ars */ }, 'i' }, { { 6 /* art */ }, 'i' } }; -static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 16 /* ai4const */ }, 'i' } +static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' } }; -static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { +static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { + { { 3 /* arr */ }, 'o' }, { { 4 /* ars */ }, 'i' }, - { { 15 /* uimm6 */ }, 'i' } + { { 35 /* tp7 */ }, 'i' } }; -static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { +static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { { { 6 /* art */ }, 'o' }, { { 4 /* ars */ }, 'i' }, - { { 13 /* lsi4x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { - { { 4 /* ars */ }, 'o' }, - { { 14 /* simm7 */ }, 'i' } + { { 21 /* uimm8x4 */ }, 'i' } }; -static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { - { { 5 /* *ars_invisible */ }, 'i' } +static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } }; -static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { - { { 6 /* art */ }, 'i' }, +static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = { + { { 6 /* art */ }, 'm' }, { { 4 /* ars */ }, 'i' }, - { { 13 /* lsi4x4 */ }, 'i' } + { { 21 /* uimm8x4 */ }, 'i' } }; -static xtensa_arg_internal Iclass_rur_threadptr_args[] = { - { { 3 /* arr */ }, 'o' } +static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'i' }, + { { STATE_SCOMPARE1 }, 'i' } }; -static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = { - { { STATE_THREADPTR }, 'i' } +static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = { + { { 6 /* art */ }, 'o' } }; -static xtensa_arg_internal Iclass_wur_threadptr_args[] = { - { { 6 /* art */ }, 'i' } +static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'i' } }; -static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = { - { { STATE_THREADPTR }, 'o' } +static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = { + { { 6 /* art */ }, 'i' } }; -static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 23 /* simm8 */ }, 'i' } +static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'o' } }; -static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 24 /* simm8x256 */ }, 'i' } +static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = { + { { 6 /* art */ }, 'm' } }; -static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 6 /* art */ }, 'i' } +static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'm' } }; -static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { +static xtensa_arg_internal Iclass_xt_mul32_args[] = { { { 3 /* arr */ }, 'o' }, { { 4 /* ars */ }, 'i' }, { { 6 /* art */ }, 'i' } }; -static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 17 /* b4const */ }, 'i' }, - { { 28 /* label8 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 67 /* bbi */ }, 'i' }, - { { 28 /* label8 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 18 /* b4constu */ }, 'i' }, - { { 28 /* label8 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 6 /* art */ }, 'i' }, - { { 28 /* label8 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 30 /* label12 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { - { { 0 /* soffsetx4 */ }, 'i' }, - { { 7 /* ar0 */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 7 /* ar0 */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 6 /* art */ }, 'i' }, - { { 82 /* sae */ }, 'i' }, - { { 27 /* op2p1 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { - { { 31 /* soffset */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 20 /* uimm8x2 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 20 /* uimm8x2 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 21 /* uimm8x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { - { { 6 /* art */ }, 'o' }, - { { 32 /* uimm16x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = { - { { STATE_LITBADDR }, 'i' }, - { { STATE_LITBEN }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 19 /* uimm8 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 29 /* ulabel8 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { - { { STATE_LBEG }, 'o' }, - { { STATE_LEND }, 'o' }, - { { STATE_LCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 29 /* ulabel8 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { - { { STATE_LBEG }, 'o' }, - { { STATE_LEND }, 'o' }, - { { STATE_LCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { - { { 6 /* art */ }, 'o' }, - { { 25 /* simm12b */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { - { { 3 /* arr */ }, 'm' }, - { { 4 /* ars */ }, 'i' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { - { { 5 /* *ars_invisible */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { - { { 6 /* art */ }, 'i' }, - { { 4 /* ars */ }, 'i' }, - { { 20 /* uimm8x2 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { - { { 6 /* art */ }, 'i' }, - { { 4 /* ars */ }, 'i' }, - { { 21 /* uimm8x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { - { { 6 /* art */ }, 'i' }, - { { 4 /* ars */ }, 'i' }, - { { 19 /* uimm8 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { - { { STATE_SAR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { - { { 86 /* sas */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { - { { STATE_SAR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 26 /* msalp32 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 6 /* art */ }, 'i' }, - { { 84 /* sargt */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 6 /* art */ }, 'i' }, - { { 70 /* s */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { - { { STATE_XTSYNC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { - { { 6 /* art */ }, 'o' }, - { { 70 /* s */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { - { { STATE_PSWOE }, 'i' }, - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSOWB }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PSUM }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { - { { STATE_LEND }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { - { { STATE_LEND }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { - { { STATE_LEND }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { - { { STATE_LCOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_LCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_LCOUNT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { - { { STATE_LBEG }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { - { { STATE_LBEG }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { - { { STATE_LBEG }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { - { { STATE_SAR }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { - { { STATE_SAR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = { - { { STATE_LITBADDR }, 'i' }, - { { STATE_LITBEN }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = { - { { STATE_LITBADDR }, 'o' }, - { { STATE_LITBEN }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = { - { { STATE_LITBADDR }, 'm' }, - { { STATE_LITBEN }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'i' }, - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSOWB }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PSUM }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSRING }, 'm' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_PSINTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'm' }, - { { STATE_PSCALLINC }, 'm' }, - { { STATE_PSOWB }, 'm' }, - { { STATE_PSRING }, 'm' }, - { { STATE_PSUM }, 'm' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_PSINTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC5 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC5 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC5 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE5 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE5 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE5 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC6 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC6 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE6 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE6 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC7 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC7 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE7 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE7 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS5 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS5 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS5 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS6 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS6 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS7 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS7 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCVADDR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCVADDR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEPC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEPC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEPC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCCAUSE }, 'i' }, - { { STATE_XTSYNC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCCAUSE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCCAUSE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC0 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_VECBASE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_VECBASE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_VECBASE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = { - { { STATE_ACC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 34 /* my */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = { - { { STATE_ACC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = { - { { 33 /* mx */ }, 'i' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = { - { { STATE_ACC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = { - { { 33 /* mx */ }, 'i' }, - { { 34 /* my */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = { - { { STATE_ACC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 34 /* my */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = { - { { 33 /* mx */ }, 'i' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = { - { { 33 /* mx */ }, 'i' }, - { { 34 /* my */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = { - { { 35 /* mw */ }, 'o' }, - { { 4 /* ars */ }, 'm' }, - { { 33 /* mx */ }, 'i' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = { - { { 35 /* mw */ }, 'o' }, - { { 4 /* ars */ }, 'm' }, - { { 33 /* mx */ }, 'i' }, - { { 34 /* my */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = { - { { 35 /* mw */ }, 'o' }, - { { 4 /* ars */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mul16_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = { - { { 6 /* art */ }, 'o' }, - { { 36 /* mr0 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = { - { { 6 /* art */ }, 'i' }, - { { 36 /* mr0 */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = { - { { 6 /* art */ }, 'm' }, - { { 36 /* mr0 */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = { - { { 6 /* art */ }, 'o' }, - { { 37 /* mr1 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = { - { { 6 /* art */ }, 'i' }, - { { 37 /* mr1 */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = { - { { 6 /* art */ }, 'm' }, - { { 37 /* mr1 */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = { - { { 6 /* art */ }, 'o' }, - { { 38 /* mr2 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = { - { { 6 /* art */ }, 'i' }, - { { 38 /* mr2 */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = { - { { 6 /* art */ }, 'm' }, - { { 38 /* mr2 */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = { - { { 6 /* art */ }, 'o' }, - { { 39 /* mr3 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = { - { { 6 /* art */ }, 'i' }, - { { 39 /* mr3 */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = { - { { 6 /* art */ }, 'm' }, - { { 39 /* mr3 */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = { - { { STATE_ACC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = { - { { STATE_ACC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { - { { 70 /* s */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSRING }, 'm' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_PSINTLEVEL }, 'o' }, - { { STATE_EPC1 }, 'i' }, - { { STATE_EPC2 }, 'i' }, - { { STATE_EPC3 }, 'i' }, - { { STATE_EPC4 }, 'i' }, - { { STATE_EPC5 }, 'i' }, - { { STATE_EPC6 }, 'i' }, - { { STATE_EPC7 }, 'i' }, - { { STATE_EPS2 }, 'i' }, - { { STATE_EPS3 }, 'i' }, - { { STATE_EPS4 }, 'i' }, - { { STATE_EPS5 }, 'i' }, - { { STATE_EPS6 }, 'i' }, - { { STATE_EPS7 }, 'i' }, - { { STATE_InOCDMode }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { - { { 70 /* s */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PSINTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INTERRUPT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INTENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INTENABLE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INTENABLE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { - { { 41 /* imms */ }, 'i' }, - { { 40 /* immt */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { - { { 41 /* imms */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKA0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKA0 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKA0 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKC0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKC0 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKC0 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKA1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKA1 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKA1 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKC1 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKC1 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKA0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKA0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKA0 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKA1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKA1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKA1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKENABLE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKENABLE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEBUGCAUSE }, 'i' }, - { { STATE_DBNUM }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEBUGCAUSE }, 'o' }, - { { STATE_DBNUM }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEBUGCAUSE }, 'm' }, - { { STATE_DBNUM }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ICOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_ICOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_ICOUNT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ICOUNTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ICOUNTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ICOUNTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_DDR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_DDR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { - { { 41 /* imms */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { - { { STATE_InOCDMode }, 'm' }, - { { STATE_EPC6 }, 'i' }, - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSRING }, 'o' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'o' }, - { { STATE_PSINTLEVEL }, 'o' }, - { { STATE_EPS6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { - { { STATE_InOCDMode }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = { - { { 44 /* br */ }, 'o' }, - { { 43 /* bs */ }, 'i' }, - { { 42 /* bt */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = { - { { 42 /* bt */ }, 'o' }, - { { 49 /* bs4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = { - { { 42 /* bt */ }, 'o' }, - { { 52 /* bs8 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = { - { { 43 /* bs */ }, 'i' }, - { { 28 /* label8 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = { - { { 3 /* arr */ }, 'm' }, - { { 4 /* ars */ }, 'i' }, - { { 42 /* bt */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = { - { { 6 /* art */ }, 'o' }, - { { 57 /* brall */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = { - { { 6 /* art */ }, 'i' }, - { { 57 /* brall */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = { - { { 6 /* art */ }, 'm' }, - { { 57 /* brall */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_CCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_CCOUNT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE0 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE0 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE1 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE1 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE2 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE2 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 21 /* uimm8x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 22 /* uimm4x16 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 21 /* uimm8x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { - { { 6 /* art */ }, 'i' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 21 /* uimm8x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 22 /* uimm4x16 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 21 /* uimm8x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 21 /* uimm8x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 22 /* uimm4x16 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { - { { 6 /* art */ }, 'i' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PTBASE }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PTBASE }, 'i' }, - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PTBASE }, 'm' }, - { { STATE_EXCVADDR }, 'i' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ASID3 }, 'i' }, - { { STATE_ASID2 }, 'i' }, - { { STATE_ASID1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ASID3 }, 'o' }, - { { STATE_ASID2 }, 'o' }, - { { STATE_ASID1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ASID3 }, 'm' }, - { { STATE_ASID2 }, 'm' }, - { { STATE_ASID1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INSTPGSZID4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INSTPGSZID4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INSTPGSZID4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DATAPGSZID4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DATAPGSZID4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DATAPGSZID4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { - { { 6 /* art */ }, 'i' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { - { { 6 /* art */ }, 'i' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = { - { { STATE_PTBASE }, 'i' }, - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = { - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = { - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CPENABLE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CPENABLE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 58 /* tp7 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 58 /* tp7 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 21 /* uimm8x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { - { { 6 /* art */ }, 'i' }, - { { 4 /* ars */ }, 'i' }, - { { 21 /* uimm8x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = { - { { 6 /* art */ }, 'm' }, - { { 4 /* ars */ }, 'i' }, - { { 21 /* uimm8x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'i' }, - { { STATE_SCOMPARE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_div_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_mul32_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_fcr_args[] = { - { { 3 /* arr */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_fcr_stateArgs[] = { - { { STATE_RoundMode }, 'i' }, - { { STATE_InvalidEnable }, 'i' }, - { { STATE_DivZeroEnable }, 'i' }, - { { STATE_OverflowEnable }, 'i' }, - { { STATE_UnderflowEnable }, 'i' }, - { { STATE_InexactEnable }, 'i' }, - { { STATE_FPreserved20 }, 'i' }, - { { STATE_FPreserved5 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_fcr_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_fcr_stateArgs[] = { - { { STATE_RoundMode }, 'o' }, - { { STATE_InvalidEnable }, 'o' }, - { { STATE_DivZeroEnable }, 'o' }, - { { STATE_OverflowEnable }, 'o' }, - { { STATE_UnderflowEnable }, 'o' }, - { { STATE_InexactEnable }, 'o' }, - { { STATE_FPreserved20 }, 'o' }, - { { STATE_FPreserved5 }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_fsr_args[] = { - { { 3 /* arr */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_fsr_stateArgs[] = { - { { STATE_InvalidFlag }, 'i' }, - { { STATE_DivZeroFlag }, 'i' }, - { { STATE_OverflowFlag }, 'i' }, - { { STATE_UnderflowFlag }, 'i' }, - { { STATE_InexactFlag }, 'i' }, - { { STATE_FPreserved20a }, 'i' }, - { { STATE_FPreserved7 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_fsr_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_fsr_stateArgs[] = { - { { STATE_InvalidFlag }, 'o' }, - { { STATE_DivZeroFlag }, 'o' }, - { { STATE_OverflowFlag }, 'o' }, - { { STATE_UnderflowFlag }, 'o' }, - { { STATE_InexactFlag }, 'o' }, - { { STATE_FPreserved20a }, 'o' }, - { { STATE_FPreserved7 }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_args[] = { - { { 62 /* frr */ }, 'o' }, - { { 63 /* frs */ }, 'i' }, - { { 64 /* frt */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_stateArgs[] = { - { { STATE_RoundMode }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_mac_args[] = { - { { 62 /* frr */ }, 'm' }, - { { 63 /* frs */ }, 'i' }, - { { 64 /* frt */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_mac_stateArgs[] = { - { { STATE_RoundMode }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_cmov_args[] = { - { { 62 /* frr */ }, 'm' }, - { { 63 /* frs */ }, 'i' }, - { { 42 /* bt */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_cmov_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_mov_args[] = { - { { 62 /* frr */ }, 'm' }, - { { 63 /* frs */ }, 'i' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_mov_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_mov2_args[] = { - { { 62 /* frr */ }, 'o' }, - { { 63 /* frs */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_mov2_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_cmp_args[] = { - { { 44 /* br */ }, 'o' }, - { { 63 /* frs */ }, 'i' }, - { { 64 /* frt */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_cmp_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_float_args[] = { - { { 62 /* frr */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 65 /* t */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_float_stateArgs[] = { - { { STATE_RoundMode }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_int_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 63 /* frs */ }, 'i' }, - { { 65 /* t */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_int_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_rfr_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 63 /* frs */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_rfr_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_wfr_args[] = { - { { 62 /* frr */ }, 'o' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_wfr_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_lsi_args[] = { - { { 64 /* frt */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 61 /* cimm8x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_lsi_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_lsiu_args[] = { - { { 64 /* frt */ }, 'o' }, - { { 4 /* ars */ }, 'm' }, - { { 61 /* cimm8x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_lsiu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_lsx_args[] = { - { { 62 /* frr */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_lsx_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_lsxu_args[] = { - { { 62 /* frr */ }, 'o' }, - { { 4 /* ars */ }, 'm' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_lsxu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_ssi_args[] = { - { { 64 /* frt */ }, 'i' }, - { { 4 /* ars */ }, 'i' }, - { { 61 /* cimm8x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_ssi_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_ssiu_args[] = { - { { 64 /* frt */ }, 'i' }, - { { 4 /* ars */ }, 'm' }, - { { 61 /* cimm8x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_ssiu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_ssx_args[] = { - { { 62 /* frr */ }, 'i' }, - { { 4 /* ars */ }, 'i' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_ssx_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_ssxu_args[] = { - { { 62 /* frr */ }, 'i' }, - { { 4 /* ars */ }, 'm' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_fp_ssxu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wb18_0_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 60 /* xt_wbr18_label */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wb18_1_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 17 /* b4const */ }, 'i' }, - { { 60 /* xt_wbr18_label */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wb18_2_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 18 /* b4constu */ }, 'i' }, - { { 60 /* xt_wbr18_label */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wb18_3_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 67 /* bbi */ }, 'i' }, - { { 60 /* xt_wbr18_label */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wb18_4_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 6 /* art */ }, 'i' }, - { { 60 /* xt_wbr18_label */ }, 'i' } -}; - -static xtensa_iclass_internal iclasses[] = { - { 0, 0 /* xt_iclass_excw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_rfe */, - 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfde */, - 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_syscall */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_simcall */, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_call12_args, - 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_call8_args, - 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_call4_args, - 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx12_args, - 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx8_args, - 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx4_args, - 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_entry_args, - 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_movsp_args, - 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rotw_args, - 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_retw_args, - 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfwou */, - 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_l32e_args, - 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_s32e_args, - 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_windowbase_args, - 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_windowbase_args, - 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_windowbase_args, - 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_windowstart_args, - 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_windowstart_args, - 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_windowstart_args, - 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_add_n_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addi_n_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bz6_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_ill_n */, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_loadi4_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_mov_n_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_movi_n_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_nopn */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_retn_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_storei4_args, - 0, 0, 0, 0 }, - { 1, Iclass_rur_threadptr_args, - 1, Iclass_rur_threadptr_stateArgs, 0, 0 }, - { 1, Iclass_wur_threadptr_args, - 1, Iclass_wur_threadptr_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_addi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addmi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addsub_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bit_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8b_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8u_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bst8_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bsz12_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_call0_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_callx0_args, - 0, 0, 0, 0 }, - { 4, Iclass_xt_iclass_exti_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_ill */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_jump_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_jumpx_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l16ui_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l16si_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l32i_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_l32r_args, - 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_l8i_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_loop_args, - 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_loopz_args, - 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_movi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_movz_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_neg_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_nop */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_return_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s16i_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32i_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s8i_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_sar_args, - 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_sari_args, - 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_shifts_args, - 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_shiftst_args, - 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_shiftt_args, - 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_slli_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_srai_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_srli_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_memw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_extw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_isync */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_sync */, - 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_rsil_args, - 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_lend_args, - 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_lend_args, - 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_lend_args, - 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_lcount_args, - 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_lcount_args, - 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_lcount_args, - 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_lbeg_args, - 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_lbeg_args, - 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_lbeg_args, - 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_sar_args, - 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_sar_args, - 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_sar_args, - 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_litbase_args, - 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_litbase_args, - 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_litbase_args, - 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_176_args, - 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_208_args, - 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ps_args, - 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ps_args, - 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ps_args, - 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc1_args, - 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc1_args, - 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc1_args, - 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave1_args, - 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave1_args, - 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave1_args, - 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc2_args, - 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc2_args, - 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc2_args, - 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave2_args, - 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave2_args, - 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave2_args, - 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc3_args, - 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc3_args, - 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc3_args, - 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave3_args, - 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave3_args, - 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave3_args, - 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc4_args, - 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc4_args, - 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc4_args, - 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave4_args, - 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave4_args, - 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave4_args, - 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc5_args, - 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc5_args, - 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc5_args, - 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave5_args, - 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave5_args, - 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave5_args, - 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc6_args, - 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc6_args, - 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc6_args, - 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave6_args, - 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave6_args, - 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave6_args, - 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc7_args, - 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc7_args, - 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc7_args, - 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave7_args, - 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave7_args, - 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave7_args, - 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps2_args, - 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps2_args, - 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps2_args, - 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps3_args, - 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps3_args, - 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps3_args, - 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps4_args, - 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps4_args, - 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps4_args, - 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps5_args, - 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps5_args, - 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps5_args, - 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps6_args, - 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps6_args, - 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps6_args, - 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps7_args, - 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps7_args, - 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps7_args, - 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excvaddr_args, - 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excvaddr_args, - 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excvaddr_args, - 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_depc_args, - 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_depc_args, - 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_depc_args, - 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_exccause_args, - 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_exccause_args, - 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_exccause_args, - 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_misc0_args, - 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_misc0_args, - 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_misc0_args, - 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_misc1_args, - 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_misc1_args, - 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_misc1_args, - 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_misc2_args, - 3, Iclass_xt_iclass_rsr_misc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_misc2_args, - 3, Iclass_xt_iclass_wsr_misc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_misc2_args, - 3, Iclass_xt_iclass_xsr_misc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_misc3_args, - 3, Iclass_xt_iclass_rsr_misc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_misc3_args, - 3, Iclass_xt_iclass_wsr_misc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_misc3_args, - 3, Iclass_xt_iclass_xsr_misc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_prid_args, - 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_vecbase_args, - 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_vecbase_args, - 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_vecbase_args, - 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_aa_args, - 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_ad_args, - 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_da_args, - 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_dd_args, - 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16a_aa_args, - 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16a_ad_args, - 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16a_da_args, - 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16a_dd_args, - 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 }, - { 4, Iclass_xt_iclass_mac16al_da_args, - 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 }, - { 4, Iclass_xt_iclass_mac16al_dd_args, - 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_l_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_mul16_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_rsr_m0_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wsr_m0_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_xsr_m0_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_rsr_m1_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wsr_m1_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_xsr_m1_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_rsr_m2_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wsr_m2_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_xsr_m2_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_rsr_m3_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wsr_m3_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_xsr_m3_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_acclo_args, - 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_acclo_args, - 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_acclo_args, - 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_acchi_args, - 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_acchi_args, - 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_acchi_args, - 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rfi_args, - 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wait_args, - 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_interrupt_args, - 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intset_args, - 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intclear_args, - 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_intenable_args, - 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intenable_args, - 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_intenable_args, - 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_break_args, - 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_break_n_args, - 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreaka0_args, - 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreaka0_args, - 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreaka0_args, - 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreakc0_args, - 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreakc0_args, - 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreakc0_args, - 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreaka1_args, - 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreaka1_args, - 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreaka1_args, - 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreakc1_args, - 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreakc1_args, - 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreakc1_args, - 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ibreaka0_args, - 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ibreaka0_args, - 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ibreaka0_args, - 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ibreaka1_args, - 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ibreaka1_args, - 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ibreaka1_args, - 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ibreakenable_args, - 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ibreakenable_args, - 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ibreakenable_args, - 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_debugcause_args, - 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_debugcause_args, - 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_debugcause_args, - 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_icount_args, - 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_icount_args, - 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_icount_args, - 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_icountlevel_args, - 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_icountlevel_args, - 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_icountlevel_args, - 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ddr_args, - 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ddr_args, - 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ddr_args, - 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rfdo_args, - 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfdd */, - 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_mmid_args, - 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_bbool1_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bbool4_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bbool8_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bbranch_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bmove_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_RSR_BR_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_WSR_BR_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_XSR_BR_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccount_args, - 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccount_args, - 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccount_args, - 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare0_args, - 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare0_args, - 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare0_args, - 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare1_args, - 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare1_args, - 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare1_args, - 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare2_args, - 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare2_args, - 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare2_args, - 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_icache_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_icache_lock_args, - 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_icache_inv_args, - 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_licx_args, - 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_sicx_args, - 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_ind_args, - 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_inv_args, - 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_dpf_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_lock_args, - 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_sdct_args, - 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_ldct_args, - 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ptevaddr_args, - 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ptevaddr_args, - 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ptevaddr_args, - 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_rasid_args, - 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_rasid_args, - 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_rasid_args, - 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_itlbcfg_args, - 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_itlbcfg_args, - 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_itlbcfg_args, - 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dtlbcfg_args, - 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dtlbcfg_args, - 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dtlbcfg_args, - 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_idtlb_args, - 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_rdtlb_args, - 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_wdtlb_args, - 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_iitlb_args, - 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_ritlb_args, - 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_witlb_args, - 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_ldpte */, - 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_hwwitlba */, - 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_hwwdtlba */, - 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_cpenable_args, - 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_cpenable_args, - 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_cpenable_args, - 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_clamp_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_minmax_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_nsa_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_sx_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l32ai_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32ri_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32c1i_args, - 2, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_scompare1_args, - 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_scompare1_args, - 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_scompare1_args, - 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_div_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_mul32_args, - 0, 0, 0, 0 }, - { 1, Iclass_rur_fcr_args, - 9, Iclass_rur_fcr_stateArgs, 0, 0 }, - { 1, Iclass_wur_fcr_args, - 9, Iclass_wur_fcr_stateArgs, 0, 0 }, - { 1, Iclass_rur_fsr_args, - 8, Iclass_rur_fsr_stateArgs, 0, 0 }, - { 1, Iclass_wur_fsr_args, - 8, Iclass_wur_fsr_stateArgs, 0, 0 }, - { 3, Iclass_fp_args, - 2, Iclass_fp_stateArgs, 0, 0 }, - { 3, Iclass_fp_mac_args, - 2, Iclass_fp_mac_stateArgs, 0, 0 }, - { 3, Iclass_fp_cmov_args, - 1, Iclass_fp_cmov_stateArgs, 0, 0 }, - { 3, Iclass_fp_mov_args, - 1, Iclass_fp_mov_stateArgs, 0, 0 }, - { 2, Iclass_fp_mov2_args, - 1, Iclass_fp_mov2_stateArgs, 0, 0 }, - { 3, Iclass_fp_cmp_args, - 1, Iclass_fp_cmp_stateArgs, 0, 0 }, - { 3, Iclass_fp_float_args, - 2, Iclass_fp_float_stateArgs, 0, 0 }, - { 3, Iclass_fp_int_args, - 1, Iclass_fp_int_stateArgs, 0, 0 }, - { 2, Iclass_fp_rfr_args, - 1, Iclass_fp_rfr_stateArgs, 0, 0 }, - { 2, Iclass_fp_wfr_args, - 1, Iclass_fp_wfr_stateArgs, 0, 0 }, - { 3, Iclass_fp_lsi_args, - 1, Iclass_fp_lsi_stateArgs, 0, 0 }, - { 3, Iclass_fp_lsiu_args, - 1, Iclass_fp_lsiu_stateArgs, 0, 0 }, - { 3, Iclass_fp_lsx_args, - 1, Iclass_fp_lsx_stateArgs, 0, 0 }, - { 3, Iclass_fp_lsxu_args, - 1, Iclass_fp_lsxu_stateArgs, 0, 0 }, - { 3, Iclass_fp_ssi_args, - 1, Iclass_fp_ssi_stateArgs, 0, 0 }, - { 3, Iclass_fp_ssiu_args, - 1, Iclass_fp_ssiu_stateArgs, 0, 0 }, - { 3, Iclass_fp_ssx_args, - 1, Iclass_fp_ssx_stateArgs, 0, 0 }, - { 3, Iclass_fp_ssxu_args, - 1, Iclass_fp_ssxu_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_wb18_0_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_wb18_1_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_wb18_2_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_wb18_3_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_wb18_4_args, - 0, 0, 0, 0 } -}; - - -/* Opcode encodings. */ - -static void -Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2080; -} - -static void -Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000; -} - -static void -Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3200; -} - -static void -Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5000; -} - -static void -Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5100; -} - -static void -Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x35; -} - -static void -Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x25; -} - -static void -Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15; -} - -static void -Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf0; -} - -static void -Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe0; -} - -static void -Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd0; -} - -static void -Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36; -} - -static void -Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1000; -} - -static void -Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x408000; -} - -static void -Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x90; -} - -static void -Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf01d; -} - -static void -Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3400; -} - -static void -Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3500; -} - -static void -Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x90000; -} - -static void -Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x490000; -} - -static void -Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x34800; -} - -static void -Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x134800; -} - -static void -Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x614800; -} - -static void -Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x34900; -} - -static void -Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x134900; -} - -static void -Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x614900; -} - -static void -Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa; -} - -static void -Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb; -} - -static void -Opcode_addi_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000; -} - -static void -Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8c; -} - -static void -Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xcc; -} - -static void -Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf06d; -} - -static void -Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8; -} - -static void -Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd; -} - -static void -Opcode_mov_n_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000; -} - -static void -Opcode_mov_n_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa3000; -} - -static void -Opcode_mov_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc080; -} - -static void -Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc; -} - -static void -Opcode_movi_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc000; -} - -static void -Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf03d; -} - -static void -Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf00d; -} - -static void -Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9; -} - -static void -Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30e70; -} - -static void -Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3e700; -} - -static void -Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc002; -} - -static void -Opcode_addi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60000; -} - -static void -Opcode_addi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200c00; -} - -static void -Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd002; -} - -static void -Opcode_addmi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70000; -} - -static void -Opcode_addmi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200d00; -} - -static void -Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x800000; -} - -static void -Opcode_add_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x92000; -} - -static void -Opcode_add_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000; -} - -static void -Opcode_add_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80000; -} - -static void -Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc00000; -} - -static void -Opcode_sub_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa8000; -} - -static void -Opcode_sub_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa000; -} - -static void -Opcode_sub_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc0000; -} - -static void -Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x900000; -} - -static void -Opcode_addx2_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x94000; -} - -static void -Opcode_addx2_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000; -} - -static void -Opcode_addx2_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x90000; -} - -static void -Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa00000; -} - -static void -Opcode_addx4_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x98000; -} - -static void -Opcode_addx4_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5000; -} - -static void -Opcode_addx4_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa0000; -} - -static void -Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb00000; -} - -static void -Opcode_addx8_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x93000; -} - -static void -Opcode_addx8_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb0000; -} - -static void -Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd00000; -} - -static void -Opcode_subx2_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd0000; -} - -static void -Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe00000; -} - -static void -Opcode_subx4_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe0000; -} - -static void -Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf00000; -} - -static void -Opcode_subx8_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf0000; -} - -static void -Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x100000; -} - -static void -Opcode_and_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x95000; -} - -static void -Opcode_and_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000; -} - -static void -Opcode_and_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10000; -} - -static void -Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200000; -} - -static void -Opcode_or_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9e000; -} - -static void -Opcode_or_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7000; -} - -static void -Opcode_or_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20000; -} - -static void -Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300000; -} - -static void -Opcode_xor_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb0000; -} - -static void -Opcode_xor_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb000; -} - -static void -Opcode_xor_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30000; -} - -static void -Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x26; -} - -static void -Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x66; -} - -static void -Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe6; -} - -static void -Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa6; -} - -static void -Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6007; -} - -static void -Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe007; -} - -static void -Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf6; -} - -static void -Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb6; -} - -static void -Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1007; -} - -static void -Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9007; -} - -static void -Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa007; -} - -static void -Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2007; -} - -static void -Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb007; -} - -static void -Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3007; -} - -static void -Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8007; -} - -static void -Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7; -} - -static void -Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4007; -} - -static void -Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc007; -} - -static void -Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5007; -} - -static void -Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd007; -} - -static void -Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16; -} - -static void -Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x56; -} - -static void -Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd6; -} - -static void -Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x96; -} - -static void -Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5; -} - -static void -Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc0; -} - -static void -Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40000; -} - -static void -Opcode_extui_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40000; -} - -static void -Opcode_extui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000; -} - -static void -Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0; -} - -static void -Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6; -} - -static void -Opcode_j_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc0000; -} - -static void -Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa0; -} - -static void -Opcode_jx_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa3010; -} - -static void -Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1002; -} - -static void -Opcode_l16ui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200100; -} - -static void -Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9002; -} - -static void -Opcode_l16si_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200900; -} - -static void -Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2002; -} - -static void -Opcode_l32i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200200; -} - -static void -Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1; -} - -static void -Opcode_l32r_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x100000; -} - -static void -Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2; -} - -static void -Opcode_l8ui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200000; -} - -static void -Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8076; -} - -static void -Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9076; -} - -static void -Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa076; -} - -static void -Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa002; -} - -static void -Opcode_movi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80000; -} - -static void -Opcode_movi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200a00; -} - -static void -Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x830000; -} - -static void -Opcode_moveqz_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x96000; -} - -static void -Opcode_moveqz_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x83000; -} - -static void -Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x930000; -} - -static void -Opcode_movnez_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9a000; -} - -static void -Opcode_movnez_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x93000; -} - -static void -Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa30000; -} - -static void -Opcode_movltz_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x99000; -} - -static void -Opcode_movltz_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa3000; -} - -static void -Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb30000; -} - -static void -Opcode_movgez_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x97000; -} - -static void -Opcode_movgez_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb3000; -} - -static void -Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600000; -} - -static void -Opcode_neg_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa5000; -} - -static void -Opcode_neg_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd100; -} - -static void -Opcode_neg_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60000; -} - -static void -Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600100; -} - -static void -Opcode_abs_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd000; -} - -static void -Opcode_abs_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60010; -} - -static void -Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20f0; -} - -static void -Opcode_nop_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa3040; -} - -static void -Opcode_nop_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc090; -} - -static void -Opcode_nop_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc8000000; - slotbuf[1] = 0; -} - -static void -Opcode_nop_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20f; -} - -static void -Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80; -} - -static void -Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5002; -} - -static void -Opcode_s16i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200500; -} - -static void -Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6002; -} - -static void -Opcode_s32i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200600; -} - -static void -Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4002; -} - -static void -Opcode_s8i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200400; -} - -static void -Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400000; -} - -static void -Opcode_ssr_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40000; -} - -static void -Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x401000; -} - -static void -Opcode_ssl_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa3020; -} - -static void -Opcode_ssl_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40100; -} - -static void -Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x402000; -} - -static void -Opcode_ssa8l_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40200; -} - -static void -Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x403000; -} - -static void -Opcode_ssa8b_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40300; -} - -static void -Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x404000; -} - -static void -Opcode_ssai_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40400; -} - -static void -Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa10000; -} - -static void -Opcode_sll_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa6000; -} - -static void -Opcode_sll_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa1000; -} - -static void -Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x810000; -} - -static void -Opcode_src_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa2000; -} - -static void -Opcode_src_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x81000; -} - -static void -Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x910000; -} - -static void -Opcode_srl_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa5200; -} - -static void -Opcode_srl_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd400; -} - -static void -Opcode_srl_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x91000; -} - -static void -Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb10000; -} - -static void -Opcode_sra_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa5100; -} - -static void -Opcode_sra_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd200; -} - -static void -Opcode_sra_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb1000; -} - -static void -Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10000; -} - -static void -Opcode_slli_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x90000; -} - -static void -Opcode_slli_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1000; -} - -static void -Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x210000; -} - -static void -Opcode_srai_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa0000; -} - -static void -Opcode_srai_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe000; -} - -static void -Opcode_srai_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x21000; -} - -static void -Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x410000; -} - -static void -Opcode_srli_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa4000; -} - -static void -Opcode_srli_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9000; -} - -static void -Opcode_srli_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x41000; -} - -static void -Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20c0; -} - -static void -Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20d0; -} - -static void -Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000; -} - -static void -Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2010; -} - -static void -Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2020; -} - -static void -Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2030; -} - -static void -Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000; -} - -static void -Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30100; -} - -static void -Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130100; -} - -static void -Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610100; -} - -static void -Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30200; -} - -static void -Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130200; -} - -static void -Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610200; -} - -static void -Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30000; -} - -static void -Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130000; -} - -static void -Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610000; -} - -static void -Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30300; -} - -static void -Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130300; -} - -static void -Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610300; -} - -static void -Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30500; -} - -static void -Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130500; -} - -static void -Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610500; -} - -static void -Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b000; -} - -static void -Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d000; -} - -static void -Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e600; -} - -static void -Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e600; -} - -static void -Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e600; -} - -static void -Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b100; -} - -static void -Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b100; -} - -static void -Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b100; -} - -static void -Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d100; -} - -static void -Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d100; -} - -static void -Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d100; -} - -static void -Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b200; -} - -static void -Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b200; -} - -static void -Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b200; -} - -static void -Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d200; -} - -static void -Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d200; -} - -static void -Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d200; -} - -static void -Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b300; -} - -static void -Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b300; -} - -static void -Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b300; -} - -static void -Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d300; -} - -static void -Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d300; -} - -static void -Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d300; -} - -static void -Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b400; -} - -static void -Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b400; -} - -static void -Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b400; -} - -static void -Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d400; -} - -static void -Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d400; -} - -static void -Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d400; -} - -static void -Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b500; -} - -static void -Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b500; -} - -static void -Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b500; -} - -static void -Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d500; -} - -static void -Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d500; -} - -static void -Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d500; -} - -static void -Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b600; -} - -static void -Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b600; -} - -static void -Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b600; -} - -static void -Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d600; -} - -static void -Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d600; -} - -static void -Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d600; -} - -static void -Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b700; -} - -static void -Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b700; -} - -static void -Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b700; -} - -static void -Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d700; -} - -static void -Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d700; -} - -static void -Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d700; -} - -static void -Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c200; -} - -static void -Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c200; -} - -static void -Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c200; -} - -static void -Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c300; -} - -static void -Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c300; -} - -static void -Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c300; -} - -static void -Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c400; -} - -static void -Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c400; -} - -static void -Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c400; -} - -static void -Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c500; -} - -static void -Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c500; -} - -static void -Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c500; -} - -static void -Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c600; -} - -static void -Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c600; -} - -static void -Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c600; -} - -static void -Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c700; -} - -static void -Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c700; -} - -static void -Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c700; -} - -static void -Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ee00; -} - -static void -Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ee00; -} - -static void -Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ee00; -} - -static void -Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c000; -} - -static void -Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c000; -} - -static void -Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c000; -} - -static void -Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e800; -} - -static void -Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e800; -} - -static void -Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e800; -} - -static void -Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f400; -} - -static void -Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f400; -} - -static void -Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f400; -} - -static void -Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f500; -} - -static void -Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f500; -} - -static void -Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f500; -} - -static void -Opcode_rsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f600; -} - -static void -Opcode_wsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f600; -} - -static void -Opcode_xsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f600; -} - -static void -Opcode_rsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f700; -} - -static void -Opcode_wsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f700; -} - -static void -Opcode_xsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f700; -} - -static void -Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3eb00; -} - -static void -Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e700; -} - -static void -Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e700; -} - -static void -Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e700; -} - -static void -Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x740004; -} - -static void -Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x750004; -} - -static void -Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x760004; -} - -static void -Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x770004; -} - -static void -Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700004; -} - -static void -Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x710004; -} - -static void -Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x720004; -} - -static void -Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x730004; -} - -static void -Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x340004; -} - -static void -Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x350004; -} - -static void -Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x360004; -} - -static void -Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x370004; -} - -static void -Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x640004; -} - -static void -Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x650004; -} - -static void -Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x660004; -} - -static void -Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x670004; -} - -static void -Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x240004; -} - -static void -Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x250004; -} - -static void -Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x260004; -} - -static void -Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x270004; -} - -static void -Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x780004; -} - -static void -Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x790004; -} - -static void -Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7a0004; -} - -static void -Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7b0004; -} - -static void -Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7c0004; -} - -static void -Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7d0004; -} - -static void -Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7e0004; -} - -static void -Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7f0004; -} - -static void -Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x380004; -} - -static void -Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x390004; -} - -static void -Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3a0004; -} - -static void -Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b0004; -} - -static void -Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c0004; -} - -static void -Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d0004; -} - -static void -Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e0004; -} - -static void -Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f0004; -} - -static void -Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x680004; -} - -static void -Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x690004; -} - -static void -Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6a0004; -} - -static void -Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6b0004; -} - -static void -Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6c0004; -} - -static void -Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6d0004; -} - -static void -Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6e0004; -} - -static void -Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6f0004; -} - -static void -Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x280004; -} - -static void -Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x290004; -} - -static void -Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2a0004; -} - -static void -Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2b0004; -} - -static void -Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2c0004; -} - -static void -Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2d0004; -} - -static void -Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2e0004; -} - -static void -Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2f0004; -} - -static void -Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x580004; -} - -static void -Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x480004; -} - -static void -Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x590004; -} - -static void -Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x490004; -} - -static void -Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5a0004; -} - -static void -Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4a0004; -} - -static void -Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5b0004; -} - -static void -Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4b0004; -} - -static void -Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x180004; -} - -static void -Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80004; -} - -static void -Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x190004; -} - -static void -Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x90004; -} - -static void -Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1a0004; -} - -static void -Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa0004; -} - -static void -Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b0004; -} - -static void -Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb0004; -} - -static void -Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x900004; -} - -static void -Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x800004; -} - -static void -Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc10000; -} - -static void -Opcode_mul16u_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9b000; -} - -static void -Opcode_mul16u_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc1000; -} - -static void -Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd10000; -} - -static void -Opcode_mul16s_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9c000; -} - -static void -Opcode_mul16s_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd1000; -} - -static void -Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x32000; -} - -static void -Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x132000; -} - -static void -Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x612000; -} - -static void -Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x32100; -} - -static void -Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x132100; -} - -static void -Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x612100; -} - -static void -Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x32200; -} - -static void -Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x132200; -} - -static void -Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x612200; -} - -static void -Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x32300; -} - -static void -Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x132300; -} - -static void -Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x612300; -} - -static void -Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x31000; -} - -static void -Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x131000; -} - -static void -Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x611000; -} - -static void -Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x31100; -} - -static void -Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x131100; -} - -static void -Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x611100; -} - -static void -Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3010; -} - -static void -Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7000; -} - -static void -Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e200; -} - -static void -Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e200; -} - -static void -Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e300; -} - -static void -Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e400; -} - -static void -Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e400; -} - -static void -Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e400; -} - -static void -Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000; -} - -static void -Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf02d; -} - -static void -Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x39000; -} - -static void -Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x139000; -} - -static void -Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x619000; -} - -static void -Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3a000; -} - -static void -Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13a000; -} - -static void -Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61a000; -} - -static void -Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x39100; -} - -static void -Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x139100; -} - -static void -Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x619100; -} - -static void -Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3a100; -} - -static void -Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13a100; -} - -static void -Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61a100; -} - -static void -Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x38000; -} - -static void -Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x138000; -} - -static void -Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x618000; -} - -static void -Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x38100; -} - -static void -Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x138100; -} - -static void -Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x618100; -} - -static void -Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36000; -} - -static void -Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136000; -} - -static void -Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616000; -} - -static void -Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e900; -} - -static void -Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e900; -} - -static void -Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e900; -} - -static void -Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ec00; -} - -static void -Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ec00; -} - -static void -Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ec00; -} - -static void -Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ed00; -} - -static void -Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ed00; -} - -static void -Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ed00; -} - -static void -Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36800; -} - -static void -Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136800; -} - -static void -Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616800; -} - -static void -Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf1e000; -} - -static void -Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf1e010; -} - -static void -Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x135900; -} - -static void -Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20000; -} - -static void -Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x120000; -} - -static void -Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x220000; -} - -static void -Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x320000; -} - -static void -Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x420000; -} - -static void -Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8000; -} - -static void -Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9000; -} - -static void -Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa000; -} - -static void -Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb000; -} - -static void -Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x76; -} - -static void -Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1076; -} - -static void -Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc30000; -} - -static void -Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd30000; -} - -static void -Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30400; -} - -static void -Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130400; -} - -static void -Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610400; -} - -static void -Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ea00; -} - -static void -Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ea00; -} - -static void -Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ea00; -} - -static void -Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f000; -} - -static void -Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f000; -} - -static void -Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f000; -} - -static void -Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f100; -} - -static void -Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f100; -} - -static void -Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f100; -} - -static void -Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f200; -} - -static void -Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f200; -} - -static void -Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f200; -} - -static void -Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70c2; -} - -static void -Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70e2; -} - -static void -Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70d2; -} - -static void -Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x270d2; -} - -static void -Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x370d2; -} - -static void -Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70f2; -} - -static void -Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf10000; -} - -static void -Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf12000; -} - -static void -Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf11000; -} - -static void -Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf13000; -} - -static void -Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7042; -} - -static void -Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7052; -} - -static void -Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x47082; -} - -static void -Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x57082; -} - -static void -Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7062; -} - -static void -Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7072; -} - -static void -Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7002; -} - -static void -Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7012; -} - -static void -Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7022; -} - -static void -Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7032; -} - -static void -Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7082; -} - -static void -Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x27082; -} - -static void -Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x37082; -} - -static void -Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf19000; -} - -static void -Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf18000; -} - -static void -Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x135300; -} - -static void -Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x35300; -} - -static void -Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x615300; -} - -static void -Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x35a00; -} - -static void -Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x135a00; -} - -static void -Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x615a00; -} - -static void -Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x35b00; -} - -static void -Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x135b00; -} - -static void -Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x615b00; -} - -static void -Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x35c00; -} - -static void -Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x135c00; -} - -static void -Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x615c00; -} - -static void -Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50c000; -} - -static void -Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50d000; -} - -static void -Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50b000; -} - -static void -Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50f000; -} - -static void -Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50e000; -} - -static void -Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x504000; -} - -static void -Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x505000; -} - -static void -Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x503000; -} - -static void -Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x507000; -} - -static void -Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x506000; -} - -static void -Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf1f000; -} - -static void -Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x501000; -} - -static void -Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x509000; -} - -static void -Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e000; -} - -static void -Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e000; -} - -static void -Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e000; -} - -static void -Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x330000; -} - -static void -Opcode_clamps_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x33000; -} - -static void -Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x430000; -} - -static void -Opcode_min_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x43000; -} - -static void -Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x530000; -} - -static void -Opcode_max_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x53000; -} - -static void -Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x630000; -} - -static void -Opcode_minu_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x63000; -} - -static void -Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x730000; -} - -static void -Opcode_maxu_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x73000; -} - -static void -Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40e000; -} - -static void -Opcode_nsa_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40e00; -} - -static void -Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40f000; -} - -static void -Opcode_nsau_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40f00; -} - -static void -Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x230000; -} - -static void -Opcode_sext_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9f000; -} - -static void -Opcode_sext_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8000; -} - -static void -Opcode_sext_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x23000; -} - -static void -Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb002; -} - -static void -Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf002; -} - -static void -Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe002; -} - -static void -Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30c00; -} - -static void -Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130c00; -} - -static void -Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610c00; -} - -static void -Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc20000; -} - -static void -Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd20000; -} - -static void -Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe20000; -} - -static void -Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf20000; -} - -static void -Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x820000; -} - -static void -Opcode_mull_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9d000; -} - -static void -Opcode_mull_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x82000; -} - -static void -Opcode_muluh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa20000; -} - -static void -Opcode_mulsh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb20000; -} - -static void -Opcode_rur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30e80; -} - -static void -Opcode_wur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3e800; -} - -static void -Opcode_rur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30e90; -} - -static void -Opcode_wur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3e900; -} - -static void -Opcode_add_s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa0000; -} - -static void -Opcode_sub_s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1a0000; -} - -static void -Opcode_mul_s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2a0000; -} - -static void -Opcode_madd_s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4a0000; -} - -static void -Opcode_msub_s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5a0000; -} - -static void -Opcode_movf_s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xcb0000; -} - -static void -Opcode_movt_s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xdb0000; -} - -static void -Opcode_moveqz_s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8b0000; -} - -static void -Opcode_movnez_s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9b0000; -} - -static void -Opcode_movltz_s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xab0000; -} - -static void -Opcode_movgez_s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbb0000; -} - -static void -Opcode_abs_s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xfa0010; -} - -static void -Opcode_mov_s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xfa0000; -} - -static void -Opcode_neg_s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xfa0060; -} - -static void -Opcode_un_s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b0000; -} - -static void -Opcode_oeq_s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2b0000; -} - -static void -Opcode_ueq_s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b0000; -} - -static void -Opcode_olt_s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4b0000; -} - -static void -Opcode_ult_s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5b0000; -} - -static void -Opcode_ole_s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6b0000; -} - -static void -Opcode_ule_s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7b0000; -} - -static void -Opcode_float_s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca0000; -} - -static void -Opcode_ufloat_s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xda0000; -} - -static void -Opcode_round_s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8a0000; -} - -static void -Opcode_ceil_s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xba0000; -} - -static void -Opcode_floor_s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xaa0000; -} - -static void -Opcode_trunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9a0000; -} - -static void -Opcode_utrunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xea0000; -} - -static void -Opcode_rfr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xfa0040; -} - -static void -Opcode_wfr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xfa0050; -} - -static void -Opcode_lsi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3; -} - -static void -Opcode_lsiu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8003; -} - -static void -Opcode_lsx_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80000; -} - -static void -Opcode_lsxu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x180000; -} - -static void -Opcode_ssi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4003; -} - -static void -Opcode_ssiu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc003; -} - -static void -Opcode_ssx_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x480000; -} - -static void -Opcode_ssxu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x580000; -} - -static void -Opcode_beqz_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa8000000; - slotbuf[1] = 0; -} - -static void -Opcode_bnez_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc0000000; - slotbuf[1] = 0; -} - -static void -Opcode_bgez_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb0000000; - slotbuf[1] = 0; -} - -static void -Opcode_bltz_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb8000000; - slotbuf[1] = 0; -} - -static void -Opcode_beqi_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40000000; - slotbuf[1] = 0; -} - -static void -Opcode_bnei_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x98000000; - slotbuf[1] = 0; -} - -static void -Opcode_bgei_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50000000; - slotbuf[1] = 0; -} - -static void -Opcode_blti_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70000000; - slotbuf[1] = 0; -} - -static void -Opcode_bgeui_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60000000; - slotbuf[1] = 0; -} - -static void -Opcode_bltui_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80000000; - slotbuf[1] = 0; -} - -static void -Opcode_bbci_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8000000; - slotbuf[1] = 0; -} - -static void -Opcode_bbsi_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10000000; - slotbuf[1] = 0; -} - -static void -Opcode_beq_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x38000000; - slotbuf[1] = 0; -} - -static void -Opcode_bne_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x90000000; - slotbuf[1] = 0; -} - -static void -Opcode_bge_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x48000000; - slotbuf[1] = 0; -} - -static void -Opcode_blt_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x68000000; - slotbuf[1] = 0; -} - -static void -Opcode_bgeu_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x58000000; - slotbuf[1] = 0; -} - -static void -Opcode_bltu_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x78000000; - slotbuf[1] = 0; -} - -static void -Opcode_bany_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20000000; - slotbuf[1] = 0; -} - -static void -Opcode_bnone_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa0000000; - slotbuf[1] = 0; -} - -static void -Opcode_ball_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x18000000; - slotbuf[1] = 0; -} - -static void -Opcode_bnall_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x88000000; - slotbuf[1] = 0; -} - -static void -Opcode_bbc_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x28000000; - slotbuf[1] = 0; -} - -static void -Opcode_bbs_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30000000; - slotbuf[1] = 0; -} - -xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { - Opcode_excw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { - Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { - Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { - Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { - Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { - Opcode_call12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { - Opcode_call8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { - Opcode_call4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { - Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { - Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { - Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { - Opcode_entry_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { - Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { - Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { - Opcode_retw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { - 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { - Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { - Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { - Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { - Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { - Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { - Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { - Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { - Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { - Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { - Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { - 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { - 0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0, 0, Opcode_addi_n_Slot_xt_flix64_slot2_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { - 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { - 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { - 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { - 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { - 0, 0, Opcode_mov_n_Slot_inst16b_encode, Opcode_mov_n_Slot_xt_flix64_slot0_encode, Opcode_mov_n_Slot_xt_flix64_slot0_encode, Opcode_mov_n_Slot_xt_flix64_slot1_encode, Opcode_mov_n_Slot_xt_flix64_slot2_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { - 0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0, 0, Opcode_movi_n_Slot_xt_flix64_slot2_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { - 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { - 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { - 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { - Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { - Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { - Opcode_addi_Slot_inst_encode, 0, 0, Opcode_addi_Slot_xt_flix64_slot0_encode, Opcode_addi_Slot_xt_flix64_slot0_encode, Opcode_addi_Slot_xt_flix64_slot1_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { - Opcode_addmi_Slot_inst_encode, 0, 0, Opcode_addmi_Slot_xt_flix64_slot0_encode, Opcode_addmi_Slot_xt_flix64_slot0_encode, Opcode_addmi_Slot_xt_flix64_slot1_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { - Opcode_add_Slot_inst_encode, 0, 0, Opcode_add_Slot_xt_flix64_slot0_encode, Opcode_add_Slot_xt_flix64_slot0_encode, Opcode_add_Slot_xt_flix64_slot1_encode, Opcode_add_Slot_xt_flix64_slot2_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { - Opcode_sub_Slot_inst_encode, 0, 0, Opcode_sub_Slot_xt_flix64_slot0_encode, Opcode_sub_Slot_xt_flix64_slot0_encode, Opcode_sub_Slot_xt_flix64_slot1_encode, Opcode_sub_Slot_xt_flix64_slot2_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { - Opcode_addx2_Slot_inst_encode, 0, 0, Opcode_addx2_Slot_xt_flix64_slot0_encode, Opcode_addx2_Slot_xt_flix64_slot0_encode, Opcode_addx2_Slot_xt_flix64_slot1_encode, Opcode_addx2_Slot_xt_flix64_slot2_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { - Opcode_addx4_Slot_inst_encode, 0, 0, Opcode_addx4_Slot_xt_flix64_slot0_encode, Opcode_addx4_Slot_xt_flix64_slot0_encode, Opcode_addx4_Slot_xt_flix64_slot1_encode, Opcode_addx4_Slot_xt_flix64_slot2_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { - Opcode_addx8_Slot_inst_encode, 0, 0, Opcode_addx8_Slot_xt_flix64_slot0_encode, Opcode_addx8_Slot_xt_flix64_slot0_encode, Opcode_addx8_Slot_xt_flix64_slot1_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { - Opcode_subx2_Slot_inst_encode, 0, 0, Opcode_subx2_Slot_xt_flix64_slot0_encode, Opcode_subx2_Slot_xt_flix64_slot0_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { - Opcode_subx4_Slot_inst_encode, 0, 0, Opcode_subx4_Slot_xt_flix64_slot0_encode, Opcode_subx4_Slot_xt_flix64_slot0_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { - Opcode_subx8_Slot_inst_encode, 0, 0, Opcode_subx8_Slot_xt_flix64_slot0_encode, Opcode_subx8_Slot_xt_flix64_slot0_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { - Opcode_and_Slot_inst_encode, 0, 0, Opcode_and_Slot_xt_flix64_slot0_encode, Opcode_and_Slot_xt_flix64_slot0_encode, Opcode_and_Slot_xt_flix64_slot1_encode, Opcode_and_Slot_xt_flix64_slot2_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { - Opcode_or_Slot_inst_encode, 0, 0, Opcode_or_Slot_xt_flix64_slot0_encode, Opcode_or_Slot_xt_flix64_slot0_encode, Opcode_or_Slot_xt_flix64_slot1_encode, Opcode_or_Slot_xt_flix64_slot2_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { - Opcode_xor_Slot_inst_encode, 0, 0, Opcode_xor_Slot_xt_flix64_slot0_encode, Opcode_xor_Slot_xt_flix64_slot0_encode, Opcode_xor_Slot_xt_flix64_slot1_encode, Opcode_xor_Slot_xt_flix64_slot2_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { - Opcode_beqi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { - Opcode_bnei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { - Opcode_bgei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { - Opcode_blti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { - Opcode_bbci_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { - Opcode_bbsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { - Opcode_bgeui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { - Opcode_bltui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { - Opcode_beq_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { - Opcode_bne_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { - Opcode_bge_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { - Opcode_blt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { - Opcode_bgeu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { - Opcode_bltu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { - Opcode_bany_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { - Opcode_bnone_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { - Opcode_ball_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { - Opcode_bnall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { - Opcode_bbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { - Opcode_bbs_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { - Opcode_beqz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { - Opcode_bnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { - Opcode_bgez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { - Opcode_bltz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { - Opcode_call0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { - Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { - Opcode_extui_Slot_inst_encode, 0, 0, Opcode_extui_Slot_xt_flix64_slot0_encode, Opcode_extui_Slot_xt_flix64_slot0_encode, Opcode_extui_Slot_xt_flix64_slot1_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { - Opcode_ill_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { - Opcode_j_Slot_inst_encode, 0, 0, 0, 0, Opcode_j_Slot_xt_flix64_slot1_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { - Opcode_jx_Slot_inst_encode, 0, 0, 0, 0, Opcode_jx_Slot_xt_flix64_slot1_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { - Opcode_l16ui_Slot_inst_encode, 0, 0, Opcode_l16ui_Slot_xt_flix64_slot0_encode, Opcode_l16ui_Slot_xt_flix64_slot0_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { - Opcode_l16si_Slot_inst_encode, 0, 0, Opcode_l16si_Slot_xt_flix64_slot0_encode, Opcode_l16si_Slot_xt_flix64_slot0_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { - Opcode_l32i_Slot_inst_encode, 0, 0, Opcode_l32i_Slot_xt_flix64_slot0_encode, Opcode_l32i_Slot_xt_flix64_slot0_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { - Opcode_l32r_Slot_inst_encode, 0, 0, Opcode_l32r_Slot_xt_flix64_slot0_encode, Opcode_l32r_Slot_xt_flix64_slot0_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { - Opcode_l8ui_Slot_inst_encode, 0, 0, Opcode_l8ui_Slot_xt_flix64_slot0_encode, Opcode_l8ui_Slot_xt_flix64_slot0_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { - Opcode_loop_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { - Opcode_loopnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { - Opcode_loopgtz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { - Opcode_movi_Slot_inst_encode, 0, 0, Opcode_movi_Slot_xt_flix64_slot0_encode, Opcode_movi_Slot_xt_flix64_slot0_encode, Opcode_movi_Slot_xt_flix64_slot1_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { - Opcode_moveqz_Slot_inst_encode, 0, 0, Opcode_moveqz_Slot_xt_flix64_slot0_encode, Opcode_moveqz_Slot_xt_flix64_slot0_encode, Opcode_moveqz_Slot_xt_flix64_slot1_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { - Opcode_movnez_Slot_inst_encode, 0, 0, Opcode_movnez_Slot_xt_flix64_slot0_encode, Opcode_movnez_Slot_xt_flix64_slot0_encode, Opcode_movnez_Slot_xt_flix64_slot1_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { - Opcode_movltz_Slot_inst_encode, 0, 0, Opcode_movltz_Slot_xt_flix64_slot0_encode, Opcode_movltz_Slot_xt_flix64_slot0_encode, Opcode_movltz_Slot_xt_flix64_slot1_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { - Opcode_movgez_Slot_inst_encode, 0, 0, Opcode_movgez_Slot_xt_flix64_slot0_encode, Opcode_movgez_Slot_xt_flix64_slot0_encode, Opcode_movgez_Slot_xt_flix64_slot1_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { - Opcode_neg_Slot_inst_encode, 0, 0, Opcode_neg_Slot_xt_flix64_slot0_encode, Opcode_neg_Slot_xt_flix64_slot0_encode, Opcode_neg_Slot_xt_flix64_slot1_encode, Opcode_neg_Slot_xt_flix64_slot2_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { - Opcode_abs_Slot_inst_encode, 0, 0, Opcode_abs_Slot_xt_flix64_slot0_encode, Opcode_abs_Slot_xt_flix64_slot0_encode, 0, Opcode_abs_Slot_xt_flix64_slot2_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { - Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_xt_flix64_slot0_encode, Opcode_nop_Slot_xt_flix64_slot0_encode, Opcode_nop_Slot_xt_flix64_slot1_encode, Opcode_nop_Slot_xt_flix64_slot2_encode, Opcode_nop_Slot_xt_flix64_slot3_encode -}; - -xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { - Opcode_ret_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { - Opcode_s16i_Slot_inst_encode, 0, 0, Opcode_s16i_Slot_xt_flix64_slot0_encode, Opcode_s16i_Slot_xt_flix64_slot0_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { - Opcode_s32i_Slot_inst_encode, 0, 0, Opcode_s32i_Slot_xt_flix64_slot0_encode, Opcode_s32i_Slot_xt_flix64_slot0_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { - Opcode_s8i_Slot_inst_encode, 0, 0, Opcode_s8i_Slot_xt_flix64_slot0_encode, Opcode_s8i_Slot_xt_flix64_slot0_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { - Opcode_ssr_Slot_inst_encode, 0, 0, Opcode_ssr_Slot_xt_flix64_slot0_encode, Opcode_ssr_Slot_xt_flix64_slot0_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { - Opcode_ssl_Slot_inst_encode, 0, 0, Opcode_ssl_Slot_xt_flix64_slot0_encode, Opcode_ssl_Slot_xt_flix64_slot0_encode, Opcode_ssl_Slot_xt_flix64_slot1_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { - Opcode_ssa8l_Slot_inst_encode, 0, 0, Opcode_ssa8l_Slot_xt_flix64_slot0_encode, Opcode_ssa8l_Slot_xt_flix64_slot0_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { - Opcode_ssa8b_Slot_inst_encode, 0, 0, Opcode_ssa8b_Slot_xt_flix64_slot0_encode, Opcode_ssa8b_Slot_xt_flix64_slot0_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { - Opcode_ssai_Slot_inst_encode, 0, 0, Opcode_ssai_Slot_xt_flix64_slot0_encode, Opcode_ssai_Slot_xt_flix64_slot0_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { - Opcode_sll_Slot_inst_encode, 0, 0, Opcode_sll_Slot_xt_flix64_slot0_encode, Opcode_sll_Slot_xt_flix64_slot0_encode, Opcode_sll_Slot_xt_flix64_slot1_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { - Opcode_src_Slot_inst_encode, 0, 0, Opcode_src_Slot_xt_flix64_slot0_encode, Opcode_src_Slot_xt_flix64_slot0_encode, Opcode_src_Slot_xt_flix64_slot1_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { - Opcode_srl_Slot_inst_encode, 0, 0, Opcode_srl_Slot_xt_flix64_slot0_encode, Opcode_srl_Slot_xt_flix64_slot0_encode, Opcode_srl_Slot_xt_flix64_slot1_encode, Opcode_srl_Slot_xt_flix64_slot2_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { - Opcode_sra_Slot_inst_encode, 0, 0, Opcode_sra_Slot_xt_flix64_slot0_encode, Opcode_sra_Slot_xt_flix64_slot0_encode, Opcode_sra_Slot_xt_flix64_slot1_encode, Opcode_sra_Slot_xt_flix64_slot2_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { - Opcode_slli_Slot_inst_encode, 0, 0, Opcode_slli_Slot_xt_flix64_slot0_encode, Opcode_slli_Slot_xt_flix64_slot0_encode, Opcode_slli_Slot_xt_flix64_slot1_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { - Opcode_srai_Slot_inst_encode, 0, 0, Opcode_srai_Slot_xt_flix64_slot0_encode, Opcode_srai_Slot_xt_flix64_slot0_encode, Opcode_srai_Slot_xt_flix64_slot1_encode, Opcode_srai_Slot_xt_flix64_slot2_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { - Opcode_srli_Slot_inst_encode, 0, 0, Opcode_srli_Slot_xt_flix64_slot0_encode, Opcode_srli_Slot_xt_flix64_slot0_encode, Opcode_srli_Slot_xt_flix64_slot1_encode, Opcode_srli_Slot_xt_flix64_slot2_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { - Opcode_memw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { - Opcode_extw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { - Opcode_isync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { - Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { - Opcode_esync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { - Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { - Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { - Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { - Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { - Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { - Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { - Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { - Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { - Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { - Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { - Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { - Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { - Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { - Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { - Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { - Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { - Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = { - Opcode_rsr_176_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = { - Opcode_rsr_208_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { - Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { - Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { - Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { - Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { - Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { - Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { - Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { - Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { - Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { - Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { - Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { - Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { - Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { - Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { - Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { - Opcode_rsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { - Opcode_wsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { - Opcode_xsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { - Opcode_rsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { - Opcode_wsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { - Opcode_xsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { - Opcode_rsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { - Opcode_wsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { - Opcode_xsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { - Opcode_rsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { - Opcode_wsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { - Opcode_xsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { - Opcode_rsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { - Opcode_wsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { - Opcode_xsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { - Opcode_rsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { - Opcode_wsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { - Opcode_xsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = { - Opcode_rsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = { - Opcode_wsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = { - Opcode_xsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = { - Opcode_rsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = { - Opcode_wsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = { - Opcode_xsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = { - Opcode_rsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = { - Opcode_wsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = { - Opcode_xsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = { - Opcode_rsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = { - Opcode_wsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = { - Opcode_xsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { - Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { - Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { - Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { - Opcode_rsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { - Opcode_wsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { - Opcode_xsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { - Opcode_rsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { - Opcode_wsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { - Opcode_xsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { - Opcode_rsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { - Opcode_wsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { - Opcode_xsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = { - Opcode_rsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = { - Opcode_wsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = { - Opcode_xsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = { - Opcode_rsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = { - Opcode_wsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = { - Opcode_xsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { - Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { - Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { - Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { - Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { - Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { - Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { - Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { - Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { - Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { - Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { - Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { - Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { - Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { - Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { - Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_misc2_encode_fns[] = { - Opcode_rsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_misc2_encode_fns[] = { - Opcode_wsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_misc2_encode_fns[] = { - Opcode_xsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_misc3_encode_fns[] = { - Opcode_rsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_misc3_encode_fns[] = { - Opcode_wsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_misc3_encode_fns[] = { - Opcode_xsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { - Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { - Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { - Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { - Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = { - Opcode_mul_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = { - Opcode_mul_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = { - Opcode_mul_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = { - Opcode_mul_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = { - Opcode_umul_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = { - Opcode_umul_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = { - Opcode_umul_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = { - Opcode_umul_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = { - Opcode_mul_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = { - Opcode_mul_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = { - Opcode_mul_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = { - Opcode_mul_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = { - Opcode_mul_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = { - Opcode_mul_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = { - Opcode_mul_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = { - Opcode_mul_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = { - Opcode_mul_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = { - Opcode_mul_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = { - Opcode_mul_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = { - Opcode_mul_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = { - Opcode_mula_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = { - Opcode_mula_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = { - Opcode_mula_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = { - Opcode_mula_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = { - Opcode_muls_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = { - Opcode_muls_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = { - Opcode_muls_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = { - Opcode_muls_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = { - Opcode_mula_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = { - Opcode_mula_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = { - Opcode_mula_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = { - Opcode_mula_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = { - Opcode_muls_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = { - Opcode_muls_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = { - Opcode_muls_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = { - Opcode_muls_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = { - Opcode_mula_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = { - Opcode_mula_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = { - Opcode_mula_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = { - Opcode_mula_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = { - Opcode_muls_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = { - Opcode_muls_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = { - Opcode_muls_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = { - Opcode_muls_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = { - Opcode_mula_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = { - Opcode_mula_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = { - Opcode_mula_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = { - Opcode_mula_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = { - Opcode_muls_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = { - Opcode_muls_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = { - Opcode_muls_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = { - Opcode_muls_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = { - Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = { - Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = { - Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = { - Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = { - Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = { - Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = { - Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = { - Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = { - Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = { - Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = { - Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = { - Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = { - Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = { - Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = { - Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = { - Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = { - Opcode_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = { - Opcode_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { - Opcode_mul16u_Slot_inst_encode, 0, 0, Opcode_mul16u_Slot_xt_flix64_slot0_encode, Opcode_mul16u_Slot_xt_flix64_slot0_encode, Opcode_mul16u_Slot_xt_flix64_slot1_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { - Opcode_mul16s_Slot_inst_encode, 0, 0, Opcode_mul16s_Slot_xt_flix64_slot0_encode, Opcode_mul16s_Slot_xt_flix64_slot0_encode, Opcode_mul16s_Slot_xt_flix64_slot1_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = { - Opcode_rsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = { - Opcode_wsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = { - Opcode_xsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = { - Opcode_rsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = { - Opcode_wsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = { - Opcode_xsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = { - Opcode_rsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = { - Opcode_wsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = { - Opcode_xsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = { - Opcode_rsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = { - Opcode_wsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = { - Opcode_xsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = { - Opcode_rsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = { - Opcode_wsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = { - Opcode_xsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = { - Opcode_rsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = { - Opcode_wsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = { - Opcode_xsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { - Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { - Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { - Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { - Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { - Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { - Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { - Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { - Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { - Opcode_break_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { - 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { - Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { - Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { - Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { - Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { - Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { - Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { - Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { - Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { - Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { - Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { - Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { - Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { - Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { - Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { - Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { - Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { - Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { - Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { - Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { - Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { - Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { - Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { - Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { - Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { - Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { - Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { - Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { - Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { - Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { - Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { - Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { - Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { - Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { - Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { - Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { - Opcode_wsr_mmid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = { - Opcode_andb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = { - Opcode_andbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = { - Opcode_orb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = { - Opcode_orbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = { - Opcode_xorb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = { - Opcode_any4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = { - Opcode_all4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = { - Opcode_any8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = { - Opcode_all8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = { - Opcode_bf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = { - Opcode_bt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = { - Opcode_movf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = { - Opcode_movt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = { - Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = { - Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = { - Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { - Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { - Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { - Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { - Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { - Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { - Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { - Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { - Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { - Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { - Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { - Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { - Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { - Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { - Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = { - Opcode_ipfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = { - Opcode_ihu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = { - Opcode_iiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { - Opcode_iii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { - Opcode_lict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { - Opcode_licw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { - Opcode_sict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { - Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { - Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { - Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { - Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { - Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { - Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { - Opcode_dii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { - Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { - Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { - Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { - Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = { - Opcode_dpfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = { - Opcode_dhu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = { - Opcode_diu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { - Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { - Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = { - Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = { - Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = { - Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = { - Opcode_rsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = { - Opcode_wsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = { - Opcode_xsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = { - Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = { - Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = { - Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = { - Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = { - Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = { - Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { - Opcode_idtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { - Opcode_pdtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { - Opcode_rdtlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { - Opcode_rdtlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { - Opcode_wdtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { - Opcode_iitlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { - Opcode_pitlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { - Opcode_ritlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { - Opcode_ritlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { - Opcode_witlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = { - Opcode_ldpte_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = { - Opcode_hwwitlba_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = { - Opcode_hwwdtlba_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { - Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { - Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { - Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { - Opcode_clamps_Slot_inst_encode, 0, 0, Opcode_clamps_Slot_xt_flix64_slot0_encode, Opcode_clamps_Slot_xt_flix64_slot0_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { - Opcode_min_Slot_inst_encode, 0, 0, Opcode_min_Slot_xt_flix64_slot0_encode, Opcode_min_Slot_xt_flix64_slot0_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { - Opcode_max_Slot_inst_encode, 0, 0, Opcode_max_Slot_xt_flix64_slot0_encode, Opcode_max_Slot_xt_flix64_slot0_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { - Opcode_minu_Slot_inst_encode, 0, 0, Opcode_minu_Slot_xt_flix64_slot0_encode, Opcode_minu_Slot_xt_flix64_slot0_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { - Opcode_maxu_Slot_inst_encode, 0, 0, Opcode_maxu_Slot_xt_flix64_slot0_encode, Opcode_maxu_Slot_xt_flix64_slot0_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { - Opcode_nsa_Slot_inst_encode, 0, 0, Opcode_nsa_Slot_xt_flix64_slot0_encode, Opcode_nsa_Slot_xt_flix64_slot0_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { - Opcode_nsau_Slot_inst_encode, 0, 0, Opcode_nsau_Slot_xt_flix64_slot0_encode, Opcode_nsau_Slot_xt_flix64_slot0_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { - Opcode_sext_Slot_inst_encode, 0, 0, Opcode_sext_Slot_xt_flix64_slot0_encode, Opcode_sext_Slot_xt_flix64_slot0_encode, Opcode_sext_Slot_xt_flix64_slot1_encode, Opcode_sext_Slot_xt_flix64_slot2_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { - Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { - Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { - Opcode_s32c1i_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { - Opcode_rsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { - Opcode_wsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { - Opcode_xsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = { - Opcode_quou_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = { - Opcode_quos_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = { - Opcode_remu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = { - Opcode_rems_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { - Opcode_mull_Slot_inst_encode, 0, 0, Opcode_mull_Slot_xt_flix64_slot0_encode, Opcode_mull_Slot_xt_flix64_slot0_encode, Opcode_mull_Slot_xt_flix64_slot1_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muluh_encode_fns[] = { - Opcode_muluh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mulsh_encode_fns[] = { - Opcode_mulsh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_fcr_encode_fns[] = { - Opcode_rur_fcr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_fcr_encode_fns[] = { - Opcode_wur_fcr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_fsr_encode_fns[] = { - Opcode_rur_fsr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_fsr_encode_fns[] = { - Opcode_wur_fsr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_add_s_encode_fns[] = { - Opcode_add_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_sub_s_encode_fns[] = { - Opcode_sub_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_s_encode_fns[] = { - Opcode_mul_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_madd_s_encode_fns[] = { - Opcode_madd_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_msub_s_encode_fns[] = { - Opcode_msub_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_movf_s_encode_fns[] = { - Opcode_movf_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_movt_s_encode_fns[] = { - Opcode_movt_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_moveqz_s_encode_fns[] = { - Opcode_moveqz_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_movnez_s_encode_fns[] = { - Opcode_movnez_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_movltz_s_encode_fns[] = { - Opcode_movltz_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_movgez_s_encode_fns[] = { - Opcode_movgez_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_abs_s_encode_fns[] = { - Opcode_abs_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mov_s_encode_fns[] = { - Opcode_mov_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_neg_s_encode_fns[] = { - Opcode_neg_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_un_s_encode_fns[] = { - Opcode_un_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_oeq_s_encode_fns[] = { - Opcode_oeq_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ueq_s_encode_fns[] = { - Opcode_ueq_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_olt_s_encode_fns[] = { - Opcode_olt_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ult_s_encode_fns[] = { - Opcode_ult_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ole_s_encode_fns[] = { - Opcode_ole_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ule_s_encode_fns[] = { - Opcode_ule_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_float_s_encode_fns[] = { - Opcode_float_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ufloat_s_encode_fns[] = { - Opcode_ufloat_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_round_s_encode_fns[] = { - Opcode_round_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ceil_s_encode_fns[] = { - Opcode_ceil_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_floor_s_encode_fns[] = { - Opcode_floor_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_trunc_s_encode_fns[] = { - Opcode_trunc_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_utrunc_s_encode_fns[] = { - Opcode_utrunc_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfr_encode_fns[] = { - Opcode_rfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wfr_encode_fns[] = { - Opcode_wfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_lsi_encode_fns[] = { - Opcode_lsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_lsiu_encode_fns[] = { - Opcode_lsiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_lsx_encode_fns[] = { - Opcode_lsx_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_lsxu_encode_fns[] = { - Opcode_lsxu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ssi_encode_fns[] = { - Opcode_ssi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ssiu_encode_fns[] = { - Opcode_ssiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ssx_encode_fns[] = { - Opcode_ssx_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ssxu_encode_fns[] = { - Opcode_ssxu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_beqz_w18_encode_fns[] = { - 0, 0, 0, 0, 0, 0, 0, Opcode_beqz_w18_Slot_xt_flix64_slot3_encode -}; - -xtensa_opcode_encode_fn Opcode_bnez_w18_encode_fns[] = { - 0, 0, 0, 0, 0, 0, 0, Opcode_bnez_w18_Slot_xt_flix64_slot3_encode -}; - -xtensa_opcode_encode_fn Opcode_bgez_w18_encode_fns[] = { - 0, 0, 0, 0, 0, 0, 0, Opcode_bgez_w18_Slot_xt_flix64_slot3_encode -}; - -xtensa_opcode_encode_fn Opcode_bltz_w18_encode_fns[] = { - 0, 0, 0, 0, 0, 0, 0, Opcode_bltz_w18_Slot_xt_flix64_slot3_encode -}; - -xtensa_opcode_encode_fn Opcode_beqi_w18_encode_fns[] = { - 0, 0, 0, 0, 0, 0, 0, Opcode_beqi_w18_Slot_xt_flix64_slot3_encode -}; - -xtensa_opcode_encode_fn Opcode_bnei_w18_encode_fns[] = { - 0, 0, 0, 0, 0, 0, 0, Opcode_bnei_w18_Slot_xt_flix64_slot3_encode -}; - -xtensa_opcode_encode_fn Opcode_bgei_w18_encode_fns[] = { - 0, 0, 0, 0, 0, 0, 0, Opcode_bgei_w18_Slot_xt_flix64_slot3_encode -}; - -xtensa_opcode_encode_fn Opcode_blti_w18_encode_fns[] = { - 0, 0, 0, 0, 0, 0, 0, Opcode_blti_w18_Slot_xt_flix64_slot3_encode -}; - -xtensa_opcode_encode_fn Opcode_bgeui_w18_encode_fns[] = { - 0, 0, 0, 0, 0, 0, 0, Opcode_bgeui_w18_Slot_xt_flix64_slot3_encode -}; - -xtensa_opcode_encode_fn Opcode_bltui_w18_encode_fns[] = { - 0, 0, 0, 0, 0, 0, 0, Opcode_bltui_w18_Slot_xt_flix64_slot3_encode -}; - -xtensa_opcode_encode_fn Opcode_bbci_w18_encode_fns[] = { - 0, 0, 0, 0, 0, 0, 0, Opcode_bbci_w18_Slot_xt_flix64_slot3_encode -}; - -xtensa_opcode_encode_fn Opcode_bbsi_w18_encode_fns[] = { - 0, 0, 0, 0, 0, 0, 0, Opcode_bbsi_w18_Slot_xt_flix64_slot3_encode -}; - -xtensa_opcode_encode_fn Opcode_beq_w18_encode_fns[] = { - 0, 0, 0, 0, 0, 0, 0, Opcode_beq_w18_Slot_xt_flix64_slot3_encode -}; - -xtensa_opcode_encode_fn Opcode_bne_w18_encode_fns[] = { - 0, 0, 0, 0, 0, 0, 0, Opcode_bne_w18_Slot_xt_flix64_slot3_encode -}; - -xtensa_opcode_encode_fn Opcode_bge_w18_encode_fns[] = { - 0, 0, 0, 0, 0, 0, 0, Opcode_bge_w18_Slot_xt_flix64_slot3_encode -}; - -xtensa_opcode_encode_fn Opcode_blt_w18_encode_fns[] = { - 0, 0, 0, 0, 0, 0, 0, Opcode_blt_w18_Slot_xt_flix64_slot3_encode -}; - -xtensa_opcode_encode_fn Opcode_bgeu_w18_encode_fns[] = { - 0, 0, 0, 0, 0, 0, 0, Opcode_bgeu_w18_Slot_xt_flix64_slot3_encode -}; - -xtensa_opcode_encode_fn Opcode_bltu_w18_encode_fns[] = { - 0, 0, 0, 0, 0, 0, 0, Opcode_bltu_w18_Slot_xt_flix64_slot3_encode -}; - -xtensa_opcode_encode_fn Opcode_bany_w18_encode_fns[] = { - 0, 0, 0, 0, 0, 0, 0, Opcode_bany_w18_Slot_xt_flix64_slot3_encode -}; - -xtensa_opcode_encode_fn Opcode_bnone_w18_encode_fns[] = { - 0, 0, 0, 0, 0, 0, 0, Opcode_bnone_w18_Slot_xt_flix64_slot3_encode -}; - -xtensa_opcode_encode_fn Opcode_ball_w18_encode_fns[] = { - 0, 0, 0, 0, 0, 0, 0, Opcode_ball_w18_Slot_xt_flix64_slot3_encode -}; - -xtensa_opcode_encode_fn Opcode_bnall_w18_encode_fns[] = { - 0, 0, 0, 0, 0, 0, 0, Opcode_bnall_w18_Slot_xt_flix64_slot3_encode -}; - -xtensa_opcode_encode_fn Opcode_bbc_w18_encode_fns[] = { - 0, 0, 0, 0, 0, 0, 0, Opcode_bbc_w18_Slot_xt_flix64_slot3_encode -}; - -xtensa_opcode_encode_fn Opcode_bbs_w18_encode_fns[] = { - 0, 0, 0, 0, 0, 0, 0, Opcode_bbs_w18_Slot_xt_flix64_slot3_encode -}; - - -/* Opcode table. */ - -static xtensa_opcode_internal opcodes[] = { - { "excw", 0 /* xt_iclass_excw */, - 0, - Opcode_excw_encode_fns, 0, 0 }, - { "rfe", 1 /* xt_iclass_rfe */, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfe_encode_fns, 0, 0 }, - { "rfde", 2 /* xt_iclass_rfde */, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfde_encode_fns, 0, 0 }, - { "syscall", 3 /* xt_iclass_syscall */, - 0, - Opcode_syscall_encode_fns, 0, 0 }, - { "simcall", 4 /* xt_iclass_simcall */, - 0, - Opcode_simcall_encode_fns, 0, 0 }, - { "call12", 5 /* xt_iclass_call12 */, - XTENSA_OPCODE_IS_CALL, - Opcode_call12_encode_fns, 0, 0 }, - { "call8", 6 /* xt_iclass_call8 */, - XTENSA_OPCODE_IS_CALL, - Opcode_call8_encode_fns, 0, 0 }, - { "call4", 7 /* xt_iclass_call4 */, - XTENSA_OPCODE_IS_CALL, - Opcode_call4_encode_fns, 0, 0 }, - { "callx12", 8 /* xt_iclass_callx12 */, - XTENSA_OPCODE_IS_CALL, - Opcode_callx12_encode_fns, 0, 0 }, - { "callx8", 9 /* xt_iclass_callx8 */, - XTENSA_OPCODE_IS_CALL, - Opcode_callx8_encode_fns, 0, 0 }, - { "callx4", 10 /* xt_iclass_callx4 */, - XTENSA_OPCODE_IS_CALL, - Opcode_callx4_encode_fns, 0, 0 }, - { "entry", 11 /* xt_iclass_entry */, - 0, - Opcode_entry_encode_fns, 0, 0 }, - { "movsp", 12 /* xt_iclass_movsp */, - 0, - Opcode_movsp_encode_fns, 0, 0 }, - { "rotw", 13 /* xt_iclass_rotw */, - 0, - Opcode_rotw_encode_fns, 0, 0 }, - { "retw", 14 /* xt_iclass_retw */, - XTENSA_OPCODE_IS_JUMP, - Opcode_retw_encode_fns, 0, 0 }, - { "retw.n", 14 /* xt_iclass_retw */, - XTENSA_OPCODE_IS_JUMP, - Opcode_retw_n_encode_fns, 0, 0 }, - { "rfwo", 15 /* xt_iclass_rfwou */, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfwo_encode_fns, 0, 0 }, - { "rfwu", 15 /* xt_iclass_rfwou */, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfwu_encode_fns, 0, 0 }, - { "l32e", 16 /* xt_iclass_l32e */, - 0, - Opcode_l32e_encode_fns, 0, 0 }, - { "s32e", 17 /* xt_iclass_s32e */, - 0, - Opcode_s32e_encode_fns, 0, 0 }, - { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */, - 0, - Opcode_rsr_windowbase_encode_fns, 0, 0 }, - { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */, - 0, - Opcode_wsr_windowbase_encode_fns, 0, 0 }, - { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */, - 0, - Opcode_xsr_windowbase_encode_fns, 0, 0 }, - { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */, - 0, - Opcode_rsr_windowstart_encode_fns, 0, 0 }, - { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */, - 0, - Opcode_wsr_windowstart_encode_fns, 0, 0 }, - { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */, - 0, - Opcode_xsr_windowstart_encode_fns, 0, 0 }, - { "add.n", 24 /* xt_iclass_add.n */, - 0, - Opcode_add_n_encode_fns, 0, 0 }, - { "addi.n", 25 /* xt_iclass_addi.n */, - 0, - Opcode_addi_n_encode_fns, 0, 0 }, - { "beqz.n", 26 /* xt_iclass_bz6 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqz_n_encode_fns, 0, 0 }, - { "bnez.n", 26 /* xt_iclass_bz6 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnez_n_encode_fns, 0, 0 }, - { "ill.n", 27 /* xt_iclass_ill.n */, - 0, - Opcode_ill_n_encode_fns, 0, 0 }, - { "l32i.n", 28 /* xt_iclass_loadi4 */, - 0, - Opcode_l32i_n_encode_fns, 0, 0 }, - { "mov.n", 29 /* xt_iclass_mov.n */, - 0, - Opcode_mov_n_encode_fns, 0, 0 }, - { "movi.n", 30 /* xt_iclass_movi.n */, - 0, - Opcode_movi_n_encode_fns, 0, 0 }, - { "nop.n", 31 /* xt_iclass_nopn */, - 0, - Opcode_nop_n_encode_fns, 0, 0 }, - { "ret.n", 32 /* xt_iclass_retn */, - XTENSA_OPCODE_IS_JUMP, - Opcode_ret_n_encode_fns, 0, 0 }, - { "s32i.n", 33 /* xt_iclass_storei4 */, - 0, - Opcode_s32i_n_encode_fns, 0, 0 }, - { "rur.threadptr", 34 /* rur_threadptr */, - 0, - Opcode_rur_threadptr_encode_fns, 0, 0 }, - { "wur.threadptr", 35 /* wur_threadptr */, - 0, - Opcode_wur_threadptr_encode_fns, 0, 0 }, - { "addi", 36 /* xt_iclass_addi */, - 0, - Opcode_addi_encode_fns, 0, 0 }, - { "addmi", 37 /* xt_iclass_addmi */, - 0, - Opcode_addmi_encode_fns, 0, 0 }, - { "add", 38 /* xt_iclass_addsub */, - 0, - Opcode_add_encode_fns, 0, 0 }, - { "sub", 38 /* xt_iclass_addsub */, - 0, - Opcode_sub_encode_fns, 0, 0 }, - { "addx2", 38 /* xt_iclass_addsub */, - 0, - Opcode_addx2_encode_fns, 0, 0 }, - { "addx4", 38 /* xt_iclass_addsub */, - 0, - Opcode_addx4_encode_fns, 0, 0 }, - { "addx8", 38 /* xt_iclass_addsub */, - 0, - Opcode_addx8_encode_fns, 0, 0 }, - { "subx2", 38 /* xt_iclass_addsub */, - 0, - Opcode_subx2_encode_fns, 0, 0 }, - { "subx4", 38 /* xt_iclass_addsub */, - 0, - Opcode_subx4_encode_fns, 0, 0 }, - { "subx8", 38 /* xt_iclass_addsub */, - 0, - Opcode_subx8_encode_fns, 0, 0 }, - { "and", 39 /* xt_iclass_bit */, - 0, - Opcode_and_encode_fns, 0, 0 }, - { "or", 39 /* xt_iclass_bit */, - 0, - Opcode_or_encode_fns, 0, 0 }, - { "xor", 39 /* xt_iclass_bit */, - 0, - Opcode_xor_encode_fns, 0, 0 }, - { "beqi", 40 /* xt_iclass_bsi8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqi_encode_fns, 0, 0 }, - { "bnei", 40 /* xt_iclass_bsi8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnei_encode_fns, 0, 0 }, - { "bgei", 40 /* xt_iclass_bsi8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgei_encode_fns, 0, 0 }, - { "blti", 40 /* xt_iclass_bsi8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_blti_encode_fns, 0, 0 }, - { "bbci", 41 /* xt_iclass_bsi8b */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbci_encode_fns, 0, 0 }, - { "bbsi", 41 /* xt_iclass_bsi8b */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbsi_encode_fns, 0, 0 }, - { "bgeui", 42 /* xt_iclass_bsi8u */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgeui_encode_fns, 0, 0 }, - { "bltui", 42 /* xt_iclass_bsi8u */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltui_encode_fns, 0, 0 }, - { "beq", 43 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beq_encode_fns, 0, 0 }, - { "bne", 43 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bne_encode_fns, 0, 0 }, - { "bge", 43 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bge_encode_fns, 0, 0 }, - { "blt", 43 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_blt_encode_fns, 0, 0 }, - { "bgeu", 43 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgeu_encode_fns, 0, 0 }, - { "bltu", 43 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltu_encode_fns, 0, 0 }, - { "bany", 43 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bany_encode_fns, 0, 0 }, - { "bnone", 43 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnone_encode_fns, 0, 0 }, - { "ball", 43 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_ball_encode_fns, 0, 0 }, - { "bnall", 43 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnall_encode_fns, 0, 0 }, - { "bbc", 43 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbc_encode_fns, 0, 0 }, - { "bbs", 43 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbs_encode_fns, 0, 0 }, - { "beqz", 44 /* xt_iclass_bsz12 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqz_encode_fns, 0, 0 }, - { "bnez", 44 /* xt_iclass_bsz12 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnez_encode_fns, 0, 0 }, - { "bgez", 44 /* xt_iclass_bsz12 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgez_encode_fns, 0, 0 }, - { "bltz", 44 /* xt_iclass_bsz12 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltz_encode_fns, 0, 0 }, - { "call0", 45 /* xt_iclass_call0 */, - XTENSA_OPCODE_IS_CALL, - Opcode_call0_encode_fns, 0, 0 }, - { "callx0", 46 /* xt_iclass_callx0 */, - XTENSA_OPCODE_IS_CALL, - Opcode_callx0_encode_fns, 0, 0 }, - { "extui", 47 /* xt_iclass_exti */, - 0, - Opcode_extui_encode_fns, 0, 0 }, - { "ill", 48 /* xt_iclass_ill */, - 0, - Opcode_ill_encode_fns, 0, 0 }, - { "j", 49 /* xt_iclass_jump */, - XTENSA_OPCODE_IS_JUMP, - Opcode_j_encode_fns, 0, 0 }, - { "jx", 50 /* xt_iclass_jumpx */, - XTENSA_OPCODE_IS_JUMP, - Opcode_jx_encode_fns, 0, 0 }, - { "l16ui", 51 /* xt_iclass_l16ui */, - 0, - Opcode_l16ui_encode_fns, 0, 0 }, - { "l16si", 52 /* xt_iclass_l16si */, - 0, - Opcode_l16si_encode_fns, 0, 0 }, - { "l32i", 53 /* xt_iclass_l32i */, - 0, - Opcode_l32i_encode_fns, 0, 0 }, - { "l32r", 54 /* xt_iclass_l32r */, - 0, - Opcode_l32r_encode_fns, 0, 0 }, - { "l8ui", 55 /* xt_iclass_l8i */, - 0, - Opcode_l8ui_encode_fns, 0, 0 }, - { "loop", 56 /* xt_iclass_loop */, - XTENSA_OPCODE_IS_LOOP, - Opcode_loop_encode_fns, 0, 0 }, - { "loopnez", 57 /* xt_iclass_loopz */, - XTENSA_OPCODE_IS_LOOP, - Opcode_loopnez_encode_fns, 0, 0 }, - { "loopgtz", 57 /* xt_iclass_loopz */, - XTENSA_OPCODE_IS_LOOP, - Opcode_loopgtz_encode_fns, 0, 0 }, - { "movi", 58 /* xt_iclass_movi */, - 0, - Opcode_movi_encode_fns, 0, 0 }, - { "moveqz", 59 /* xt_iclass_movz */, - 0, - Opcode_moveqz_encode_fns, 0, 0 }, - { "movnez", 59 /* xt_iclass_movz */, - 0, - Opcode_movnez_encode_fns, 0, 0 }, - { "movltz", 59 /* xt_iclass_movz */, - 0, - Opcode_movltz_encode_fns, 0, 0 }, - { "movgez", 59 /* xt_iclass_movz */, - 0, - Opcode_movgez_encode_fns, 0, 0 }, - { "neg", 60 /* xt_iclass_neg */, - 0, - Opcode_neg_encode_fns, 0, 0 }, - { "abs", 60 /* xt_iclass_neg */, - 0, - Opcode_abs_encode_fns, 0, 0 }, - { "nop", 61 /* xt_iclass_nop */, - 0, - Opcode_nop_encode_fns, 0, 0 }, - { "ret", 62 /* xt_iclass_return */, - XTENSA_OPCODE_IS_JUMP, - Opcode_ret_encode_fns, 0, 0 }, - { "s16i", 63 /* xt_iclass_s16i */, - 0, - Opcode_s16i_encode_fns, 0, 0 }, - { "s32i", 64 /* xt_iclass_s32i */, - 0, - Opcode_s32i_encode_fns, 0, 0 }, - { "s8i", 65 /* xt_iclass_s8i */, - 0, - Opcode_s8i_encode_fns, 0, 0 }, - { "ssr", 66 /* xt_iclass_sar */, - 0, - Opcode_ssr_encode_fns, 0, 0 }, - { "ssl", 66 /* xt_iclass_sar */, - 0, - Opcode_ssl_encode_fns, 0, 0 }, - { "ssa8l", 66 /* xt_iclass_sar */, - 0, - Opcode_ssa8l_encode_fns, 0, 0 }, - { "ssa8b", 66 /* xt_iclass_sar */, - 0, - Opcode_ssa8b_encode_fns, 0, 0 }, - { "ssai", 67 /* xt_iclass_sari */, - 0, - Opcode_ssai_encode_fns, 0, 0 }, - { "sll", 68 /* xt_iclass_shifts */, - 0, - Opcode_sll_encode_fns, 0, 0 }, - { "src", 69 /* xt_iclass_shiftst */, - 0, - Opcode_src_encode_fns, 0, 0 }, - { "srl", 70 /* xt_iclass_shiftt */, - 0, - Opcode_srl_encode_fns, 0, 0 }, - { "sra", 70 /* xt_iclass_shiftt */, - 0, - Opcode_sra_encode_fns, 0, 0 }, - { "slli", 71 /* xt_iclass_slli */, - 0, - Opcode_slli_encode_fns, 0, 0 }, - { "srai", 72 /* xt_iclass_srai */, - 0, - Opcode_srai_encode_fns, 0, 0 }, - { "srli", 73 /* xt_iclass_srli */, - 0, - Opcode_srli_encode_fns, 0, 0 }, - { "memw", 74 /* xt_iclass_memw */, - 0, - Opcode_memw_encode_fns, 0, 0 }, - { "extw", 75 /* xt_iclass_extw */, - 0, - Opcode_extw_encode_fns, 0, 0 }, - { "isync", 76 /* xt_iclass_isync */, - 0, - Opcode_isync_encode_fns, 0, 0 }, - { "rsync", 77 /* xt_iclass_sync */, - 0, - Opcode_rsync_encode_fns, 0, 0 }, - { "esync", 77 /* xt_iclass_sync */, - 0, - Opcode_esync_encode_fns, 0, 0 }, - { "dsync", 77 /* xt_iclass_sync */, - 0, - Opcode_dsync_encode_fns, 0, 0 }, - { "rsil", 78 /* xt_iclass_rsil */, - 0, - Opcode_rsil_encode_fns, 0, 0 }, - { "rsr.lend", 79 /* xt_iclass_rsr.lend */, - 0, - Opcode_rsr_lend_encode_fns, 0, 0 }, - { "wsr.lend", 80 /* xt_iclass_wsr.lend */, - 0, - Opcode_wsr_lend_encode_fns, 0, 0 }, - { "xsr.lend", 81 /* xt_iclass_xsr.lend */, - 0, - Opcode_xsr_lend_encode_fns, 0, 0 }, - { "rsr.lcount", 82 /* xt_iclass_rsr.lcount */, - 0, - Opcode_rsr_lcount_encode_fns, 0, 0 }, - { "wsr.lcount", 83 /* xt_iclass_wsr.lcount */, - 0, - Opcode_wsr_lcount_encode_fns, 0, 0 }, - { "xsr.lcount", 84 /* xt_iclass_xsr.lcount */, - 0, - Opcode_xsr_lcount_encode_fns, 0, 0 }, - { "rsr.lbeg", 85 /* xt_iclass_rsr.lbeg */, - 0, - Opcode_rsr_lbeg_encode_fns, 0, 0 }, - { "wsr.lbeg", 86 /* xt_iclass_wsr.lbeg */, - 0, - Opcode_wsr_lbeg_encode_fns, 0, 0 }, - { "xsr.lbeg", 87 /* xt_iclass_xsr.lbeg */, - 0, - Opcode_xsr_lbeg_encode_fns, 0, 0 }, - { "rsr.sar", 88 /* xt_iclass_rsr.sar */, - 0, - Opcode_rsr_sar_encode_fns, 0, 0 }, - { "wsr.sar", 89 /* xt_iclass_wsr.sar */, - 0, - Opcode_wsr_sar_encode_fns, 0, 0 }, - { "xsr.sar", 90 /* xt_iclass_xsr.sar */, - 0, - Opcode_xsr_sar_encode_fns, 0, 0 }, - { "rsr.litbase", 91 /* xt_iclass_rsr.litbase */, - 0, - Opcode_rsr_litbase_encode_fns, 0, 0 }, - { "wsr.litbase", 92 /* xt_iclass_wsr.litbase */, - 0, - Opcode_wsr_litbase_encode_fns, 0, 0 }, - { "xsr.litbase", 93 /* xt_iclass_xsr.litbase */, - 0, - Opcode_xsr_litbase_encode_fns, 0, 0 }, - { "rsr.176", 94 /* xt_iclass_rsr.176 */, - 0, - Opcode_rsr_176_encode_fns, 0, 0 }, - { "rsr.208", 95 /* xt_iclass_rsr.208 */, - 0, - Opcode_rsr_208_encode_fns, 0, 0 }, - { "rsr.ps", 96 /* xt_iclass_rsr.ps */, - 0, - Opcode_rsr_ps_encode_fns, 0, 0 }, - { "wsr.ps", 97 /* xt_iclass_wsr.ps */, - 0, - Opcode_wsr_ps_encode_fns, 0, 0 }, - { "xsr.ps", 98 /* xt_iclass_xsr.ps */, - 0, - Opcode_xsr_ps_encode_fns, 0, 0 }, - { "rsr.epc1", 99 /* xt_iclass_rsr.epc1 */, - 0, - Opcode_rsr_epc1_encode_fns, 0, 0 }, - { "wsr.epc1", 100 /* xt_iclass_wsr.epc1 */, - 0, - Opcode_wsr_epc1_encode_fns, 0, 0 }, - { "xsr.epc1", 101 /* xt_iclass_xsr.epc1 */, - 0, - Opcode_xsr_epc1_encode_fns, 0, 0 }, - { "rsr.excsave1", 102 /* xt_iclass_rsr.excsave1 */, - 0, - Opcode_rsr_excsave1_encode_fns, 0, 0 }, - { "wsr.excsave1", 103 /* xt_iclass_wsr.excsave1 */, - 0, - Opcode_wsr_excsave1_encode_fns, 0, 0 }, - { "xsr.excsave1", 104 /* xt_iclass_xsr.excsave1 */, - 0, - Opcode_xsr_excsave1_encode_fns, 0, 0 }, - { "rsr.epc2", 105 /* xt_iclass_rsr.epc2 */, - 0, - Opcode_rsr_epc2_encode_fns, 0, 0 }, - { "wsr.epc2", 106 /* xt_iclass_wsr.epc2 */, - 0, - Opcode_wsr_epc2_encode_fns, 0, 0 }, - { "xsr.epc2", 107 /* xt_iclass_xsr.epc2 */, - 0, - Opcode_xsr_epc2_encode_fns, 0, 0 }, - { "rsr.excsave2", 108 /* xt_iclass_rsr.excsave2 */, - 0, - Opcode_rsr_excsave2_encode_fns, 0, 0 }, - { "wsr.excsave2", 109 /* xt_iclass_wsr.excsave2 */, - 0, - Opcode_wsr_excsave2_encode_fns, 0, 0 }, - { "xsr.excsave2", 110 /* xt_iclass_xsr.excsave2 */, - 0, - Opcode_xsr_excsave2_encode_fns, 0, 0 }, - { "rsr.epc3", 111 /* xt_iclass_rsr.epc3 */, - 0, - Opcode_rsr_epc3_encode_fns, 0, 0 }, - { "wsr.epc3", 112 /* xt_iclass_wsr.epc3 */, - 0, - Opcode_wsr_epc3_encode_fns, 0, 0 }, - { "xsr.epc3", 113 /* xt_iclass_xsr.epc3 */, - 0, - Opcode_xsr_epc3_encode_fns, 0, 0 }, - { "rsr.excsave3", 114 /* xt_iclass_rsr.excsave3 */, - 0, - Opcode_rsr_excsave3_encode_fns, 0, 0 }, - { "wsr.excsave3", 115 /* xt_iclass_wsr.excsave3 */, - 0, - Opcode_wsr_excsave3_encode_fns, 0, 0 }, - { "xsr.excsave3", 116 /* xt_iclass_xsr.excsave3 */, - 0, - Opcode_xsr_excsave3_encode_fns, 0, 0 }, - { "rsr.epc4", 117 /* xt_iclass_rsr.epc4 */, - 0, - Opcode_rsr_epc4_encode_fns, 0, 0 }, - { "wsr.epc4", 118 /* xt_iclass_wsr.epc4 */, - 0, - Opcode_wsr_epc4_encode_fns, 0, 0 }, - { "xsr.epc4", 119 /* xt_iclass_xsr.epc4 */, - 0, - Opcode_xsr_epc4_encode_fns, 0, 0 }, - { "rsr.excsave4", 120 /* xt_iclass_rsr.excsave4 */, - 0, - Opcode_rsr_excsave4_encode_fns, 0, 0 }, - { "wsr.excsave4", 121 /* xt_iclass_wsr.excsave4 */, - 0, - Opcode_wsr_excsave4_encode_fns, 0, 0 }, - { "xsr.excsave4", 122 /* xt_iclass_xsr.excsave4 */, - 0, - Opcode_xsr_excsave4_encode_fns, 0, 0 }, - { "rsr.epc5", 123 /* xt_iclass_rsr.epc5 */, - 0, - Opcode_rsr_epc5_encode_fns, 0, 0 }, - { "wsr.epc5", 124 /* xt_iclass_wsr.epc5 */, - 0, - Opcode_wsr_epc5_encode_fns, 0, 0 }, - { "xsr.epc5", 125 /* xt_iclass_xsr.epc5 */, - 0, - Opcode_xsr_epc5_encode_fns, 0, 0 }, - { "rsr.excsave5", 126 /* xt_iclass_rsr.excsave5 */, - 0, - Opcode_rsr_excsave5_encode_fns, 0, 0 }, - { "wsr.excsave5", 127 /* xt_iclass_wsr.excsave5 */, - 0, - Opcode_wsr_excsave5_encode_fns, 0, 0 }, - { "xsr.excsave5", 128 /* xt_iclass_xsr.excsave5 */, - 0, - Opcode_xsr_excsave5_encode_fns, 0, 0 }, - { "rsr.epc6", 129 /* xt_iclass_rsr.epc6 */, - 0, - Opcode_rsr_epc6_encode_fns, 0, 0 }, - { "wsr.epc6", 130 /* xt_iclass_wsr.epc6 */, - 0, - Opcode_wsr_epc6_encode_fns, 0, 0 }, - { "xsr.epc6", 131 /* xt_iclass_xsr.epc6 */, - 0, - Opcode_xsr_epc6_encode_fns, 0, 0 }, - { "rsr.excsave6", 132 /* xt_iclass_rsr.excsave6 */, - 0, - Opcode_rsr_excsave6_encode_fns, 0, 0 }, - { "wsr.excsave6", 133 /* xt_iclass_wsr.excsave6 */, - 0, - Opcode_wsr_excsave6_encode_fns, 0, 0 }, - { "xsr.excsave6", 134 /* xt_iclass_xsr.excsave6 */, - 0, - Opcode_xsr_excsave6_encode_fns, 0, 0 }, - { "rsr.epc7", 135 /* xt_iclass_rsr.epc7 */, - 0, - Opcode_rsr_epc7_encode_fns, 0, 0 }, - { "wsr.epc7", 136 /* xt_iclass_wsr.epc7 */, - 0, - Opcode_wsr_epc7_encode_fns, 0, 0 }, - { "xsr.epc7", 137 /* xt_iclass_xsr.epc7 */, - 0, - Opcode_xsr_epc7_encode_fns, 0, 0 }, - { "rsr.excsave7", 138 /* xt_iclass_rsr.excsave7 */, - 0, - Opcode_rsr_excsave7_encode_fns, 0, 0 }, - { "wsr.excsave7", 139 /* xt_iclass_wsr.excsave7 */, - 0, - Opcode_wsr_excsave7_encode_fns, 0, 0 }, - { "xsr.excsave7", 140 /* xt_iclass_xsr.excsave7 */, - 0, - Opcode_xsr_excsave7_encode_fns, 0, 0 }, - { "rsr.eps2", 141 /* xt_iclass_rsr.eps2 */, - 0, - Opcode_rsr_eps2_encode_fns, 0, 0 }, - { "wsr.eps2", 142 /* xt_iclass_wsr.eps2 */, - 0, - Opcode_wsr_eps2_encode_fns, 0, 0 }, - { "xsr.eps2", 143 /* xt_iclass_xsr.eps2 */, - 0, - Opcode_xsr_eps2_encode_fns, 0, 0 }, - { "rsr.eps3", 144 /* xt_iclass_rsr.eps3 */, - 0, - Opcode_rsr_eps3_encode_fns, 0, 0 }, - { "wsr.eps3", 145 /* xt_iclass_wsr.eps3 */, - 0, - Opcode_wsr_eps3_encode_fns, 0, 0 }, - { "xsr.eps3", 146 /* xt_iclass_xsr.eps3 */, - 0, - Opcode_xsr_eps3_encode_fns, 0, 0 }, - { "rsr.eps4", 147 /* xt_iclass_rsr.eps4 */, - 0, - Opcode_rsr_eps4_encode_fns, 0, 0 }, - { "wsr.eps4", 148 /* xt_iclass_wsr.eps4 */, - 0, - Opcode_wsr_eps4_encode_fns, 0, 0 }, - { "xsr.eps4", 149 /* xt_iclass_xsr.eps4 */, - 0, - Opcode_xsr_eps4_encode_fns, 0, 0 }, - { "rsr.eps5", 150 /* xt_iclass_rsr.eps5 */, - 0, - Opcode_rsr_eps5_encode_fns, 0, 0 }, - { "wsr.eps5", 151 /* xt_iclass_wsr.eps5 */, - 0, - Opcode_wsr_eps5_encode_fns, 0, 0 }, - { "xsr.eps5", 152 /* xt_iclass_xsr.eps5 */, - 0, - Opcode_xsr_eps5_encode_fns, 0, 0 }, - { "rsr.eps6", 153 /* xt_iclass_rsr.eps6 */, - 0, - Opcode_rsr_eps6_encode_fns, 0, 0 }, - { "wsr.eps6", 154 /* xt_iclass_wsr.eps6 */, - 0, - Opcode_wsr_eps6_encode_fns, 0, 0 }, - { "xsr.eps6", 155 /* xt_iclass_xsr.eps6 */, - 0, - Opcode_xsr_eps6_encode_fns, 0, 0 }, - { "rsr.eps7", 156 /* xt_iclass_rsr.eps7 */, - 0, - Opcode_rsr_eps7_encode_fns, 0, 0 }, - { "wsr.eps7", 157 /* xt_iclass_wsr.eps7 */, - 0, - Opcode_wsr_eps7_encode_fns, 0, 0 }, - { "xsr.eps7", 158 /* xt_iclass_xsr.eps7 */, - 0, - Opcode_xsr_eps7_encode_fns, 0, 0 }, - { "rsr.excvaddr", 159 /* xt_iclass_rsr.excvaddr */, - 0, - Opcode_rsr_excvaddr_encode_fns, 0, 0 }, - { "wsr.excvaddr", 160 /* xt_iclass_wsr.excvaddr */, - 0, - Opcode_wsr_excvaddr_encode_fns, 0, 0 }, - { "xsr.excvaddr", 161 /* xt_iclass_xsr.excvaddr */, - 0, - Opcode_xsr_excvaddr_encode_fns, 0, 0 }, - { "rsr.depc", 162 /* xt_iclass_rsr.depc */, - 0, - Opcode_rsr_depc_encode_fns, 0, 0 }, - { "wsr.depc", 163 /* xt_iclass_wsr.depc */, - 0, - Opcode_wsr_depc_encode_fns, 0, 0 }, - { "xsr.depc", 164 /* xt_iclass_xsr.depc */, - 0, - Opcode_xsr_depc_encode_fns, 0, 0 }, - { "rsr.exccause", 165 /* xt_iclass_rsr.exccause */, - 0, - Opcode_rsr_exccause_encode_fns, 0, 0 }, - { "wsr.exccause", 166 /* xt_iclass_wsr.exccause */, - 0, - Opcode_wsr_exccause_encode_fns, 0, 0 }, - { "xsr.exccause", 167 /* xt_iclass_xsr.exccause */, - 0, - Opcode_xsr_exccause_encode_fns, 0, 0 }, - { "rsr.misc0", 168 /* xt_iclass_rsr.misc0 */, - 0, - Opcode_rsr_misc0_encode_fns, 0, 0 }, - { "wsr.misc0", 169 /* xt_iclass_wsr.misc0 */, - 0, - Opcode_wsr_misc0_encode_fns, 0, 0 }, - { "xsr.misc0", 170 /* xt_iclass_xsr.misc0 */, - 0, - Opcode_xsr_misc0_encode_fns, 0, 0 }, - { "rsr.misc1", 171 /* xt_iclass_rsr.misc1 */, - 0, - Opcode_rsr_misc1_encode_fns, 0, 0 }, - { "wsr.misc1", 172 /* xt_iclass_wsr.misc1 */, - 0, - Opcode_wsr_misc1_encode_fns, 0, 0 }, - { "xsr.misc1", 173 /* xt_iclass_xsr.misc1 */, - 0, - Opcode_xsr_misc1_encode_fns, 0, 0 }, - { "rsr.misc2", 174 /* xt_iclass_rsr.misc2 */, - 0, - Opcode_rsr_misc2_encode_fns, 0, 0 }, - { "wsr.misc2", 175 /* xt_iclass_wsr.misc2 */, - 0, - Opcode_wsr_misc2_encode_fns, 0, 0 }, - { "xsr.misc2", 176 /* xt_iclass_xsr.misc2 */, - 0, - Opcode_xsr_misc2_encode_fns, 0, 0 }, - { "rsr.misc3", 177 /* xt_iclass_rsr.misc3 */, - 0, - Opcode_rsr_misc3_encode_fns, 0, 0 }, - { "wsr.misc3", 178 /* xt_iclass_wsr.misc3 */, - 0, - Opcode_wsr_misc3_encode_fns, 0, 0 }, - { "xsr.misc3", 179 /* xt_iclass_xsr.misc3 */, - 0, - Opcode_xsr_misc3_encode_fns, 0, 0 }, - { "rsr.prid", 180 /* xt_iclass_rsr.prid */, - 0, - Opcode_rsr_prid_encode_fns, 0, 0 }, - { "rsr.vecbase", 181 /* xt_iclass_rsr.vecbase */, - 0, - Opcode_rsr_vecbase_encode_fns, 0, 0 }, - { "wsr.vecbase", 182 /* xt_iclass_wsr.vecbase */, - 0, - Opcode_wsr_vecbase_encode_fns, 0, 0 }, - { "xsr.vecbase", 183 /* xt_iclass_xsr.vecbase */, - 0, - Opcode_xsr_vecbase_encode_fns, 0, 0 }, - { "mul.aa.ll", 184 /* xt_iclass_mac16_aa */, - 0, - Opcode_mul_aa_ll_encode_fns, 0, 0 }, - { "mul.aa.hl", 184 /* xt_iclass_mac16_aa */, - 0, - Opcode_mul_aa_hl_encode_fns, 0, 0 }, - { "mul.aa.lh", 184 /* xt_iclass_mac16_aa */, - 0, - Opcode_mul_aa_lh_encode_fns, 0, 0 }, - { "mul.aa.hh", 184 /* xt_iclass_mac16_aa */, - 0, - Opcode_mul_aa_hh_encode_fns, 0, 0 }, - { "umul.aa.ll", 184 /* xt_iclass_mac16_aa */, - 0, - Opcode_umul_aa_ll_encode_fns, 0, 0 }, - { "umul.aa.hl", 184 /* xt_iclass_mac16_aa */, - 0, - Opcode_umul_aa_hl_encode_fns, 0, 0 }, - { "umul.aa.lh", 184 /* xt_iclass_mac16_aa */, - 0, - Opcode_umul_aa_lh_encode_fns, 0, 0 }, - { "umul.aa.hh", 184 /* xt_iclass_mac16_aa */, - 0, - Opcode_umul_aa_hh_encode_fns, 0, 0 }, - { "mul.ad.ll", 185 /* xt_iclass_mac16_ad */, - 0, - Opcode_mul_ad_ll_encode_fns, 0, 0 }, - { "mul.ad.hl", 185 /* xt_iclass_mac16_ad */, - 0, - Opcode_mul_ad_hl_encode_fns, 0, 0 }, - { "mul.ad.lh", 185 /* xt_iclass_mac16_ad */, - 0, - Opcode_mul_ad_lh_encode_fns, 0, 0 }, - { "mul.ad.hh", 185 /* xt_iclass_mac16_ad */, - 0, - Opcode_mul_ad_hh_encode_fns, 0, 0 }, - { "mul.da.ll", 186 /* xt_iclass_mac16_da */, - 0, - Opcode_mul_da_ll_encode_fns, 0, 0 }, - { "mul.da.hl", 186 /* xt_iclass_mac16_da */, - 0, - Opcode_mul_da_hl_encode_fns, 0, 0 }, - { "mul.da.lh", 186 /* xt_iclass_mac16_da */, - 0, - Opcode_mul_da_lh_encode_fns, 0, 0 }, - { "mul.da.hh", 186 /* xt_iclass_mac16_da */, - 0, - Opcode_mul_da_hh_encode_fns, 0, 0 }, - { "mul.dd.ll", 187 /* xt_iclass_mac16_dd */, - 0, - Opcode_mul_dd_ll_encode_fns, 0, 0 }, - { "mul.dd.hl", 187 /* xt_iclass_mac16_dd */, - 0, - Opcode_mul_dd_hl_encode_fns, 0, 0 }, - { "mul.dd.lh", 187 /* xt_iclass_mac16_dd */, - 0, - Opcode_mul_dd_lh_encode_fns, 0, 0 }, - { "mul.dd.hh", 187 /* xt_iclass_mac16_dd */, - 0, - Opcode_mul_dd_hh_encode_fns, 0, 0 }, - { "mula.aa.ll", 188 /* xt_iclass_mac16a_aa */, - 0, - Opcode_mula_aa_ll_encode_fns, 0, 0 }, - { "mula.aa.hl", 188 /* xt_iclass_mac16a_aa */, - 0, - Opcode_mula_aa_hl_encode_fns, 0, 0 }, - { "mula.aa.lh", 188 /* xt_iclass_mac16a_aa */, - 0, - Opcode_mula_aa_lh_encode_fns, 0, 0 }, - { "mula.aa.hh", 188 /* xt_iclass_mac16a_aa */, - 0, - Opcode_mula_aa_hh_encode_fns, 0, 0 }, - { "muls.aa.ll", 188 /* xt_iclass_mac16a_aa */, - 0, - Opcode_muls_aa_ll_encode_fns, 0, 0 }, - { "muls.aa.hl", 188 /* xt_iclass_mac16a_aa */, - 0, - Opcode_muls_aa_hl_encode_fns, 0, 0 }, - { "muls.aa.lh", 188 /* xt_iclass_mac16a_aa */, - 0, - Opcode_muls_aa_lh_encode_fns, 0, 0 }, - { "muls.aa.hh", 188 /* xt_iclass_mac16a_aa */, - 0, - Opcode_muls_aa_hh_encode_fns, 0, 0 }, - { "mula.ad.ll", 189 /* xt_iclass_mac16a_ad */, - 0, - Opcode_mula_ad_ll_encode_fns, 0, 0 }, - { "mula.ad.hl", 189 /* xt_iclass_mac16a_ad */, - 0, - Opcode_mula_ad_hl_encode_fns, 0, 0 }, - { "mula.ad.lh", 189 /* xt_iclass_mac16a_ad */, - 0, - Opcode_mula_ad_lh_encode_fns, 0, 0 }, - { "mula.ad.hh", 189 /* xt_iclass_mac16a_ad */, - 0, - Opcode_mula_ad_hh_encode_fns, 0, 0 }, - { "muls.ad.ll", 189 /* xt_iclass_mac16a_ad */, - 0, - Opcode_muls_ad_ll_encode_fns, 0, 0 }, - { "muls.ad.hl", 189 /* xt_iclass_mac16a_ad */, - 0, - Opcode_muls_ad_hl_encode_fns, 0, 0 }, - { "muls.ad.lh", 189 /* xt_iclass_mac16a_ad */, - 0, - Opcode_muls_ad_lh_encode_fns, 0, 0 }, - { "muls.ad.hh", 189 /* xt_iclass_mac16a_ad */, - 0, - Opcode_muls_ad_hh_encode_fns, 0, 0 }, - { "mula.da.ll", 190 /* xt_iclass_mac16a_da */, - 0, - Opcode_mula_da_ll_encode_fns, 0, 0 }, - { "mula.da.hl", 190 /* xt_iclass_mac16a_da */, - 0, - Opcode_mula_da_hl_encode_fns, 0, 0 }, - { "mula.da.lh", 190 /* xt_iclass_mac16a_da */, - 0, - Opcode_mula_da_lh_encode_fns, 0, 0 }, - { "mula.da.hh", 190 /* xt_iclass_mac16a_da */, - 0, - Opcode_mula_da_hh_encode_fns, 0, 0 }, - { "muls.da.ll", 190 /* xt_iclass_mac16a_da */, - 0, - Opcode_muls_da_ll_encode_fns, 0, 0 }, - { "muls.da.hl", 190 /* xt_iclass_mac16a_da */, - 0, - Opcode_muls_da_hl_encode_fns, 0, 0 }, - { "muls.da.lh", 190 /* xt_iclass_mac16a_da */, - 0, - Opcode_muls_da_lh_encode_fns, 0, 0 }, - { "muls.da.hh", 190 /* xt_iclass_mac16a_da */, - 0, - Opcode_muls_da_hh_encode_fns, 0, 0 }, - { "mula.dd.ll", 191 /* xt_iclass_mac16a_dd */, - 0, - Opcode_mula_dd_ll_encode_fns, 0, 0 }, - { "mula.dd.hl", 191 /* xt_iclass_mac16a_dd */, - 0, - Opcode_mula_dd_hl_encode_fns, 0, 0 }, - { "mula.dd.lh", 191 /* xt_iclass_mac16a_dd */, - 0, - Opcode_mula_dd_lh_encode_fns, 0, 0 }, - { "mula.dd.hh", 191 /* xt_iclass_mac16a_dd */, - 0, - Opcode_mula_dd_hh_encode_fns, 0, 0 }, - { "muls.dd.ll", 191 /* xt_iclass_mac16a_dd */, - 0, - Opcode_muls_dd_ll_encode_fns, 0, 0 }, - { "muls.dd.hl", 191 /* xt_iclass_mac16a_dd */, - 0, - Opcode_muls_dd_hl_encode_fns, 0, 0 }, - { "muls.dd.lh", 191 /* xt_iclass_mac16a_dd */, - 0, - Opcode_muls_dd_lh_encode_fns, 0, 0 }, - { "muls.dd.hh", 191 /* xt_iclass_mac16a_dd */, - 0, - Opcode_muls_dd_hh_encode_fns, 0, 0 }, - { "mula.da.ll.lddec", 192 /* xt_iclass_mac16al_da */, - 0, - Opcode_mula_da_ll_lddec_encode_fns, 0, 0 }, - { "mula.da.ll.ldinc", 192 /* xt_iclass_mac16al_da */, - 0, - Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 }, - { "mula.da.hl.lddec", 192 /* xt_iclass_mac16al_da */, - 0, - Opcode_mula_da_hl_lddec_encode_fns, 0, 0 }, - { "mula.da.hl.ldinc", 192 /* xt_iclass_mac16al_da */, - 0, - Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 }, - { "mula.da.lh.lddec", 192 /* xt_iclass_mac16al_da */, - 0, - Opcode_mula_da_lh_lddec_encode_fns, 0, 0 }, - { "mula.da.lh.ldinc", 192 /* xt_iclass_mac16al_da */, - 0, - Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 }, - { "mula.da.hh.lddec", 192 /* xt_iclass_mac16al_da */, - 0, - Opcode_mula_da_hh_lddec_encode_fns, 0, 0 }, - { "mula.da.hh.ldinc", 192 /* xt_iclass_mac16al_da */, - 0, - Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 }, - { "mula.dd.ll.lddec", 193 /* xt_iclass_mac16al_dd */, - 0, - Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 }, - { "mula.dd.ll.ldinc", 193 /* xt_iclass_mac16al_dd */, - 0, - Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 }, - { "mula.dd.hl.lddec", 193 /* xt_iclass_mac16al_dd */, - 0, - Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 }, - { "mula.dd.hl.ldinc", 193 /* xt_iclass_mac16al_dd */, - 0, - Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 }, - { "mula.dd.lh.lddec", 193 /* xt_iclass_mac16al_dd */, - 0, - Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 }, - { "mula.dd.lh.ldinc", 193 /* xt_iclass_mac16al_dd */, - 0, - Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 }, - { "mula.dd.hh.lddec", 193 /* xt_iclass_mac16al_dd */, - 0, - Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 }, - { "mula.dd.hh.ldinc", 193 /* xt_iclass_mac16al_dd */, - 0, - Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 }, - { "lddec", 194 /* xt_iclass_mac16_l */, - 0, - Opcode_lddec_encode_fns, 0, 0 }, - { "ldinc", 194 /* xt_iclass_mac16_l */, - 0, - Opcode_ldinc_encode_fns, 0, 0 }, - { "mul16u", 195 /* xt_iclass_mul16 */, - 0, - Opcode_mul16u_encode_fns, 0, 0 }, - { "mul16s", 195 /* xt_iclass_mul16 */, - 0, - Opcode_mul16s_encode_fns, 0, 0 }, - { "rsr.m0", 196 /* xt_iclass_rsr.m0 */, - 0, - Opcode_rsr_m0_encode_fns, 0, 0 }, - { "wsr.m0", 197 /* xt_iclass_wsr.m0 */, - 0, - Opcode_wsr_m0_encode_fns, 0, 0 }, - { "xsr.m0", 198 /* xt_iclass_xsr.m0 */, - 0, - Opcode_xsr_m0_encode_fns, 0, 0 }, - { "rsr.m1", 199 /* xt_iclass_rsr.m1 */, - 0, - Opcode_rsr_m1_encode_fns, 0, 0 }, - { "wsr.m1", 200 /* xt_iclass_wsr.m1 */, - 0, - Opcode_wsr_m1_encode_fns, 0, 0 }, - { "xsr.m1", 201 /* xt_iclass_xsr.m1 */, - 0, - Opcode_xsr_m1_encode_fns, 0, 0 }, - { "rsr.m2", 202 /* xt_iclass_rsr.m2 */, - 0, - Opcode_rsr_m2_encode_fns, 0, 0 }, - { "wsr.m2", 203 /* xt_iclass_wsr.m2 */, - 0, - Opcode_wsr_m2_encode_fns, 0, 0 }, - { "xsr.m2", 204 /* xt_iclass_xsr.m2 */, - 0, - Opcode_xsr_m2_encode_fns, 0, 0 }, - { "rsr.m3", 205 /* xt_iclass_rsr.m3 */, - 0, - Opcode_rsr_m3_encode_fns, 0, 0 }, - { "wsr.m3", 206 /* xt_iclass_wsr.m3 */, - 0, - Opcode_wsr_m3_encode_fns, 0, 0 }, - { "xsr.m3", 207 /* xt_iclass_xsr.m3 */, - 0, - Opcode_xsr_m3_encode_fns, 0, 0 }, - { "rsr.acclo", 208 /* xt_iclass_rsr.acclo */, - 0, - Opcode_rsr_acclo_encode_fns, 0, 0 }, - { "wsr.acclo", 209 /* xt_iclass_wsr.acclo */, - 0, - Opcode_wsr_acclo_encode_fns, 0, 0 }, - { "xsr.acclo", 210 /* xt_iclass_xsr.acclo */, - 0, - Opcode_xsr_acclo_encode_fns, 0, 0 }, - { "rsr.acchi", 211 /* xt_iclass_rsr.acchi */, - 0, - Opcode_rsr_acchi_encode_fns, 0, 0 }, - { "wsr.acchi", 212 /* xt_iclass_wsr.acchi */, - 0, - Opcode_wsr_acchi_encode_fns, 0, 0 }, - { "xsr.acchi", 213 /* xt_iclass_xsr.acchi */, - 0, - Opcode_xsr_acchi_encode_fns, 0, 0 }, - { "rfi", 214 /* xt_iclass_rfi */, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfi_encode_fns, 0, 0 }, - { "waiti", 215 /* xt_iclass_wait */, - 0, - Opcode_waiti_encode_fns, 0, 0 }, - { "rsr.interrupt", 216 /* xt_iclass_rsr.interrupt */, - 0, - Opcode_rsr_interrupt_encode_fns, 0, 0 }, - { "wsr.intset", 217 /* xt_iclass_wsr.intset */, - 0, - Opcode_wsr_intset_encode_fns, 0, 0 }, - { "wsr.intclear", 218 /* xt_iclass_wsr.intclear */, - 0, - Opcode_wsr_intclear_encode_fns, 0, 0 }, - { "rsr.intenable", 219 /* xt_iclass_rsr.intenable */, - 0, - Opcode_rsr_intenable_encode_fns, 0, 0 }, - { "wsr.intenable", 220 /* xt_iclass_wsr.intenable */, - 0, - Opcode_wsr_intenable_encode_fns, 0, 0 }, - { "xsr.intenable", 221 /* xt_iclass_xsr.intenable */, - 0, - Opcode_xsr_intenable_encode_fns, 0, 0 }, - { "break", 222 /* xt_iclass_break */, - 0, - Opcode_break_encode_fns, 0, 0 }, - { "break.n", 223 /* xt_iclass_break.n */, - 0, - Opcode_break_n_encode_fns, 0, 0 }, - { "rsr.dbreaka0", 224 /* xt_iclass_rsr.dbreaka0 */, - 0, - Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, - { "wsr.dbreaka0", 225 /* xt_iclass_wsr.dbreaka0 */, - 0, - Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, - { "xsr.dbreaka0", 226 /* xt_iclass_xsr.dbreaka0 */, - 0, - Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, - { "rsr.dbreakc0", 227 /* xt_iclass_rsr.dbreakc0 */, - 0, - Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, - { "wsr.dbreakc0", 228 /* xt_iclass_wsr.dbreakc0 */, - 0, - Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, - { "xsr.dbreakc0", 229 /* xt_iclass_xsr.dbreakc0 */, - 0, - Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, - { "rsr.dbreaka1", 230 /* xt_iclass_rsr.dbreaka1 */, - 0, - Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, - { "wsr.dbreaka1", 231 /* xt_iclass_wsr.dbreaka1 */, - 0, - Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, - { "xsr.dbreaka1", 232 /* xt_iclass_xsr.dbreaka1 */, - 0, - Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, - { "rsr.dbreakc1", 233 /* xt_iclass_rsr.dbreakc1 */, - 0, - Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, - { "wsr.dbreakc1", 234 /* xt_iclass_wsr.dbreakc1 */, - 0, - Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, - { "xsr.dbreakc1", 235 /* xt_iclass_xsr.dbreakc1 */, - 0, - Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, - { "rsr.ibreaka0", 236 /* xt_iclass_rsr.ibreaka0 */, - 0, - Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, - { "wsr.ibreaka0", 237 /* xt_iclass_wsr.ibreaka0 */, - 0, - Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, - { "xsr.ibreaka0", 238 /* xt_iclass_xsr.ibreaka0 */, - 0, - Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, - { "rsr.ibreaka1", 239 /* xt_iclass_rsr.ibreaka1 */, - 0, - Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, - { "wsr.ibreaka1", 240 /* xt_iclass_wsr.ibreaka1 */, - 0, - Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, - { "xsr.ibreaka1", 241 /* xt_iclass_xsr.ibreaka1 */, - 0, - Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, - { "rsr.ibreakenable", 242 /* xt_iclass_rsr.ibreakenable */, - 0, - Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, - { "wsr.ibreakenable", 243 /* xt_iclass_wsr.ibreakenable */, - 0, - Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, - { "xsr.ibreakenable", 244 /* xt_iclass_xsr.ibreakenable */, - 0, - Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, - { "rsr.debugcause", 245 /* xt_iclass_rsr.debugcause */, - 0, - Opcode_rsr_debugcause_encode_fns, 0, 0 }, - { "wsr.debugcause", 246 /* xt_iclass_wsr.debugcause */, - 0, - Opcode_wsr_debugcause_encode_fns, 0, 0 }, - { "xsr.debugcause", 247 /* xt_iclass_xsr.debugcause */, - 0, - Opcode_xsr_debugcause_encode_fns, 0, 0 }, - { "rsr.icount", 248 /* xt_iclass_rsr.icount */, - 0, - Opcode_rsr_icount_encode_fns, 0, 0 }, - { "wsr.icount", 249 /* xt_iclass_wsr.icount */, - 0, - Opcode_wsr_icount_encode_fns, 0, 0 }, - { "xsr.icount", 250 /* xt_iclass_xsr.icount */, - 0, - Opcode_xsr_icount_encode_fns, 0, 0 }, - { "rsr.icountlevel", 251 /* xt_iclass_rsr.icountlevel */, - 0, - Opcode_rsr_icountlevel_encode_fns, 0, 0 }, - { "wsr.icountlevel", 252 /* xt_iclass_wsr.icountlevel */, - 0, - Opcode_wsr_icountlevel_encode_fns, 0, 0 }, - { "xsr.icountlevel", 253 /* xt_iclass_xsr.icountlevel */, - 0, - Opcode_xsr_icountlevel_encode_fns, 0, 0 }, - { "rsr.ddr", 254 /* xt_iclass_rsr.ddr */, - 0, - Opcode_rsr_ddr_encode_fns, 0, 0 }, - { "wsr.ddr", 255 /* xt_iclass_wsr.ddr */, - 0, - Opcode_wsr_ddr_encode_fns, 0, 0 }, - { "xsr.ddr", 256 /* xt_iclass_xsr.ddr */, - 0, - Opcode_xsr_ddr_encode_fns, 0, 0 }, - { "rfdo", 257 /* xt_iclass_rfdo */, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfdo_encode_fns, 0, 0 }, - { "rfdd", 258 /* xt_iclass_rfdd */, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfdd_encode_fns, 0, 0 }, - { "wsr.mmid", 259 /* xt_iclass_wsr.mmid */, - 0, - Opcode_wsr_mmid_encode_fns, 0, 0 }, - { "andb", 260 /* xt_iclass_bbool1 */, - 0, - Opcode_andb_encode_fns, 0, 0 }, - { "andbc", 260 /* xt_iclass_bbool1 */, - 0, - Opcode_andbc_encode_fns, 0, 0 }, - { "orb", 260 /* xt_iclass_bbool1 */, - 0, - Opcode_orb_encode_fns, 0, 0 }, - { "orbc", 260 /* xt_iclass_bbool1 */, - 0, - Opcode_orbc_encode_fns, 0, 0 }, - { "xorb", 260 /* xt_iclass_bbool1 */, - 0, - Opcode_xorb_encode_fns, 0, 0 }, - { "any4", 261 /* xt_iclass_bbool4 */, - 0, - Opcode_any4_encode_fns, 0, 0 }, - { "all4", 261 /* xt_iclass_bbool4 */, - 0, - Opcode_all4_encode_fns, 0, 0 }, - { "any8", 262 /* xt_iclass_bbool8 */, - 0, - Opcode_any8_encode_fns, 0, 0 }, - { "all8", 262 /* xt_iclass_bbool8 */, - 0, - Opcode_all8_encode_fns, 0, 0 }, - { "bf", 263 /* xt_iclass_bbranch */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bf_encode_fns, 0, 0 }, - { "bt", 263 /* xt_iclass_bbranch */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bt_encode_fns, 0, 0 }, - { "movf", 264 /* xt_iclass_bmove */, - 0, - Opcode_movf_encode_fns, 0, 0 }, - { "movt", 264 /* xt_iclass_bmove */, - 0, - Opcode_movt_encode_fns, 0, 0 }, - { "rsr.br", 265 /* xt_iclass_RSR.BR */, - 0, - Opcode_rsr_br_encode_fns, 0, 0 }, - { "wsr.br", 266 /* xt_iclass_WSR.BR */, - 0, - Opcode_wsr_br_encode_fns, 0, 0 }, - { "xsr.br", 267 /* xt_iclass_XSR.BR */, - 0, - Opcode_xsr_br_encode_fns, 0, 0 }, - { "rsr.ccount", 268 /* xt_iclass_rsr.ccount */, - 0, - Opcode_rsr_ccount_encode_fns, 0, 0 }, - { "wsr.ccount", 269 /* xt_iclass_wsr.ccount */, - 0, - Opcode_wsr_ccount_encode_fns, 0, 0 }, - { "xsr.ccount", 270 /* xt_iclass_xsr.ccount */, - 0, - Opcode_xsr_ccount_encode_fns, 0, 0 }, - { "rsr.ccompare0", 271 /* xt_iclass_rsr.ccompare0 */, - 0, - Opcode_rsr_ccompare0_encode_fns, 0, 0 }, - { "wsr.ccompare0", 272 /* xt_iclass_wsr.ccompare0 */, - 0, - Opcode_wsr_ccompare0_encode_fns, 0, 0 }, - { "xsr.ccompare0", 273 /* xt_iclass_xsr.ccompare0 */, - 0, - Opcode_xsr_ccompare0_encode_fns, 0, 0 }, - { "rsr.ccompare1", 274 /* xt_iclass_rsr.ccompare1 */, - 0, - Opcode_rsr_ccompare1_encode_fns, 0, 0 }, - { "wsr.ccompare1", 275 /* xt_iclass_wsr.ccompare1 */, - 0, - Opcode_wsr_ccompare1_encode_fns, 0, 0 }, - { "xsr.ccompare1", 276 /* xt_iclass_xsr.ccompare1 */, - 0, - Opcode_xsr_ccompare1_encode_fns, 0, 0 }, - { "rsr.ccompare2", 277 /* xt_iclass_rsr.ccompare2 */, - 0, - Opcode_rsr_ccompare2_encode_fns, 0, 0 }, - { "wsr.ccompare2", 278 /* xt_iclass_wsr.ccompare2 */, - 0, - Opcode_wsr_ccompare2_encode_fns, 0, 0 }, - { "xsr.ccompare2", 279 /* xt_iclass_xsr.ccompare2 */, - 0, - Opcode_xsr_ccompare2_encode_fns, 0, 0 }, - { "ipf", 280 /* xt_iclass_icache */, - 0, - Opcode_ipf_encode_fns, 0, 0 }, - { "ihi", 280 /* xt_iclass_icache */, - 0, - Opcode_ihi_encode_fns, 0, 0 }, - { "ipfl", 281 /* xt_iclass_icache_lock */, - 0, - Opcode_ipfl_encode_fns, 0, 0 }, - { "ihu", 281 /* xt_iclass_icache_lock */, - 0, - Opcode_ihu_encode_fns, 0, 0 }, - { "iiu", 281 /* xt_iclass_icache_lock */, - 0, - Opcode_iiu_encode_fns, 0, 0 }, - { "iii", 282 /* xt_iclass_icache_inv */, - 0, - Opcode_iii_encode_fns, 0, 0 }, - { "lict", 283 /* xt_iclass_licx */, - 0, - Opcode_lict_encode_fns, 0, 0 }, - { "licw", 283 /* xt_iclass_licx */, - 0, - Opcode_licw_encode_fns, 0, 0 }, - { "sict", 284 /* xt_iclass_sicx */, - 0, - Opcode_sict_encode_fns, 0, 0 }, - { "sicw", 284 /* xt_iclass_sicx */, - 0, - Opcode_sicw_encode_fns, 0, 0 }, - { "dhwb", 285 /* xt_iclass_dcache */, - 0, - Opcode_dhwb_encode_fns, 0, 0 }, - { "dhwbi", 285 /* xt_iclass_dcache */, - 0, - Opcode_dhwbi_encode_fns, 0, 0 }, - { "diwb", 286 /* xt_iclass_dcache_ind */, - 0, - Opcode_diwb_encode_fns, 0, 0 }, - { "diwbi", 286 /* xt_iclass_dcache_ind */, - 0, - Opcode_diwbi_encode_fns, 0, 0 }, - { "dhi", 287 /* xt_iclass_dcache_inv */, - 0, - Opcode_dhi_encode_fns, 0, 0 }, - { "dii", 287 /* xt_iclass_dcache_inv */, - 0, - Opcode_dii_encode_fns, 0, 0 }, - { "dpfr", 288 /* xt_iclass_dpf */, - 0, - Opcode_dpfr_encode_fns, 0, 0 }, - { "dpfw", 288 /* xt_iclass_dpf */, - 0, - Opcode_dpfw_encode_fns, 0, 0 }, - { "dpfro", 288 /* xt_iclass_dpf */, - 0, - Opcode_dpfro_encode_fns, 0, 0 }, - { "dpfwo", 288 /* xt_iclass_dpf */, - 0, - Opcode_dpfwo_encode_fns, 0, 0 }, - { "dpfl", 289 /* xt_iclass_dcache_lock */, - 0, - Opcode_dpfl_encode_fns, 0, 0 }, - { "dhu", 289 /* xt_iclass_dcache_lock */, - 0, - Opcode_dhu_encode_fns, 0, 0 }, - { "diu", 289 /* xt_iclass_dcache_lock */, - 0, - Opcode_diu_encode_fns, 0, 0 }, - { "sdct", 290 /* xt_iclass_sdct */, - 0, - Opcode_sdct_encode_fns, 0, 0 }, - { "ldct", 291 /* xt_iclass_ldct */, - 0, - Opcode_ldct_encode_fns, 0, 0 }, - { "wsr.ptevaddr", 292 /* xt_iclass_wsr.ptevaddr */, - 0, - Opcode_wsr_ptevaddr_encode_fns, 0, 0 }, - { "rsr.ptevaddr", 293 /* xt_iclass_rsr.ptevaddr */, - 0, - Opcode_rsr_ptevaddr_encode_fns, 0, 0 }, - { "xsr.ptevaddr", 294 /* xt_iclass_xsr.ptevaddr */, - 0, - Opcode_xsr_ptevaddr_encode_fns, 0, 0 }, - { "rsr.rasid", 295 /* xt_iclass_rsr.rasid */, - 0, - Opcode_rsr_rasid_encode_fns, 0, 0 }, - { "wsr.rasid", 296 /* xt_iclass_wsr.rasid */, - 0, - Opcode_wsr_rasid_encode_fns, 0, 0 }, - { "xsr.rasid", 297 /* xt_iclass_xsr.rasid */, - 0, - Opcode_xsr_rasid_encode_fns, 0, 0 }, - { "rsr.itlbcfg", 298 /* xt_iclass_rsr.itlbcfg */, - 0, - Opcode_rsr_itlbcfg_encode_fns, 0, 0 }, - { "wsr.itlbcfg", 299 /* xt_iclass_wsr.itlbcfg */, - 0, - Opcode_wsr_itlbcfg_encode_fns, 0, 0 }, - { "xsr.itlbcfg", 300 /* xt_iclass_xsr.itlbcfg */, - 0, - Opcode_xsr_itlbcfg_encode_fns, 0, 0 }, - { "rsr.dtlbcfg", 301 /* xt_iclass_rsr.dtlbcfg */, - 0, - Opcode_rsr_dtlbcfg_encode_fns, 0, 0 }, - { "wsr.dtlbcfg", 302 /* xt_iclass_wsr.dtlbcfg */, - 0, - Opcode_wsr_dtlbcfg_encode_fns, 0, 0 }, - { "xsr.dtlbcfg", 303 /* xt_iclass_xsr.dtlbcfg */, - 0, - Opcode_xsr_dtlbcfg_encode_fns, 0, 0 }, - { "idtlb", 304 /* xt_iclass_idtlb */, - 0, - Opcode_idtlb_encode_fns, 0, 0 }, - { "pdtlb", 305 /* xt_iclass_rdtlb */, - 0, - Opcode_pdtlb_encode_fns, 0, 0 }, - { "rdtlb0", 305 /* xt_iclass_rdtlb */, - 0, - Opcode_rdtlb0_encode_fns, 0, 0 }, - { "rdtlb1", 305 /* xt_iclass_rdtlb */, - 0, - Opcode_rdtlb1_encode_fns, 0, 0 }, - { "wdtlb", 306 /* xt_iclass_wdtlb */, - 0, - Opcode_wdtlb_encode_fns, 0, 0 }, - { "iitlb", 307 /* xt_iclass_iitlb */, - 0, - Opcode_iitlb_encode_fns, 0, 0 }, - { "pitlb", 308 /* xt_iclass_ritlb */, - 0, - Opcode_pitlb_encode_fns, 0, 0 }, - { "ritlb0", 308 /* xt_iclass_ritlb */, - 0, - Opcode_ritlb0_encode_fns, 0, 0 }, - { "ritlb1", 308 /* xt_iclass_ritlb */, - 0, - Opcode_ritlb1_encode_fns, 0, 0 }, - { "witlb", 309 /* xt_iclass_witlb */, - 0, - Opcode_witlb_encode_fns, 0, 0 }, - { "ldpte", 310 /* xt_iclass_ldpte */, - 0, - Opcode_ldpte_encode_fns, 0, 0 }, - { "hwwitlba", 311 /* xt_iclass_hwwitlba */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_hwwitlba_encode_fns, 0, 0 }, - { "hwwdtlba", 312 /* xt_iclass_hwwdtlba */, - 0, - Opcode_hwwdtlba_encode_fns, 0, 0 }, - { "rsr.cpenable", 313 /* xt_iclass_rsr.cpenable */, - 0, - Opcode_rsr_cpenable_encode_fns, 0, 0 }, - { "wsr.cpenable", 314 /* xt_iclass_wsr.cpenable */, - 0, - Opcode_wsr_cpenable_encode_fns, 0, 0 }, - { "xsr.cpenable", 315 /* xt_iclass_xsr.cpenable */, - 0, - Opcode_xsr_cpenable_encode_fns, 0, 0 }, - { "clamps", 316 /* xt_iclass_clamp */, - 0, - Opcode_clamps_encode_fns, 0, 0 }, - { "min", 317 /* xt_iclass_minmax */, - 0, - Opcode_min_encode_fns, 0, 0 }, - { "max", 317 /* xt_iclass_minmax */, - 0, - Opcode_max_encode_fns, 0, 0 }, - { "minu", 317 /* xt_iclass_minmax */, - 0, - Opcode_minu_encode_fns, 0, 0 }, - { "maxu", 317 /* xt_iclass_minmax */, - 0, - Opcode_maxu_encode_fns, 0, 0 }, - { "nsa", 318 /* xt_iclass_nsa */, - 0, - Opcode_nsa_encode_fns, 0, 0 }, - { "nsau", 318 /* xt_iclass_nsa */, - 0, - Opcode_nsau_encode_fns, 0, 0 }, - { "sext", 319 /* xt_iclass_sx */, - 0, - Opcode_sext_encode_fns, 0, 0 }, - { "l32ai", 320 /* xt_iclass_l32ai */, - 0, - Opcode_l32ai_encode_fns, 0, 0 }, - { "s32ri", 321 /* xt_iclass_s32ri */, - 0, - Opcode_s32ri_encode_fns, 0, 0 }, - { "s32c1i", 322 /* xt_iclass_s32c1i */, - 0, - Opcode_s32c1i_encode_fns, 0, 0 }, - { "rsr.scompare1", 323 /* xt_iclass_rsr.scompare1 */, - 0, - Opcode_rsr_scompare1_encode_fns, 0, 0 }, - { "wsr.scompare1", 324 /* xt_iclass_wsr.scompare1 */, - 0, - Opcode_wsr_scompare1_encode_fns, 0, 0 }, - { "xsr.scompare1", 325 /* xt_iclass_xsr.scompare1 */, - 0, - Opcode_xsr_scompare1_encode_fns, 0, 0 }, - { "quou", 326 /* xt_iclass_div */, - 0, - Opcode_quou_encode_fns, 0, 0 }, - { "quos", 326 /* xt_iclass_div */, - 0, - Opcode_quos_encode_fns, 0, 0 }, - { "remu", 326 /* xt_iclass_div */, - 0, - Opcode_remu_encode_fns, 0, 0 }, - { "rems", 326 /* xt_iclass_div */, - 0, - Opcode_rems_encode_fns, 0, 0 }, - { "mull", 327 /* xt_mul32 */, - 0, - Opcode_mull_encode_fns, 0, 0 }, - { "muluh", 327 /* xt_mul32 */, - 0, - Opcode_muluh_encode_fns, 0, 0 }, - { "mulsh", 327 /* xt_mul32 */, - 0, - Opcode_mulsh_encode_fns, 0, 0 }, - { "rur.fcr", 328 /* rur_fcr */, - 0, - Opcode_rur_fcr_encode_fns, 0, 0 }, - { "wur.fcr", 329 /* wur_fcr */, - 0, - Opcode_wur_fcr_encode_fns, 0, 0 }, - { "rur.fsr", 330 /* rur_fsr */, - 0, - Opcode_rur_fsr_encode_fns, 0, 0 }, - { "wur.fsr", 331 /* wur_fsr */, - 0, - Opcode_wur_fsr_encode_fns, 0, 0 }, - { "add.s", 332 /* fp */, - 0, - Opcode_add_s_encode_fns, 0, 0 }, - { "sub.s", 332 /* fp */, - 0, - Opcode_sub_s_encode_fns, 0, 0 }, - { "mul.s", 332 /* fp */, - 0, - Opcode_mul_s_encode_fns, 0, 0 }, - { "madd.s", 333 /* fp_mac */, - 0, - Opcode_madd_s_encode_fns, 0, 0 }, - { "msub.s", 333 /* fp_mac */, - 0, - Opcode_msub_s_encode_fns, 0, 0 }, - { "movf.s", 334 /* fp_cmov */, - 0, - Opcode_movf_s_encode_fns, 0, 0 }, - { "movt.s", 334 /* fp_cmov */, - 0, - Opcode_movt_s_encode_fns, 0, 0 }, - { "moveqz.s", 335 /* fp_mov */, - 0, - Opcode_moveqz_s_encode_fns, 0, 0 }, - { "movnez.s", 335 /* fp_mov */, - 0, - Opcode_movnez_s_encode_fns, 0, 0 }, - { "movltz.s", 335 /* fp_mov */, - 0, - Opcode_movltz_s_encode_fns, 0, 0 }, - { "movgez.s", 335 /* fp_mov */, - 0, - Opcode_movgez_s_encode_fns, 0, 0 }, - { "abs.s", 336 /* fp_mov2 */, - 0, - Opcode_abs_s_encode_fns, 0, 0 }, - { "mov.s", 336 /* fp_mov2 */, - 0, - Opcode_mov_s_encode_fns, 0, 0 }, - { "neg.s", 336 /* fp_mov2 */, - 0, - Opcode_neg_s_encode_fns, 0, 0 }, - { "un.s", 337 /* fp_cmp */, - 0, - Opcode_un_s_encode_fns, 0, 0 }, - { "oeq.s", 337 /* fp_cmp */, - 0, - Opcode_oeq_s_encode_fns, 0, 0 }, - { "ueq.s", 337 /* fp_cmp */, - 0, - Opcode_ueq_s_encode_fns, 0, 0 }, - { "olt.s", 337 /* fp_cmp */, - 0, - Opcode_olt_s_encode_fns, 0, 0 }, - { "ult.s", 337 /* fp_cmp */, - 0, - Opcode_ult_s_encode_fns, 0, 0 }, - { "ole.s", 337 /* fp_cmp */, - 0, - Opcode_ole_s_encode_fns, 0, 0 }, - { "ule.s", 337 /* fp_cmp */, - 0, - Opcode_ule_s_encode_fns, 0, 0 }, - { "float.s", 338 /* fp_float */, - 0, - Opcode_float_s_encode_fns, 0, 0 }, - { "ufloat.s", 338 /* fp_float */, - 0, - Opcode_ufloat_s_encode_fns, 0, 0 }, - { "round.s", 339 /* fp_int */, - 0, - Opcode_round_s_encode_fns, 0, 0 }, - { "ceil.s", 339 /* fp_int */, - 0, - Opcode_ceil_s_encode_fns, 0, 0 }, - { "floor.s", 339 /* fp_int */, - 0, - Opcode_floor_s_encode_fns, 0, 0 }, - { "trunc.s", 339 /* fp_int */, - 0, - Opcode_trunc_s_encode_fns, 0, 0 }, - { "utrunc.s", 339 /* fp_int */, - 0, - Opcode_utrunc_s_encode_fns, 0, 0 }, - { "rfr", 340 /* fp_rfr */, - 0, - Opcode_rfr_encode_fns, 0, 0 }, - { "wfr", 341 /* fp_wfr */, - 0, - Opcode_wfr_encode_fns, 0, 0 }, - { "lsi", 342 /* fp_lsi */, - 0, - Opcode_lsi_encode_fns, 0, 0 }, - { "lsiu", 343 /* fp_lsiu */, - 0, - Opcode_lsiu_encode_fns, 0, 0 }, - { "lsx", 344 /* fp_lsx */, - 0, - Opcode_lsx_encode_fns, 0, 0 }, - { "lsxu", 345 /* fp_lsxu */, - 0, - Opcode_lsxu_encode_fns, 0, 0 }, - { "ssi", 346 /* fp_ssi */, - 0, - Opcode_ssi_encode_fns, 0, 0 }, - { "ssiu", 347 /* fp_ssiu */, - 0, - Opcode_ssiu_encode_fns, 0, 0 }, - { "ssx", 348 /* fp_ssx */, - 0, - Opcode_ssx_encode_fns, 0, 0 }, - { "ssxu", 349 /* fp_ssxu */, - 0, - Opcode_ssxu_encode_fns, 0, 0 }, - { "beqz.w18", 350 /* xt_iclass_wb18_0 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqz_w18_encode_fns, 0, 0 }, - { "bnez.w18", 350 /* xt_iclass_wb18_0 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnez_w18_encode_fns, 0, 0 }, - { "bgez.w18", 350 /* xt_iclass_wb18_0 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgez_w18_encode_fns, 0, 0 }, - { "bltz.w18", 350 /* xt_iclass_wb18_0 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltz_w18_encode_fns, 0, 0 }, - { "beqi.w18", 351 /* xt_iclass_wb18_1 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqi_w18_encode_fns, 0, 0 }, - { "bnei.w18", 351 /* xt_iclass_wb18_1 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnei_w18_encode_fns, 0, 0 }, - { "bgei.w18", 351 /* xt_iclass_wb18_1 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgei_w18_encode_fns, 0, 0 }, - { "blti.w18", 351 /* xt_iclass_wb18_1 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_blti_w18_encode_fns, 0, 0 }, - { "bgeui.w18", 352 /* xt_iclass_wb18_2 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgeui_w18_encode_fns, 0, 0 }, - { "bltui.w18", 352 /* xt_iclass_wb18_2 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltui_w18_encode_fns, 0, 0 }, - { "bbci.w18", 353 /* xt_iclass_wb18_3 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbci_w18_encode_fns, 0, 0 }, - { "bbsi.w18", 353 /* xt_iclass_wb18_3 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbsi_w18_encode_fns, 0, 0 }, - { "beq.w18", 354 /* xt_iclass_wb18_4 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beq_w18_encode_fns, 0, 0 }, - { "bne.w18", 354 /* xt_iclass_wb18_4 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bne_w18_encode_fns, 0, 0 }, - { "bge.w18", 354 /* xt_iclass_wb18_4 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bge_w18_encode_fns, 0, 0 }, - { "blt.w18", 354 /* xt_iclass_wb18_4 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_blt_w18_encode_fns, 0, 0 }, - { "bgeu.w18", 354 /* xt_iclass_wb18_4 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgeu_w18_encode_fns, 0, 0 }, - { "bltu.w18", 354 /* xt_iclass_wb18_4 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltu_w18_encode_fns, 0, 0 }, - { "bany.w18", 354 /* xt_iclass_wb18_4 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bany_w18_encode_fns, 0, 0 }, - { "bnone.w18", 354 /* xt_iclass_wb18_4 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnone_w18_encode_fns, 0, 0 }, - { "ball.w18", 354 /* xt_iclass_wb18_4 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_ball_w18_encode_fns, 0, 0 }, - { "bnall.w18", 354 /* xt_iclass_wb18_4 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnall_w18_encode_fns, 0, 0 }, - { "bbc.w18", 354 /* xt_iclass_wb18_4 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbc_w18_encode_fns, 0, 0 }, - { "bbs.w18", 354 /* xt_iclass_wb18_4 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbs_w18_encode_fns, 0, 0 } -}; - - -/* Slot-specific opcode decode functions. */ - -static int -Slot_inst_decode (const xtensa_insnbuf insn) -{ - switch (Field_op0_Slot_inst_get (insn)) - { - case 0: - switch (Field_op1_Slot_inst_get (insn)) - { - case 0: - switch (Field_op2_Slot_inst_get (insn)) - { - case 0: - switch (Field_r_Slot_inst_get (insn)) - { - case 0: - switch (Field_m_Slot_inst_get (insn)) - { - case 0: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_n_Slot_inst_get (insn) == 0) - return 79; /* ill */ - break; - case 2: - switch (Field_n_Slot_inst_get (insn)) - { - case 0: - return 98; /* ret */ - case 1: - return 14; /* retw */ - case 2: - return 81; /* jx */ - } - break; - case 3: - switch (Field_n_Slot_inst_get (insn)) - { - case 0: - return 77; /* callx0 */ - case 1: - return 10; /* callx4 */ - case 2: - return 9; /* callx8 */ - case 3: - return 8; /* callx12 */ - } - break; - } - break; - case 1: - return 12; /* movsp */ - case 2: - if (Field_s_Slot_inst_get (insn) == 0) - { - switch (Field_t_Slot_inst_get (insn)) - { - case 0: - return 116; /* isync */ - case 1: - return 117; /* rsync */ - case 2: - return 118; /* esync */ - case 3: - return 119; /* dsync */ - case 8: - return 0; /* excw */ - case 12: - return 114; /* memw */ - case 13: - return 115; /* extw */ - case 15: - return 97; /* nop */ - } - } - break; - case 3: - switch (Field_t_Slot_inst_get (insn)) - { - case 0: - switch (Field_s_Slot_inst_get (insn)) - { - case 0: - return 1; /* rfe */ - case 2: - return 2; /* rfde */ - case 4: - return 16; /* rfwo */ - case 5: - return 17; /* rfwu */ - } - break; - case 1: - return 316; /* rfi */ - } - break; - case 4: - return 324; /* break */ - case 5: - switch (Field_s_Slot_inst_get (insn)) - { - case 0: - if (Field_t_Slot_inst_get (insn) == 0) - return 3; /* syscall */ - break; - case 1: - if (Field_t_Slot_inst_get (insn) == 0) - return 4; /* simcall */ - break; - } - break; - case 6: - return 120; /* rsil */ - case 7: - if (Field_t_Slot_inst_get (insn) == 0) - return 317; /* waiti */ - break; - case 8: - return 367; /* any4 */ - case 9: - return 368; /* all4 */ - case 10: - return 369; /* any8 */ - case 11: - return 370; /* all8 */ - } - break; - case 1: - return 49; /* and */ - case 2: - return 50; /* or */ - case 3: - return 51; /* xor */ - case 4: - switch (Field_r_Slot_inst_get (insn)) - { - case 0: - if (Field_t_Slot_inst_get (insn) == 0) - return 102; /* ssr */ - break; - case 1: - if (Field_t_Slot_inst_get (insn) == 0) - return 103; /* ssl */ - break; - case 2: - if (Field_t_Slot_inst_get (insn) == 0) - return 104; /* ssa8l */ - break; - case 3: - if (Field_t_Slot_inst_get (insn) == 0) - return 105; /* ssa8b */ - break; - case 4: - if (Field_thi3_Slot_inst_get (insn) == 0) - return 106; /* ssai */ - break; - case 8: - if (Field_s_Slot_inst_get (insn) == 0) - return 13; /* rotw */ - break; - case 14: - return 448; /* nsa */ - case 15: - return 449; /* nsau */ - } - break; - case 5: - switch (Field_r_Slot_inst_get (insn)) - { - case 1: - return 438; /* hwwitlba */ - case 3: - return 434; /* ritlb0 */ - case 4: - if (Field_t_Slot_inst_get (insn) == 0) - return 432; /* iitlb */ - break; - case 5: - return 433; /* pitlb */ - case 6: - return 436; /* witlb */ - case 7: - return 435; /* ritlb1 */ - case 9: - return 439; /* hwwdtlba */ - case 11: - return 429; /* rdtlb0 */ - case 12: - if (Field_t_Slot_inst_get (insn) == 0) - return 427; /* idtlb */ - break; - case 13: - return 428; /* pdtlb */ - case 14: - return 431; /* wdtlb */ - case 15: - return 430; /* rdtlb1 */ - } - break; - case 6: - switch (Field_s_Slot_inst_get (insn)) - { - case 0: - return 95; /* neg */ - case 1: - return 96; /* abs */ - } - break; - case 8: - return 41; /* add */ - case 9: - return 43; /* addx2 */ - case 10: - return 44; /* addx4 */ - case 11: - return 45; /* addx8 */ - case 12: - return 42; /* sub */ - case 13: - return 46; /* subx2 */ - case 14: - return 47; /* subx4 */ - case 15: - return 48; /* subx8 */ - } - break; - case 1: - switch (Field_op2_Slot_inst_get (insn)) - { - case 0: - case 1: - return 111; /* slli */ - case 2: - case 3: - return 112; /* srai */ - case 4: - return 113; /* srli */ - case 6: - switch (Field_sr_Slot_inst_get (insn)) - { - case 0: - return 129; /* xsr.lbeg */ - case 1: - return 123; /* xsr.lend */ - case 2: - return 126; /* xsr.lcount */ - case 3: - return 132; /* xsr.sar */ - case 4: - return 377; /* xsr.br */ - case 5: - return 135; /* xsr.litbase */ - case 12: - return 456; /* xsr.scompare1 */ - case 16: - return 312; /* xsr.acclo */ - case 17: - return 315; /* xsr.acchi */ - case 32: - return 300; /* xsr.m0 */ - case 33: - return 303; /* xsr.m1 */ - case 34: - return 306; /* xsr.m2 */ - case 35: - return 309; /* xsr.m3 */ - case 72: - return 22; /* xsr.windowbase */ - case 73: - return 25; /* xsr.windowstart */ - case 83: - return 417; /* xsr.ptevaddr */ - case 90: - return 420; /* xsr.rasid */ - case 91: - return 423; /* xsr.itlbcfg */ - case 92: - return 426; /* xsr.dtlbcfg */ - case 96: - return 346; /* xsr.ibreakenable */ - case 104: - return 358; /* xsr.ddr */ - case 128: - return 340; /* xsr.ibreaka0 */ - case 129: - return 343; /* xsr.ibreaka1 */ - case 144: - return 328; /* xsr.dbreaka0 */ - case 145: - return 334; /* xsr.dbreaka1 */ - case 160: - return 331; /* xsr.dbreakc0 */ - case 161: - return 337; /* xsr.dbreakc1 */ - case 177: - return 143; /* xsr.epc1 */ - case 178: - return 149; /* xsr.epc2 */ - case 179: - return 155; /* xsr.epc3 */ - case 180: - return 161; /* xsr.epc4 */ - case 181: - return 167; /* xsr.epc5 */ - case 182: - return 173; /* xsr.epc6 */ - case 183: - return 179; /* xsr.epc7 */ - case 192: - return 206; /* xsr.depc */ - case 194: - return 185; /* xsr.eps2 */ - case 195: - return 188; /* xsr.eps3 */ - case 196: - return 191; /* xsr.eps4 */ - case 197: - return 194; /* xsr.eps5 */ - case 198: - return 197; /* xsr.eps6 */ - case 199: - return 200; /* xsr.eps7 */ - case 209: - return 146; /* xsr.excsave1 */ - case 210: - return 152; /* xsr.excsave2 */ - case 211: - return 158; /* xsr.excsave3 */ - case 212: - return 164; /* xsr.excsave4 */ - case 213: - return 170; /* xsr.excsave5 */ - case 214: - return 176; /* xsr.excsave6 */ - case 215: - return 182; /* xsr.excsave7 */ - case 224: - return 442; /* xsr.cpenable */ - case 228: - return 323; /* xsr.intenable */ - case 230: - return 140; /* xsr.ps */ - case 231: - return 225; /* xsr.vecbase */ - case 232: - return 209; /* xsr.exccause */ - case 233: - return 349; /* xsr.debugcause */ - case 234: - return 380; /* xsr.ccount */ - case 236: - return 352; /* xsr.icount */ - case 237: - return 355; /* xsr.icountlevel */ - case 238: - return 203; /* xsr.excvaddr */ - case 240: - return 383; /* xsr.ccompare0 */ - case 241: - return 386; /* xsr.ccompare1 */ - case 242: - return 389; /* xsr.ccompare2 */ - case 244: - return 212; /* xsr.misc0 */ - case 245: - return 215; /* xsr.misc1 */ - case 246: - return 218; /* xsr.misc2 */ - case 247: - return 221; /* xsr.misc3 */ - } - break; - case 8: - return 108; /* src */ - case 9: - if (Field_s_Slot_inst_get (insn) == 0) - return 109; /* srl */ - break; - case 10: - if (Field_t_Slot_inst_get (insn) == 0) - return 107; /* sll */ - break; - case 11: - if (Field_s_Slot_inst_get (insn) == 0) - return 110; /* sra */ - break; - case 12: - return 296; /* mul16u */ - case 13: - return 297; /* mul16s */ - case 15: - switch (Field_r_Slot_inst_get (insn)) - { - case 0: - return 396; /* lict */ - case 1: - return 398; /* sict */ - case 2: - return 397; /* licw */ - case 3: - return 399; /* sicw */ - case 8: - return 414; /* ldct */ - case 9: - return 413; /* sdct */ - case 14: - if (Field_t_Slot_inst_get (insn) == 0) - return 359; /* rfdo */ - if (Field_t_Slot_inst_get (insn) == 1) - return 360; /* rfdd */ - break; - case 15: - return 437; /* ldpte */ - } - break; - } - break; - case 2: - switch (Field_op2_Slot_inst_get (insn)) - { - case 0: - return 362; /* andb */ - case 1: - return 363; /* andbc */ - case 2: - return 364; /* orb */ - case 3: - return 365; /* orbc */ - case 4: - return 366; /* xorb */ - case 8: - return 461; /* mull */ - case 10: - return 462; /* muluh */ - case 11: - return 463; /* mulsh */ - case 12: - return 457; /* quou */ - case 13: - return 458; /* quos */ - case 14: - return 459; /* remu */ - case 15: - return 460; /* rems */ - } - break; - case 3: - switch (Field_op2_Slot_inst_get (insn)) - { - case 0: - switch (Field_sr_Slot_inst_get (insn)) - { - case 0: - return 127; /* rsr.lbeg */ - case 1: - return 121; /* rsr.lend */ - case 2: - return 124; /* rsr.lcount */ - case 3: - return 130; /* rsr.sar */ - case 4: - return 375; /* rsr.br */ - case 5: - return 133; /* rsr.litbase */ - case 12: - return 454; /* rsr.scompare1 */ - case 16: - return 310; /* rsr.acclo */ - case 17: - return 313; /* rsr.acchi */ - case 32: - return 298; /* rsr.m0 */ - case 33: - return 301; /* rsr.m1 */ - case 34: - return 304; /* rsr.m2 */ - case 35: - return 307; /* rsr.m3 */ - case 72: - return 20; /* rsr.windowbase */ - case 73: - return 23; /* rsr.windowstart */ - case 83: - return 416; /* rsr.ptevaddr */ - case 90: - return 418; /* rsr.rasid */ - case 91: - return 421; /* rsr.itlbcfg */ - case 92: - return 424; /* rsr.dtlbcfg */ - case 96: - return 344; /* rsr.ibreakenable */ - case 104: - return 356; /* rsr.ddr */ - case 128: - return 338; /* rsr.ibreaka0 */ - case 129: - return 341; /* rsr.ibreaka1 */ - case 144: - return 326; /* rsr.dbreaka0 */ - case 145: - return 332; /* rsr.dbreaka1 */ - case 160: - return 329; /* rsr.dbreakc0 */ - case 161: - return 335; /* rsr.dbreakc1 */ - case 176: - return 136; /* rsr.176 */ - case 177: - return 141; /* rsr.epc1 */ - case 178: - return 147; /* rsr.epc2 */ - case 179: - return 153; /* rsr.epc3 */ - case 180: - return 159; /* rsr.epc4 */ - case 181: - return 165; /* rsr.epc5 */ - case 182: - return 171; /* rsr.epc6 */ - case 183: - return 177; /* rsr.epc7 */ - case 192: - return 204; /* rsr.depc */ - case 194: - return 183; /* rsr.eps2 */ - case 195: - return 186; /* rsr.eps3 */ - case 196: - return 189; /* rsr.eps4 */ - case 197: - return 192; /* rsr.eps5 */ - case 198: - return 195; /* rsr.eps6 */ - case 199: - return 198; /* rsr.eps7 */ - case 208: - return 137; /* rsr.208 */ - case 209: - return 144; /* rsr.excsave1 */ - case 210: - return 150; /* rsr.excsave2 */ - case 211: - return 156; /* rsr.excsave3 */ - case 212: - return 162; /* rsr.excsave4 */ - case 213: - return 168; /* rsr.excsave5 */ - case 214: - return 174; /* rsr.excsave6 */ - case 215: - return 180; /* rsr.excsave7 */ - case 224: - return 440; /* rsr.cpenable */ - case 226: - return 318; /* rsr.interrupt */ - case 228: - return 321; /* rsr.intenable */ - case 230: - return 138; /* rsr.ps */ - case 231: - return 223; /* rsr.vecbase */ - case 232: - return 207; /* rsr.exccause */ - case 233: - return 347; /* rsr.debugcause */ - case 234: - return 378; /* rsr.ccount */ - case 235: - return 222; /* rsr.prid */ - case 236: - return 350; /* rsr.icount */ - case 237: - return 353; /* rsr.icountlevel */ - case 238: - return 201; /* rsr.excvaddr */ - case 240: - return 381; /* rsr.ccompare0 */ - case 241: - return 384; /* rsr.ccompare1 */ - case 242: - return 387; /* rsr.ccompare2 */ - case 244: - return 210; /* rsr.misc0 */ - case 245: - return 213; /* rsr.misc1 */ - case 246: - return 216; /* rsr.misc2 */ - case 247: - return 219; /* rsr.misc3 */ - } - break; - case 1: - switch (Field_sr_Slot_inst_get (insn)) - { - case 0: - return 128; /* wsr.lbeg */ - case 1: - return 122; /* wsr.lend */ - case 2: - return 125; /* wsr.lcount */ - case 3: - return 131; /* wsr.sar */ - case 4: - return 376; /* wsr.br */ - case 5: - return 134; /* wsr.litbase */ - case 12: - return 455; /* wsr.scompare1 */ - case 16: - return 311; /* wsr.acclo */ - case 17: - return 314; /* wsr.acchi */ - case 32: - return 299; /* wsr.m0 */ - case 33: - return 302; /* wsr.m1 */ - case 34: - return 305; /* wsr.m2 */ - case 35: - return 308; /* wsr.m3 */ - case 72: - return 21; /* wsr.windowbase */ - case 73: - return 24; /* wsr.windowstart */ - case 83: - return 415; /* wsr.ptevaddr */ - case 89: - return 361; /* wsr.mmid */ - case 90: - return 419; /* wsr.rasid */ - case 91: - return 422; /* wsr.itlbcfg */ - case 92: - return 425; /* wsr.dtlbcfg */ - case 96: - return 345; /* wsr.ibreakenable */ - case 104: - return 357; /* wsr.ddr */ - case 128: - return 339; /* wsr.ibreaka0 */ - case 129: - return 342; /* wsr.ibreaka1 */ - case 144: - return 327; /* wsr.dbreaka0 */ - case 145: - return 333; /* wsr.dbreaka1 */ - case 160: - return 330; /* wsr.dbreakc0 */ - case 161: - return 336; /* wsr.dbreakc1 */ - case 177: - return 142; /* wsr.epc1 */ - case 178: - return 148; /* wsr.epc2 */ - case 179: - return 154; /* wsr.epc3 */ - case 180: - return 160; /* wsr.epc4 */ - case 181: - return 166; /* wsr.epc5 */ - case 182: - return 172; /* wsr.epc6 */ - case 183: - return 178; /* wsr.epc7 */ - case 192: - return 205; /* wsr.depc */ - case 194: - return 184; /* wsr.eps2 */ - case 195: - return 187; /* wsr.eps3 */ - case 196: - return 190; /* wsr.eps4 */ - case 197: - return 193; /* wsr.eps5 */ - case 198: - return 196; /* wsr.eps6 */ - case 199: - return 199; /* wsr.eps7 */ - case 209: - return 145; /* wsr.excsave1 */ - case 210: - return 151; /* wsr.excsave2 */ - case 211: - return 157; /* wsr.excsave3 */ - case 212: - return 163; /* wsr.excsave4 */ - case 213: - return 169; /* wsr.excsave5 */ - case 214: - return 175; /* wsr.excsave6 */ - case 215: - return 181; /* wsr.excsave7 */ - case 224: - return 441; /* wsr.cpenable */ - case 226: - return 319; /* wsr.intset */ - case 227: - return 320; /* wsr.intclear */ - case 228: - return 322; /* wsr.intenable */ - case 230: - return 139; /* wsr.ps */ - case 231: - return 224; /* wsr.vecbase */ - case 232: - return 208; /* wsr.exccause */ - case 233: - return 348; /* wsr.debugcause */ - case 234: - return 379; /* wsr.ccount */ - case 236: - return 351; /* wsr.icount */ - case 237: - return 354; /* wsr.icountlevel */ - case 238: - return 202; /* wsr.excvaddr */ - case 240: - return 382; /* wsr.ccompare0 */ - case 241: - return 385; /* wsr.ccompare1 */ - case 242: - return 388; /* wsr.ccompare2 */ - case 244: - return 211; /* wsr.misc0 */ - case 245: - return 214; /* wsr.misc1 */ - case 246: - return 217; /* wsr.misc2 */ - case 247: - return 220; /* wsr.misc3 */ - } - break; - case 2: - return 450; /* sext */ - case 3: - return 443; /* clamps */ - case 4: - return 444; /* min */ - case 5: - return 445; /* max */ - case 6: - return 446; /* minu */ - case 7: - return 447; /* maxu */ - case 8: - return 91; /* moveqz */ - case 9: - return 92; /* movnez */ - case 10: - return 93; /* movltz */ - case 11: - return 94; /* movgez */ - case 12: - return 373; /* movf */ - case 13: - return 374; /* movt */ - case 14: - switch (Field_st_Slot_inst_get (insn)) - { - case 231: - return 37; /* rur.threadptr */ - case 232: - return 464; /* rur.fcr */ - case 233: - return 466; /* rur.fsr */ - } - break; - case 15: - switch (Field_sr_Slot_inst_get (insn)) - { - case 231: - return 38; /* wur.threadptr */ - case 232: - return 465; /* wur.fcr */ - case 233: - return 467; /* wur.fsr */ - } - break; - } - break; - case 4: - case 5: - return 78; /* extui */ - case 8: - switch (Field_op2_Slot_inst_get (insn)) - { - case 0: - return 500; /* lsx */ - case 1: - return 501; /* lsxu */ - case 4: - return 504; /* ssx */ - case 5: - return 505; /* ssxu */ - } - break; - case 9: - switch (Field_op2_Slot_inst_get (insn)) - { - case 0: - return 18; /* l32e */ - case 4: - return 19; /* s32e */ - } - break; - case 10: - switch (Field_op2_Slot_inst_get (insn)) - { - case 0: - return 468; /* add.s */ - case 1: - return 469; /* sub.s */ - case 2: - return 470; /* mul.s */ - case 4: - return 471; /* madd.s */ - case 5: - return 472; /* msub.s */ - case 8: - return 491; /* round.s */ - case 9: - return 494; /* trunc.s */ - case 10: - return 493; /* floor.s */ - case 11: - return 492; /* ceil.s */ - case 12: - return 489; /* float.s */ - case 13: - return 490; /* ufloat.s */ - case 14: - return 495; /* utrunc.s */ - case 15: - switch (Field_t_Slot_inst_get (insn)) - { - case 0: - return 480; /* mov.s */ - case 1: - return 479; /* abs.s */ - case 4: - return 496; /* rfr */ - case 5: - return 497; /* wfr */ - case 6: - return 481; /* neg.s */ - } - break; - } - break; - case 11: - switch (Field_op2_Slot_inst_get (insn)) - { - case 1: - return 482; /* un.s */ - case 2: - return 483; /* oeq.s */ - case 3: - return 484; /* ueq.s */ - case 4: - return 485; /* olt.s */ - case 5: - return 486; /* ult.s */ - case 6: - return 487; /* ole.s */ - case 7: - return 488; /* ule.s */ - case 8: - return 475; /* moveqz.s */ - case 9: - return 476; /* movnez.s */ - case 10: - return 477; /* movltz.s */ - case 11: - return 478; /* movgez.s */ - case 12: - return 473; /* movf.s */ - case 13: - return 474; /* movt.s */ - } - break; - } - break; - case 1: - return 85; /* l32r */ - case 2: - switch (Field_r_Slot_inst_get (insn)) - { - case 0: - return 86; /* l8ui */ - case 1: - return 82; /* l16ui */ - case 2: - return 84; /* l32i */ - case 4: - return 101; /* s8i */ - case 5: - return 99; /* s16i */ - case 6: - return 100; /* s32i */ - case 7: - switch (Field_t_Slot_inst_get (insn)) - { - case 0: - return 406; /* dpfr */ - case 1: - return 407; /* dpfw */ - case 2: - return 408; /* dpfro */ - case 3: - return 409; /* dpfwo */ - case 4: - return 400; /* dhwb */ - case 5: - return 401; /* dhwbi */ - case 6: - return 404; /* dhi */ - case 7: - return 405; /* dii */ - case 8: - switch (Field_op1_Slot_inst_get (insn)) - { - case 0: - return 410; /* dpfl */ - case 2: - return 411; /* dhu */ - case 3: - return 412; /* diu */ - case 4: - return 402; /* diwb */ - case 5: - return 403; /* diwbi */ - } - break; - case 12: - return 390; /* ipf */ - case 13: - switch (Field_op1_Slot_inst_get (insn)) - { - case 0: - return 392; /* ipfl */ - case 2: - return 393; /* ihu */ - case 3: - return 394; /* iiu */ - } - break; - case 14: - return 391; /* ihi */ - case 15: - return 395; /* iii */ - } - break; - case 9: - return 83; /* l16si */ - case 10: - return 90; /* movi */ - case 11: - return 451; /* l32ai */ - case 12: - return 39; /* addi */ - case 13: - return 40; /* addmi */ - case 14: - return 453; /* s32c1i */ - case 15: - return 452; /* s32ri */ - } - break; - case 3: - switch (Field_r_Slot_inst_get (insn)) - { - case 0: - return 498; /* lsi */ - case 4: - return 502; /* ssi */ - case 8: - return 499; /* lsiu */ - case 12: - return 503; /* ssiu */ - } - break; - case 4: - switch (Field_op2_Slot_inst_get (insn)) - { - case 0: - switch (Field_op1_Slot_inst_get (insn)) - { - case 8: - if (Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 287; /* mula.dd.ll.ldinc */ - break; - case 9: - if (Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 289; /* mula.dd.hl.ldinc */ - break; - case 10: - if (Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 291; /* mula.dd.lh.ldinc */ - break; - case 11: - if (Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 293; /* mula.dd.hh.ldinc */ - break; - } - break; - case 1: - switch (Field_op1_Slot_inst_get (insn)) - { - case 8: - if (Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 286; /* mula.dd.ll.lddec */ - break; - case 9: - if (Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 288; /* mula.dd.hl.lddec */ - break; - case 10: - if (Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 290; /* mula.dd.lh.lddec */ - break; - case 11: - if (Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 292; /* mula.dd.hh.lddec */ - break; - } - break; - case 2: - switch (Field_op1_Slot_inst_get (insn)) - { - case 4: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 242; /* mul.dd.ll */ - break; - case 5: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 243; /* mul.dd.hl */ - break; - case 6: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 244; /* mul.dd.lh */ - break; - case 7: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 245; /* mul.dd.hh */ - break; - case 8: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 270; /* mula.dd.ll */ - break; - case 9: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 271; /* mula.dd.hl */ - break; - case 10: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 272; /* mula.dd.lh */ - break; - case 11: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 273; /* mula.dd.hh */ - break; - case 12: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 274; /* muls.dd.ll */ - break; - case 13: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 275; /* muls.dd.hl */ - break; - case 14: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 276; /* muls.dd.lh */ - break; - case 15: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 277; /* muls.dd.hh */ - break; - } - break; - case 3: - switch (Field_op1_Slot_inst_get (insn)) - { - case 4: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 234; /* mul.ad.ll */ - break; - case 5: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 235; /* mul.ad.hl */ - break; - case 6: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 236; /* mul.ad.lh */ - break; - case 7: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 237; /* mul.ad.hh */ - break; - case 8: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 254; /* mula.ad.ll */ - break; - case 9: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 255; /* mula.ad.hl */ - break; - case 10: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 256; /* mula.ad.lh */ - break; - case 11: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 257; /* mula.ad.hh */ - break; - case 12: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 258; /* muls.ad.ll */ - break; - case 13: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 259; /* muls.ad.hl */ - break; - case 14: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 260; /* muls.ad.lh */ - break; - case 15: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 261; /* muls.ad.hh */ - break; - } - break; - case 4: - switch (Field_op1_Slot_inst_get (insn)) - { - case 8: - if (Field_r3_Slot_inst_get (insn) == 0) - return 279; /* mula.da.ll.ldinc */ - break; - case 9: - if (Field_r3_Slot_inst_get (insn) == 0) - return 281; /* mula.da.hl.ldinc */ - break; - case 10: - if (Field_r3_Slot_inst_get (insn) == 0) - return 283; /* mula.da.lh.ldinc */ - break; - case 11: - if (Field_r3_Slot_inst_get (insn) == 0) - return 285; /* mula.da.hh.ldinc */ - break; - } - break; - case 5: - switch (Field_op1_Slot_inst_get (insn)) - { - case 8: - if (Field_r3_Slot_inst_get (insn) == 0) - return 278; /* mula.da.ll.lddec */ - break; - case 9: - if (Field_r3_Slot_inst_get (insn) == 0) - return 280; /* mula.da.hl.lddec */ - break; - case 10: - if (Field_r3_Slot_inst_get (insn) == 0) - return 282; /* mula.da.lh.lddec */ - break; - case 11: - if (Field_r3_Slot_inst_get (insn) == 0) - return 284; /* mula.da.hh.lddec */ - break; - } - break; - case 6: - switch (Field_op1_Slot_inst_get (insn)) - { - case 4: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 238; /* mul.da.ll */ - break; - case 5: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 239; /* mul.da.hl */ - break; - case 6: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 240; /* mul.da.lh */ - break; - case 7: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 241; /* mul.da.hh */ - break; - case 8: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 262; /* mula.da.ll */ - break; - case 9: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 263; /* mula.da.hl */ - break; - case 10: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 264; /* mula.da.lh */ - break; - case 11: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 265; /* mula.da.hh */ - break; - case 12: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 266; /* muls.da.ll */ - break; - case 13: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 267; /* muls.da.hl */ - break; - case 14: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 268; /* muls.da.lh */ - break; - case 15: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 269; /* muls.da.hh */ - break; - } - break; - case 7: - switch (Field_op1_Slot_inst_get (insn)) - { - case 0: - if (Field_r_Slot_inst_get (insn) == 0) - return 230; /* umul.aa.ll */ - break; - case 1: - if (Field_r_Slot_inst_get (insn) == 0) - return 231; /* umul.aa.hl */ - break; - case 2: - if (Field_r_Slot_inst_get (insn) == 0) - return 232; /* umul.aa.lh */ - break; - case 3: - if (Field_r_Slot_inst_get (insn) == 0) - return 233; /* umul.aa.hh */ - break; - case 4: - if (Field_r_Slot_inst_get (insn) == 0) - return 226; /* mul.aa.ll */ - break; - case 5: - if (Field_r_Slot_inst_get (insn) == 0) - return 227; /* mul.aa.hl */ - break; - case 6: - if (Field_r_Slot_inst_get (insn) == 0) - return 228; /* mul.aa.lh */ - break; - case 7: - if (Field_r_Slot_inst_get (insn) == 0) - return 229; /* mul.aa.hh */ - break; - case 8: - if (Field_r_Slot_inst_get (insn) == 0) - return 246; /* mula.aa.ll */ - break; - case 9: - if (Field_r_Slot_inst_get (insn) == 0) - return 247; /* mula.aa.hl */ - break; - case 10: - if (Field_r_Slot_inst_get (insn) == 0) - return 248; /* mula.aa.lh */ - break; - case 11: - if (Field_r_Slot_inst_get (insn) == 0) - return 249; /* mula.aa.hh */ - break; - case 12: - if (Field_r_Slot_inst_get (insn) == 0) - return 250; /* muls.aa.ll */ - break; - case 13: - if (Field_r_Slot_inst_get (insn) == 0) - return 251; /* muls.aa.hl */ - break; - case 14: - if (Field_r_Slot_inst_get (insn) == 0) - return 252; /* muls.aa.lh */ - break; - case 15: - if (Field_r_Slot_inst_get (insn) == 0) - return 253; /* muls.aa.hh */ - break; - } - break; - case 8: - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_rhi_Slot_inst_get (insn) == 0) - return 295; /* ldinc */ - break; - case 9: - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_rhi_Slot_inst_get (insn) == 0) - return 294; /* lddec */ - break; - } - break; - case 5: - switch (Field_n_Slot_inst_get (insn)) - { - case 0: - return 76; /* call0 */ - case 1: - return 7; /* call4 */ - case 2: - return 6; /* call8 */ - case 3: - return 5; /* call12 */ - } - break; - case 6: - switch (Field_n_Slot_inst_get (insn)) - { - case 0: - return 80; /* j */ - case 1: - switch (Field_m_Slot_inst_get (insn)) - { - case 0: - return 72; /* beqz */ - case 1: - return 73; /* bnez */ - case 2: - return 75; /* bltz */ - case 3: - return 74; /* bgez */ - } - break; - case 2: - switch (Field_m_Slot_inst_get (insn)) - { - case 0: - return 52; /* beqi */ - case 1: - return 53; /* bnei */ - case 2: - return 55; /* blti */ - case 3: - return 54; /* bgei */ - } - break; - case 3: - switch (Field_m_Slot_inst_get (insn)) - { - case 0: - return 11; /* entry */ - case 1: - switch (Field_r_Slot_inst_get (insn)) - { - case 0: - return 371; /* bf */ - case 1: - return 372; /* bt */ - case 8: - return 87; /* loop */ - case 9: - return 88; /* loopnez */ - case 10: - return 89; /* loopgtz */ - } - break; - case 2: - return 59; /* bltui */ - case 3: - return 58; /* bgeui */ - } - break; - } - break; - case 7: - switch (Field_r_Slot_inst_get (insn)) - { - case 0: - return 67; /* bnone */ - case 1: - return 60; /* beq */ - case 2: - return 63; /* blt */ - case 3: - return 65; /* bltu */ - case 4: - return 68; /* ball */ - case 5: - return 70; /* bbc */ - case 6: - case 7: - return 56; /* bbci */ - case 8: - return 66; /* bany */ - case 9: - return 61; /* bne */ - case 10: - return 62; /* bge */ - case 11: - return 64; /* bgeu */ - case 12: - return 69; /* bnall */ - case 13: - return 71; /* bbs */ - case 14: - case 15: - return 57; /* bbsi */ - } - break; - } - return 0; +static xtensa_iclass_internal iclasses[] = { + { 0, 0 /* xt_iclass_excw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_rfe */, + 2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfde */, + 1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_syscall */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_simcall */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call12_args, + 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call8_args, + 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call4_args, + 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx12_args, + 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx8_args, + 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx4_args, + 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_entry_args, + 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movsp_args, + 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rotw_args, + 1, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_retw_args, + 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfwou */, + 5, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_l32e_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32e_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowbase_args, + 1, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowbase_args, + 1, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowbase_args, + 1, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowstart_args, + 1, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowstart_args, + 1, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowstart_args, + 1, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_add_n_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addi_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bz6_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill_n */, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_loadi4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_mov_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_movi_n_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nopn */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_retn_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_storei4_args, + 0, 0, 0, 0 }, + { 1, Iclass_rur_threadptr_args, + 1, Iclass_rur_threadptr_stateArgs, 0, 0 }, + { 1, Iclass_wur_threadptr_args, + 1, Iclass_wur_threadptr_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_addi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addmi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addsub_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bit_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8b_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8u_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bst8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bsz12_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_callx0_args, + 0, 0, 0, 0 }, + { 4, Iclass_xt_iclass_exti_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jump_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jumpx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16ui_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16si_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_l32r_args, + 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_l8i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_loop_args, + 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_loopz_args, + 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_movz_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_neg_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nop */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_return_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s16i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s8i_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_sar_args, + 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sari_args, + 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shifts_args, + 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_shiftst_args, + 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shiftt_args, + 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_slli_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srli_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_memw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_extw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_isync */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_sync */, + 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rsil_args, + 6, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lend_args, + 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lend_args, + 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lend_args, + 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lcount_args, + 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lcount_args, + 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lcount_args, + 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lbeg_args, + 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lbeg_args, + 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lbeg_args, + 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_sar_args, + 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_sar_args, + 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_sar_args, + 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_litbase_args, + 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_litbase_args, + 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_litbase_args, + 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_176_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_208_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ps_args, + 6, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ps_args, + 6, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ps_args, + 6, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc1_args, + 1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc1_args, + 1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc1_args, + 1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave1_args, + 1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave1_args, + 1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave1_args, + 1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc2_args, + 1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc2_args, + 1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc2_args, + 1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave2_args, + 1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave2_args, + 1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave2_args, + 1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc3_args, + 1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc3_args, + 1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc3_args, + 1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave3_args, + 1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave3_args, + 1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave3_args, + 1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc4_args, + 1, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc4_args, + 1, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc4_args, + 1, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave4_args, + 1, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave4_args, + 1, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave4_args, + 1, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc5_args, + 1, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc5_args, + 1, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc5_args, + 1, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave5_args, + 1, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave5_args, + 1, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave5_args, + 1, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps2_args, + 1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps2_args, + 1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps2_args, + 1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps3_args, + 1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps3_args, + 1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps3_args, + 1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps4_args, + 1, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps4_args, + 1, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps4_args, + 1, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps5_args, + 1, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps5_args, + 1, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps5_args, + 1, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excvaddr_args, + 1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excvaddr_args, + 1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excvaddr_args, + 1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_depc_args, + 1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_depc_args, + 1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_depc_args, + 1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_exccause_args, + 2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_exccause_args, + 1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_exccause_args, + 1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc0_args, + 1, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc0_args, + 1, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc0_args, + 1, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc1_args, + 1, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc1_args, + 1, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc1_args, + 1, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_prid_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_vecbase_args, + 1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_vecbase_args, + 1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_vecbase_args, + 1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rfi_args, + 16, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wait_args, + 1, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_interrupt_args, + 1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intset_args, + 2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intclear_args, + 2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_intenable_args, + 1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intenable_args, + 1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_intenable_args, + 1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_break_args, + 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_break_n_args, + 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka0_args, + 1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka0_args, + 2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka0_args, + 2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc0_args, + 1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc0_args, + 2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc0_args, + 2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka1_args, + 1, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka1_args, + 2, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka1_args, + 2, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc1_args, + 1, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc1_args, + 2, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc1_args, + 2, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka0_args, + 1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka0_args, + 1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka0_args, + 1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka1_args, + 1, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka1_args, + 1, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka1_args, + 1, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreakenable_args, + 1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreakenable_args, + 1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreakenable_args, + 1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_debugcause_args, + 2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_debugcause_args, + 2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_debugcause_args, + 2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icount_args, + 1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icount_args, + 2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icount_args, + 2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icountlevel_args, + 1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icountlevel_args, + 1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icountlevel_args, + 1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ddr_args, + 1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ddr_args, + 2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ddr_args, + 2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rfdo_args, + 9, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfdd */, + 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_mmid_args, + 1, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccount_args, + 1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccount_args, + 2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccount_args, + 2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare0_args, + 1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare0_args, + 2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare0_args, + 2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_idtlb_args, + 1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rdtlb_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wdtlb_args, + 1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_iitlb_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_ritlb_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_witlb_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_minmax_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_nsa_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_sx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32ai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32ri_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32c1i_args, + 2, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_scompare1_args, + 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_scompare1_args, + 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_scompare1_args, + 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 }, + { 3, Iclass_xt_mul32_args, + 0, 0, 0, 0 } +}; + + +/* Opcode encodings. */ + +static void +Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80200; +} + +static void +Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300; +} + +static void +Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2300; +} + +static void +Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500; +} + +static void +Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500; +} + +static void +Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0000; +} + +static void +Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580000; +} + +static void +Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0000; +} + +static void +Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70000; +} + +static void +Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0000; +} + +static void +Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100; +} + +static void +Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x804; +} + +static void +Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd10f; +} + +static void +Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4300; +} + +static void +Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5300; +} + +static void +Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90; +} + +static void +Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x94; +} + +static void +Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4830; +} + +static void +Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4831; +} + +static void +Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4816; +} + +static void +Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4930; +} + +static void +Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4931; +} + +static void +Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4916; +} + +static void +Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000; +} + +static void +Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb000; +} + +static void +Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc800; +} + +static void +Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc00; +} + +static void +Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd60f; +} + +static void +Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd000; +} + +static void +Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000; +} + +static void +Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd30f; +} + +static void +Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00f; +} + +static void +Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9000; +} + +static void +Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e03e; +} + +static void +Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe73f; +} + +static void +Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200c00; +} + +static void +Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200d00; +} + +static void +Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8; +} + +static void +Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc; +} + +static void +Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9; +} + +static void +Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa; +} + +static void +Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb; +} + +static void +Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd; +} + +static void +Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe; +} + +static void +Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf; +} + +static void +Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3; +} + +static void +Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680000; +} + +static void +Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690000; +} + +static void +Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b0000; +} + +static void +Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0000; +} + +static void +Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700600; +} + +static void +Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700e00; +} + +static void +Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0000; +} + +static void +Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e0000; +} + +static void +Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700100; +} + +static void +Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700900; +} + +static void +Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700a00; +} + +static void +Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700200; +} + +static void +Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700b00; +} + +static void +Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700300; +} + +static void +Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700800; +} + +static void +Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700000; +} + +static void +Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700400; +} + +static void +Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700c00; +} + +static void +Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700500; +} + +static void +Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700d00; +} + +static void +Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640000; +} + +static void +Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650000; +} + +static void +Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x670000; +} + +static void +Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x660000; +} + +static void +Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40; +} + +static void +Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200100; +} + +static void +Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200900; +} + +static void +Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200200; +} + +static void +Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0800; +} + +static void +Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0900; +} + +static void +Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0a00; +} + +static void +Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200a00; +} + +static void +Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38; +} + +static void +Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39; +} + +static void +Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a; +} + +static void +Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b; +} + +static void +Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6; +} + +static void +Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1006; +} + +static void +Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0200; +} + +static void +Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200500; +} + +static void +Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200600; +} + +static void +Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200400; +} + +static void +Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4; +} + +static void +Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104; +} + +static void +Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x204; +} + +static void +Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x304; +} + +static void +Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x404; +} + +static void +Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a; +} + +static void +Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18; +} + +static void +Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19; +} + +static void +Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b; +} + +static void +Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10; +} + +static void +Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12; +} + +static void +Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14; +} + +static void +Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0200; +} + +static void +Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0200; +} + +static void +Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200; +} + +static void +Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10200; +} + +static void +Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20200; +} + +static void +Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30200; +} + +static void +Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600; +} + +static void +Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130; +} + +static void +Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x131; +} + +static void +Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x116; +} + +static void +Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230; +} + +static void +Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x231; +} + +static void +Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x216; +} + +static void +Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30; +} + +static void +Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x31; +} + +static void +Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16; +} + +static void +Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330; +} + +static void +Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x331; +} + +static void +Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x316; +} + +static void +Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530; +} + +static void +Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x531; +} + +static void +Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x516; +} + +static void +Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb030; +} + +static void +Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd030; +} + +static void +Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe630; +} + +static void +Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe631; +} + +static void +Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe616; +} + +static void +Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb130; +} + +static void +Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb131; +} + +static void +Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb116; +} + +static void +Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd130; +} + +static void +Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd131; +} + +static void +Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd116; +} + +static void +Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb230; +} + +static void +Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb231; +} + +static void +Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb216; +} + +static void +Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd230; +} + +static void +Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd231; +} + +static void +Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd216; +} + +static void +Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb330; +} + +static void +Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb331; +} + +static void +Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb316; +} + +static void +Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd330; +} + +static void +Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd331; +} + +static void +Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd316; +} + +static void +Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb430; +} + +static void +Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb431; +} + +static void +Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb416; +} + +static void +Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd430; +} + +static void +Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd431; +} + +static void +Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd416; +} + +static void +Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb530; +} + +static void +Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb531; +} + +static void +Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb516; +} + +static void +Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd530; +} + +static void +Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd531; +} + +static void +Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd516; +} + +static void +Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc230; +} + +static void +Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc231; +} + +static void +Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc216; +} + +static void +Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc330; +} + +static void +Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc331; +} + +static void +Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc316; +} + +static void +Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc430; +} + +static void +Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc431; +} + +static void +Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc416; +} + +static void +Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc530; +} + +static void +Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc531; +} + +static void +Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc516; +} + +static void +Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee30; +} + +static void +Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee31; +} + +static void +Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee16; +} + +static void +Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc030; +} + +static void +Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc031; +} + +static void +Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc016; +} + +static void +Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe830; +} + +static void +Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe831; +} + +static void +Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe816; +} + +static void +Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf430; +} + +static void +Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf431; +} + +static void +Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf416; +} + +static void +Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf530; +} + +static void +Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf531; +} + +static void +Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf516; +} + +static void +Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb30; +} + +static void +Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe730; +} + +static void +Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe731; +} + +static void +Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe716; +} + +static void +Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10300; +} + +static void +Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700; +} + +static void +Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe230; +} + +static void +Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe231; +} + +static void +Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe331; +} + +static void +Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe430; +} + +static void +Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe431; +} + +static void +Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe416; +} + +static void +Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400; +} + +static void +Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20f; +} + +static void +Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9030; +} + +static void +Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9031; +} + +static void +Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9016; +} + +static void +Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa030; +} + +static void +Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa031; +} + +static void +Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa016; +} + +static void +Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9130; +} + +static void +Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9131; +} + +static void +Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9116; +} + +static void +Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa130; +} + +static void +Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa131; +} + +static void +Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa116; +} + +static void +Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8030; +} + +static void +Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8031; +} + +static void +Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8016; +} + +static void +Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8130; +} + +static void +Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8131; +} + +static void +Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8116; +} + +static void +Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6030; +} + +static void +Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6031; +} + +static void +Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6016; +} + +static void +Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe930; +} + +static void +Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe931; +} + +static void +Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe916; +} + +static void +Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec30; +} + +static void +Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec31; +} + +static void +Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec16; +} + +static void +Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xed30; +} + +static void +Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xed31; +} + +static void +Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xed16; +} + +static void +Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6830; +} + +static void +Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6831; +} + +static void +Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6816; +} + +static void +Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1f; +} + +static void +Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e1f; +} + +static void +Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5931; +} + +static void +Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea30; +} + +static void +Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea31; +} + +static void +Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea16; +} + +static void +Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf030; +} + +static void +Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf031; +} + +static void +Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf016; +} + +static void +Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc05; +} + +static void +Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd05; +} + +static void +Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb05; +} + +static void +Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf05; +} + +static void +Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe05; +} + +static void +Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x405; +} + +static void +Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x505; +} + +static void +Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305; +} + +static void +Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x705; +} + +static void +Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x605; +} + +static void +Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34; +} + +static void +Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35; +} + +static void +Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36; +} + +static void +Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x37; +} + +static void +Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe04; +} + +static void +Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf04; +} + +static void +Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32; +} + +static void +Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200b00; +} + +static void +Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200f00; +} + +static void +Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200e00; +} + +static void +Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc30; +} + +static void +Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc31; +} + +static void +Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc16; +} + +static void +Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28; +} + +static void +Opcode_muluh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a; +} + +static void +Opcode_mulsh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b; +} + +static void +Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c; +} + +static void +Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d; } -static int -Slot_inst16b_decode (const xtensa_insnbuf insn) -{ - switch (Field_op0_Slot_inst16b_get (insn)) - { - case 12: - switch (Field_i_Slot_inst16b_get (insn)) - { - case 0: - return 33; /* movi.n */ - case 1: - switch (Field_z_Slot_inst16b_get (insn)) - { - case 0: - return 28; /* beqz.n */ - case 1: - return 29; /* bnez.n */ - } - break; - } - break; - case 13: - switch (Field_r_Slot_inst16b_get (insn)) - { - case 0: - return 32; /* mov.n */ - case 15: - switch (Field_t_Slot_inst16b_get (insn)) - { - case 0: - return 35; /* ret.n */ - case 1: - return 15; /* retw.n */ - case 2: - return 325; /* break.n */ - case 3: - if (Field_s_Slot_inst16b_get (insn) == 0) - return 34; /* nop.n */ - break; - case 6: - if (Field_s_Slot_inst16b_get (insn) == 0) - return 30; /* ill.n */ - break; - } - break; - } - break; - } - return 0; -} +xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { + Opcode_excw_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { + Opcode_rfe_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { + Opcode_rfde_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { + Opcode_syscall_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { + Opcode_simcall_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { + Opcode_call12_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { + Opcode_call8_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { + Opcode_call4_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { + Opcode_callx12_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { + Opcode_callx8_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { + Opcode_callx4_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { + Opcode_entry_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { + Opcode_movsp_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { + Opcode_rotw_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { + Opcode_retw_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { + 0, 0, Opcode_retw_n_Slot_inst16b_encode +}; + +xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { + Opcode_rfwo_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { + Opcode_rfwu_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { + Opcode_l32e_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { + Opcode_s32e_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { + Opcode_rsr_windowbase_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { + Opcode_wsr_windowbase_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { + Opcode_xsr_windowbase_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { + Opcode_rsr_windowstart_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { + Opcode_wsr_windowstart_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { + Opcode_xsr_windowstart_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { + 0, Opcode_add_n_Slot_inst16a_encode, 0 +}; + +xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { + 0, Opcode_addi_n_Slot_inst16a_encode, 0 +}; + +xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { + 0, 0, Opcode_beqz_n_Slot_inst16b_encode +}; + +xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { + 0, 0, Opcode_bnez_n_Slot_inst16b_encode +}; + +xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { + 0, 0, Opcode_ill_n_Slot_inst16b_encode +}; + +xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { + 0, Opcode_l32i_n_Slot_inst16a_encode, 0 +}; + +xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { + 0, 0, Opcode_mov_n_Slot_inst16b_encode +}; + +xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { + 0, 0, Opcode_movi_n_Slot_inst16b_encode +}; + +xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { + 0, 0, Opcode_nop_n_Slot_inst16b_encode +}; + +xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { + 0, 0, Opcode_ret_n_Slot_inst16b_encode +}; + +xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { + 0, Opcode_s32i_n_Slot_inst16a_encode, 0 +}; + +xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { + Opcode_rur_threadptr_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { + Opcode_wur_threadptr_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { + Opcode_addi_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { + Opcode_addmi_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { + Opcode_add_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { + Opcode_sub_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { + Opcode_addx2_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { + Opcode_addx4_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { + Opcode_addx8_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { + Opcode_subx2_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { + Opcode_subx4_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { + Opcode_subx8_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { + Opcode_and_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { + Opcode_or_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { + Opcode_xor_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { + Opcode_beqi_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { + Opcode_bnei_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { + Opcode_bgei_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { + Opcode_blti_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { + Opcode_bbci_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { + Opcode_bbsi_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { + Opcode_bgeui_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { + Opcode_bltui_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { + Opcode_beq_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { + Opcode_bne_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { + Opcode_bge_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { + Opcode_blt_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { + Opcode_bgeu_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { + Opcode_bltu_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { + Opcode_bany_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { + Opcode_bnone_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { + Opcode_ball_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { + Opcode_bnall_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { + Opcode_bbc_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { + Opcode_bbs_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { + Opcode_beqz_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { + Opcode_bnez_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { + Opcode_bgez_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { + Opcode_bltz_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { + Opcode_call0_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { + Opcode_callx0_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { + Opcode_extui_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { + Opcode_ill_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { + Opcode_j_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { + Opcode_jx_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { + Opcode_l16ui_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { + Opcode_l16si_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { + Opcode_l32i_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { + Opcode_l32r_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { + Opcode_l8ui_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { + Opcode_loop_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { + Opcode_loopnez_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { + Opcode_loopgtz_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { + Opcode_movi_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { + Opcode_moveqz_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { + Opcode_movnez_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { + Opcode_movltz_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { + Opcode_movgez_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { + Opcode_neg_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { + Opcode_abs_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { + Opcode_nop_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { + Opcode_ret_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { + Opcode_s16i_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { + Opcode_s32i_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { + Opcode_s8i_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { + Opcode_ssr_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { + Opcode_ssl_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { + Opcode_ssa8l_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { + Opcode_ssa8b_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { + Opcode_ssai_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { + Opcode_sll_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { + Opcode_src_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { + Opcode_srl_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { + Opcode_sra_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { + Opcode_slli_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { + Opcode_srai_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { + Opcode_srli_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { + Opcode_memw_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { + Opcode_extw_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { + Opcode_isync_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { + Opcode_rsync_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { + Opcode_esync_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { + Opcode_dsync_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { + Opcode_rsil_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { + Opcode_rsr_lend_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { + Opcode_wsr_lend_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { + Opcode_xsr_lend_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { + Opcode_rsr_lcount_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { + Opcode_wsr_lcount_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { + Opcode_xsr_lcount_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { + Opcode_rsr_lbeg_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { + Opcode_wsr_lbeg_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { + Opcode_xsr_lbeg_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { + Opcode_rsr_sar_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { + Opcode_wsr_sar_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { + Opcode_xsr_sar_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { + Opcode_rsr_litbase_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { + Opcode_wsr_litbase_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { + Opcode_xsr_litbase_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = { + Opcode_rsr_176_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = { + Opcode_rsr_208_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { + Opcode_rsr_ps_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { + Opcode_wsr_ps_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { + Opcode_xsr_ps_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { + Opcode_rsr_epc1_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { + Opcode_wsr_epc1_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { + Opcode_xsr_epc1_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { + Opcode_rsr_excsave1_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { + Opcode_wsr_excsave1_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { + Opcode_xsr_excsave1_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { + Opcode_rsr_epc2_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { + Opcode_wsr_epc2_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { + Opcode_xsr_epc2_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { + Opcode_rsr_excsave2_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { + Opcode_wsr_excsave2_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { + Opcode_xsr_excsave2_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { + Opcode_rsr_epc3_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { + Opcode_wsr_epc3_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { + Opcode_xsr_epc3_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { + Opcode_rsr_excsave3_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { + Opcode_wsr_excsave3_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { + Opcode_xsr_excsave3_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { + Opcode_rsr_epc4_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { + Opcode_wsr_epc4_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { + Opcode_xsr_epc4_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { + Opcode_rsr_excsave4_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { + Opcode_wsr_excsave4_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { + Opcode_xsr_excsave4_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { + Opcode_rsr_epc5_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { + Opcode_wsr_epc5_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { + Opcode_xsr_epc5_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { + Opcode_rsr_excsave5_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { + Opcode_wsr_excsave5_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { + Opcode_xsr_excsave5_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { + Opcode_rsr_eps2_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { + Opcode_wsr_eps2_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { + Opcode_xsr_eps2_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { + Opcode_rsr_eps3_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { + Opcode_wsr_eps3_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { + Opcode_xsr_eps3_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { + Opcode_rsr_eps4_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { + Opcode_wsr_eps4_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { + Opcode_xsr_eps4_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { + Opcode_rsr_eps5_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { + Opcode_wsr_eps5_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { + Opcode_xsr_eps5_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { + Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { + Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { + Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { + Opcode_rsr_depc_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { + Opcode_wsr_depc_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { + Opcode_xsr_depc_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { + Opcode_rsr_exccause_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { + Opcode_wsr_exccause_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { + Opcode_xsr_exccause_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { + Opcode_rsr_misc0_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { + Opcode_wsr_misc0_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { + Opcode_xsr_misc0_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { + Opcode_rsr_misc1_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { + Opcode_wsr_misc1_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { + Opcode_xsr_misc1_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { + Opcode_rsr_prid_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { + Opcode_rsr_vecbase_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { + Opcode_wsr_vecbase_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { + Opcode_xsr_vecbase_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { + Opcode_rfi_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { + Opcode_waiti_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { + Opcode_rsr_interrupt_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { + Opcode_wsr_intset_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { + Opcode_wsr_intclear_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { + Opcode_rsr_intenable_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { + Opcode_wsr_intenable_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { + Opcode_xsr_intenable_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { + Opcode_break_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { + 0, 0, Opcode_break_n_Slot_inst16b_encode +}; + +xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { + Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { + Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { + Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { + Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { + Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { + Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { + Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0 +}; -static int -Slot_inst16a_decode (const xtensa_insnbuf insn) -{ - switch (Field_op0_Slot_inst16a_get (insn)) - { - case 8: - return 31; /* l32i.n */ - case 9: - return 36; /* s32i.n */ - case 10: - return 26; /* add.n */ - case 11: - return 27; /* addi.n */ - } - return 0; -} +xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { + Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0 +}; -static int -Slot_xt_flix64_slot2_decode (const xtensa_insnbuf insn) -{ - switch (Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn)) - { - case 0: - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 1) - return 41; /* add */ - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 5) - return 42; /* sub */ - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 2) - return 43; /* addx2 */ - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 3) - return 49; /* and */ - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 4) - return 450; /* sext */ - break; - case 1: - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 1) - return 27; /* addi.n */ - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 2) - return 44; /* addx4 */ - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 3) - return 50; /* or */ - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 5) - return 51; /* xor */ - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 4) - return 113; /* srli */ - break; - } - if (Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0 && - Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6) - return 33; /* movi.n */ - if (Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 2 && - Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 && - Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0) - return 32; /* mov.n */ - if (Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 3 && - Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 && - Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0) - return 97; /* nop */ - if (Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 8 && - Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 && - Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0) - return 96; /* abs */ - if (Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 9 && - Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 && - Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0) - return 95; /* neg */ - if (Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 5 && - Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 && - Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0) - return 110; /* sra */ - if (Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 3 && - Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 && - Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0) - return 109; /* srl */ - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 7) - return 112; /* srai */ - return 0; -} +xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { + Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0 +}; -static int -Slot_xt_flix64_slot0_decode (const xtensa_insnbuf insn) -{ - switch (Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_get (insn)) - { - case 0: - if (Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_get (insn) == 2) - return 78; /* extui */ - switch (Field_op1_Slot_xt_flix64_slot0_get (insn)) - { - case 0: - switch (Field_op2_Slot_xt_flix64_slot0_get (insn)) - { - case 0: - if (Field_r_Slot_xt_flix64_slot0_get (insn) == 2) - { - if (Field_s_Slot_xt_flix64_slot0_get (insn) == 0) - { - if (Field_t_Slot_xt_flix64_slot0_get (insn) == 15) - return 97; /* nop */ - } - } - break; - case 1: - return 49; /* and */ - case 2: - return 50; /* or */ - case 3: - return 51; /* xor */ - case 4: - switch (Field_r_Slot_xt_flix64_slot0_get (insn)) - { - case 0: - if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0) - return 102; /* ssr */ - break; - case 1: - if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0) - return 103; /* ssl */ - break; - case 2: - if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0) - return 104; /* ssa8l */ - break; - case 3: - if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0) - return 105; /* ssa8b */ - break; - case 4: - if (Field_thi3_Slot_xt_flix64_slot0_get (insn) == 0) - return 106; /* ssai */ - break; - case 14: - return 448; /* nsa */ - case 15: - return 449; /* nsau */ - } - break; - case 6: - switch (Field_s_Slot_xt_flix64_slot0_get (insn)) - { - case 0: - return 95; /* neg */ - case 1: - return 96; /* abs */ - } - break; - case 8: - return 41; /* add */ - case 9: - return 43; /* addx2 */ - case 10: - return 44; /* addx4 */ - case 11: - return 45; /* addx8 */ - case 12: - return 42; /* sub */ - case 13: - return 46; /* subx2 */ - case 14: - return 47; /* subx4 */ - case 15: - return 48; /* subx8 */ - } - break; - case 1: - if (Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_get (insn) == 1) - return 112; /* srai */ - if (Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_get (insn) == 0) - return 111; /* slli */ - switch (Field_op2_Slot_xt_flix64_slot0_get (insn)) - { - case 4: - return 113; /* srli */ - case 8: - return 108; /* src */ - case 9: - if (Field_s_Slot_xt_flix64_slot0_get (insn) == 0) - return 109; /* srl */ - break; - case 10: - if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0) - return 107; /* sll */ - break; - case 11: - if (Field_s_Slot_xt_flix64_slot0_get (insn) == 0) - return 110; /* sra */ - break; - case 12: - return 296; /* mul16u */ - case 13: - return 297; /* mul16s */ - } - break; - case 2: - if (Field_op2_Slot_xt_flix64_slot0_get (insn) == 8) - return 461; /* mull */ - break; - case 3: - switch (Field_op2_Slot_xt_flix64_slot0_get (insn)) - { - case 2: - return 450; /* sext */ - case 3: - return 443; /* clamps */ - case 4: - return 444; /* min */ - case 5: - return 445; /* max */ - case 6: - return 446; /* minu */ - case 7: - return 447; /* maxu */ - case 8: - return 91; /* moveqz */ - case 9: - return 92; /* movnez */ - case 10: - return 93; /* movltz */ - case 11: - return 94; /* movgez */ - } - break; - } - break; - case 2: - switch (Field_r_Slot_xt_flix64_slot0_get (insn)) - { - case 0: - return 86; /* l8ui */ - case 1: - return 82; /* l16ui */ - case 2: - return 84; /* l32i */ - case 4: - return 101; /* s8i */ - case 5: - return 99; /* s16i */ - case 6: - return 100; /* s32i */ - case 9: - return 83; /* l16si */ - case 10: - return 90; /* movi */ - case 12: - return 39; /* addi */ - case 13: - return 40; /* addmi */ - } - break; - } - if (Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get (insn) == 1) - return 85; /* l32r */ - if (Field_sae4_Slot_xt_flix64_slot0_get (insn) == 0 && - Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_get (insn) == 3 && - Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get (insn) == 0 && - Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_get (insn) == 0) - return 32; /* mov.n */ - return 0; -} +xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { + Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0 +}; -static int -Slot_xt_flix64_slot1_decode (const xtensa_insnbuf insn) -{ - if (Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0 && - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 1) - return 78; /* extui */ - switch (Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn)) - { - case 0: - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) - return 90; /* movi */ - break; - case 2: - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 1) - return 39; /* addi */ - break; - case 3: - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 1) - return 40; /* addmi */ - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 && - Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_get (insn) == 0) - return 51; /* xor */ - break; - } - switch (Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn)) - { - case 8: - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) - return 111; /* slli */ - break; - case 16: - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) - return 112; /* srai */ - break; - case 19: - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 && - Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0) - return 107; /* sll */ - break; - } - switch (Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn)) - { - case 18: - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) - return 41; /* add */ - break; - case 19: - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) - return 45; /* addx8 */ - break; - case 20: - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) - return 43; /* addx2 */ - break; - case 21: - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) - return 49; /* and */ - break; - case 22: - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) - return 91; /* moveqz */ - break; - case 23: - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) - return 94; /* movgez */ - break; - case 24: - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) - return 44; /* addx4 */ - break; - case 25: - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) - return 93; /* movltz */ - break; - case 26: - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) - return 92; /* movnez */ - break; - case 27: - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) - return 296; /* mul16u */ - break; - case 28: - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) - return 297; /* mul16s */ - break; - case 29: - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) - return 461; /* mull */ - break; - case 30: - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) - return 50; /* or */ - break; - case 31: - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) - return 450; /* sext */ - break; - case 34: - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) - return 108; /* src */ - break; - case 36: - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) - return 113; /* srli */ - break; - } - if (Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 280 && - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 && - Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0) - return 32; /* mov.n */ - if (Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 281 && - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 && - Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0) - return 81; /* jx */ - if (Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 141 && - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 && - Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0) - return 103; /* ssl */ - if (Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 71 && - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 && - Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0) - return 97; /* nop */ - if (Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 148 && - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 && - Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0) - return 95; /* neg */ - if (Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 149 && - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 && - Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0) - return 110; /* sra */ - if (Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 75 && - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 && - Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0) - return 109; /* srl */ - if (Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 5 && - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 && - Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0) - return 42; /* sub */ - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 3) - return 80; /* j */ - return 0; -} +xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { + Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { + Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0 +}; -static int -Slot_xt_flix64_slot3_decode (const xtensa_insnbuf insn) -{ - switch (Field_op0_s6_Slot_xt_flix64_slot3_get (insn)) - { - case 1: - if (Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get (insn) == 0) - return 516; /* bbci.w18 */ - break; - case 2: - if (Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get (insn) == 0) - return 517; /* bbsi.w18 */ - break; - case 3: - if (Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) - return 526; /* ball.w18 */ - break; - case 4: - if (Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) - return 524; /* bany.w18 */ - break; - case 5: - if (Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) - return 528; /* bbc.w18 */ - break; - case 6: - if (Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) - return 529; /* bbs.w18 */ - break; - case 7: - if (Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) - return 518; /* beq.w18 */ - break; - case 8: - if (Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) - return 510; /* beqi.w18 */ - break; - case 9: - if (Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) - return 520; /* bge.w18 */ - break; - case 10: - if (Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) - return 512; /* bgei.w18 */ - break; - case 11: - if (Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) - return 522; /* bgeu.w18 */ - break; - case 12: - if (Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) - return 514; /* bgeui.w18 */ - break; - case 13: - if (Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) - return 521; /* blt.w18 */ - break; - case 14: - if (Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) - return 513; /* blti.w18 */ - break; - case 15: - if (Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) - return 523; /* bltu.w18 */ - break; - case 16: - if (Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) - return 515; /* bltui.w18 */ - break; - case 17: - if (Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) - return 527; /* bnall.w18 */ - break; - case 18: - if (Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) - return 519; /* bne.w18 */ - break; - case 19: - if (Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) - return 511; /* bnei.w18 */ - break; - case 20: - if (Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) - return 525; /* bnone.w18 */ - break; - case 21: - if (Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) - return 506; /* beqz.w18 */ - break; - case 22: - if (Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) - return 508; /* bgez.w18 */ - break; - case 23: - if (Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) - return 509; /* bltz.w18 */ - break; - case 24: - if (Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) - return 507; /* bnez.w18 */ - break; - case 25: - if (Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) - return 97; /* nop */ - break; - } - return 0; -} +xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { + Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0 +}; - -/* Instruction slots. */ +xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { + Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0 +}; -static void -Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = (insn[0] & 0xffffff); -} +xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { + Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0 +}; -static void -Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); -} +xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { + Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0 +}; -static void -Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = (insn[0] & 0xffff); -} +xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { + Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0 +}; -static void -Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); -} +xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { + Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0 +}; -static void -Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = (insn[0] & 0xffff); -} +xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { + Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0 +}; -static void -Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); -} +xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { + Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0 +}; -static void -Slot_xt_format1_Format_xt_flix64_slot0_4_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = ((insn[0] & 0xffffff0) >> 4); -} +xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { + Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0 +}; -static void -Slot_xt_format1_Format_xt_flix64_slot0_4_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffffff0) | ((slotbuf[0] & 0xffffff) << 4); -} +xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { + Opcode_rsr_debugcause_Slot_inst_encode, 0, 0 +}; -static void -Slot_xt_format2_Format_xt_flix64_slot0_4_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = ((insn[0] & 0xffffff0) >> 4); -} +xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { + Opcode_wsr_debugcause_Slot_inst_encode, 0, 0 +}; -static void -Slot_xt_format2_Format_xt_flix64_slot0_4_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffffff0) | ((slotbuf[0] & 0xffffff) << 4); -} +xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { + Opcode_xsr_debugcause_Slot_inst_encode, 0, 0 +}; -static void -Slot_xt_format1_Format_xt_flix64_slot1_28_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = ((insn[0] & 0xf0000000) >> 28); - slotbuf[0] = (slotbuf[0] & ~0xffff0) | ((insn[1] & 0xffff) << 4); -} +xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { + Opcode_rsr_icount_Slot_inst_encode, 0, 0 +}; -static void -Slot_xt_format1_Format_xt_flix64_slot1_28_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xf0000000) | ((slotbuf[0] & 0xf) << 28); - insn[1] = (insn[1] & ~0xffff) | ((slotbuf[0] & 0xffff0) >> 4); -} +xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { + Opcode_wsr_icount_Slot_inst_encode, 0, 0 +}; -static void -Slot_xt_format1_Format_xt_flix64_slot2_48_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = ((insn[1] & 0xffff0000) >> 16); -} +xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { + Opcode_xsr_icount_Slot_inst_encode, 0, 0 +}; -static void -Slot_xt_format1_Format_xt_flix64_slot2_48_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[1] = (insn[1] & ~0xffff0000) | ((slotbuf[0] & 0xffff) << 16); -} +xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { + Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0 +}; -static void -Slot_xt_format2_Format_xt_flix64_slot3_28_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[0] = ((insn[0] & 0xf0000000) >> 28); - slotbuf[0] = (slotbuf[0] & ~0xfffffff0) | ((insn[1] & 0xfffffff) << 4); - slotbuf[1] = ((insn[1] & 0x70000000) >> 28); -} +xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { + Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0 +}; -static void -Slot_xt_format2_Format_xt_flix64_slot3_28_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xf0000000) | ((slotbuf[0] & 0xf) << 28); - insn[1] = (insn[1] & ~0xfffffff) | ((slotbuf[0] & 0xfffffff0) >> 4); - insn[1] = (insn[1] & ~0x70000000) | ((slotbuf[1] & 0x7) << 28); -} +xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { + Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0 +}; -static xtensa_get_field_fn -Slot_inst_get_field_fns[] = { - Field_t_Slot_inst_get, - Field_bbi4_Slot_inst_get, - Field_bbi_Slot_inst_get, - Field_imm12_Slot_inst_get, - Field_imm8_Slot_inst_get, - Field_s_Slot_inst_get, - Field_imm12b_Slot_inst_get, - Field_imm16_Slot_inst_get, - Field_m_Slot_inst_get, - Field_n_Slot_inst_get, - Field_offset_Slot_inst_get, - Field_op0_Slot_inst_get, - Field_op1_Slot_inst_get, - Field_op2_Slot_inst_get, - Field_r_Slot_inst_get, - Field_sa4_Slot_inst_get, - Field_sae4_Slot_inst_get, - Field_sae_Slot_inst_get, - Field_sal_Slot_inst_get, - Field_sargt_Slot_inst_get, - Field_sas4_Slot_inst_get, - Field_sas_Slot_inst_get, - Field_sr_Slot_inst_get, - Field_st_Slot_inst_get, - Field_thi3_Slot_inst_get, - Field_imm4_Slot_inst_get, - Field_mn_Slot_inst_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_r3_Slot_inst_get, - Field_rbit2_Slot_inst_get, - Field_rhi_Slot_inst_get, - Field_t3_Slot_inst_get, - Field_tbit2_Slot_inst_get, - Field_tlo_Slot_inst_get, - Field_w_Slot_inst_get, - Field_y_Slot_inst_get, - Field_x_Slot_inst_get, - Field_t2_Slot_inst_get, - Field_s2_Slot_inst_get, - Field_r2_Slot_inst_get, - Field_t4_Slot_inst_get, - Field_s4_Slot_inst_get, - Field_r4_Slot_inst_get, - Field_t8_Slot_inst_get, - Field_s8_Slot_inst_get, - Field_r8_Slot_inst_get, - Field_xt_wbr15_imm_Slot_inst_get, - Field_xt_wbr18_imm_Slot_inst_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_mr0_get, - Implicit_Field_mr1_get, - Implicit_Field_mr2_get, - Implicit_Field_mr3_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get +xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { + Opcode_rsr_ddr_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { + Opcode_wsr_ddr_Slot_inst_encode, 0, 0 }; -static xtensa_set_field_fn -Slot_inst_set_field_fns[] = { - Field_t_Slot_inst_set, - Field_bbi4_Slot_inst_set, - Field_bbi_Slot_inst_set, - Field_imm12_Slot_inst_set, - Field_imm8_Slot_inst_set, - Field_s_Slot_inst_set, - Field_imm12b_Slot_inst_set, - Field_imm16_Slot_inst_set, - Field_m_Slot_inst_set, - Field_n_Slot_inst_set, - Field_offset_Slot_inst_set, - Field_op0_Slot_inst_set, - Field_op1_Slot_inst_set, - Field_op2_Slot_inst_set, - Field_r_Slot_inst_set, - Field_sa4_Slot_inst_set, - Field_sae4_Slot_inst_set, - Field_sae_Slot_inst_set, - Field_sal_Slot_inst_set, - Field_sargt_Slot_inst_set, - Field_sas4_Slot_inst_set, - Field_sas_Slot_inst_set, - Field_sr_Slot_inst_set, - Field_st_Slot_inst_set, - Field_thi3_Slot_inst_set, - Field_imm4_Slot_inst_set, - Field_mn_Slot_inst_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_r3_Slot_inst_set, - Field_rbit2_Slot_inst_set, - Field_rhi_Slot_inst_set, - Field_t3_Slot_inst_set, - Field_tbit2_Slot_inst_set, - Field_tlo_Slot_inst_set, - Field_w_Slot_inst_set, - Field_y_Slot_inst_set, - Field_x_Slot_inst_set, - Field_t2_Slot_inst_set, - Field_s2_Slot_inst_set, - Field_r2_Slot_inst_set, - Field_t4_Slot_inst_set, - Field_s4_Slot_inst_set, - Field_r4_Slot_inst_set, - Field_t8_Slot_inst_set, - Field_s8_Slot_inst_set, - Field_r8_Slot_inst_set, - Field_xt_wbr15_imm_Slot_inst_set, - Field_xt_wbr18_imm_Slot_inst_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set +xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { + Opcode_xsr_ddr_Slot_inst_encode, 0, 0 }; -static xtensa_get_field_fn -Slot_inst16a_get_field_fns[] = { - Field_t_Slot_inst16a_get, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16a_get, - 0, - 0, - Field_r_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16a_get, - Field_st_Slot_inst16a_get, - 0, - Field_imm4_Slot_inst16a_get, - 0, - Field_i_Slot_inst16a_get, - Field_imm6lo_Slot_inst16a_get, - Field_imm6hi_Slot_inst16a_get, - Field_imm7lo_Slot_inst16a_get, - Field_imm7hi_Slot_inst16a_get, - Field_z_Slot_inst16a_get, - Field_imm6_Slot_inst16a_get, - Field_imm7_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_t2_Slot_inst16a_get, - Field_s2_Slot_inst16a_get, - Field_r2_Slot_inst16a_get, - Field_t4_Slot_inst16a_get, - Field_s4_Slot_inst16a_get, - Field_r4_Slot_inst16a_get, - Field_t8_Slot_inst16a_get, - Field_s8_Slot_inst16a_get, - Field_r8_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_mr0_get, - Implicit_Field_mr1_get, - Implicit_Field_mr2_get, - Implicit_Field_mr3_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get +xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { + Opcode_rfdo_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { + Opcode_rfdd_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { + Opcode_wsr_mmid_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { + Opcode_rsr_ccount_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { + Opcode_wsr_ccount_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { + Opcode_xsr_ccount_Slot_inst_encode, 0, 0 }; -static xtensa_set_field_fn -Slot_inst16a_set_field_fns[] = { - Field_t_Slot_inst16a_set, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16a_set, - 0, - 0, - Field_r_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16a_set, - Field_st_Slot_inst16a_set, - 0, - Field_imm4_Slot_inst16a_set, - 0, - Field_i_Slot_inst16a_set, - Field_imm6lo_Slot_inst16a_set, - Field_imm6hi_Slot_inst16a_set, - Field_imm7lo_Slot_inst16a_set, - Field_imm7hi_Slot_inst16a_set, - Field_z_Slot_inst16a_set, - Field_imm6_Slot_inst16a_set, - Field_imm7_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_t2_Slot_inst16a_set, - Field_s2_Slot_inst16a_set, - Field_r2_Slot_inst16a_set, - Field_t4_Slot_inst16a_set, - Field_s4_Slot_inst16a_set, - Field_r4_Slot_inst16a_set, - Field_t8_Slot_inst16a_set, - Field_s8_Slot_inst16a_set, - Field_r8_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set +xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { + Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0 }; -static xtensa_get_field_fn -Slot_inst16b_get_field_fns[] = { - Field_t_Slot_inst16b_get, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16b_get, - 0, - 0, - Field_r_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16b_get, - Field_st_Slot_inst16b_get, - 0, - Field_imm4_Slot_inst16b_get, - 0, - Field_i_Slot_inst16b_get, - Field_imm6lo_Slot_inst16b_get, - Field_imm6hi_Slot_inst16b_get, - Field_imm7lo_Slot_inst16b_get, - Field_imm7hi_Slot_inst16b_get, - Field_z_Slot_inst16b_get, - Field_imm6_Slot_inst16b_get, - Field_imm7_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_t2_Slot_inst16b_get, - Field_s2_Slot_inst16b_get, - Field_r2_Slot_inst16b_get, - Field_t4_Slot_inst16b_get, - Field_s4_Slot_inst16b_get, - Field_r4_Slot_inst16b_get, - Field_t8_Slot_inst16b_get, - Field_s8_Slot_inst16b_get, - Field_r8_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_mr0_get, - Implicit_Field_mr1_get, - Implicit_Field_mr2_get, - Implicit_Field_mr3_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get +xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { + Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { + Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { + Opcode_idtlb_Slot_inst_encode, 0, 0 }; -static xtensa_set_field_fn -Slot_inst16b_set_field_fns[] = { - Field_t_Slot_inst16b_set, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16b_set, - 0, - 0, - Field_r_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16b_set, - Field_st_Slot_inst16b_set, - 0, - Field_imm4_Slot_inst16b_set, - 0, - Field_i_Slot_inst16b_set, - Field_imm6lo_Slot_inst16b_set, - Field_imm6hi_Slot_inst16b_set, - Field_imm7lo_Slot_inst16b_set, - Field_imm7hi_Slot_inst16b_set, - Field_z_Slot_inst16b_set, - Field_imm6_Slot_inst16b_set, - Field_imm7_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_t2_Slot_inst16b_set, - Field_s2_Slot_inst16b_set, - Field_r2_Slot_inst16b_set, - Field_t4_Slot_inst16b_set, - Field_s4_Slot_inst16b_set, - Field_r4_Slot_inst16b_set, - Field_t8_Slot_inst16b_set, - Field_s8_Slot_inst16b_set, - Field_r8_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set +xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { + Opcode_pdtlb_Slot_inst_encode, 0, 0 }; -static xtensa_get_field_fn -Slot_xt_flix64_slot0_get_field_fns[] = { - Field_t_Slot_xt_flix64_slot0_get, - 0, - 0, - 0, - Field_imm8_Slot_xt_flix64_slot0_get, - Field_s_Slot_xt_flix64_slot0_get, - Field_imm12b_Slot_xt_flix64_slot0_get, - Field_imm16_Slot_xt_flix64_slot0_get, - Field_m_Slot_xt_flix64_slot0_get, - Field_n_Slot_xt_flix64_slot0_get, - 0, - 0, - Field_op1_Slot_xt_flix64_slot0_get, - Field_op2_Slot_xt_flix64_slot0_get, - Field_r_Slot_xt_flix64_slot0_get, - 0, - Field_sae4_Slot_xt_flix64_slot0_get, - Field_sae_Slot_xt_flix64_slot0_get, - Field_sal_Slot_xt_flix64_slot0_get, - Field_sargt_Slot_xt_flix64_slot0_get, - 0, - Field_sas_Slot_xt_flix64_slot0_get, - 0, - 0, - Field_thi3_Slot_xt_flix64_slot0_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get, - Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_get, - Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_get, - Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_get, - Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_get, - Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_get, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_mr0_get, - Implicit_Field_mr1_get, - Implicit_Field_mr2_get, - Implicit_Field_mr3_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get +xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { + Opcode_rdtlb0_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { + Opcode_rdtlb1_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { + Opcode_wdtlb_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { + Opcode_iitlb_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { + Opcode_pitlb_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { + Opcode_ritlb0_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { + Opcode_ritlb1_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { + Opcode_witlb_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { + Opcode_min_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { + Opcode_max_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { + Opcode_minu_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { + Opcode_maxu_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { + Opcode_nsa_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { + Opcode_nsau_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { + Opcode_sext_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { + Opcode_l32ai_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { + Opcode_s32ri_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { + Opcode_s32c1i_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { + Opcode_rsr_scompare1_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { + Opcode_wsr_scompare1_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { + Opcode_xsr_scompare1_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { + Opcode_mull_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_muluh_encode_fns[] = { + Opcode_muluh_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_mulsh_encode_fns[] = { + Opcode_mulsh_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { + Opcode_mul16u_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { + Opcode_mul16s_Slot_inst_encode, 0, 0 +}; + + +/* Opcode table. */ + +static xtensa_opcode_internal opcodes[] = { + { "excw", 0 /* xt_iclass_excw */, + 0, + Opcode_excw_encode_fns, 0, 0 }, + { "rfe", 1 /* xt_iclass_rfe */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfe_encode_fns, 0, 0 }, + { "rfde", 2 /* xt_iclass_rfde */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfde_encode_fns, 0, 0 }, + { "syscall", 3 /* xt_iclass_syscall */, + 0, + Opcode_syscall_encode_fns, 0, 0 }, + { "simcall", 4 /* xt_iclass_simcall */, + 0, + Opcode_simcall_encode_fns, 0, 0 }, + { "call12", 5 /* xt_iclass_call12 */, + XTENSA_OPCODE_IS_CALL, + Opcode_call12_encode_fns, 0, 0 }, + { "call8", 6 /* xt_iclass_call8 */, + XTENSA_OPCODE_IS_CALL, + Opcode_call8_encode_fns, 0, 0 }, + { "call4", 7 /* xt_iclass_call4 */, + XTENSA_OPCODE_IS_CALL, + Opcode_call4_encode_fns, 0, 0 }, + { "callx12", 8 /* xt_iclass_callx12 */, + XTENSA_OPCODE_IS_CALL, + Opcode_callx12_encode_fns, 0, 0 }, + { "callx8", 9 /* xt_iclass_callx8 */, + XTENSA_OPCODE_IS_CALL, + Opcode_callx8_encode_fns, 0, 0 }, + { "callx4", 10 /* xt_iclass_callx4 */, + XTENSA_OPCODE_IS_CALL, + Opcode_callx4_encode_fns, 0, 0 }, + { "entry", 11 /* xt_iclass_entry */, + 0, + Opcode_entry_encode_fns, 0, 0 }, + { "movsp", 12 /* xt_iclass_movsp */, + 0, + Opcode_movsp_encode_fns, 0, 0 }, + { "rotw", 13 /* xt_iclass_rotw */, + 0, + Opcode_rotw_encode_fns, 0, 0 }, + { "retw", 14 /* xt_iclass_retw */, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_encode_fns, 0, 0 }, + { "retw.n", 14 /* xt_iclass_retw */, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_n_encode_fns, 0, 0 }, + { "rfwo", 15 /* xt_iclass_rfwou */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwo_encode_fns, 0, 0 }, + { "rfwu", 15 /* xt_iclass_rfwou */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwu_encode_fns, 0, 0 }, + { "l32e", 16 /* xt_iclass_l32e */, + 0, + Opcode_l32e_encode_fns, 0, 0 }, + { "s32e", 17 /* xt_iclass_s32e */, + 0, + Opcode_s32e_encode_fns, 0, 0 }, + { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */, + 0, + Opcode_rsr_windowbase_encode_fns, 0, 0 }, + { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */, + 0, + Opcode_wsr_windowbase_encode_fns, 0, 0 }, + { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */, + 0, + Opcode_xsr_windowbase_encode_fns, 0, 0 }, + { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */, + 0, + Opcode_rsr_windowstart_encode_fns, 0, 0 }, + { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */, + 0, + Opcode_wsr_windowstart_encode_fns, 0, 0 }, + { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */, + 0, + Opcode_xsr_windowstart_encode_fns, 0, 0 }, + { "add.n", 24 /* xt_iclass_add.n */, + 0, + Opcode_add_n_encode_fns, 0, 0 }, + { "addi.n", 25 /* xt_iclass_addi.n */, + 0, + Opcode_addi_n_encode_fns, 0, 0 }, + { "beqz.n", 26 /* xt_iclass_bz6 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_n_encode_fns, 0, 0 }, + { "bnez.n", 26 /* xt_iclass_bz6 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_n_encode_fns, 0, 0 }, + { "ill.n", 27 /* xt_iclass_ill.n */, + 0, + Opcode_ill_n_encode_fns, 0, 0 }, + { "l32i.n", 28 /* xt_iclass_loadi4 */, + 0, + Opcode_l32i_n_encode_fns, 0, 0 }, + { "mov.n", 29 /* xt_iclass_mov.n */, + 0, + Opcode_mov_n_encode_fns, 0, 0 }, + { "movi.n", 30 /* xt_iclass_movi.n */, + 0, + Opcode_movi_n_encode_fns, 0, 0 }, + { "nop.n", 31 /* xt_iclass_nopn */, + 0, + Opcode_nop_n_encode_fns, 0, 0 }, + { "ret.n", 32 /* xt_iclass_retn */, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_n_encode_fns, 0, 0 }, + { "s32i.n", 33 /* xt_iclass_storei4 */, + 0, + Opcode_s32i_n_encode_fns, 0, 0 }, + { "rur.threadptr", 34 /* rur_threadptr */, + 0, + Opcode_rur_threadptr_encode_fns, 0, 0 }, + { "wur.threadptr", 35 /* wur_threadptr */, + 0, + Opcode_wur_threadptr_encode_fns, 0, 0 }, + { "addi", 36 /* xt_iclass_addi */, + 0, + Opcode_addi_encode_fns, 0, 0 }, + { "addmi", 37 /* xt_iclass_addmi */, + 0, + Opcode_addmi_encode_fns, 0, 0 }, + { "add", 38 /* xt_iclass_addsub */, + 0, + Opcode_add_encode_fns, 0, 0 }, + { "sub", 38 /* xt_iclass_addsub */, + 0, + Opcode_sub_encode_fns, 0, 0 }, + { "addx2", 38 /* xt_iclass_addsub */, + 0, + Opcode_addx2_encode_fns, 0, 0 }, + { "addx4", 38 /* xt_iclass_addsub */, + 0, + Opcode_addx4_encode_fns, 0, 0 }, + { "addx8", 38 /* xt_iclass_addsub */, + 0, + Opcode_addx8_encode_fns, 0, 0 }, + { "subx2", 38 /* xt_iclass_addsub */, + 0, + Opcode_subx2_encode_fns, 0, 0 }, + { "subx4", 38 /* xt_iclass_addsub */, + 0, + Opcode_subx4_encode_fns, 0, 0 }, + { "subx8", 38 /* xt_iclass_addsub */, + 0, + Opcode_subx8_encode_fns, 0, 0 }, + { "and", 39 /* xt_iclass_bit */, + 0, + Opcode_and_encode_fns, 0, 0 }, + { "or", 39 /* xt_iclass_bit */, + 0, + Opcode_or_encode_fns, 0, 0 }, + { "xor", 39 /* xt_iclass_bit */, + 0, + Opcode_xor_encode_fns, 0, 0 }, + { "beqi", 40 /* xt_iclass_bsi8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqi_encode_fns, 0, 0 }, + { "bnei", 40 /* xt_iclass_bsi8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnei_encode_fns, 0, 0 }, + { "bgei", 40 /* xt_iclass_bsi8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgei_encode_fns, 0, 0 }, + { "blti", 40 /* xt_iclass_bsi8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blti_encode_fns, 0, 0 }, + { "bbci", 41 /* xt_iclass_bsi8b */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbci_encode_fns, 0, 0 }, + { "bbsi", 41 /* xt_iclass_bsi8b */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbsi_encode_fns, 0, 0 }, + { "bgeui", 42 /* xt_iclass_bsi8u */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeui_encode_fns, 0, 0 }, + { "bltui", 42 /* xt_iclass_bsi8u */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltui_encode_fns, 0, 0 }, + { "beq", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beq_encode_fns, 0, 0 }, + { "bne", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bne_encode_fns, 0, 0 }, + { "bge", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bge_encode_fns, 0, 0 }, + { "blt", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blt_encode_fns, 0, 0 }, + { "bgeu", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeu_encode_fns, 0, 0 }, + { "bltu", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltu_encode_fns, 0, 0 }, + { "bany", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bany_encode_fns, 0, 0 }, + { "bnone", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnone_encode_fns, 0, 0 }, + { "ball", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_ball_encode_fns, 0, 0 }, + { "bnall", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnall_encode_fns, 0, 0 }, + { "bbc", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbc_encode_fns, 0, 0 }, + { "bbs", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbs_encode_fns, 0, 0 }, + { "beqz", 44 /* xt_iclass_bsz12 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_encode_fns, 0, 0 }, + { "bnez", 44 /* xt_iclass_bsz12 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_encode_fns, 0, 0 }, + { "bgez", 44 /* xt_iclass_bsz12 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgez_encode_fns, 0, 0 }, + { "bltz", 44 /* xt_iclass_bsz12 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltz_encode_fns, 0, 0 }, + { "call0", 45 /* xt_iclass_call0 */, + XTENSA_OPCODE_IS_CALL, + Opcode_call0_encode_fns, 0, 0 }, + { "callx0", 46 /* xt_iclass_callx0 */, + XTENSA_OPCODE_IS_CALL, + Opcode_callx0_encode_fns, 0, 0 }, + { "extui", 47 /* xt_iclass_exti */, + 0, + Opcode_extui_encode_fns, 0, 0 }, + { "ill", 48 /* xt_iclass_ill */, + 0, + Opcode_ill_encode_fns, 0, 0 }, + { "j", 49 /* xt_iclass_jump */, + XTENSA_OPCODE_IS_JUMP, + Opcode_j_encode_fns, 0, 0 }, + { "jx", 50 /* xt_iclass_jumpx */, + XTENSA_OPCODE_IS_JUMP, + Opcode_jx_encode_fns, 0, 0 }, + { "l16ui", 51 /* xt_iclass_l16ui */, + 0, + Opcode_l16ui_encode_fns, 0, 0 }, + { "l16si", 52 /* xt_iclass_l16si */, + 0, + Opcode_l16si_encode_fns, 0, 0 }, + { "l32i", 53 /* xt_iclass_l32i */, + 0, + Opcode_l32i_encode_fns, 0, 0 }, + { "l32r", 54 /* xt_iclass_l32r */, + 0, + Opcode_l32r_encode_fns, 0, 0 }, + { "l8ui", 55 /* xt_iclass_l8i */, + 0, + Opcode_l8ui_encode_fns, 0, 0 }, + { "loop", 56 /* xt_iclass_loop */, + XTENSA_OPCODE_IS_LOOP, + Opcode_loop_encode_fns, 0, 0 }, + { "loopnez", 57 /* xt_iclass_loopz */, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopnez_encode_fns, 0, 0 }, + { "loopgtz", 57 /* xt_iclass_loopz */, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopgtz_encode_fns, 0, 0 }, + { "movi", 58 /* xt_iclass_movi */, + 0, + Opcode_movi_encode_fns, 0, 0 }, + { "moveqz", 59 /* xt_iclass_movz */, + 0, + Opcode_moveqz_encode_fns, 0, 0 }, + { "movnez", 59 /* xt_iclass_movz */, + 0, + Opcode_movnez_encode_fns, 0, 0 }, + { "movltz", 59 /* xt_iclass_movz */, + 0, + Opcode_movltz_encode_fns, 0, 0 }, + { "movgez", 59 /* xt_iclass_movz */, + 0, + Opcode_movgez_encode_fns, 0, 0 }, + { "neg", 60 /* xt_iclass_neg */, + 0, + Opcode_neg_encode_fns, 0, 0 }, + { "abs", 60 /* xt_iclass_neg */, + 0, + Opcode_abs_encode_fns, 0, 0 }, + { "nop", 61 /* xt_iclass_nop */, + 0, + Opcode_nop_encode_fns, 0, 0 }, + { "ret", 62 /* xt_iclass_return */, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_encode_fns, 0, 0 }, + { "s16i", 63 /* xt_iclass_s16i */, + 0, + Opcode_s16i_encode_fns, 0, 0 }, + { "s32i", 64 /* xt_iclass_s32i */, + 0, + Opcode_s32i_encode_fns, 0, 0 }, + { "s8i", 65 /* xt_iclass_s8i */, + 0, + Opcode_s8i_encode_fns, 0, 0 }, + { "ssr", 66 /* xt_iclass_sar */, + 0, + Opcode_ssr_encode_fns, 0, 0 }, + { "ssl", 66 /* xt_iclass_sar */, + 0, + Opcode_ssl_encode_fns, 0, 0 }, + { "ssa8l", 66 /* xt_iclass_sar */, + 0, + Opcode_ssa8l_encode_fns, 0, 0 }, + { "ssa8b", 66 /* xt_iclass_sar */, + 0, + Opcode_ssa8b_encode_fns, 0, 0 }, + { "ssai", 67 /* xt_iclass_sari */, + 0, + Opcode_ssai_encode_fns, 0, 0 }, + { "sll", 68 /* xt_iclass_shifts */, + 0, + Opcode_sll_encode_fns, 0, 0 }, + { "src", 69 /* xt_iclass_shiftst */, + 0, + Opcode_src_encode_fns, 0, 0 }, + { "srl", 70 /* xt_iclass_shiftt */, + 0, + Opcode_srl_encode_fns, 0, 0 }, + { "sra", 70 /* xt_iclass_shiftt */, + 0, + Opcode_sra_encode_fns, 0, 0 }, + { "slli", 71 /* xt_iclass_slli */, + 0, + Opcode_slli_encode_fns, 0, 0 }, + { "srai", 72 /* xt_iclass_srai */, + 0, + Opcode_srai_encode_fns, 0, 0 }, + { "srli", 73 /* xt_iclass_srli */, + 0, + Opcode_srli_encode_fns, 0, 0 }, + { "memw", 74 /* xt_iclass_memw */, + 0, + Opcode_memw_encode_fns, 0, 0 }, + { "extw", 75 /* xt_iclass_extw */, + 0, + Opcode_extw_encode_fns, 0, 0 }, + { "isync", 76 /* xt_iclass_isync */, + 0, + Opcode_isync_encode_fns, 0, 0 }, + { "rsync", 77 /* xt_iclass_sync */, + 0, + Opcode_rsync_encode_fns, 0, 0 }, + { "esync", 77 /* xt_iclass_sync */, + 0, + Opcode_esync_encode_fns, 0, 0 }, + { "dsync", 77 /* xt_iclass_sync */, + 0, + Opcode_dsync_encode_fns, 0, 0 }, + { "rsil", 78 /* xt_iclass_rsil */, + 0, + Opcode_rsil_encode_fns, 0, 0 }, + { "rsr.lend", 79 /* xt_iclass_rsr.lend */, + 0, + Opcode_rsr_lend_encode_fns, 0, 0 }, + { "wsr.lend", 80 /* xt_iclass_wsr.lend */, + 0, + Opcode_wsr_lend_encode_fns, 0, 0 }, + { "xsr.lend", 81 /* xt_iclass_xsr.lend */, + 0, + Opcode_xsr_lend_encode_fns, 0, 0 }, + { "rsr.lcount", 82 /* xt_iclass_rsr.lcount */, + 0, + Opcode_rsr_lcount_encode_fns, 0, 0 }, + { "wsr.lcount", 83 /* xt_iclass_wsr.lcount */, + 0, + Opcode_wsr_lcount_encode_fns, 0, 0 }, + { "xsr.lcount", 84 /* xt_iclass_xsr.lcount */, + 0, + Opcode_xsr_lcount_encode_fns, 0, 0 }, + { "rsr.lbeg", 85 /* xt_iclass_rsr.lbeg */, + 0, + Opcode_rsr_lbeg_encode_fns, 0, 0 }, + { "wsr.lbeg", 86 /* xt_iclass_wsr.lbeg */, + 0, + Opcode_wsr_lbeg_encode_fns, 0, 0 }, + { "xsr.lbeg", 87 /* xt_iclass_xsr.lbeg */, + 0, + Opcode_xsr_lbeg_encode_fns, 0, 0 }, + { "rsr.sar", 88 /* xt_iclass_rsr.sar */, + 0, + Opcode_rsr_sar_encode_fns, 0, 0 }, + { "wsr.sar", 89 /* xt_iclass_wsr.sar */, + 0, + Opcode_wsr_sar_encode_fns, 0, 0 }, + { "xsr.sar", 90 /* xt_iclass_xsr.sar */, + 0, + Opcode_xsr_sar_encode_fns, 0, 0 }, + { "rsr.litbase", 91 /* xt_iclass_rsr.litbase */, + 0, + Opcode_rsr_litbase_encode_fns, 0, 0 }, + { "wsr.litbase", 92 /* xt_iclass_wsr.litbase */, + 0, + Opcode_wsr_litbase_encode_fns, 0, 0 }, + { "xsr.litbase", 93 /* xt_iclass_xsr.litbase */, + 0, + Opcode_xsr_litbase_encode_fns, 0, 0 }, + { "rsr.176", 94 /* xt_iclass_rsr.176 */, + 0, + Opcode_rsr_176_encode_fns, 0, 0 }, + { "rsr.208", 95 /* xt_iclass_rsr.208 */, + 0, + Opcode_rsr_208_encode_fns, 0, 0 }, + { "rsr.ps", 96 /* xt_iclass_rsr.ps */, + 0, + Opcode_rsr_ps_encode_fns, 0, 0 }, + { "wsr.ps", 97 /* xt_iclass_wsr.ps */, + 0, + Opcode_wsr_ps_encode_fns, 0, 0 }, + { "xsr.ps", 98 /* xt_iclass_xsr.ps */, + 0, + Opcode_xsr_ps_encode_fns, 0, 0 }, + { "rsr.epc1", 99 /* xt_iclass_rsr.epc1 */, + 0, + Opcode_rsr_epc1_encode_fns, 0, 0 }, + { "wsr.epc1", 100 /* xt_iclass_wsr.epc1 */, + 0, + Opcode_wsr_epc1_encode_fns, 0, 0 }, + { "xsr.epc1", 101 /* xt_iclass_xsr.epc1 */, + 0, + Opcode_xsr_epc1_encode_fns, 0, 0 }, + { "rsr.excsave1", 102 /* xt_iclass_rsr.excsave1 */, + 0, + Opcode_rsr_excsave1_encode_fns, 0, 0 }, + { "wsr.excsave1", 103 /* xt_iclass_wsr.excsave1 */, + 0, + Opcode_wsr_excsave1_encode_fns, 0, 0 }, + { "xsr.excsave1", 104 /* xt_iclass_xsr.excsave1 */, + 0, + Opcode_xsr_excsave1_encode_fns, 0, 0 }, + { "rsr.epc2", 105 /* xt_iclass_rsr.epc2 */, + 0, + Opcode_rsr_epc2_encode_fns, 0, 0 }, + { "wsr.epc2", 106 /* xt_iclass_wsr.epc2 */, + 0, + Opcode_wsr_epc2_encode_fns, 0, 0 }, + { "xsr.epc2", 107 /* xt_iclass_xsr.epc2 */, + 0, + Opcode_xsr_epc2_encode_fns, 0, 0 }, + { "rsr.excsave2", 108 /* xt_iclass_rsr.excsave2 */, + 0, + Opcode_rsr_excsave2_encode_fns, 0, 0 }, + { "wsr.excsave2", 109 /* xt_iclass_wsr.excsave2 */, + 0, + Opcode_wsr_excsave2_encode_fns, 0, 0 }, + { "xsr.excsave2", 110 /* xt_iclass_xsr.excsave2 */, + 0, + Opcode_xsr_excsave2_encode_fns, 0, 0 }, + { "rsr.epc3", 111 /* xt_iclass_rsr.epc3 */, + 0, + Opcode_rsr_epc3_encode_fns, 0, 0 }, + { "wsr.epc3", 112 /* xt_iclass_wsr.epc3 */, + 0, + Opcode_wsr_epc3_encode_fns, 0, 0 }, + { "xsr.epc3", 113 /* xt_iclass_xsr.epc3 */, + 0, + Opcode_xsr_epc3_encode_fns, 0, 0 }, + { "rsr.excsave3", 114 /* xt_iclass_rsr.excsave3 */, + 0, + Opcode_rsr_excsave3_encode_fns, 0, 0 }, + { "wsr.excsave3", 115 /* xt_iclass_wsr.excsave3 */, + 0, + Opcode_wsr_excsave3_encode_fns, 0, 0 }, + { "xsr.excsave3", 116 /* xt_iclass_xsr.excsave3 */, + 0, + Opcode_xsr_excsave3_encode_fns, 0, 0 }, + { "rsr.epc4", 117 /* xt_iclass_rsr.epc4 */, + 0, + Opcode_rsr_epc4_encode_fns, 0, 0 }, + { "wsr.epc4", 118 /* xt_iclass_wsr.epc4 */, + 0, + Opcode_wsr_epc4_encode_fns, 0, 0 }, + { "xsr.epc4", 119 /* xt_iclass_xsr.epc4 */, + 0, + Opcode_xsr_epc4_encode_fns, 0, 0 }, + { "rsr.excsave4", 120 /* xt_iclass_rsr.excsave4 */, + 0, + Opcode_rsr_excsave4_encode_fns, 0, 0 }, + { "wsr.excsave4", 121 /* xt_iclass_wsr.excsave4 */, + 0, + Opcode_wsr_excsave4_encode_fns, 0, 0 }, + { "xsr.excsave4", 122 /* xt_iclass_xsr.excsave4 */, + 0, + Opcode_xsr_excsave4_encode_fns, 0, 0 }, + { "rsr.epc5", 123 /* xt_iclass_rsr.epc5 */, + 0, + Opcode_rsr_epc5_encode_fns, 0, 0 }, + { "wsr.epc5", 124 /* xt_iclass_wsr.epc5 */, + 0, + Opcode_wsr_epc5_encode_fns, 0, 0 }, + { "xsr.epc5", 125 /* xt_iclass_xsr.epc5 */, + 0, + Opcode_xsr_epc5_encode_fns, 0, 0 }, + { "rsr.excsave5", 126 /* xt_iclass_rsr.excsave5 */, + 0, + Opcode_rsr_excsave5_encode_fns, 0, 0 }, + { "wsr.excsave5", 127 /* xt_iclass_wsr.excsave5 */, + 0, + Opcode_wsr_excsave5_encode_fns, 0, 0 }, + { "xsr.excsave5", 128 /* xt_iclass_xsr.excsave5 */, + 0, + Opcode_xsr_excsave5_encode_fns, 0, 0 }, + { "rsr.eps2", 129 /* xt_iclass_rsr.eps2 */, + 0, + Opcode_rsr_eps2_encode_fns, 0, 0 }, + { "wsr.eps2", 130 /* xt_iclass_wsr.eps2 */, + 0, + Opcode_wsr_eps2_encode_fns, 0, 0 }, + { "xsr.eps2", 131 /* xt_iclass_xsr.eps2 */, + 0, + Opcode_xsr_eps2_encode_fns, 0, 0 }, + { "rsr.eps3", 132 /* xt_iclass_rsr.eps3 */, + 0, + Opcode_rsr_eps3_encode_fns, 0, 0 }, + { "wsr.eps3", 133 /* xt_iclass_wsr.eps3 */, + 0, + Opcode_wsr_eps3_encode_fns, 0, 0 }, + { "xsr.eps3", 134 /* xt_iclass_xsr.eps3 */, + 0, + Opcode_xsr_eps3_encode_fns, 0, 0 }, + { "rsr.eps4", 135 /* xt_iclass_rsr.eps4 */, + 0, + Opcode_rsr_eps4_encode_fns, 0, 0 }, + { "wsr.eps4", 136 /* xt_iclass_wsr.eps4 */, + 0, + Opcode_wsr_eps4_encode_fns, 0, 0 }, + { "xsr.eps4", 137 /* xt_iclass_xsr.eps4 */, + 0, + Opcode_xsr_eps4_encode_fns, 0, 0 }, + { "rsr.eps5", 138 /* xt_iclass_rsr.eps5 */, + 0, + Opcode_rsr_eps5_encode_fns, 0, 0 }, + { "wsr.eps5", 139 /* xt_iclass_wsr.eps5 */, + 0, + Opcode_wsr_eps5_encode_fns, 0, 0 }, + { "xsr.eps5", 140 /* xt_iclass_xsr.eps5 */, + 0, + Opcode_xsr_eps5_encode_fns, 0, 0 }, + { "rsr.excvaddr", 141 /* xt_iclass_rsr.excvaddr */, + 0, + Opcode_rsr_excvaddr_encode_fns, 0, 0 }, + { "wsr.excvaddr", 142 /* xt_iclass_wsr.excvaddr */, + 0, + Opcode_wsr_excvaddr_encode_fns, 0, 0 }, + { "xsr.excvaddr", 143 /* xt_iclass_xsr.excvaddr */, + 0, + Opcode_xsr_excvaddr_encode_fns, 0, 0 }, + { "rsr.depc", 144 /* xt_iclass_rsr.depc */, + 0, + Opcode_rsr_depc_encode_fns, 0, 0 }, + { "wsr.depc", 145 /* xt_iclass_wsr.depc */, + 0, + Opcode_wsr_depc_encode_fns, 0, 0 }, + { "xsr.depc", 146 /* xt_iclass_xsr.depc */, + 0, + Opcode_xsr_depc_encode_fns, 0, 0 }, + { "rsr.exccause", 147 /* xt_iclass_rsr.exccause */, + 0, + Opcode_rsr_exccause_encode_fns, 0, 0 }, + { "wsr.exccause", 148 /* xt_iclass_wsr.exccause */, + 0, + Opcode_wsr_exccause_encode_fns, 0, 0 }, + { "xsr.exccause", 149 /* xt_iclass_xsr.exccause */, + 0, + Opcode_xsr_exccause_encode_fns, 0, 0 }, + { "rsr.misc0", 150 /* xt_iclass_rsr.misc0 */, + 0, + Opcode_rsr_misc0_encode_fns, 0, 0 }, + { "wsr.misc0", 151 /* xt_iclass_wsr.misc0 */, + 0, + Opcode_wsr_misc0_encode_fns, 0, 0 }, + { "xsr.misc0", 152 /* xt_iclass_xsr.misc0 */, + 0, + Opcode_xsr_misc0_encode_fns, 0, 0 }, + { "rsr.misc1", 153 /* xt_iclass_rsr.misc1 */, + 0, + Opcode_rsr_misc1_encode_fns, 0, 0 }, + { "wsr.misc1", 154 /* xt_iclass_wsr.misc1 */, + 0, + Opcode_wsr_misc1_encode_fns, 0, 0 }, + { "xsr.misc1", 155 /* xt_iclass_xsr.misc1 */, + 0, + Opcode_xsr_misc1_encode_fns, 0, 0 }, + { "rsr.prid", 156 /* xt_iclass_rsr.prid */, + 0, + Opcode_rsr_prid_encode_fns, 0, 0 }, + { "rsr.vecbase", 157 /* xt_iclass_rsr.vecbase */, + 0, + Opcode_rsr_vecbase_encode_fns, 0, 0 }, + { "wsr.vecbase", 158 /* xt_iclass_wsr.vecbase */, + 0, + Opcode_wsr_vecbase_encode_fns, 0, 0 }, + { "xsr.vecbase", 159 /* xt_iclass_xsr.vecbase */, + 0, + Opcode_xsr_vecbase_encode_fns, 0, 0 }, + { "rfi", 160 /* xt_iclass_rfi */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfi_encode_fns, 0, 0 }, + { "waiti", 161 /* xt_iclass_wait */, + 0, + Opcode_waiti_encode_fns, 0, 0 }, + { "rsr.interrupt", 162 /* xt_iclass_rsr.interrupt */, + 0, + Opcode_rsr_interrupt_encode_fns, 0, 0 }, + { "wsr.intset", 163 /* xt_iclass_wsr.intset */, + 0, + Opcode_wsr_intset_encode_fns, 0, 0 }, + { "wsr.intclear", 164 /* xt_iclass_wsr.intclear */, + 0, + Opcode_wsr_intclear_encode_fns, 0, 0 }, + { "rsr.intenable", 165 /* xt_iclass_rsr.intenable */, + 0, + Opcode_rsr_intenable_encode_fns, 0, 0 }, + { "wsr.intenable", 166 /* xt_iclass_wsr.intenable */, + 0, + Opcode_wsr_intenable_encode_fns, 0, 0 }, + { "xsr.intenable", 167 /* xt_iclass_xsr.intenable */, + 0, + Opcode_xsr_intenable_encode_fns, 0, 0 }, + { "break", 168 /* xt_iclass_break */, + 0, + Opcode_break_encode_fns, 0, 0 }, + { "break.n", 169 /* xt_iclass_break.n */, + 0, + Opcode_break_n_encode_fns, 0, 0 }, + { "rsr.dbreaka0", 170 /* xt_iclass_rsr.dbreaka0 */, + 0, + Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, + { "wsr.dbreaka0", 171 /* xt_iclass_wsr.dbreaka0 */, + 0, + Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, + { "xsr.dbreaka0", 172 /* xt_iclass_xsr.dbreaka0 */, + 0, + Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, + { "rsr.dbreakc0", 173 /* xt_iclass_rsr.dbreakc0 */, + 0, + Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, + { "wsr.dbreakc0", 174 /* xt_iclass_wsr.dbreakc0 */, + 0, + Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, + { "xsr.dbreakc0", 175 /* xt_iclass_xsr.dbreakc0 */, + 0, + Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, + { "rsr.dbreaka1", 176 /* xt_iclass_rsr.dbreaka1 */, + 0, + Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, + { "wsr.dbreaka1", 177 /* xt_iclass_wsr.dbreaka1 */, + 0, + Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, + { "xsr.dbreaka1", 178 /* xt_iclass_xsr.dbreaka1 */, + 0, + Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, + { "rsr.dbreakc1", 179 /* xt_iclass_rsr.dbreakc1 */, + 0, + Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, + { "wsr.dbreakc1", 180 /* xt_iclass_wsr.dbreakc1 */, + 0, + Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, + { "xsr.dbreakc1", 181 /* xt_iclass_xsr.dbreakc1 */, + 0, + Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, + { "rsr.ibreaka0", 182 /* xt_iclass_rsr.ibreaka0 */, + 0, + Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, + { "wsr.ibreaka0", 183 /* xt_iclass_wsr.ibreaka0 */, + 0, + Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, + { "xsr.ibreaka0", 184 /* xt_iclass_xsr.ibreaka0 */, + 0, + Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, + { "rsr.ibreaka1", 185 /* xt_iclass_rsr.ibreaka1 */, + 0, + Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, + { "wsr.ibreaka1", 186 /* xt_iclass_wsr.ibreaka1 */, + 0, + Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, + { "xsr.ibreaka1", 187 /* xt_iclass_xsr.ibreaka1 */, + 0, + Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, + { "rsr.ibreakenable", 188 /* xt_iclass_rsr.ibreakenable */, + 0, + Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, + { "wsr.ibreakenable", 189 /* xt_iclass_wsr.ibreakenable */, + 0, + Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, + { "xsr.ibreakenable", 190 /* xt_iclass_xsr.ibreakenable */, + 0, + Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, + { "rsr.debugcause", 191 /* xt_iclass_rsr.debugcause */, + 0, + Opcode_rsr_debugcause_encode_fns, 0, 0 }, + { "wsr.debugcause", 192 /* xt_iclass_wsr.debugcause */, + 0, + Opcode_wsr_debugcause_encode_fns, 0, 0 }, + { "xsr.debugcause", 193 /* xt_iclass_xsr.debugcause */, + 0, + Opcode_xsr_debugcause_encode_fns, 0, 0 }, + { "rsr.icount", 194 /* xt_iclass_rsr.icount */, + 0, + Opcode_rsr_icount_encode_fns, 0, 0 }, + { "wsr.icount", 195 /* xt_iclass_wsr.icount */, + 0, + Opcode_wsr_icount_encode_fns, 0, 0 }, + { "xsr.icount", 196 /* xt_iclass_xsr.icount */, + 0, + Opcode_xsr_icount_encode_fns, 0, 0 }, + { "rsr.icountlevel", 197 /* xt_iclass_rsr.icountlevel */, + 0, + Opcode_rsr_icountlevel_encode_fns, 0, 0 }, + { "wsr.icountlevel", 198 /* xt_iclass_wsr.icountlevel */, + 0, + Opcode_wsr_icountlevel_encode_fns, 0, 0 }, + { "xsr.icountlevel", 199 /* xt_iclass_xsr.icountlevel */, + 0, + Opcode_xsr_icountlevel_encode_fns, 0, 0 }, + { "rsr.ddr", 200 /* xt_iclass_rsr.ddr */, + 0, + Opcode_rsr_ddr_encode_fns, 0, 0 }, + { "wsr.ddr", 201 /* xt_iclass_wsr.ddr */, + 0, + Opcode_wsr_ddr_encode_fns, 0, 0 }, + { "xsr.ddr", 202 /* xt_iclass_xsr.ddr */, + 0, + Opcode_xsr_ddr_encode_fns, 0, 0 }, + { "rfdo", 203 /* xt_iclass_rfdo */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdo_encode_fns, 0, 0 }, + { "rfdd", 204 /* xt_iclass_rfdd */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdd_encode_fns, 0, 0 }, + { "wsr.mmid", 205 /* xt_iclass_wsr.mmid */, + 0, + Opcode_wsr_mmid_encode_fns, 0, 0 }, + { "rsr.ccount", 206 /* xt_iclass_rsr.ccount */, + 0, + Opcode_rsr_ccount_encode_fns, 0, 0 }, + { "wsr.ccount", 207 /* xt_iclass_wsr.ccount */, + 0, + Opcode_wsr_ccount_encode_fns, 0, 0 }, + { "xsr.ccount", 208 /* xt_iclass_xsr.ccount */, + 0, + Opcode_xsr_ccount_encode_fns, 0, 0 }, + { "rsr.ccompare0", 209 /* xt_iclass_rsr.ccompare0 */, + 0, + Opcode_rsr_ccompare0_encode_fns, 0, 0 }, + { "wsr.ccompare0", 210 /* xt_iclass_wsr.ccompare0 */, + 0, + Opcode_wsr_ccompare0_encode_fns, 0, 0 }, + { "xsr.ccompare0", 211 /* xt_iclass_xsr.ccompare0 */, + 0, + Opcode_xsr_ccompare0_encode_fns, 0, 0 }, + { "idtlb", 212 /* xt_iclass_idtlb */, + 0, + Opcode_idtlb_encode_fns, 0, 0 }, + { "pdtlb", 213 /* xt_iclass_rdtlb */, + 0, + Opcode_pdtlb_encode_fns, 0, 0 }, + { "rdtlb0", 213 /* xt_iclass_rdtlb */, + 0, + Opcode_rdtlb0_encode_fns, 0, 0 }, + { "rdtlb1", 213 /* xt_iclass_rdtlb */, + 0, + Opcode_rdtlb1_encode_fns, 0, 0 }, + { "wdtlb", 214 /* xt_iclass_wdtlb */, + 0, + Opcode_wdtlb_encode_fns, 0, 0 }, + { "iitlb", 215 /* xt_iclass_iitlb */, + 0, + Opcode_iitlb_encode_fns, 0, 0 }, + { "pitlb", 216 /* xt_iclass_ritlb */, + 0, + Opcode_pitlb_encode_fns, 0, 0 }, + { "ritlb0", 216 /* xt_iclass_ritlb */, + 0, + Opcode_ritlb0_encode_fns, 0, 0 }, + { "ritlb1", 216 /* xt_iclass_ritlb */, + 0, + Opcode_ritlb1_encode_fns, 0, 0 }, + { "witlb", 217 /* xt_iclass_witlb */, + 0, + Opcode_witlb_encode_fns, 0, 0 }, + { "min", 218 /* xt_iclass_minmax */, + 0, + Opcode_min_encode_fns, 0, 0 }, + { "max", 218 /* xt_iclass_minmax */, + 0, + Opcode_max_encode_fns, 0, 0 }, + { "minu", 218 /* xt_iclass_minmax */, + 0, + Opcode_minu_encode_fns, 0, 0 }, + { "maxu", 218 /* xt_iclass_minmax */, + 0, + Opcode_maxu_encode_fns, 0, 0 }, + { "nsa", 219 /* xt_iclass_nsa */, + 0, + Opcode_nsa_encode_fns, 0, 0 }, + { "nsau", 219 /* xt_iclass_nsa */, + 0, + Opcode_nsau_encode_fns, 0, 0 }, + { "sext", 220 /* xt_iclass_sx */, + 0, + Opcode_sext_encode_fns, 0, 0 }, + { "l32ai", 221 /* xt_iclass_l32ai */, + 0, + Opcode_l32ai_encode_fns, 0, 0 }, + { "s32ri", 222 /* xt_iclass_s32ri */, + 0, + Opcode_s32ri_encode_fns, 0, 0 }, + { "s32c1i", 223 /* xt_iclass_s32c1i */, + 0, + Opcode_s32c1i_encode_fns, 0, 0 }, + { "rsr.scompare1", 224 /* xt_iclass_rsr.scompare1 */, + 0, + Opcode_rsr_scompare1_encode_fns, 0, 0 }, + { "wsr.scompare1", 225 /* xt_iclass_wsr.scompare1 */, + 0, + Opcode_wsr_scompare1_encode_fns, 0, 0 }, + { "xsr.scompare1", 226 /* xt_iclass_xsr.scompare1 */, + 0, + Opcode_xsr_scompare1_encode_fns, 0, 0 }, + { "mull", 227 /* xt_mul32 */, + 0, + Opcode_mull_encode_fns, 0, 0 }, + { "muluh", 227 /* xt_mul32 */, + 0, + Opcode_muluh_encode_fns, 0, 0 }, + { "mulsh", 227 /* xt_mul32 */, + 0, + Opcode_mulsh_encode_fns, 0, 0 }, + { "mul16u", 227 /* xt_mul32 */, + 0, + Opcode_mul16u_encode_fns, 0, 0 }, + { "mul16s", 227 /* xt_mul32 */, + 0, + Opcode_mul16s_encode_fns, 0, 0 } }; -static xtensa_set_field_fn -Slot_xt_flix64_slot0_set_field_fns[] = { - Field_t_Slot_xt_flix64_slot0_set, - 0, - 0, - 0, - Field_imm8_Slot_xt_flix64_slot0_set, - Field_s_Slot_xt_flix64_slot0_set, - Field_imm12b_Slot_xt_flix64_slot0_set, - Field_imm16_Slot_xt_flix64_slot0_set, - Field_m_Slot_xt_flix64_slot0_set, - Field_n_Slot_xt_flix64_slot0_set, - 0, - 0, - Field_op1_Slot_xt_flix64_slot0_set, - Field_op2_Slot_xt_flix64_slot0_set, - Field_r_Slot_xt_flix64_slot0_set, - 0, - Field_sae4_Slot_xt_flix64_slot0_set, - Field_sae_Slot_xt_flix64_slot0_set, - Field_sal_Slot_xt_flix64_slot0_set, - Field_sargt_Slot_xt_flix64_slot0_set, - 0, - Field_sas_Slot_xt_flix64_slot0_set, - 0, - 0, - Field_thi3_Slot_xt_flix64_slot0_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_set, - Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_set, - Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_set, - Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_set, - Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_set, - Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; + +/* Slot-specific opcode decode functions. */ -static xtensa_get_field_fn -Slot_xt_flix64_slot1_get_field_fns[] = { - Field_t_Slot_xt_flix64_slot1_get, - 0, - 0, - 0, - Field_imm8_Slot_xt_flix64_slot1_get, - Field_s_Slot_xt_flix64_slot1_get, - Field_imm12b_Slot_xt_flix64_slot1_get, - 0, - 0, - 0, - Field_offset_Slot_xt_flix64_slot1_get, - 0, - 0, - Field_op2_Slot_xt_flix64_slot1_get, - Field_r_Slot_xt_flix64_slot1_get, - 0, - 0, - Field_sae_Slot_xt_flix64_slot1_get, - Field_sal_Slot_xt_flix64_slot1_get, - Field_sargt_Slot_xt_flix64_slot1_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_op0_s4_Slot_xt_flix64_slot1_get, - Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_get, - Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_get, - Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_get, - Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_get, - Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_get, - Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_get, - Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_get, - Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_get, - Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_get, - Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_get, - Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_get, - Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_get, - Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_get, - Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_get, - Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_get, - Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get, - Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_get, - Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_get, - Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_get, - Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_get, - Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_mr0_get, - Implicit_Field_mr1_get, - Implicit_Field_mr2_get, - Implicit_Field_mr3_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get -}; +static int +Slot_inst_decode (const xtensa_insnbuf insn) +{ + switch (Field_op0_Slot_inst_get (insn)) + { + case 0: + switch (Field_op1_Slot_inst_get (insn)) + { + case 0: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + switch (Field_m_Slot_inst_get (insn)) + { + case 0: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_n_Slot_inst_get (insn) == 0) + return 79; /* ill */ + break; + case 2: + switch (Field_n_Slot_inst_get (insn)) + { + case 0: + return 98; /* ret */ + case 1: + return 14; /* retw */ + case 2: + return 81; /* jx */ + } + break; + case 3: + switch (Field_n_Slot_inst_get (insn)) + { + case 0: + return 77; /* callx0 */ + case 1: + return 10; /* callx4 */ + case 2: + return 9; /* callx8 */ + case 3: + return 8; /* callx12 */ + } + break; + } + break; + case 1: + return 12; /* movsp */ + case 2: + if (Field_s_Slot_inst_get (insn) == 0) + { + switch (Field_t_Slot_inst_get (insn)) + { + case 0: + return 116; /* isync */ + case 1: + return 117; /* rsync */ + case 2: + return 118; /* esync */ + case 3: + return 119; /* dsync */ + case 8: + return 0; /* excw */ + case 12: + return 114; /* memw */ + case 13: + return 115; /* extw */ + case 15: + return 97; /* nop */ + } + } + break; + case 3: + switch (Field_t_Slot_inst_get (insn)) + { + case 0: + switch (Field_s_Slot_inst_get (insn)) + { + case 0: + return 1; /* rfe */ + case 2: + return 2; /* rfde */ + case 4: + return 16; /* rfwo */ + case 5: + return 17; /* rfwu */ + } + break; + case 1: + return 202; /* rfi */ + } + break; + case 4: + return 210; /* break */ + case 5: + switch (Field_s_Slot_inst_get (insn)) + { + case 0: + if (Field_t_Slot_inst_get (insn) == 0) + return 3; /* syscall */ + break; + case 1: + if (Field_t_Slot_inst_get (insn) == 0) + return 4; /* simcall */ + break; + } + break; + case 6: + return 120; /* rsil */ + case 7: + if (Field_t_Slot_inst_get (insn) == 0) + return 203; /* waiti */ + break; + } + break; + case 1: + return 49; /* and */ + case 2: + return 50; /* or */ + case 3: + return 51; /* xor */ + case 4: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + if (Field_t_Slot_inst_get (insn) == 0) + return 102; /* ssr */ + break; + case 1: + if (Field_t_Slot_inst_get (insn) == 0) + return 103; /* ssl */ + break; + case 2: + if (Field_t_Slot_inst_get (insn) == 0) + return 104; /* ssa8l */ + break; + case 3: + if (Field_t_Slot_inst_get (insn) == 0) + return 105; /* ssa8b */ + break; + case 4: + if (Field_thi3_Slot_inst_get (insn) == 0) + return 106; /* ssai */ + break; + case 8: + if (Field_s_Slot_inst_get (insn) == 0) + return 13; /* rotw */ + break; + case 14: + return 268; /* nsa */ + case 15: + return 269; /* nsau */ + } + break; + case 5: + switch (Field_r_Slot_inst_get (insn)) + { + case 3: + return 261; /* ritlb0 */ + case 4: + if (Field_t_Slot_inst_get (insn) == 0) + return 259; /* iitlb */ + break; + case 5: + return 260; /* pitlb */ + case 6: + return 263; /* witlb */ + case 7: + return 262; /* ritlb1 */ + case 11: + return 256; /* rdtlb0 */ + case 12: + if (Field_t_Slot_inst_get (insn) == 0) + return 254; /* idtlb */ + break; + case 13: + return 255; /* pdtlb */ + case 14: + return 258; /* wdtlb */ + case 15: + return 257; /* rdtlb1 */ + } + break; + case 6: + switch (Field_s_Slot_inst_get (insn)) + { + case 0: + return 95; /* neg */ + case 1: + return 96; /* abs */ + } + break; + case 8: + return 41; /* add */ + case 9: + return 43; /* addx2 */ + case 10: + return 44; /* addx4 */ + case 11: + return 45; /* addx8 */ + case 12: + return 42; /* sub */ + case 13: + return 46; /* subx2 */ + case 14: + return 47; /* subx4 */ + case 15: + return 48; /* subx8 */ + } + break; + case 1: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + case 1: + return 111; /* slli */ + case 2: + case 3: + return 112; /* srai */ + case 4: + return 113; /* srli */ + case 6: + switch (Field_sr_Slot_inst_get (insn)) + { + case 0: + return 129; /* xsr.lbeg */ + case 1: + return 123; /* xsr.lend */ + case 2: + return 126; /* xsr.lcount */ + case 3: + return 132; /* xsr.sar */ + case 5: + return 135; /* xsr.litbase */ + case 12: + return 276; /* xsr.scompare1 */ + case 72: + return 22; /* xsr.windowbase */ + case 73: + return 25; /* xsr.windowstart */ + case 96: + return 232; /* xsr.ibreakenable */ + case 104: + return 244; /* xsr.ddr */ + case 128: + return 226; /* xsr.ibreaka0 */ + case 129: + return 229; /* xsr.ibreaka1 */ + case 144: + return 214; /* xsr.dbreaka0 */ + case 145: + return 220; /* xsr.dbreaka1 */ + case 160: + return 217; /* xsr.dbreakc0 */ + case 161: + return 223; /* xsr.dbreakc1 */ + case 177: + return 143; /* xsr.epc1 */ + case 178: + return 149; /* xsr.epc2 */ + case 179: + return 155; /* xsr.epc3 */ + case 180: + return 161; /* xsr.epc4 */ + case 181: + return 167; /* xsr.epc5 */ + case 192: + return 188; /* xsr.depc */ + case 194: + return 173; /* xsr.eps2 */ + case 195: + return 176; /* xsr.eps3 */ + case 196: + return 179; /* xsr.eps4 */ + case 197: + return 182; /* xsr.eps5 */ + case 209: + return 146; /* xsr.excsave1 */ + case 210: + return 152; /* xsr.excsave2 */ + case 211: + return 158; /* xsr.excsave3 */ + case 212: + return 164; /* xsr.excsave4 */ + case 213: + return 170; /* xsr.excsave5 */ + case 228: + return 209; /* xsr.intenable */ + case 230: + return 140; /* xsr.ps */ + case 231: + return 201; /* xsr.vecbase */ + case 232: + return 191; /* xsr.exccause */ + case 233: + return 235; /* xsr.debugcause */ + case 234: + return 250; /* xsr.ccount */ + case 236: + return 238; /* xsr.icount */ + case 237: + return 241; /* xsr.icountlevel */ + case 238: + return 185; /* xsr.excvaddr */ + case 240: + return 253; /* xsr.ccompare0 */ + case 244: + return 194; /* xsr.misc0 */ + case 245: + return 197; /* xsr.misc1 */ + } + break; + case 8: + return 108; /* src */ + case 9: + if (Field_s_Slot_inst_get (insn) == 0) + return 109; /* srl */ + break; + case 10: + if (Field_t_Slot_inst_get (insn) == 0) + return 107; /* sll */ + break; + case 11: + if (Field_s_Slot_inst_get (insn) == 0) + return 110; /* sra */ + break; + case 12: + return 280; /* mul16u */ + case 13: + return 281; /* mul16s */ + case 15: + switch (Field_r_Slot_inst_get (insn)) + { + case 14: + if (Field_t_Slot_inst_get (insn) == 0) + return 245; /* rfdo */ + if (Field_t_Slot_inst_get (insn) == 1) + return 246; /* rfdd */ + break; + } + break; + } + break; + case 2: + switch (Field_op2_Slot_inst_get (insn)) + { + case 8: + return 277; /* mull */ + case 10: + return 278; /* muluh */ + case 11: + return 279; /* mulsh */ + } + break; + case 3: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + switch (Field_sr_Slot_inst_get (insn)) + { + case 0: + return 127; /* rsr.lbeg */ + case 1: + return 121; /* rsr.lend */ + case 2: + return 124; /* rsr.lcount */ + case 3: + return 130; /* rsr.sar */ + case 5: + return 133; /* rsr.litbase */ + case 12: + return 274; /* rsr.scompare1 */ + case 72: + return 20; /* rsr.windowbase */ + case 73: + return 23; /* rsr.windowstart */ + case 96: + return 230; /* rsr.ibreakenable */ + case 104: + return 242; /* rsr.ddr */ + case 128: + return 224; /* rsr.ibreaka0 */ + case 129: + return 227; /* rsr.ibreaka1 */ + case 144: + return 212; /* rsr.dbreaka0 */ + case 145: + return 218; /* rsr.dbreaka1 */ + case 160: + return 215; /* rsr.dbreakc0 */ + case 161: + return 221; /* rsr.dbreakc1 */ + case 176: + return 136; /* rsr.176 */ + case 177: + return 141; /* rsr.epc1 */ + case 178: + return 147; /* rsr.epc2 */ + case 179: + return 153; /* rsr.epc3 */ + case 180: + return 159; /* rsr.epc4 */ + case 181: + return 165; /* rsr.epc5 */ + case 192: + return 186; /* rsr.depc */ + case 194: + return 171; /* rsr.eps2 */ + case 195: + return 174; /* rsr.eps3 */ + case 196: + return 177; /* rsr.eps4 */ + case 197: + return 180; /* rsr.eps5 */ + case 208: + return 137; /* rsr.208 */ + case 209: + return 144; /* rsr.excsave1 */ + case 210: + return 150; /* rsr.excsave2 */ + case 211: + return 156; /* rsr.excsave3 */ + case 212: + return 162; /* rsr.excsave4 */ + case 213: + return 168; /* rsr.excsave5 */ + case 226: + return 204; /* rsr.interrupt */ + case 228: + return 207; /* rsr.intenable */ + case 230: + return 138; /* rsr.ps */ + case 231: + return 199; /* rsr.vecbase */ + case 232: + return 189; /* rsr.exccause */ + case 233: + return 233; /* rsr.debugcause */ + case 234: + return 248; /* rsr.ccount */ + case 235: + return 198; /* rsr.prid */ + case 236: + return 236; /* rsr.icount */ + case 237: + return 239; /* rsr.icountlevel */ + case 238: + return 183; /* rsr.excvaddr */ + case 240: + return 251; /* rsr.ccompare0 */ + case 244: + return 192; /* rsr.misc0 */ + case 245: + return 195; /* rsr.misc1 */ + } + break; + case 1: + switch (Field_sr_Slot_inst_get (insn)) + { + case 0: + return 128; /* wsr.lbeg */ + case 1: + return 122; /* wsr.lend */ + case 2: + return 125; /* wsr.lcount */ + case 3: + return 131; /* wsr.sar */ + case 5: + return 134; /* wsr.litbase */ + case 12: + return 275; /* wsr.scompare1 */ + case 72: + return 21; /* wsr.windowbase */ + case 73: + return 24; /* wsr.windowstart */ + case 89: + return 247; /* wsr.mmid */ + case 96: + return 231; /* wsr.ibreakenable */ + case 104: + return 243; /* wsr.ddr */ + case 128: + return 225; /* wsr.ibreaka0 */ + case 129: + return 228; /* wsr.ibreaka1 */ + case 144: + return 213; /* wsr.dbreaka0 */ + case 145: + return 219; /* wsr.dbreaka1 */ + case 160: + return 216; /* wsr.dbreakc0 */ + case 161: + return 222; /* wsr.dbreakc1 */ + case 177: + return 142; /* wsr.epc1 */ + case 178: + return 148; /* wsr.epc2 */ + case 179: + return 154; /* wsr.epc3 */ + case 180: + return 160; /* wsr.epc4 */ + case 181: + return 166; /* wsr.epc5 */ + case 192: + return 187; /* wsr.depc */ + case 194: + return 172; /* wsr.eps2 */ + case 195: + return 175; /* wsr.eps3 */ + case 196: + return 178; /* wsr.eps4 */ + case 197: + return 181; /* wsr.eps5 */ + case 209: + return 145; /* wsr.excsave1 */ + case 210: + return 151; /* wsr.excsave2 */ + case 211: + return 157; /* wsr.excsave3 */ + case 212: + return 163; /* wsr.excsave4 */ + case 213: + return 169; /* wsr.excsave5 */ + case 226: + return 205; /* wsr.intset */ + case 227: + return 206; /* wsr.intclear */ + case 228: + return 208; /* wsr.intenable */ + case 230: + return 139; /* wsr.ps */ + case 231: + return 200; /* wsr.vecbase */ + case 232: + return 190; /* wsr.exccause */ + case 233: + return 234; /* wsr.debugcause */ + case 234: + return 249; /* wsr.ccount */ + case 236: + return 237; /* wsr.icount */ + case 237: + return 240; /* wsr.icountlevel */ + case 238: + return 184; /* wsr.excvaddr */ + case 240: + return 252; /* wsr.ccompare0 */ + case 244: + return 193; /* wsr.misc0 */ + case 245: + return 196; /* wsr.misc1 */ + } + break; + case 2: + return 270; /* sext */ + case 4: + return 264; /* min */ + case 5: + return 265; /* max */ + case 6: + return 266; /* minu */ + case 7: + return 267; /* maxu */ + case 8: + return 91; /* moveqz */ + case 9: + return 92; /* movnez */ + case 10: + return 93; /* movltz */ + case 11: + return 94; /* movgez */ + case 14: + if (Field_st_Slot_inst_get (insn) == 231) + return 37; /* rur.threadptr */ + break; + case 15: + if (Field_sr_Slot_inst_get (insn) == 231) + return 38; /* wur.threadptr */ + break; + } + break; + case 4: + case 5: + return 78; /* extui */ + case 9: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + return 18; /* l32e */ + case 4: + return 19; /* s32e */ + } + break; + } + break; + case 1: + return 85; /* l32r */ + case 2: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + return 86; /* l8ui */ + case 1: + return 82; /* l16ui */ + case 2: + return 84; /* l32i */ + case 4: + return 101; /* s8i */ + case 5: + return 99; /* s16i */ + case 6: + return 100; /* s32i */ + case 9: + return 83; /* l16si */ + case 10: + return 90; /* movi */ + case 11: + return 271; /* l32ai */ + case 12: + return 39; /* addi */ + case 13: + return 40; /* addmi */ + case 14: + return 273; /* s32c1i */ + case 15: + return 272; /* s32ri */ + } + break; + case 5: + switch (Field_n_Slot_inst_get (insn)) + { + case 0: + return 76; /* call0 */ + case 1: + return 7; /* call4 */ + case 2: + return 6; /* call8 */ + case 3: + return 5; /* call12 */ + } + break; + case 6: + switch (Field_n_Slot_inst_get (insn)) + { + case 0: + return 80; /* j */ + case 1: + switch (Field_m_Slot_inst_get (insn)) + { + case 0: + return 72; /* beqz */ + case 1: + return 73; /* bnez */ + case 2: + return 75; /* bltz */ + case 3: + return 74; /* bgez */ + } + break; + case 2: + switch (Field_m_Slot_inst_get (insn)) + { + case 0: + return 52; /* beqi */ + case 1: + return 53; /* bnei */ + case 2: + return 55; /* blti */ + case 3: + return 54; /* bgei */ + } + break; + case 3: + switch (Field_m_Slot_inst_get (insn)) + { + case 0: + return 11; /* entry */ + case 1: + switch (Field_r_Slot_inst_get (insn)) + { + case 8: + return 87; /* loop */ + case 9: + return 88; /* loopnez */ + case 10: + return 89; /* loopgtz */ + } + break; + case 2: + return 59; /* bltui */ + case 3: + return 58; /* bgeui */ + } + break; + } + break; + case 7: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + return 67; /* bnone */ + case 1: + return 60; /* beq */ + case 2: + return 63; /* blt */ + case 3: + return 65; /* bltu */ + case 4: + return 68; /* ball */ + case 5: + return 70; /* bbc */ + case 6: + case 7: + return 56; /* bbci */ + case 8: + return 66; /* bany */ + case 9: + return 61; /* bne */ + case 10: + return 62; /* bge */ + case 11: + return 64; /* bgeu */ + case 12: + return 69; /* bnall */ + case 13: + return 71; /* bbs */ + case 14: + case 15: + return 57; /* bbsi */ + } + break; + } + return 0; +} -static xtensa_set_field_fn -Slot_xt_flix64_slot1_set_field_fns[] = { - Field_t_Slot_xt_flix64_slot1_set, - 0, - 0, - 0, - Field_imm8_Slot_xt_flix64_slot1_set, - Field_s_Slot_xt_flix64_slot1_set, - Field_imm12b_Slot_xt_flix64_slot1_set, - 0, - 0, - 0, - Field_offset_Slot_xt_flix64_slot1_set, - 0, - 0, - Field_op2_Slot_xt_flix64_slot1_set, - Field_r_Slot_xt_flix64_slot1_set, - 0, - 0, - Field_sae_Slot_xt_flix64_slot1_set, - Field_sal_Slot_xt_flix64_slot1_set, - Field_sargt_Slot_xt_flix64_slot1_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_op0_s4_Slot_xt_flix64_slot1_set, - Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_set, - Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_set, - Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_set, - Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_set, - Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_set, - Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_set, - Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_set, - Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_set, - Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_set, - Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_set, - Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_set, - Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_set, - Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_set, - Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_set, - Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_set, - Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_set, - Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_set, - Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_set, - Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_set, - Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_set, - Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; +static int +Slot_inst16b_decode (const xtensa_insnbuf insn) +{ + switch (Field_op0_Slot_inst16b_get (insn)) + { + case 12: + switch (Field_i_Slot_inst16b_get (insn)) + { + case 0: + return 33; /* movi.n */ + case 1: + switch (Field_z_Slot_inst16b_get (insn)) + { + case 0: + return 28; /* beqz.n */ + case 1: + return 29; /* bnez.n */ + } + break; + } + break; + case 13: + switch (Field_r_Slot_inst16b_get (insn)) + { + case 0: + return 32; /* mov.n */ + case 15: + switch (Field_t_Slot_inst16b_get (insn)) + { + case 0: + return 35; /* ret.n */ + case 1: + return 15; /* retw.n */ + case 2: + return 211; /* break.n */ + case 3: + if (Field_s_Slot_inst16b_get (insn) == 0) + return 34; /* nop.n */ + break; + case 6: + if (Field_s_Slot_inst16b_get (insn) == 0) + return 30; /* ill.n */ + break; + } + break; + } + break; + } + return 0; +} + +static int +Slot_inst16a_decode (const xtensa_insnbuf insn) +{ + switch (Field_op0_Slot_inst16a_get (insn)) + { + case 8: + return 31; /* l32i.n */ + case 9: + return 36; /* s32i.n */ + case 10: + return 26; /* add.n */ + case 11: + return 27; /* addi.n */ + } + return 0; +} -static xtensa_get_field_fn -Slot_xt_flix64_slot2_get_field_fns[] = { - Field_t_Slot_xt_flix64_slot2_get, - 0, - 0, - 0, - 0, - Field_s_Slot_xt_flix64_slot2_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_r_Slot_xt_flix64_slot2_get, - 0, - 0, - 0, - 0, - Field_sargt_Slot_xt_flix64_slot2_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_imm7_Slot_xt_flix64_slot2_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_op0_s5_Slot_xt_flix64_slot2_get, - Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_get, - Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_get, - Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_get, - Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_get, - Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_get, - Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_get, - Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_get, - Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_get, - Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_get, - Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get, - Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_get, - Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_get, - Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_mr0_get, - Implicit_Field_mr1_get, - Implicit_Field_mr2_get, - Implicit_Field_mr3_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get -}; + +/* Instruction slots. */ -static xtensa_set_field_fn -Slot_xt_flix64_slot2_set_field_fns[] = { - Field_t_Slot_xt_flix64_slot2_set, - 0, - 0, - 0, - 0, - Field_s_Slot_xt_flix64_slot2_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_r_Slot_xt_flix64_slot2_set, - 0, - 0, - 0, - 0, - Field_sargt_Slot_xt_flix64_slot2_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_imm7_Slot_xt_flix64_slot2_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_op0_s5_Slot_xt_flix64_slot2_set, - Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_set, - Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_set, - Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_set, - Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_set, - Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_set, - Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_set, - Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_set, - Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_set, - Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_set, - Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_set, - Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_set, - Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_set, - Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, +static void +Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[0] = (insn[0] & 0xffffff); +} + +static void +Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); +} + +static void +Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[0] = ((insn[0] & 0xffff00) >> 8); +} + +static void +Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8); +} + +static void +Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[0] = ((insn[0] & 0xffff00) >> 8); +} + +static void +Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8); +} + +static xtensa_get_field_fn +Slot_inst_get_field_fns[] = { + Field_t_Slot_inst_get, + Field_bbi4_Slot_inst_get, + Field_bbi_Slot_inst_get, + Field_imm12_Slot_inst_get, + Field_imm8_Slot_inst_get, + Field_s_Slot_inst_get, + Field_imm12b_Slot_inst_get, + Field_imm16_Slot_inst_get, + Field_m_Slot_inst_get, + Field_n_Slot_inst_get, + Field_offset_Slot_inst_get, + Field_op0_Slot_inst_get, + Field_op1_Slot_inst_get, + Field_op2_Slot_inst_get, + Field_r_Slot_inst_get, + Field_sa4_Slot_inst_get, + Field_sae4_Slot_inst_get, + Field_sae_Slot_inst_get, + Field_sal_Slot_inst_get, + Field_sargt_Slot_inst_get, + Field_sas4_Slot_inst_get, + Field_sas_Slot_inst_get, + Field_sr_Slot_inst_get, + Field_st_Slot_inst_get, + Field_thi3_Slot_inst_get, + Field_imm4_Slot_inst_get, + Field_mn_Slot_inst_get, 0, 0, 0, @@ -20837,6 +9122,43 @@ Slot_xt_flix64_slot2_set_field_fns[] = { 0, 0, 0, + Field_xt_wbr15_imm_Slot_inst_get, + Field_xt_wbr18_imm_Slot_inst_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get +}; + +static xtensa_set_field_fn +Slot_inst_set_field_fns[] = { + Field_t_Slot_inst_set, + Field_bbi4_Slot_inst_set, + Field_bbi_Slot_inst_set, + Field_imm12_Slot_inst_set, + Field_imm8_Slot_inst_set, + Field_s_Slot_inst_set, + Field_imm12b_Slot_inst_set, + Field_imm16_Slot_inst_set, + Field_m_Slot_inst_set, + Field_n_Slot_inst_set, + Field_offset_Slot_inst_set, + Field_op0_Slot_inst_set, + Field_op1_Slot_inst_set, + Field_op2_Slot_inst_set, + Field_r_Slot_inst_set, + Field_sa4_Slot_inst_set, + Field_sae4_Slot_inst_set, + Field_sae_Slot_inst_set, + Field_sal_Slot_inst_set, + Field_sargt_Slot_inst_set, + Field_sas4_Slot_inst_set, + Field_sas_Slot_inst_set, + Field_sr_Slot_inst_set, + Field_st_Slot_inst_set, + Field_thi3_Slot_inst_set, + Field_imm4_Slot_inst_set, + Field_mn_Slot_inst_set, 0, 0, 0, @@ -20845,14 +9167,8 @@ Slot_xt_flix64_slot2_set_field_fns[] = { 0, 0, 0, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, + Field_xt_wbr15_imm_Slot_inst_set, + Field_xt_wbr18_imm_Slot_inst_set, Implicit_Field_set, Implicit_Field_set, Implicit_Field_set, @@ -20860,94 +9176,22 @@ Slot_xt_flix64_slot2_set_field_fns[] = { }; static xtensa_get_field_fn -Slot_xt_flix64_slot3_get_field_fns[] = { - Field_t_Slot_xt_flix64_slot3_get, - 0, - Field_bbi_Slot_xt_flix64_slot3_get, - 0, - 0, - Field_s_Slot_xt_flix64_slot3_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_r_Slot_xt_flix64_slot3_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_xt_wbr18_imm_Slot_xt_flix64_slot3_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, +Slot_inst16a_get_field_fns[] = { + Field_t_Slot_inst16a_get, 0, 0, 0, 0, + Field_s_Slot_inst16a_get, 0, 0, 0, 0, 0, + Field_op0_Slot_inst16a_get, 0, 0, + Field_r_Slot_inst16a_get, 0, 0, 0, @@ -20955,93 +9199,44 @@ Slot_xt_flix64_slot3_get_field_fns[] = { 0, 0, 0, + Field_sr_Slot_inst16a_get, + Field_st_Slot_inst16a_get, 0, + Field_imm4_Slot_inst16a_get, 0, + Field_i_Slot_inst16a_get, + Field_imm6lo_Slot_inst16a_get, + Field_imm6hi_Slot_inst16a_get, + Field_imm7lo_Slot_inst16a_get, + Field_imm7hi_Slot_inst16a_get, + Field_z_Slot_inst16a_get, + Field_imm6_Slot_inst16a_get, + Field_imm7_Slot_inst16a_get, 0, - Field_op0_s6_Slot_xt_flix64_slot3_get, - Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_get, - Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get, - Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_get, - Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_get, - Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_get, - Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_get, - Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_get, - Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_get, - Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_get, - Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_get, - Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_get, - Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_get, - Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_get, - Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_get, - Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_get, - Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_get, - Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_get, - Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_get, - Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_get, - Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_get, - Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_get, - Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_get, - Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_get, - Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_get, 0, Implicit_Field_ar0_get, Implicit_Field_ar4_get, Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_mr0_get, - Implicit_Field_mr1_get, - Implicit_Field_mr2_get, - Implicit_Field_mr3_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get + Implicit_Field_ar12_get }; static xtensa_set_field_fn -Slot_xt_flix64_slot3_set_field_fns[] = { - Field_t_Slot_xt_flix64_slot3_set, - 0, - Field_bbi_Slot_xt_flix64_slot3_set, - 0, - 0, - Field_s_Slot_xt_flix64_slot3_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_r_Slot_xt_flix64_slot3_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, +Slot_inst16a_set_field_fns[] = { + Field_t_Slot_inst16a_set, 0, 0, 0, 0, + Field_s_Slot_inst16a_set, 0, 0, 0, 0, 0, + Field_op0_Slot_inst16a_set, 0, 0, + Field_r_Slot_inst16a_set, 0, 0, 0, @@ -21049,22 +9244,44 @@ Slot_xt_flix64_slot3_set_field_fns[] = { 0, 0, 0, + Field_sr_Slot_inst16a_set, + Field_st_Slot_inst16a_set, 0, + Field_imm4_Slot_inst16a_set, 0, + Field_i_Slot_inst16a_set, + Field_imm6lo_Slot_inst16a_set, + Field_imm6hi_Slot_inst16a_set, + Field_imm7lo_Slot_inst16a_set, + Field_imm7hi_Slot_inst16a_set, + Field_z_Slot_inst16a_set, + Field_imm6_Slot_inst16a_set, + Field_imm7_Slot_inst16a_set, 0, 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16b_get_field_fns[] = { + Field_t_Slot_inst16b_get, 0, - Field_xt_wbr18_imm_Slot_xt_flix64_slot3_set, 0, 0, 0, + Field_s_Slot_inst16b_get, 0, 0, 0, 0, 0, + Field_op0_Slot_inst16b_get, 0, 0, + Field_r_Slot_inst16b_get, 0, 0, 0, @@ -21072,21 +9289,44 @@ Slot_xt_flix64_slot3_set_field_fns[] = { 0, 0, 0, + Field_sr_Slot_inst16b_get, + Field_st_Slot_inst16b_get, 0, + Field_imm4_Slot_inst16b_get, 0, + Field_i_Slot_inst16b_get, + Field_imm6lo_Slot_inst16b_get, + Field_imm6hi_Slot_inst16b_get, + Field_imm7lo_Slot_inst16b_get, + Field_imm7hi_Slot_inst16b_get, + Field_z_Slot_inst16b_get, + Field_imm6_Slot_inst16b_get, + Field_imm7_Slot_inst16b_get, 0, 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get +}; + +static xtensa_set_field_fn +Slot_inst16b_set_field_fns[] = { + Field_t_Slot_inst16b_set, 0, 0, 0, 0, + Field_s_Slot_inst16b_set, 0, 0, 0, 0, 0, + Field_op0_Slot_inst16b_set, 0, 0, + Field_r_Slot_inst16b_set, 0, 0, 0, @@ -21094,46 +9334,24 @@ Slot_xt_flix64_slot3_set_field_fns[] = { 0, 0, 0, + Field_sr_Slot_inst16b_set, + Field_st_Slot_inst16b_set, 0, + Field_imm4_Slot_inst16b_set, 0, + Field_i_Slot_inst16b_set, + Field_imm6lo_Slot_inst16b_set, + Field_imm6hi_Slot_inst16b_set, + Field_imm7lo_Slot_inst16b_set, + Field_imm7hi_Slot_inst16b_set, + Field_z_Slot_inst16b_set, + Field_imm6_Slot_inst16b_set, + Field_imm7_Slot_inst16b_set, 0, - Field_op0_s6_Slot_xt_flix64_slot3_set, - Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_set, - Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_set, - Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_set, - Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_set, - Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_set, - Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_set, - Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_set, - Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_set, - Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_set, - Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_set, - Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_set, - Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_set, - Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_set, - Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_set, - Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_set, - Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_set, - Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_set, - Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_set, - Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_set, - Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_set, - Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_set, - Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_set, - Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_set, - Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_set, 0, Implicit_Field_set, Implicit_Field_set, Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, Implicit_Field_set }; @@ -21149,27 +9367,7 @@ static xtensa_slot_internal slots[] = { { "Inst16b", "x16b", 0, Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, - Slot_inst16b_decode, "nop.n" }, - { "xt_flix64_slot0", "xt_format1", 0, - Slot_xt_format1_Format_xt_flix64_slot0_4_get, Slot_xt_format1_Format_xt_flix64_slot0_4_set, - Slot_xt_flix64_slot0_get_field_fns, Slot_xt_flix64_slot0_set_field_fns, - Slot_xt_flix64_slot0_decode, "nop" }, - { "xt_flix64_slot0", "xt_format2", 0, - Slot_xt_format2_Format_xt_flix64_slot0_4_get, Slot_xt_format2_Format_xt_flix64_slot0_4_set, - Slot_xt_flix64_slot0_get_field_fns, Slot_xt_flix64_slot0_set_field_fns, - Slot_xt_flix64_slot0_decode, "nop" }, - { "xt_flix64_slot1", "xt_format1", 1, - Slot_xt_format1_Format_xt_flix64_slot1_28_get, Slot_xt_format1_Format_xt_flix64_slot1_28_set, - Slot_xt_flix64_slot1_get_field_fns, Slot_xt_flix64_slot1_set_field_fns, - Slot_xt_flix64_slot1_decode, "nop" }, - { "xt_flix64_slot2", "xt_format1", 2, - Slot_xt_format1_Format_xt_flix64_slot2_48_get, Slot_xt_format1_Format_xt_flix64_slot2_48_set, - Slot_xt_flix64_slot2_get_field_fns, Slot_xt_flix64_slot2_set_field_fns, - Slot_xt_flix64_slot2_decode, "nop" }, - { "xt_flix64_slot3", "xt_format2", 1, - Slot_xt_format2_Format_xt_flix64_slot3_28_get, Slot_xt_format2_Format_xt_flix64_slot3_28_set, - Slot_xt_flix64_slot3_get_field_fns, Slot_xt_flix64_slot3_set_field_fns, - Slot_xt_flix64_slot3_decode, "nop" } + Slot_inst16b_decode, "nop.n" } }; @@ -21179,35 +9377,18 @@ static void Format_x24_encode (xtensa_insnbuf insn) { insn[0] = 0; - insn[1] = 0; } static void Format_x16a_encode (xtensa_insnbuf insn) { - insn[0] = 0x8; - insn[1] = 0; + insn[0] = 0x800000; } static void Format_x16b_encode (xtensa_insnbuf insn) { - insn[0] = 0xc; - insn[1] = 0; -} - -static void -Format_xt_format1_encode (xtensa_insnbuf insn) -{ - insn[0] = 0xe; - insn[1] = 0; -} - -static void -Format_xt_format2_encode (xtensa_insnbuf insn) -{ - insn[0] = 0xf; - insn[1] = 0; + insn[0] = 0xc00000; } static int Format_x24_slots[] = { 0 }; @@ -21216,32 +9397,22 @@ static int Format_x16a_slots[] = { 1 }; static int Format_x16b_slots[] = { 2 }; -static int Format_xt_format1_slots[] = { 3, 5, 6 }; - -static int Format_xt_format2_slots[] = { 4, 7 }; - static xtensa_format_internal formats[] = { { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, - { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }, - { "xt_format1", 8, Format_xt_format1_encode, 3, Format_xt_format1_slots }, - { "xt_format2", 8, Format_xt_format2_encode, 2, Format_xt_format2_slots } + { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots } }; static int format_decoder (const xtensa_insnbuf insn) { - if ((insn[0] & 0x8) == 0 && (insn[1] & 0) == 0) + if ((insn[0] & 0x800000) == 0) return 0; /* x24 */ - if ((insn[0] & 0xc) == 0x8 && (insn[1] & 0) == 0) + if ((insn[0] & 0xc00000) == 0x800000) return 1; /* x16a */ - if ((insn[0] & 0xe) == 0xc && (insn[1] & 0) == 0) + if ((insn[0] & 0xe00000) == 0xc00000) return 2; /* x16b */ - if ((insn[0] & 0xf) == 0xe && (insn[1] & 0) == 0) - return 3; /* xt_format1 */ - if ((insn[0] & 0xf) == 0xf && (insn[1] & 0x80000000) == 0) - return 4; /* xt_format2 */ return -1; } @@ -21260,14 +9431,14 @@ static int length_table[16] = { 2, 2, 2, - 8, - 8 + -1, + -1 }; static int length_decoder (const unsigned char *insn) { - int op0 = insn[0] & 0xf; + int op0 = (insn[0] >> 4) & 0xf; return length_table[op0]; } @@ -21275,15 +9446,15 @@ length_decoder (const unsigned char *insn) /* Top-level ISA structure. */ xtensa_isa_internal xtensa_modules = { - 0 /* little-endian */, - 8 /* insn_size */, 0, - 5, formats, format_decoder, length_decoder, - 8, slots, - 135 /* num_fields */, - 188, operands, - 355, iclasses, - 530, opcodes, 0, - 8, regfiles, + 1 /* big-endian */, + 3 /* insn_size */, 0, + 3, formats, format_decoder, length_decoder, + 3, slots, + 41 /* num_fields */, + 75, operands, + 228, iclasses, + 282, opcodes, 0, + 1, regfiles, NUM_STATES, states, 0, NUM_SYSREGS, sysregs, 0, { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, diff --git a/include/xtensa-config.h b/include/xtensa-config.h index 30f4f41..fe9b051 100644 --- a/include/xtensa-config.h +++ b/include/xtensa-config.h @@ -44,10 +44,7 @@ #define XCHAL_HAVE_L32R 1 #undef XSHAL_USE_ABSOLUTE_LITERALS -#define XSHAL_USE_ABSOLUTE_LITERALS 0 - -#undef XSHAL_HAVE_TEXT_SECTION_LITERALS -#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ +#define XSHAL_USE_ABSOLUTE_LITERALS 1 #undef XCHAL_HAVE_MAC16 #define XCHAL_HAVE_MAC16 0 @@ -59,10 +56,10 @@ #define XCHAL_HAVE_MUL32 1 #undef XCHAL_HAVE_MUL32_HIGH -#define XCHAL_HAVE_MUL32_HIGH 0 +#define XCHAL_HAVE_MUL32_HIGH 1 #undef XCHAL_HAVE_DIV32 -#define XCHAL_HAVE_DIV32 1 +#define XCHAL_HAVE_DIV32 0 #undef XCHAL_HAVE_NSA #define XCHAL_HAVE_NSA 1 @@ -103,8 +100,6 @@ #undef XCHAL_HAVE_FP_RSQRT #define XCHAL_HAVE_FP_RSQRT 0 -#undef XCHAL_HAVE_DFP_accel -#define XCHAL_HAVE_DFP_accel 0 #undef XCHAL_HAVE_WINDOWED #define XCHAL_HAVE_WINDOWED 1 @@ -119,32 +114,32 @@ #undef XCHAL_ICACHE_SIZE -#define XCHAL_ICACHE_SIZE 16384 +#define XCHAL_ICACHE_SIZE 0 #undef XCHAL_DCACHE_SIZE -#define XCHAL_DCACHE_SIZE 16384 +#define XCHAL_DCACHE_SIZE 0 #undef XCHAL_ICACHE_LINESIZE -#define XCHAL_ICACHE_LINESIZE 32 +#define XCHAL_ICACHE_LINESIZE 16 #undef XCHAL_DCACHE_LINESIZE -#define XCHAL_DCACHE_LINESIZE 32 +#define XCHAL_DCACHE_LINESIZE 16 #undef XCHAL_ICACHE_LINEWIDTH -#define XCHAL_ICACHE_LINEWIDTH 5 +#define XCHAL_ICACHE_LINEWIDTH 4 #undef XCHAL_DCACHE_LINEWIDTH -#define XCHAL_DCACHE_LINEWIDTH 5 +#define XCHAL_DCACHE_LINEWIDTH 4 #undef XCHAL_DCACHE_IS_WRITEBACK -#define XCHAL_DCACHE_IS_WRITEBACK 1 +#define XCHAL_DCACHE_IS_WRITEBACK 0 #undef XCHAL_HAVE_MMU #define XCHAL_HAVE_MMU 1 #undef XCHAL_MMU_MIN_PTE_PAGE_SIZE -#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12 +#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 29 #undef XCHAL_HAVE_DEBUG @@ -157,8 +152,11 @@ #define XCHAL_NUM_DBREAK 2 #undef XCHAL_DEBUGLEVEL -#define XCHAL_DEBUGLEVEL 6 +#define XCHAL_DEBUGLEVEL 4 + +#undef XCHAL_EXCM_LEVEL +#define XCHAL_EXCM_LEVEL 3 #undef XCHAL_MAX_INSTRUCTION_SIZE #define XCHAL_MAX_INSTRUCTION_SIZE 3 -- 1.8.1 open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/local/patches/gcc-6.3.0_fixup.patch000066400000000000000000000033431321570333100265610ustar00rootroot00000000000000diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c index 015dd1049fb..df80ad9117e 100644 --- a/gcc/config/xtensa/xtensa.c +++ b/gcc/config/xtensa/xtensa.c @@ -1780,7 +1780,8 @@ xtensa_emit_call (int callop, rtx *operands) rtx tgt = operands[callop]; if (GET_CODE (tgt) == CONST_INT) - sprintf (result, "call%d\t0x%lx", WINDOW_SIZE, INTVAL (tgt)); + sprintf (result, "call%d\t" HOST_WIDE_INT_PRINT_HEX, + WINDOW_SIZE, INTVAL (tgt)); else if (register_operand (tgt, VOIDmode)) sprintf (result, "callx%d\t%%%d", WINDOW_SIZE, callop); else @@ -2351,14 +2352,14 @@ print_operand (FILE *file, rtx x, int letter) case 'L': if (GET_CODE (x) == CONST_INT) - fprintf (file, "%ld", (32 - INTVAL (x)) & 0x1f); + fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INTVAL (x)) & 0x1f); else output_operand_lossage ("invalid %%L value"); break; case 'R': if (GET_CODE (x) == CONST_INT) - fprintf (file, "%ld", INTVAL (x) & 0x1f); + fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x1f); else output_operand_lossage ("invalid %%R value"); break; @@ -2372,7 +2373,7 @@ print_operand (FILE *file, rtx x, int letter) case 'd': if (GET_CODE (x) == CONST_INT) - fprintf (file, "%ld", INTVAL (x)); + fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x)); else output_operand_lossage ("invalid %%d value"); break; @@ -2437,7 +2438,7 @@ print_operand (FILE *file, rtx x, int letter) else if (GET_CODE (x) == MEM) output_address (GET_MODE (x), XEXP (x, 0)); else if (GET_CODE (x) == CONST_INT) - fprintf (file, "%ld", INTVAL (x)); + fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x)); else output_addr_const (file, x); } open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/local/patches/gcc.patch000066400000000000000000000042741321570333100247100ustar00rootroot00000000000000diff --git a/include/xtensa-config.h b/include/xtensa-config.h index 5ae4c80..8397564 100644 --- a/include/xtensa-config.h +++ b/include/xtensa-config.h @@ -43,10 +43,7 @@ #define XCHAL_HAVE_L32R 1 #undef XSHAL_USE_ABSOLUTE_LITERALS -#define XSHAL_USE_ABSOLUTE_LITERALS 0 - -#undef XSHAL_HAVE_TEXT_SECTION_LITERALS -#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ +#define XSHAL_USE_ABSOLUTE_LITERALS 1 #undef XCHAL_HAVE_MAC16 #define XCHAL_HAVE_MAC16 0 @@ -58,10 +55,10 @@ #define XCHAL_HAVE_MUL32 1 #undef XCHAL_HAVE_MUL32_HIGH -#define XCHAL_HAVE_MUL32_HIGH 0 +#define XCHAL_HAVE_MUL32_HIGH 1 #undef XCHAL_HAVE_DIV32 -#define XCHAL_HAVE_DIV32 1 +#define XCHAL_HAVE_DIV32 0 #undef XCHAL_HAVE_NSA #define XCHAL_HAVE_NSA 1 @@ -102,8 +99,6 @@ #undef XCHAL_HAVE_FP_RSQRT #define XCHAL_HAVE_FP_RSQRT 0 -#undef XCHAL_HAVE_DFP_accel -#define XCHAL_HAVE_DFP_accel 0 #undef XCHAL_HAVE_WINDOWED #define XCHAL_HAVE_WINDOWED 1 @@ -118,32 +113,32 @@ #undef XCHAL_ICACHE_SIZE -#define XCHAL_ICACHE_SIZE 16384 +#define XCHAL_ICACHE_SIZE 0 #undef XCHAL_DCACHE_SIZE -#define XCHAL_DCACHE_SIZE 16384 +#define XCHAL_DCACHE_SIZE 0 #undef XCHAL_ICACHE_LINESIZE -#define XCHAL_ICACHE_LINESIZE 32 +#define XCHAL_ICACHE_LINESIZE 16 #undef XCHAL_DCACHE_LINESIZE -#define XCHAL_DCACHE_LINESIZE 32 +#define XCHAL_DCACHE_LINESIZE 16 #undef XCHAL_ICACHE_LINEWIDTH -#define XCHAL_ICACHE_LINEWIDTH 5 +#define XCHAL_ICACHE_LINEWIDTH 4 #undef XCHAL_DCACHE_LINEWIDTH -#define XCHAL_DCACHE_LINEWIDTH 5 +#define XCHAL_DCACHE_LINEWIDTH 4 #undef XCHAL_DCACHE_IS_WRITEBACK -#define XCHAL_DCACHE_IS_WRITEBACK 1 +#define XCHAL_DCACHE_IS_WRITEBACK 0 #undef XCHAL_HAVE_MMU #define XCHAL_HAVE_MMU 1 #undef XCHAL_MMU_MIN_PTE_PAGE_SIZE -#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12 +#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 29 #undef XCHAL_HAVE_DEBUG @@ -156,8 +151,11 @@ #define XCHAL_NUM_DBREAK 2 #undef XCHAL_DEBUGLEVEL -#define XCHAL_DEBUGLEVEL 6 +#define XCHAL_DEBUGLEVEL 4 + +#undef XCHAL_EXCM_LEVEL +#define XCHAL_EXCM_LEVEL 3 #undef XCHAL_MAX_INSTRUCTION_SIZE #define XCHAL_MAX_INSTRUCTION_SIZE 3 open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/scripts/000077500000000000000000000000001321570333100220725ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/scripts/checkpatch.pl000077500000000000000000003111121321570333100245260ustar00rootroot00000000000000#!/usr/bin/perl -w # (c) 2001, Dave Jones. (the file handling bit) # (c) 2005, Joel Schopp (the ugly bit) # (c) 2007,2008, Andy Whitcroft (new conditions, test suite) # (c) 2008-2010 Andy Whitcroft # Licensed under the terms of the GNU GPL License version 2 use strict; my $P = $0; $P =~ s@.*/@@g; my $V = '0.32'; use Getopt::Long qw(:config no_auto_abbrev); my $quiet = 0; my $tree = 1; my $chk_signoff = 1; my $chk_patch = 1; my $tst_only; my $emacs = 0; my $terse = 0; my $file = 0; my $check = 0; my $summary = 1; my $mailback = 0; my $summary_file = 0; my $show_types = 0; my $root; my %debug; my %ignore_type = (); my @ignore = (); my $help = 0; my $configuration_file = ".checkpatch.conf"; my $max_line_length = 80; sub help { my ($exitcode) = @_; print << "EOM"; Usage: $P [OPTION]... [FILE]... Version: $V Options: -q, --quiet quiet --no-tree run without a kernel tree --no-signoff do not check for 'Signed-off-by' line --patch treat FILE as patchfile (default) --emacs emacs compile window format --terse one line per report -f, --file treat FILE as regular source file --subjective, --strict enable more subjective tests --ignore TYPE(,TYPE2...) ignore various comma separated message types --max-line-length=n set the maximum line length, if exceeded, warn --show-types show the message "types" in the output --root=PATH PATH to the kernel tree root --no-summary suppress the per-file summary --mailback only produce a report in case of warnings/errors --summary-file include the filename in summary --debug KEY=[0|1] turn on/off debugging of KEY, where KEY is one of 'values', 'possible', 'type', and 'attr' (default is all off) --test-only=WORD report only warnings/errors containing WORD literally -h, --help, --version display this help and exit When FILE is - read standard input. EOM exit($exitcode); } my $conf = which_conf($configuration_file); if (-f $conf) { my @conf_args; open(my $conffile, '<', "$conf") or warn "$P: Can't find a readable $configuration_file file $!\n"; while (<$conffile>) { my $line = $_; $line =~ s/\s*\n?$//g; $line =~ s/^\s*//g; $line =~ s/\s+/ /g; next if ($line =~ m/^\s*#/); next if ($line =~ m/^\s*$/); my @words = split(" ", $line); foreach my $word (@words) { last if ($word =~ m/^#/); push (@conf_args, $word); } } close($conffile); unshift(@ARGV, @conf_args) if @conf_args; } GetOptions( 'q|quiet+' => \$quiet, 'tree!' => \$tree, 'signoff!' => \$chk_signoff, 'patch!' => \$chk_patch, 'emacs!' => \$emacs, 'terse!' => \$terse, 'f|file!' => \$file, 'subjective!' => \$check, 'strict!' => \$check, 'ignore=s' => \@ignore, 'show-types!' => \$show_types, 'max-line-length=i' => \$max_line_length, 'root=s' => \$root, 'summary!' => \$summary, 'mailback!' => \$mailback, 'summary-file!' => \$summary_file, 'debug=s' => \%debug, 'test-only=s' => \$tst_only, 'h|help' => \$help, 'version' => \$help ) or help(1); help(0) if ($help); my $exit = 0; if ($#ARGV < 0) { print "$P: no input files\n"; exit(1); } @ignore = split(/,/, join(',',@ignore)); foreach my $word (@ignore) { $word =~ s/\s*\n?$//g; $word =~ s/^\s*//g; $word =~ s/\s+/ /g; $word =~ tr/[a-z]/[A-Z]/; next if ($word =~ m/^\s*#/); next if ($word =~ m/^\s*$/); $ignore_type{$word}++; } my $dbg_values = 0; my $dbg_possible = 0; my $dbg_type = 0; my $dbg_attr = 0; for my $key (keys %debug) { ## no critic eval "\${dbg_$key} = '$debug{$key}';"; die "$@" if ($@); } my $rpt_cleaners = 0; if ($terse) { $emacs = 1; $quiet++; } if ($tree) { if (defined $root) { if (!top_of_kernel_tree($root)) { die "$P: $root: --root does not point at a valid tree\n"; } } else { if (top_of_kernel_tree('.')) { $root = '.'; } elsif ($0 =~ m@(.*)/scripts/[^/]*$@ && top_of_kernel_tree($1)) { $root = $1; } } if (!defined $root) { print "Must be run from the top-level dir. of a kernel tree\n"; exit(2); } } my $emitted_corrupt = 0; our $Ident = qr{ [A-Za-z_][A-Za-z\d_]* (?:\s*\#\#\s*[A-Za-z_][A-Za-z\d_]*)* }x; our $Storage = qr{extern|static|asmlinkage}; our $Sparse = qr{ __user| __kernel| __force| __iomem| __must_check| __init_refok| __kprobes| __ref| __rcu }x; # Notes to $Attribute: # We need \b after 'init' otherwise 'initconst' will cause a false positive in a check our $Attribute = qr{ const| __percpu| __nocast| __safe| __bitwise__| __packed__| __packed2__| __naked| __maybe_unused| __always_unused| __noreturn| __used| __cold| __noclone| __deprecated| __read_mostly| __kprobes| __(?:mem|cpu|dev|)(?:initdata|initconst|init\b)| ____cacheline_aligned| ____cacheline_aligned_in_smp| ____cacheline_internodealigned_in_smp| __weak }x; our $Modifier; our $Inline = qr{inline|__always_inline|noinline}; our $Member = qr{->$Ident|\.$Ident|\[[^]]*\]}; our $Lval = qr{$Ident(?:$Member)*}; our $Float_hex = qr{(?i)0x[0-9a-f]+p-?[0-9]+[fl]?}; our $Float_dec = qr{(?i)(?:[0-9]+\.[0-9]*|[0-9]*\.[0-9]+)(?:e-?[0-9]+)?[fl]?}; our $Float_int = qr{(?i)[0-9]+e-?[0-9]+[fl]?}; our $Float = qr{$Float_hex|$Float_dec|$Float_int}; our $Constant = qr{$Float|(?i)(?:0x[0-9a-f]+|[0-9]+)[ul]*}; our $Assignment = qr{\*\=|/=|%=|\+=|-=|<<=|>>=|&=|\^=|\|=|=}; our $Compare = qr{<=|>=|==|!=|<|>}; our $Operators = qr{ <=|>=|==|!=| =>|->|<<|>>|<|>|!|~| &&|\|\||,|\^|\+\+|--|&|\||\+|-|\*|\/|% }x; our $NonptrType; our $Type; our $Declare; our $NON_ASCII_UTF8 = qr{ [\xC2-\xDF][\x80-\xBF] # non-overlong 2-byte | \xE0[\xA0-\xBF][\x80-\xBF] # excluding overlongs | [\xE1-\xEC\xEE\xEF][\x80-\xBF]{2} # straight 3-byte | \xED[\x80-\x9F][\x80-\xBF] # excluding surrogates | \xF0[\x90-\xBF][\x80-\xBF]{2} # planes 1-3 | [\xF1-\xF3][\x80-\xBF]{3} # planes 4-15 | \xF4[\x80-\x8F][\x80-\xBF]{2} # plane 16 }x; our $UTF8 = qr{ [\x09\x0A\x0D\x20-\x7E] # ASCII | $NON_ASCII_UTF8 }x; our $typeTypedefs = qr{(?x: (?:__)?(?:u|s|be|le)(?:8|16|32|64)| atomic_t )}; our $logFunctions = qr{(?x: printk(?:_ratelimited|_once|)| [a-z0-9]+_(?:printk|emerg|alert|crit|err|warning|warn|notice|info|debug|dbg|vdbg|devel|cont|WARN)(?:_ratelimited|_once|)| WARN(?:_RATELIMIT|_ONCE|)| panic| MODULE_[A-Z_]+ )}; our $signature_tags = qr{(?xi: Signed-off-by:| Acked-by:| Tested-by:| Reviewed-by:| Reported-by:| To:| Cc: )}; our @typeList = ( qr{void}, qr{(?:unsigned\s+)?char}, qr{(?:unsigned\s+)?short}, qr{(?:unsigned\s+)?int}, qr{(?:unsigned\s+)?long}, qr{(?:unsigned\s+)?long\s+int}, qr{(?:unsigned\s+)?long\s+long}, qr{(?:unsigned\s+)?long\s+long\s+int}, qr{unsigned}, qr{float}, qr{double}, qr{bool}, qr{struct\s+$Ident}, qr{union\s+$Ident}, qr{enum\s+$Ident}, qr{${Ident}_t}, qr{${Ident}_handler}, qr{${Ident}_handler_fn}, ); our @modifierList = ( qr{fastcall}, ); our $allowed_asm_includes = qr{(?x: irq| memory )}; # memory.h: ARM has a custom one sub build_types { my $mods = "(?x: \n" . join("|\n ", @modifierList) . "\n)"; my $all = "(?x: \n" . join("|\n ", @typeList) . "\n)"; $Modifier = qr{(?:$Attribute|$Sparse|$mods)}; $NonptrType = qr{ (?:$Modifier\s+|const\s+)* (?: (?:typeof|__typeof__)\s*\([^\)]*\)| (?:$typeTypedefs\b)| (?:${all}\b) ) (?:\s+$Modifier|\s+const)* }x; $Type = qr{ $NonptrType (?:(?:\s|\*|\[\])+\s*const|(?:\s|\*|\[\])+|(?:\s*\[\s*\])+)? (?:\s+$Inline|\s+$Modifier)* }x; $Declare = qr{(?:$Storage\s+)?$Type}; } build_types(); our $Typecast = qr{\s*(\(\s*$NonptrType\s*\)){0,1}\s*}; # Using $balanced_parens, $LvalOrFunc, or $FuncArg # requires at least perl version v5.10.0 # Any use must be runtime checked with $^V our $balanced_parens = qr/(\((?:[^\(\)]++|(?-1))*\))/; our $LvalOrFunc = qr{($Lval)\s*($balanced_parens{0,1})\s*}; our $FuncArg = qr{$Typecast{0,1}($LvalOrFunc|$Constant)}; sub deparenthesize { my ($string) = @_; return "" if (!defined($string)); $string =~ s@^\s*\(\s*@@g; $string =~ s@\s*\)\s*$@@g; $string =~ s@\s+@ @g; return $string; } $chk_signoff = 0 if ($file); my @rawlines = (); my @lines = (); my $vname; for my $filename (@ARGV) { my $FILE; if ($file) { open($FILE, '-|', "diff -u /dev/null $filename") || die "$P: $filename: diff failed - $!\n"; } elsif ($filename eq '-') { open($FILE, '<&STDIN'); } else { open($FILE, '<', "$filename") || die "$P: $filename: open failed - $!\n"; } if ($filename eq '-') { $vname = 'Your patch'; } else { $vname = $filename; } while (<$FILE>) { chomp; push(@rawlines, $_); } close($FILE); if (!process($filename)) { $exit = 1; } @rawlines = (); @lines = (); } exit($exit); sub top_of_kernel_tree { my ($root) = @_; my @tree_check = ( "COPYING", "CREDITS", "Kbuild", "MAINTAINERS", "Makefile", "README", "Documentation", "arch", "include", "drivers", "fs", "init", "ipc", "kernel", "lib", "scripts", ); foreach my $check (@tree_check) { if (! -e $root . '/' . $check) { return 0; } } return 1; } sub parse_email { my ($formatted_email) = @_; my $name = ""; my $address = ""; my $comment = ""; if ($formatted_email =~ /^(.*)<(\S+\@\S+)>(.*)$/) { $name = $1; $address = $2; $comment = $3 if defined $3; } elsif ($formatted_email =~ /^\s*<(\S+\@\S+)>(.*)$/) { $address = $1; $comment = $2 if defined $2; } elsif ($formatted_email =~ /(\S+\@\S+)(.*)$/) { $address = $1; $comment = $2 if defined $2; $formatted_email =~ s/$address.*$//; $name = $formatted_email; $name =~ s/^\s+|\s+$//g; $name =~ s/^\"|\"$//g; # If there's a name left after stripping spaces and # leading quotes, and the address doesn't have both # leading and trailing angle brackets, the address # is invalid. ie: # "joe smith joe@smith.com" bad # "joe smith ]+>$/) { $name = ""; $address = ""; $comment = ""; } } $name =~ s/^\s+|\s+$//g; $name =~ s/^\"|\"$//g; $address =~ s/^\s+|\s+$//g; $address =~ s/^\<|\>$//g; if ($name =~ /[^\w \-]/i) { ##has "must quote" chars $name =~ s/(?"; } return $formatted_email; } sub which_conf { my ($conf) = @_; foreach my $path (split(/:/, ".:$ENV{HOME}:.scripts")) { if (-e "$path/$conf") { return "$path/$conf"; } } return ""; } sub expand_tabs { my ($str) = @_; my $res = ''; my $n = 0; for my $c (split(//, $str)) { if ($c eq "\t") { $res .= ' '; $n++; for (; ($n % 8) != 0; $n++) { $res .= ' '; } next; } $res .= $c; $n++; } return $res; } sub copy_spacing { (my $res = shift) =~ tr/\t/ /c; return $res; } sub line_stats { my ($line) = @_; # Drop the diff line leader and expand tabs $line =~ s/^.//; $line = expand_tabs($line); # Pick the indent from the front of the line. my ($white) = ($line =~ /^(\s*)/); return (length($line), length($white)); } my $sanitise_quote = ''; sub sanitise_line_reset { my ($in_comment) = @_; if ($in_comment) { $sanitise_quote = '*/'; } else { $sanitise_quote = ''; } } sub sanitise_line { my ($line) = @_; my $res = ''; my $l = ''; my $qlen = 0; my $off = 0; my $c; # Always copy over the diff marker. $res = substr($line, 0, 1); for ($off = 1; $off < length($line); $off++) { $c = substr($line, $off, 1); # Comments we are wacking completly including the begin # and end, all to $;. if ($sanitise_quote eq '' && substr($line, $off, 2) eq '/*') { $sanitise_quote = '*/'; substr($res, $off, 2, "$;$;"); $off++; next; } if ($sanitise_quote eq '*/' && substr($line, $off, 2) eq '*/') { $sanitise_quote = ''; substr($res, $off, 2, "$;$;"); $off++; next; } if ($sanitise_quote eq '' && substr($line, $off, 2) eq '//') { $sanitise_quote = '//'; substr($res, $off, 2, $sanitise_quote); $off++; next; } # A \ in a string means ignore the next character. if (($sanitise_quote eq "'" || $sanitise_quote eq '"') && $c eq "\\") { substr($res, $off, 2, 'XX'); $off++; next; } # Regular quotes. if ($c eq "'" || $c eq '"') { if ($sanitise_quote eq '') { $sanitise_quote = $c; substr($res, $off, 1, $c); next; } elsif ($sanitise_quote eq $c) { $sanitise_quote = ''; } } #print "c<$c> SQ<$sanitise_quote>\n"; if ($off != 0 && $sanitise_quote eq '*/' && $c ne "\t") { substr($res, $off, 1, $;); } elsif ($off != 0 && $sanitise_quote eq '//' && $c ne "\t") { substr($res, $off, 1, $;); } elsif ($off != 0 && $sanitise_quote && $c ne "\t") { substr($res, $off, 1, 'X'); } else { substr($res, $off, 1, $c); } } if ($sanitise_quote eq '//') { $sanitise_quote = ''; } # The pathname on a #include may be surrounded by '<' and '>'. if ($res =~ /^.\s*\#\s*include\s+\<(.*)\>/) { my $clean = 'X' x length($1); $res =~ s@\<.*\>@<$clean>@; # The whole of a #error is a string. } elsif ($res =~ /^.\s*\#\s*(?:error|warning)\s+(.*)\b/) { my $clean = 'X' x length($1); $res =~ s@(\#\s*(?:error|warning)\s+).*@$1$clean@; } return $res; } sub ctx_statement_block { my ($linenr, $remain, $off) = @_; my $line = $linenr - 1; my $blk = ''; my $soff = $off; my $coff = $off - 1; my $coff_set = 0; my $loff = 0; my $type = ''; my $level = 0; my @stack = (); my $p; my $c; my $len = 0; my $remainder; while (1) { @stack = (['', 0]) if ($#stack == -1); #warn "CSB: blk<$blk> remain<$remain>\n"; # If we are about to drop off the end, pull in more # context. if ($off >= $len) { for (; $remain > 0; $line++) { last if (!defined $lines[$line]); next if ($lines[$line] =~ /^-/); $remain--; $loff = $len; $blk .= $lines[$line] . "\n"; $len = length($blk); $line++; last; } # Bail if there is no further context. #warn "CSB: blk<$blk> off<$off> len<$len>\n"; if ($off >= $len) { last; } if ($level == 0 && substr($blk, $off) =~ /^.\s*#\s*define/) { $level++; $type = '#'; } } $p = $c; $c = substr($blk, $off, 1); $remainder = substr($blk, $off); #warn "CSB: c<$c> type<$type> level<$level> remainder<$remainder> coff_set<$coff_set>\n"; # Handle nested #if/#else. if ($remainder =~ /^#\s*(?:ifndef|ifdef|if)\s/) { push(@stack, [ $type, $level ]); } elsif ($remainder =~ /^#\s*(?:else|elif)\b/) { ($type, $level) = @{$stack[$#stack - 1]}; } elsif ($remainder =~ /^#\s*endif\b/) { ($type, $level) = @{pop(@stack)}; } # Statement ends at the ';' or a close '}' at the # outermost level. if ($level == 0 && $c eq ';') { last; } # An else is really a conditional as long as its not else if if ($level == 0 && $coff_set == 0 && (!defined($p) || $p =~ /(?:\s|\}|\+)/) && $remainder =~ /^(else)(?:\s|{)/ && $remainder !~ /^else\s+if\b/) { $coff = $off + length($1) - 1; $coff_set = 1; #warn "CSB: mark coff<$coff> soff<$soff> 1<$1>\n"; #warn "[" . substr($blk, $soff, $coff - $soff + 1) . "]\n"; } if (($type eq '' || $type eq '(') && $c eq '(') { $level++; $type = '('; } if ($type eq '(' && $c eq ')') { $level--; $type = ($level != 0)? '(' : ''; if ($level == 0 && $coff < $soff) { $coff = $off; $coff_set = 1; #warn "CSB: mark coff<$coff>\n"; } } if (($type eq '' || $type eq '{') && $c eq '{') { $level++; $type = '{'; } if ($type eq '{' && $c eq '}') { $level--; $type = ($level != 0)? '{' : ''; if ($level == 0) { if (substr($blk, $off + 1, 1) eq ';') { $off++; } last; } } # Preprocessor commands end at the newline unless escaped. if ($type eq '#' && $c eq "\n" && $p ne "\\") { $level--; $type = ''; $off++; last; } $off++; } # We are truly at the end, so shuffle to the next line. if ($off == $len) { $loff = $len + 1; $line++; $remain--; } my $statement = substr($blk, $soff, $off - $soff + 1); my $condition = substr($blk, $soff, $coff - $soff + 1); #warn "STATEMENT<$statement>\n"; #warn "CONDITION<$condition>\n"; #print "coff<$coff> soff<$off> loff<$loff>\n"; return ($statement, $condition, $line, $remain + 1, $off - $loff + 1, $level); } sub statement_lines { my ($stmt) = @_; # Strip the diff line prefixes and rip blank lines at start and end. $stmt =~ s/(^|\n)./$1/g; $stmt =~ s/^\s*//; $stmt =~ s/\s*$//; my @stmt_lines = ($stmt =~ /\n/g); return $#stmt_lines + 2; } sub statement_rawlines { my ($stmt) = @_; my @stmt_lines = ($stmt =~ /\n/g); return $#stmt_lines + 2; } sub statement_block_size { my ($stmt) = @_; $stmt =~ s/(^|\n)./$1/g; $stmt =~ s/^\s*{//; $stmt =~ s/}\s*$//; $stmt =~ s/^\s*//; $stmt =~ s/\s*$//; my @stmt_lines = ($stmt =~ /\n/g); my @stmt_statements = ($stmt =~ /;/g); my $stmt_lines = $#stmt_lines + 2; my $stmt_statements = $#stmt_statements + 1; if ($stmt_lines > $stmt_statements) { return $stmt_lines; } else { return $stmt_statements; } } sub ctx_statement_full { my ($linenr, $remain, $off) = @_; my ($statement, $condition, $level); my (@chunks); # Grab the first conditional/block pair. ($statement, $condition, $linenr, $remain, $off, $level) = ctx_statement_block($linenr, $remain, $off); #print "F: c<$condition> s<$statement> remain<$remain>\n"; push(@chunks, [ $condition, $statement ]); if (!($remain > 0 && $condition =~ /^\s*(?:\n[+-])?\s*(?:if|else|do)\b/s)) { return ($level, $linenr, @chunks); } # Pull in the following conditional/block pairs and see if they # could continue the statement. for (;;) { ($statement, $condition, $linenr, $remain, $off, $level) = ctx_statement_block($linenr, $remain, $off); #print "C: c<$condition> s<$statement> remain<$remain>\n"; last if (!($remain > 0 && $condition =~ /^(?:\s*\n[+-])*\s*(?:else|do)\b/s)); #print "C: push\n"; push(@chunks, [ $condition, $statement ]); } return ($level, $linenr, @chunks); } sub ctx_block_get { my ($linenr, $remain, $outer, $open, $close, $off) = @_; my $line; my $start = $linenr - 1; my $blk = ''; my @o; my @c; my @res = (); my $level = 0; my @stack = ($level); for ($line = $start; $remain > 0; $line++) { next if ($rawlines[$line] =~ /^-/); $remain--; $blk .= $rawlines[$line]; # Handle nested #if/#else. if ($lines[$line] =~ /^.\s*#\s*(?:ifndef|ifdef|if)\s/) { push(@stack, $level); } elsif ($lines[$line] =~ /^.\s*#\s*(?:else|elif)\b/) { $level = $stack[$#stack - 1]; } elsif ($lines[$line] =~ /^.\s*#\s*endif\b/) { $level = pop(@stack); } foreach my $c (split(//, $lines[$line])) { ##print "C<$c>L<$level><$open$close>O<$off>\n"; if ($off > 0) { $off--; next; } if ($c eq $close && $level > 0) { $level--; last if ($level == 0); } elsif ($c eq $open) { $level++; } } if (!$outer || $level <= 1) { push(@res, $rawlines[$line]); } last if ($level == 0); } return ($level, @res); } sub ctx_block_outer { my ($linenr, $remain) = @_; my ($level, @r) = ctx_block_get($linenr, $remain, 1, '{', '}', 0); return @r; } sub ctx_block { my ($linenr, $remain) = @_; my ($level, @r) = ctx_block_get($linenr, $remain, 0, '{', '}', 0); return @r; } sub ctx_statement { my ($linenr, $remain, $off) = @_; my ($level, @r) = ctx_block_get($linenr, $remain, 0, '(', ')', $off); return @r; } sub ctx_block_level { my ($linenr, $remain) = @_; return ctx_block_get($linenr, $remain, 0, '{', '}', 0); } sub ctx_statement_level { my ($linenr, $remain, $off) = @_; return ctx_block_get($linenr, $remain, 0, '(', ')', $off); } sub ctx_locate_comment { my ($first_line, $end_line) = @_; # Catch a comment on the end of the line itself. my ($current_comment) = ($rawlines[$end_line - 1] =~ m@.*(/\*.*\*/)\s*(?:\\\s*)?$@); return $current_comment if (defined $current_comment); # Look through the context and try and figure out if there is a # comment. my $in_comment = 0; $current_comment = ''; for (my $linenr = $first_line; $linenr < $end_line; $linenr++) { my $line = $rawlines[$linenr - 1]; #warn " $line\n"; if ($linenr == $first_line and $line =~ m@^.\s*\*@) { $in_comment = 1; } if ($line =~ m@/\*@) { $in_comment = 1; } if (!$in_comment && $current_comment ne '') { $current_comment = ''; } $current_comment .= $line . "\n" if ($in_comment); if ($line =~ m@\*/@) { $in_comment = 0; } } chomp($current_comment); return($current_comment); } sub ctx_has_comment { my ($first_line, $end_line) = @_; my $cmt = ctx_locate_comment($first_line, $end_line); ##print "LINE: $rawlines[$end_line - 1 ]\n"; ##print "CMMT: $cmt\n"; return ($cmt ne ''); } sub raw_line { my ($linenr, $cnt) = @_; my $offset = $linenr - 1; $cnt++; my $line; while ($cnt) { $line = $rawlines[$offset++]; next if (defined($line) && $line =~ /^-/); $cnt--; } return $line; } sub cat_vet { my ($vet) = @_; my ($res, $coded); $res = ''; while ($vet =~ /([^[:cntrl:]]*)([[:cntrl:]]|$)/g) { $res .= $1; if ($2 ne '') { $coded = sprintf("^%c", unpack('C', $2) + 64); $res .= $coded; } } $res =~ s/$/\$/; return $res; } my $av_preprocessor = 0; my $av_pending; my @av_paren_type; my $av_pend_colon; sub annotate_reset { $av_preprocessor = 0; $av_pending = '_'; @av_paren_type = ('E'); $av_pend_colon = 'O'; } sub annotate_values { my ($stream, $type) = @_; my $res; my $var = '_' x length($stream); my $cur = $stream; print "$stream\n" if ($dbg_values > 1); while (length($cur)) { @av_paren_type = ('E') if ($#av_paren_type < 0); print " <" . join('', @av_paren_type) . "> <$type> <$av_pending>" if ($dbg_values > 1); if ($cur =~ /^(\s+)/o) { print "WS($1)\n" if ($dbg_values > 1); if ($1 =~ /\n/ && $av_preprocessor) { $type = pop(@av_paren_type); $av_preprocessor = 0; } } elsif ($cur =~ /^(\(\s*$Type\s*)\)/ && $av_pending eq '_') { print "CAST($1)\n" if ($dbg_values > 1); push(@av_paren_type, $type); $type = 'c'; } elsif ($cur =~ /^($Type)\s*(?:$Ident|,|\)|\(|\s*$)/) { print "DECLARE($1)\n" if ($dbg_values > 1); $type = 'T'; } elsif ($cur =~ /^($Modifier)\s*/) { print "MODIFIER($1)\n" if ($dbg_values > 1); $type = 'T'; } elsif ($cur =~ /^(\#\s*define\s*$Ident)(\(?)/o) { print "DEFINE($1,$2)\n" if ($dbg_values > 1); $av_preprocessor = 1; push(@av_paren_type, $type); if ($2 ne '') { $av_pending = 'N'; } $type = 'E'; } elsif ($cur =~ /^(\#\s*(?:undef\s*$Ident|include\b))/o) { print "UNDEF($1)\n" if ($dbg_values > 1); $av_preprocessor = 1; push(@av_paren_type, $type); } elsif ($cur =~ /^(\#\s*(?:ifdef|ifndef|if))/o) { print "PRE_START($1)\n" if ($dbg_values > 1); $av_preprocessor = 1; push(@av_paren_type, $type); push(@av_paren_type, $type); $type = 'E'; } elsif ($cur =~ /^(\#\s*(?:else|elif))/o) { print "PRE_RESTART($1)\n" if ($dbg_values > 1); $av_preprocessor = 1; push(@av_paren_type, $av_paren_type[$#av_paren_type]); $type = 'E'; } elsif ($cur =~ /^(\#\s*(?:endif))/o) { print "PRE_END($1)\n" if ($dbg_values > 1); $av_preprocessor = 1; # Assume all arms of the conditional end as this # one does, and continue as if the #endif was not here. pop(@av_paren_type); push(@av_paren_type, $type); $type = 'E'; } elsif ($cur =~ /^(\\\n)/o) { print "PRECONT($1)\n" if ($dbg_values > 1); } elsif ($cur =~ /^(__attribute__)\s*\(?/o) { print "ATTR($1)\n" if ($dbg_values > 1); $av_pending = $type; $type = 'N'; } elsif ($cur =~ /^(sizeof)\s*(\()?/o) { print "SIZEOF($1)\n" if ($dbg_values > 1); if (defined $2) { $av_pending = 'V'; } $type = 'N'; } elsif ($cur =~ /^(if|while|for)\b/o) { print "COND($1)\n" if ($dbg_values > 1); $av_pending = 'E'; $type = 'N'; } elsif ($cur =~/^(case)/o) { print "CASE($1)\n" if ($dbg_values > 1); $av_pend_colon = 'C'; $type = 'N'; } elsif ($cur =~/^(return|else|goto|typeof|__typeof__)\b/o) { print "KEYWORD($1)\n" if ($dbg_values > 1); $type = 'N'; } elsif ($cur =~ /^(\()/o) { print "PAREN('$1')\n" if ($dbg_values > 1); push(@av_paren_type, $av_pending); $av_pending = '_'; $type = 'N'; } elsif ($cur =~ /^(\))/o) { my $new_type = pop(@av_paren_type); if ($new_type ne '_') { $type = $new_type; print "PAREN('$1') -> $type\n" if ($dbg_values > 1); } else { print "PAREN('$1')\n" if ($dbg_values > 1); } } elsif ($cur =~ /^($Ident)\s*\(/o) { print "FUNC($1)\n" if ($dbg_values > 1); $type = 'V'; $av_pending = 'V'; } elsif ($cur =~ /^($Ident\s*):(?:\s*\d+\s*(,|=|;))?/) { if (defined $2 && $type eq 'C' || $type eq 'T') { $av_pend_colon = 'B'; } elsif ($type eq 'E') { $av_pend_colon = 'L'; } print "IDENT_COLON($1,$type>$av_pend_colon)\n" if ($dbg_values > 1); $type = 'V'; } elsif ($cur =~ /^($Ident|$Constant)/o) { print "IDENT($1)\n" if ($dbg_values > 1); $type = 'V'; } elsif ($cur =~ /^($Assignment)/o) { print "ASSIGN($1)\n" if ($dbg_values > 1); $type = 'N'; } elsif ($cur =~/^(;|{|})/) { print "END($1)\n" if ($dbg_values > 1); $type = 'E'; $av_pend_colon = 'O'; } elsif ($cur =~/^(,)/) { print "COMMA($1)\n" if ($dbg_values > 1); $type = 'C'; } elsif ($cur =~ /^(\?)/o) { print "QUESTION($1)\n" if ($dbg_values > 1); $type = 'N'; } elsif ($cur =~ /^(:)/o) { print "COLON($1,$av_pend_colon)\n" if ($dbg_values > 1); substr($var, length($res), 1, $av_pend_colon); if ($av_pend_colon eq 'C' || $av_pend_colon eq 'L') { $type = 'E'; } else { $type = 'N'; } $av_pend_colon = 'O'; } elsif ($cur =~ /^(\[)/o) { print "CLOSE($1)\n" if ($dbg_values > 1); $type = 'N'; } elsif ($cur =~ /^(-(?![->])|\+(?!\+)|\*|\&\&|\&)/o) { my $variant; print "OPV($1)\n" if ($dbg_values > 1); if ($type eq 'V') { $variant = 'B'; } else { $variant = 'U'; } substr($var, length($res), 1, $variant); $type = 'N'; } elsif ($cur =~ /^($Operators)/o) { print "OP($1)\n" if ($dbg_values > 1); if ($1 ne '++' && $1 ne '--') { $type = 'N'; } } elsif ($cur =~ /(^.)/o) { print "C($1)\n" if ($dbg_values > 1); } if (defined $1) { $cur = substr($cur, length($1)); $res .= $type x length($1); } } return ($res, $var); } sub possible { my ($possible, $line) = @_; my $notPermitted = qr{(?: ^(?: $Modifier| $Storage| $Type| DEFINE_\S+ )$| ^(?: goto| return| case| else| asm|__asm__| do| \#| \#\#| )(?:\s|$)| ^(?:typedef|struct|enum)\b )}x; warn "CHECK<$possible> ($line)\n" if ($dbg_possible > 2); if ($possible !~ $notPermitted) { # Check for modifiers. $possible =~ s/\s*$Storage\s*//g; $possible =~ s/\s*$Sparse\s*//g; if ($possible =~ /^\s*$/) { } elsif ($possible =~ /\s/) { $possible =~ s/\s*$Type\s*//g; for my $modifier (split(' ', $possible)) { if ($modifier !~ $notPermitted) { warn "MODIFIER: $modifier ($possible) ($line)\n" if ($dbg_possible); push(@modifierList, $modifier); } } } else { warn "POSSIBLE: $possible ($line)\n" if ($dbg_possible); push(@typeList, $possible); } build_types(); } else { warn "NOTPOSS: $possible ($line)\n" if ($dbg_possible > 1); } } my $prefix = ''; sub show_type { return !defined $ignore_type{$_[0]}; } sub report { if (!show_type($_[1]) || (defined $tst_only && $_[2] !~ /\Q$tst_only\E/)) { return 0; } my $line; if ($show_types) { $line = "$prefix$_[0]:$_[1]: $_[2]\n"; } else { $line = "$prefix$_[0]: $_[2]\n"; } $line = (split('\n', $line))[0] . "\n" if ($terse); push(our @report, $line); return 1; } sub report_dump { our @report; } sub ERROR { if (report("ERROR", $_[0], $_[1])) { our $clean = 0; our $cnt_error++; } } sub WARN { if (report("WARNING", $_[0], $_[1])) { our $clean = 0; our $cnt_warn++; } } sub CHK { if ($check && report("CHECK", $_[0], $_[1])) { our $clean = 0; our $cnt_chk++; } } sub check_absolute_file { my ($absolute, $herecurr) = @_; my $file = $absolute; ##print "absolute<$absolute>\n"; # See if any suffix of this path is a path within the tree. while ($file =~ s@^[^/]*/@@) { if (-f "$root/$file") { ##print "file<$file>\n"; last; } } if (! -f _) { return 0; } # It is, so see if the prefix is acceptable. my $prefix = $absolute; substr($prefix, -length($file)) = ''; ##print "prefix<$prefix>\n"; if ($prefix ne ".../") { WARN("USE_RELATIVE_PATH", "use relative pathname instead of absolute in changelog text\n" . $herecurr); } } sub pos_last_openparen { my ($line) = @_; my $pos = 0; my $opens = $line =~ tr/\(/\(/; my $closes = $line =~ tr/\)/\)/; my $last_openparen = 0; if (($opens == 0) || ($closes >= $opens)) { return -1; } my $len = length($line); for ($pos = 0; $pos < $len; $pos++) { my $string = substr($line, $pos); if ($string =~ /^($FuncArg|$balanced_parens)/) { $pos += length($1) - 1; } elsif (substr($line, $pos, 1) eq '(') { $last_openparen = $pos; } elsif (index($string, '(') == -1) { last; } } return $last_openparen + 1; } sub process { my $filename = shift; my $linenr=0; my $prevline=""; my $prevrawline=""; my $stashline=""; my $stashrawline=""; my $length; my $indent; my $previndent=0; my $stashindent=0; our $clean = 1; my $signoff = 0; my $is_patch = 0; my $in_header_lines = 1; my $in_commit_log = 0; #Scanning lines before patch my $non_utf8_charset = 0; our @report = (); our $cnt_lines = 0; our $cnt_error = 0; our $cnt_warn = 0; our $cnt_chk = 0; # Trace the real file/line as we go. my $realfile = ''; my $realline = 0; my $realcnt = 0; my $here = ''; my $in_comment = 0; my $comment_edge = 0; my $first_line = 0; my $p1_prefix = ''; my $prev_values = 'E'; # suppression flags my %suppress_ifbraces; my %suppress_whiletrailers; my %suppress_export; my $suppress_statement = 0; my %camelcase = (); # Pre-scan the patch sanitizing the lines. # Pre-scan the patch looking for any __setup documentation. # my @setup_docs = (); my $setup_docs = 0; sanitise_line_reset(); my $line; foreach my $rawline (@rawlines) { $linenr++; $line = $rawline; if ($rawline=~/^\+\+\+\s+(\S+)/) { $setup_docs = 0; if ($1 =~ m@Documentation/kernel-parameters.txt$@) { $setup_docs = 1; } #next; } if ($rawline=~/^\@\@ -\d+(?:,\d+)? \+(\d+)(,(\d+))? \@\@/) { $realline=$1-1; if (defined $2) { $realcnt=$3+1; } else { $realcnt=1+1; } $in_comment = 0; # Guestimate if this is a continuing comment. Run # the context looking for a comment "edge". If this # edge is a close comment then we must be in a comment # at context start. my $edge; my $cnt = $realcnt; for (my $ln = $linenr + 1; $cnt > 0; $ln++) { next if (defined $rawlines[$ln - 1] && $rawlines[$ln - 1] =~ /^-/); $cnt--; #print "RAW<$rawlines[$ln - 1]>\n"; last if (!defined $rawlines[$ln - 1]); if ($rawlines[$ln - 1] =~ m@(/\*|\*/)@ && $rawlines[$ln - 1] !~ m@"[^"]*(?:/\*|\*/)[^"]*"@) { ($edge) = $1; last; } } if (defined $edge && $edge eq '*/') { $in_comment = 1; } # Guestimate if this is a continuing comment. If this # is the start of a diff block and this line starts # ' *' then it is very likely a comment. if (!defined $edge && $rawlines[$linenr] =~ m@^.\s*(?:\*\*+| \*)(?:\s|$)@) { $in_comment = 1; } ##print "COMMENT:$in_comment edge<$edge> $rawline\n"; sanitise_line_reset($in_comment); } elsif ($realcnt && $rawline =~ /^(?:\+| |$)/) { # Standardise the strings and chars within the input to # simplify matching -- only bother with positive lines. $line = sanitise_line($rawline); } push(@lines, $line); if ($realcnt > 1) { $realcnt-- if ($line =~ /^(?:\+| |$)/); } else { $realcnt = 0; } #print "==>$rawline\n"; #print "-->$line\n"; if ($setup_docs && $line =~ /^\+/) { push(@setup_docs, $line); } } $prefix = ''; $realcnt = 0; $linenr = 0; foreach my $line (@lines) { $linenr++; my $rawline = $rawlines[$linenr - 1]; #extract the line range in the file after the patch is applied if ($line=~/^\@\@ -\d+(?:,\d+)? \+(\d+)(,(\d+))? \@\@/) { $is_patch = 1; $first_line = $linenr + 1; $realline=$1-1; if (defined $2) { $realcnt=$3+1; } else { $realcnt=1+1; } annotate_reset(); $prev_values = 'E'; %suppress_ifbraces = (); %suppress_whiletrailers = (); %suppress_export = (); $suppress_statement = 0; next; # track the line number as we move through the hunk, note that # new versions of GNU diff omit the leading space on completely # blank context lines so we need to count that too. } elsif ($line =~ /^( |\+|$)/) { $realline++; $realcnt-- if ($realcnt != 0); # Measure the line length and indent. ($length, $indent) = line_stats($rawline); # Track the previous line. ($prevline, $stashline) = ($stashline, $line); ($previndent, $stashindent) = ($stashindent, $indent); ($prevrawline, $stashrawline) = ($stashrawline, $rawline); #warn "line<$line>\n"; } elsif ($realcnt == 1) { $realcnt--; } my $hunk_line = ($realcnt != 0); #make up the handle for any error we report on this line $prefix = "$filename:$realline: " if ($emacs && $file); $prefix = "$filename:$linenr: " if ($emacs && !$file); $here = "#$linenr: " if (!$file); $here = "#$realline: " if ($file); # extract the filename as it passes if ($line =~ /^diff --git.*?(\S+)$/) { $realfile = $1; $realfile =~ s@^([^/]*)/@@; $in_commit_log = 0; } elsif ($line =~ /^\+\+\+\s+(\S+)/) { $realfile = $1; $realfile =~ s@^([^/]*)/@@; $in_commit_log = 0; $p1_prefix = $1; if (!$file && $tree && $p1_prefix ne '' && -e "$root/$p1_prefix") { WARN("PATCH_PREFIX", "patch prefix '$p1_prefix' exists, appears to be a -p0 patch\n"); } if ($realfile =~ m@^include/asm/@) { ERROR("MODIFIED_INCLUDE_ASM", "do not modify files in include/asm, change architecture specific files in include/asm-\n" . "$here$rawline\n"); } next; } $here .= "FILE: $realfile:$realline:" if ($realcnt != 0); my $hereline = "$here\n$rawline\n"; my $herecurr = "$here\n$rawline\n"; my $hereprev = "$here\n$prevrawline\n$rawline\n"; $cnt_lines++ if ($realcnt != 0); # Check for incorrect file permissions if ($line =~ /^new (file )?mode.*[7531]\d{0,2}$/) { my $permhere = $here . "FILE: $realfile\n"; if ($realfile =~ /(Makefile|Kconfig|\.c|\.h|\.S|\.tmpl)$/) { ERROR("EXECUTE_PERMISSIONS", "do not set execute permissions for source files\n" . $permhere); } } # Check the patch for a signoff: if ($line =~ /^\s*signed-off-by:/i) { $signoff++; $in_commit_log = 0; } # Check signature styles if (!$in_header_lines && $line =~ /^(\s*)([a-z0-9_-]+by:|$signature_tags)(\s*)(.*)/i) { my $space_before = $1; my $sign_off = $2; my $space_after = $3; my $email = $4; my $ucfirst_sign_off = ucfirst(lc($sign_off)); if ($sign_off !~ /$signature_tags/) { WARN("BAD_SIGN_OFF", "Non-standard signature: $sign_off\n" . $herecurr); } if (defined $space_before && $space_before ne "") { WARN("BAD_SIGN_OFF", "Do not use whitespace before $ucfirst_sign_off\n" . $herecurr); } if ($sign_off =~ /-by:$/i && $sign_off ne $ucfirst_sign_off) { WARN("BAD_SIGN_OFF", "'$ucfirst_sign_off' is the preferred signature form\n" . $herecurr); } if (!defined $space_after || $space_after ne " ") { WARN("BAD_SIGN_OFF", "Use a single space after $ucfirst_sign_off\n" . $herecurr); } my ($email_name, $email_address, $comment) = parse_email($email); my $suggested_email = format_email(($email_name, $email_address)); if ($suggested_email eq "") { ERROR("BAD_SIGN_OFF", "Unrecognized email address: '$email'\n" . $herecurr); } else { my $dequoted = $suggested_email; $dequoted =~ s/^"//; $dequoted =~ s/" $comment" ne $email && "$suggested_email$comment" ne $email) { WARN("BAD_SIGN_OFF", "email address '$email' might be better as '$suggested_email$comment'\n" . $herecurr); } } } # Check for wrappage within a valid hunk of the file if ($realcnt != 0 && $line !~ m{^(?:\+|-| |\\ No newline|$)}) { ERROR("CORRUPTED_PATCH", "patch seems to be corrupt (line wrapped?)\n" . $herecurr) if (!$emitted_corrupt++); } # Check for absolute kernel paths. if ($tree) { while ($line =~ m{(?:^|\s)(/\S*)}g) { my $file = $1; if ($file =~ m{^(.*?)(?::\d+)+:?$} && check_absolute_file($1, $herecurr)) { # } else { check_absolute_file($file, $herecurr); } } } # UTF-8 regex found at http://www.w3.org/International/questions/qa-forms-utf-8.en.php if (($realfile =~ /^$/ || $line =~ /^\+/) && $rawline !~ m/^$UTF8*$/) { my ($utf8_prefix) = ($rawline =~ /^($UTF8*)/); my $blank = copy_spacing($rawline); my $ptr = substr($blank, 0, length($utf8_prefix)) . "^"; my $hereptr = "$hereline$ptr\n"; CHK("INVALID_UTF8", "Invalid UTF-8, patch and commit message should be encoded in UTF-8\n" . $hereptr); } # Check if it's the start of a commit log # (not a header line and we haven't seen the patch filename) if ($in_header_lines && $realfile =~ /^$/ && $rawline !~ /^(commit\b|from\b|[\w-]+:).+$/i) { $in_header_lines = 0; $in_commit_log = 1; } # Check if there is UTF-8 in a commit log when a mail header has explicitly # declined it, i.e defined some charset where it is missing. if ($in_header_lines && $rawline =~ /^Content-Type:.+charset="(.+)".*$/ && $1 !~ /utf-8/i) { $non_utf8_charset = 1; } if ($in_commit_log && $non_utf8_charset && $realfile =~ /^$/ && $rawline =~ /$NON_ASCII_UTF8/) { WARN("UTF8_BEFORE_PATCH", "8-bit UTF-8 used in possible commit log\n" . $herecurr); } # ignore non-hunk lines and lines being removed next if (!$hunk_line || $line =~ /^-/); #trailing whitespace if ($line =~ /^\+.*\015/) { my $herevet = "$here\n" . cat_vet($rawline) . "\n"; ERROR("DOS_LINE_ENDINGS", "DOS line endings\n" . $herevet); } elsif ($rawline =~ /^\+.*\S\s+$/ || $rawline =~ /^\+\s+$/) { my $herevet = "$here\n" . cat_vet($rawline) . "\n"; ERROR("TRAILING_WHITESPACE", "trailing whitespace\n" . $herevet); $rpt_cleaners = 1; } # check for Kconfig help text having a real description # Only applies when adding the entry originally, after that we do not have # sufficient context to determine whether it is indeed long enough. if ($realfile =~ /Kconfig/ && $line =~ /.\s*config\s+/) { my $length = 0; my $cnt = $realcnt; my $ln = $linenr + 1; my $f; my $is_start = 0; my $is_end = 0; for (; $cnt > 0 && defined $lines[$ln - 1]; $ln++) { $f = $lines[$ln - 1]; $cnt-- if ($lines[$ln - 1] !~ /^-/); $is_end = $lines[$ln - 1] =~ /^\+/; next if ($f =~ /^-/); if ($lines[$ln - 1] =~ /.\s*(?:bool|tristate)\s*\"/) { $is_start = 1; } elsif ($lines[$ln - 1] =~ /.\s*(?:---)?help(?:---)?$/) { $length = -1; } $f =~ s/^.//; $f =~ s/#.*//; $f =~ s/^\s+//; next if ($f =~ /^$/); if ($f =~ /^\s*config\s/) { $is_end = 1; last; } $length++; } WARN("CONFIG_DESCRIPTION", "please write a paragraph that describes the config symbol fully\n" . $herecurr) if ($is_start && $is_end && $length < 4); #print "is_start<$is_start> is_end<$is_end> length<$length>\n"; } # discourage the addition of CONFIG_EXPERIMENTAL in Kconfig. if ($realfile =~ /Kconfig/ && $line =~ /.\s*depends on\s+.*\bEXPERIMENTAL\b/) { WARN("CONFIG_EXPERIMENTAL", "Use of CONFIG_EXPERIMENTAL is deprecated. For alternatives, see https://lkml.org/lkml/2012/10/23/580\n"); } if (($realfile =~ /Makefile.*/ || $realfile =~ /Kbuild.*/) && ($line =~ /\+(EXTRA_[A-Z]+FLAGS).*/)) { my $flag = $1; my $replacement = { 'EXTRA_AFLAGS' => 'asflags-y', 'EXTRA_CFLAGS' => 'ccflags-y', 'EXTRA_CPPFLAGS' => 'cppflags-y', 'EXTRA_LDFLAGS' => 'ldflags-y', }; WARN("DEPRECATED_VARIABLE", "Use of $flag is deprecated, please use \`$replacement->{$flag} instead.\n" . $herecurr) if ($replacement->{$flag}); } # check we are in a valid source file if not then ignore this hunk next if ($realfile !~ /\.(h|c|s|S|pl|sh)$/); #line length limit if ($line =~ /^\+/ && $prevrawline !~ /\/\*\*/ && $rawline !~ /^.\s*\*\s*\@$Ident\s/ && !($line =~ /^\+\s*$logFunctions\s*\(\s*(?:(KERN_\S+\s*|[^"]*))?"[X\t]*"\s*(?:|,|\)\s*;)\s*$/ || $line =~ /^\+\s*"[^"]*"\s*(?:\s*|,|\)\s*;)\s*$/) && $length > $max_line_length) { WARN("LONG_LINE", "line over $max_line_length characters\n" . $herecurr); } # Check for user-visible strings broken across lines, which breaks the ability # to grep for the string. Limited to strings used as parameters (those # following an open parenthesis), which almost completely eliminates false # positives, as well as warning only once per parameter rather than once per # line of the string. Make an exception when the previous string ends in a # newline (multiple lines in one string constant) or \n\t (common in inline # assembly to indent the instruction on the following line). if ($line =~ /^\+\s*"/ && $prevline =~ /"\s*$/ && $prevline =~ /\(/ && $prevrawline !~ /\\n(?:\\t)*"\s*$/) { WARN("SPLIT_STRING", "quoted string split across lines\n" . $hereprev); } # check for spaces before a quoted newline if ($rawline =~ /^.*\".*\s\\n/) { WARN("QUOTED_WHITESPACE_BEFORE_NEWLINE", "unnecessary whitespace before a quoted newline\n" . $herecurr); } # check for adding lines without a newline. if ($line =~ /^\+/ && defined $lines[$linenr] && $lines[$linenr] =~ /^\\ No newline at end of file/) { WARN("MISSING_EOF_NEWLINE", "adding a line without newline at end of file\n" . $herecurr); } # Blackfin: use hi/lo macros if ($realfile =~ m@arch/blackfin/.*\.S$@) { if ($line =~ /\.[lL][[:space:]]*=.*&[[:space:]]*0x[fF][fF][fF][fF]/) { my $herevet = "$here\n" . cat_vet($line) . "\n"; ERROR("LO_MACRO", "use the LO() macro, not (... & 0xFFFF)\n" . $herevet); } if ($line =~ /\.[hH][[:space:]]*=.*>>[[:space:]]*16/) { my $herevet = "$here\n" . cat_vet($line) . "\n"; ERROR("HI_MACRO", "use the HI() macro, not (... >> 16)\n" . $herevet); } } # check we are in a valid source file C or perl if not then ignore this hunk next if ($realfile !~ /\.(h|c|pl)$/); # at the beginning of a line any tabs must come first and anything # more than 8 must use tabs. if ($rawline =~ /^\+\s* \t\s*\S/ || $rawline =~ /^\+\s* \s*/) { my $herevet = "$here\n" . cat_vet($rawline) . "\n"; ERROR("CODE_INDENT", "code indent should use tabs where possible\n" . $herevet); $rpt_cleaners = 1; } # check for space before tabs. if ($rawline =~ /^\+/ && $rawline =~ / \t/) { my $herevet = "$here\n" . cat_vet($rawline) . "\n"; WARN("SPACE_BEFORE_TAB", "please, no space before tabs\n" . $herevet); } # check for && or || at the start of a line if ($rawline =~ /^\+\s*(&&|\|\|)/) { CHK("LOGICAL_CONTINUATIONS", "Logical continuations should be on the previous line\n" . $hereprev); } # check multi-line statement indentation matches previous line if ($^V && $^V ge 5.10.0 && $prevline =~ /^\+(\t*)(if \(|$Ident\().*(\&\&|\|\||,)\s*$/) { $prevline =~ /^\+(\t*)(.*)$/; my $oldindent = $1; my $rest = $2; my $pos = pos_last_openparen($rest); if ($pos >= 0) { $line =~ /^(\+| )([ \t]*)/; my $newindent = $2; my $goodtabindent = $oldindent . "\t" x ($pos / 8) . " " x ($pos % 8); my $goodspaceindent = $oldindent . " " x $pos; if ($newindent ne $goodtabindent && $newindent ne $goodspaceindent) { CHK("PARENTHESIS_ALIGNMENT", "Alignment should match open parenthesis\n" . $hereprev); } } } if ($line =~ /^\+.*\*[ \t]*\)[ \t]+/) { CHK("SPACING", "No space is necessary after a cast\n" . $hereprev); } if ($realfile =~ m@^(drivers/net/|net/)@ && $rawline =~ /^\+[ \t]*\/\*[ \t]*$/ && $prevrawline =~ /^\+[ \t]*$/) { WARN("NETWORKING_BLOCK_COMMENT_STYLE", "networking block comments don't use an empty /* line, use /* Comment...\n" . $hereprev); } if ($realfile =~ m@^(drivers/net/|net/)@ && $rawline !~ m@^\+[ \t]*\*/[ \t]*$@ && #trailing */ $rawline !~ m@^\+.*/\*.*\*/[ \t]*$@ && #inline /*...*/ $rawline !~ m@^\+.*\*{2,}/[ \t]*$@ && #trailing **/ $rawline =~ m@^\+[ \t]*.+\*\/[ \t]*$@) { #non blank */ WARN("NETWORKING_BLOCK_COMMENT_STYLE", "networking block comments put the trailing */ on a separate line\n" . $herecurr); } # check for spaces at the beginning of a line. # Exceptions: # 1) within comments # 2) indented preprocessor commands # 3) hanging labels if ($rawline =~ /^\+ / && $line !~ /\+ *(?:$;|#|$Ident:)/) { my $herevet = "$here\n" . cat_vet($rawline) . "\n"; WARN("LEADING_SPACE", "please, no spaces at the start of a line\n" . $herevet); } # check we are in a valid C source file if not then ignore this hunk next if ($realfile !~ /\.(h|c)$/); # discourage the addition of CONFIG_EXPERIMENTAL in #if(def). if ($line =~ /^\+\s*\#\s*if.*\bCONFIG_EXPERIMENTAL\b/) { WARN("CONFIG_EXPERIMENTAL", "Use of CONFIG_EXPERIMENTAL is deprecated. For alternatives, see https://lkml.org/lkml/2012/10/23/580\n"); } # check for RCS/CVS revision markers if ($rawline =~ /^\+.*\$(Revision|Log|Id)(?:\$|)/) { WARN("CVS_KEYWORD", "CVS style keyword markers, these will _not_ be updated\n". $herecurr); } # Blackfin: don't use __builtin_bfin_[cs]sync if ($line =~ /__builtin_bfin_csync/) { my $herevet = "$here\n" . cat_vet($line) . "\n"; ERROR("CSYNC", "use the CSYNC() macro in asm/blackfin.h\n" . $herevet); } if ($line =~ /__builtin_bfin_ssync/) { my $herevet = "$here\n" . cat_vet($line) . "\n"; ERROR("SSYNC", "use the SSYNC() macro in asm/blackfin.h\n" . $herevet); } # check for old HOTPLUG __dev section markings if ($line =~ /\b(__dev(init|exit)(data|const|))\b/) { WARN("HOTPLUG_SECTION", "Using $1 is unnecessary\n" . $herecurr); } # Check for potential 'bare' types my ($stat, $cond, $line_nr_next, $remain_next, $off_next, $realline_next); #print "LINE<$line>\n"; if ($linenr >= $suppress_statement && $realcnt && $line =~ /.\s*\S/) { ($stat, $cond, $line_nr_next, $remain_next, $off_next) = ctx_statement_block($linenr, $realcnt, 0); $stat =~ s/\n./\n /g; $cond =~ s/\n./\n /g; #print "linenr<$linenr> <$stat>\n"; # If this statement has no statement boundaries within # it there is no point in retrying a statement scan # until we hit end of it. my $frag = $stat; $frag =~ s/;+\s*$//; if ($frag !~ /(?:{|;)/) { #print "skip<$line_nr_next>\n"; $suppress_statement = $line_nr_next; } # Find the real next line. $realline_next = $line_nr_next; if (defined $realline_next && (!defined $lines[$realline_next - 1] || substr($lines[$realline_next - 1], $off_next) =~ /^\s*$/)) { $realline_next++; } my $s = $stat; $s =~ s/{.*$//s; # Ignore goto labels. if ($s =~ /$Ident:\*$/s) { # Ignore functions being called } elsif ($s =~ /^.\s*$Ident\s*\(/s) { } elsif ($s =~ /^.\s*else\b/s) { # declarations always start with types } elsif ($prev_values eq 'E' && $s =~ /^.\s*(?:$Storage\s+)?(?:$Inline\s+)?(?:const\s+)?((?:\s*$Ident)+?)\b(?:\s+$Sparse)?\s*\**\s*(?:$Ident|\(\*[^\)]*\))(?:\s*$Modifier)?\s*(?:;|=|,|\()/s) { my $type = $1; $type =~ s/\s+/ /g; possible($type, "A:" . $s); # definitions in global scope can only start with types } elsif ($s =~ /^.(?:$Storage\s+)?(?:$Inline\s+)?(?:const\s+)?($Ident)\b\s*(?!:)/s) { possible($1, "B:" . $s); } # any (foo ... *) is a pointer cast, and foo is a type while ($s =~ /\(($Ident)(?:\s+$Sparse)*[\s\*]+\s*\)/sg) { possible($1, "C:" . $s); } # Check for any sort of function declaration. # int foo(something bar, other baz); # void (*store_gdt)(x86_descr_ptr *); if ($prev_values eq 'E' && $s =~ /^(.(?:typedef\s*)?(?:(?:$Storage|$Inline)\s*)*\s*$Type\s*(?:\b$Ident|\(\*\s*$Ident\))\s*)\(/s) { my ($name_len) = length($1); my $ctx = $s; substr($ctx, 0, $name_len + 1, ''); $ctx =~ s/\)[^\)]*$//; for my $arg (split(/\s*,\s*/, $ctx)) { if ($arg =~ /^(?:const\s+)?($Ident)(?:\s+$Sparse)*\s*\**\s*(:?\b$Ident)?$/s || $arg =~ /^($Ident)$/s) { possible($1, "D:" . $s); } } } } # # Checks which may be anchored in the context. # # Check for switch () and associated case and default # statements should be at the same indent. if ($line=~/\bswitch\s*\(.*\)/) { my $err = ''; my $sep = ''; my @ctx = ctx_block_outer($linenr, $realcnt); shift(@ctx); for my $ctx (@ctx) { my ($clen, $cindent) = line_stats($ctx); if ($ctx =~ /^\+\s*(case\s+|default:)/ && $indent != $cindent) { $err .= "$sep$ctx\n"; $sep = ''; } else { $sep = "[...]\n"; } } if ($err ne '') { ERROR("SWITCH_CASE_INDENT_LEVEL", "switch and case should be at the same indent\n$hereline$err"); } } # if/while/etc brace do not go on next line, unless defining a do while loop, # or if that brace on the next line is for something else if ($line =~ /(.*)\b((?:if|while|for|switch)\s*\(|do\b|else\b)/ && $line !~ /^.\s*\#/) { my $pre_ctx = "$1$2"; my ($level, @ctx) = ctx_statement_level($linenr, $realcnt, 0); if ($line =~ /^\+\t{6,}/) { WARN("DEEP_INDENTATION", "Too many leading tabs - consider code refactoring\n" . $herecurr); } my $ctx_cnt = $realcnt - $#ctx - 1; my $ctx = join("\n", @ctx); my $ctx_ln = $linenr; my $ctx_skip = $realcnt; while ($ctx_skip > $ctx_cnt || ($ctx_skip == $ctx_cnt && defined $lines[$ctx_ln - 1] && $lines[$ctx_ln - 1] =~ /^-/)) { ##print "SKIP<$ctx_skip> CNT<$ctx_cnt>\n"; $ctx_skip-- if (!defined $lines[$ctx_ln - 1] || $lines[$ctx_ln - 1] !~ /^-/); $ctx_ln++; } #print "realcnt<$realcnt> ctx_cnt<$ctx_cnt>\n"; #print "pre<$pre_ctx>\nline<$line>\nctx<$ctx>\nnext<$lines[$ctx_ln - 1]>\n"; if ($ctx !~ /{\s*/ && defined($lines[$ctx_ln -1]) && $lines[$ctx_ln - 1] =~ /^\+\s*{/) { ERROR("OPEN_BRACE", "that open brace { should be on the previous line\n" . "$here\n$ctx\n$rawlines[$ctx_ln - 1]\n"); } if ($level == 0 && $pre_ctx !~ /}\s*while\s*\($/ && $ctx =~ /\)\s*\;\s*$/ && defined $lines[$ctx_ln - 1]) { my ($nlength, $nindent) = line_stats($lines[$ctx_ln - 1]); if ($nindent > $indent) { WARN("TRAILING_SEMICOLON", "trailing semicolon indicates no statements, indent implies otherwise\n" . "$here\n$ctx\n$rawlines[$ctx_ln - 1]\n"); } } } # Check relative indent for conditionals and blocks. if ($line =~ /\b(?:(?:if|while|for)\s*\(|do\b)/ && $line !~ /^.\s*#/ && $line !~ /\}\s*while\s*/) { ($stat, $cond, $line_nr_next, $remain_next, $off_next) = ctx_statement_block($linenr, $realcnt, 0) if (!defined $stat); my ($s, $c) = ($stat, $cond); substr($s, 0, length($c), ''); # Make sure we remove the line prefixes as we have # none on the first line, and are going to readd them # where necessary. $s =~ s/\n./\n/gs; # Find out how long the conditional actually is. my @newlines = ($c =~ /\n/gs); my $cond_lines = 1 + $#newlines; # We want to check the first line inside the block # starting at the end of the conditional, so remove: # 1) any blank line termination # 2) any opening brace { on end of the line # 3) any do (...) { my $continuation = 0; my $check = 0; $s =~ s/^.*\bdo\b//; $s =~ s/^\s*{//; if ($s =~ s/^\s*\\//) { $continuation = 1; } if ($s =~ s/^\s*?\n//) { $check = 1; $cond_lines++; } # Also ignore a loop construct at the end of a # preprocessor statement. if (($prevline =~ /^.\s*#\s*define\s/ || $prevline =~ /\\\s*$/) && $continuation == 0) { $check = 0; } my $cond_ptr = -1; $continuation = 0; while ($cond_ptr != $cond_lines) { $cond_ptr = $cond_lines; # If we see an #else/#elif then the code # is not linear. if ($s =~ /^\s*\#\s*(?:else|elif)/) { $check = 0; } # Ignore: # 1) blank lines, they should be at 0, # 2) preprocessor lines, and # 3) labels. if ($continuation || $s =~ /^\s*?\n/ || $s =~ /^\s*#\s*?/ || $s =~ /^\s*$Ident\s*:/) { $continuation = ($s =~ /^.*?\\\n/) ? 1 : 0; if ($s =~ s/^.*?\n//) { $cond_lines++; } } } my (undef, $sindent) = line_stats("+" . $s); my $stat_real = raw_line($linenr, $cond_lines); # Check if either of these lines are modified, else # this is not this patch's fault. if (!defined($stat_real) || $stat !~ /^\+/ && $stat_real !~ /^\+/) { $check = 0; } if (defined($stat_real) && $cond_lines > 1) { $stat_real = "[...]\n$stat_real"; } #print "line<$line> prevline<$prevline> indent<$indent> sindent<$sindent> check<$check> continuation<$continuation> s<$s> cond_lines<$cond_lines> stat_real<$stat_real> stat<$stat>\n"; if ($check && (($sindent % 8) != 0 || ($sindent <= $indent && $s ne ''))) { WARN("SUSPECT_CODE_INDENT", "suspect code indent for conditional statements ($indent, $sindent)\n" . $herecurr . "$stat_real\n"); } } # Track the 'values' across context and added lines. my $opline = $line; $opline =~ s/^./ /; my ($curr_values, $curr_vars) = annotate_values($opline . "\n", $prev_values); $curr_values = $prev_values . $curr_values; if ($dbg_values) { my $outline = $opline; $outline =~ s/\t/ /g; print "$linenr > .$outline\n"; print "$linenr > $curr_values\n"; print "$linenr > $curr_vars\n"; } $prev_values = substr($curr_values, -1); #ignore lines not being added if ($line=~/^[^\+]/) {next;} # TEST: allow direct testing of the type matcher. if ($dbg_type) { if ($line =~ /^.\s*$Declare\s*$/) { ERROR("TEST_TYPE", "TEST: is type\n" . $herecurr); } elsif ($dbg_type > 1 && $line =~ /^.+($Declare)/) { ERROR("TEST_NOT_TYPE", "TEST: is not type ($1 is)\n". $herecurr); } next; } # TEST: allow direct testing of the attribute matcher. if ($dbg_attr) { if ($line =~ /^.\s*$Modifier\s*$/) { ERROR("TEST_ATTR", "TEST: is attr\n" . $herecurr); } elsif ($dbg_attr > 1 && $line =~ /^.+($Modifier)/) { ERROR("TEST_NOT_ATTR", "TEST: is not attr ($1 is)\n". $herecurr); } next; } # check for initialisation to aggregates open brace on the next line if ($line =~ /^.\s*{/ && $prevline =~ /(?:^|[^=])=\s*$/) { ERROR("OPEN_BRACE", "that open brace { should be on the previous line\n" . $hereprev); } # # Checks which are anchored on the added line. # # check for malformed paths in #include statements (uses RAW line) if ($rawline =~ m{^.\s*\#\s*include\s+[<"](.*)[">]}) { my $path = $1; if ($path =~ m{//}) { ERROR("MALFORMED_INCLUDE", "malformed #include filename\n" . $herecurr); } if ($path =~ "^uapi/" && $realfile =~ m@\binclude/uapi/@) { ERROR("UAPI_INCLUDE", "No #include in ...include/uapi/... should use a uapi/ path prefix\n" . $herecurr); } } # no C99 // comments if ($line =~ m{//}) { ERROR("C99_COMMENTS", "do not use C99 // comments\n" . $herecurr); } # Remove C99 comments. $line =~ s@//.*@@; $opline =~ s@//.*@@; # EXPORT_SYMBOL should immediately follow the thing it is exporting, consider # the whole statement. #print "APW <$lines[$realline_next - 1]>\n"; if (defined $realline_next && exists $lines[$realline_next - 1] && !defined $suppress_export{$realline_next} && ($lines[$realline_next - 1] =~ /EXPORT_SYMBOL.*\((.*)\)/ || $lines[$realline_next - 1] =~ /EXPORT_UNUSED_SYMBOL.*\((.*)\)/)) { # Handle definitions which produce identifiers with # a prefix: # XXX(foo); # EXPORT_SYMBOL(something_foo); my $name = $1; if ($stat =~ /^(?:.\s*}\s*\n)?.([A-Z_]+)\s*\(\s*($Ident)/ && $name =~ /^${Ident}_$2/) { #print "FOO C name<$name>\n"; $suppress_export{$realline_next} = 1; } elsif ($stat !~ /(?: \n.}\s*$| ^.DEFINE_$Ident\(\Q$name\E\)| ^.DECLARE_$Ident\(\Q$name\E\)| ^.LIST_HEAD\(\Q$name\E\)| ^.(?:$Storage\s+)?$Type\s*\(\s*\*\s*\Q$name\E\s*\)\s*\(| \b\Q$name\E(?:\s+$Attribute)*\s*(?:;|=|\[|\() )/x) { #print "FOO A<$lines[$realline_next - 1]> stat<$stat> name<$name>\n"; $suppress_export{$realline_next} = 2; } else { $suppress_export{$realline_next} = 1; } } if (!defined $suppress_export{$linenr} && $prevline =~ /^.\s*$/ && ($line =~ /EXPORT_SYMBOL.*\((.*)\)/ || $line =~ /EXPORT_UNUSED_SYMBOL.*\((.*)\)/)) { #print "FOO B <$lines[$linenr - 1]>\n"; $suppress_export{$linenr} = 2; } if (defined $suppress_export{$linenr} && $suppress_export{$linenr} == 2) { WARN("EXPORT_SYMBOL", "EXPORT_SYMBOL(foo); should immediately follow its function/variable\n" . $herecurr); } # check for global initialisers. if ($line =~ /^.$Type\s*$Ident\s*(?:\s+$Modifier)*\s*=\s*(0|NULL|false)\s*;/) { ERROR("GLOBAL_INITIALISERS", "do not initialise globals to 0 or NULL\n" . $herecurr); } # check for static initialisers. if ($line =~ /\bstatic\s.*=\s*(0|NULL|false)\s*;/) { ERROR("INITIALISED_STATIC", "do not initialise statics to 0 or NULL\n" . $herecurr); } # check for static const char * arrays. if ($line =~ /\bstatic\s+const\s+char\s*\*\s*(\w+)\s*\[\s*\]\s*=\s*/) { WARN("STATIC_CONST_CHAR_ARRAY", "static const char * array should probably be static const char * const\n" . $herecurr); } # check for static char foo[] = "bar" declarations. if ($line =~ /\bstatic\s+char\s+(\w+)\s*\[\s*\]\s*=\s*"/) { WARN("STATIC_CONST_CHAR_ARRAY", "static char array declaration should probably be static const char\n" . $herecurr); } # check for declarations of struct pci_device_id if ($line =~ /\bstruct\s+pci_device_id\s+\w+\s*\[\s*\]\s*\=\s*\{/) { WARN("DEFINE_PCI_DEVICE_TABLE", "Use DEFINE_PCI_DEVICE_TABLE for struct pci_device_id\n" . $herecurr); } # check for new typedefs, only function parameters and sparse annotations # make sense. if ($line =~ /\btypedef\s/ && $line !~ /\btypedef\s+$Type\s*\(\s*\*?$Ident\s*\)\s*\(/ && $line !~ /\btypedef\s+$Type\s+$Ident\s*\(/ && $line !~ /\b$typeTypedefs\b/ && $line !~ /\b__bitwise(?:__|)\b/) { WARN("NEW_TYPEDEFS", "do not add new typedefs\n" . $herecurr); } # * goes on variable not on type # (char*[ const]) while ($line =~ m{(\($NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)\))}g) { #print "AA<$1>\n"; my ($from, $to) = ($2, $2); # Should start with a space. $to =~ s/^(\S)/ $1/; # Should not end with a space. $to =~ s/\s+$//; # '*'s should not have spaces between. while ($to =~ s/\*\s+\*/\*\*/) { } #print "from<$from> to<$to>\n"; if ($from ne $to) { ERROR("POINTER_LOCATION", "\"(foo$from)\" should be \"(foo$to)\"\n" . $herecurr); } } while ($line =~ m{(\b$NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)($Ident))}g) { #print "BB<$1>\n"; my ($from, $to, $ident) = ($2, $2, $3); # Should start with a space. $to =~ s/^(\S)/ $1/; # Should not end with a space. $to =~ s/\s+$//; # '*'s should not have spaces between. while ($to =~ s/\*\s+\*/\*\*/) { } # Modifiers should have spaces. $to =~ s/(\b$Modifier$)/$1 /; #print "from<$from> to<$to> ident<$ident>\n"; if ($from ne $to && $ident !~ /^$Modifier$/) { ERROR("POINTER_LOCATION", "\"foo${from}bar\" should be \"foo${to}bar\"\n" . $herecurr); } } # # no BUG() or BUG_ON() # if ($line =~ /\b(BUG|BUG_ON)\b/) { # print "Try to use WARN_ON & Recovery code rather than BUG() or BUG_ON()\n"; # print "$herecurr"; # $clean = 0; # } if ($line =~ /\bLINUX_VERSION_CODE\b/) { WARN("LINUX_VERSION_CODE", "LINUX_VERSION_CODE should be avoided, code should be for the version to which it is merged\n" . $herecurr); } # check for uses of printk_ratelimit if ($line =~ /\bprintk_ratelimit\s*\(/) { WARN("PRINTK_RATELIMITED", "Prefer printk_ratelimited or pr__ratelimited to printk_ratelimit\n" . $herecurr); } # printk should use KERN_* levels. Note that follow on printk's on the # same line do not need a level, so we use the current block context # to try and find and validate the current printk. In summary the current # printk includes all preceding printk's which have no newline on the end. # we assume the first bad printk is the one to report. if ($line =~ /\bprintk\((?!KERN_)\s*"/) { my $ok = 0; for (my $ln = $linenr - 1; $ln >= $first_line; $ln--) { #print "CHECK<$lines[$ln - 1]\n"; # we have a preceding printk if it ends # with "\n" ignore it, else it is to blame if ($lines[$ln - 1] =~ m{\bprintk\(}) { if ($rawlines[$ln - 1] !~ m{\\n"}) { $ok = 1; } last; } } if ($ok == 0) { WARN("PRINTK_WITHOUT_KERN_LEVEL", "printk() should include KERN_ facility level\n" . $herecurr); } } if ($line =~ /\bprintk\s*\(\s*KERN_([A-Z]+)/) { my $orig = $1; my $level = lc($orig); $level = "warn" if ($level eq "warning"); my $level2 = $level; $level2 = "dbg" if ($level eq "debug"); WARN("PREFER_PR_LEVEL", "Prefer netdev_$level2(netdev, ... then dev_$level2(dev, ... then pr_$level(... to printk(KERN_$orig ...\n" . $herecurr); } if ($line =~ /\bpr_warning\s*\(/) { WARN("PREFER_PR_LEVEL", "Prefer pr_warn(... to pr_warning(...\n" . $herecurr); } if ($line =~ /\bdev_printk\s*\(\s*KERN_([A-Z]+)/) { my $orig = $1; my $level = lc($orig); $level = "warn" if ($level eq "warning"); $level = "dbg" if ($level eq "debug"); WARN("PREFER_DEV_LEVEL", "Prefer dev_$level(... to dev_printk(KERN_$orig, ...\n" . $herecurr); } # function brace can't be on same line, except for #defines of do while, # or if closed on same line if (($line=~/$Type\s*$Ident\(.*\).*\s{/) and !($line=~/\#\s*define.*do\s{/) and !($line=~/}/)) { ERROR("OPEN_BRACE", "open brace '{' following function declarations go on the next line\n" . $herecurr); } # open braces for enum, union and struct go on the same line. if ($line =~ /^.\s*{/ && $prevline =~ /^.\s*(?:typedef\s+)?(enum|union|struct)(?:\s+$Ident)?\s*$/) { ERROR("OPEN_BRACE", "open brace '{' following $1 go on the same line\n" . $hereprev); } # missing space after union, struct or enum definition if ($line =~ /^.\s*(?:typedef\s+)?(enum|union|struct)(?:\s+$Ident)?(?:\s+$Ident)?[=\{]/) { WARN("SPACING", "missing space after $1 definition\n" . $herecurr); } # check for spacing round square brackets; allowed: # 1. with a type on the left -- int [] a; # 2. at the beginning of a line for slice initialisers -- [0...10] = 5, # 3. inside a curly brace -- = { [0...10] = 5 } while ($line =~ /(.*?\s)\[/g) { my ($where, $prefix) = ($-[1], $1); if ($prefix !~ /$Type\s+$/ && ($where != 0 || $prefix !~ /^.\s+$/) && $prefix !~ /[{,]\s+$/) { ERROR("BRACKET_SPACE", "space prohibited before open square bracket '['\n" . $herecurr); } } # check for spaces between functions and their parentheses. while ($line =~ /($Ident)\s+\(/g) { my $name = $1; my $ctx_before = substr($line, 0, $-[1]); my $ctx = "$ctx_before$name"; # Ignore those directives where spaces _are_ permitted. if ($name =~ /^(?: if|for|while|switch|return|case| volatile|__volatile__| __attribute__|format|__extension__| asm|__asm__)$/x) { # cpp #define statements have non-optional spaces, ie # if there is a space between the name and the open # parenthesis it is simply not a parameter group. } elsif ($ctx_before =~ /^.\s*\#\s*define\s*$/) { # cpp #elif statement condition may start with a ( } elsif ($ctx =~ /^.\s*\#\s*elif\s*$/) { # If this whole things ends with a type its most # likely a typedef for a function. } elsif ($ctx =~ /$Type$/) { } else { WARN("SPACING", "space prohibited between function name and open parenthesis '('\n" . $herecurr); } } # check for whitespace before a non-naked semicolon if ($line =~ /^\+.*\S\s+;/) { CHK("SPACING", "space prohibited before semicolon\n" . $herecurr); } # Check operator spacing. if (!($line=~/\#\s*include/)) { my $ops = qr{ <<=|>>=|<=|>=|==|!=| \+=|-=|\*=|\/=|%=|\^=|\|=|&=| =>|->|<<|>>|<|>|=|!|~| &&|\|\||,|\^|\+\+|--|&|\||\+|-|\*|\/|%| \?|: }x; my @elements = split(/($ops|;)/, $opline); my $off = 0; my $blank = copy_spacing($opline); for (my $n = 0; $n < $#elements; $n += 2) { $off += length($elements[$n]); # Pick up the preceding and succeeding characters. my $ca = substr($opline, 0, $off); my $cc = ''; if (length($opline) >= ($off + length($elements[$n + 1]))) { $cc = substr($opline, $off + length($elements[$n + 1])); } my $cb = "$ca$;$cc"; my $a = ''; $a = 'V' if ($elements[$n] ne ''); $a = 'W' if ($elements[$n] =~ /\s$/); $a = 'C' if ($elements[$n] =~ /$;$/); $a = 'B' if ($elements[$n] =~ /(\[|\()$/); $a = 'O' if ($elements[$n] eq ''); $a = 'E' if ($ca =~ /^\s*$/); my $op = $elements[$n + 1]; my $c = ''; if (defined $elements[$n + 2]) { $c = 'V' if ($elements[$n + 2] ne ''); $c = 'W' if ($elements[$n + 2] =~ /^\s/); $c = 'C' if ($elements[$n + 2] =~ /^$;/); $c = 'B' if ($elements[$n + 2] =~ /^(\)|\]|;)/); $c = 'O' if ($elements[$n + 2] eq ''); $c = 'E' if ($elements[$n + 2] =~ /^\s*\\$/); } else { $c = 'E'; } my $ctx = "${a}x${c}"; my $at = "(ctx:$ctx)"; my $ptr = substr($blank, 0, $off) . "^"; my $hereptr = "$hereline$ptr\n"; # Pull out the value of this operator. my $op_type = substr($curr_values, $off + 1, 1); # Get the full operator variant. my $opv = $op . substr($curr_vars, $off, 1); # Ignore operators passed as parameters. if ($op_type ne 'V' && $ca =~ /\s$/ && $cc =~ /^\s*,/) { # # Ignore comments # } elsif ($op =~ /^$;+$/) { # ; should have either the end of line or a space or \ after it } elsif ($op eq ';') { if ($ctx !~ /.x[WEBC]/ && $cc !~ /^\\/ && $cc !~ /^;/) { ERROR("SPACING", "space required after that '$op' $at\n" . $hereptr); } # // is a comment } elsif ($op eq '//') { # No spaces for: # -> # : when part of a bitfield } elsif ($op eq '->' || $opv eq ':B') { if ($ctx =~ /Wx.|.xW/) { ERROR("SPACING", "spaces prohibited around that '$op' $at\n" . $hereptr); } # , must have a space on the right. } elsif ($op eq ',') { if ($ctx !~ /.x[WEC]/ && $cc !~ /^}/) { ERROR("SPACING", "space required after that '$op' $at\n" . $hereptr); } # '*' as part of a type definition -- reported already. } elsif ($opv eq '*_') { #warn "'*' is part of type\n"; # unary operators should have a space before and # none after. May be left adjacent to another # unary operator, or a cast } elsif ($op eq '!' || $op eq '~' || $opv eq '*U' || $opv eq '-U' || $opv eq '&U' || $opv eq '&&U') { if ($ctx !~ /[WEBC]x./ && $ca !~ /(?:\)|!|~|\*|-|\&|\||\+\+|\-\-|\{)$/) { ERROR("SPACING", "space required before that '$op' $at\n" . $hereptr); } if ($op eq '*' && $cc =~/\s*$Modifier\b/) { # A unary '*' may be const } elsif ($ctx =~ /.xW/) { ERROR("SPACING", "space prohibited after that '$op' $at\n" . $hereptr); } # unary ++ and unary -- are allowed no space on one side. } elsif ($op eq '++' or $op eq '--') { if ($ctx !~ /[WEOBC]x[^W]/ && $ctx !~ /[^W]x[WOBEC]/) { ERROR("SPACING", "space required one side of that '$op' $at\n" . $hereptr); } if ($ctx =~ /Wx[BE]/ || ($ctx =~ /Wx./ && $cc =~ /^;/)) { ERROR("SPACING", "space prohibited before that '$op' $at\n" . $hereptr); } if ($ctx =~ /ExW/) { ERROR("SPACING", "space prohibited after that '$op' $at\n" . $hereptr); } # << and >> may either have or not have spaces both sides } elsif ($op eq '<<' or $op eq '>>' or $op eq '&' or $op eq '^' or $op eq '|' or $op eq '+' or $op eq '-' or $op eq '*' or $op eq '/' or $op eq '%') { if ($ctx =~ /Wx[^WCE]|[^WCE]xW/) { ERROR("SPACING", "need consistent spacing around '$op' $at\n" . $hereptr); } # A colon needs no spaces before when it is # terminating a case value or a label. } elsif ($opv eq ':C' || $opv eq ':L') { if ($ctx =~ /Wx./) { ERROR("SPACING", "space prohibited before that '$op' $at\n" . $hereptr); } # All the others need spaces both sides. } elsif ($ctx !~ /[EWC]x[CWE]/) { my $ok = 0; # Ignore email addresses if (($op eq '<' && $cc =~ /^\S+\@\S+>/) || ($op eq '>' && $ca =~ /<\S+\@\S+$/)) { $ok = 1; } # Ignore ?: if (($opv eq ':O' && $ca =~ /\?$/) || ($op eq '?' && $cc =~ /^:/)) { $ok = 1; } if ($ok == 0) { ERROR("SPACING", "spaces required around that '$op' $at\n" . $hereptr); } } $off += length($elements[$n + 1]); } } # check for multiple assignments if ($line =~ /^.\s*$Lval\s*=\s*$Lval\s*=(?!=)/) { CHK("MULTIPLE_ASSIGNMENTS", "multiple assignments should be avoided\n" . $herecurr); } ## # check for multiple declarations, allowing for a function declaration ## # continuation. ## if ($line =~ /^.\s*$Type\s+$Ident(?:\s*=[^,{]*)?\s*,\s*$Ident.*/ && ## $line !~ /^.\s*$Type\s+$Ident(?:\s*=[^,{]*)?\s*,\s*$Type\s*$Ident.*/) { ## ## # Remove any bracketed sections to ensure we do not ## # falsly report the parameters of functions. ## my $ln = $line; ## while ($ln =~ s/\([^\(\)]*\)//g) { ## } ## if ($ln =~ /,/) { ## WARN("MULTIPLE_DECLARATION", ## "declaring multiple variables together should be avoided\n" . $herecurr); ## } ## } #need space before brace following if, while, etc if (($line =~ /\(.*\){/ && $line !~ /\($Type\){/) || $line =~ /do{/) { ERROR("SPACING", "space required before the open brace '{'\n" . $herecurr); } # closing brace should have a space following it when it has anything # on the line if ($line =~ /}(?!(?:,|;|\)))\S/) { ERROR("SPACING", "space required after that close brace '}'\n" . $herecurr); } # check spacing on square brackets if ($line =~ /\[\s/ && $line !~ /\[\s*$/) { ERROR("SPACING", "space prohibited after that open square bracket '['\n" . $herecurr); } if ($line =~ /\s\]/) { ERROR("SPACING", "space prohibited before that close square bracket ']'\n" . $herecurr); } # check spacing on parentheses if ($line =~ /\(\s/ && $line !~ /\(\s*(?:\\)?$/ && $line !~ /for\s*\(\s+;/) { ERROR("SPACING", "space prohibited after that open parenthesis '('\n" . $herecurr); } if ($line =~ /(\s+)\)/ && $line !~ /^.\s*\)/ && $line !~ /for\s*\(.*;\s+\)/ && $line !~ /:\s+\)/) { ERROR("SPACING", "space prohibited before that close parenthesis ')'\n" . $herecurr); } #goto labels aren't indented, allow a single space however if ($line=~/^.\s+[A-Za-z\d_]+:(?![0-9]+)/ and !($line=~/^. [A-Za-z\d_]+:/) and !($line=~/^.\s+default:/)) { WARN("INDENTED_LABEL", "labels should not be indented\n" . $herecurr); } # Return is not a function. if (defined($stat) && $stat =~ /^.\s*return(\s*)(\(.*);/s) { my $spacing = $1; my $value = $2; # Flatten any parentheses $value =~ s/\(/ \(/g; $value =~ s/\)/\) /g; while ($value =~ s/\[[^\[\]]*\]/1/ || $value !~ /(?:$Ident|-?$Constant)\s* $Compare\s* (?:$Ident|-?$Constant)/x && $value =~ s/\([^\(\)]*\)/1/) { } #print "value<$value>\n"; if ($value =~ /^\s*(?:$Ident|-?$Constant)\s*$/) { ERROR("RETURN_PARENTHESES", "return is not a function, parentheses are not required\n" . $herecurr); } elsif ($spacing !~ /\s+/) { ERROR("SPACING", "space required before the open parenthesis '('\n" . $herecurr); } } # Return of what appears to be an errno should normally be -'ve if ($line =~ /^.\s*return\s*(E[A-Z]*)\s*;/) { my $name = $1; if ($name ne 'EOF' && $name ne 'ERROR') { WARN("USE_NEGATIVE_ERRNO", "return of an errno should typically be -ve (return -$1)\n" . $herecurr); } } # Need a space before open parenthesis after if, while etc if ($line=~/\b(if|while|for|switch)\(/) { ERROR("SPACING", "space required before the open parenthesis '('\n" . $herecurr); } # Check for illegal assignment in if conditional -- and check for trailing # statements after the conditional. if ($line =~ /do\s*(?!{)/) { ($stat, $cond, $line_nr_next, $remain_next, $off_next) = ctx_statement_block($linenr, $realcnt, 0) if (!defined $stat); my ($stat_next) = ctx_statement_block($line_nr_next, $remain_next, $off_next); $stat_next =~ s/\n./\n /g; ##print "stat<$stat> stat_next<$stat_next>\n"; if ($stat_next =~ /^\s*while\b/) { # If the statement carries leading newlines, # then count those as offsets. my ($whitespace) = ($stat_next =~ /^((?:\s*\n[+-])*\s*)/s); my $offset = statement_rawlines($whitespace) - 1; $suppress_whiletrailers{$line_nr_next + $offset} = 1; } } if (!defined $suppress_whiletrailers{$linenr} && $line =~ /\b(?:if|while|for)\s*\(/ && $line !~ /^.\s*#/) { my ($s, $c) = ($stat, $cond); if ($c =~ /\bif\s*\(.*[^<>!=]=[^=].*/s) { ERROR("ASSIGN_IN_IF", "do not use assignment in if condition\n" . $herecurr); } # Find out what is on the end of the line after the # conditional. substr($s, 0, length($c), ''); $s =~ s/\n.*//g; $s =~ s/$;//g; # Remove any comments if (length($c) && $s !~ /^\s*{?\s*\\*\s*$/ && $c !~ /}\s*while\s*/) { # Find out how long the conditional actually is. my @newlines = ($c =~ /\n/gs); my $cond_lines = 1 + $#newlines; my $stat_real = ''; $stat_real = raw_line($linenr, $cond_lines) . "\n" if ($cond_lines); if (defined($stat_real) && $cond_lines > 1) { $stat_real = "[...]\n$stat_real"; } ERROR("TRAILING_STATEMENTS", "trailing statements should be on next line\n" . $herecurr . $stat_real); } } # Check for bitwise tests written as boolean if ($line =~ / (?: (?:\[|\(|\&\&|\|\|) \s*0[xX][0-9]+\s* (?:\&\&|\|\|) | (?:\&\&|\|\|) \s*0[xX][0-9]+\s* (?:\&\&|\|\||\)|\]) )/x) { WARN("HEXADECIMAL_BOOLEAN_TEST", "boolean test with hexadecimal, perhaps just 1 \& or \|?\n" . $herecurr); } # if and else should not have general statements after it if ($line =~ /^.\s*(?:}\s*)?else\b(.*)/) { my $s = $1; $s =~ s/$;//g; # Remove any comments if ($s !~ /^\s*(?:\sif|(?:{|)\s*\\?\s*$)/) { ERROR("TRAILING_STATEMENTS", "trailing statements should be on next line\n" . $herecurr); } } # if should not continue a brace if ($line =~ /}\s*if\b/) { ERROR("TRAILING_STATEMENTS", "trailing statements should be on next line\n" . $herecurr); } # case and default should not have general statements after them if ($line =~ /^.\s*(?:case\s*.*|default\s*):/g && $line !~ /\G(?: (?:\s*$;*)(?:\s*{)?(?:\s*$;*)(?:\s*\\)?\s*$| \s*return\s+ )/xg) { ERROR("TRAILING_STATEMENTS", "trailing statements should be on next line\n" . $herecurr); } # Check for }else {, these must be at the same # indent level to be relevant to each other. if ($prevline=~/}\s*$/ and $line=~/^.\s*else\s*/ and $previndent == $indent) { ERROR("ELSE_AFTER_BRACE", "else should follow close brace '}'\n" . $hereprev); } if ($prevline=~/}\s*$/ and $line=~/^.\s*while\s*/ and $previndent == $indent) { my ($s, $c) = ctx_statement_block($linenr, $realcnt, 0); # Find out what is on the end of the line after the # conditional. substr($s, 0, length($c), ''); $s =~ s/\n.*//g; if ($s =~ /^\s*;/) { ERROR("WHILE_AFTER_BRACE", "while should follow close brace '}'\n" . $hereprev); } } #CamelCase while ($line =~ m{($Constant|$Lval)}g) { my $var = $1; if ($var !~ /$Constant/ && $var =~ /[A-Z]\w*[a-z]|[a-z]\w*[A-Z]/ && $var !~ /"^(?:Clear|Set|TestClear|TestSet|)Page[A-Z]/ && !defined $camelcase{$var}) { $camelcase{$var} = 1; WARN("CAMELCASE", "Avoid CamelCase: <$var>\n" . $herecurr); } } #no spaces allowed after \ in define if ($line=~/\#\s*define.*\\\s$/) { WARN("WHITESPACE_AFTER_LINE_CONTINUATION", "Whitepspace after \\ makes next lines useless\n" . $herecurr); } #warn if is #included and is available (uses RAW line) if ($tree && $rawline =~ m{^.\s*\#\s*include\s*\}) { my $file = "$1.h"; my $checkfile = "include/linux/$file"; if (-f "$root/$checkfile" && $realfile ne $checkfile && $1 !~ /$allowed_asm_includes/) { if ($realfile =~ m{^arch/}) { CHK("ARCH_INCLUDE_LINUX", "Consider using #include instead of \n" . $herecurr); } else { WARN("INCLUDE_LINUX", "Use #include instead of \n" . $herecurr); } } } # multi-statement macros should be enclosed in a do while loop, grab the # first statement and ensure its the whole macro if its not enclosed # in a known good container if ($realfile !~ m@/vmlinux.lds.h$@ && $line =~ /^.\s*\#\s*define\s*$Ident(\()?/) { my $ln = $linenr; my $cnt = $realcnt; my ($off, $dstat, $dcond, $rest); my $ctx = ''; ($dstat, $dcond, $ln, $cnt, $off) = ctx_statement_block($linenr, $realcnt, 0); $ctx = $dstat; #print "dstat<$dstat> dcond<$dcond> cnt<$cnt> off<$off>\n"; #print "LINE<$lines[$ln-1]> len<" . length($lines[$ln-1]) . "\n"; $dstat =~ s/^.\s*\#\s*define\s+$Ident(?:\([^\)]*\))?\s*//; $dstat =~ s/$;//g; $dstat =~ s/\\\n.//g; $dstat =~ s/^\s*//s; $dstat =~ s/\s*$//s; # Flatten any parentheses and braces while ($dstat =~ s/\([^\(\)]*\)/1/ || $dstat =~ s/\{[^\{\}]*\}/1/ || $dstat =~ s/\[[^\[\]]*\]/1/) { } # Flatten any obvious string concatentation. while ($dstat =~ s/("X*")\s*$Ident/$1/ || $dstat =~ s/$Ident\s*("X*")/$1/) { } my $exceptions = qr{ $Declare| module_param_named| MODULE_PARM_DESC| DECLARE_PER_CPU| DEFINE_PER_CPU| __typeof__\(| union| struct| \.$Ident\s*=\s*| ^\"|\"$ }x; #print "REST<$rest> dstat<$dstat> ctx<$ctx>\n"; if ($dstat ne '' && $dstat !~ /^(?:$Ident|-?$Constant),$/ && # 10, // foo(), $dstat !~ /^(?:$Ident|-?$Constant);$/ && # foo(); $dstat !~ /^[!~-]?(?:$Ident|$Constant)$/ && # 10 // foo() // !foo // ~foo // -foo $dstat !~ /^'X'$/ && # character constants $dstat !~ /$exceptions/ && $dstat !~ /^\.$Ident\s*=/ && # .foo = $dstat !~ /^do\s*$Constant\s*while\s*$Constant;?$/ && # do {...} while (...); // do {...} while (...) $dstat !~ /^for\s*$Constant$/ && # for (...) $dstat !~ /^for\s*$Constant\s+(?:$Ident|-?$Constant)$/ && # for (...) bar() $dstat !~ /^do\s*{/ && # do {... $dstat !~ /^\({/) # ({... { $ctx =~ s/\n*$//; my $herectx = $here . "\n"; my $cnt = statement_rawlines($ctx); for (my $n = 0; $n < $cnt; $n++) { $herectx .= raw_line($linenr, $n) . "\n"; } if ($dstat =~ /;/) { ERROR("MULTISTATEMENT_MACRO_USE_DO_WHILE", "Macros with multiple statements should be enclosed in a do - while loop\n" . "$herectx"); } else { ERROR("COMPLEX_MACRO", "Macros with complex values should be enclosed in parenthesis\n" . "$herectx"); } } # check for line continuations outside of #defines, preprocessor #, and asm } else { if ($prevline !~ /^..*\\$/ && $line !~ /^\+\s*\#.*\\$/ && # preprocessor $line !~ /^\+.*\b(__asm__|asm)\b.*\\$/ && # asm $line =~ /^\+.*\\$/) { WARN("LINE_CONTINUATIONS", "Avoid unnecessary line continuations\n" . $herecurr); } } # do {} while (0) macro tests: # single-statement macros do not need to be enclosed in do while (0) loop, # macro should not end with a semicolon if ($^V && $^V ge 5.10.0 && $realfile !~ m@/vmlinux.lds.h$@ && $line =~ /^.\s*\#\s*define\s+$Ident(\()?/) { my $ln = $linenr; my $cnt = $realcnt; my ($off, $dstat, $dcond, $rest); my $ctx = ''; ($dstat, $dcond, $ln, $cnt, $off) = ctx_statement_block($linenr, $realcnt, 0); $ctx = $dstat; $dstat =~ s/\\\n.//g; if ($dstat =~ /^\+\s*#\s*define\s+$Ident\s*${balanced_parens}\s*do\s*{(.*)\s*}\s*while\s*\(\s*0\s*\)\s*([;\s]*)\s*$/) { my $stmts = $2; my $semis = $3; $ctx =~ s/\n*$//; my $cnt = statement_rawlines($ctx); my $herectx = $here . "\n"; for (my $n = 0; $n < $cnt; $n++) { $herectx .= raw_line($linenr, $n) . "\n"; } if (($stmts =~ tr/;/;/) == 1 && $stmts !~ /^\s*(if|while|for|switch)\b/) { WARN("SINGLE_STATEMENT_DO_WHILE_MACRO", "Single statement macros should not use a do {} while (0) loop\n" . "$herectx"); } if (defined $semis && $semis ne "") { WARN("DO_WHILE_MACRO_WITH_TRAILING_SEMICOLON", "do {} while (0) macros should not be semicolon terminated\n" . "$herectx"); } } } # make sure symbols are always wrapped with VMLINUX_SYMBOL() ... # all assignments may have only one of the following with an assignment: # . # ALIGN(...) # VMLINUX_SYMBOL(...) if ($realfile eq 'vmlinux.lds.h' && $line =~ /(?:(?:^|\s)$Ident\s*=|=\s*$Ident(?:\s|$))/) { WARN("MISSING_VMLINUX_SYMBOL", "vmlinux.lds.h needs VMLINUX_SYMBOL() around C-visible symbols\n" . $herecurr); } # check for redundant bracing round if etc if ($line =~ /(^.*)\bif\b/ && $1 !~ /else\s*$/) { my ($level, $endln, @chunks) = ctx_statement_full($linenr, $realcnt, 1); #print "chunks<$#chunks> linenr<$linenr> endln<$endln> level<$level>\n"; #print "APW: <<$chunks[1][0]>><<$chunks[1][1]>>\n"; if ($#chunks > 0 && $level == 0) { my @allowed = (); my $allow = 0; my $seen = 0; my $herectx = $here . "\n"; my $ln = $linenr - 1; for my $chunk (@chunks) { my ($cond, $block) = @{$chunk}; # If the condition carries leading newlines, then count those as offsets. my ($whitespace) = ($cond =~ /^((?:\s*\n[+-])*\s*)/s); my $offset = statement_rawlines($whitespace) - 1; $allowed[$allow] = 0; #print "COND<$cond> whitespace<$whitespace> offset<$offset>\n"; # We have looked at and allowed this specific line. $suppress_ifbraces{$ln + $offset} = 1; $herectx .= "$rawlines[$ln + $offset]\n[...]\n"; $ln += statement_rawlines($block) - 1; substr($block, 0, length($cond), ''); $seen++ if ($block =~ /^\s*{/); #print "cond<$cond> block<$block> allowed<$allowed[$allow]>\n"; if (statement_lines($cond) > 1) { #print "APW: ALLOWED: cond<$cond>\n"; $allowed[$allow] = 1; } if ($block =~/\b(?:if|for|while)\b/) { #print "APW: ALLOWED: block<$block>\n"; $allowed[$allow] = 1; } if (statement_block_size($block) > 1) { #print "APW: ALLOWED: lines block<$block>\n"; $allowed[$allow] = 1; } $allow++; } if ($seen) { my $sum_allowed = 0; foreach (@allowed) { $sum_allowed += $_; } if ($sum_allowed == 0) { WARN("BRACES", "braces {} are not necessary for any arm of this statement\n" . $herectx); } elsif ($sum_allowed != $allow && $seen != $allow) { CHK("BRACES", "braces {} should be used on all arms of this statement\n" . $herectx); } } } } if (!defined $suppress_ifbraces{$linenr - 1} && $line =~ /\b(if|while|for|else)\b/) { my $allowed = 0; # Check the pre-context. if (substr($line, 0, $-[0]) =~ /(\}\s*)$/) { #print "APW: ALLOWED: pre<$1>\n"; $allowed = 1; } my ($level, $endln, @chunks) = ctx_statement_full($linenr, $realcnt, $-[0]); # Check the condition. my ($cond, $block) = @{$chunks[0]}; #print "CHECKING<$linenr> cond<$cond> block<$block>\n"; if (defined $cond) { substr($block, 0, length($cond), ''); } if (statement_lines($cond) > 1) { #print "APW: ALLOWED: cond<$cond>\n"; $allowed = 1; } if ($block =~/\b(?:if|for|while)\b/) { #print "APW: ALLOWED: block<$block>\n"; $allowed = 1; } if (statement_block_size($block) > 1) { #print "APW: ALLOWED: lines block<$block>\n"; $allowed = 1; } # Check the post-context. if (defined $chunks[1]) { my ($cond, $block) = @{$chunks[1]}; if (defined $cond) { substr($block, 0, length($cond), ''); } if ($block =~ /^\s*\{/) { #print "APW: ALLOWED: chunk-1 block<$block>\n"; $allowed = 1; } } if ($level == 0 && $block =~ /^\s*\{/ && !$allowed) { my $herectx = $here . "\n"; my $cnt = statement_rawlines($block); for (my $n = 0; $n < $cnt; $n++) { $herectx .= raw_line($linenr, $n) . "\n"; } WARN("BRACES", "braces {} are not necessary for single statement blocks\n" . $herectx); } } # check for unnecessary blank lines around braces if (($line =~ /^..*}\s*$/ && $prevline =~ /^.\s*$/)) { CHK("BRACES", "Blank lines aren't necessary before a close brace '}'\n" . $hereprev); } if (($line =~ /^.\s*$/ && $prevline =~ /^..*{\s*$/)) { CHK("BRACES", "Blank lines aren't necessary after an open brace '{'\n" . $hereprev); } # no volatiles please my $asm_volatile = qr{\b(__asm__|asm)\s+(__volatile__|volatile)\b}; if ($line =~ /\bvolatile\b/ && $line !~ /$asm_volatile/) { WARN("VOLATILE", "Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt\n" . $herecurr); } # warn about #if 0 if ($line =~ /^.\s*\#\s*if\s+0\b/) { CHK("REDUNDANT_CODE", "if this code is redundant consider removing it\n" . $herecurr); } # check for needless "if () fn()" uses if ($prevline =~ /\bif\s*\(\s*($Lval)\s*\)/) { my $expr = '\s*\(\s*' . quotemeta($1) . '\s*\)\s*;'; if ($line =~ /\b(kfree|usb_free_urb|debugfs_remove(?:_recursive)?)$expr/) { WARN('NEEDLESS_IF', "$1(NULL) is safe this check is probably not required\n" . $hereprev); } } # prefer usleep_range over udelay if ($line =~ /\budelay\s*\(\s*(\d+)\s*\)/) { # ignore udelay's < 10, however if (! ($1 < 10) ) { CHK("USLEEP_RANGE", "usleep_range is preferred over udelay; see Documentation/timers/timers-howto.txt\n" . $line); } } # warn about unexpectedly long msleep's if ($line =~ /\bmsleep\s*\((\d+)\);/) { if ($1 < 20) { WARN("MSLEEP", "msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.txt\n" . $line); } } # warn about #ifdefs in C files # if ($line =~ /^.\s*\#\s*if(|n)def/ && ($realfile =~ /\.c$/)) { # print "#ifdef in C files should be avoided\n"; # print "$herecurr"; # $clean = 0; # } # warn about spacing in #ifdefs if ($line =~ /^.\s*\#\s*(ifdef|ifndef|elif)\s\s+/) { ERROR("SPACING", "exactly one space required after that #$1\n" . $herecurr); } # check for spinlock_t definitions without a comment. if ($line =~ /^.\s*(struct\s+mutex|spinlock_t)\s+\S+;/ || $line =~ /^.\s*(DEFINE_MUTEX)\s*\(/) { my $which = $1; if (!ctx_has_comment($first_line, $linenr)) { CHK("UNCOMMENTED_DEFINITION", "$1 definition without comment\n" . $herecurr); } } # check for memory barriers without a comment. if ($line =~ /\b(mb|rmb|wmb|read_barrier_depends|smp_mb|smp_rmb|smp_wmb|smp_read_barrier_depends)\(/) { if (!ctx_has_comment($first_line, $linenr)) { CHK("MEMORY_BARRIER", "memory barrier without comment\n" . $herecurr); } } # check of hardware specific defines if ($line =~ m@^.\s*\#\s*if.*\b(__i386__|__powerpc64__|__sun__|__s390x__)\b@ && $realfile !~ m@include/asm-@) { CHK("ARCH_DEFINES", "architecture specific defines should be avoided\n" . $herecurr); } # Check that the storage class is at the beginning of a declaration if ($line =~ /\b$Storage\b/ && $line !~ /^.\s*$Storage\b/) { WARN("STORAGE_CLASS", "storage class should be at the beginning of the declaration\n" . $herecurr) } # check the location of the inline attribute, that it is between # storage class and type. if ($line =~ /\b$Type\s+$Inline\b/ || $line =~ /\b$Inline\s+$Storage\b/) { ERROR("INLINE_LOCATION", "inline keyword should sit between storage class and type\n" . $herecurr); } # Check for __inline__ and __inline, prefer inline if ($line =~ /\b(__inline__|__inline)\b/) { WARN("INLINE", "plain inline is preferred over $1\n" . $herecurr); } # Check for __attribute__ packed, prefer __packed if ($line =~ /\b__attribute__\s*\(\s*\(.*\bpacked\b/) { WARN("PREFER_PACKED", "__packed is preferred over __attribute__((packed))\n" . $herecurr); } # Check for __attribute__ aligned, prefer __aligned if ($line =~ /\b__attribute__\s*\(\s*\(.*aligned/) { WARN("PREFER_ALIGNED", "__aligned(size) is preferred over __attribute__((aligned(size)))\n" . $herecurr); } # Check for __attribute__ format(printf, prefer __printf if ($line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*printf/) { WARN("PREFER_PRINTF", "__printf(string-index, first-to-check) is preferred over __attribute__((format(printf, string-index, first-to-check)))\n" . $herecurr); } # Check for __attribute__ format(scanf, prefer __scanf if ($line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*scanf\b/) { WARN("PREFER_SCANF", "__scanf(string-index, first-to-check) is preferred over __attribute__((format(scanf, string-index, first-to-check)))\n" . $herecurr); } # check for sizeof(&) if ($line =~ /\bsizeof\s*\(\s*\&/) { WARN("SIZEOF_ADDRESS", "sizeof(& should be avoided\n" . $herecurr); } # check for sizeof without parenthesis if ($line =~ /\bsizeof\s+((?:\*\s*|)$Lval|$Type(?:\s+$Lval|))/) { WARN("SIZEOF_PARENTHESIS", "sizeof $1 should be sizeof($1)\n" . $herecurr); } # check for line continuations in quoted strings with odd counts of " if ($rawline =~ /\\$/ && $rawline =~ tr/"/"/ % 2) { WARN("LINE_CONTINUATIONS", "Avoid line continuations in quoted strings\n" . $herecurr); } # check for struct spinlock declarations if ($line =~ /^.\s*\bstruct\s+spinlock\s+\w+\s*;/) { WARN("USE_SPINLOCK_T", "struct spinlock should be spinlock_t\n" . $herecurr); } # Check for misused memsets if ($^V && $^V ge 5.10.0 && defined $stat && $stat =~ /^\+(?:.*?)\bmemset\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*$FuncArg\s*\)/s) { my $ms_addr = $2; my $ms_val = $7; my $ms_size = $12; if ($ms_size =~ /^(0x|)0$/i) { ERROR("MEMSET", "memset to 0's uses 0 as the 2nd argument, not the 3rd\n" . "$here\n$stat\n"); } elsif ($ms_size =~ /^(0x|)1$/i) { WARN("MEMSET", "single byte memset is suspicious. Swapped 2nd/3rd argument?\n" . "$here\n$stat\n"); } } # typecasts on min/max could be min_t/max_t if ($^V && $^V ge 5.10.0 && defined $stat && $stat =~ /^\+(?:.*?)\b(min|max)\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\)/) { if (defined $2 || defined $7) { my $call = $1; my $cast1 = deparenthesize($2); my $arg1 = $3; my $cast2 = deparenthesize($7); my $arg2 = $8; my $cast; if ($cast1 ne "" && $cast2 ne "" && $cast1 ne $cast2) { $cast = "$cast1 or $cast2"; } elsif ($cast1 ne "") { $cast = $cast1; } else { $cast = $cast2; } WARN("MINMAX", "$call() should probably be ${call}_t($cast, $arg1, $arg2)\n" . "$here\n$stat\n"); } } # check usleep_range arguments if ($^V && $^V ge 5.10.0 && defined $stat && $stat =~ /^\+(?:.*?)\busleep_range\s*\(\s*($FuncArg)\s*,\s*($FuncArg)\s*\)/) { my $min = $1; my $max = $7; if ($min eq $max) { WARN("USLEEP_RANGE", "usleep_range should not use min == max args; see Documentation/timers/timers-howto.txt\n" . "$here\n$stat\n"); } elsif ($min =~ /^\d+$/ && $max =~ /^\d+$/ && $min > $max) { WARN("USLEEP_RANGE", "usleep_range args reversed, use min then max; see Documentation/timers/timers-howto.txt\n" . "$here\n$stat\n"); } } # check for new externs in .c files. if ($realfile =~ /\.c$/ && defined $stat && $stat =~ /^.\s*(?:extern\s+)?$Type\s+($Ident)(\s*)\(/s) { my $function_name = $1; my $paren_space = $2; my $s = $stat; if (defined $cond) { substr($s, 0, length($cond), ''); } if ($s =~ /^\s*;/ && $function_name ne 'uninitialized_var') { WARN("AVOID_EXTERNS", "externs should be avoided in .c files\n" . $herecurr); } if ($paren_space =~ /\n/) { WARN("FUNCTION_ARGUMENTS", "arguments for function declarations should follow identifier\n" . $herecurr); } } elsif ($realfile =~ /\.c$/ && defined $stat && $stat =~ /^.\s*extern\s+/) { WARN("AVOID_EXTERNS", "externs should be avoided in .c files\n" . $herecurr); } # checks for new __setup's if ($rawline =~ /\b__setup\("([^"]*)"/) { my $name = $1; if (!grep(/$name/, @setup_docs)) { CHK("UNDOCUMENTED_SETUP", "__setup appears un-documented -- check Documentation/kernel-parameters.txt\n" . $herecurr); } } # check for pointless casting of kmalloc return if ($line =~ /\*\s*\)\s*[kv][czm]alloc(_node){0,1}\b/) { WARN("UNNECESSARY_CASTS", "unnecessary cast may hide bugs, see http://c-faq.com/malloc/mallocnocast.html\n" . $herecurr); } # check for alloc argument mismatch if ($line =~ /\b(kcalloc|kmalloc_array)\s*\(\s*sizeof\b/) { WARN("ALLOC_ARRAY_ARGS", "$1 uses number as first arg, sizeof is generally wrong\n" . $herecurr); } # check for multiple semicolons if ($line =~ /;\s*;\s*$/) { WARN("ONE_SEMICOLON", "Statements terminations use 1 semicolon\n" . $herecurr); } # check for switch/default statements without a break; if ($^V && $^V ge 5.10.0 && defined $stat && $stat =~ /^\+[$;\s]*(?:case[$;\s]+\w+[$;\s]*:[$;\s]*|)*[$;\s]*\bdefault[$;\s]*:[$;\s]*;/g) { my $ctx = ''; my $herectx = $here . "\n"; my $cnt = statement_rawlines($stat); for (my $n = 0; $n < $cnt; $n++) { $herectx .= raw_line($linenr, $n) . "\n"; } WARN("DEFAULT_NO_BREAK", "switch default: should use break\n" . $herectx); } # check for gcc specific __FUNCTION__ if ($line =~ /__FUNCTION__/) { WARN("USE_FUNC", "__func__ should be used instead of gcc specific __FUNCTION__\n" . $herecurr); } # check for use of yield() if ($line =~ /\byield\s*\(\s*\)/) { WARN("YIELD", "Using yield() is generally wrong. See yield() kernel-doc (sched/core.c)\n" . $herecurr); } # check for semaphores initialized locked if ($line =~ /^.\s*sema_init.+,\W?0\W?\)/) { WARN("CONSIDER_COMPLETION", "consider using a completion\n" . $herecurr); } # recommend kstrto* over simple_strto* and strict_strto* if ($line =~ /\b((simple|strict)_(strto(l|ll|ul|ull)))\s*\(/) { WARN("CONSIDER_KSTRTO", "$1 is obsolete, use k$3 instead\n" . $herecurr); } # check for __initcall(), use device_initcall() explicitly please if ($line =~ /^.\s*__initcall\s*\(/) { WARN("USE_DEVICE_INITCALL", "please use device_initcall() instead of __initcall()\n" . $herecurr); } # check for various ops structs, ensure they are const. my $struct_ops = qr{acpi_dock_ops| address_space_operations| backlight_ops| block_device_operations| dentry_operations| dev_pm_ops| dma_map_ops| extent_io_ops| file_lock_operations| file_operations| hv_ops| ide_dma_ops| intel_dvo_dev_ops| item_operations| iwl_ops| kgdb_arch| kgdb_io| kset_uevent_ops| lock_manager_operations| microcode_ops| mtrr_ops| neigh_ops| nlmsvc_binding| pci_raw_ops| pipe_buf_operations| platform_hibernation_ops| platform_suspend_ops| proto_ops| rpc_pipe_ops| seq_operations| snd_ac97_build_ops| soc_pcmcia_socket_ops| stacktrace_ops| sysfs_ops| tty_operations| usb_mon_operations| wd_ops}x; if ($line !~ /\bconst\b/ && $line =~ /\bstruct\s+($struct_ops)\b/) { WARN("CONST_STRUCT", "struct $1 should normally be const\n" . $herecurr); } # use of NR_CPUS is usually wrong # ignore definitions of NR_CPUS and usage to define arrays as likely right if ($line =~ /\bNR_CPUS\b/ && $line !~ /^.\s*\s*#\s*if\b.*\bNR_CPUS\b/ && $line !~ /^.\s*\s*#\s*define\b.*\bNR_CPUS\b/ && $line !~ /^.\s*$Declare\s.*\[[^\]]*NR_CPUS[^\]]*\]/ && $line !~ /\[[^\]]*\.\.\.[^\]]*NR_CPUS[^\]]*\]/ && $line !~ /\[[^\]]*NR_CPUS[^\]]*\.\.\.[^\]]*\]/) { WARN("NR_CPUS", "usage of NR_CPUS is often wrong - consider using cpu_possible(), num_possible_cpus(), for_each_possible_cpu(), etc\n" . $herecurr); } # check for %L{u,d,i} in strings my $string; while ($line =~ /(?:^|")([X\t]*)(?:"|$)/g) { $string = substr($rawline, $-[1], $+[1] - $-[1]); $string =~ s/%%/__/g; if ($string =~ /(?mutex.\n" . $herecurr); } } if ($line =~ /debugfs_create_file.*S_IWUGO/ || $line =~ /DEVICE_ATTR.*S_IWUGO/ ) { WARN("EXPORTED_WORLD_WRITABLE", "Exporting world writable files is usually an error. Consider more restrictive permissions.\n" . $herecurr); } } # If we have no input at all, then there is nothing to report on # so just keep quiet. if ($#rawlines == -1) { exit(0); } # In mailback mode only produce a report in the negative, for # things that appear to be patches. if ($mailback && ($clean == 1 || !$is_patch)) { exit(0); } # This is not a patch, and we are are in 'no-patch' mode so # just keep quiet. if (!$chk_patch && !$is_patch) { exit(0); } if (!$is_patch) { ERROR("NOT_UNIFIED_DIFF", "Does not appear to be a unified-diff format patch\n"); } if ($is_patch && $chk_signoff && $signoff == 0) { ERROR("MISSING_SIGN_OFF", "Missing Signed-off-by: line(s)\n"); } print report_dump(); if ($summary && !($clean == 1 && $quiet == 1)) { print "$filename " if ($summary_file); print "total: $cnt_error errors, $cnt_warn warnings, " . (($check)? "$cnt_chk checks, " : "") . "$cnt_lines lines checked\n"; print "\n" if ($quiet == 0); } if ($quiet == 0) { if ($^V lt 5.10.0) { print("NOTE: perl $^V is not modern enough to detect all possible issues.\n"); print("An upgrade to at least perl v5.10.0 is suggested.\n\n"); } # If there were whitespace errors which cleanpatch can fix # then suggest that. if ($rpt_cleaners) { print "NOTE: whitespace errors detected, you may wish to use scripts/cleanpatch or\n"; print " scripts/cleanfile\n\n"; $rpt_cleaners = 0; } } if ($quiet == 0 && keys %ignore_type) { print "NOTE: Ignored message types:"; foreach my $ignore (sort keys %ignore_type) { print " $ignore"; } print "\n\n"; } if ($clean == 1 && $quiet == 0) { print "$vname has no obvious style problems and is ready for submission.\n" } if ($clean == 0 && $quiet == 0) { print << "EOM"; $vname has style problems, please review. If any of these errors are false positives, please report them to the maintainer, see CHECKPATCH in MAINTAINERS. EOM } return $clean; } open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/scripts/pre-commit.sh000077500000000000000000000001261321570333100245040ustar00rootroot00000000000000#!/bin/sh exec git diff --cached | scripts/checkpatch.pl --no-signoff --no-tree -q - open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/000077500000000000000000000000001321570333100235655ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/.gitignore000066400000000000000000000000301321570333100255460ustar00rootroot00000000000000/build /toolchain /*.fw open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/CMakeLists.txt000066400000000000000000000124661321570333100263360ustar00rootroot00000000000000## # Copyright (c) 2013 Qualcomm Atheros, Inc. # # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted (subject to the limitations in the # disclaimer below) provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the # distribution. # # * Neither the name of Qualcomm Atheros nor the names of its # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE # GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT # HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED # WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR # BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, # WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE # OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN # IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ## SET(CMAKE_C_COMPILER_WORKS 1) CMAKE_MINIMUM_REQUIRED(VERSION 2.6) PROJECT(ath9k_firmware NONE) ENABLE_LANGUAGE(C) ADD_DEFINITIONS( -g -Os -Wunused-label -Wunused-variable -Wunused-value -Wpointer-arith -nostdlib -Wundef -Wunused-but-set-variable -Wmaybe-uninitialized ) ADD_DEFINITIONS( -D_RAM_ -DBIG_ENDIAN -D_BYTE_ORDER=_BIG_ENDIAN -D__XTENSA__ -DFUSION_USB_FW -DRX_SCATTER -DFUSION_USB_ENABLE_TX_STREAM -DFUSION_USB_ENABLE_RX_STREAM -DATH_ENABLE_CABQ ) SET(SOURCES magpie_fw_dev/target/init/app_start.c magpie_fw_dev/target/init/init.c magpie_fw_dev/target/init/magpie.c magpie_fw_dev/target/adf/adf_nbuf.c magpie_fw_dev/target/adf/adf_net.c magpie_fw_dev/target/adf/adf_os_defer_pvt.c magpie_fw_dev/target/adf/adf_os_dma.c magpie_fw_dev/target/adf/adf_os_irq_pvt.c magpie_fw_dev/target/adf/adf_os_timer.c magpie_fw_dev/target/buf_pool/buf_pool_static.c magpie_fw_dev/target/cmnos/dbg_api.c magpie_fw_dev/target/cmnos/cmnos_sflash.c magpie_fw_dev/target/hif/usb_api_main_patch.c wlan/ah.c wlan/ah_osdep.c wlan/ar5416Phy.c wlan/ar5416_hw.c wlan/ar5416_phy.c wlan/ratectrl_11n_ln.c wlan/if_owl.c wlan/if_ath.c wlan/if_ath_pci.c magpie_fw_dev/target/wlan/wlan_pci.c wlan/ieee80211_output.c magpie_fw_dev/target/htc/htc.c magpie_fw_dev/target/wmi/wmi_svc.c ) IF(TARGET_K2) SET(SOURCES ${SOURCES} magpie_fw_dev/target/hif/k2_HIF_usb_patch.c magpie_fw_dev/target/hif/usb_api_k2_patch.c ) SET(LIBS ${LIBS} hif) ADD_DEFINITIONS(-DPROJECT_K2) SET(PLATFORM_NAME k2) SET(SOURCES ${SOURCES} magpie_fw_dev/target/cmnos/k2_cmnos_clock_patch.c magpie_fw_dev/target/cmnos/k2_fw_cmnos_printf.c ) SET(FIRMWARE_NAME htc_9271.fw) ELSEIF(TARGET_MAGPIE) ADD_DEFINITIONS( -DROM_VER_1_1 -D_ROM_1_1_ -DPROJECT_MAGPIE -DMAGPIE_MERLIN ) SET(SOURCES ${SOURCES} magpie_fw_dev/target/hif/usb_api_magpie_patch.c magpie_fw_dev/target/rompatch/cmnos_clock_patch.c magpie_fw_dev/target/rompatch/HIF_usb_patch.c ) INCLUDE_DIRECTORIES( ${CMAKE_SOURCE_DIR}/magpie_fw_dev/target/adf ) SET(PLATFORM_NAME magpie) SET(FIRMWARE_NAME htc_7010.fw) ELSE() MESSAGE(FATAL_ERROR "Unknown target name") ENDIF() INCLUDE_DIRECTORIES( ${CMAKE_SOURCE_DIR}/include ${CMAKE_SOURCE_DIR}/magpie_fw_dev/target/ ${CMAKE_SOURCE_DIR}/magpie_fw_dev/target/inc ${CMAKE_SOURCE_DIR}/magpie_fw_dev/target/inc/xtensa-elf ${CMAKE_SOURCE_DIR}/magpie_fw_dev/target/inc/${PLATFORM_NAME} ${CMAKE_SOURCE_DIR}/magpie_fw_dev/target/inc/${PLATFORM_NAME}/${PLATFORM_NAME} ${CMAKE_SOURCE_DIR}/wlan ${CMAKE_SOURCE_DIR}/wlan/include ${CMAKE_SOURCE_DIR}/wlan/include/${PLATFORM_NAME} ${CMAKE_SOURCE_DIR}/magpie_fw_dev/target/wlan ${CMAKE_SOURCE_DIR}/magpie_fw_dev/target/cmnos ${CMAKE_SOURCE_DIR}/magpie_fw_dev/target/wmi ${CMAKE_SOURCE_DIR}/magpie_fw_dev/target/adf ${CMAKE_SOURCE_DIR}/magpie_fw_dev/target/buf_pool ${CMAKE_SOURCE_DIR}/magpie_fw_dev/target/htc ) ADD_LIBRARY(firmware ${SOURCES}) ADD_CUSTOM_COMMAND( OUTPUT fw.elf DEPENDS firmware COMMAND ${CMAKE_C_COMPILER} -nostdlib -fno-lto -Wl,--start-group ${CMAKE_BINARY_DIR}/libfirmware.a -Wl,--end-group -Wl,-T,${CMAKE_SOURCE_DIR}/ram-${PLATFORM_NAME}.ld -Wl,-T,${CMAKE_SOURCE_DIR}/rom-addrs-${PLATFORM_NAME}.ld -o fw.elf ) ADD_CUSTOM_COMMAND( OUTPUT fw.bin DEPENDS fw.elf COMMAND ${CMAKE_OBJCOPY} --change-section-lma .boot-0x400000 --change-section-vma .boot-0x400000 --change-section-lma .text-0x400000 --change-section-vma .text-0x400000 -O binary fw.elf fw.bin ) ADD_CUSTOM_COMMAND( OUTPUT ${FIRMWARE_NAME} DEPENDS fw.bin COMMAND ${CMAKE_SOURCE_DIR}/firmware-crc.pl < fw.bin > ${FIRMWARE_NAME} ) ADD_CUSTOM_TARGET(gen-firmware ALL DEPENDS ${FIRMWARE_NAME}) open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/Makefile000066400000000000000000000036211321570333100252270ustar00rootroot00000000000000## # Copyright (c) 2013 Qualcomm Atheros, Inc. # # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted (subject to the limitations in the # disclaimer below) provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the # distribution. # # * Neither the name of Qualcomm Atheros nor the names of its # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE # GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT # HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED # WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR # BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, # WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE # OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN # IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ## all: [ -d build ] || ./configure || { rm -rf build; false; } +$(MAKE) -C build/k2 +$(MAKE) -C build/magpie cp build/k2/htc_*.fw build/magpie/htc_*.fw . clean: rm -rf build htc_*.fw open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/configure000077500000000000000000000043211321570333100254740ustar00rootroot00000000000000#!/bin/sh ## # Copyright (c) 2013 Qualcomm Atheros, Inc. # # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted (subject to the limitations in the # disclaimer below) provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the # distribution. # # * Neither the name of Qualcomm Atheros nor the names of its # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE # GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT # HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED # WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR # BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, # WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE # OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN # IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ## TARGET=xtensa-elf [ -z "$CROSS_COMPILE" ] && CROSS_COMPILE="$PWD/../toolchain/inst/bin/$TARGET-" TOOLCHAIN_FILE="$PWD/build/toolchain.cmake" set -e rm -rf build mkdir -p build cat > "$TOOLCHAIN_FILE" < * * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _ATH_ROM_H_ #define _ATH_ROM_H_ #include #include #include int strcmp(const char *s1, const char *s2); LOCAL BOOLEAN bSet_configuration(void); LOCAL void HTCControlSvcProcessMsg(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t hdr_buf, adf_nbuf_t pBuffers, void *arg); LOCAL void HTCMsgRecvHandler(adf_nbuf_t hdr_buf, adf_nbuf_t buffer, void *context); void athos_indirection_table_install(void); void HIFusb_DescTraceDump(void); void _HIFusb_isr_handler(hif_handle_t); void _HIFusb_start(hif_handle_t); void mUsbEPinHighBandSet(uint8_t EPn, uint8_t dir, uint16_t size); void mUsbEPMap(uint8_t EPn, uint8_t MAP); void mUsbEPMxPtSzHigh(uint8_t EPn, uint8_t dir, uint16_t size); void mUsbEPMxPtSzLow(uint8_t EPn, uint8_t dir, uint16_t size); void mUsbFIFOConfig(uint8_t FIFOn, uint8_t cfg); void mUsbFIFOMap(uint8_t FIFOn, uint8_t MAP); #endif /* _ATH_ROM_H_ */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/000077500000000000000000000000001321570333100263615ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/000077500000000000000000000000001321570333100276475ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/adf/000077500000000000000000000000001321570333100304015ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/adf/adf_nbuf.c000077500000000000000000000357201321570333100323230ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** * This file contains buffer Abstraction routines for FreeBSD * the abstracted buffer called adf_nbuf is opaque to the * user,hence these routines should be called to manipulate * anything inside it. */ #include #include "cmnos_api.h" #include #include // ############################################################################# VDESC * __adf_nbuf_last(VBUF *buf); // ############################################################################# /** * * @brief allocate a new nbuf, * * @param hdl (adf_net handle) * @param size (size of the new buf) * @param reserve (amount of space to reserve in the head) * * @return newly allocated nbuf */ __adf_nbuf_t __adf_nbuf_alloc(adf_os_size_t size, a_uint32_t reserve, a_uint32_t align) { VBUF *buf = NULL; VDESC *desc; buf = VBUF_alloc_vbuf(); if ( buf != NULL ) { desc = VDESC_alloc_vdesc(); desc->buf_addr = (A_UINT8 *)A_ALLOCRAM(size); desc->buf_size = size; desc->next_desc = NULL; desc->data_offset = reserve; desc->data_size = 0; desc->control = 0; buf->desc_list = desc; buf->buf_length = 0; } return buf; } /** * @brief Free the nbuf * function to be called in * @param hdl * @param adf_nbuf * */ void __adf_nbuf_free(__adf_nbuf_t buf) { adf_os_assert(0); } /** * @brief reallocate the head space, call it only after the you * have called headroom * * @param adf_nbuf * @param headroom * * @return new nbuf */ __adf_nbuf_t __adf_nbuf_realloc_headroom(__adf_nbuf_t buf, a_uint32_t headroom) { adf_os_assert(0); return NULL; } /** * @brief expand the tailroom, mostly by adding the new tail * buffer, also take care of the priv * * @param buf * @param tailroom * * @return struct mbuf * (buffer with the new tailroom) */ __adf_nbuf_t __adf_nbuf_realloc_tailroom(__adf_nbuf_t buf, a_uint32_t tailroom) { adf_os_assert(0); return NULL; } /** * @brief expand the headroom or tailroom or both * * @param buf * @param headroom ( 0 if no headroom expansion req) * @param tailroom ( 0 if no tailroom expansion req) * * @return struct mbuf* (NULL if something goofed up) */ __adf_nbuf_t __adf_nbuf_expand(__adf_nbuf_t buf, a_uint32_t headroom, a_uint32_t tailroom) { adf_os_assert(0); return NULL; } /** * @brief put data in the head * * @param buf * @param len (how much data to put) * * @return new data pointer ,NULL if the len is more than the * space available in the head frag. */ a_uint8_t * __adf_nbuf_push_head(__adf_nbuf_t buf, adf_os_size_t len) { a_uint8_t *ptr = NULL; VDESC *desc = buf->desc_list; desc->data_offset -= len; desc->data_size += len; buf->buf_length += len; ptr = desc->buf_addr + desc->data_offset; return(ptr); } /** * * @brief add data in the end of tail * * @param buf * @param len (how much data to put) * * @return previous tail (data+len),NULL if the len is more than * space available */ a_uint8_t * __adf_nbuf_put_tail(__adf_nbuf_t buf, adf_os_size_t len) { a_uint8_t *tail = NULL; VDESC *last_desc = __adf_nbuf_last(buf); tail = last_desc->buf_addr + last_desc->data_offset + last_desc->data_size; last_desc->data_size += len; buf->buf_length += len; return tail; } /** * @brief strip data from head * * @param adf_nbuf * @param len (how much data to rip) * * @return new data pointer */ a_uint8_t * __adf_nbuf_pull_head(__adf_nbuf_t buf, adf_os_size_t len) { a_uint8_t *ptr = NULL; VDESC *desc = buf->desc_list; desc->data_offset += len; desc->data_size -= len; buf->buf_length -= len; ptr = desc->buf_addr + desc->data_offset; return ptr; } /** * @brief strip data from tail, priv safe * * @param buf * @param len (how much to strip down) * */ void __adf_nbuf_trim_tail(__adf_nbuf_t buf, adf_os_size_t len) { VDESC *last_desc = __adf_nbuf_last(buf); adf_os_assert(buf != NULL); last_desc->data_size -= len; buf->buf_length -= len; //adf_os_assert(0); //0820 } /** * @brief Copy assumes that we create a writeable copy of the * nbuf which is equivalent in FreeBSD as duping the * mbuf. * * @param src * * @return struct mbuf * (newly allocated buffer) */ __adf_nbuf_t __adf_nbuf_copy(__adf_nbuf_t src) { __adf_nbuf_t buf = NULL; adf_os_assert(src != NULL); return buf; } /** * @brief make the writable copy of the nbuf * * @param adf_nbuf * * @return new nbuf */ __adf_nbuf_t __adf_nbuf_unshare(__adf_nbuf_t src) { __adf_nbuf_t buf = NULL; adf_os_assert(src != NULL); return buf; } /** * @brief return the frag data & len, where frag no. is * specified by the index * * @param[in] buf * @param[out] sg (scatter/gather list of all the frags) * */ void __adf_nbuf_frag_info(__adf_nbuf_t buf, adf_os_sglist_t *sg) { VDESC *desc = buf->desc_list; int count = 0; while( desc != NULL ) { sg->sg_segs[count].vaddr = desc->buf_addr + desc->data_offset; sg->sg_segs[count].len = desc->data_size; count++; desc = desc->next_desc; } sg->nsegs = count; } /** * @brief retrieve the priv space pointer from nbuf * * @param buf (nbuf to attach the priv space) * * @return uint8_t* ( pointer to the data ) */ a_uint8_t * __adf_nbuf_get_priv(__adf_nbuf_t buf) { adf_os_assert(buf != NULL); return buf->ctx; } /** * * @brief append the nbuf to the queue * * @param adf_qhead * @param adf_nbuf * */ void __adf_nbuf_queue_add(__adf_nbuf_qhead_t *qhead, __adf_nbuf_t buf) { qhead->qlen++; buf->next_buf = NULL; if (qhead->head == NULL) { qhead->head = buf; } else { qhead->tail->next_buf = buf; } qhead->tail = buf; } /** * @brief dequeue an nbuf * * @param adf_qhead * * @return the nbuf */ __adf_nbuf_t __adf_nbuf_queue_remove(__adf_nbuf_qhead_t *qhead) { __adf_nbuf_t b0 = NULL; if (qhead->head) { qhead->qlen--; b0 = qhead->head; if ( qhead->head == qhead->tail ) { qhead->head = NULL; qhead->tail = NULL; } else { qhead->head = qhead->head->next_buf; } b0->next_buf = NULL; } return b0; } /** * ****************DMA Routines Start Here***************** */ /** * @brief creates a streaming mapping (takes a pre allocated * global tag for 4K mbuf sizes) * * @param hdl * @param max_sz * @param dmap * * @return a_status_t */ a_status_t __adf_nbuf_dmamap_create(__adf_os_device_t osdev, __adf_os_dma_map_t *dmap) { a_status_t retval = A_STATUS_OK; (*dmap) = A_ALLOCRAM(sizeof(struct __adf_dma_map)); if(*dmap == NULL) return A_STATUS_ENOMEM; (*dmap)->buf = NULL; return retval; } a_status_t __adf_nbuf_map(__adf_os_device_t osdev, __adf_os_dma_map_t bmap, __adf_nbuf_t buf, adf_os_dma_dir_t dir) { bmap->buf = buf; return A_STATUS_OK; } void __adf_nbuf_unmap(__adf_os_device_t osdev, __adf_os_dma_map_t bmap, adf_os_dma_dir_t dir) { bmap->buf = NULL; return; } void __adf_nbuf_dmamap_destroy(__adf_os_device_t osdev, __adf_os_dma_map_t dmap) { //dmap->buf = NULL; // Should not be called in FW! //return A_STATUS_OK; } /** * @brief return the dma map info * * @param[in] bmap * @param[out] sg (map_info ptr) */ void __adf_nbuf_dmamap_info(__adf_os_dma_map_t bmap, adf_os_dmamap_info_t *sg) { VDESC *desc = bmap->buf->desc_list; int count = 0; while( desc != NULL ) { sg->dma_segs[count].paddr = (adf_os_dma_addr_t)(desc->buf_addr + desc->data_offset); sg->dma_segs[count].len = desc->data_size; count++; desc = desc->next_desc; } sg->nsegs = count; } /** * **************************Misc routines*************** */ /** * @brief sets the cksum type & value for nbuf * XXX: not fully implemented * * @param buf * @param cksum */ void __adf_nbuf_set_rx_cksum(__adf_nbuf_t buf, adf_nbuf_rx_cksum_t *cksum) { } a_status_t __adf_nbuf_get_vlan_info(adf_net_handle_t hdl, __adf_nbuf_t buf, adf_net_vlanhdr_t *vlan) { return A_STATUS_OK; } __adf_nbuf_t __adf_nbuf_create_frm_frag(__adf_nbuf_queue_t *qhead) { VBUF *buf_tmp, *buf_head = NULL; VDESC *vdesc_prev = NULL, *vdesc_tmp = NULL; a_uint32_t cnt = 0, len = __adf_nbuf_queue_len(qhead); a_uint16_t total_len = 0; buf_head = VBUF_alloc_vbuf(); buf_tmp = __adf_nbuf_queue_first(qhead); __adf_os_assert(buf_head); __adf_os_assert(buf_tmp); buf_head->desc_list = buf_tmp->desc_list; while ((buf_tmp = __adf_nbuf_queue_remove(qhead)) != NULL) { cnt++; //adf_os_print("merge buf: %x\n", buf_tmp->desc_list->buf_addr + buf_tmp->desc_list->data_offset); total_len += buf_tmp->buf_length; if (vdesc_prev) { /* link "the last VDESC of previous VBUF" to "the 1st VDESC of this VBUF" */ vdesc_prev->next_desc = buf_tmp->desc_list; } /* traverse VDESC list in this VBUF to find out the last VDESC */ vdesc_tmp = buf_tmp->desc_list; while (vdesc_tmp->next_desc) { vdesc_tmp = vdesc_tmp->next_desc; } vdesc_prev = vdesc_tmp; /* return VBUF to the pool */ buf_tmp->desc_list = NULL; buf_tmp->buf_length = 0; VBUF_free_vbuf(buf_tmp); } if (cnt != len) { //adf_os_print("cnt: %x, len: %x, __adf_nbuf_queue_len: %x\n", cnt, len, // __adf_nbuf_queue_len(qhead)); adf_os_assert(0); } //__adf_os_assert(cnt == len); buf_head->buf_length = total_len; return buf_head; } void __adf_nbuf_split_to_frag(__adf_nbuf_t buf, __adf_nbuf_qhead_t *qhead) { VBUF *buf_tmp; VDESC *desc_tmp = NULL; __adf_nbuf_queue_init(qhead); desc_tmp = buf->desc_list; while (desc_tmp /*&& desc_tmp->buf_addr*/) { buf_tmp = VBUF_alloc_vbuf(); __adf_os_assert(buf_tmp); //desc_tmp->data_size = 0; buf_tmp->desc_list = desc_tmp; //buf_tmp->buf_length = desc_tmp->buf_size; buf_tmp->buf_length = desc_tmp->data_size; buf_tmp->next_buf = NULL; //adf_os_print("split - buf: %x\n", buf_tmp->desc_list->buf_addr + buf_tmp->desc_list->data_offset); __adf_nbuf_queue_add(qhead, buf_tmp); desc_tmp = desc_tmp->next_desc; buf_tmp->desc_list->next_desc = NULL; } buf->desc_list = NULL; buf->buf_length = 0; VBUF_free_vbuf(buf); } /** * @brief return the last mbuf * * @param m0 * * @return struct mbuf* */ VDESC * __adf_nbuf_last(VBUF *buf) { VDESC *desc = buf->desc_list; //for(; desc->next_desc != NULL; desc = desc->next_desc) // ; while(desc->next_desc != NULL) { desc = desc->next_desc; } return desc; } /** * @brief num bytes in the head * * @param adf_nbuf * * @return num of bytes available */ a_uint32_t __adf_nbuf_headroom(__adf_nbuf_t buf) { return buf->desc_list->data_offset; } /** * @brief num of bytes available in the tail excluding the priv * portion * * @param adf_nbuf * * @return num of bytes */ a_uint32_t __adf_nbuf_tailroom(__adf_nbuf_t buf) { VDESC *last_desc = __adf_nbuf_last(buf); return last_desc->buf_size - last_desc->data_offset - last_desc->data_size; } /** * @brief get the entire packet length * * @param adf_nbuf * * @return total length of packet (sum of all frag lengths) */ a_uint32_t __adf_nbuf_len(__adf_nbuf_t buf) { return buf->buf_length; } /** * @brief Clone the nbuf (will not create writeable copies) * * @param adf_nbuf * * @return Read-only copy of the nbuf (including clusters) */ __adf_nbuf_t __adf_nbuf_clone(__adf_nbuf_t src) { __adf_nbuf_t buf = NULL; return buf; } void __adf_nbuf_cat(__adf_nbuf_t dst, __adf_nbuf_t src) { } /* * @brief check if the mbuf is cloned or not * * @param buf * * @return a_bool_t */ a_bool_t __adf_nbuf_is_cloned(__adf_nbuf_t buf) { return A_FALSE; } /** * @brief This will return the header's addr & m_len */ void __adf_nbuf_peek_header(__adf_nbuf_t buf, a_uint8_t **addr, a_uint32_t *len) { VDESC *desc = buf->desc_list; *addr = desc->buf_addr + desc->data_offset; *len = desc->data_size; } /** * @brief init the queue * @param qhead */ void __adf_nbuf_queue_init(__adf_nbuf_qhead_t *qhead) { qhead->qlen = 0; qhead->head = NULL; qhead->tail = NULL; } /** * @brief return the length of queue * @param adf_qhead * * @return length * */ a_uint32_t __adf_nbuf_queue_len(__adf_nbuf_qhead_t *qhead) { return qhead->qlen; } /** * @brief returns the first guy in the Q * @param qhead * * @return (NULL if the Q is empty) */ __adf_nbuf_t __adf_nbuf_queue_first(__adf_nbuf_queue_t *qhead) { return qhead->head; } /** * @brief return the next packet from packet chain * * @param buf (packet) * * @return (NULL if no packets are there) */ __adf_nbuf_t __adf_nbuf_queue_next(__adf_nbuf_t buf) { return buf->next_buf; } /** * @brief check if the queue is empty or not * * @param qhead * * @return a_bool_t */ a_bool_t __adf_nbuf_is_queue_empty(__adf_nbuf_qhead_t *qhead) { return ((qhead->qlen == 0)); } adf_nbuf_pvt.h000077500000000000000000000147771321570333100331530ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/adf/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * FreeBSD specific prototypes */ #ifndef _ADF_NBUF_PVT_H #define _ADF_NBUF_PVT_H #include //#include #include //#include #define __ADF_NBUF_NULL NULL #define __ADF_NBUF_CTX_BUF typedef VBUF * __adf_nbuf_t; /** * queue head */ typedef struct __adf_nbuf_qhead { VBUF *head; VBUF *tail; a_uint32_t qlen; }__adf_nbuf_qhead_t; typedef __adf_nbuf_qhead_t __adf_nbuf_queue_t; __adf_nbuf_t __adf_nbuf_alloc(adf_os_size_t size, a_uint32_t reserve, a_uint32_t align); void __adf_nbuf_free(__adf_nbuf_t buf); a_uint8_t * __adf_nbuf_push_head(__adf_nbuf_t buf, adf_os_size_t size); a_uint8_t * __adf_nbuf_pull_head(__adf_nbuf_t buf, adf_os_size_t size); a_uint8_t * __adf_nbuf_put_tail(__adf_nbuf_t buf, adf_os_size_t size); void __adf_nbuf_trim_tail(__adf_nbuf_t buf, adf_os_size_t size); __adf_nbuf_t __adf_nbuf_realloc_headroom(__adf_nbuf_t buf, a_uint32_t headroom); __adf_nbuf_t __adf_nbuf_realloc_tailroom(__adf_nbuf_t buf, a_uint32_t tailroom); __adf_nbuf_t __adf_nbuf_expand(__adf_nbuf_t buf, a_uint32_t headroom, a_uint32_t tailroom); __adf_nbuf_t __adf_nbuf_copy(__adf_nbuf_t src); __adf_nbuf_t __adf_nbuf_unshare(__adf_nbuf_t src); void __adf_nbuf_frag_info(__adf_nbuf_t buf, adf_os_sglist_t *sg); a_uint8_t * __adf_nbuf_get_priv(__adf_nbuf_t buf); void __adf_nbuf_queue_add(__adf_nbuf_qhead_t *qhead, __adf_nbuf_t buf); __adf_nbuf_t __adf_nbuf_queue_remove(__adf_nbuf_qhead_t *qhead); a_uint32_t __adf_nbuf_tx_cksum_info(__adf_nbuf_t buf, a_uint8_t **hdr_off, a_uint8_t **where); void __adf_nbuf_set_rx_cksum(__adf_nbuf_t buf, adf_nbuf_rx_cksum_t *cksum); void __adf_nbuf_get_tso_info(__adf_nbuf_t buf, adf_nbuf_tso_t *tso); a_status_t __adf_nbuf_get_vlan_info(adf_net_handle_t hdl, __adf_nbuf_t buf, adf_net_vlanhdr_t *vlan); void __adf_nbuf_dmamap_info(__adf_os_dma_map_t bmap, adf_os_dmamap_info_t *sg); /** * @brief return the last mbuf * * @param m0 * * @return struct mbuf* */ VDESC * __adf_nbuf_last(VBUF *buf); /** * @brief num bytes in the head * * @param adf_nbuf * * @return num of bytes available */ a_uint32_t __adf_nbuf_headroom(__adf_nbuf_t buf); /** * @brief num of bytes available in the tail excluding the priv * portion * * @param adf_nbuf * * @return num of bytes */ a_uint32_t __adf_nbuf_tailroom(__adf_nbuf_t buf); /** * @brief get the entire packet length * * @param adf_nbuf * * @return total length of packet (sum of all frag lengths) */ a_uint32_t __adf_nbuf_len(__adf_nbuf_t buf); /** * @brief Clone the nbuf (will not create writeable copies) * * @param adf_nbuf * * @return Read-only copy of the nbuf (including clusters) */ __adf_nbuf_t __adf_nbuf_clone(__adf_nbuf_t src); void __adf_nbuf_cat(__adf_nbuf_t dst, __adf_nbuf_t src); /* * @brief check if the mbuf is cloned or not * * @param buf * * @return a_bool_t */ a_bool_t __adf_nbuf_is_cloned(__adf_nbuf_t buf); /** * @brief This will return the header's addr & m_len */ void __adf_nbuf_peek_header(__adf_nbuf_t buf, a_uint8_t **addr, a_uint32_t *len); /** * @brief init the queue * @param qhead */ void __adf_nbuf_queue_init(__adf_nbuf_qhead_t *qhead); /** * @brief return the length of queue * @param adf_qhead * * @return length * */ a_uint32_t __adf_nbuf_queue_len(__adf_nbuf_qhead_t *qhead); /** * @brief returns the first guy in the Q * @param qhead * * @return (NULL if the Q is empty) */ __adf_nbuf_t __adf_nbuf_queue_first(__adf_nbuf_queue_t *qhead); /** * @brief return the next packet from packet chain * * @param buf (packet) * * @return (NULL if no packets are there) */ __adf_nbuf_t __adf_nbuf_queue_next(__adf_nbuf_t buf); /** * @brief check if the queue is empty or not * * @param qhead * * @return a_bool_t */ a_bool_t __adf_nbuf_is_queue_empty(__adf_nbuf_qhead_t *qhead); __adf_nbuf_t __adf_nbuf_create_frm_frag(__adf_nbuf_queue_t *head); void __adf_nbuf_split_to_frag(__adf_nbuf_t buf, __adf_nbuf_queue_t *qhead); a_status_t __adf_nbuf_dmamap_create(__adf_os_device_t osdev, __adf_os_dma_map_t *dmap); void __adf_nbuf_dmamap_destroy(__adf_os_device_t osdev, __adf_os_dma_map_t dmap); a_status_t __adf_nbuf_map(__adf_os_device_t osdev, __adf_os_dma_map_t dmap, __adf_nbuf_t buf, adf_os_dma_dir_t dir); void __adf_nbuf_unmap(__adf_os_device_t osdev, __adf_os_dma_map_t dmap, adf_os_dma_dir_t dir); #endif open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/adf/adf_net.c000077500000000000000000000042611321570333100321530ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** * @module_name ADF_NET * @module_desc Magpie Network Shim */ #include /** * Prototypes */ /** * @brief register the driver into the shim * @param[in] drv * * @return a_status_t */ a_status_t __adf_net_register_drv(adf_drv_info_t *drv) { wlan_pci_register_drv(drv); return A_STATUS_OK; } /** * @brief unregister the driver from the shim * @param[in] name */ void __adf_net_unregister_drv(a_uint8_t *name) { // do nothing... } adf_net_pvt.h000077500000000000000000000067561321570333100330050ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/adf/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __ADF_NET_PVT_H #define __ADF_NET_PVT_H #define ADF_NET_MAX_NAME 64 #define ADF_DEF_TX_TIMEOUT 5 /*Seconds I suppose*/ #define __ADF_NET_NULL NULL #define __ADF_PCI_BAR0 0x10 a_status_t __adf_net_register_drv(adf_drv_info_t *drv); void __adf_net_unregister_drv(a_uint8_t *name); typedef struct __adf_net_mod { int dummy; }__adf_net_mod_t; typedef struct __adf_softc { int dummy; }__adf_softc_t; static inline a_bool_t __adf_net_carrier_ok(adf_net_handle_t hdl) { return 1; } static inline void __adf_net_carrier_off(adf_net_handle_t hdl) { } static inline void __adf_net_carrier_on(adf_net_handle_t hdl) { } static inline void __adf_net_start_queue(adf_net_handle_t hdl) { } static inline void __adf_net_stop_queue(adf_net_handle_t hdl) { } static inline void __adf_net_wake_queue(adf_net_handle_t hdl) { } static inline a_bool_t __adf_net_queue_stopped(adf_net_handle_t hdl) { return 1; } static inline a_bool_t __adf_net_is_running(adf_net_handle_t hdl) { return 1; } static inline a_bool_t __adf_net_is_up(adf_net_handle_t hdl) { return 1; } static inline adf_net_handle_t __adf_net_dev_create(adf_drv_handle_t hdl, adf_dev_sw_t *op, adf_net_dev_info_t *info) { return NULL; } static inline adf_net_handle_t __adf_net_vdev_create(adf_net_handle_t dev_hdl, adf_drv_handle_t hdl, adf_vdev_sw_t *op, adf_net_dev_info_t *info) { return NULL; } static inline const a_uint8_t * __adf_net_ifname(adf_net_handle_t hdl) { return NULL; } static inline adf_os_handle_t __adf_net_dev_to_os(__adf_os_device_t osdev) { return NULL; } static inline adf_os_handle_t __adf_net_hdl_to_os(adf_net_handle_t hdl) { return NULL; } #endif adf_os_atomic_pvt.h000077500000000000000000000047041321570333100341630ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/adf/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __ADF_OS_ATOMIC_PVT_H #define __ADF_OS_ATOMIC_PVT_H typedef a_uint32_t __adf_os_atomic_t; /** * @brief This initiallizes the varriable to zero * * @param __adf_os_atomic_t (int pointer) * */ static inline void __adf_os_atomic_init(__adf_os_atomic_t *v) { //atomic_store_rel_int(v,0); } static inline a_uint32_t __adf_os_atomic_read(__adf_os_atomic_t *v) { //return (atomic_load_acq_int(v)); return *v; } static inline void __adf_os_atomic_inc(__adf_os_atomic_t *v) { //atomic_add_int(v,1); (*v)++; } static inline void __adf_os_atomic_dec(__adf_os_atomic_t *v) { //atomic_subtract_int(v,1); (*v)--; } /* static inline void __adf_os_atomic_write(__adf_os_atomic_t *v,a_uint32_t p) { atomic_store_rel_int(v,(int)p); } */ #endif adf_os_defer_pvt.c000077500000000000000000000036051321570333100337660ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/adf/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "adf_os_defer_pvt.h" void __adf_os_defer_func(void *arg, int pending) { __adf_os_defer_ctx_t *ctx = (__adf_os_defer_ctx_t *)arg; ctx->caller_fn(ctx->caller_arg); } adf_os_defer_pvt.h000077500000000000000000000075701321570333100340000ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/adf/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __ADF_OS_DEFER_PVT_H #define __ADF_OS_DEFER_PVT_H #include #include #include "Magpie_api.h" /* * Because the real function taked an extra int :( */ typedef struct { adf_os_defer_fn_t caller_fn; void *caller_arg; }__adf_os_defer_ctx_t; /* * wrapper around the real task func */ typedef struct { //struct task tsk; __adf_os_defer_ctx_t ctx; }__adf_os_defer_t; //typedef __adf_os_defer_t __adf_os_bh_t; typedef A_tasklet_t __adf_os_bh_t; typedef __adf_os_defer_t __adf_os_work_t; /* * wrapper function */ extern void __adf_os_defer_func(void *arg, int pending); /** * @brief initiallize the defer function (work or bh) * * @param defer * @param func * @param arg */ static inline void __adf_os_init_defer(__adf_os_defer_t *defer, adf_os_defer_fn_t func, void *arg) { defer->ctx.caller_fn = func; defer->ctx.caller_arg = arg; //TASK_INIT(&defer->tsk, 0, __adf_os_defer_func, &defer->ctx); } static inline void __adf_os_init_work(adf_os_handle_t hdl, __adf_os_work_t *work, adf_os_defer_fn_t func, void *arg) { __adf_os_init_defer(work, func, arg); } static inline void __adf_os_init_bh(adf_os_handle_t hdl, __adf_os_bh_t *bh, adf_os_defer_fn_t func, void *arg) { //__adf_os_init_defer(bh, func, arg); A_TASKLET_INIT_TASK(func, arg, bh); } static inline void __adf_os_sched_work(adf_os_handle_t hdl, __adf_os_work_t * work) { //taskqueue_enqueue(taskqueue_thread, &work->tsk); } static inline void __adf_os_disable_work(adf_os_handle_t hdl, __adf_os_work_t * work) { //taskqueue_drain(taskqueue_thread, &work->tsk); } static inline void __adf_os_sched_bh(adf_os_handle_t hdl, __adf_os_bh_t * bh) { A_TASKLET_SCHEDULE(bh); } static inline void __adf_os_disable_bh(adf_os_handle_t hdl, __adf_os_bh_t * bh) { A_TASKLET_DISABLE(bh); } #endif open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/adf/adf_os_dma.c000077500000000000000000000052651321570333100326340ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include "Magpie_api.h" #include "cmnos_api.h" #if 0 void __adf_os_dma_load(void *arg, bus_dma_segment_t *dseg, int nseg, int error) { if (error) return; adf_os_assert(nseg == 1); ((bus_dma_segment_t *)arg)[0].ds_addr = dseg[0].ds_addr; ((bus_dma_segment_t *)arg)[0].ds_len = dseg[0].ds_len; } #endif /** * @brief Allocates a DMA region, uses the tag elem to store the * tag value which constant for all the mappings done * through this API. * * @param osdev * @param size * @param coherent * @param dmap * * @return void* (Virtual address) */ inline void* __adf_os_dmamem_alloc(__adf_os_device_t osdev, adf_os_size_t size, a_bool_t coherent, __adf_os_dma_map_t *dmap) { (*dmap) = A_ALLOCRAM(sizeof(struct __adf_dma_map)); if((*dmap) == NULL){ goto fail_malloc; } (*dmap)->ds_addr = A_ALLOCRAM(size); (*dmap)->ds_len = size; return (*dmap)->ds_addr; fail_malloc: return NULL; } adf_os_dma_pvt.h000077500000000000000000000052221321570333100334440ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/adf/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __ADF_NBUF_DMA_PVT_H #define __ADF_NBUF_DMA_PVT_H #include #include inline void* __adf_os_dmamem_alloc(__adf_os_device_t osdev, adf_os_size_t size, a_bool_t coherent, __adf_os_dma_map_t *dmap); /* * Free a previously mapped DMA buffer * Direction doesnt matter, since this API is called at closing time. */ static inline void __adf_os_dmamem_free(adf_os_device_t osdev, __adf_os_size_t size, a_bool_t coherent, void *vaddr, __adf_os_dma_map_t dmap) { } //#define __adf_os_dmamem_map2addr(_dmap) ((_dmap)->seg[0].ds_addr) #define __adf_os_dmamem_map2addr(_dmap) ((adf_os_dma_addr_t)(_dmap)->ds_addr) static inline void __adf_os_dmamem_cache_sync(__adf_os_device_t osdev, __adf_os_dma_map_t dmap, adf_os_cache_sync_t sync) { } static inline adf_os_size_t __adf_os_cache_line_size(void) { /** * Todo */ return 0; } #endif adf_os_io_pvt.h000077500000000000000000000051701321570333100333140ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/adf/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _ADF_OS_IO_PVT_H #define _ADF_OS_IO_PVT_H #include #define __bswap16(x) \ ((((x) & 0xff00) >> 8) | \ (((x) & 0x00ff) << 8)) #define __bswap32(x) \ ((((x) & 0xff000000) >> 24) | \ (((x) & 0x00ff0000) >> 8) | \ (((x) & 0x0000ff00) << 8) | \ (((x) & 0x000000ff) << 24)) #define __adf_os_ntohs(x) x #define __adf_os_ntohl(x) x #define __adf_os_htons(x) x #define __adf_os_htonl(x) x #define __adf_os_cpu_to_le16(x) __bswap16(x) #endif adf_os_irq_pvt.c000077500000000000000000000045131321570333100334730ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/adf/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include int __adf_os_setup_intr(__adf_os_device_t osdev, adf_os_drv_intr fn); void __adf_os_free_intr(__adf_os_device_t osdev); extern adf_os_drv_intr g_wlan_intr; /** * @brief setup the Interrupt handler for the driver * @param[in] dev * @param[in] sc * * @return int */ int __adf_os_setup_intr(__adf_os_device_t osdev, adf_os_drv_intr fn) { g_wlan_intr = fn; return 0; } /** * @brief deregister from the kernel the interrupt handler * @param[in] dev * @param[in] sc */ void __adf_os_free_intr(__adf_os_device_t osdev) { g_wlan_intr = NULL; } adf_os_irq_pvt.h000077500000000000000000000036211321570333100334770ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/adf/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __ADF_OS_IRQ_PVT_H #define __ADF_OS_IRQ_PVT_H int __adf_os_setup_intr(__adf_os_device_t osdev, adf_os_drv_intr fn); void __adf_os_free_intr(__adf_os_device_t osdev); #endif adf_os_lock_pvt.h000077500000000000000000000055471321570333100336450ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/adf/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _ADF_OS_LOCK_PVT_H #define _ADF_OS_LOCK_PVT_H typedef int __adf_os_spinlock_t; typedef int __adf_os_mutex_t; static inline void __adf_os_init_mutex(__adf_os_mutex_t *mtx) { } static inline int __adf_os_mutex_acquire(__adf_os_mutex_t *mtx) { return 0; } static inline void __adf_os_mutex_release(__adf_os_mutex_t *mtx) { } static inline void __adf_os_spinlock_init(__adf_os_spinlock_t *lock) { } /* * Synchronous versions - only for OS' that have interrupt disable */ static inline void __adf_os_spin_lock_irq(__adf_os_spinlock_t *lock, a_uint32_t *flags) { //mtx_lock_spin(lock); (*flags)=0; } static inline void __adf_os_spin_unlock_irq(__adf_os_spinlock_t *lock, a_uint32_t *flags) { //mtx_unlock_spin(lock); } static inline void __adf_os_spin_lock_bh(__adf_os_spinlock_t *lock) { //mtx_lock_spin(lock); } static inline void __adf_os_spin_unlock_bh(__adf_os_spinlock_t *lock) { //mtx_unlock_spin(lock); } static inline a_bool_t __adf_os_spinlock_irq_exec(adf_os_handle_t hdl, __adf_os_spinlock_t *lock, adf_os_irqlocked_func_t func, void *arg) { return 0; } #endif adf_os_mem_pvt.h000077500000000000000000000053671321570333100334730ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/adf/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef ADF_OS_MEM_PVT_H #define ADF_OS_MEM_PVT_H #include "cmnos_api.h" #include "Magpie_api.h" static inline void * __adf_os_mem_alloc(adf_os_size_t size) { // return (malloc(size,M_DEVBUF,M_DONTWAIT | M_ZERO)); return A_ALLOCRAM(size); } static inline void __adf_os_mem_free(void *buf) { //Should not be called in FW! //free(buf,M_DEVBUF); } /* move a memory buffer */ static inline void __adf_os_mem_copy(void *dst, const void *src, adf_os_size_t size) { A_MEMCPY(dst,src,size); } /* set a memory buffer */ static inline void __adf_os_mem_set(void *buf, a_uint8_t b, adf_os_size_t size) { A_MEMSET(buf, b, size); } static inline void __adf_os_mem_move(void *dst, void *src, adf_os_size_t size) { A_MEMMOVE(dst, src, size); } /* zero a memory buffer */ static inline void __adf_os_mem_zero(void *buf, adf_os_size_t size) { A_MEMZERO(buf,size); } /* compare two memory buffers */ static inline int __adf_os_mem_cmp(void *buf1, void *buf2, adf_os_size_t size) { return (A_MEMCMP (buf1, buf2, size) == 0) ? 0 : 1; } #endif adf_os_module_pvt.h000077500000000000000000000044411321570333100341720ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/adf/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __ADF_OS_MODULE_PVT_H #define __ADF_OS_MODULE_PVT_H //#include //#include //int __adf_os_virt_mod(struct module *mod, int event, void *arg); /** * MACRO's for initiallization */ /** * init module macro */ #define __adf_os_virt_module_init(_fn) /** * @brief generic driver /module init function * * @param mod (module data) * @param event (LOAD or UNLOAD) * @param arg (any extra argument needed if * * @return int */ /** * exit module macro */ #define __adf_os_virt_module_exit(_fn) #define __adf_os_module_dep(_name, _dep) #endif adf_os_pci_pvt.h000077500000000000000000000066601321570333100334650ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/adf/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __ADF_OS_PCI_PVT_H #define __ADF_OS_PCI_PVT_H #include //extern A_PCI_INIT_FUNC g_pci_init_func; /** * init module macro */ #define __adf_os_pci_module_init(_fn) A_PCI_INIT_FUNC g_pci_init_func = _fn; /** * exit module macro */ #define __adf_os_pci_module_exit(_fn) /** * initiallize the PCI driver structure * Instance name will be _pci_info */ #define __adf_os_pci_set_drv_info(_name, _pci_ids, _attach, _detach, _suspend, _resume) \ { \ (_attach), \ (_detach), \ (_suspend), \ (_resume), \ ADF_OS_BUS_TYPE_PCI, \ { (_pci_ids)}, \ #_name \ }; /** * XXX: pci functions undone * @param osdev * @param offset * @param val * * @return int */ static inline int __adf_os_pci_config_read8(adf_os_device_t osdev, int offset, a_uint8_t *val) { (*val) = wlan_pci_config_read(offset, 1); return 0; /** * XXX:how do we know the read succeded */ } static inline int __adf_os_pci_config_write8(adf_os_device_t osdev, int offset, a_uint8_t val) { wlan_pci_config_write(offset, val, 1); return 0; } static inline int __adf_os_pci_config_read16(adf_os_device_t osdev, int offset, a_uint16_t *val) { (*val) = wlan_pci_config_read(offset, 2); return 0; } static inline int __adf_os_pci_config_write16(adf_os_device_t osdev, int offset, a_uint16_t val) { wlan_pci_config_write(offset, val, 2); return 0; } static inline int __adf_os_pci_config_read32(adf_os_device_t osdev, int offset, a_uint32_t *val) { (*val) = wlan_pci_config_read(offset, 4); return 0; } static inline int __adf_os_pci_config_write32(adf_os_device_t osdev, int offset, a_uint32_t val) { wlan_pci_config_write(offset, val, 4); return 0; } #endif adf_os_time_pvt.h000077500000000000000000000050741321570333100336460ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/adf/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _ADF_OS_TIME_PVT_H #define _ADF_OS_TIME_PVT_H #include #include "Magpie_api.h" /** * @brief this code is modified version of tvtohz(9) which * returns signed int which we don't require, hence we * got rid of the type casting thing * * @return unsigned long */ static inline unsigned long __adf_os_ticks(void) { return MSEC_TO_TICK(A_MILLISECONDS()); } static inline a_uint32_t __adf_os_ticks_to_msecs(unsigned long ticks) { return TICK_TO_MSEC(ticks); } static inline unsigned long __adf_os_msecs_to_ticks(a_uint32_t msecs) { return MSEC_TO_TICK(msecs); } static inline unsigned long __adf_os_getuptime(void) { return MSEC_TO_TICK(A_MILLISECONDS());; } static inline void __adf_os_udelay(int usecs) { A_DELAY_USECS(usecs); } static inline void __adf_os_mdelay(int msecs) { A_DELAY_USECS(msecs*1000); } #endif adf_os_timer.c000077500000000000000000000036401321570333100331270ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/adf/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include void __adf_os_timer_func(A_HANDLE timer_handle, void *arg) { __adf_os_timer_t *timer = (__adf_os_timer_t *)timer_handle; timer->timer_func(arg); } adf_os_timer_pvt.h000077500000000000000000000064211321570333100340250ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/adf/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _ADF_OS_TIMER_PVT_H #define _ADF_OS_TIMER_PVT_H #include #include "Magpie_api.h" typedef struct { A_timer_t *magpie_timer; adf_os_timer_func_t timer_func; }__adf_os_timer_t; //typedef A_timer_t __adf_os_timer_t; void __adf_os_timer_func(A_HANDLE timer_handle, void *arg); /* * Initialize a timer */ static inline void __adf_os_timer_init(adf_os_handle_t hdl, __adf_os_timer_t *timer, adf_os_timer_func_t func, void *arg) { timer->timer_func = func; A_INIT_TIMER(timer->magpie_timer, __adf_os_timer_func, arg); } /* * start a timer */ static inline void __adf_os_timer_start(__adf_os_timer_t *timer, int msec) { A_TIMEOUT_MS(timer->magpie_timer, msec); } /* * Cancel a timer * * Return: TRUE if timer was cancelled and deactived, * FALSE if timer was cancelled but already got fired. */ static inline a_bool_t __adf_os_timer_cancel(__adf_os_timer_t *timer) { A_UNTIMEOUT(timer->magpie_timer); return A_TRUE; } /* * XXX Synchronously canel a timer * * Return: TRUE if timer was cancelled and deactived, * FALSE if timer was cancelled but already got fired. * * Synchronization Rules: * 1. caller must make sure timer function will not use * adf_os_set_timer to add iteself again. * 2. caller must not hold any lock that timer function * is likely to hold as well. * 3. It can't be called from interrupt context. */ static inline a_bool_t __adf_os_timer_sync_cancel(__adf_os_timer_t *timer) { // @TODO: IS OK?? A_UNTIMEOUT(timer->magpie_timer); return A_TRUE; } #endif adf_os_types_pvt.h000077500000000000000000000116271321570333100340550ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/adf/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __ADF_OS_TYPES_PVT_H #define __ADF_OS_TYPES_PVT_H #include #include //#include "cmnos_api.h" //#include "Magpie_api.h" #include #define __ADF_OS_MAX_SCATTER 1 #define __adf_os_packed __attribute__((__packed__)) #define __ADF_OS_NAME_SIZE 10 /* * Private definitions of general data types */ /** * Endian-ness */ #undef ADF_LITTLE_ENDIAN_MACHINE #undef ADF_BIG_ENDIAN_MACHINE //#if (_BYTE_ORDER == _LITTLE_ENDIAN) #ifdef LITTLE_ENDIAN #define ADF_LITTLE_ENDIAN_MACHINE //#elif (_BYTE_ORDER == _BIG_ENDIAN) #elif BIG_ENDIAN #define ADF_BIG_ENDIAN_MACHINE #endif /** * CACHE-SYNC (DMA) */ #define __ADF_SYNC_PREREAD 0 #define __ADF_SYNC_POSTREAD 1 #define __ADF_SYNC_PREWRITE 2 #define __ADF_SYNC_POSTWRITE 3 #define __ADF_OS_DMA_TO_DEVICE 0 #define __ADF_OS_DMA_FROM_DEVICE 1 struct __adf_softc; enum __adf_net_wireless_evcode{ __ADF_IEEE80211_ASSOC = 100, __ADF_IEEE80211_REASSOC = 101, __ADF_IEEE80211_DISASSOC = 102, __ADF_IEEE80211_JOIN = 103, __ADF_IEEE80211_LEAVE = 104, __ADF_IEEE80211_SCAN = 105, __ADF_IEEE80211_REPLAY = 106, __ADF_IEEE80211_MICHAEL = 107, __ADF_IEEE80211_REJOIN = 108, __ADF_CUSTOM_PUSH_BUTTON = 109, }; /* generic data types */ struct __adf_device { int dummy; }; typedef struct __adf_device *__adf_os_device_t; struct __adf_dma_map { VBUF *buf; A_UINT32 *ds_addr; A_UINT16 ds_len; }; typedef struct __adf_dma_map *__adf_os_dma_map_t; typedef A_UINT32 __adf_os_dma_addr_t; typedef A_UINT32 __adf_os_dma_size_t; typedef unsigned int __adf_os_size_t; typedef int __adf_os_off_t; #define __adf_os_iomem_t #if 0 typedef int __a_uint8_t; typedef int __a_int8_t; typedef int __a_uint16_t; typedef int __a_int16_t; typedef int __a_uint32_t; typedef int __a_int32_t; typedef int __a_uint64_t; typedef int __a_int64_t; #else typedef A_UINT8 __a_uint8_t; typedef A_INT8 __a_int8_t; typedef A_UINT16 __a_uint16_t; typedef A_INT16 __a_int16_t; typedef A_UINT32 __a_uint32_t; typedef A_INT32 __a_int32_t; typedef A_UINT64 __a_uint64_t; typedef A_INT64 __a_int64_t; typedef A_UINT32 u_int32_t; typedef A_UINT16 u_int16_t; typedef A_UINT8 u_int8_t; typedef unsigned int u_int; typedef unsigned long u_long; //typedef __adf_os_size_t size_t; typedef A_UINT64 u_int64_t; #endif //extern void my_printf(struct ath_hal *ah, const char* fmt, ...); //#define __adf_os_print my_printf #define __adf_os_print A_PRINTF #if 1 #if defined(__XCC__) #include "stdarg.h" #define __va_list __gnuc_va_list #endif #endif /* For compiling WLAN drivers */ #define IFNAMSIZ 10 #define ENXIO -1 #define ENOMEM -1 #define EIO -1 #define caddr_t int #define ENODEV -1 #define EOPNOTSUPP -1 #define KASSERT(exp, msg) #if 0 #ifndef __packed #define __packed __attribute__((__packed__)) #endif #ifndef roundup #define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ #endif #endif #endif adf_os_util_pvt.h000077500000000000000000000065011321570333100336610ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/adf/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __ADF_OS_UTIL_PVT_H #define __ADF_OS_UTIL_PVT_H #include #define __adf_os_unlikely(_expr) #define __adf_os_likely(_expr) /** * @brief memory barriers. */ #define __adf_os_wmb() oops no implementation... #define __adf_os_rmb() oops no implementation... #define __adf_os_mb() oops no implementation... #define __adf_os_min(_a, _b) ((_a < _b) ? _a : _b) #define __adf_os_max(_a, _b) ((_a > _b) ? _a : _b) #ifdef _DEBUG_BUILD_ #define __adf_os_assert(expr) do {\ if(!(expr)) { \ adf_os_print("Assertion failed! %s:%s %s:%d\n", #expr, __FUNCTION__, __FILE__, __LINE__); \ while(1){} \ \ }\ }while(0); #else #if defined(PROJECT_MAGPIE) #define __adf_os_assert(expr) do { \ if(!(expr)) { \ adf_os_print("Assertion failed! %s\n", __FUNCTION__); \ (*((volatile uint32_t *)(0x12345678))); \ } \ }while(0); #else #define __adf_os_assert(expr) do { \ if(!(expr)) { \ while(1){} \ } \ }while(0); #endif #endif #ifndef inline #define inline #endif static void inline __adf_os_get_rand(adf_os_handle_t hdl,__a_uint8_t *ptr, __a_uint32_t len) { #if 0 u_int8_t *dp = ptr; u_int32_t v; size_t nb; while (len > 0) { v = arc4random(); nb = len > sizeof(u_int32_t) ? sizeof(u_int32_t) : len; bcopy(&v, dp, len > sizeof(u_int32_t) ? sizeof(u_int32_t) : len); dp += sizeof(u_int32_t); len -= nb; } #endif } #endif /*_ADF_OS_UTIL_PVT_H*/ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/buf_pool/000077500000000000000000000000001321570333100314545ustar00rootroot00000000000000buf_pool_api.h000077500000000000000000000055161321570333100342160ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/buf_pool/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * @File: buf_pool_api.h * * @Abstract: BUF Pool api * * @Notes: */ #ifndef _BUF_POOL_API_H #define _BUF_POOL_API_H #include /* endpoint defines */ typedef enum { POOL_ID_HTC_CONTROL = 0, POOL_ID_WMI_SVC_CMD_REPLY = 1, POOL_ID_WMI_SVC_EVENT = 2, POOL_ID_WLAN_RX_BUF = 3, POOL_ID_MAX = 10 } BUF_POOL_ID; typedef void* pool_handle_t; /* hardware API table structure (API descriptions below) */ struct buf_pool_api { pool_handle_t (*_init)(adf_os_handle_t handle); void (*_shutdown)(pool_handle_t handle); void (*_create_pool)(pool_handle_t handle, BUF_POOL_ID poolId, int nItems, int nSize); adf_nbuf_t (*_alloc_buf)(pool_handle_t handle, BUF_POOL_ID poolId, int reserve); adf_nbuf_t (*_alloc_buf_align)(pool_handle_t handle, BUF_POOL_ID poolId, int reserve, int align); void (*_free_buf)(pool_handle_t handle, BUF_POOL_ID poolId, adf_nbuf_t buf); /* room to expand this table by another table */ void *pReserved; }; extern void buf_pool_module_install(struct buf_pool_api *apis); #endif /* #ifndef _BUF_POOL_API_H */ buf_pool_static.c000077500000000000000000000120651321570333100347240ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/buf_pool/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * @File: * * @Abstract: Buf pool implementation: static version * * @Notes: */ #include #include #include #include #include #include #include #include "buf_pool_static.h" LOCAL htc_handle_t _buf_pool_static_init(adf_net_handle_t handle); LOCAL void _buf_pool_static_create_pool(pool_handle_t handle, BUF_POOL_ID poolId, int nItems, int nSize); LOCAL adf_nbuf_t _buf_pool_static_alloc_buf(pool_handle_t handle, BUF_POOL_ID poolId, int reserve); LOCAL adf_nbuf_t _buf_pool_static_alloc_buf_align(pool_handle_t handle, BUF_POOL_ID poolId, int reserve, int align); LOCAL void _buf_pool_static_free_buf(pool_handle_t handle, BUF_POOL_ID poolId, adf_nbuf_t buf); LOCAL void _buf_pool_static_shutdown(pool_handle_t handle); BUF_POOL_STATIC_CONTEXT g_poolCtx; void buf_pool_module_install(struct buf_pool_api *pAPIs) { pAPIs->_init = _buf_pool_static_init; pAPIs->_create_pool = _buf_pool_static_create_pool; pAPIs->_alloc_buf = _buf_pool_static_alloc_buf; pAPIs->_alloc_buf_align = _buf_pool_static_alloc_buf_align; pAPIs->_free_buf = _buf_pool_static_free_buf; pAPIs->_shutdown = _buf_pool_static_shutdown; } LOCAL pool_handle_t _buf_pool_static_init(adf_os_handle_t handle) { #if 1 int i; for(i=0; i < POOL_ID_MAX; i++) { g_poolCtx.bufQ[i] = NULL; } return &g_poolCtx; #else BUF_POOL_STATIC_CONTEXT *ctx; //ctx = (BUF_POOL_static_CONTEXT *)A_ALLOCRAM(sizeof(BUF_POOL_static_CONTEXT)); ctx = (BUF_POOL_STATIC_CONTEXT *)adf_os_mem_alloc(sizeof(BUF_POOL_STATIC_CONTEXT)); ctx->NetHandle = handle; return ctx; #endif } LOCAL void _buf_pool_static_shutdown(pool_handle_t handle) { // SHALL NOT BE USED in FW } LOCAL void _buf_pool_static_create_pool(pool_handle_t handle, BUF_POOL_ID poolId, int nItems, int nSize) { int i; VBUF *buf; VDESC *desc; //BUF_POOL_STATIC_CONTEXT *ctx = (BUF_POOL_STATIC_CONTEXT *)handle; for ( i = 0; i < nItems; i++) { buf = VBUF_alloc_vbuf(); desc = VDESC_alloc_vdesc(); desc->buf_addr = (A_UINT8 *)adf_os_mem_alloc(nSize); desc->buf_size = nSize; desc->data_offset = 0; desc->data_size = 0; buf->buf_length = 0; buf->desc_list = desc; if ( g_poolCtx.bufQ[poolId] == NULL ) { g_poolCtx.bufQ[poolId] = buf; } else { buf->next_buf = g_poolCtx.bufQ[poolId]; g_poolCtx.bufQ[poolId] = buf; } } } LOCAL adf_nbuf_t _buf_pool_static_alloc_buf(pool_handle_t handle, BUF_POOL_ID poolId, int reserve) { VBUF *buf; buf = g_poolCtx.bufQ[poolId]; if ( buf != NULL ) { g_poolCtx.bufQ[poolId] = buf->next_buf; buf->next_buf = NULL; buf->desc_list->data_offset = reserve; buf->desc_list->data_size = 0; buf->buf_length = 0; } return buf; } LOCAL adf_nbuf_t _buf_pool_static_alloc_buf_align(pool_handle_t handle, BUF_POOL_ID poolId, int reserve, int align) { return _buf_pool_static_alloc_buf(handle, poolId, reserve); } LOCAL void _buf_pool_static_free_buf(pool_handle_t handle, BUF_POOL_ID poolId, adf_nbuf_t buf) { if ( g_poolCtx.bufQ[poolId] == NULL ) { g_poolCtx.bufQ[poolId] = buf; } else { buf->next_buf = g_poolCtx.bufQ[poolId]; g_poolCtx.bufQ[poolId] = buf; } } buf_pool_static.h000077500000000000000000000040001321570333100347170ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/buf_pool/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * @File: * * @Abstract: * * @Notes: */ #ifndef BUF_POOL_STATIC_H_ #define BUF_POOL_STATIC_H_ typedef struct _BUF_POOL_STATIC_CONTEXT { VBUF *bufQ[POOL_ID_MAX]; // Left a door for extension the structure void *pReserved; } BUF_POOL_STATIC_CONTEXT; #endif /*BUF_POOL_STATIC_H_*/ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/cmnos/000077500000000000000000000000001321570333100307665ustar00rootroot00000000000000clock_api.h000077500000000000000000000044601321570333100330130ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/cmnos/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __CLOCK_API_H__ #define __CLOCK_API_H__ #define TICK_MSEC_RATIO 1 #define TICK_TO_MSEC(tick) ((tick)/TICK_MSEC_RATIO) #define MSEC_TO_TICK(msec) ((msec)* TICK_MSEC_RATIO) struct clock_api { void (* _clock_init)(A_UINT32 ref_clk); void (* _clockregs_init)(void); A_UINT32 (* _uart_frequency)(void); void (* _delay_us)(int); void (* _wlan_band_set)(int); A_UINT32 (* _refclk_speed_get)(void); A_UINT32 (* _milliseconds)(void); void (* _sysclk_change)(void); #if defined(PROJECT_K2) A_UINT32 (* _sysclk_get)(void); #endif void (* _clock_tick)(void); }; #endif /* __CLOCK_API_H__ */ cmnos_api.h000077500000000000000000000504011321570333100330330ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/cmnos/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __CMNOS_API_H__ #define __CMNOS_API_H__ /* * This file contains wrappers to OS operating system functions * that are available in all versions of the operating system. * * Target software must always use these wrappers to access OS * services -- it may not access any OS services directly. */ #include "sys_cfg.h" #include "xtensa/config/core.h" #include "xtensa/hal.h" #include "xtensa/xtruntime.h" /* cmnos interface */ #include "printf_api.h" #include "uart_api.h" #include "dbg_api.h" #include "mem_api.h" #include "misc_api.h" #include "string_api.h" #include "timer_api.h" #include "romp_api.h" #include "allocram_api.h" #include "tasklet_api.h" #include "clock_api.h" #include "intr_api.h" #include "wdt_api.h" #include "eeprom_api.h" #include "usb_api.h" #include #include #if defined(PROJECT_K2) #if SYSTEM_MODULE_SFLASH #include "cmnos/sflash_api.h" #endif #endif #define AR6K_ROM_START 0x004e0000 #define AR6K_ROM_ADDR(byte_offset) (AR6K_ROM_START+(byte_offset)) #define TARG_ROM_ADDRS(byte_offset) AR6K_ROM_ADDR(byte_offset) #define IML_SIGNAL_UNUSED0_ADDR TARG_ROM_ADDRS(0) /* Cannot be used -- aligned */ #define IML_SIGNAL_ASSERT_ADDR TARG_ROM_ADDRS(1) /* Signal an assertion failure */ #define IML_SIGNAL_PRINTF_ADDR TARG_ROM_ADDRS(2) /* Signal a printf request */ #define IML_SIGNAL_UNUSED4_ADDR TARG_ROM_ADDRS(4) /* Cannot be used -- aligned */ #define IML_SIGNAL_UNUSED8_ADDR TARG_ROM_ADDRS(8) /* Cannot be used -- aligned */ #define IML_SIGNAL_UNUSEDC_ADDR TARG_ROM_ADDRS(0xc) /* Cannot be used -- aligned */ #define IML_SIGNAL_MASK 0xfffe000f #define IML_LINENUM_SHIFT 4 #define NOW() xthal_get_ccount() #if defined(__XTENSA__) #define _A_BARRIER asm volatile("memw") #else #define _A_BARRIER #endif #define A_ASSERT( __bool ) \ do { \ if (0 == (__bool)) { \ (void)*((volatile int *)(IML_SIGNAL_ASSERT_ADDR+(__LINE__<<4)));\ _A_BARRIER; \ } \ } while (0) #define A_IML_IS_ASSERT(vaddr) \ (((vaddr) & IML_SIGNAL_MASK) == (IML_SIGNAL_ASSERT_ADDR & IML_SIGNAL_MASK)) #define PRINT_FAILURE_STATE() \ do { \ uint32_t epc1, epc2, epc3, epc4; \ \ asm volatile("rsr %0,%1" : "=r" (epc1) : "n" (EPC_1)); \ asm volatile("rsr %0,%1" : "=r" (epc2) : "n" (EPC_2)); \ asm volatile("rsr %0,%1" : "=r" (epc3) : "n" (EPC_3)); \ asm volatile("rsr %0,%1" : "=r" (epc4) : "n" (EPC_4)); \ \ A_PRINTF("\tepc1=0x%x, epc2=0x%x, epc3=0x%x, epc4=0x%x\n", \ epc1, epc2, epc3, epc4); \ A_PRINTF("0x%08x, 0x%08x, 0x%08x, \n\r", \ DEBUG_SYSTEM_STATE, WATCH_DOG_RESET_COUNTER, \ WATCH_DOG_MAGIC_PATTERN); \ } while(0) //////////////////////////////////////////////////////////////////////////////////// //#define A_CMN(sym) _A_OS_INDIRECTION_TABLE->cmnos.sym #define A_CMN(sym) _A_MAGPIE_INDIRECTION_TABLE->cmnos.sym #if SYSTEM_MODULE_MEM /* Mem interfaces */ #define A_MEMSET(addr, value, size) \ A_CMN(mem._memset((char *)(addr), (int)(value), (int)(size))) #define A_MEMZERO(addr, size) \ A_CMN(mem._memset((char *)(addr), (int)0, (int)(size))) #define A_MEMCPY(dst, src, size) \ A_CMN(mem._memcpy((char *)(dst), (char *)(src), (int)(size))) #define A_MEMMOVE(dst, src, size) \ A_CMN(mem._memmove((char *)(dst), (char *)(src), (int)(size))) #define A_MEMCMP(p1, p2, nbytes) \ A_CMN(mem._memcmp)((void *)(p1), (void *)(p2), (int)(nbytes)) #else /* Mem interfaces */ #define A_MEMSET(addr, value, size) #define A_MEMZERO(addr, size) #define A_MEMCPY(dst, src, size) #define A_MEMMOVE(dst, src, size) #define A_MEMCMP(p1, p2, nbytes) #endif #if 1 /* String interfaces */ #define A_STRCPY(dst, src) A_CMN(string._strcpy((dst), (src))) #define A_STRNCPY(dst, src, n) A_CMN(string._strncpy((dst), (src), (n))) #define A_STRLEN(str) A_CMN(string._strlen(str)) #define A_STRCMP(str1, str2) A_CMN(string._strcmp((str1), (str2))) #define A_STRNCMP(str1, str2, n) A_CMN(string._strncmp((str1), (str2), (n))) #endif #if SYSTEM_MODULE_PRINT /* Printf support */ #define A_PRINTF_INIT() A_CMN(printf._printf_init()) #define A_PRINTF A_CMN(printf._printf) #else #define A_PRINTF_INIT() #define A_PRINTF #endif /* SYSTEM_MODULE_PRINT */ #if SYSTEM_MODULE_UART /* Serial port support */ #define A_UART_INIT() A_CMN(uart._uart_init()) #define A_UART_HWINIT(freq, baud) \ A_CMN(uart._uart_hwinit((freq), (baud))) #define A_UART_ENABLED() (HOST_INTEREST->hi_uart_enable) #define A_PUTS(str) A_CMN(uart._uart_str_out(str)) #define A_PUTC(ch) A_CMN(uart._uart_char_put(ch)) #define A_GETC(pCh) A_CMN(uart._uart_char_get(pCh)) #define A_UART_TASK() A_CMN(uart._uart_task()) #define A_UART_CONFIG(x) A_CMN(uart._uart_config(x)) #else #define A_UART_INIT() #define A_UART_HWINIT(freq, baud) #define A_UART_ENABLED() #define A_PUTS(str) #define A_PUTC(ch) #define A_GETC(pCh) #define A_UART_TASK() #define A_UART_CONFIG(x) #endif #if SYSTEM_MODULE_MISC /* Reset Support */ #define A_RESET() A_CMN(misc._system_reset()) #define A_RESET_MAC() A_CMN(misc._mac_reset()) /* Assertion failure */ #define A_ASSFAIL(regdump) A_CMN(misc._assfail((regdump))) /* Report a failure to the Host */ #define A_REPORT_FAILURE(data, len) \ A_CMN(misc._report_failure_to_host((data), (len))) /* UNALIGNED references are used for ASSERTs */ #define A_MISALIGNED_LOAD_HANDLER(dump) A_CMN(misc._misaligned_load_handler(dump)) /* reture the host interface type */ #define A_IS_HOST_PRESENT() A_CMN(misc._is_host_present()) #define A_KBHIT(delay) A_CMN(misc._kbhit(delay)) #define A_GET_ROM_VER() A_CMN(misc._rom_version_get()) #else /* Reset Support */ #define A_RESET() #define A_RESET_MAC() /* Assertion failure */ #define A_ASSFAIL(regdump) #define A_MISALIGNED_LOAD_HANDLER(dump) /* Report a failure to the Host */ #define A_REPORT_FAILURE(data, len) #define A_IS_HOST_PRESENT() #define A_KBHIT(delay) #define A_GET_ROM_VER() #endif //#if SYSTEM_MODULE_DBG /* debug Support */ //#define A_DBG_INIT() A_CMN(dbg._dbg_init()) //#define A_DBG_TASK() A_CMN(dbg._dbg_task()) //#else //#define A_DBG_INIT() //#define A_DBG_TASK() //#endif #if SYSTEM_MODULE_USB /* debug Support */ #define A_USB_INIT() A_CMN(usb._usb_init()) #define A_USB_ROM_TASK() A_CMN(usb._usb_rom_task()) #define A_USB_FW_TASK() A_CMN(usb._usb_fw_task()) #define A_USB_INIT_PHY() A_CMN(usb._usb_init_phy()) #define A_USB_EP0_SETUP() A_CMN(usb._usb_ep0_setup()) #define A_USB_EP0_TX_DATA() A_CMN(usb._usb_ep0_tx_data()) #define A_USB_EP0_RX_DATA() A_CMN(usb._usb_ep0_rx_data()) #define A_USB_GET_CONFIG() A_CMN(usb._usb_get_configuration()) #define A_USB_SET_CONFIG() A_CMN(usb._usb_set_configuration()) #define A_USB_GET_INTERFACE() A_CMN(usb._usb_get_interface()) #define A_USB_SET_INTERFACE() A_CMN(usb._usb_set_interface()) #define A_USB_STANDARD_CMD() A_CMN(usb._usb_standard_cmd()) #define A_USB_VENDOR_CMD() A_CMN(usb._usb_vendor_cmd()) #define A_USB_POWER_OFF() A_CMN(usb._usb_power_off()) #define A_USB_RESET_FIFO() A_CMN(usb._usb_reset_fifo()) #define A_USB_GEN_WDT() A_CMN(usb._usb_gen_wdt()) #define A_USB_JUMP_BOOT() A_CMN(usb._usb_jump_boot()) #define A_USB_GET_DESCRIPTOR() A_CMN(usb._usb_get_descriptor()) #define A_USB_SET_ADDRESS() A_CMN(usb._usb_set_address()) #define A_USB_SET_FEATURE() A_CMN(usb._usb_set_feature()) #define A_USB_CLEAR_FEATURE() A_CMN(usb._usb_clr_feature()) #define A_USB_GET_STATUS() A_CMN(usb._usb_get_status()) #define A_USB_SETUP_DESC() A_CMN(usb._usb_setup_desc()) #define A_USB_STATUS_IN() A_CMN(usb._usb_status_in()) #define A_USB_REG_OUT() A_CMN(usb._usb_reg_out()) #define A_USB_EP0_TX() A_CMN(usb._usb_ep0_tx()) #define A_USB_EP0_RX() A_CMN(usb._usb_ep0_rx()) #define A_USB_CLK_INIT() A_CMN(usb._usb_clk_init()) #else #define A_USB_INIT() #define A_USB_TASK() #define A_USB_INIT_PHY() #define A_USB_EP0_SETUP() #define A_USB_EP0_TX() #define A_USB_EP0_RX() #define A_USB_GET_CONFIG() #define A_USB_SET_CONFIG() #define A_USB_GET_INTERFACE() #define A_USB_SET_INTERFACE() #define A_USB_STANDARD_CMD() #define A_USB_VENDOR_CMD() #define A_USB_POWER_OFF() #define A_USB_RESET_FIFO() #define A_USB_GEN_WDT() #define A_USB_JUMP_BOOT() #define A_USB_GET_DESCRIPTOR() #define A_USB_SET_ADDRESS() #define A_USB_SET_FEATURE() #define A_USB_CLEAR_FEATURE() #define A_USB_GET_STATUS() #define A_USB_SETUP_DESC() #define A_USB_STATUS_IN() #define A_USB_REG_OUT() #define A_USB_EP0_TX() #define A_USB_EP0_RX() #define A_USB_CLK_INIT() #endif #if SYSTEM_MODULE_INTR /* Low-level interrupt support intended for use by OS modules */ #define A_INTR_GET_INTRENABLE() A_CMN(intr._get_intrenable()) #define A_INTR_SET_INTRENABLE(val) A_CMN(intr._set_intrenable(val)) #define A_INTR_GET_INTRPENDING() A_CMN(intr._get_intrpending()) #define A_INTR_UNBLOCK_ALL_INTRLVL() A_CMN(intr._unblock_all_intrlvl()) /* Interrupt support */ #define A_INTR_INIT() A_CMN(intr._intr_init()) #define A_INTR_DISABLE(pOld) \ do { \ *(pOld) = A_CMN(intr._intr_disable()); \ } while (0) #define A_INTR_RESTORE(old) A_CMN(intr._intr_restore((old))) #define A_INVOKE_ISR(inum) A_CMN(intr._intr_invoke_isr(inum)) #define A_INTR_MASK(inum) A_CMN(intr._intr_mask_inum(inum)) #define A_INTR_UNMASK(inum) A_CMN(intr._intr_unmask_inum(inum)) #define A_ATTACH_ISR(inum, isr, arg) A_CMN(intr._intr_attach_isr(inum, isr, arg)) #else #define A_INTR_INIT() #define A_INTR_DISABLE(pOld) #define A_INTR_RESTORE(old) #define A_INTR_GET_INTRENABLE() #define A_INTR_SET_INTRENABLE(val) #define A_INTR_GET_INTRPENDING() #define A_INTR_UNBLOCK_ALL_INTRLVL() #define A_INVOKE_ISR(inum) #define A_INTR_MASK(inum) #define A_INTR_UNMASK(inum) #define A_ATTACH_ISR(inum, isr, arg) #endif /* Tasklet Support */ #define A_TASKLET_INIT() A_CMN(tasklet._tasklet_init()) #define A_TASKLET_INIT_TASK(f, arg, t) A_CMN(tasklet._tasklet_init_task(f, arg, t)) #define A_TASKLET_DISABLE(t) A_CMN(tasklet._tasklet_disable(t)) #define A_TASKLET_SCHEDULE(t) A_CMN(tasklet._tasklet_schedule(t)) #define A_TASKLET_RUN() A_CMN(tasklet._tasklet_run()) /* RAM Allocation Support */ #if defined(__mips__) #define alloc_arena_start _end #endif #if defined(__XTENSA__) #define alloc_arena_start _end #endif #if SYSTEM_MODULE_CLOCK #define A_CLOCK_INIT(refclk_guess) A_CMN(clock._clock_init(refclk_guess)) #define A_CLOCK_TICK() A_CMN(clock._clock_tick()) #define A_CLOCK_GET_TICK() A_CMN(clock._clock_get_tick()) /* * Get the number of millisecond ticks since the system was started. * Note that this only approximates 1Ms. It's actually 32 ticks of * a 32KHz clock. * * Returns a A_UINT32 value. */ #define A_MILLISECONDS() A_CMN(clock._milliseconds()) /* * Get the frequency of the reference clock, expressed as * an A_refclk_speed_t. */ #define A_REFCLK_SPEED_GET() A_CMN(clock._refclk_speed_get()) /* Spin delay */ #define A_DELAY_USECS(us) A_CMN(clock._delay_us(us)) #define A_UART_FREQUENCY() A_CMN(clock._uart_frequency()) #define A_CLOCKREGS_INIT() A_CMN(clock._clockregs_init()) /* which_band is either A_BAND_24GHZ or A_BAND_5GHZ */ #define A_WLAN_BAND_SET(which_band) \ A_CMN(clock._wlan_band_set(which_band)) /* Called whenever the system clock changes speed */ #define A_SYSCLK_CHANGE() A_CMN(clock._sysclk_change()) #else #define A_CLOCK_INIT(refclk_guess) #define A_CLOCK_TICK() #define A_CLOCK_GET_TICK() #define A_MILLISECONDS() #define A_REFCLK_SPEED_GET() #define A_DELAY_USECS(us) #define A_UART_FREQUENCY() #define A_CLOCKREGS_INIT() #define A_WLAN_BAND_SET(which_band) #define A_SYSCLK_CHANGE() #endif // Timer #define A_INIT_TIMER(pTimer, pFunction, pArg) \ A_CMN(timer._timer_setfn((pTimer), (pFunction), (pArg))) /* Set a (possibly periodic) timer for "period" Milliseconds. */ #define A_TIMEOUT_MS(pTimer, period) \ A_CMN(timer._timer_arm((pTimer), (period))) #define A_UNTIMEOUT(pTimer) \ A_CMN(timer._timer_disarm(pTimer)) #define A_TIMER_RUN() \ A_CMN(timer._timer_run()) #define A_GMAC_BOOT_INIT() \ A_CMN(gmac.gmac_boot_init()) #if SYSTEM_MODULE_ALLOCRAM /* Default size of ALLOCRAM area */ #define ARENA_SZ_DEFAULT 12000 #define A_ALLOCRAM_INIT(arena_start, arena_size) \ do { \ extern unsigned int alloc_arena_start; \ void *astart; \ int asize; \ astart = (arena_start) ? (void *)(arena_start) : &alloc_arena_start; \ asize = (arena_size) ? (arena_size) : (ARENA_SZ_DEFAULT); \ A_CMN(allocram.cmnos_allocram_init((astart), (asize))); \ } while (0) #define A_ALLOCRAM(nbytes) A_CMN(allocram.cmnos_allocram(0, (nbytes))) #define A_ALLOCRAM_DEBUG() A_CMN(allocram.cmnos_allocram_debug()) #else #define A_ALLOCRAM_INIT(arena_start, arena_size) #define A_ALLOCRAM(nbytes) #define A_ALLOCRAM_DEBUG() #endif #if SYSTEM_MODULE_ROM_PATCH #define A_ROMP_INIT() A_CMN(romp._romp_init()) #define A_ROMP_DOWNLOAD(x) A_CMN(romp._romp_download(x)) #define A_ROMP_DECODE(addr) A_CMN(romp._romp_decode(addr)) #define A_ROMP_INSTALL() A_CMN(romp._romp_install()) #else #define A_ROMP_INIT() #define A_ROMP_DOWNLOAD(x) #define A_ROMP_DECODE(addr) #define A_ROMP_INSTALL() #endif #if SYSTEM_MODULE_WDT #define A_WDT_INIT() A_CMN(wdt_timer._wdt_init()) #define A_WDT_ENABLE() A_CMN(wdt_timer._wdt_enable()) #define A_WDT_DISABLE() A_CMN(wdt_timer._wdt_disable()) #define A_WDT_SET(t) A_CMN(wdt_timer._wdt_set(t)) #define A_WDT_TASK() A_CMN(wdt_timer._wdt_task()) #define A_WDT_LASTBOOT() A_CMN(wdt_timer._wdt_last_boot()) #define A_WDT_RESET() A_CMN(wdt_timer._wdt_reset()) #else #define A_WDT_INIT() #define A_WDT_ENABLE() #define A_WDT_DISABLE() #define A_WDT_SET(t) #define A_WDT_TASK() #define A_WDT_LASTBOOT() #define A_WDT_RESET() #endif #if SYSTEM_MODULE_EEPROM #define A_EEP_INIT() A_CMN(eep._eep_init()) #define A_EEP_READ(off, len, buf) A_CMN(eep._eep_read(off, len, buf)) #define A_EEP_WRITE(off, len, buf) A_CMN(eep._eep_write(off, len, buf)) #define A_EEP_IS_EXIST() A_CMN(eep._eep_is_exist()) #else #define A_EEP_INIT() #define A_EEP_READ(off, len, buf) #define A_EEP_WRITE(off, len, buf) #define A_EEP_IS_EXIST() #endif struct _A_os_linkage_check; /* OS-dependent */ typedef struct _A_cmnos_indirection_table { int (* hal_linkage_check)(int sz, struct _A_os_linkage_check *); unsigned int *start_bss; void (* app_start)(void); #if SYSTEM_MODULE_MEM struct mem_api mem; #endif #if SYSTEM_MODULE_MISC struct misc_api misc; #endif #if SYSTEM_MODULE_PRINT struct printf_api printf; #endif #if SYSTEM_MODULE_UART struct uart_api uart; #endif //#if SYSTEM_MODULE_DBG // struct dbg_api dbg; //#endif #if SYSTEM_MODULE_GMAC struct gmac_api gmac; #endif #if SYSTEM_MODULE_USB struct usb_api usb; #endif #if SYSTEM_MODULE_CLOCK struct clock_api clock; #endif #if SYSTEM_MODULE_TIMER struct timer_api timer; #endif #if SYSTEM_MODULE_INTR struct intr_api intr; #endif #if SYSTEM_MODULE_ALLOCRAM struct allocram_api allocram; #endif #if SYSTEM_MODULE_ROM_PATCH struct romp_api romp; #endif #if SYSTEM_MODULE_WDT struct wdt_api wdt_timer; #endif #if SYSTEM_MODULE_EEPROM struct eep_api eep; #endif struct string_api string; struct tasklet_api tasklet; } _A_cmnos_indirection_table_t; /* Module installation for cmnos modules */ #if SYSTEM_MODULE_MEM extern void cmnos_mem_module_install(struct mem_api *); #endif #if SYSTEM_MODULE_MISC extern void cmnos_misc_module_install(struct misc_api *); #endif #if SYSTEM_MODULE_PRINT extern void cmnos_printf_module_install(struct printf_api *); #endif #if SYSTEM_MODULE_UART extern void cmnos_uart_module_install(struct uart_api *); #endif //#if SYSTEM_MODULE_DBG //extern void cmnos_dbg_module_install(struct dbg_api *); //#endif #if SYSTEM_MODULE_USB extern void cmnos_usb_module_install(struct usb_api *); #endif #if SYSTEM_MODULE_INTR extern void cmnos_intr_module_install(struct intr_api *); #endif #if SYSTEM_MODULE_CLOCK extern void cmnos_clock_module_install(struct clock_api *); #endif #if SYSTEM_MODULE_TIMER extern void cmnos_timer_module_install(struct timer_api *); #endif #if SYSTEM_MODULE_ALLOCRAM extern void cmnos_allocram_module_install(struct allocram_api *); #endif #if SYSTEM_MODULE_ROM_PATCH extern void cmnos_romp_module_install(struct romp_api *); #endif #if SYSTEM_MODULE_WDT extern void cmnos_wdt_module_install(struct wdt_api *); #endif #if SYSTEM_MODULE_EEPROM extern void cmnos_eep_module_install(struct eep_api *); #endif extern void cmnos_tasklet_module_install(struct tasklet_api *); extern void cmnos_string_module_install(struct string_api *tbl); #endif /* __CMNOS_API_H__ */ cmnos_sflash.c000077500000000000000000000642351321570333100335470ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/cmnos/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "sys_cfg.h" #include "athos_api.h" #if SYSTEM_MODULE_SFLASH #include "adf_os_io.h" #include "reg_defs.h" #include "sflash_api.h" /******************************************* * Definitions of module internal constant * *******************************************/ /* Definitions of base address and Flash sise -> Project dependent */ #define ZM_SPI_REGISTER_BASE SPI_REG_BASE_ADDRESS /* 0x0005B000 */ #define ZM_SPI_FLASH_BASE SPI_FLASH_BASE /* 0x0F000000 */ #define ZM_SPI_FLASH_MAX_ADDR SPI_FLASH_MAX_ADDR /* 0x0FFFFFFF */ #define ZM_SPI_FLASH_MAX_SIZE SPI_FLASH_MAX_SIZE /* 0x01000000 */ /* * Base address of Clock and Reset Control Registers is 0x00050000 * Offset of Clock Control Register is 0x40 * SPI_SEL (bit 8) : Switch the function of I/O pin 19~22 between GPIO and SPI. * 0 -> act as GPIO5~8; * 1 -> act as SPI pins. */ #define ZM_SPI_CLK_CTRL_ADDR 0x00050040 #define ZM_SPI_SPI_SEL_BIT 0x100 /* Definitions of Serial Flash constants -> According to standard or vendor dependent */ #define ZM_SFLASH_PAGE_SIZE 256 /* Definitions of OP Code -> According to standard or vendor dependent */ #define ZM_SFLASH_OP_READ 0x03 /* Read Data Bytes */ #define ZM_SFLASH_OP_FAST_READ 0x0B /* Read Data Bytes at Higher Speed */ /* * For MXIC, sector erase : Command 0x20, size 4K bytes * block erase : Command 0xD8, size 64K bytes * chip earse : command 0x60 or 0xC7 * For Spansion, sector erase : Command 0x20 or 0xD8, size 64K bytes (For 64 KB sector devices, either command is valid and performs the same function.) * block erase : Command 0xD8, size 256K bytes * chip earse : command 0x60 or 0xC7, Uniform 64 KB Sector Product (For 64 KB sector devices, either command is valid and performs the same function.) * 0xC7, Uniform 256 KB Sector Product */ #define ZM_SFLASH_OP_SE 0x20 /* Sector Erase */ #define ZM_SFLASH_OP_BE 0xD8 /* Block Erase */ #define ZM_SFLASH_OP_CE 0xC7 /* Chip Erase */ #define ZM_SFLASH_OP_PP 0x02 /* Page Program */ #define ZM_SFLASH_OP_RDSR 0x05 /* Read from Status Register */ #define ZM_SFLASH_OP_WRSR 0x01 /* Write to Status Register */ #define ZM_SFLASH_OP_WREN 0x06 /* Write Enable */ #define ZM_SFLASH_OP_WRDI 0x04 /* Write Disable */ #define ZM_SFLASH_OP_RDID 0x9F /* Read Identification */ #define ZM_SFLASH_OP_DP 0xB9 /* Deep Power Down */ #define ZM_SFLASH_OP_RES 0xAB /* Release from Deep Power Down, Release from Deep Power Down and Read Electronic Signature */ /* Definitions of Status Register -> According to standard or vendor dependent */ /* Write in progress bit * 1 = Device Busy. A Write Status Register, program, or erase operation is in progress * 0 = Ready. Device is in standby mode and can accept commands. */ #define ZM_SFLASH_STATUS_REG_WIP (1<<0) /* Write enable latch bit * 1 = Device accepts Write Status Register, program, or erase commands * 0 = Ignores Write Status Register, program, or erase commands */ #define ZM_SFLASH_STATUS_REG_WEL (1<<1) /* Status register write disable bit * 1 = Protects when WP#/ACC is low * 0 = No protection, even when WP#/ACC is low */ #define ZM_SFLASH_STATUS_REG_SRWD (1<<7) /* Definitions of SPI Flash Controller -> SPI Flash Controller dependent */ /* SPI Flash Controller used in K2 project is part of Falcon's "Driver Support Logic" (DSL) block */ /* * Offset Register * ====== ========================================================== * 0x0000 SPI control/status register (SPI_CS) * 0x0004 SPI address/opcode register (SPI_AO) * 0x0008 SPI data register (SPI_D) */ /* * SPI control/status register (SPI_CS) * Access: R/W * Cold reset: (See field descriptions) * Warm reset: (Same as cold reset) * Notes: * * 3:0 - Transmit byte count. Determines the number of bytes * transmitted from Falcon to the SPI device. Values of 1-8 are * valid; other values are illegal. See the 'Notes' section below * for details on how to use this field. Resets to an undefined * value. * 7:4 - Receive byte count. Determines the number of bytes received * from the SPI device into Falcon. Values of 0-8 are valid; * other values are illegal. See the 'Notes' section below for * details on how to use this field. Resets to an undefined * value. * 8 - SPI transaction start. Only writes to this field are * meaningful; reads always return 0. Resets to 0x0. For writes: * * A write of '1' starts the SPI transaction defined by the * transmit byte count, receive byte count, SPI_AO, and SPI_D * registers. * * A write of '0' has no effect * 9 - SPI chip select 1 enable. Resets to 0x0. See bug 12540. * 0 - SP0 is enabled and SP1 is forced inactive. * 1 - SP1 is enabled and SP0 is forced inactive. * 15:10 - Reserved * 16 - Transaction busy indication. Read-only; writes to this bit are * ignored. Resets to 0x0. * 0 - No SPI transaction is ongoing. Software may start a new * SPI transaction by writing to the 'SPI transaction start' * bit within this register. * 1 - An SPI transaction presently is underway. Software must * not try to start a new SPI transaction, nor may software * alter the value of any field of the SPI_CS, SPI_AO, or * SPI_D registers. * 18:17 - Automatically-determined SPI address size. Read-only; writes * to this bit are ignored. Resets to an undefined value, but * then is updated after the autosizing process completes. * 0 - SPI address size was determined to be 16 bits * 1 - SPI address size was determined to be 24 bits * 2 - Reserved * 3 - Automatic SPI address size determination failed. Typical * causes of this result: * * The SPI device is missing * * The SPI device is unprogrammed * * The SPI device is programmed with an incorrect * SPI_MAGIC value * 20:19 - SPI autosize override. Resets to 0x0. * 0 - Use automatically-determined SPI address size (see bits * [18:17] of this register) * 1 - Force SPI address size to 16 bits * 2 - Force SPI address size to 24 bits * 3 - Reserved * 31:21 - Reserved */ #define SPI_CS_ADDRESS MAGPIE_REG_SPI_CS_ADDR //(ZM_SPI_REGISTER_BASE + 0x00000000) /* 3:0 - Transmit byte count, values of 1-8 are valid */ #define SPI_CS_TXBCNT_MSB 3 #define SPI_CS_TXBCNT_LSB 0 #define SPI_CS_TXBCNT_MASK 0x0000000f #define SPI_CS_TXBCNT_GET(x) (((x) & SPI_CS_TXBCNT_MASK) >> SPI_CS_TXBCNT_LSB) #define SPI_CS_TXBCNT_SET(x) (((0x0 | (x)) << SPI_CS_TXBCNT_LSB) & SPI_CS_TXBCNT_MASK) /* 7:4 - Receive byte count, values of 1-8 are valid */ #define SPI_CS_RXBCNT_MSB 7 #define SPI_CS_RXBCNT_LSB 4 #define SPI_CS_RXBCNT_MASK 0x000000f0 #define SPI_CS_RXBCNT_GET(x) (((x) & SPI_CS_RXBCNT_MASK) >> SPI_CS_RXBCNT_LSB) #define SPI_CS_RXBCNT_SET(x) (((0x0 | (x)) << SPI_CS_RXBCNT_LSB) & SPI_CS_RXBCNT_MASK) /* 8 - SPI transaction start */ #define SPI_CS_XCNSTART_MSB 8 #define SPI_CS_XCNSTART_LSB 8 #define SPI_CS_XCNSTART_MASK 0x00000100 #define SPI_CS_XCNSTART_GET(x) 0x0 #define SPI_CS_XCNSTART_SET(x) (((0x0 | (x)) << SPI_CS_XCNSTART_LSB) & SPI_CS_XCNSTART_MASK) #define SPI_CS_XCNSTART_RESET 0x0 /* 9 - SPI chip select */ #define SPI_CS_CS_MSB 9 #define SPI_CS_CS_LSB 9 #define SPI_CS_CS_MASK 0x00000200 #define SPI_CS_CS_GET(x) (((x) & SPI_CS_CS_MASK) >> SPI_CS_CS_LSB) #define SPI_CS_CS_SET(x) (((0x0 | (x)) << SPI_CS_CS_LSB) & SPI_CS_CS_MASK) #define SPI_CS_CS_RESET 0x0 /* 16 - Transaction busy indication */ #define SPI_CS_BUSY_MSB 16 #define SPI_CS_BUSY_LSB 16 #define SPI_CS_BUSY_MASK 0x00010000 #define SPI_CS_BUSY_GET(x) (((x) & SPI_CS_BUSY_MASK) >> SPI_CS_BUSY_LSB) #define SPI_CS_BUSY_SET(x) (((0x0 | (x)) << SPI_CS_BUSY_LSB) & SPI_CS_BUSY_MASK) #define SPI_CS_BUSY_RESET 0x0 /* 18:17 - Automatically-determined SPI address size */ #define SPI_CS_AUTOSIZ_MSB 18 #define SPI_CS_AUTOSIZ_LSB 17 #define SPI_CS_AUTOSIZ_MASK 0x00060000 #define SPI_CS_AUTOSIZ_GET(x) (((x) & SPI_CS_AUTOSIZ_MASK) >> SPI_CS_AUTOSIZ_LSB) #define SPI_CS_AUTOSIZ_SET(x) (((0x0 | (x)) << SPI_CS_AUTOSIZ_LSB) & SPI_CS_AUTOSIZ_MASK) /* 20:19 - SPI autosize override */ #define SPI_CS_AUTOSIZ_OVR_MSB 20 #define SPI_CS_AUTOSIZ_OVR_LSB 19 #define SPI_CS_AUTOSIZ_OVR_MASK 0x00180000 #define SPI_CS_AUTOSIZ_OVR_GET(x) (((x) & SPI_CS_AUTOSIZ_OVR_MASK) >> SPI_CS_AUTOSIZ_OVR_LSB) #define SPI_CS_AUTOSIZ_OVR_SET(x) (((0x0 | (x)) << SPI_CS_AUTOSIZ_OVR_LSB) & SPI_CS_AUTOSIZ_OVR_MASK) #define SPI_CS_AUTOSIZ_OVR_RESET 0x0 #define SPI_CS_RESET (0x0 | \ SPI_CS_AUTOSIZ_OVR_SET(SPI_CS_AUTOSIZ_OVR_RESET) | \ SPI_CS_BUSY_SET(SPI_CS_BUSY_RESET) | \ SPI_CS_CS_SET(SPI_CS_CS_RESET) | \ SPI_CS_XCNSTART_SET(SPI_CS_XCNSTART_RESET)) /* * SPI address/opcode register (SPI_AO) * Access: R/W * Cold reset: (See field descriptions) * Warm reset: (Same as cold reset) * Notes: * * 7:0 - SPI opcode. Usually this field specifies the 8-bit opcode * (aka "instruction") to transmit to the SPI device as the first * part of an SPI transaction. See the 'Notes' section below for * more details. Resets to an undefined value. * 31:8 - Address. Usually this field specifies the 24-bit address to * transmit to the SPI device. See the 'Notes' section below for * more details. Resets to an undefined value. */ #define SPI_AO_ADDRESS MAGPIE_REG_SPI_AO_ADDR //(ZM_SPI_REGISTER_BASE + 0x00000004) /* 7:0 - SPI opcode */ #define SPI_AO_OPC_MSB 7 #define SPI_AO_OPC_LSB 0 #define SPI_AO_OPC_MASK 0x000000ff #define SPI_AO_OPC_GET(x) (((x) & SPI_AO_OPC_MASK) >> SPI_AO_OPC_LSB) #define SPI_AO_OPC_SET(x) (((0x0 | (x)) << SPI_AO_OPC_LSB) & SPI_AO_OPC_MASK) /* 31:8 - Address */ #define SPI_AO_ADDR_MSB 31 #define SPI_AO_ADDR_LSB 8 #define SPI_AO_ADDR_MASK 0xffffff00 #define SPI_AO_ADDR_GET(x) (((x) & SPI_AO_ADDR_MASK) >> SPI_AO_ADDR_LSB) #define SPI_AO_ADDR_SET(x) (((0x0 | (x)) << SPI_AO_ADDR_LSB)& SPI_AO_ADDR_MASK) /* * SPI data register (SPI_D) * Access: R/W * Cold reset: (See field descriptions) * Warm reset: (Same as cold reset) * Notes: * * 31:0 - SPI data. Usually this register specifies a series of up to * four data bytes to transmit to or receive from the SPI device. * See the 'Notes' section below for more details. Resets to an * undefined value. */ #define SPI_D_ADDRESS MAGPIE_REG_SPI_D_ADDR //(ZM_SPI_REGISTER_BASE + 0x00000008) /* 31:0 - SPI data */ #define SPI_D_DATA_MSB 31 #define SPI_D_DATA_LSB 0 #define SPI_D_DATA_MASK 0xffffffff #define SPI_D_DATA_GET(x) (((x) & SPI_D_DATA_MASK) >> SPI_D_DATA_LSB) #define SPI_D_DATA_SET(x) (((0x0 | (x)) << SPI_D_DATA_LSB) & SPI_D_DATA_MASK) /* * SPI clock division register (SPI_CLKDIV) * Access: R/W * Cold reset: (See field descriptions) * Warm reset: (Same as cold reset) * Notes: * * 17:16 - 0b00(fastest), 0b01, 0b10, 0b11(slowest) */ #define SPI_CLKDIV_ADDRESS MAGPIE_REG_SPI_CLKDIV_ADDR //SPI_BASE_ADDRESS + 0x0000001c #define SPI_CLKDIV_MSB 17 #define SPI_CLKDIV_LSB 16 #define SPI_CLKDIV_MASK 0x00030000 #define SPI_CLKDIV_GET(x) (((x) & SPI_CLKDIV_MASK) >> SPI_CLKDIV_LSB) #define SPI_CLKDIV_SET(x) (((0x0 | (x)) << SPI_CLKDIV_LSB) & SPI_CLKDIV_MASK) // read-then-write #define SPI_CLKDIV_RESET 0x3 /* * Notes * ----- * * Background * An SPI transaction consists of three phases: an opcode transmit * phase (always a single byte), followed by an optional address * transmit phase of 0-3 bytes, followed by an optional data transmit * or receive phase of 0-4 bytes. * * Combined, then, an SPI transaction consists of a 1- to 8-byte * transmit phase from Falcon to the SPI device, followed by a 0- to * 8-byte receive phase from the SPI device into Falcon. * * The 'transmit byte count' field in the SPI_CS register controls the * size (number of bytes) of the transmit phase. The source of each * of the bytes transmitted is fixed: * * Byte Source * ---- ----------------------------------------------------------- * 0 SPI_AO[7:0] (the 'SPI opcode' field) * 1 SPI_AO[31:24] (the high byte of the 'SPI address' field) * 2 SPI_AO[23:16] (the middle byte of the 'SPI address' field) * 3 SPI_AO[15:8] (the low byte of the 'SPI address' field) * 4 SPI_D[7:0] (the low byte of the 'SPI data' register) * 5 SPI_D[15:8] (the next byte of the 'SPI data' register) * 6 SPI_D[23:16] (the next byte of the 'SPI data' register) * 7 SPI_D[31:24] (the high byte of the 'SPI data' register) * * * The 'receive byte count' field in the SPI_CS register controls the * size (number of bytes) of the receive phase. The destination of * each of the bytes received is fixed: * * Byte Destination * ---- ----------------------------------------------------------- * 0 SPI_D[7:0] (the low byte of the 'SPI data' register) * 1 SPI_D[15:8] (the next byte of the 'SPI data' register) * 2 SPI_D[23:16] (the next byte of the 'SPI data' register) * 3 SPI_D[31:24] (the high byte of the 'SPI data' register) * 4 SPI_AO[7:0] (the 'SPI opcode' field) * 5 SPI_AO[15:8] (the low byte of the 'SPI address' field) * 6 SPI_AO[23:16] (the middle byte of the 'SPI address' field) * 7 SPI_AO[31:24] (the high byte of the 'SPI address' field) * * * * To perform an SPI transaction: * Write the appropriate values into the SPI_AO and SPI_D registers * * Write the appropriate values into the 'transmit byte count' and * 'received byte count' fields of the SPI_CS register. * * Write a '1' to the 'SPI transaction start' bit of the SPI_CS * register (this step can be combined with the one above if desired * so that only a single SPI_CS write is needed). * * Poll the 'transaction busy indication' bit in the SPI_CS register * until it is clear, indicating that the SPI transaction has * completed. * * If the transaction included a receive phase, then retrieve the * received data by reading the appropriate bytes from the SPI_D and * SPI_AO registers. * * * * Examples: * * A "write disable" (WRDI) transaction: * * Opcode (SPI_AO[7:0]): 0x04 (for STMicro; varies by * manufacturer and device type) * * Address (SPI_AO[31:8]): don't care (not used) * * Data (SPI_D[31:0]): don't care (not used) * * Transmission byte count: 1 * * Receive byte count: 0 * * * A "read status register" (RDSR) transaction: * * Opcode (SPI_AO[7:0]): 0x05 (for STMicro; varies by * manufacturer and device type) * * Address (SPI_AO[31:8]): don't care (not used) * * Data (SPI_D[31:0]): don't care (not used) * * Transmission byte count: 1 * * Receive byte count: 1 * * Read SPI_D[7:0] to retrieve status register value * * * A "page program" (PP) transaction to write a value of 0xdeadbeef * to address 0x123456: * * Opcode (SPI_AO[7:0]): 0x02 (for STMicro; varies by * manufacturer and device type) * * Address (SPI_AO[31:8]): 0x123456 * * Data (SPI_D[31:0]): 0xdeadbeef * * Transmission byte count: 8 * * Receive byte count: 0 */ /* Wait till Transaction busy indication bit in SPI control/status register of Falcon's SPI Flash Controller is clear */ LOCAL void _cmnos_sflash_WaitTillTransactionOver(void) { A_UINT32 poldata; A_UINT32 flg; do { poldata = ioread32(SPI_CS_ADDRESS); flg = SPI_CS_BUSY_GET(poldata); } while (flg != 0x0); } /* Wait till Write In Progress bit in Status Register of Serial Flash is clear */ LOCAL void _cmnos_sflash_WaitTillNotWriteInProcess(void) { A_UINT32 flg; do { _cmnos_sflash_WaitTillTransactionOver(); iowrite32(SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_RDSR)); iowrite32(SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(1) | SPI_CS_RXBCNT_SET(1) | SPI_CS_XCNSTART_SET(1)); _cmnos_sflash_WaitTillTransactionOver(); flg = ioread32(SPI_D_ADDRESS) & ZM_SFLASH_STATUS_REG_WIP; } while (flg != 0x0); } /************************************************************************/ /* Function to Send WREN(Write Enable) Operation */ /************************************************************************/ LOCAL void _cmnos_sflash_WriteEnable() { _cmnos_sflash_WaitTillNotWriteInProcess(); iowrite32(SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_WREN)); iowrite32(SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(1) | SPI_CS_RXBCNT_SET(0) | SPI_CS_XCNSTART_SET(1)); _cmnos_sflash_WaitTillTransactionOver(); } /************************************************************************/ /* Function to Initialize SPI Flash Controller */ /************************************************************************/ LOCAL void cmnos_sflash_init(void) { /* Switch the function of I/O pin 19~22 to act as SPI pins */ io32_set(MAGPIE_REG_CLOCK_CTRL_ADDR, BIT8); /* "Autosize-determination of the address size of serial flash" is obsolete according to Brian Yang's mail : * The designers reached an conclusion that the spi master (the apb_spi interface control) will be * modified as presuming the attached flash model to be 24-bit addressing, i.e., no more * auto-size detection! * Hence you are free to force the 24-bit addressing in the *.c test code. */ /* Force SPI address size to 24 bits */ iowrite32(SPI_CS_ADDRESS, SPI_CS_AUTOSIZ_OVR_SET(2)); } /************************************************************************/ /* Function to Send Sector/Block/Chip Erase Operation */ /************************************************************************/ LOCAL void cmnos_sflash_erase(A_UINT32 erase_type, A_UINT32 addr) { A_UINT32 erase_opcode; A_UINT32 tx_len; if (erase_type == ZM_SFLASH_SECTOR_ERASE) { erase_opcode = ZM_SFLASH_OP_SE; tx_len = 4; } else if (erase_type == ZM_SFLASH_BLOCK_ERASE) { erase_opcode = ZM_SFLASH_OP_BE; tx_len = 4; } else { erase_opcode = ZM_SFLASH_OP_CE; tx_len = 1; } _cmnos_sflash_WriteEnable(); _cmnos_sflash_WaitTillNotWriteInProcess(); iowrite32(SPI_AO_ADDRESS, SPI_AO_OPC_SET(erase_opcode) | SPI_AO_ADDR_SET(addr)); iowrite32(SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(tx_len) | SPI_CS_RXBCNT_SET(0) | SPI_CS_XCNSTART_SET(1)); #if 0 /* Do not wait(let it be completed in background) */ _cmnos_sflash_WaitTillTransactionOver(); #else /* Wait till completion */ _cmnos_sflash_WaitTillNotWriteInProcess(); /* Chip Erase takes 80 - 200 seconds to complete */ #endif } /************************************************************************/ /* Function to Perform Page Program Operation */ /* Notes: */ /* Serial Flash has the following characteristics : */ /* 1) In datasheet, 1-256 data bytes can be sent at a time, but */ /* Falcon supports only 4 bytes at a time. */ /* 2) If the eight least significant address bits(A7-A0) are not */ /* all 0, all transmitted data which goes beyond the end of the */ /* current page are programmed from the start address in the */ /* same page. */ /* This API hides the complexity of the above. */ /************************************************************************/ LOCAL void cmnos_sflash_program(A_UINT32 addr, A_UINT32 len, A_UINT8 *buf) { A_UINT32 s_addr, e_addr; A_UINT32 reminder, write_byte; A_UINT32 data_offset; A_UINT32 next_page_base; A_UINT32 t_word_data; e_addr = addr + len; for (s_addr = addr; s_addr < e_addr; ) { next_page_base = (s_addr - s_addr%ZM_SFLASH_PAGE_SIZE) + ZM_SFLASH_PAGE_SIZE; reminder = e_addr - s_addr; write_byte = next_page_base - s_addr; if (write_byte >= 4) write_byte = 4; if (write_byte > reminder) write_byte = reminder; data_offset = s_addr - addr; A_MEMCPY(&t_word_data, buf + data_offset, write_byte); _cmnos_sflash_WriteEnable(); _cmnos_sflash_WaitTillNotWriteInProcess(); iowrite32(SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_PP) | SPI_AO_ADDR_SET(s_addr)); iowrite32(SPI_D_ADDRESS, SPI_D_DATA_SET(t_word_data)); iowrite32(SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(4 + write_byte) | SPI_CS_RXBCNT_SET(0) | SPI_CS_XCNSTART_SET(1)); _cmnos_sflash_WaitTillTransactionOver(); s_addr += write_byte; } } /************************************************************************/ /* Function to Send Read/Fast Read Data Operation */ /************************************************************************/ LOCAL void cmnos_sflash_read(A_UINT32 fast, A_UINT32 addr, A_UINT32 len, A_UINT8 *buf) { A_UINT32 read_opcode; A_UINT32 i; A_UINT32 read_cnt, remainder; A_UINT32 write_byte, read_byte; if (fast) { read_opcode = ZM_SFLASH_OP_FAST_READ; write_byte = 5; } else { read_opcode = ZM_SFLASH_OP_READ; write_byte = 4; } read_cnt = len/4; remainder = len%4; if (remainder) read_cnt++; read_byte = 4; for (i = 0; i < read_cnt; i ++) { if (i == read_cnt-1 && remainder) read_byte = remainder; _cmnos_sflash_WaitTillNotWriteInProcess(); iowrite32(SPI_AO_ADDRESS, SPI_AO_OPC_SET(read_opcode) | SPI_AO_ADDR_SET(addr + i*4)); iowrite32(SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(write_byte) | SPI_CS_RXBCNT_SET(read_byte) | SPI_CS_XCNSTART_SET(1)); _cmnos_sflash_WaitTillTransactionOver(); A_MEMCPY(buf + i*4, (A_UINT8 *)(SPI_D_ADDRESS), read_byte); } } /************************************************************************/ /* Function to Read Flash Status Register */ /************************************************************************/ LOCAL A_UINT32 cmnos_sflash_rdsr(void) { A_UINT32 word_data; _cmnos_sflash_WaitTillTransactionOver(); iowrite32(SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_RDSR)); iowrite32(SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(1) | SPI_CS_RXBCNT_SET(1) | SPI_CS_XCNSTART_SET(1)); _cmnos_sflash_WaitTillTransactionOver(); word_data = ioread32(SPI_D_ADDRESS) & 0x000000FF; return word_data; } void cmnos_sflash_module_install(struct sflash_api *tbl) { /* Indispensable functions */ tbl->_sflash_init = cmnos_sflash_init; tbl->_sflash_erase = cmnos_sflash_erase; tbl->_sflash_program = cmnos_sflash_program; tbl->_sflash_read = cmnos_sflash_read; /* Dispensable functions */ tbl->_sflash_rdsr = cmnos_sflash_rdsr; } #endif /* SYSTEM_MODULE_SFLASH */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/cmnos/dbg_api.c000077500000000000000000000552721321570333100325350ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include "sys_cfg.h" #include "athos_api.h" #include "adf_os_io.h" #if defined(PROJECT_K2) #if SYSTEM_MODULE_SFLASH #include "sflash_api.h" #endif #endif /* #if defined(PROJECT_K2) */ #if defined(SYSTEM_MODULE_DBG) /* Function prototypes */ static int db_help_cmd(char *, char *, char *, char *); static int db_ldr_cmd(char *, char *, char *, char *); static int db_str_cmd(char *, char *, char *, char *); static int db_info_cmd(char *, char *, char *, char *); static int db_usb_cmd(char *, char *, char *, char *); static int db_intr_cmd(char *, char *, char *, char *); static int db_cmd_starthtc(char *cmd, char *param1, char *param2, char *param3); static int db_wdt_cmd(char *cmd, char *param1, char *param2, char *param3); #if defined(PROJECT_K2) #if SYSTEM_MODULE_SFLASH static int db_cmd_sferase(char *cmd, char *param1, char *param2, char *param3); static int db_cmd_sfpg(char *cmd, char *param1, char *param2, char *param3); static int db_cmd_sfru(char *cmd, char *param1, char *param2, char *param3); static int db_cmd_sfrm(char *cmd, char *param1, char *param2, char *param3); static int db_cmd_sfrdsr(char *cmd, char *param1, char *param2, char *param3); #endif #endif /* #if defined(PROJECT_K2) */ static int db_cmd_memcmp(char *cmd, char *param1, char *param2, char *param3); static int db_cmd_memdump(char *cmd, char *param1, char *param2, char *param3); static int db_clock_cmd(char *cmd, char *param1, char *param2, char *param3); static uint16_t db_get_cmd_line(uint8_t ch, char *cmd_line, uint16_t *i); static int db_formalize_command(char *, char *); static int db_ascii_to_hex(char *, unsigned long *); static int db_hex_to_ascii(unsigned long, char *); static void zf_debug_task(void); /* Console debug command table */ const struct DB_COMMAND_STRUCT command_table[] = { {"HELP", ", List all debug commands", db_help_cmd}, {"?", ", Equal to HELP comamnd", db_help_cmd}, /* Basic load/store/dump command */ {"LDR", ", Load word", db_ldr_cmd}, {"LDRH", ", Load half word", db_ldr_cmd}, {"LDRB", ", Load byte", db_ldr_cmd}, {"STR", " , Store word", db_str_cmd}, {"STRH", " , Store half word", db_str_cmd}, {"STRB", " , Store byte", db_str_cmd}, {"INFO", ", Print debug information", db_info_cmd}, {"USB", ", usb releated command", db_usb_cmd}, {"INTR", ", intr releated command", db_intr_cmd}, {"CLOCK", ", change the clock...", db_clock_cmd}, {"HTCR", "Issue HTC ready to host", db_cmd_starthtc}, {"WDT", ", wdt debug command", db_wdt_cmd}, #if defined(PROJECT_K2) #if SYSTEM_MODULE_SFLASH {"SFE", ", S/B/C, SPI Flash chip erase", db_cmd_sferase}, {"SFPG", " , SPI Flash program", db_cmd_sfpg}, {"SFRU", "f/r , SPI Flash fast read/read to UART", db_cmd_sfru}, {"SFRM", "f/r , SPI Flash fast read/read to Memory 0x520000", db_cmd_sfrm}, {"SFRDSR", ", SPI Flash status register read", db_cmd_sfrdsr}, #endif #endif /* #if defined(PROJECT_K2) */ {"MEMCMP", " , memory comparison", db_cmd_memcmp}, {"MEMDMP", " , memory dump", db_cmd_memdump}, {"", "", 0} /* {Command, Help description, function} */ }; char cmd_buffer[COMMAND_BUFFER_SIZE][DB_MAX_COMMAND_LENGTH]; /* Backup previous command */ int cmd_buf_ptr; int cmd_buf_full; char raw_cmd[DB_MAX_COMMAND_LENGTH]; char cmd_str[DB_MAX_COMMAND_LENGTH*4]; int cmd_not_found; uint16_t gvLen; int pressed_time; static void db_incorect_format(void) { A_PRINTF("Error! Incorrect format.\n\r"); } static void db_unknown_command(void) { A_PRINTF("Error! Unknown command.\n\r"); } static void db_print_dump(const char *mem1, const char *mem2) { unsigned int i = 0; const char *tmp; do { if (i == 0) { A_PRINTF("\n\r%06x: ", mem1); tmp = mem1; } A_PRINTF("%04x ", *(uint16_t *)mem1); mem1 += 2; i++; if (i == 8) { A_PRINTF(" "); do { if (*tmp > 0x20 && *tmp < 0x7e) A_PRINTF("%c", *tmp); else A_PRINTF("."); tmp++; } while (tmp < mem1); i = 0; } } while (mem1 < mem2); A_PRINTF("\n\r"); } static void zf_debug_init(void) { uint8_t ch; /* Purge Rx FIFO */ while ((zm_get_char(&ch)) != 0) { } cmd_buf_ptr = 0; cmd_buf_full = FALSE; gvLen = 0; pressed_time = 0; } static void zf_debug_task(void) { int i; uint8_t ch; if ((zm_get_char(&ch)) == 0) { return; } if (db_get_cmd_line(ch, raw_cmd, &gvLen) == 0) { return; } if (db_formalize_command(raw_cmd, cmd_str)) { gvLen = 0; i = 0; cmd_not_found = TRUE; while(command_table[i].cmd_func) { if (!strcmp(command_table[i].cmd_str, cmd_str)) { cmd_not_found = FALSE; command_table[i].cmd_func(cmd_str, cmd_str+DB_MAX_COMMAND_LENGTH, cmd_str+DB_MAX_COMMAND_LENGTH*2, cmd_str+DB_MAX_COMMAND_LENGTH*3); break; } i++; } if (cmd_not_found) { A_PRINTF("Error, HELP for command list.\n\r"); } } A_PRINTF(">"); return; } static uint16_t db_get_cmd_line(uint8_t ch, char *cmd_line, uint16_t *i) { int cmd_buf_loc; switch (ch) { case '\\' : /* Last command */ pressed_time++; if (pressed_time >= COMMAND_BUFFER_SIZE) { pressed_time--; } cmd_buf_loc = cmd_buf_ptr - pressed_time; if (cmd_buf_loc < 0) { if (cmd_buf_full == TRUE) { cmd_buf_loc += COMMAND_BUFFER_SIZE; } else { cmd_buf_loc = 0; } } if (A_STRLEN(cmd_buffer[cmd_buf_loc]) != 0) { A_STRCPY(cmd_line, cmd_buffer[cmd_buf_loc]); *i = A_STRLEN(cmd_buffer[cmd_buf_loc]); A_PRINTF("\r>"); A_PRINTF("%s", cmd_line); } break; case 13 : /* Return */ pressed_time = 0; cmd_line[*i] = 0; A_PRINTF("\n\r"); if (*i != 0) { //Filter duplicated string in command history if (strcmp(cmd_buffer[(cmd_buf_ptr==0)?(COMMAND_BUFFER_SIZE-1):(cmd_buf_ptr-1)], cmd_line) != 0) { A_STRCPY(cmd_buffer[cmd_buf_ptr++], cmd_line); } } if (cmd_buf_ptr >= COMMAND_BUFFER_SIZE) { cmd_buf_ptr = 0; cmd_buf_full = TRUE; } return 1; case '\b' : /* Backspace */ pressed_time = 0; if (*i > 0) { *i = *i-1; A_PRINTF("\b \b"); } break; case 0 : //None break; default : if ((ch >= ' ') && (ch <= '~')) { pressed_time = 0; if (*i < DB_MAX_COMMAND_LENGTH-2) { if ((ch >= 0x11) && (ch <= 0x7e)) { //if ((buf <= 'z') && (buf >= 'a')) //{ // buf -= 'a' - 'A'; //} cmd_line[*i] = ch; *i = *i + 1; A_PRINTF("%c", ch); } } } else { ch = 7; /* Beep */ A_PRINTF("%c", ch); } break; } /* end of switch */ return 0; } static int db_formalize_command(char *raw_str, char *cmd_str) { int i = 0; int j; int k; for (k=0; k<4; k++) { /* Remove preceeding spaces */ while (raw_str[i++] == ' '){} i--; /* Copy command string */ j = 0; while(raw_str[i] && (raw_str[i] != ' ')) { if (k == 0) { if ((raw_str[i] <= 'z') && (raw_str[i] >= 'a')) { raw_str[i] -= 'a' - 'A'; } cmd_str[k*DB_MAX_COMMAND_LENGTH + j++] = raw_str[i++]; } else { cmd_str[k*DB_MAX_COMMAND_LENGTH + j++] = raw_str[i++]; } } cmd_str[k*DB_MAX_COMMAND_LENGTH + j] = 0; } return (int)A_STRLEN(cmd_str); } static int db_ascii_to_hex(char *num_str, unsigned long *hex_num) { int i = 0; *hex_num = 0; while (num_str[i]) { if ((num_str[i] >= '0') && (num_str[i] <= '9')) { *hex_num <<= 4; *hex_num += (num_str[i] - '0'); } else if ((num_str[i] >= 'A') && (num_str[i] <= 'F')) { *hex_num <<= 4; *hex_num += (num_str[i] - 'A' + 10); } else if ((num_str[i] >= 'a') && (num_str[i] <= 'f')) { *hex_num <<= 4; *hex_num += (num_str[i] - 'a' + 10); } else { return -1; } i++; } return 0; } int db_ascii_to_int(char *num_str, unsigned long *int_num) { int i = 0; *int_num = 0; while (num_str[i]) { if ((num_str[i] >= '0') && (num_str[i] <= '9')) { *int_num *= 10; *int_num += (num_str[i] - '0'); } else { return -1; } i++; } return 0; } static int db_hex_to_ascii(unsigned long hex_num, char *num_str) { int i; unsigned long four_bits; for (i=7; i>=0; i--) { four_bits = (hex_num >> i*4) & 0xf; if (four_bits < 10) { num_str[7-i] = four_bits + '0'; } else { num_str[7-i] = four_bits - 10 + 'A'; } } num_str[8] = 0; return 0; } int db_help_cmd(char *cmd, char *param1, char *param2, char *param3) { int i; i = 0; A_PRINTF("%s %s\n", ATH_DEBUGGER_VERSION_STR, ATH_COMMAND_LIST_STR); while (command_table[i].cmd_func) { A_PRINTF("%s\t%s\n\r", command_table[i].cmd_str, command_table[i].help_str); i++; } return i; } static int db_ldr_cmd(char *cmd, char *param1, char *param2, char *param3) { unsigned long val = 0; unsigned long addr; char val_str[20]; char addr_str[20]; if (db_ascii_to_hex(param1, &addr) != -1) { if( addr == 0 ) { A_PRINTF("Error! bad address 0x%08x.\n\r", (unsigned long)addr); return -1; } if (strcmp(cmd, "LDR") == 0) { addr &= 0xfffffffc; //val = *(unsigned long *)addr; val = ioread32(addr); } else if (strcmp(cmd, "LDRH") == 0) { addr &= 0xfffffffe; val = ioread16(addr); } else if (strcmp(cmd, "LDRB") == 0) { } db_hex_to_ascii(val, val_str); db_hex_to_ascii(addr, addr_str); A_PRINTF("%s : %s\n\r", addr_str, val_str); return 0; } db_incorect_format(); return -1; } static int db_str_cmd(char *cmd, char *param1, char *param2, char *param3) { unsigned long val; unsigned long addr; char val_str[20]; char addr_str[20]; if ((A_STRLEN(param2) > 0) && (db_ascii_to_hex(param1, &addr) != -1) && (db_ascii_to_hex(param2, &val) != -1)) { if (strcmp(cmd, "STR") == 0) { addr &= 0xfffffffc; iowrite32(addr, val); } else if (strcmp(cmd, "STRH") == 0) { addr &= 0xfffffffe; //*(volatile unsigned short *)(addr & 0xfffffffe) = (unsigned short)val; iowrite16(addr, val); } else if (strcmp(cmd, "STRB") == 0) { if( addr & 0x00f00000 ) iowrite8(addr, val); else iowrite8(addr^3, val); //*(volatile unsigned char *)addr = (unsigned char)val; } db_hex_to_ascii(val, val_str); db_hex_to_ascii(addr, addr_str); A_PRINTF("%s : %s\n\r", addr_str, val_str); return 0; } db_incorect_format(); return -1; } LOCAL void dbg_timer_func(A_HANDLE alarm, void *data) { A_PRINTF("this is a timer alarm function 0x%08x\n\r", xthal_get_ccount()); } uint32_t delay = 0; static int db_intr_cmd(char *cmd, char *param1, char *param2, char *param3) { #if SYSTEM_MODULE_INTR uint32_t pending_intrs; if(strcmp(param1, "read") == 0 ) { { /* Update snapshot of pending interrupts */ pending_intrs = A_INTR_GET_INTRPENDING(); A_PRINTF("intr mask [0x%08x]\n\r", xthal_get_intenable()); A_PRINTF("intr on [0x%08x]\n\r", pending_intrs); } } else if (strcmp(param1, "timer") == 0 ) { uint32_t data = 0; if (strcmp(param2, "on") == 0 ) { /* TODO: this part is probably dead. */ pending_intrs = A_INTR_GET_INTRENABLE()|CMNOS_IMASK_XTTIMER; A_INTR_SET_INTRENABLE(pending_intrs); A_PRINTF("- intr [0x%08x]\n\r", pending_intrs); } else if ( strcmp(param2, "off") == 0 ) { pending_intrs = A_INTR_GET_INTRENABLE()&(~CMNOS_IMASK_XTTIMER); A_INTR_SET_INTRENABLE(pending_intrs); A_PRINTF("- intr [0x%08x]\n\r", pending_intrs); } else if( db_ascii_to_hex(param2, &data)==0 ) { if( data>=0 && data <=10 ) delay = data; else delay = 3; A_PRINTF("==>set cb to %d seconds \n\r", delay); } } else { A_PRINTF("\tintr read - read the interrenable status\n\r"); A_PRINTF("\tintr timer on/off/tick - timer attach on/off/ticks\n\r"); } #endif //#if SYSTEM_MODULE_INTR return 0; } static int db_usb_cmd(char *cmd, char *param1, char *param2, char *param3) { A_PRINTF("THIS IS USB COMMAND\n\r"); if( strcmp(param1, "que") == 0 ) { HIFusb_DescTraceDump(); } else { A_PRINTF("\tusb que - dump descriptor queue\n\r"); A_PRINTF("\tusb fw on/off - enable/disable write fw download to ram\n\r"); } return 0; } static void clk_change(uint32_t clk, uint32_t ratio, uint32_t baud) { uint32_t clk_sel = 0; switch(clk){ case 22: clk_sel = 0; break; case 88: clk_sel = 1; break; case 44: clk_sel = 2; break; case 117: clk_sel = 4; break; case 40: clk_sel = 6; break; default: clk_sel = 6; break; } iowrite32(0x50040, (0x300|clk_sel|(ratio>>1)<<12)); A_UART_HWINIT((clk*1000*1000)/ratio, baud); } static int db_clock_cmd(char *cmd, char *param1, char *param2, char *param3) { uint32_t ratio = 1; uint32_t baud = 19200; uint32_t clk = 0; if( db_ascii_to_int(param1, &clk) != -1 ) { A_PRINTF("changing clock to %d\n", clk); clk_change(clk, ratio, baud); } } static int db_info_cmd(char *cmd, char *param1, char *param2, char *param3) { #if 1 if(strcmp(param1, "ram") == 0 ) { A_ALLOCRAM_DEBUG(); } #if 0 /* TODO: SYSTEM_MODULE_SYS_MONITOR depends on _ROM_ or _RAM_ which * is dead too */ else if(strcmp(param1, "cpu") == 0) zfPrintCpuUtilization(); #endif else // defalut dump HIFusb_DescTraceDump(); return 1; #else { uint32_t ccount1; uint32_t ccount2; uint32_t data; register uint32_t data1; if( db_ascii_to_hex(param1, &data1)==0 ) { __asm__ __volatile__ ( "rsr %0, ccount" : "=a" (ccount1) : : "memory" ); data = *(volatile uint32_t *)(data1); __asm__ __volatile__ ( "rsr %0, ccount" : "=a" (ccount2) : : "memory" ); A_PRINTF("\n\rread 0x%08x (0x%08x) use %d clocks\n\r", data1, data, ccount2-ccount1); } __asm__ __volatile__ ( "rsr %0, ccount" : "=a" (ccount1) : : "memory" ); data = *(volatile uint32_t *)(data1); __asm__ __volatile__ ( "rsr %0, ccount" : "=a" (ccount2) : : "memory" ); A_PRINTF("\n\rread 0x%08x (0x%08x) use %d clocks\n\r", data1, data, ccount2-ccount1); __asm__ __volatile__ ( "rsr %0, ccount" : "=a" (ccount1) : : "memory" ); data = *(volatile uint32_t *)(data2); __asm__ __volatile__ ( "rsr %0, ccount" : "=a" (ccount2) : : "memory" ); A_PRINTF("read 0x%08x (0x%08x) use %d clocks\n\r", data2, data, ccount2-ccount1); __asm__ __volatile__ ( "rsr %0, ccount" : "=a" (ccount1) : : "memory" ); data = *(volatile uint32_t *)(data3); __asm__ __volatile__ ( "rsr %0, ccount" : "=a" (ccount2) : : "memory" ); A_PRINTF("read 0x%08x (0x%08x) use %d clocks\n\r", data3, data, ccount2-ccount1); } #endif return 1; } static int db_cmd_starthtc(char *cmd, char *param1, char *param2, char *param3) { extern htc_handle_t htc_handle; HTC_Ready(htc_handle); } static int db_wdt_cmd(char *cmd, char *param1, char *param2, char *param3) { if ( strcmp(param1, "rst") == 0 ) { A_PRINTF(" reseting...\n\n\r"); A_WDT_RESET(); } else if( strcmp(param1, "on") == 0 ) { A_WDT_ENABLE(); } else if (strcmp(param1, "off") == 0 ) { A_WDT_DISABLE(); } else if ( strcmp(param1, "boot") == 0 ) { A_PRINTF("Last BOOT is "); if (ENUM_WDT_BOOT == A_WDT_LASTBOOT() ) A_PRINTF("wdt"); else A_PRINTF("normal boot"); } else if (strcmp(param1, "loop") == 0 ) { T_WDT_CMD wdt_cmd; uint32_t time_offset; A_PRINTF(" doing the wdt reseting..."); if( db_ascii_to_hex(param2, &time_offset)!=0 ) { if( time_offset < 0 || time_offset >0xffffffff ) time_offset = 0xffffff; } A_PRINTF(" (wdt tick: 0x%08x...\n\n\r", time_offset); wdt_cmd.cmd = WDT_TIMEOUT; wdt_cmd.timeout = time_offset; A_WDT_SET(wdt_cmd); while(1) ; } else if (strcmp(param1, "noloop") == 0 ) { T_WDT_CMD wdt_cmd; uint32_t time_offset; A_PRINTF(" doing the wdt reseting..."); if( db_ascii_to_hex(param3, &time_offset)!=0 ) { if( time_offset < 0 || time_offset >0xffffffff ) time_offset = 0xffffff; } A_PRINTF(" (wdt tick: 0x%08x...\n\n\r", time_offset); wdt_cmd.cmd = WDT_TIMEOUT; wdt_cmd.timeout = time_offset; A_WDT_SET(wdt_cmd); } else if( strcmp(param1, "event") == 0 ) { uint32_t event= 0x00123400; /* disable ep3 intr */ iowrite8_usb(0x17, ioread8_usb(0x17)|0xc0); /* ZM_CBUS_FIFO_SIZE_REG = 0xf */ iowrite32_usb(0x100, 0x0f); /* ZM_EP3_DATA_REG = event; */ iowrite32_usb(0xF8, event); /* tx done */ iowrite8_usb(0xAE, ioread8_usb(0xAE) | 0x08); /* enable ep3 intr */ iowrite8_usb(0x17, ioread8_usb(0x17) & 0xbf); } } #if defined(PROJECT_K2) #if SYSTEM_MODULE_SFLASH /* Serial Flash -> Chip Erase, Sector Erase, Block Erase */ static int db_cmd_sferase(char *cmd, char *param1, char *param2, char *param3) { unsigned long addr; if (strcmp(param1, "s") == 0) { if (db_ascii_to_hex(param2, &addr) != -1 && addr < SPI_FLASH_MAX_SIZE) { /* Sector size is 4K (0x1000) */ A_PRINTF("Sector addr : 0x%08X\n\r", addr - addr%0x1000); A_SFLASH_ERASE(ZM_SFLASH_SECTOR_ERASE, addr); return 0; } db_incorect_format(); return -1; } else if (strcmp(param2, "b") == 0) { if (db_ascii_to_hex(param2, &addr) != -1 && addr < SPI_FLASH_MAX_SIZE) { /* Sector size is 64K (0x10000) */ A_PRINTF("Block addr : 0x%08X\n\r", addr - addr%0x10000); A_SFLASH_ERASE(ZM_SFLASH_BLOCK_ERASE, addr); return 0; } db_incorect_format(); return -1; } else if (strcmp(param1, "c") == 0) { A_SFLASH_ERASE(ZM_SFLASH_CHIP_ERASE, addr); A_PRINTF("\n\r"); return 0; } db_unknown_command(); return -1; } /* Serial Flash -> Program */ static int db_cmd_sfpg(char *cmd, char *param1, char *param2, char *param3) { unsigned long addr, len, buf; if (db_ascii_to_hex(param1, &addr) != -1 && db_ascii_to_hex(param2, &len) != -1 && db_ascii_to_hex(param3, &buf) != -1 && ((addr+len) <= SPI_FLASH_MAX_SIZE) && addr%4 == 0 && len%4 == 0 && buf%4 == 0 && ((buf >=0x500000 && buf < 0x528000) || (buf >=0x4e0000 && buf < 0x4e6000)) ) { A_SFLASH_PROG(addr, len, (A_UINT8 *)buf); A_PRINTF("\n\r"); return 0; } db_incorect_format(); return -1; } /* Serial Flash -> Read, Fast Read to UART */ static int db_cmd_sfru(char *cmd, char *param1, char *param2, char *param3) { A_UINT32 i; unsigned long addr1, addr2, t_addr; A_UINT32 fast, val; if (strcmp(param1, "r") == 0) fast = 0; else if (strcmp(param1, "f") == 0) fast = 1; else { db_unknown_command(); return -1; } if (db_ascii_to_hex(param2, &addr1) != -1 && db_ascii_to_hex(param3, &addr2) != -1 && addr1 < addr2 && addr1 < SPI_FLASH_MAX_SIZE && addr2 < SPI_FLASH_MAX_SIZE && addr1%4 == 0) { A_PRINTF("addr data data data data data data data data\n\r"); A_PRINTF("====== ======== ======== ======== ======== ======== ======== ======== ========"); for (i = 0, t_addr = addr1; t_addr < addr2; i++, t_addr += 4) { if ((i%8) == 0) A_PRINTF("\n\r%06X ", t_addr); A_SFLASH_READ(fast, t_addr, 4, (A_UINT8 *)&val); A_PRINTF("%08X ", val); } A_PRINTF("\n\r"); return 0; } db_incorect_format(); return -1; } /* Serial Flash -> Read, Fast Read to Memory */ static int db_cmd_sfrm(char *cmd, char *param1, char *param2, char *param3) { A_UINT32 i; unsigned long addr1, addr2, t_addr; A_UINT32 fast; A_UINT8 *buf = (A_UINT8 *)0x520000; if (strcmp(param1, "r") == 0) fast = 0; else if (strcmp(param1, "f") == 0) fast = 1; else { db_unknown_command(); return -1; } if (db_ascii_to_hex(param2, &addr1) != -1 && db_ascii_to_hex(param3, &addr2) != -1 && addr1 < addr2 && addr1 < SPI_FLASH_MAX_SIZE && addr2 < SPI_FLASH_MAX_SIZE && addr1%4 == 0) { for (i = 0, t_addr = addr1; t_addr < addr2; i++, t_addr += 4) { A_SFLASH_READ(fast, t_addr, 4, buf + i*4); } A_PRINTF("\n\r"); return 0; } db_incorect_format(); return -1; } /* Serial Flash -> Read Status Register */ static int db_cmd_sfrdsr(char *cmd, char *param1, char *param2, char *param3) { A_PRINTF("0x%02X\n\r", A_SFLASH_RDSR()); return 0; } #endif #endif /* #if defined(PROJECT_K2) */ /* Memory Comparison */ static int db_cmd_memcmp(char *cmd, char *param1, char *param2, char *param3) { unsigned long addr1, addr2, len; A_UINT8 *buf1, *buf2; if (db_ascii_to_hex(param1, &addr1) != -1 && db_ascii_to_hex(param2, &addr2) != -1 && db_ascii_to_hex(param3, &len) != -1 && addr1 != addr2 && addr1%4 == 0 && addr2%4 == 0 && len%4 == 0) { buf1 = (A_UINT8 *)addr1; buf2 = (A_UINT8 *)addr2; ; A_PRINTF("memcmp(buf1, buf2, len) = %d\n\r", A_MEMCMP(buf1, buf2, len)); return 0; } db_incorect_format(); return -1; } /* Memory Dump */ static int db_cmd_memdump(char *cmd, char *param1, char *param2, char *param3) { unsigned long addr1, addr2; if (db_ascii_to_hex(param1, &addr1) != -1 && db_ascii_to_hex(param2, &addr2) != -1 && addr1 < addr2 && addr1%4 == 0) { db_print_dump((const char *)addr1, (const char *)addr2); return 0; } db_incorect_format(); return -1; } void cmnos_dbg_module_install(struct dbg_api *apis) { apis->_dbg_init = zf_debug_init; apis->_dbg_task = zf_debug_task; } #endif /* SYSTEM_MODULE_DBG */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/cmnos/dbg_api.h000077500000000000000000000072721321570333100325370ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /************************************************************************/ /* */ /* FILE DESCRIPTION */ /* */ /* This file contains console debug command table structure and */ /* relative defination. */ /* */ /* ROUTINES */ /* */ /* None */ /* */ /* NOTES */ /* */ /* None */ /* */ /************************************************************************/ #ifndef _DB_DEFS_H #define _DB_DEFS_H #define ATH_DEBUGGER_VERSION_STR "Magpie Debugger: "ATH_VERSION_STR #define ATH_COMMAND_LIST_STR "\n\r===Command Listing===\n\r" #define DB_MAX_COMMAND_LENGTH 40 /* Maximum command line length */ #define COMMAND_BUFFER_SIZE 6 /* Maximum command buffer size */ struct DB_COMMAND_STRUCT { char* cmd_str; /* Command string */ char* help_str; /* Help description */ int (*cmd_func)(char *, char*, char*, char*); /* Command function */ }; #define zm_get_char(x) A_GETC(x) /******** hardware API table structure (API descriptions below) *************/ struct dbg_api { void (*_dbg_init)(void); void (*_dbg_task)(void); }; void cmnos_dbg_module_install(struct dbg_api *apis); #endif k2_cmnos_clock_patch.c000077500000000000000000000053731321570333100351330ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/cmnos/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "athos_api.h" #include "sys_cfg.h" a_uint32_t ref_clk = 0; extern a_uint32_t cticks; // clock change // void cmnos_clock_init_patch(a_uint32_t refclk) { ref_clk = refclk; } // retrieve current clock setting // a_uint32_t cmnos_refclk_speed_get_patch(void) { return ref_clk; } // software emulate delay function // void cmnos_delay_us_patch(int us) { a_uint32_t start_time = NOW(); unsigned int num_ticks = us*ref_clk; // system_freq == number of ticks per 1us while ( (NOW() - start_time) < num_ticks) { /* busy spin */ ; } } // software emulate microsecond ticks // void cmnos_tick_patch(void) { static a_uint32_t last_tick = 0; a_uint32_t current_tick = NOW(); a_uint32_t delta_tick; delta_tick = (A_UINT32 ) (current_tick - last_tick)/(ref_clk<<10); if( delta_tick > 0 ) last_tick = current_tick; cticks += delta_tick; } // get current sysmem up time in milliseconds based // a_uint32_t cmnos_milliseconds_patch(void) { cmnos_tick_patch(); return (cticks); } k2_fw_cmnos_printf.c000077500000000000000000000210541321570333100346510ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/cmnos//####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. // Copyright (C) 2002 Gary Thomas // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free // Software Foundation; either version 2 or (at your option) any later version. // // eCos is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License // for more details. // // You should have received a copy of the GNU General Public License // along with this program. If not, see . // // As a special exception, if other files instantiate templates or use macros // or inline functions from this file, or you compile this file and link it // with other works to produce a work based on this file, this file does not // by itself cause the resulting work to be covered by the GNU General Public // License. However the source code for this file must still be made available // in accordance with section (3) of the GNU General Public License. // // This exception does not invalidate any other reasons why a work based on // this file might be covered by the GNU General Public License. // // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. // at http://sources.redhat.com/ecos/ecos-license/ // ------------------------------------------- //####ECOSGPLCOPYRIGHTEND#### #include "sys_cfg.h" #include "dt_defs.h" #if SYSTEM_MODULE_PRINT #if MOVE_PRINT_TO_RAM #include "athos_api.h" #define is_digit(c) ((c >= '0') && (c <= '9')) #if defined(__GNUC__) && defined(__mips__) #define va_list __builtin_va_list #define va_arg __builtin_va_arg #define va_start __builtin_va_start #define va_end __builtin_va_end #define va_copy __builtin_va_copy #endif #include LOCAL void cmnos_write_char(char c) { if (c == '\n') { A_PUTC('\r'); A_PUTC('\n'); } else if (c == '\r') { } else { A_PUTC(c); } } LOCAL void (*_putc)(char c) = cmnos_write_char; LOCAL int _cvt(unsigned long val, char *buf, long radix, char *digits) { char temp[80]; char *cp = temp; int length = 0; if (val == 0) { /* Special case */ *cp++ = '0'; } else { while (val) { *cp++ = digits[val % radix]; val /= radix; } } while (cp != temp) { *buf++ = *--cp; length++; } *buf = '\0'; return (length); } LOCAL int cmnos_vprintf(void (*putc)(char c), const char *fmt, va_list ap) { char buf[sizeof(long)*8]; char c, sign, *cp=buf; int left_prec, right_prec, zero_fill, pad, pad_on_right, i, islong, islonglong; long val = 0; int res = 0, length = 0; while ((c = *fmt++) != '\0') { if (c == '%') { c = *fmt++; left_prec = right_prec = pad_on_right = islong = islonglong = 0; if (c == '-') { c = *fmt++; pad_on_right++; } if (c == '0') { zero_fill = TRUE; c = *fmt++; } else { zero_fill = FALSE; } while (is_digit(c)) { left_prec = (left_prec * 10) + (c - '0'); c = *fmt++; } if (c == '.') { c = *fmt++; zero_fill++; while (is_digit(c)) { right_prec = (right_prec * 10) + (c - '0'); c = *fmt++; } } else { right_prec = left_prec; } sign = '\0'; if (c == 'l') { // 'long' qualifier c = *fmt++; islong = 1; if (c == 'l') { // long long qualifier c = *fmt++; islonglong = 1; } } // Fetch value [numeric descriptors only] switch (c) { case 'p': islong = 1; case 'd': case 'D': case 'x': case 'X': case 'u': case 'U': case 'b': case 'B': if (islonglong) { val = va_arg(ap, long); } else if (islong) { val = (long)va_arg(ap, long); } else{ val = (long)va_arg(ap, int); } if ((c == 'd') || (c == 'D')) { if (val < 0) { sign = '-'; val = -val; } } else { // Mask to unsigned, sized quantity if (islong) { val &= (1ULL << (sizeof(long) * 8)) - 1; } else{ val &= (1ULL << (sizeof(int) * 8)) - 1; } } break; default: break; } // Process output switch (c) { case 'p': // Pointer (*putc)('0'); (*putc)('x'); zero_fill = TRUE; left_prec = sizeof(unsigned long)*2; case 'd': case 'D': case 'u': case 'U': case 'x': case 'X': switch (c) { case 'd': case 'D': case 'u': case 'U': length = _cvt(val, buf, 10, "0123456789"); break; case 'p': case 'x': length = _cvt(val, buf, 16, "0123456789abcdef"); break; case 'X': length = _cvt(val, buf, 16, "0123456789ABCDEF"); break; } cp = buf; break; case 's': case 'S': cp = va_arg(ap, char *); if (cp == NULL) { cp = ""; } length = 0; while (cp[length] != '\0') length++; break; case 'c': case 'C': c = va_arg(ap, int /*char*/); (*putc)(c); res++; continue; case 'b': case 'B': length = left_prec; if (left_prec == 0) { if (islonglong) length = sizeof(long)*8; else if (islong) length = sizeof(long)*8; else length = sizeof(int)*8; } for (i = 0; i < length-1; i++) { buf[i] = ((val & ((long)1< 0) { (*putc)(c); res++; } } if (sign != '\0') { (*putc)(sign); res++; } while (length-- > 0) { c = *cp++; (*putc)(c); res++; } if (pad_on_right) { while (pad-- > 0) { (*putc)(' '); res++; } } } else { (*putc)(c); res++; } } return (res); } int fw_cmnos_printf(const char *fmt, ...) { va_list ap; int ret; va_start(ap, fmt); //if (A_SERIAL_ENABLED()) { if (1) { ret = cmnos_vprintf(_putc, fmt, ap); } else { ret = 0; } va_end(ap); return (ret); } #endif /* MOVE_PRINT_TO_RAM */ #endif /* SYSTEM_MODULE_PRINT */ printf_api.h000077500000000000000000000040451321570333100332210ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/cmnos/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __PRINTF_API_H__ #define __PRINTF_API_H__ struct printf_api { void (* _printf_init)(void); int (* _printf)(const char * fmt, ...); }; /* NB: The printf module requires the serial module. */ void cmnos_printf_module_install(struct printf_api *tbl); int cmnos_printf(const char *fmt, ...); #endif /* __PRINTF_API_H__ */ sflash_api.h000077500000000000000000000053711321570333100332020ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/cmnos/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __SFLASH_API_H__ #define __SFLASH_API_H__ /* Constant definition */ #define ZM_SFLASH_SECTOR_ERASE 1 #define ZM_SFLASH_BLOCK_ERASE 2 #define ZM_SFLASH_CHIP_ERASE 0 /*!- interface of eeprom access * */ struct sflash_api { /* Indispensable functions */ void (* _sflash_init)(void); void (* _sflash_erase)(A_UINT32 erase_type, A_UINT32 addr); /* 1. erase_type : chip/block/sector, 2. addr : no use for chip erase */ void (* _sflash_program)(A_UINT32 addr, A_UINT32 len, A_UINT8 *buf); /* 1. addr : spi flash address(start from 0x0), 2. len : bite number to write , 3. *buf : source memory address */ void (* _sflash_read)(A_UINT32 fast, A_UINT32 addr, A_UINT32 len, A_UINT8 *buf); /* 1. fast : 1 for fast read, 0 for read, 2. addr : spi flash address(start from 0x0), 3. len : bite number to read , 3. *buf : destination memory address */ /* Dispensable functions */ A_UINT32 (* _sflash_rdsr)(void); /* return the value of status register */ }; #endif /* __SFLASH_API_H__ */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/hif/000077500000000000000000000000001321570333100304155ustar00rootroot00000000000000k2_HIF_usb_patch.c000077500000000000000000000045641321570333100335500ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/hif/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "sys_cfg.h" #include "dt_defs.h" #include "reg_defs.h" #include #include #include #include #include #include #include #include "hif_usb.h" /* * -- support more than 64 bytes command on ep4 -- */ int _HIFusb_get_max_msg_len_patch(hif_handle_t handle, int pipe) { switch(pipe) { case HIF_USB_PIPE_INTERRUPT: case HIF_USB_PIPE_COMMAND: return 512; default: return 1600; } } /* * -- move the usb_task to here -- */ void _HIFusb_isr_handler_patch(hif_handle_t h) { A_USB_FW_TASK(); _HIFusb_isr_handler(h); } usb_api_k2_patch.c000077500000000000000000000230541321570333100337060ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/hif/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "usb_defs.h" #include "usb_type.h" #include "usb_pre.h" #include "usb_extr.h" #include "usb_std.h" #include "reg_defs.h" #include "athos_api.h" #include "usbfifo_api.h" #include "adf_os_io.h" #include "sys_cfg.h" void _fw_usb_suspend_reboot(); extern Action eUsbCxFinishAction; extern CommandType eUsbCxCommand; extern BOOLEAN UsbChirpFinish; extern USB_FIFO_CONFIG usbFifoConf; #if SYSTEM_MODULE_USB #define CHECK_SOF_LOOP_CNT 50 void _fw_usb_suspend_reboot() { volatile uint32_t gpio_in = 0; volatile uint32_t pupd = 0; volatile uint32_t t = 0; volatile uint32_t sof_no=0,sof_no_new=0; /* Set GO_TO_SUSPEND bit to USB main control register */ io8_clr_usb(ZM_INTR_SOURCE_7_OFFSET, BIT2); A_PRINTF("!USB suspend\n\r"); /* keep the record of suspend */ #if defined(PROJECT_MAGPIE) iowrite32(WATCH_DOG_MAGIC_PATTERN_ADDR, SUS_MAGIC_PATTERN); #elif defined(PROJECT_K2) iowrite32(MAGPIE_REG_RST_STATUS_ADDR, SUS_MAGIC_PATTERN); #endif /* #if defined(PROJECT_MAGPIE) */ /* Reset USB FIFO */ A_USB_RESET_FIFO(); /* Turn off power */ A_USB_POWER_OFF(); DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xffff)) | 0x1000; #if 0 /* reset ep3/ep4 fifo in case there * is data which might affect resuming */ iowrite8(0x100ae, ioread8(0x100ae) | 0x10); iowrite8(0x100ae, ioread8(0x100af) | 0x10); /* config gpio to input before goto suspend */ /* disable JTAG/ICE */ jtag = ioread32(0x10004054); iowrite32(0x10004054, jtag | BIT17); /* disable SPI */ spi = ioread32(0x50040); iowrite32(0x50040, spi & ~BIT8); #endif /* set all GPIO to input */ gpio_in = ioread32(0x1000404c); iowrite32(0x1000404c, 0x0); /* set PU/PD for all GPIO except two UART pins */ pupd = ioread32(0x10004088); iowrite32(0x10004088, 0xA982AA6A); sof_no = ioread32(0x10004); for (t = 0; t < CHECK_SOF_LOOP_CNT; t++) { A_DELAY_USECS(1000); /* delay 1ms */ sof_no_new = ioread32(0x10004); if(sof_no_new == sof_no) break; sof_no = sof_no_new; } /* * Reset "printf" module patch point(RAM to ROM) * when K2 warm start or suspend, * which fixed the error issue cause by redownload * another different firmware. */ _indir_tbl.cmnos.printf._printf = save_cmnos_printf; /* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! * setting the go suspend here, power down right away!!! */ if (t != CHECK_SOF_LOOP_CNT) /* not time out */ io32_set(0x10000, BIT3); DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xffff)) | 0x1100; #if 0 /* pll unstable, h/w bug? */ iowrite32(0x50040, 0x300 | 6 | (1>>1) << 12); A_UART_HWINIT((40*1000*1000)/1, 19200); /* restore gpio setting */ iowrite32(0x10004054, jtag); iowrite32(0x50040, spi); #endif iowrite32(0x1000404c, gpio_in); iowrite32(0x10004088, pupd); DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xffff)) | 0x1200; /* since we still need to touch mac_base address after resuming back, * so that reset mac can't be done in ResetFifo function, * move to here... whole mac control reset.... (bit1) */ iowrite32(MAGPIE_REG_RST_PWDN_CTRL_ADDR, BIT1); io32_set(MAGPIE_REG_RST_PWDN_CTRL_ADDR, BIT0); iowrite32(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0); A_DELAY_USECS(1000); /* disable ep3 int enable, so that resume back won't * send wdt magic pattern out!!! */ mUSB_STATUS_IN_INT_DISABLE(); MAGPIE_REG_USB_RX0_SWAP_DATA = 0x1; MAGPIE_REG_USB_TX0_SWAP_DATA = 0x1; MAGPIE_REG_USB_RX1_SWAP_DATA = 0x1; MAGPIE_REG_USB_RX2_SWAP_DATA = 0x1; if (((DEBUG_SYSTEM_STATE&~(0x0000ffff))>>16 == 0x5342)) { /* UART_SEL and SPI_SEL */ iowrite32(0x50040, 0x300 | 0 | (1 >> 1) << 12); } /* Jump to boot code */ A_USB_JUMP_BOOT(); } /* * patch usb_fw_task * usb zero length interrupt should not clear by s/w, h/w will handle that * complete suspend handle, configure gpio, turn off related function, * slow down the pll for stable issue */ void _fw_usb_fw_task(void) { register uint8_t usb_interrupt_level1; register uint8_t usb_interrupt_level2; usb_interrupt_level1 = ioread8_usb(ZM_INTR_GROUP_OFFSET); #if 0 /* these endpoints are handled by DMA */ if (usb_interrupt_level1 & BIT5) { vUsb_Data_In(); } #endif if (usb_interrupt_level1 & BIT4) { usb_interrupt_level2 = ioread8_usb(ZM_INTR_SOURCE_4_OFFSET); if(usb_interrupt_level2 & BIT6) A_USB_REG_OUT(); /* vUsb_Reg_Out() */ } if (usb_interrupt_level1 & BIT6) { /* zfGenWatchDogEvent(); ?? */ usb_interrupt_level2 = ioread8_usb(ZM_INTR_SOURCE_6_OFFSET); if(usb_interrupt_level2 & BIT6) A_USB_STATUS_IN(); /* vUsb_Status_In() */ } if (usb_interrupt_level1 & BIT0) { usb_interrupt_level2 = ioread8_usb(ZM_INTR_SOURCE_0_OFFSET); /* refer to FUSB200, p 48, offset:21H, bit7 description, * should clear the command abort interrupt first!? */ if (usb_interrupt_level2 & BIT7) { /* Handle command abort */ io8_clr_usb(ZM_INTR_SOURCE_0_OFFSET, BIT7); A_PRINTF("![SOURCE_0] bit7 on\n\r"); } if (usb_interrupt_level2 & BIT1) A_USB_EP0_TX(); /* USB EP0 tx interrupt */ if (usb_interrupt_level2 & BIT2) A_USB_EP0_RX(); /* USB EP0 rx interrupt */ if (usb_interrupt_level2 & BIT0) { A_USB_EP0_SETUP(); /* vWriteUSBFakeData() */ } if (usb_interrupt_level2 & BIT3) { /* vUsb_ep0end */ eUsbCxCommand = CMD_VOID; iowrite8_usb(ZM_CX_CONFIG_STATUS_OFFSET, 0x01); } /* EP0 fail */ if (usb_interrupt_level2 & BIT4) iowrite8_usb(ZM_CX_CONFIG_STATUS_OFFSET, 0x04); if (eUsbCxFinishAction == ACT_STALL) { /* set CX_STL to stall Endpoint0 & * will also clear FIFO0 */ iowrite8_usb(ZM_CX_CONFIG_STATUS_OFFSET, 0x04); } else if (eUsbCxFinishAction == ACT_DONE) { /* set CX_DONE to indicate the transmistion * of control frame */ iowrite8_usb(ZM_CX_CONFIG_STATUS_OFFSET, 0x01); } eUsbCxFinishAction = ACT_IDLE; } if (usb_interrupt_level1 & BIT7) { usb_interrupt_level2 = ioread8_usb(ZM_INTR_SOURCE_7_OFFSET); #if 0 if (usb_interrupt_level2 & BIT7) vUsb_Data_Out0Byte(); if (usb_interrupt_level2 & BIT6) vUsb_Data_In0Byte(); #endif if (usb_interrupt_level2 & BIT1) { io8_clr_usb(ZM_INTR_SOURCE_7_OFFSET, BIT1); UsbChirpFinish = FALSE; A_PRINTF("!USB reset\n\r"); } if (usb_interrupt_level2 & BIT2) { /* TBD: the suspend resume code should put here, * Ryan, 07/18 * issue, jump back to rom code and what peripherals * should we reset here? */ _fw_usb_suspend_reboot(); } if (usb_interrupt_level2 & BIT3) { io8_clr_usb(ZM_INTR_SOURCE_7_OFFSET, BIT3); A_PRINTF("!USB resume\n\r"); } } } void _fw_usb_reset_fifo(void) { io8_set(0x100ae, 0x10); io8_set(0x100af, 0x10); /* disable ep3 int enable, so that resume back won't * send wdt magic pattern out!!! */ mUSB_STATUS_IN_INT_DISABLE(); /* update magic pattern to indicate this is a suspend * k2: MAGPIE_REG_RST_WDT_TIMER_CTRL_ADDR * magpie: MAGPIE_REG_RST_STATUS_ADDR */ iowrite32(MAGPIE_REG_RST_STATUS_ADDR, SUS_MAGIC_PATTERN); /* * Before USB suspend, USB DMA must be reset(refer to Otus) * Otus runs the following statements only * iowrite32( MAGPIE_REG_RST_PWDN_CTRL_ADDR, BIT0|BIT2 ); * iowrite32( MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0 ); * K2 must run the following statements additionally * reg_data = (A_UINT32 *)(USB_CTRL_BASE_ADDRESS + 0x118); * *reg_data = 0x00000000; * *reg_data = 0x00000001; * because of Hardware bug in K2 */ iowrite32_usb(ZM_SOC_USB_DMA_RESET_OFFSET, 0x0); /* reset both usb(bit2)/wlan(bit1) dma */ iowrite32(MAGPIE_REG_RST_PWDN_CTRL_ADDR, BIT2); io32_set(MAGPIE_REG_RST_PWDN_CTRL_ADDR, BIT0); iowrite32(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0); iowrite32_usb(ZM_SOC_USB_DMA_RESET_OFFSET, BIT0); /* MAC warem reset */ //reg_data = (uint32_t *)(K2_REG_MAC_BASE_ADDR + 0x7000); //*reg_data = 0x00000001; //A_DELAY_USECS(1); //*reg_data = 0x00000000; //while (*reg_data) ; A_PRINTF("\n change clock to 22 and go to suspend now!"); /* UART_SEL */ iowrite32(0x50040, 0x200 | 0 | (1 >> 1) << 12); A_UART_HWINIT((22*1000*1000), 19200); } #endif usb_api_magpie_patch.c000077500000000000000000000242451321570333100346370ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/hif/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include "usb_defs.h" #include "usb_type.h" #include "usb_pre.h" #include "usb_extr.h" #include "usb_std.h" #include "reg_defs.h" #include "athos_api.h" #include "usbfifo_api.h" #include "adf_os_io.h" #include "sys_cfg.h" #define measure_time 0 #define measure_time_pll 10000000 extern Action eUsbCxFinishAction; extern CommandType eUsbCxCommand; extern BOOLEAN UsbChirpFinish; extern USB_FIFO_CONFIG usbFifoConf; extern uint16_t *pu8DescriptorEX; extern uint16_t u16TxRxCounter; void zfTurnOffPower_patch(void); static void _fw_reset_dma_fifo(); static void _fw_restore_dma_fifo(); static void _fw_power_on(); static void _fw_power_off(); BOOLEAN bEepromExist = TRUE; BOOLEAN bJumptoFlash = FALSE; void _fw_usb_suspend_reboot() { /* reset usb/wlan dma */ _fw_reset_dma_fifo(); /* restore gpio setting and usb/wlan dma state */ _fw_restore_dma_fifo(); /* set clock to bypass mode - 40Mhz from XTAL */ iowrite32(MAGPIE_REG_CPU_PLL_BYPASS_ADDR, BIT0 | BIT4); A_DELAY_USECS(100); /* wait for stable */ iowrite32(MAGPIE_REG_CPU_PLL_ADDR, BIT16); A_DELAY_USECS(100); /* wait for stable */ A_UART_HWINIT((40*1000*1000), 19200); A_CLOCK_INIT(40); if (!bEepromExist) { /* jump to flash boot (eeprom data in flash) */ bJumptoFlash = TRUE; A_PRINTF("Jump to Flash BOOT\n"); app_start(); } else { A_PRINTF("receive the suspend command...\n"); /* reboot..... */ A_USB_JUMP_BOOT(); } } #define PCI_RC_RESET_BIT BIT6 #define PCI_RC_PHY_RESET_BIT BIT7 #define PCI_RC_PLL_RESET_BIT BIT8 #define PCI_RC_PHY_SHIFT_RESET_BIT BIT10 /* * -- urn_off_merlin -- * . values suggested from Lalit * */ static void turn_off_merlin() { volatile uint32_t default_data[9]; uint32_t i=0; if(1) { A_PRINTF("turn_off_merlin_ep_start ......\n"); A_DELAY_USECS(measure_time); default_data[0] = 0x9248fd00; default_data[1] = 0x24924924; default_data[2] = 0xa8000019; default_data[3] = 0x17160820; default_data[4] = 0x25980560; default_data[5] = 0xc1c00000; default_data[6] = 0x1aaabe40; default_data[7] = 0xbe105554; default_data[8] = 0x00043007; for(i=0; i<9; i++) { A_DELAY_USECS(10); iowrite32(0x10ff4040, default_data[i]); } A_DELAY_USECS(10); iowrite32(0x10ff4044, BIT0); A_PRINTF("turn_off_merlin_ep_end ......\n"); } } /* * -- turn_off_phy -- * * . write shift register to both pcie ep and rc * . */ static void turn_off_phy() { volatile uint32_t default_data[9]; uint32_t i=0; default_data[0] = 0x9248fd00; default_data[1] = 0x24924924; default_data[2] = 0xa8000019; default_data[3] = 0x17160820; default_data[4] = 0x25980560; default_data[5] = 0xc1c00000; default_data[6] = 0x1aaabe40; default_data[7] = 0xbe105554; default_data[8] = 0x00043007; for(i=0; i<9; i++) { // check for the done bit to be set while (1) { if (ioread32(0x40028) & BIT31) break; } A_DELAY_USECS(1); iowrite32(0x40024, default_data[i]); } iowrite32(0x40028, BIT0); } static void turn_off_phy_rc() { volatile uint32_t default_data[9]; uint32_t i=0; A_PRINTF("turn_off_phy_rc\n"); default_data[0] = 0x9248fd00; default_data[1] = 0x24924924; default_data[2] = 0xa8000019; default_data[3] = 0x13160820;//PwdClk1MHz=0 default_data[4] = 0x25980560; default_data[5] = 0xc1c00000; default_data[6] = 0x1aaabe40; default_data[7] = 0xbe105554; default_data[8] = 0x00043007; for(i=0; i<9; i++) { // check for the done bit to be set while (1) { if (ioread32(0x40028) & BIT31) break; } A_DELAY_USECS(1); iowrite32(0x40024, default_data[i]); } iowrite32(0x40028, BIT0); } volatile uint32_t gpio_func = 0x0; volatile uint32_t gpio = 0x0; /* * -- patch zfTurnOffPower -- * * . set suspend counter to non-zero value * . */ void zfTurnOffPower_patch(void) { A_PRINTF("+++ goto suspend ......\n"); /* setting the go suspend here, power down right away */ io32_set(0x10000, BIT3); A_DELAY_USECS(100); // TURN OFF ETH PLL _fw_power_off(); //32clk wait for External ETH PLL stable A_DELAY_USECS(100); iowrite32(0x52000, 0x70303); /* read back 0x703f7 */ iowrite32(0x52008, 0x0e91c); /* read back 0x1e948 */ io32_set(MAGPIE_REG_SUSPEND_ENABLE_ADDR, BIT0); // wake up, and turn on cpu, eth, pcie and usb pll _fw_power_on(); // restore gpio and other settings _fw_restore_dma_fifo(); /* clear suspend */ io32_clr(MAGPIE_REG_SUSPEND_ENABLE_ADDR, BIT0); io32_clr(0x52028, BIT8 | BIT12 | BIT16); } /* * -- patch zfResetUSBFIFO_patch -- * * . clear ep3/ep4 fifo * . set suspend magic pattern * . reset pcie ep phy * . reset pcie rc phy * . turn off pcie pll * . reset all pcie/gmac related registers * . reset usb dma */ void zfResetUSBFIFO_patch(void) { A_PRINTF("0x9808 0x%x ......\n", ioread32(0x10ff9808)); A_PRINTF("0x7890 0x%x ......\n", ioread32(0x10ff7890)); A_PRINTF("0x7890 0x%x ......\n", ioread32(0x10ff7890)); A_PRINTF("0x4088 0x%x ......\n", ioread32(0x10ff4088)); _fw_reset_dma_fifo(); } static void _fw_reset_dma_fifo() { io8_set(0x100ae, 0x10); io8_set(0x100af, 0x10); A_PRINTF("_fw_reset_dma_fifo\n"); // disable ep3 int enable, so that resume back won't send wdt magic pattern out!!! mUSB_STATUS_IN_INT_DISABLE(); /* update magic pattern to indicate this is a suspend */ iowrite32(WATCH_DOG_MAGIC_PATTERN_ADDR, SUS_MAGIC_PATTERN); A_PRINTF("org 0x4048 0x%x ......\n", ioread32(0x10ff4048)); A_PRINTF("org 0x404C 0x%x ......\n", ioread32(0x10ff404C)); A_PRINTF("org 0x4088 0x%x ......\n", ioread32(0x10ff4088)); /* 1010.1010.1010.0110.1010 for UB94 */ iowrite32(0x10ff4088, 0xaaa6a); iowrite32(0x10ff404C, 0x0); A_DELAY_USECS(1000); A_PRINTF("0x4048 0x%x ......\n", ioread32(0x10ff4048)); A_PRINTF("0x404C 0x%x ......\n", ioread32(0x10ff404C)); A_PRINTF("0x4088 0x%x ......\n", ioread32(0x10ff4088)); // turn off merlin turn_off_merlin(); // pcie ep A_PRINTF("turn_off_magpie_ep_start ......\n"); A_DELAY_USECS(measure_time); io32_set(0x40040, BIT0 | BIT1); turn_off_phy(); io32_clr(0x40040, BIT0 | BIT1); A_PRINTF("turn_off_magpie_ep_end ......\n"); // pcie rc A_PRINTF("turn_off_magpie_rc_start ......\n"); A_DELAY_USECS(measure_time); io32_clr(0x40040, BIT0); turn_off_phy_rc(); A_PRINTF("turn_off_magpie_rc_end ......down\n"); A_DELAY_USECS(measure_time); A_PRINTF("0x4001C %p ......\n", ioread32(0x4001c)); A_PRINTF("0x40040 %p ......\n", ioread32(0x40040)); /* turn off pcie_pll - power down (bit16) */ A_PRINTF(" before pwd PCIE PLL CFG:0x5601C: 0x%08x\n", ioread32(0x5601C)); io32_set(0x5601C, BIT18); A_PRINTF(" after pwd PCIE PLL CFG:0x5601C: 0x%08x\n", ioread32(0x5601C)); /* set everything to reset state?, requested by Oligo */ io32_set(0x50010, BIT13 | BIT12 | BIT11 | BIT9 | BIT7 | BIT6); iowrite32(0x5C000, 0); A_DELAY_USECS(10); /* reset usb DMA controller */ iowrite32_usb(ZM_SOC_USB_DMA_RESET_OFFSET, 0x0); io32_set(0x50010, BIT4); A_DELAY_USECS(5); io32_clr(0x50010, BIT4); iowrite32_usb(ZM_SOC_USB_DMA_RESET_OFFSET, BIT0); } static void _fw_power_off() { /* * 1. set CPU bypass * 2. turn off CPU PLL * 3. turn off ETH PLL * 4. disable ETH PLL bypass and update * 4.1 set suspend timeout * 5. set SUSPEND_ENABLE */ iowrite32(MAGPIE_REG_CPU_PLL_BYPASS_ADDR, BIT0 | BIT4); A_DELAY_USECS(100); // wait for stable iowrite32(MAGPIE_REG_CPU_PLL_ADDR, BIT16); A_DELAY_USECS(100); // wait for stable A_UART_HWINIT((40*1000*1000), 19200); A_CLOCK_INIT(40); io32_set(MAGPIE_REG_ETH_PLL_ADDR, BIT16); io32_set(MAGPIE_REG_ETH_PLL_BYPASS_ADDR, BIT4 | BIT0); io32_set(MAGPIE_REG_SUSPEND_ENABLE_ADDR, 0x10 << 8); } static void _fw_power_on() { /* * 1. turn on CPU PLL * 2. disable CPU bypass * 3. turn on ETH PLL * 4. disable ETH PLL bypass and update * 5. turn on pcie pll */ io32_clr(MAGPIE_REG_ETH_PLL_ADDR, BIT16); /* deassert eth_pll bypass mode and trigger update bit */ io32_clr(MAGPIE_REG_ETH_PLL_BYPASS_ADDR, BIT4 | BIT0); } static void _fw_restore_dma_fifo(void) { io32_clr(0x5601C, BIT18); /* reset pcie_rc shift */ io32_clr(0x50010, BIT10 | BIT8 | BIT7); A_DELAY_USECS(1); io32_set(0x50010, BIT10 | BIT8 | BIT7); /* reset pci_rc phy */ io32_set(MAGPIE_REG_RST_RESET_ADDR, PCI_RC_PHY_SHIFT_RESET_BIT | PCI_RC_PLL_RESET_BIT | PCI_RC_PHY_RESET_BIT | PCI_RC_RESET_BIT); A_DELAY_USECS(20); // enable dma swap function MAGPIE_REG_USB_RX0_SWAP_DATA = 0x1; MAGPIE_REG_USB_TX0_SWAP_DATA = 0x1; MAGPIE_REG_USB_RX1_SWAP_DATA = 0x1; MAGPIE_REG_USB_RX2_SWAP_DATA = 0x1; } usb_api_main_patch.c000066400000000000000000000303401321570333100343070ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/hif/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * Copyright (c) 2016 Oleksij Rempel * * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* shared patches for k2 and magpie */ #include #include #include "usb_defs.h" #include "usb_type.h" #include "usb_pre.h" #include "usb_extr.h" #include "usb_std.h" #include "reg_defs.h" #include "athos_api.h" #include "usbfifo_api.h" #include "adf_os_io.h" #include "sys_cfg.h" #define USB_EP4_MAX_PKT_SIZE bUSB_EP_MAX_PKT_SIZE_64 #define USB_EP3_MAX_PKT_SIZE bUSB_EP_MAX_PKT_SIZE_64 extern USB_FIFO_CONFIG usbFifoConf; extern Action eUsbCxFinishAction; extern void _fw_usb_suspend_reboot(); typedef void (* USBFIFO_recv_command)(VBUF *cmd); USBFIFO_recv_command m_origUsbfifoRecvCmd = NULL; void _fw_usbfifo_recv_command(VBUF *buf) { uint8_t *cmd_data; uint32_t tmp; cmd_data = (uint8_t *)(buf->desc_list->buf_addr + buf->desc_list->data_offset); tmp = *((uint32_t *)cmd_data); if (tmp == 0xFFFFFFFF) _fw_usb_suspend_reboot(); else m_origUsbfifoRecvCmd(buf); } void _fw_usbfifo_init(USB_FIFO_CONFIG *pConfig) { m_origUsbfifoRecvCmd = pConfig->recv_command; usbFifoConf.get_command_buf = pConfig->get_command_buf; usbFifoConf.recv_command = _fw_usbfifo_recv_command; usbFifoConf.get_event_buf = pConfig->get_event_buf; usbFifoConf.send_event_done = pConfig->send_event_done; } void cold_reboot(void) { A_PRINTF("Cold reboot initiated."); #if defined(PROJECT_MAGPIE) iowrite32(WATCH_DOG_MAGIC_PATTERN_ADDR, 0); #elif defined(PROJECT_K2) iowrite32(MAGPIE_REG_RST_STATUS_ADDR, 0); #endif /* #if defined(PROJECT_MAGPIE) */ A_USB_JUMP_BOOT(); } /* * support more than 64 bytes command on ep3 */ void usb_status_in_patch(void) { uint16_t count; uint16_t remainder; uint16_t reg_buf_len; static uint16_t buf_len; static VBUF *evntbuf = NULL; static volatile uint32_t *regaddr; static BOOLEAN cmd_is_new = TRUE; BOOLEAN cmd_end = FALSE; if (cmd_is_new) { evntbuf = usbFifoConf.get_event_buf(); if (evntbuf != NULL) { regaddr = (uint32_t *)VBUF_GET_DATA_ADDR(evntbuf); buf_len = evntbuf->buf_length; } else { mUSB_STATUS_IN_INT_DISABLE(); return; } cmd_is_new = FALSE; } if (buf_len > USB_EP3_MAX_PKT_SIZE) { reg_buf_len = USB_EP3_MAX_PKT_SIZE; buf_len -= USB_EP3_MAX_PKT_SIZE; } /* TODO: 64 bytes... * controller supposed will take care of zero-length? */ else { reg_buf_len = buf_len; cmd_end = TRUE; } /* INT use EP3 */ for (count = 0; count < (reg_buf_len / 4); count++) { iowrite32_usb(ZM_EP3_DATA_OFFSET, *regaddr); regaddr++; } remainder = reg_buf_len % 4; if (remainder) { switch(remainder) { case 3: iowrite32_usb(ZM_CBUS_FIFO_SIZE_OFFSET, 0x7); break; case 2: iowrite32_usb(ZM_CBUS_FIFO_SIZE_OFFSET, 0x3); break; case 1: iowrite32_usb(ZM_CBUS_FIFO_SIZE_OFFSET, 0x1); break; } iowrite32_usb(ZM_EP3_DATA_OFFSET, *regaddr); /* Restore CBus FIFO size to word size */ iowrite32_usb(ZM_CBUS_FIFO_SIZE_OFFSET, 0xF); } mUSB_EP3_XFER_DONE(); if (evntbuf != NULL && cmd_end) { usbFifoConf.send_event_done(evntbuf); cmd_is_new = TRUE; } } /* * support more than 64 bytes command on ep4 */ void usb_reg_out_patch(void) { uint16_t usbfifolen; uint16_t ii; uint32_t ep4_data; static volatile uint32_t *regaddr; static uint16_t cmd_len; static VBUF *buf; BOOLEAN cmd_is_last = FALSE; static BOOLEAN cmd_is_new = TRUE; /* get the size of this transcation */ usbfifolen = ioread8_usb(ZM_EP4_BYTE_COUNT_LOW_OFFSET); if (usbfifolen > USB_EP4_MAX_PKT_SIZE) { A_PRINTF("EP4 FIFO Bug? Buffer is too big: %x\n", usbfifolen); cold_reboot(); } /* check is command is new */ if(cmd_is_new) { buf = usbFifoConf.get_command_buf(); cmd_len = 0; if(!buf) { A_PRINTF("%s: Filed to get new buffer.\n", __func__); goto err; } /* copy free, assignment buffer of the address */ regaddr = (uint32_t *)buf->desc_list->buf_addr; cmd_is_new = FALSE; } /* just in case, suppose should not happen */ if(!buf) goto err; /* if size is smaller, this is the last command! * zero-length supposed should be set through 0x27/bit7->0x19/bit4, not here */ if(usbfifolen < USB_EP4_MAX_PKT_SIZE) cmd_is_last = TRUE; /* accumulate the size */ cmd_len += usbfifolen; if (cmd_len > buf->desc_list->buf_size) { A_PRINTF("%s: Data length on EP4 FIFO is bigger as " "allocated buffer data! Drop it!\n", __func__); goto err; } /* round it to alignment */ if(usbfifolen % 4) usbfifolen = (usbfifolen >> 2) + 1; else usbfifolen = usbfifolen >> 2; /* retrieve the data from fifo */ for(ii = 0; ii < usbfifolen; ii++) { /* read fifo data out */ ep4_data = ioread32_usb(ZM_EP4_DATA_OFFSET); *regaddr = ep4_data; regaddr++; } /* if this is the last command, callback to HTC */ if (cmd_is_last) { buf->desc_list->next_desc = NULL; buf->desc_list->data_offset = 0; buf->desc_list->data_size = cmd_len; buf->desc_list->control = 0; buf->next_buf = NULL; buf->buf_length = cmd_len; usbFifoConf.recv_command(buf); cmd_is_new = TRUE; } goto done; err: /* we might get no command buffer here? * but if we return here, the ep4 fifo will be lock out, * so that we still read them out but just drop it? */ for(ii = 0; ii < usbfifolen; ii++) ep4_data = ioread32_usb(ZM_EP4_DATA_OFFSET); done: /* mUSB_STATUS_IN_INT_ENABLE(); */ ; } /* * usb1.1 ep6 fix * TODO: * - theoretically ep6 configured same way as ep1 * so, if there are some problems we should have it * there too. * - do we really need support usb1.1? */ extern uint16_t u8UsbConfigValue; extern uint16_t u8UsbInterfaceValue; extern uint16_t u8UsbInterfaceAlternateSetting; extern SetupPacket ControlCmd; extern void vUsbClrEPx(void); #undef FS_C1_I0_A0_EP_NUMBER #define FS_C1_I0_A0_EP_NUMBER 6 #define FS_C1_I0_A0_EP6_BLKSIZE BLK512BYTE #define FS_C1_I0_A0_EP6_BLKNO DOUBLE_BLK #define FS_C1_I0_A0_EP6_DIRECTION DIRECTION_OUT #define FS_C1_I0_A0_EP6_TYPE TF_TYPE_BULK #define FS_C1_I0_A0_EP6_MAX_PACKET 0x0040 #define FS_C1_I0_A0_EP6_bInterval 0 /* EP6 */ #define FS_C1_I0_A0_EP6_FIFO_START \ (FS_C1_I0_A0_EP5_FIFO_START + FS_C1_I0_A0_EP5_FIFO_NO) #define FS_C1_I0_A0_EP6_FIFO_NO \ (FS_C1_I0_A0_EP6_BLKNO * FS_C1_I0_A0_EP6_BLKSIZE) #define FS_C1_I0_A0_EP6_FIFO_CONFIG \ (0x80 | ((FS_C1_I0_A0_EP6_BLKSIZE - 1) << 4) | \ ((FS_C1_I0_A0_EP6_BLKNO - 1) << 2) | FS_C1_I0_A0_EP6_TYPE) #define FS_C1_I0_A0_EP6_FIFO_MAP \ (((1 - FS_C1_I0_A0_EP6_DIRECTION) << 4) | EP6) #define FS_C1_I0_A0_EP6_MAP \ (FS_C1_I0_A0_EP6_FIFO_START | (FS_C1_I0_A0_EP6_FIFO_START << 4) | \ (MASK_F0 >> (4*FS_C1_I0_A0_EP6_DIRECTION))) void vUSBFIFO_EP6Cfg_FS_patch(void) { #if (FS_C1_I0_A0_EP_NUMBER >= 6) int i; /* EP0X06 */ mUsbEPMap(EP6, FS_C1_I0_A0_EP6_MAP); mUsbFIFOMap(FS_C1_I0_A0_EP6_FIFO_START, FS_C1_I0_A0_EP6_FIFO_MAP); mUsbFIFOConfig(FS_C1_I0_A0_EP6_FIFO_START, FS_C1_I0_A0_EP6_FIFO_CONFIG); for(i = FS_C1_I0_A0_EP6_FIFO_START + 1 ; i < FS_C1_I0_A0_EP6_FIFO_START + FS_C1_I0_A0_EP6_FIFO_NO ; i ++) { mUsbFIFOConfig(i, (FS_C1_I0_A0_EP6_FIFO_CONFIG & (~BIT7)) ); } mUsbEPMxPtSzHigh(EP6, FS_C1_I0_A0_EP6_DIRECTION, (FS_C1_I0_A0_EP6_MAX_PACKET & 0x7ff)); mUsbEPMxPtSzLow(EP6, FS_C1_I0_A0_EP6_DIRECTION, (FS_C1_I0_A0_EP6_MAX_PACKET & 0x7ff)); mUsbEPinHighBandSet(EP6, FS_C1_I0_A0_EP6_DIRECTION, FS_C1_I0_A0_EP6_MAX_PACKET); #endif } void vUsbFIFO_EPxCfg_FS_patch(void) { switch (u8UsbConfigValue) { #if (FS_CONFIGURATION_NUMBER >= 1) /* Configuration 0X01 */ case 0X01: switch (u8UsbInterfaceValue) { #if (FS_C1_INTERFACE_NUMBER >= 1) /* Interface 0 */ case 0: switch (u8UsbInterfaceAlternateSetting) { #if (FS_C1_I0_ALT_NUMBER >= 1) /* AlternateSetting 0 */ case 0: /* snapped.... */ /* patch up this ep6_fs config */ vUSBFIFO_EP6Cfg_FS_patch(); break; #endif default: break; } break; #endif default: break; } break; #endif default: break; } /* mCHECK_STACK(); */ } BOOLEAN bSet_configuration_patch(void) { /* do some defaul configuration */ bSet_configuration(); /* overwrite defaul FIFO configuration for FullSpeed USB */ if ((mLOW_BYTE(mDEV_REQ_VALUE()) != 0) && !mUsbHighSpeedST()) vUsbFIFO_EPxCfg_FS_patch(); eUsbCxFinishAction = ACT_DONE; return TRUE; } extern BOOLEAN bStandardCommand(void); BOOLEAN bStandardCommand_patch(void) { if (mDEV_REQ_REQ() == USB_SET_CONFIGURATION) { A_USB_SET_CONFIG(); #if ENABLE_SWAP_DATA_MODE /* SWAP FUNCTION should be enabled while DMA engine * is not working, the best place to enable it * is before we trigger the DMA */ MAGPIE_REG_USB_RX0_SWAP_DATA = 0x1; MAGPIE_REG_USB_TX0_SWAP_DATA = 0x1; #if SYSTEM_MODULE_HP_EP5 MAGPIE_REG_USB_RX1_SWAP_DATA = 0x1; #endif #if SYSTEM_MODULE_HP_EP6 MAGPIE_REG_USB_RX2_SWAP_DATA = 0x1; #endif #endif /* ENABLE_SWAP_DATA_MODE */ return TRUE; } else return bStandardCommand(); } /* * usb descriptor patch */ extern uint16_t *u8ConfigDescriptorEX; extern uint16_t *pu8DescriptorEX; extern uint16_t u16TxRxCounter; extern SetupPacket ControlCmd; extern uint16_t *u8UsbDeviceDescriptor; extern BOOLEAN bGet_descriptor(void); uint16_t ConfigDescriptorPatch[30]; uint16_t UsbDeviceDescriptorPatch[9]; #define BCD_DEVICE_OFFSET 6 #define BCD_DEVICE_FW_SIGNATURE 0xffff #define VENDOR_ID_OFFSET 4 #define PRODUCT_ID_OFFSET 5 #define EP3_TRANSFER_TYPE_OFFSET 17 #define EP3_INT_INTERVAL 19 #define EP4_TRANSFER_TYPE_OFFSET 21 #define EP4_INT_INTERVAL 22 BOOLEAN bGet_descriptor_patch(void) { if (mDEV_REQ_VALUE_HIGH() == 1) { uint8_t *p = (uint8_t *)u8UsbDeviceDescriptor; /* Copy Usb Device Descriptor */ ath_hal_memcpy(UsbDeviceDescriptorPatch, p, sizeof(UsbDeviceDescriptorPatch)); /* Change bcdDevice. we need it to detect if FW * was uploaded. */ UsbDeviceDescriptorPatch[BCD_DEVICE_OFFSET] = BCD_DEVICE_FW_SIGNATURE; pu8DescriptorEX = UsbDeviceDescriptorPatch; u16TxRxCounter = mTABLE_LEN(u8UsbDeviceDescriptor[0]); if (u16TxRxCounter > mDEV_REQ_LENGTH()) u16TxRxCounter = mDEV_REQ_LENGTH(); A_USB_EP0_TX_DATA(); return TRUE; } else if (mDEV_REQ_VALUE_HIGH() == 2) { uint8_t *p = (uint8_t *)u8ConfigDescriptorEX; /* Copy ConfigDescriptor */ ath_hal_memcpy(ConfigDescriptorPatch, p, sizeof(ConfigDescriptorPatch)); /* place holder for EPx patches */ if (mDEV_REQ_VALUE_LOW() == 0) { /* configuration no: 0 */ pu8DescriptorEX = ConfigDescriptorPatch; u16TxRxCounter = ConfigDescriptorPatch[1]; } else return FALSE; if (u16TxRxCounter > mDEV_REQ_LENGTH()) u16TxRxCounter = mDEV_REQ_LENGTH(); A_USB_EP0_TX_DATA(); return TRUE; } else return bGet_descriptor(); } open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/htc/000077500000000000000000000000001321570333100304255ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/htc/htc.c000077500000000000000000000730131321570333100313560ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * @File: * * @Abstract: host target communications * * @Notes: */ #include #include #include #include #include #include #include #include "htc_internal.h" #define A_UNCACHED_ADDR(addr) addr /* prototypes */ LOCAL void HTCControlSvcProcessMsg(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t hdr_buf, adf_nbuf_t pBuffers, void *arg); LOCAL void HTCControlSvcProcessSendComplete(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t pBuffers, void *arg); LOCAL void HTCMsgRecvHandler(adf_nbuf_t hdr_buf, adf_nbuf_t buf, void *context); LOCAL void HTCSendDoneHandler(adf_nbuf_t buf, void *context); LOCAL void HTCFreeMsgBuffer(HTC_CONTEXT *pHTC, adf_nbuf_t pBuffer); LOCAL adf_nbuf_t HTCAllocMsgBuffer(HTC_CONTEXT *pHTC); LOCAL void HTCCheckAndSendCreditReport(HTC_CONTEXT *pHTC, A_UINT32 EpMask, HTC_ENDPOINT *pEndpoint, HTC_ENDPOINT_ID Id); LOCAL void AdjustCreditThreshold(HTC_ENDPOINT *pEndpoint); LOCAL void HTC_AssembleBuffers(HTC_CONTEXT *pHTC, int Count, int Size); LOCAL htc_handle_t _HTC_Init(/*A_UINT32 dataAddr,*/ HTC_SETUP_COMPLETE_CB SetupComplete, HTC_CONFIG *pConfig); LOCAL void _HTC_RegisterService(htc_handle_t handle, HTC_SERVICE *pService); LOCAL void _HTC_Ready(htc_handle_t handle); LOCAL void ReturnBuffers(htc_handle_t htcHandle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_t pBuffers, A_BOOL sendCreditFlag); LOCAL void _HTC_ReturnBuffers(htc_handle_t handle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_t pBuffers); LOCAL void _HTC_ReturnBuffersList(htc_handle_t htcHandle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_queue_t bufHead); LOCAL void _HTC_SendMsg(htc_handle_t handle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_t pBuffers); void _HTC_PauseRecv(HTC_ENDPOINT_ID EndpointID); void _HTC_ResumeRecv(HTC_ENDPOINT_ID EndpointID); LOCAL void HTCProcessConnectMsg(HTC_CONTEXT *pHTC, HTC_CONNECT_SERVICE_MSG *pMsg); LOCAL void HTCProcessConfigPipeMsg(HTC_CONTEXT *pHTC, HTC_CONFIG_PIPE_MSG *pMsg); LOCAL void RedistributeCredit(adf_nbuf_t buf, int toPipeId); LOCAL void _HTC_Shutdown(htc_handle_t htcHandle); /* macro to check if the service wants to prevent credit dribbling by using a dynamic threshold */ #define CHECK_AND_ADJUST_CREDIT_THRESHOLD(pEndpoint) \ if ((pEndpoint)->ConnectionFlags & HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE) { \ AdjustCreditThreshold((pEndpoint)); \ } LOCAL void HTC_AssembleBuffers(HTC_CONTEXT *pHTC, int Count, int Size) { BUF_Pool_create_pool(pHTC->PoolHandle, POOL_ID_HTC_CONTROL, Count, Size); } LOCAL htc_handle_t _HTC_Init(HTC_SETUP_COMPLETE_CB SetupComplete, HTC_CONFIG *pConfig) { HIF_CALLBACK hifCBConfig; HTC_CONTEXT *pHTC; pHTC = (HTC_CONTEXT *)adf_os_mem_alloc(sizeof(HTC_CONTEXT)); adf_os_mem_zero(pHTC, sizeof(HTC_CONTEXT)); pHTC->OSHandle = pConfig->OSHandle; pHTC->PoolHandle = pConfig->PoolHandle; pHTC->hifHandle = pConfig->HIFHandle; hifCBConfig.send_buf_done = A_INDIR(htc._HTC_SendDoneHandler); hifCBConfig.recv_buf = A_INDIR(htc._HTC_MsgRecvHandler); hifCBConfig.context = pHTC; /* initialize hardware layer */ HIF_register_callback(pConfig->HIFHandle, &hifCBConfig); /* see if the host wants us to override the number of ctrl buffers */ pHTC->NumBuffersForCreditRpts = 0; if (0 == pHTC->NumBuffersForCreditRpts) { /* nothing to override, simply set default */ pHTC->NumBuffersForCreditRpts = HTC_DEFAULT_NUM_CTRL_BUFFERS; } pHTC->MaxEpPendingCreditRpts = 0; if (0 == pHTC->MaxEpPendingCreditRpts) { pHTC->MaxEpPendingCreditRpts = HTC_DEFAULT_MAX_EP_PENDING_CREDIT_REPORTS; } /* calculate the total allocation size based on the number of credit report buffers */ pHTC->CtrlBufferAllocSize = MIN_CREDIT_BUFFER_ALLOC_SIZE * pHTC->NumBuffersForCreditRpts; /* we need at least enough buffer space for 1 ctrl message */ pHTC->CtrlBufferAllocSize = A_MAX(pHTC->CtrlBufferAllocSize,MAX_HTC_SETUP_MSG_SIZE); /* save the size of each buffer/credit we will receive */ pHTC->RecvBufferSize = pConfig->CreditSize; //RecvBufferSize; pHTC->TotalCredits = pConfig->CreditNumber; pHTC->TotalCreditsAssigned = 0; /* setup the pseudo service that handles HTC control messages */ pHTC->HTCControlService.ProcessRecvMsg = A_INDIR(htc._HTC_ControlSvcProcessMsg); pHTC->HTCControlService.ProcessSendBufferComplete = A_INDIR(htc._HTC_ControlSvcProcessSendComplete); pHTC->HTCControlService.TrailerSpcCheckLimit = HTC_CTRL_BUFFER_CHECK_SIZE; pHTC->HTCControlService.MaxSvcMsgSize = MAX_HTC_SETUP_MSG_SIZE; pHTC->HTCControlService.ServiceCtx = pHTC; /* automatically register this pseudo service to endpoint 1 */ pHTC->Endpoints[ENDPOINT0].pService = &pHTC->HTCControlService; HIF_get_default_pipe(pHTC->hifHandle, &pHTC->Endpoints[ENDPOINT0].UpLinkPipeID, &pHTC->Endpoints[ENDPOINT0].DownLinkPipeID); /* Initialize control pipe so we could receive the HTC control packets */ // @TODO: msg size! HIF_config_pipe(pHTC->hifHandle, pHTC->Endpoints[ENDPOINT0].UpLinkPipeID, 1); /* set the first free endpoint */ pHTC->CurrentEpIndex = ENDPOINT1; pHTC->SetupCompleteCb = SetupComplete; /* setup buffers for just the setup phase, we only need 1 buffer to handle * setup */ HTC_AssembleBuffers(pHTC, 4, MAX_HTC_SETUP_MSG_SIZE); /* start hardware layer so that we can queue buffers */ HIF_start(pHTC->hifHandle); return pHTC; } LOCAL void _HTC_Shutdown(htc_handle_t htcHandle) { HTC_CONTEXT *pHTC = (HTC_CONTEXT *)htcHandle; adf_os_mem_free(pHTC); } LOCAL void _HTC_RegisterService(htc_handle_t htcHandle, HTC_SERVICE *pService) { HTC_CONTEXT *pHTC = (HTC_CONTEXT *)htcHandle; /* add it to the list */ pService->pNext = pHTC->pServiceList; pHTC->pServiceList = pService; } LOCAL void _HTC_Ready(htc_handle_t htcHandle) { adf_nbuf_t pBuffer; HTC_READY_MSG *pReady; a_uint8_t *addr; HTC_CONTEXT *pHTC = (HTC_CONTEXT *)htcHandle; pBuffer = HTCAllocMsgBuffer(pHTC); /* an optimization... the header length is chosen to * be aligned on a 16 bit bounday, the fields in the message are designed to * be aligned */ addr = adf_nbuf_put_tail(pBuffer, sizeof(HTC_READY_MSG)); pReady = (HTC_READY_MSG *)addr; A_MEMZERO(pReady,sizeof(HTC_READY_MSG)); pReady->MessageID = adf_os_htons(HTC_MSG_READY_ID); pReady->CreditSize = adf_os_htons((A_UINT16)pHTC->RecvBufferSize); pReady->CreditCount = adf_os_htons((A_UINT16)pHTC->TotalCredits); pReady->MaxEndpoints = ENDPOINT_MAX; /* send out the message */ HTC_SendMsg(pHTC, ENDPOINT0, pBuffer); /* now we need to wait for service connection requests */ } LOCAL void ReturnBuffers(htc_handle_t htcHandle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_t pBuffers, A_BOOL sendCreditFlag) { int nbufs = 1; HTC_CONTEXT *pHTC = (HTC_CONTEXT *)htcHandle; /* supply some head-room again */ adf_nbuf_push_head(pBuffers, HTC_HDR_LENGTH); /* enqueue all buffers to the single mailbox */ HIF_return_recv_buf(pHTC->hifHandle, pHTC->Endpoints[EndpointID].UpLinkPipeID, pBuffers); if (pHTC->StateFlags & HTC_STATE_SETUP_COMPLETE) { A_UINT32 epCreditMask = (1 << EndpointID); /* we are running normally */ /* update pending credit counts with the number of buffers that were added */ pHTC->Endpoints[EndpointID].CreditsToReturn += (A_INT16)nbufs; pHTC->Endpoints[EndpointID].CreditsConsumed -= (A_INT16)nbufs; /* update bit map that this endpoint has non-zero credits */ pHTC->EpCreditPendingMap |= epCreditMask; if (sendCreditFlag) { HTCCheckAndSendCreditReport(pHTC, epCreditMask,&pHTC->Endpoints[EndpointID],EndpointID); } } else { /* we have not started yet so all return operations are simply adding buffers * to the interface at startup, so we can keep track of how many total * credits we get */ /* update global count that will be returned to the host */ pHTC->TotalCredits += nbufs; } } LOCAL void _HTC_ReturnBuffersList(htc_handle_t htcHandle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_queue_t bufHead) { HTC_CONTEXT *pHTC = (HTC_CONTEXT *)htcHandle; adf_nbuf_t netbuf, tmpNbuf; /* retrieve each nbuf in the queue */ netbuf = adf_nbuf_queue_first(&bufHead); while (netbuf) { tmpNbuf = netbuf; netbuf = adf_nbuf_queue_next(netbuf); ReturnBuffers(htcHandle, EndpointID, tmpNbuf, FALSE); } HTCCheckAndSendCreditReport(pHTC, (1 << EndpointID),&pHTC->Endpoints[EndpointID],EndpointID); } LOCAL void _HTC_ReturnBuffers(htc_handle_t htcHandle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_t pBuffers) { ReturnBuffers(htcHandle, EndpointID, pBuffers, TRUE); } LOCAL void _HTC_SendMsg(htc_handle_t htcHandle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_t pBuffers) { HTC_FRAME_HDR *pHTCHdr; int totsz; HTC_CONTEXT *pHTC = (HTC_CONTEXT *)htcHandle; HTC_BUF_CONTEXT *ctx; ctx = (HTC_BUF_CONTEXT *)adf_nbuf_get_priv(pBuffers); /* init total size (this does not include the space we will put in for the HTC header) */ totsz = adf_nbuf_len(pBuffers); /* the first buffer stores the header */ /* back up buffer by a header size when we pass it down, by agreed upon convention the caller * points the buffer to it's payload and leaves head room for the HTC header * Note: in HTCSendDoneHandler(), we undo this so that the caller get's it's buffer * back untainted */ pHTCHdr = (HTC_FRAME_HDR *)adf_nbuf_push_head(pBuffers, HTC_HDR_LENGTH); /* flag that this is the header buffer that was modified */ ctx->htc_flags |= HTC_FLAGS_BUF_HDR; /* mark where this buffer came from */ ctx->end_point = EndpointID; /* the header start is ALWAYS aligned since we DMA it directly */ /* set some fields, the rest of them will be filled below when we check for * trailer space */ pHTCHdr->Flags = 0; pHTCHdr->EndpointID = EndpointID; /* check opportunistically if we can return any reports via a trailer */ do { int room,i,totalReportBytes; A_UINT32 creditsPendingMap, compareMask; HTC_CREDIT_REPORT *pCreditRpt; HTC_RECORD_HDR *pRecHdr; int pipeMaxLen; A_UINT32 roomForPipeMaxLen; /* figure out how much room the last buffer can spare */ pipeMaxLen = HIF_get_max_msg_len(pHTC->hifHandle, pHTC->Endpoints[EndpointID].DownLinkPipeID); roomForPipeMaxLen = pipeMaxLen - adf_nbuf_headroom(pBuffers) - adf_nbuf_len(pBuffers); if ( roomForPipeMaxLen < 0 ) { roomForPipeMaxLen = 0; } room = adf_os_min( adf_nbuf_tailroom(pBuffers), roomForPipeMaxLen); if (room < (int)(sizeof(HTC_CREDIT_REPORT) + sizeof(HTC_RECORD_HDR))) { /* no room for any reports */ break; } /* note, a record header only has 8 bit fields, so this is safe. * we need an uncached pointer here too */ totalReportBytes = 0; /* get a copy */ creditsPendingMap = pHTC->EpCreditPendingMap; /* test pending map to see if we can send a report , if any * credits are available, we might as well send them on the * unused space in the buffer */ if (creditsPendingMap) { pRecHdr = (HTC_RECORD_HDR *)adf_nbuf_put_tail(pBuffers, sizeof(HTC_RECORD_HDR)); /* set the ID, the length will be updated with the number of credit reports we * can fit (see below) */ pRecHdr->RecordID = HTC_RECORD_CREDITS; pRecHdr->Length = 0; /* the credit report follows the record header */ totalReportBytes += sizeof(HTC_RECORD_HDR); room -= sizeof(HTC_RECORD_HDR); /* walkthrough pending credits map and build the records */ for (i = 0; (creditsPendingMap != 0) && (room >= (int)sizeof(HTC_CREDIT_REPORT)); i++) { compareMask = (1 << i); if (compareMask & creditsPendingMap) { pCreditRpt = (HTC_CREDIT_REPORT *)adf_nbuf_put_tail(pBuffers, sizeof(HTC_CREDIT_REPORT)); /* clear pending mask, we are going to return all these credits */ creditsPendingMap &= ~(compareMask); /* add this record */ pCreditRpt->EndpointID = i; pCreditRpt->Credits = (A_UINT8)pHTC->Endpoints[i].CreditsToReturn; /* remove pending credits, we always send deltas */ pHTC->Endpoints[i].CreditsToReturn = 0; /* adjust new threshold for this endpoint if needed */ CHECK_AND_ADJUST_CREDIT_THRESHOLD(&pHTC->Endpoints[i]); /* update this record length */ pRecHdr->Length += sizeof(HTC_CREDIT_REPORT); room -= sizeof(HTC_CREDIT_REPORT); totalReportBytes += sizeof(HTC_CREDIT_REPORT); if ( room < sizeof(HTC_CREDIT_REPORT) ) { break; } } } /* update new pending credits map */ pHTC->EpCreditPendingMap = creditsPendingMap; } if (totalReportBytes <= 0) { break; } /* must fit into a byte, this should never actually happen since * the maximum possible number of endpoints is 32. * The trailer can have at most 1 credit record with up to 32 reports in the record. * The trailer can have at most 1 lookahead record with only 1 lookahead report in the record. */ /* set header option bytes */ pHTCHdr->ControlBytes[0] = totalReportBytes; /* HTC frame contains a trailer */ pHTCHdr->Flags |= HTC_FLAGS_RECV_TRAILER; /* increment total size by the reports we added */ totsz += totalReportBytes; /* adjust the last buffer we used for adding on the trailer */ } while (FALSE); if (totsz == 0) { } /* set length for message (this includes any reports that were added above) */ pHTCHdr->PayloadLen = adf_os_htons(totsz); HIF_send_buffer(pHTC->hifHandle, pHTC->Endpoints[EndpointID].DownLinkPipeID, pBuffers); } void _HTC_PauseRecv(HTC_ENDPOINT_ID EndpointID) { } void _HTC_ResumeRecv(HTC_ENDPOINT_ID EndpointID) { } int _HTC_GetReservedHeadroom(htc_handle_t htcHandle) { HTC_CONTEXT *pHTC = (HTC_CONTEXT *)htcHandle; return HTC_HDR_LENGTH + HIF_get_reserved_headroom(pHTC->hifHandle); } void htc_module_install(struct htc_apis *pAPIs) { pAPIs->_HTC_Init = _HTC_Init; pAPIs->_HTC_ReturnBuffers = _HTC_ReturnBuffers; pAPIs->_HTC_ReturnBuffersList = _HTC_ReturnBuffersList; pAPIs->_HTC_Ready = _HTC_Ready; pAPIs->_HTC_RegisterService = _HTC_RegisterService; pAPIs->_HTC_SendMsg = _HTC_SendMsg; pAPIs->_HTC_Shutdown = _HTC_Shutdown; pAPIs->_HTC_GetReservedHeadroom = _HTC_GetReservedHeadroom; pAPIs->_HTC_MsgRecvHandler = HTCMsgRecvHandler; pAPIs->_HTC_SendDoneHandler = HTCSendDoneHandler; pAPIs->_HTC_ControlSvcProcessMsg = HTCControlSvcProcessMsg; pAPIs->_HTC_ControlSvcProcessSendComplete = HTCControlSvcProcessSendComplete; } /* free message to the free list */ LOCAL void HTCFreeMsgBuffer(HTC_CONTEXT *pHTC, adf_nbuf_t buf) { BUF_Pool_free_buf(pHTC->PoolHandle, POOL_ID_HTC_CONTROL, buf); } /* HTC control message allocator (also used for empty frames to send trailer options) */ LOCAL adf_nbuf_t HTCAllocMsgBuffer(HTC_CONTEXT *pHTC) { return BUF_Pool_alloc_buf(pHTC->PoolHandle, POOL_ID_HTC_CONTROL, HTC_GetReservedHeadroom(pHTC)); } LOCAL void HTCCheckAndSendCreditReport(HTC_CONTEXT *pHTC, A_UINT32 EpMask, HTC_ENDPOINT *pEndpoint, HTC_ENDPOINT_ID Eid) { adf_nbuf_t pCredBuffer; HTC_BUF_CONTEXT *ctx; do { /* check if host needs credits */ if (!(pHTC->EpHostNeedsCreditMap & EpMask)) { /* host does not need any credits for this set */ break; } /* check if any are pending */ if (!(pHTC->EpCreditPendingMap & EpMask)) { /* nothing to send up */ break; } /* was an endpoint specified? */ if (pEndpoint != NULL) { /* see if a threshold is in effect for this endpoint */ if (pEndpoint->CreditReturnThreshhold != 0) { if (pEndpoint->CreditsToReturn < pEndpoint->CreditReturnThreshhold) { /* this endpoint is using a threshold to prevent credits from dribbling * back to the host */ break; } } if (pEndpoint->PendingCreditReports >= pHTC->MaxEpPendingCreditRpts) { /* this endpoint already has some reports outstanding */ /* flag that as soon as a buffer is reaped, we issue a credit update to * pick up this credit that is being held up because the endpoint has already * exceeded the max outstanding credit report limit */ pHTC->StateFlags |= HTC_SEND_CREDIT_UPDATE_SOON; break; } } /* if we get here we have some credits to send up */ /* allocate a message buffer for the trailer */ pCredBuffer = HTCAllocMsgBuffer(pHTC); if (NULL == pCredBuffer) { /* no buffers left to send an empty message with trailers, host will just * have to wait until we get our endpoint 0 messages back.. */ /* mark that we need to send an update as soon as we can get a buffer back */ pHTC->StateFlags |= HTC_SEND_CREDIT_UPDATE_SOON; break; } ctx = (HTC_BUF_CONTEXT *)adf_nbuf_get_priv(pCredBuffer); if (pEndpoint != NULL) { /* keep track of pending reports */ pEndpoint->PendingCreditReports++; /* save the endpoint in order to decrement the count when the send completes */ ctx->htc_flags = Eid | HTC_FLAGS_CREDIT_RPT; } /* this is an empty message, the HTC_SendMsg will tack on a trailer in the remaining * space, NOTE: no need to flush the cache, the header and trailers are assembled * using uncached addresses */ HTC_SendMsg(pHTC, ENDPOINT0, pCredBuffer); } while (FALSE); } /* called in response to the arrival of a service connection message */ LOCAL void HTCProcessConnectMsg(HTC_CONTEXT *pHTC, HTC_CONNECT_SERVICE_MSG *pMsg) { HTC_SERVICE *pService = pHTC->pServiceList; A_UINT8 connectStatus = HTC_SERVICE_NOT_FOUND; adf_nbuf_t pBuffer; HTC_CONNECT_SERVICE_RESPONSE_MSG *pRspMsg; int metaDataOutLen = 0; A_UINT16 serviceId = adf_os_ntohs(pMsg->ServiceID); pBuffer = HTCAllocMsgBuffer(pHTC); /* note : this will be aligned */ pRspMsg = (HTC_CONNECT_SERVICE_RESPONSE_MSG *) adf_nbuf_put_tail(pBuffer, sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG)); A_MEMZERO(pRspMsg,sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG)); pRspMsg->MessageID = adf_os_htons(HTC_MSG_CONNECT_SERVICE_RESPONSE_ID); /* reflect the service ID for this connect attempt */ pRspMsg->ServiceID = adf_os_htons(serviceId); while (pService) { if (pHTC->CurrentEpIndex >= ENDPOINT_MAX) { /* no more endpoints */ connectStatus = HTC_SERVICE_NO_RESOURCES; break; } if (serviceId == pService->ServiceID) { /* we found a match */ A_UINT8 *pMetaDataIN = NULL; A_UINT8 *pMetaDataOut; /* outgoing meta data resides in the space after the response message */ pMetaDataOut = ((A_UINT8 *)pRspMsg) + sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG); if (pMsg->ServiceMetaLength != 0) { /* the meta data follows the connect service message */ pMetaDataIN = ((A_UINT8 *)pMsg) + sizeof(HTC_CONNECT_SERVICE_MSG); } /* call the connect callback with the endpoint to use and pointers to meta data */ connectStatus = pService->ProcessConnect(pService, pHTC->CurrentEpIndex, pMetaDataIN, pMsg->ServiceMetaLength, pMetaDataOut, &metaDataOutLen); /* check if the service accepted this connection request */ if (HTC_SERVICE_SUCCESS == connectStatus) { /* set the length of the response meta data going back to the host */ pRspMsg->ServiceMetaLength = (A_UINT8)metaDataOutLen; /* set the endpoint ID the host will now communicate over */ pRspMsg->EndpointID = pHTC->CurrentEpIndex; /* return the maximum message size for this service */ pRspMsg->MaxMsgSize = adf_os_htons((A_UINT16)pService->MaxSvcMsgSize); /* assign this endpoint to this service, this will be used in routing messages */ pHTC->Endpoints[pHTC->CurrentEpIndex].pService = pService; /* set connection flags */ pHTC->Endpoints[pHTC->CurrentEpIndex].ConnectionFlags = pMsg->ConnectionFlags; pHTC->Endpoints[pHTC->CurrentEpIndex].DownLinkPipeID = pMsg->DownLinkPipeID; pHTC->Endpoints[pHTC->CurrentEpIndex].UpLinkPipeID = pMsg->UpLinkPipeID; /* mark that we are now connected */ pService->ServiceFlags |= HTC_SERVICE_FLAGS_CONNECTED; /* bump up our index, this EP is now in use */ pHTC->CurrentEpIndex++; } break; } pService = pService->pNext; } pRspMsg->Status = connectStatus; /* send out the response message */ HTC_SendMsg(pHTC, ENDPOINT0, pBuffer); } LOCAL void HTCProcessConfigPipeMsg(HTC_CONTEXT *pHTC, HTC_CONFIG_PIPE_MSG *pMsg) { adf_nbuf_t pBuffer; HTC_CONFIG_PIPE_RESPONSE_MSG *pRspMsg; pBuffer = HTCAllocMsgBuffer(pHTC); /* note : this will be aligned */ pRspMsg = (HTC_CONFIG_PIPE_RESPONSE_MSG *) adf_nbuf_put_tail(pBuffer, sizeof(HTC_CONFIG_PIPE_RESPONSE_MSG)); A_MEMZERO(pRspMsg,sizeof(HTC_CONFIG_PIPE_RESPONSE_MSG)); pRspMsg->MessageID = adf_os_htons(HTC_MSG_CONFIG_PIPE_RESPONSE_ID); /* reflect the service ID for this connect attempt */ pRspMsg->PipeID = pMsg->PipeID; if ( HIF_is_pipe_supported(pHTC->hifHandle, pMsg->PipeID) ) { pRspMsg->Status = 0; } else { pRspMsg->Status = 1; goto config_done; } if ( (pHTC->TotalCreditsAssigned + pMsg->CreditCount) <= pHTC->TotalCredits ) { pHTC->TotalCreditsAssigned += pMsg->CreditCount; } else { pRspMsg->Status = 2; goto config_done; } HIF_config_pipe(pHTC->hifHandle, pMsg->PipeID, pMsg->CreditCount); config_done: /* send out the response message */ HTC_SendMsg(pHTC, ENDPOINT0, pBuffer); } /* process an incomming control message from the host */ LOCAL void HTCControlSvcProcessMsg(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t hdr_buf, adf_nbuf_t pBuffers, void *arg) { A_BOOL setupComplete = FALSE; a_uint8_t *anbdata; a_uint32_t anblen; HTC_CONTEXT *pHTC = (HTC_CONTEXT *)arg; HTC_UNKNOWN_MSG *pMsg; adf_os_assert(hdr_buf == ADF_NBUF_NULL); /* we assume buffers are aligned such that we can access the message * parameters directly*/ adf_nbuf_peek_header(pBuffers, &anbdata, &anblen); pMsg = (HTC_UNKNOWN_MSG *)anbdata; /* we cannot handle fragmented messages across buffers */ switch ( adf_os_ntohs(pMsg->MessageID) ) { case HTC_MSG_CONNECT_SERVICE_ID: HTCProcessConnectMsg(pHTC, (HTC_CONNECT_SERVICE_MSG *)pMsg); break; case HTC_MSG_CONFIG_PIPE_ID: HTCProcessConfigPipeMsg(pHTC, (HTC_CONFIG_PIPE_MSG *)pMsg); break; case HTC_MSG_SETUP_COMPLETE_ID: /* the host has indicated that it has completed all setup tasks and we can now let the services take over to run the rest of the application */ setupComplete = TRUE; /* can't get this more than once */ break; default: ; } if (pHTC->StateFlags & HTC_STATE_SETUP_COMPLETE) { /* recycle buffer only if we are fully running */ HTC_ReturnBuffers(pHTC, ENDPOINT0,pBuffers); } else { /* supply some head-room again */ adf_nbuf_push_head(pBuffers, HTC_HDR_LENGTH); /* otherwise return the packet back to mbox */ HIF_return_recv_buf(pHTC->hifHandle, pHTC->Endpoints[EndpointID].UpLinkPipeID, pBuffers); } if (setupComplete) { /* mark that setup has completed */ pHTC->StateFlags |= HTC_STATE_SETUP_COMPLETE; if (pHTC->SetupCompleteCb != NULL) { pHTC->SetupCompleteCb(); } } } /* callback when endpoint 0 send buffers are completed */ LOCAL void HTCControlSvcProcessSendComplete(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t pBuffers, void *arg) { HTC_CONTEXT *pHTC = (HTC_CONTEXT *)arg; HTC_BUF_CONTEXT *ctx; HTC_ENDPOINT_ID creditRptEndpoint; ctx = (HTC_BUF_CONTEXT *)adf_nbuf_get_priv(pBuffers); /* put them back into the pool */ if ( ctx->htc_flags & HTC_FLAGS_CREDIT_RPT ) { /* extract the endpoint number that requested this credit report */ creditRptEndpoint = ctx->htc_flags & HTC_FLAGS_CRPT_EP_MASK; pHTC->Endpoints[creditRptEndpoint].PendingCreditReports--; } HTCFreeMsgBuffer(pHTC, pBuffers); if (pHTC->StateFlags & HTC_SEND_CREDIT_UPDATE_SOON) { /* this flag is set when the host could not send a credit report * because we ran out of HTC control buffers */ pHTC->StateFlags &= ~HTC_SEND_CREDIT_UPDATE_SOON; /* send out a report if anything is pending */ HTCCheckAndSendCreditReport(pHTC, HTC_ANY_ENDPOINT_MASK,NULL,ENDPOINT_MAX); } } LOCAL void HTCSendDoneHandler(adf_nbuf_t buf, void *context) { A_UINT8 current_eid; HTC_CONTEXT *pHTC = (HTC_CONTEXT *)context; HTC_BUF_CONTEXT *ctx; ctx = (HTC_BUF_CONTEXT *)adf_nbuf_get_priv(buf); current_eid = ctx->end_point; /* Walk through the buffers and fixup the ones we used for HTC headers. * The buffer list may contain more than one string of HTC buffers comprising of an * HTC message so we need to check every buffer */ adf_nbuf_pull_head(buf, HTC_HDR_LENGTH); pHTC->Endpoints[current_eid].pService-> ProcessSendBufferComplete(current_eid, buf, pHTC->Endpoints[current_eid].pService->ServiceCtx); } LOCAL void AdjustCreditThreshold(HTC_ENDPOINT *pEndpoint) { A_INT16 creditsOutstanding = pEndpoint->CreditsToReturn + pEndpoint->CreditsConsumed; /* set the new threshold based on the number of credits that have been consumed * and which have not been returned by the app. * Note: it is okay for this threshold to be zero which indicates no threshold * is in use */ switch (pEndpoint->ConnectionFlags & HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK) { case HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH : creditsOutstanding >>= 2; break; case HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF : creditsOutstanding >>= 1; break; case HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS : creditsOutstanding = (creditsOutstanding * 3) >> 2; break; /* default case is unity */ } pEndpoint->CreditReturnThreshhold = creditsOutstanding; } LOCAL void RedistributeCredit(adf_nbuf_t buf, int toPipeId) { } /* callback from the mailbox hardware layer when a full message arrives */ LOCAL void HTCMsgRecvHandler(adf_nbuf_t hdr_buf, adf_nbuf_t buffer, void *context) { HTC_ENDPOINT *pEndpoint; A_UINT32 eidMask; int eid; a_uint8_t *anbdata; a_uint32_t anblen; HTC_FRAME_HDR *pHTCHdr; HTC_CONTEXT *pHTC = (HTC_CONTEXT *)context; adf_nbuf_t tmp_nbuf; if (hdr_buf == ADF_NBUF_NULL) { /* HTC hdr is not in the hdr_buf */ tmp_nbuf = buffer; } else { tmp_nbuf = hdr_buf; } adf_nbuf_peek_header(tmp_nbuf, &anbdata, &anblen); pHTCHdr = (HTC_FRAME_HDR *)anbdata; eid = pHTCHdr->EndpointID; pEndpoint = &pHTC->Endpoints[eid]; eidMask = 1 << eid; if (pHTCHdr->Flags & HTC_FLAGS_CREDIT_REDISTRIBUTION) { /* The pipe id where the credit is redistributed to is carried in Control * Byte 0 */ RedistributeCredit(tmp_nbuf, pHTCHdr->ControlBytes[0]); return; } if (pHTC->StateFlags & HTC_STATE_SETUP_COMPLETE) { /* after setup we keep track of credit consumption to allow us to * adjust thresholds to reduce credit dribbling */ pEndpoint->CreditsConsumed ++; } /* from the design document, we put the endpoint into a "host-needs-credit" state * when we receive a frame with the NEED_CREDIT_UPDATE flag set . * if the host received credits through an opportunistic path, then it can * issue a another frame with this bit cleared, this signals the target to clear * the "host-needs-credit" state */ if (pHTCHdr->Flags & HTC_FLAGS_NEED_CREDIT_UPDATE) { /* the host is running low (or is out) of credits on this * endpoint, update mask */ pHTC->EpHostNeedsCreditMap |= eidMask; /* check and set new threshold since host has reached a low credit situation */ CHECK_AND_ADJUST_CREDIT_THRESHOLD(pEndpoint); } else { /* clear the flag */ pHTC->EpHostNeedsCreditMap &= ~(eidMask); pEndpoint->CreditReturnThreshhold = 0; } /* Adjust the first buffer to point to the start of the actual payload, the first buffer contains the header */ adf_nbuf_pull_head(tmp_nbuf, HTC_HDR_LENGTH); /* NOTE : This callback could re-queue the recv buffers within this calling context. * The callback could also send a response message within the context of this callback * as the result of parsing this message. In either case, if there are * pending credits and the host needs them, a credit report will be sent either through * the response message trailer or a NULL message through HTC_ReturnBuffers(). */ pEndpoint->pService->ProcessRecvMsg(eid, hdr_buf, buffer, pEndpoint->pService->ServiceCtx); /* Calls to HTC_ReturnBuffers drives the endpoint credit reporting state machine. * We do not want to delay credits for too long in the event that the application is * holding onto buffers for excessive periods of time. This gives us "some" better * opportunities to send up credits. */ HTCCheckAndSendCreditReport(pHTC, eidMask, pEndpoint, eid); } open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/htc/htc_api.h000077500000000000000000000144101321570333100322100ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * @File: htc_api.h * * @Abstract: host-target communications API * * @Notes: */ #ifndef __HTC_API_H__ #define __HTC_API_H__ #include #include #include #include #define HTC_HDR_SZ HTC_HDR_LENGTH #define HTC_BUFSZ_MAX_SEND 2048 typedef void (* HTC_SERVICE_ProcessRecvMsg)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t, adf_nbuf_t, void *ServiceCtx); typedef void (* HTC_SERVICE_ProcessSendBufferComplete)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t, void *ServiceCtx); /* HTC service structure : * the caller is required to allocate storage for the service structure and register the * structure using HTC_RegisterService() The service must set the following fields: * ProcessRecvMsg * ProcessSendBufferComplete * ProcessConnect * ServiceID * MaxSvcMsgSize (for message validation) * */ typedef struct _HTC_SERVICE { struct _HTC_SERVICE *pNext; /* Callback for processing receive messages. HTC calls this callback whenever a * message arrives on the endpoint assigned to this service. * HTC_BUFFER is a chain of buffers containing a full application message. * HTC_BUFFER->buffer points to the start of the msg buffer (past the HTC header) */ void (* ProcessRecvMsg)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t, adf_nbuf_t, void *ServiceCtx); /* callback to process completed send buffers */ void (* ProcessSendBufferComplete)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t, void *ServiceCtx); /* optional callback when a connection request occurs. * The EndpointID is the assigned endpoint, the callback returns a connect * response status code to allow or disallow the connection. * pDataIn points to the optional meta data supplied in the connection request * pDataOut points to a buffer to send back meta data * If no callback is supplied, HTC assumes the connect is allowed */ A_UINT8 (* ProcessConnect)(struct _HTC_SERVICE *pService, HTC_ENDPOINT_ID EndpointID, A_UINT8 *pDataIn, int LengthIn, A_UINT8 *pDataOut, int *pLengthOut); A_UINT16 ServiceID; /* service ID to match connection requests */ A_UINT16 ServiceFlags; /* service flags */ A_UINT16 MaxSvcMsgSize; /* maximum length of service-specific messages exchanged on the endpoint */ A_UINT16 TrailerSpcCheckLimit; /* amount of space in each send buffer that HTC can check for trailer data. This should be set to the smallest HTC buffer that can be sent through the service. The service can disable trailer data insertion by setting this value to 0. */ void *ServiceCtx; } HTC_SERVICE; #define HTC_SERVICE_FLAGS_CONNECTED (1 << 0) /* service has at least 1 connection */ #define IS_SERVICE_CONNECTED(s) ((s)->ServiceFlags & HTC_SERVICE_FLAGS_CONNECTED) /* configuration settings for the WMI service */ typedef struct _HTC_CONFIG { int CreditSize; /* */ int CreditNumber; adf_os_handle_t OSHandle; hif_handle_t HIFHandle; pool_handle_t PoolHandle; } HTC_CONFIG; typedef struct _HTC_BUF_CONTEXT { A_UINT8 end_point; A_UINT8 htc_flags; /* htc flags (used by HTC layer only) */ } HTC_BUF_CONTEXT; typedef void* htc_handle_t; /* * setup complete function, supplied by HTC caller at HTC_init time. * HTC calls this function after the host has indicated that the service connection * phase is complete. * */ typedef void (* HTC_SETUP_COMPLETE_CB)(void); struct htc_apis { htc_handle_t (* _HTC_Init)(HTC_SETUP_COMPLETE_CB, HTC_CONFIG *pConfig); void (* _HTC_Shutdown)(htc_handle_t); void (* _HTC_RegisterService)(htc_handle_t, HTC_SERVICE *); void (* _HTC_Ready)(htc_handle_t); void (* _HTC_ReturnBuffers)(htc_handle_t handle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_t); void (* _HTC_ReturnBuffersList)(htc_handle_t handle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_queue_t); void (* _HTC_SendMsg)(htc_handle_t handle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_t); int (* _HTC_GetReservedHeadroom)(htc_handle_t handle); /* These APIs below are for patch purpose only */ void (*_HTC_MsgRecvHandler)(adf_nbuf_t hdr_buf, adf_nbuf_t buf, void *context); void (*_HTC_SendDoneHandler)(adf_nbuf_t buf, void *context); void (*_HTC_ControlSvcProcessMsg)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t hdr_buf, adf_nbuf_t buf, void *arg); void (*_HTC_ControlSvcProcessSendComplete)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t pBuffers, void *arg); void *pReserved; /* for expansion if need be */ }; extern void htc_module_install(struct htc_apis *pAPIs); #endif /* _HTC_API_H__ */ htc_internal.h000077500000000000000000000145631321570333100332050ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/htc/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * @File: * * @Abstract: internal data and structure definitions for HTC * * @Notes: */ #ifndef HTC_INTERNAL_H_ #define HTC_INTERNAL_H_ /* minimum buffer size to hold up to 8 endpoint reports, lookahead and the HTC header */ #define MIN_BUF_SIZE_FOR_RPTS (A_ROUND_UP((sizeof(HTC_LOOKAHEAD_REPORT) + \ (sizeof(HTC_CREDIT_REPORT)) * 8 + \ (sizeof(HTC_RECORD_HDR)) * 2 ) + \ HTC_HDR_LENGTH, \ sizeof(A_UINT32))) /* minimum allocation for a credit message */ #define MIN_CREDIT_BUFFER_ALLOC_SIZE (MIN_BUF_SIZE_FOR_RPTS) /* max ctrl buffers size for a setup message */ #define MAX_HTC_SETUP_MSG_SIZE 64 /* The max size of USB command/event pipe is 64 bytes */ /* check size for trailer space */ #define HTC_CTRL_BUFFER_CHECK_SIZE (MIN_BUF_SIZE_FOR_RPTS - HTC_HDR_LENGTH) #define HTC_DEFAULT_NUM_CTRL_BUFFERS 6 #define HTC_DEFAULT_MAX_EP_PENDING_CREDIT_REPORTS 3 /* an EP should not have more than this many outstanding reports */ #define HTC_FLAGS_CRPT_EP_MASK 0x1F /* if the message is a credit report this is the endpoint that issued it */ #define HTC_FLAGS_CREDIT_RPT (1 << 5) /* the buffer was a credit report */ #define HTC_FLAGS_BUF_HDR (1 << 6) /* the buffer was manipulated and a header added */ #define HTC_FLAGS_RECV_END_MSG (1 << 7) /* this buffer is the last buffer for the recev message (used for recv pause logic) */ #define HTC_MAILBOX 0 /* we use mailbox 0 for all communications */ #define HTC_ANY_ENDPOINT_MASK 0xFFFFFFFF #define HTC_LOOKAHEAD_POST_VALID 0x55 #define HTC_LOOKAHEAD_PRE_VALID 0xAA #define MAX_HTC_CREDITS 255 typedef struct _HTC_ENDPOINT { A_INT16 CreditsToReturn; /* credits that are ready to be returned to the host */ HTC_SERVICE *pService; /* service that is bound to this endpoint */ #ifdef HTC_PAUSE_RESUME_REF_COUNTING int PauseRefCount; /* reference count */ #endif A_INT16 CreditReturnThreshhold; /* threshold before credits are returned via NULL pkts, this reduces dribbling effect */ A_INT16 CreditsConsumed; /* number of credits consumed (outstanding) on the endpoint */ A_UINT16 ConnectionFlags; /* HTC connection flags */ int PendingCreditReports; /* no. of pending credit reports issued by this endpoint */ A_UINT8 DownLinkPipeID; /* The pipe ID to be use for the direction: target -> host */ A_UINT8 UpLinkPipeID; /* The pipe ID to be use for the direction: host -> target */ } HTC_ENDPOINT; typedef struct _HTC_CONTEXT { adf_os_handle_t OSHandle; HTC_ENDPOINT Endpoints[ENDPOINT_MAX]; /* endpoint state structs */ A_UINT32 EpHostNeedsCreditMap; /* credit update bit map for all EPs */ A_UINT32 EpCreditPendingMap; /* credits pending bit map for all EPs */ A_UINT32 EpRecvPausedMap; /* recv pause state bit map for all EPs */ HTC_ENDPOINT_ID CurrentEpIndex; /* current unused endpoint index */ HTC_SERVICE HTCControlService; /* the pseudo service that handles EP0 traffic */ HTC_SERVICE *pServiceList; /* the service list */ int RecvBufferSize; /* the length of each recv buffer that HTC is given */ A_UINT32 StateFlags; /* state flags */ HTC_SETUP_COMPLETE_CB SetupCompleteCb; /* caller supplied setup completion routine */ int TotalCredits; /* total credits in system */ int TotalCreditsAssigned; int NumBuffersForCreditRpts; /* number of control buffers for credit reports */ int CtrlBufferAllocSize; /* length of allocation */ A_UINT8 *pCtrlBuffer; /* control buffer to be carved up for messages */ int MaxEpPendingCreditRpts; /* maximum number of pending credit reports that any 1 EP can have */ hif_handle_t hifHandle; pool_handle_t PoolHandle; // Left a door for extension the structure void *pReserved; } HTC_CONTEXT; #define HTC_STATE_SETUP_COMPLETE (1 << 0) /* HTC host-target setup is complete */ #define HTC_SEND_CREDIT_UPDATE_SOON (1 << 1) /* Credit update message needs to be sent */ #define HTC_STATE_BUFF_REALLOC (1 << 2) /* buffers have been reallocated for credit messages */ #endif /*HTC_INTERNAL_H_*/ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/000077500000000000000000000000001321570333100304205ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/OTUS/000077500000000000000000000000001321570333100312125ustar00rootroot00000000000000OTUS_soc.h000077500000000000000000000245101321570333100327470ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/OTUS/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AR6K_SOC_H__ #define __AR6K_SOC_H__ //#include "hw/apb_map.h" //#include "hw/rtc_reg.h" //#include "hw/mbox_reg.h" /* * Basic types, appropriate for both * the 32-bit MIPS core on AR6000 and * the 32-bit XTensa core on AR6002 */ typedef signed char A_CHAR; typedef signed char A_INT8; typedef unsigned char A_UINT8; typedef unsigned char A_UCHAR; typedef short A_INT16; typedef unsigned short A_UINT16; typedef int A_INT32; typedef unsigned int A_UINT32; typedef long long A_INT64; typedef unsigned long long A_UINT64; typedef int A_BOOL; typedef unsigned int ULONG; typedef ULONG A_ULONG; typedef A_ULONG A_ADDR; #if 0 //#include "targaddrs.h" /* * Some platform-specific macros and constants that may needed * outside of the BSP. */ /* * AR6001/MIPS uses a cache line size of 16 Bytes. * AR6002/Xtensa has no caches; but existing code assumes * that this constant is non-zero. To avoid code complexity * and possibly subtle bugs we define a bogus cache * line size for Xtensa that matches MIPs'. */ #define A_CACHE_LINE_SIZE 16 #if defined(AR6001) #define A_MIPS_KSEG_UNCACHED 0xa0000000 #define A_MIPS_KSEG_CACHED 0x80000000 #define A_MIPS_KSEG_MASK 0xe0000000 /* * Convert a cached virtual address or a CPU physical address into * an uncached virtual address. */ #define A_UNCACHED_ADDR(addr) \ ((void *)(((A_UINT32)(addr)) | A_MIPS_KSEG_UNCACHED)) /* * Convert an uncached or CPU physical address into * a cached virtual address. */ #define A_CACHED_ADDR(addr) \ ((void *)((((A_UINT32)(addr)) & ~A_MIPS_KSEG_MASK) | A_MIPS_KSEG_CACHED)) /* Read/Write a 32-bit AR6000 SOC register, specified by its physical address */ #define A_SOC_ADDR_READ(addr) (*((volatile A_UINT32 *)A_UNCACHED_ADDR(addr))) #define A_SOC_ADDR_WRITE(addr, val) \ do { \ (*((volatile A_UINT32 *)A_UNCACHED_ADDR(addr))) = (A_UINT32)(val); \ } while (0) #define A_RTC_REG_READ(addr) A_SOC_ADDR_READ(addr) #define A_MC_REG_READ(addr) A_SOC_ADDR_READ(addr) #define A_UART_REG_READ(addr) A_SOC_ADDR_READ(addr) #define A_SI_REG_READ(addr) A_SOC_ADDR_READ(addr) #define A_GPIO_REG_READ(addr) A_SOC_ADDR_READ(addr) #define A_MBOX_REG_READ(addr) A_SOC_ADDR_READ(addr) #define A_WMAC_REG_READ(addr) A_SOC_ADDR_READ(addr) #define A_ANALOG_REG_READ(addr) A_SOC_ADDR_READ(addr) #define A_RTC_REG_WRITE(addr, val) A_SOC_ADDR_WRITE((addr), (val)) #define A_MC_REG_WRITE(addr, val) A_SOC_ADDR_WRITE((addr), (val)) #define A_UART_REG_WRITE(addr, val) A_SOC_ADDR_WRITE((addr), (val)) #define A_SI_REG_WRITE(addr, val) A_SOC_ADDR_WRITE((addr), (val)) #define A_GPIO_REG_WRITE(addr, val) A_SOC_ADDR_WRITE((addr), (val)) #define A_MBOX_REG_WRITE(addr, val) A_SOC_ADDR_WRITE((addr), (val)) #define A_WMAC_REG_WRITE(addr, val) A_SOC_ADDR_WRITE((addr), (val)) #define A_ANALOG_REG_WRITE(addr, val) A_SOC_ADDR_WRITE((addr), (val)) #endif #if defined(AR6002) #define A_UNCACHED_ADDR(addr) (addr) #define A_CACHED_ADDR(addr) (addr) #define A_SOC_ADDR_READ(addr) (*((volatile A_UINT32 *)(addr))) #define A_SOC_ADDR_WRITE(addr, val) \ do { \ (*((volatile A_UINT32 *)(addr))) = (A_UINT32)(val); \ } while (0) #define A_RTC_REG_READ(addr) A_SOC_ADDR_READ(RTC_BASE_ADDRESS|(A_UINT32)(addr)) #define A_MC_REG_READ(addr) A_SOC_ADDR_READ(VMC_BASE_ADDRESS|(A_UINT32)(addr)) #define A_UART_REG_READ(addr) A_SOC_ADDR_READ(UART_BASE_ADDRESS|(A_UINT32)(addr)) #define A_SI_REG_READ(addr) A_SOC_ADDR_READ(SI_BASE_ADDRESS|(A_UINT32)(addr)) #define A_GPIO_REG_READ(addr) A_SOC_ADDR_READ(GPIO_BASE_ADDRESS|(A_UINT32)(addr)) #define A_MBOX_REG_READ(addr) A_SOC_ADDR_READ(MBOX_BASE_ADDRESS|(A_UINT32)(addr)) #define A_WMAC_REG_READ(addr) A_SOC_ADDR_READ(MAC_BASE_ADDRESS|(A_UINT32)(addr)) #define A_ANALOG_REG_READ(addr) A_SOC_ADDR_READ(ANALOG_INTF_BASE_ADDRESS|(A_UINT32)(addr)) #define A_RTC_REG_WRITE(addr, val) A_SOC_ADDR_WRITE(RTC_BASE_ADDRESS|(A_UINT32)(addr), (val)) #define A_MC_REG_WRITE(addr, val) A_SOC_ADDR_WRITE(VMC_BASE_ADDRESS|(A_UINT32)(addr), (val)) #define A_UART_REG_WRITE(addr, val) A_SOC_ADDR_WRITE(UART_BASE_ADDRESS|(A_UINT32)(addr), (val)) #define A_SI_REG_WRITE(addr, val) A_SOC_ADDR_WRITE(SI_BASE_ADDRESS|(A_UINT32)(addr), (val)) #define A_GPIO_REG_WRITE(addr, val) A_SOC_ADDR_WRITE(GPIO_BASE_ADDRESS|(A_UINT32)(addr), (val)) #define A_MBOX_REG_WRITE(addr, val) A_SOC_ADDR_WRITE(MBOX_BASE_ADDRESS|(A_UINT32)(addr), (val)) #define A_WMAC_REG_WRITE(addr, val) A_SOC_ADDR_WRITE(MAC_BASE_ADDRESS|(A_UINT32)(addr), (val)) #define A_ANALOG_REG_WRITE(addr, val) A_SOC_ADDR_WRITE(ANALOG_INTF_BASE_ADDRESS|(A_UINT32)(addr), (val)) #endif /* AR6002 */ /* * Sleep/stay awake control. * It is the caller's responsibility to guarantee atomicity. */ typedef A_UINT32 A_old_sleep_t; #define A_SYSTEM_SLEEP_DISABLE(pOldSystemSleep) \ do { \ *(pOldSystemSleep) = A_RTC_REG_READ(SYSTEM_SLEEP_ADDRESS); \ A_RTC_REG_WRITE(SYSTEM_SLEEP_ADDRESS, \ *(pOldSystemSleep) | SYSTEM_SLEEP_DISABLE_MASK); \ (void)A_RTC_REG_READ(SYSTEM_SLEEP_ADDRESS); /* flush */ \ } while (0) #define A_SYSTEM_SLEEP_RESTORE(OldSystemSleep) \ do { \ A_RTC_REG_WRITE(SYSTEM_SLEEP_ADDRESS, (OldSystemSleep)); \ (void)A_RTC_REG_READ(SYSTEM_SLEEP_ADDRESS); /* flush */ \ } while (0) /* * AR6K-specific High Frequency Timestamp support. * This is intended for use as a performance tool, and * is not to be used in normal operation. */ typedef struct { A_UINT32 highfreq; /* ~40MHz resolution */ A_UINT32 lowfreq; /* ~32KHz resolution */ } A_timestamp_t; /* * Enable HighFrequency timer. * Normally, we keep this OFF in order to save power. */ #define HF_TIMER_CONTROL_START_MASK HF_TIMER_CONTROL_ON_MASK #define A_TIMESTAMP_ENABLE() \ do { \ A_RTC_REG_WRITE(HF_TIMER_ADDRESS, (40000000/32768)<<12); \ A_RTC_REG_WRITE(HF_TIMER_CONTROL_ADDRESS, \ HF_TIMER_CONTROL_START_MASK | \ HF_TIMER_CONTROL_AUTO_RESTART_MASK | \ HF_TIMER_CONTROL_RESET_MASK); \ } while (0) /* * Turn it OFF when you're done: */ #define A_TIMESTAMP_DISABLE() A_RTC_REG_WRITE(HF_TIMER_CONTROL_ADDRESS, 0) /* * Get a timestamp. It's the caller's responsibility to * guarantee atomicity of the two reads, if needed. */ #define A_TIMESTAMP(pTimestamp) \ do { \ (pTimestamp)->highfreq = A_RTC_REG_READ(HF_TIMER_COUNT_ADDRESS); \ (pTimestamp)->lowfreq = A_RTC_REG_READ(HF_LF_COUNT_ADDRESS); \ } while (0) /* * Supported reference clock speeds. * * Note: MAC HAL code has multiple tables indexed by these values, * so do not rearrange them. Add any new refclk values at the end. */ typedef enum { AR6K_REFCLK_UNKNOWN = -1, /* Unsupported ref clock -- use PLL Bypass */ AR6K_REFCLK_19_2_MHZ = 0, AR6K_REFCLK_26_MHZ = 1, AR6K_REFCLK_40_MHZ = 2, AR6K_REFCLK_52_MHZ = 3, AR6K_REFCLK_38_4_MHZ = 4, AR6K_REFCLK_24_MHZ = 5, } A_refclk_speed_t; #define A_REFCLK_UNKNOWN AR6K_REFCLK_UNKNOWN #define A_REFCLK_19_2_MHZ AR6K_REFCLK_19_2_MHZ #define A_REFCLK_26_MHZ AR6K_REFCLK_26_MHZ #define A_REFCLK_40_MHZ AR6K_REFCLK_40_MHZ #define A_REFCLK_52_MHZ AR6K_REFCLK_52_MHZ #define A_REFCLK_38_4_MHZ AR6K_REFCLK_38_4_MHZ #define A_REFCLK_24_MHZ AR6K_REFCLK_24_MHZ /* System defaults to 2.4GHz settings */ #define A_BAND_DEFAULT A_BAND_24GHZ #if defined(AR6001) #define FLASH_ADDR(n) AR6000_FLASH_ADDR(n) #endif #if defined(AR6002) #define HOST_INTEREST ((struct host_interest_s *)AR6002_HOST_INTEREST_ADDRESS) #else #define HOST_INTEREST ((struct host_interest_s *)AR6001_HOST_INTEREST_ADDRESS) #endif #define AR6K_OPTION_TEST(option) \ (A_MBOX_REG_READ(LOCAL_SCRATCH_ADDRESS) & (option)) #endif #endif /* __AR6K_SOC_H__ */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/adf_nbuf.h000077500000000000000000000354241321570333100323500ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** * @defgroup adf_nbuf_public network buffer API */ /** * @ingroup adf_nbuf_public * @file adf_nbuf.h * This file defines the network buffer abstraction. */ #ifndef _ADF_NBUF_H #define _ADF_NBUF_H #include #include #include #include #include /** * @brief Platform indepedent packet abstraction */ typedef __adf_nbuf_t adf_nbuf_t; /** * @brief invalid handle */ #define ADF_NBUF_NULL __ADF_NBUF_NULL /** * @brief Platform independent packet queue abstraction */ typedef __adf_nbuf_queue_t adf_nbuf_queue_t; /** * BUS/DMA mapping routines */ /** * @brief Create a DMA map. This can later be used to map * networking buffers. They : * - need space in adf_drv's software descriptor * - are typically created during adf_drv_create * - need to be created before any API(adf_nbuf_map) that uses them * * @param[in] osdev os device * @param[out] dmap map handle * * @return status of the operation */ static inline a_status_t adf_nbuf_dmamap_create(adf_os_device_t osdev, adf_os_dma_map_t *dmap) { return (__adf_nbuf_dmamap_create(osdev, dmap)); } /** * @brief Delete a dmap map * * @param[in] osdev os device * @param[in] dmap */ static inline void adf_nbuf_dmamap_destroy(adf_os_device_t osdev, adf_os_dma_map_t dmap) { __adf_nbuf_dmamap_destroy(osdev, dmap); } /** * @brief Map a buffer to local bus address space * * @param[in] osdev os device * @param[in] bmap map handle * @param[in] buf buf to be mapped * @param[in] dir DMA direction * * @return status of the operation */ static inline a_status_t adf_nbuf_map(adf_os_device_t osdev, adf_os_dma_map_t bmap, adf_nbuf_t buf, adf_os_dma_dir_t dir) { return __adf_nbuf_map(osdev, bmap, buf, dir); } /** * @brief Unmap a previously mapped buf * * @param[in] osdev os device * @param[in] bmap map handle * @param[in] dir DMA direction */ static inline void adf_nbuf_unmap(adf_os_device_t osdev, adf_os_dma_map_t bmap, adf_os_dma_dir_t dir) { __adf_nbuf_unmap(osdev, bmap, dir); } /** * @brief returns information about the mapped buf * * @param[in] bmap map handle * @param[out] sg map info */ static inline void adf_nbuf_dmamap_info(adf_os_dma_map_t bmap, adf_os_dmamap_info_t *sg) { __adf_nbuf_dmamap_info(bmap, sg); } /* * nbuf allocation rouines */ /** * @brief Allocate adf_nbuf * * The nbuf created is guarenteed to have only 1 physical segment * * @param[in] hdl platform device object * @param[in] size data buffer size for this adf_nbuf including max header * size * @param[in] reserve headroom to start with. * @param[in] align alignment for the start buffer. * * @return The new adf_nbuf instance or NULL if there's not enough memory. */ static inline adf_nbuf_t adf_nbuf_alloc(adf_os_size_t size, int reserve, int align) { return __adf_nbuf_alloc(size, reserve,align); } /** * @brief Free adf_nbuf * * @param[in] buf buffer to free */ static inline void adf_nbuf_free(adf_nbuf_t buf) { __adf_nbuf_free(buf); } /** * @brief Reallocate such that there's required headroom in * buf. Note that this can allocate a new buffer, or * change geometry of the orignial buffer. The new buffer * is returned in the (new_buf). * * @param[in] buf (older buffer) * @param[in] headroom * * @return newly allocated buffer */ static inline adf_nbuf_t adf_nbuf_realloc_headroom(adf_nbuf_t buf, a_uint32_t headroom) { return (__adf_nbuf_realloc_headroom(buf, headroom)); } /** * @brief expand the tailroom to the new tailroom, but the buffer * remains the same * * @param[in] buf buffer * @param[in] tailroom new tailroom * * @return expanded buffer or NULL on failure */ static inline adf_nbuf_t adf_nbuf_realloc_tailroom(adf_nbuf_t buf, a_uint32_t tailroom) { return (__adf_nbuf_realloc_tailroom(buf, tailroom)); } /** * @brief this will expand both tail & head room for a given * buffer, you may or may not get a new buffer.Use it * only when its required to expand both. Otherwise use * realloc (head/tail) will solve the purpose. Reason for * having an extra API is that some OS do this in more * optimized way, rather than calling realloc (head/tail) * back to back. * * @param[in] buf buffer * @param[in] headroom new headroom * @param[in] tailroom new tailroom * * @return expanded buffer */ static inline adf_nbuf_t adf_nbuf_expand(adf_nbuf_t buf, a_uint32_t headroom, a_uint32_t tailroom) { return (__adf_nbuf_expand(buf,headroom,tailroom)); } /** * @brief Copy src buffer into dst. This API is useful, for * example, because most native buffer provide a way to * copy a chain into a single buffer. Therefore as a side * effect, it also "linearizes" a buffer (which is * perhaps why you'll use it mostly). It creates a * writeable copy. * * @param[in] buf source nbuf to copy from * * @return the new nbuf */ static inline adf_nbuf_t adf_nbuf_copy(adf_nbuf_t buf) { return(__adf_nbuf_copy(buf)); } /** * @brief link two nbufs, the new buf is piggybacked into the * older one. * * @param[in] dst buffer to piggyback into * @param[in] src buffer to put * * @return status of the call */ static inline void adf_nbuf_cat(adf_nbuf_t dst,adf_nbuf_t src) { __adf_nbuf_cat(dst, src); } /** * @brief clone the nbuf (copy is readonly) * * @param[in] buf nbuf to clone from * * @return cloned buffer */ static inline adf_nbuf_t adf_nbuf_clone(adf_nbuf_t buf) { return(__adf_nbuf_clone(buf)); } /** * @brief Create a version of the specified nbuf whose * contents can be safely modified without affecting * other users.If the nbuf is a clone then this function * creates a new copy of the data. If the buffer is not * a clone the original buffer is returned. * * @param[in] buf source nbuf to create a writable copy from * * @return new buffer which is writeable */ static inline adf_nbuf_t adf_nbuf_unshare(adf_nbuf_t buf) { return(__adf_nbuf_unshare(buf)); } /* * nbuf manipulation routines */ /** * @brief return the amount of headroom int the current nbuf * * @param[in] buf buffer * * @return amount of head room */ static inline a_uint32_t adf_nbuf_headroom(adf_nbuf_t buf) { return (__adf_nbuf_headroom(buf)); } /** * @brief return the amount of tail space available * * @param[in] buf buffer * * @return amount of tail room */ static inline a_uint32_t adf_nbuf_tailroom(adf_nbuf_t buf) { return (__adf_nbuf_tailroom(buf)); } /** * @brief Push data in the front * * @param[in] buf buf instance * @param[in] size size to be pushed * * @return New data pointer of this buf after data has been pushed, * or NULL if there is not enough room in this buf. */ static inline a_uint8_t * adf_nbuf_push_head(adf_nbuf_t buf, adf_os_size_t size) { return __adf_nbuf_push_head(buf, size); } /** * @brief Puts data in the end * * @param[in] buf buf instance * @param[in] size size to be pushed * * @return data pointer of this buf where new data has to be * put, or NULL if there is not enough room in this buf. */ static inline a_uint8_t * adf_nbuf_put_tail(adf_nbuf_t buf, adf_os_size_t size) { return __adf_nbuf_put_tail(buf, size); } /** * @brief pull data out from the front * * @param[in] buf buf instance * @param[in] size size to be popped * * @return New data pointer of this buf after data has been popped, * or NULL if there is not sufficient data to pull. */ static inline a_uint8_t * adf_nbuf_pull_head(adf_nbuf_t buf, adf_os_size_t size) { return __adf_nbuf_pull_head(buf, size); } /** * * @brief trim data out from the end * * @param[in] buf buf instance * @param[in] size size to be popped * * @return none */ static inline void adf_nbuf_trim_tail(adf_nbuf_t buf, adf_os_size_t size) { __adf_nbuf_trim_tail(buf, size); } /** * @brief Get the length of the buf * * @param[in] buf the buf instance * * @return The total length of this buf. */ static inline adf_os_size_t adf_nbuf_len(adf_nbuf_t buf) { return (__adf_nbuf_len(buf)); } /** * @brief test whether the nbuf is cloned or not * * @param[in] buf buffer * * @return TRUE if it is cloned, else FALSE */ static inline a_bool_t adf_nbuf_is_cloned(adf_nbuf_t buf) { return (__adf_nbuf_is_cloned(buf)); } /* * nbuf frag routines */ /** * @brief return the frag pointer & length of the frag * * @param[in] buf buffer * @param[out] sg this will return all the frags of the nbuf * */ static inline void adf_nbuf_frag_info(adf_nbuf_t buf, adf_os_sglist_t *sg) { __adf_nbuf_frag_info(buf, sg); } /** * @brief return the data pointer & length of the header * * @param[in] buf nbuf * @param[out] addr data pointer * @param[out] len length of the data * */ static inline void adf_nbuf_peek_header(adf_nbuf_t buf, a_uint8_t **addr, a_uint32_t *len) { __adf_nbuf_peek_header(buf, addr, len); } /* * nbuf private context routines */ /** * @brief get the priv pointer from the nbuf'f private space * * @param[in] buf * * @return data pointer to typecast into your priv structure */ static inline a_uint8_t * adf_nbuf_get_priv(adf_nbuf_t buf) { return (__adf_nbuf_get_priv(buf)); } /* * nbuf queue routines */ /** * @brief Initialize buf queue * * @param[in] head buf queue head */ static inline void adf_nbuf_queue_init(adf_nbuf_queue_t *head) { __adf_nbuf_queue_init(head); } /** * @brief Append a nbuf to the tail of the buf queue * * @param[in] head buf queue head * @param[in] buf buf */ static inline void adf_nbuf_queue_add(adf_nbuf_queue_t *head, adf_nbuf_t buf) { __adf_nbuf_queue_add(head, buf); } /** * @brief Retrieve a buf from the head of the buf queue * * @param[in] head buf queue head * * @return The head buf in the buf queue. */ static inline adf_nbuf_t adf_nbuf_queue_remove(adf_nbuf_queue_t *head) { return __adf_nbuf_queue_remove(head); } /** * @brief get the length of the queue * * @param[in] head buf queue head * * @return length of the queue */ static inline a_uint32_t adf_nbuf_queue_len(adf_nbuf_queue_t *head) { return __adf_nbuf_queue_len(head); } /** * @brief get the first guy/packet in the queue * * @param[in] head buf queue head * * @return first buffer in queue */ static inline adf_nbuf_t adf_nbuf_queue_first(adf_nbuf_queue_t *head) { return (__adf_nbuf_queue_first(head)); } /** * @brief get the next guy/packet of the given buffer (or * packet) * * @param[in] buf buffer * * @return next buffer/packet */ static inline adf_nbuf_t adf_nbuf_queue_next(adf_nbuf_t buf) { return (__adf_nbuf_queue_next(buf)); } /** * @brief Check if the buf queue is empty * * @param[in] nbq buf queue handle * * @return TRUE if queue is empty * @return FALSE if queue is not emty */ static inline a_bool_t adf_nbuf_is_queue_empty(adf_nbuf_queue_t * nbq) { return __adf_nbuf_is_queue_empty(nbq); } /* * nbuf extension routines XXX */ /** * @brief Gets the tx checksumming to be performed on this buf * * @param[in] buf buffer * @param[out] hdr_off the (tcp) header start * @param[out] where the checksum offset */ static inline adf_net_cksum_type_t adf_nbuf_tx_cksum_info(adf_nbuf_t buf, a_uint8_t **hdr_off, a_uint8_t **where) { return(__adf_nbuf_tx_cksum_info(buf, hdr_off, where)); } /** * @brief Drivers that support hw checksumming use this to * indicate checksum info to the stack. * * @param[in] buf buffer * @param[in] cksum checksum */ static inline void adf_nbuf_set_rx_cksum(adf_nbuf_t buf, adf_nbuf_rx_cksum_t *cksum) { __adf_nbuf_set_rx_cksum(buf, cksum); } /** * @brief Drivers that are capable of TCP Large segment offload * use this to get the offload info out of an buf. * * @param[in] buf buffer * @param[out] tso offload info */ static inline void adf_nbuf_get_tso_info(adf_nbuf_t buf, adf_nbuf_tso_t *tso) { __adf_nbuf_get_tso_info(buf, tso); } /*static inline void adf_nbuf_set_vlan_info(adf_nbuf_t buf, adf_net_vlan_tag_t vlan_tag) { __adf_nbuf_set_vlan_info(buf, vlan_tag); }*/ /** * @brief This function extracts the vid & priority from an * nbuf * * * @param[in] hdl net handle * @param[in] buf buffer * @param[in] vlan vlan header * * @return status of the operation */ static inline a_status_t adf_nbuf_get_vlan_info(adf_net_handle_t hdl, adf_nbuf_t buf, adf_net_vlanhdr_t *vlan) { return __adf_nbuf_get_vlan_info(hdl, buf, vlan); } static inline adf_nbuf_t adf_nbuf_create_frm_frag(adf_nbuf_queue_t *head) { return __adf_nbuf_create_frm_frag(head); } static inline void adf_nbuf_split_to_frag(adf_nbuf_t buf, adf_nbuf_queue_t *qhead) { return __adf_nbuf_split_to_frag(buf, qhead); } #endif open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/adf_net.h000077500000000000000000000173711321570333100322050ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** * @defgroup adf_net_public network abstraction API */ /** * @ingroup adf_net_public * @file adf_net.h * These APIs abstract the OS networking stack from a driver. */ /** * @mainpage * @section Introduction * The Atheros Driver Framework provides a mechanism to run the Atheros * WLAN driver on a variety of Operating Systems and Platforms. It achieves * this by abstracting all OS-specific and platform-specific functionality * the driver requires. This ensures the core logic in the driver is OS- * and platform-independent. * @section Modules * The driver framework consists of three main components: * @subsection sec1 Network Stack * This component abstracts the OS network stack. See @ref adf_net_public for details. * @subsection sec2 Network Buffer * This component abstracts the OS network buffer. See @ref adf_nbuf_public for details. * @subsection sec3 OS services * This component abstracts any OS services. See @ref adf_os_public for details. */ #ifndef _ADF_NET_H #define _ADF_NET_H #include #include #include "adf_net_types.h" #include "adf_net_wcmd.h" #include #include /* * check for a NULL handle * */ #define ADF_NET_NULL __ADF_NET_NULL /** * @brief this register the driver to the shim, but won't get * any handle until create device is called. * * @param[in] drv driver info structure * * @return status of operation */ static inline a_status_t adf_net_register_drv(adf_drv_info_t *drv) { return(__adf_net_register_drv(drv)); } /** * @brief deregister the driver from the shim * * @param[in] name driver name passed in adf_drv_info_t * * @see adf_net_register_drv() */ static inline void adf_net_unregister_drv(a_uint8_t *drv_name) { __adf_net_unregister_drv(drv_name); } /** * @brief register a real device with the kernel * * @param[in] hdl driver handle for this device * @param[in] op per-device switch structure * @param[in] info basic device information * * @return opaque device handle */ static inline adf_net_handle_t adf_net_dev_create(adf_drv_handle_t hdl, adf_dev_sw_t *op, adf_net_dev_info_t *info) { return (__adf_net_dev_create(hdl, op, info)); } /** * @brief register a virtual device with the kernel. * A virtual device is always backed by a real device. * * @param[in] dev_hdl opaque device handle for the real device * @param[in] hdl driver handle for this virtual device * @param[in] op per-virtual-device switch structure * @param[in] info basic virtual device information * * @return opaque device handle * * @see adf_net_dev_create() */ static inline adf_net_handle_t adf_net_vdev_create(adf_net_handle_t dev_hdl, adf_drv_handle_t hdl, adf_vdev_sw_t *op, adf_net_dev_info_t *info) { return (__adf_net_vdev_create(dev_hdl, hdl, op, info)); } /** * @brief Checks if the interface is running or not * * @param[in] hdl opaque device handle * * @return true if running, false if not */ static inline a_bool_t adf_net_is_running(adf_net_handle_t hdl) { return (__adf_net_is_running(hdl)); } /** * @brief Checks if the interface is up or not * * @param[in] hdl opaque device handle * * @return true if up, false if not */ static inline a_bool_t adf_net_is_up(adf_net_handle_t hdl) { return (__adf_net_is_up(hdl)); } /** * @brief check whether the carrier is available or not * * @param[in] hdl opaque device handle * * @return a_bool_t true if available, false if not */ static inline a_bool_t adf_net_carrier_ok(adf_net_handle_t hdl) { return(__adf_net_carrier_ok(hdl)); } /** * @brief inform the networking stack that the link is down * * @param[in] hdl opaque device handle */ static inline void adf_net_carrier_off(adf_net_handle_t hdl) { __adf_net_carrier_off(hdl); } /** * @brief inform the networking stack that the link is up * * @param[in] hdl opaque device handle * * @see adf_net_carrier_off() */ static inline void adf_net_carrier_on(adf_net_handle_t hdl) { __adf_net_carrier_on(hdl); } /* * Queue mgmt. * driver will use these to keep the native networking stack abreast of its * resource (descriptor) situation. */ /** * @brief inform the networking stack that the device is ready to receive * transmit packets. Typically called during init. * * @param[in] hdl opaque device handle */ static inline void adf_net_start_queue(adf_net_handle_t hdl) { __adf_net_start_queue(hdl); } /** * @brief inform the networking stack to stop sending transmit packets. * Typically called if the driver runs out of resources for the device. * * @param[in] hdl opaque device handle */ static inline void adf_net_stop_queue(adf_net_handle_t hdl) { __adf_net_stop_queue(hdl); } /** * @brief inform the native stack to resume sending packets * to transmit.Typically called when the driver has resources * available again for the device. * * @note adf_net_wake_queue() is the counterpart of adf_net_stop_queue() * * @param[in] hdl opaque device handle */ static inline void adf_net_wake_queue(adf_net_handle_t hdl) { __adf_net_wake_queue(hdl); } /** * @brief Check the state of the queue * * @param[in] hdl opaque device handle * * @return true if stopped, false if not */ static inline a_bool_t adf_net_queue_stopped(adf_net_handle_t hdl) { return(__adf_net_queue_stopped(hdl)); } /** * @brief get interface name * * @param[in] hdl opaque device handle * * @return name of interface */ static inline const a_uint8_t * adf_net_ifname(adf_net_handle_t hdl) { return (__adf_net_ifname(hdl)); } /** * @brief Get OS Handle from OS device object. * * @param[in] osdev OS device object * * @return OS handle */ static inline adf_os_handle_t adf_net_dev_to_os(adf_os_device_t osdev) { return __adf_net_dev_to_os(osdev); } /** * @brief Get OS Handle from OS net handle. * * @param[in] osdev OS net handle * * @return OS handle */ static inline adf_os_handle_t adf_net_hdl_to_os(adf_net_handle_t hdl) { return __adf_net_hdl_to_os(hdl); } #endif open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/adf_net_sw.h000077500000000000000000000122261321570333100327100ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** * @ingroup adf_net_public * @file adf_net_sw.h * This file defines the device and virtual device switch tables. */ #ifndef __ADF_NET_SW_H #define __ADF_NET_SW_H /** * @brief per device switch structure */ typedef struct _adf_dev_sw{ /** * @brief Handler for device open - mandatory interface */ a_status_t (*drv_open) (adf_drv_handle_t hdl); /** * @brief Handler for device close - mandatory interface */ void (*drv_close) (adf_drv_handle_t hdl); /** * @brief Handler for transmit - mandatory interface */ a_status_t (*drv_tx) (adf_drv_handle_t hdl, adf_nbuf_t pkt); /** * @brief Handler for configuration command - mandatory interface */ a_status_t (*drv_cmd) (adf_drv_handle_t hdl, adf_net_cmd_t cmd, adf_net_cmd_data_t *data); /** * @brief Handler for ioctl - mandatory interface */ a_status_t (*drv_ioctl) (adf_drv_handle_t hdl, int num, void *data); /** * @brief Handler for transmission timeout - mandatory interface */ a_status_t (*drv_tx_timeout)(adf_drv_handle_t hdl); /** * @brief Handler for wireless configuration - optional interface */ a_status_t (*drv_wcmd) (adf_drv_handle_t hdl, adf_net_wcmd_type_t cmd, adf_net_wcmd_data_t *data); /** * @brief Handler for polling if polling/deferred processing required - * optional interface */ adf_net_poll_resp_t (*drv_poll) (adf_drv_handle_t hdl, int quota, int *work_done); /** * @brief Handler for per cpu deffered callback (e.g. for RSS) - optional * interface */ adf_net_poll_resp_t (*drv_poll_cpu) (adf_drv_handle_t hdl, int quota, int *work_done, void *arg); /** * @brief Handler for disabling receive interrupts for polling. * adf_drv should do proper locking - these are not called in atomic context */ void (*drv_poll_int_disable)(adf_drv_handle_t hdl); /** * @brief Handler for enabling receive interrupts for polling. * adf_drv should do proper locking - these are not called in atomic context */ void (*drv_poll_int_enable) (adf_drv_handle_t hdl); }adf_dev_sw_t; /** * @brief Virtual device switch structure */ typedef struct _adf_vdev_sw{ /** * @brief Handler for device open */ a_status_t (*drv_open) (adf_drv_handle_t hdl); /** * @brief Handler for device close */ void (*drv_close) (adf_drv_handle_t hdl); /** * @brief Handler for transmit */ a_status_t (*drv_tx) (adf_drv_handle_t hdl, adf_nbuf_t pkt); /** * @brief Handler for configuration command */ a_status_t (*drv_cmd) (adf_drv_handle_t hdl, adf_net_cmd_t cmd, adf_net_cmd_data_t *data); /** * @brief Handler for wireless configuration */ a_status_t (*drv_wcmd) (adf_drv_handle_t hdl, adf_net_wcmd_type_t cmd, adf_net_wcmd_data_t *data); /** * @brief Handler for transmission timeout */ a_status_t (*drv_tx_timeout) (adf_drv_handle_t hdl); /** * @brief Handler for ioctl */ a_status_t (*drv_ioctl) (adf_drv_handle_t hdl, int num, void *data); }adf_vdev_sw_t; #endif adf_net_types.h000077500000000000000000000302601321570333100333420ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** * @ingroup adf_net_public * @file adf_net_types.h * This file defines types used in the networking stack abstraction. */ #ifndef _ADF_NET_TYPES_H #define _ADF_NET_TYPES_H /** * @brief These control/get info from the device */ #define ADF_NET_CMD(_x) \ ADF_NET_CMD_GET_##_x, \ ADF_NET_CMD_SET_##_x /** * @brief Get/Set commands from anet to adf_drv */ typedef enum { ADF_NET_CMD(LINK_INFO), ADF_NET_CMD(POLL_INFO), ADF_NET_CMD(CKSUM_INFO), ADF_NET_CMD(RING_INFO), ADF_NET_CMD(MAC_ADDR), ADF_NET_CMD(MTU), ADF_NET_CMD_GET_DMA_INFO, ADF_NET_CMD_GET_OFFLOAD_CAP, ADF_NET_CMD_GET_STATS, ADF_NET_CMD_ADD_VID, ADF_NET_CMD_DEL_VID, ADF_NET_CMD_SET_MCAST, ADF_NET_CMD_GET_MCAST_CAP }adf_net_cmd_t; /** * @brief Indicates what features are supported by the interface. */ #define ADF_NET_LINK_SUPP_10baseT_Half (1 << 0) #define ADF_NET_LINK_SUPP_10baseT_Full (1 << 1) #define ADF_NET_LINK_SUPP_100baseT_Half (1 << 2) #define ADF_NET_LINK_SUPP_100baseT_Full (1 << 3) #define ADF_NET_LINK_SUPP_1000baseT_Half (1 << 4) #define ADF_NET_LINK_SUPP_1000baseT_Full (1 << 5) #define ADF_NET_LINK_SUPP_Autoneg (1 << 6) #define ADF_NET_LINK_SUPP_Pause (1 << 7) #define ADF_NET_LINK_SUPP_Asym_Pause (1 << 8) #define ADF_NET_LINK_SUPP_100 (ADF_NET_LINK_SUPP_10baseT_Half | \ ADF_NET_LINK_SUPP_10baseT_Full | \ ADF_NET_LINK_SUPP_100baseT_Half | \ ADF_NET_LINK_SUPP_100baseT_Full) #define ADF_NET_LINK_SUPP_1000 (ADF_NET_LINK_SUPP_100 | \ ADF_NET_LINK_SUPP_1000baseT_Full) /** * @brief Indicates what features are advertised by the interface. */ #define ADF_NET_LINK_ADV_10baseT_Half (1 << 0) #define ADF_NET_LINK_ADV_10baseT_Full (1 << 1) #define ADF_NET_LINK_ADV_100baseT_Half (1 << 2) #define ADF_NET_LINK_ADV_100baseT_Full (1 << 3) #define ADF_NET_LINK_ADV_1000baseT_Half (1 << 4) #define ADF_NET_LINK_ADV_1000baseT_Full (1 << 5) #define ADF_NET_LINK_ADV_Autoneg (1 << 6) #define ADF_NET_LINK_ADV_Pause (1 << 7) #define ADF_NET_LINK_ADV_Asym_Pause (1 << 8) #define ADF_NET_LINK_ADV_100 (ADF_NET_LINK_ADV_10baseT_Half | \ ADF_NET_LINK_ADV_10baseT_Full | \ ADF_NET_LINK_ADV_100baseT_Half | \ ADF_NET_LINK_ADV_100baseT_Full) #define ADF_NET_LINK_ADV_1000 (ADF_NET_LINK_ADV_100 | \ ADF_NET_LINK_ADV_1000baseT_Full) /** * @brief The forced/current speed/duplex/autoneg */ #define ADF_NET_LINK_SPEED_10 10 #define ADF_NET_LINK_SPEED_100 100 #define ADF_NET_LINK_SPEED_1000 1000 #define ADF_NET_LINK_DUPLEX_HALF 0x00 #define ADF_NET_LINK_DUPLEX_FULL 0x01 #define ADF_NET_LINK_AUTONEG_DISABLE 0x00 #define ADF_NET_LINK_AUTONEG_ENABLE 0x01 #define ADF_NET_MAC_ADDR_MAX_LEN 6 #define ADF_NET_IF_NAME_SIZE 64 #define ADF_NET_ETH_LEN ADF_NET_MAC_ADDR_MAX_LEN #define ADF_NET_MAX_MCAST_ADDR 128 /** * @brief link info capability/parameters for the device * Note the flags below */ typedef struct { a_uint32_t supported; /*RO Features this if supports*/ a_uint32_t advertized; /*Features this interface advertizes*/ a_int16_t speed; /*Force speed 10M, 100M, gigE*/ a_int8_t duplex; /*duplex full or half*/ a_uint8_t autoneg; /*Enabled/disable autoneg*/ }adf_net_cmd_link_info_t; typedef struct adf_net_ethaddr{ a_uint8_t addr[ADF_NET_ETH_LEN]; } adf_net_ethaddr_t; typedef struct { a_uint8_t ether_dhost[ADF_NET_ETH_LEN]; /* destination eth addr */ a_uint8_t ether_shost[ADF_NET_ETH_LEN]; /* source ether addr */ a_uint16_t ether_type; /* packet type ID field */ }adf_net_ethhdr_t; typedef struct { #if defined (ADF_LITTLE_ENDIAN_MACHINE) a_uint8_t ip_hl:4, ip_version:4; #elif defined (ADF_BIG_ENDIAN_MACHINE) a_uint8_t ip_version:4, ip_hl:4; #else #error "Please fix" #endif a_uint8_t ip_tos; a_uint16_t ip_len; a_uint16_t ip_id; a_uint16_t ip_frag_off; a_uint8_t ip_ttl; a_uint8_t ip_proto; a_uint16_t ip_check; a_uint32_t ip_saddr; a_uint32_t ip_daddr; /*The options start here. */ }adf_net_iphdr_t; /** * @brief Vlan header */ typedef struct adf_net_vlanhdr{ a_uint16_t tpid; #if defined (ADF_LITTLE_ENDIAN_MACHINE) a_uint16_t vid:12; /* Vlan id*/ a_uint8_t cfi:1; /* reserved for CFI, don't use*/ a_uint8_t prio:3; /* Priority*/ #elif defined (ADF_BIG_ENDIAN_MACHINE) a_uint8_t prio:3; /* Priority*/ a_uint8_t cfi:1; /* reserved for CFI, don't use*/ a_uint16_t vid:12; /* Vlan id*/ #else #error "Please fix" #endif }adf_net_vlanhdr_t; typedef struct adf_net_vid{ #if defined (ADF_LITTLE_ENDIAN_MACHINE) a_uint16_t val:12; a_uint8_t res:4; #elif defined (ADF_BIG_ENDIAN_MACHINE) a_uint8_t res:4; a_uint16_t val:12; #else #error "Please fix" #endif }adf_net_vid_t; /** * @brief Command for setting ring paramters. */ typedef struct { a_uint32_t rx_bufsize; /*Ro field. For shim's that maintain a pool*/ a_uint32_t rx_ndesc; a_uint32_t tx_ndesc; }adf_net_cmd_ring_info_t; /** * @brief Whether the interface is polled or not. If so, the polling bias (number of * packets it wants to process per invocation */ typedef struct { a_bool_t polled; a_uint32_t poll_wt; }adf_net_cmd_poll_info_t; /** * @brief Basic device info */ typedef struct { a_uint8_t if_name[ADF_NET_IF_NAME_SIZE]; a_uint8_t dev_addr[ADF_NET_MAC_ADDR_MAX_LEN]; }adf_net_dev_info_t; typedef struct adf_dma_info { adf_os_dma_mask_t dma_mask; a_uint32_t sg_nsegs; /**< scatter segments */ }adf_net_cmd_dma_info_t; /** * @brief Defines the TX and RX checksumming capabilities/state of the device * The actual checksum handling happens on an adf_nbuf * If offload capability command not supported, all offloads are assumed to be * none. */ typedef enum { ADF_NET_CKSUM_NONE, /*Cannot do any checksum*/ ADF_NET_CKSUM_TCP_UDP_IPv4, /*tcp/udp on ipv4 with pseudo hdr*/ ADF_NET_CKSUM_TCP_UDP_IPv6, /*tcp/udp on ipv6*/ }adf_net_cksum_type_t; typedef struct { adf_net_cksum_type_t tx_cksum; adf_net_cksum_type_t rx_cksum; }adf_net_cksum_info_t; typedef adf_net_cksum_info_t adf_net_cmd_cksum_info_t; /*XXX needed?*/ /** * @brief Command for set/unset vid */ typedef a_uint16_t adf_net_cmd_vid_t ; /*get/set vlan id*/ typedef enum { ADF_NET_TSO_NONE, ADF_NET_TSO_IPV4, /**< for tsp ipv4 only*/ ADF_NET_TSO_ALL, /**< ip4 & ipv6*/ }adf_net_tso_type_t; /** * @brief Command for getting offloading capabilities of a device */ typedef struct { adf_net_cksum_info_t cksum_cap; adf_net_tso_type_t tso; a_uint8_t vlan_supported; }adf_net_cmd_offload_cap_t; /** * @brief Command for getting general stats from a device */ typedef struct { a_uint32_t tx_packets; /**< total packets transmitted*/ a_uint32_t rx_packets; /**< total packets recieved*/ a_uint32_t tx_bytes; /**< total bytes transmitted*/ a_uint32_t rx_bytes; /**< total bytes recieved*/ a_uint32_t tx_dropped; /**< total tx dropped because of lack of buffers*/ a_uint32_t rx_dropped; /**< total rx dropped because of lack of buffers*/ a_uint32_t rx_errors; /**< bad packet recieved*/ a_uint32_t tx_errors; /**< transmisison problems*/ }adf_net_cmd_stats_t; typedef enum adf_net_cmd_mcast_cap{ ADF_NET_MCAST_SUP=0, ADF_NET_MCAST_NOTSUP }adf_net_cmd_mcast_cap_t; typedef struct adf_net_cmd_mcaddr{ a_uint32_t nelem; /**< No. of mcast addresses*/ adf_net_ethaddr_t mcast[ADF_NET_MAX_MCAST_ADDR]; }adf_net_cmd_mcaddr_t; typedef union { adf_net_cmd_link_info_t link_info; adf_net_cmd_poll_info_t poll_info; adf_net_cmd_cksum_info_t cksum_info; adf_net_cmd_ring_info_t ring_info; adf_net_cmd_dma_info_t dma_info; adf_net_cmd_vid_t vid; adf_net_cmd_offload_cap_t offload_cap; adf_net_cmd_stats_t stats; adf_net_cmd_mcaddr_t mcast_info; adf_net_cmd_mcast_cap_t mcast_cap; }adf_net_cmd_data_t; /** * @brief For polled devices, adf_drv responds with one of the following status in * its poll function. */ typedef enum { ADF_NET_POLL_DONE, ADF_NET_POLL_NOT_DONE, ADF_NET_POLL_OOM, }adf_net_poll_resp_t; /** * @brief For recieve checksum API */ typedef enum { ADF_NBUF_RX_CKSUM_NONE, /*device failed to ckecksum*/ ADF_NBUF_RX_CKSUM_HW, /*checksum successful and value returned*/ ADF_NBUF_RX_CKSUM_UNNECESSARY, /*cksum successful, no value*/ }adf_nbuf_rx_cksum_type_t; typedef struct { adf_nbuf_rx_cksum_type_t result; a_uint32_t val; }adf_nbuf_rx_cksum_t; /** * @brief For TCP large Segment Offload */ typedef struct { adf_net_tso_type_t type; a_uint16_t mss; a_uint8_t hdr_off; }adf_nbuf_tso_t; /** * @brief Wireless events * ADF_IEEE80211_ASSOC = station associate (bss mode) * ADF_IEEE80211_REASSOC = station re-associate (bss mode) * ADF_IEEE80211_DISASSOC = station disassociate (bss mode) * ADF_IEEE80211_JOIN = station join (ap mode) * ADF_IEEE80211_LEAVE = station leave (ap mode) * ADF_IEEE80211_SCAN = scan complete, results available * ADF_IEEE80211_REPLAY = sequence counter replay detected * ADF_IEEE80211_MICHAEL = Michael MIC failure detected * ADF_IEEE80211_REJOIN = station re-associate (ap mode) * ADF_CUSTOM_PUSH_BUTTON = */ typedef enum adf_net_wireless_events{ ADF_IEEE80211_ASSOC = __ADF_IEEE80211_ASSOC, ADF_IEEE80211_REASSOC = __ADF_IEEE80211_REASSOC, ADF_IEEE80211_DISASSOC = __ADF_IEEE80211_DISASSOC, ADF_IEEE80211_JOIN = __ADF_IEEE80211_JOIN, ADF_IEEE80211_LEAVE = __ADF_IEEE80211_LEAVE, ADF_IEEE80211_SCAN = __ADF_IEEE80211_SCAN, ADF_IEEE80211_REPLAY = __ADF_IEEE80211_REPLAY, ADF_IEEE80211_MICHAEL = __ADF_IEEE80211_MICHAEL, ADF_IEEE80211_REJOIN = __ADF_IEEE80211_REJOIN, ADF_CUSTOM_PUSH_BUTTON = __ADF_CUSTOM_PUSH_BUTTON }adf_net_wireless_event_t; #endif /*_ADF_NET_TYPES_H*/ adf_net_wcmd.h000077500000000000000000001707461321570333100331460ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** * Copyright (c) Atheros Communications Inc. 2002-2008 * */ #ifndef __ADF_NET_WCMD_H #define __ADF_NET_WCMD_H #include #include #include /** * Defines */ #define ADF_NET_WCMD_NAME_SIZE __ADF_OS_NAME_SIZE #define ADF_NET_WCMD_NICK_NAME 32 /**< Max Device nick name size*/ #define ADF_NET_WCMD_MODE_NAME_LEN 6 #define ADF_NET_WCMD_IE_MAXLEN 256 /** Max Len for IE */ #define ADF_NET_WCMD_MAX_BITRATES 32 #define ADF_NET_WCMD_MAX_ENC_SZ 8 #define ADF_NET_WCMD_MAX_FREQ 32 #define ADF_NET_WCMD_MAX_TXPOWER 8 #define ADF_NET_WCMD_EVENT_CAP 6 /** * @brief key set/get info */ #define ADF_NET_WCMD_KEYBUF_SIZE 16 #define ADF_NET_WCMD_MICBUF_SIZE 16/**< space for tx+rx keys */ #define ADF_NET_WCMD_KEY_DEFAULT 0x80/**< default xmit key */ #define ADF_NET_WCMD_ADDR_LEN 6 #define ADF_NET_WCMD_KEYDATA_SZ \ (ADF_NET_WCMD_KEYBUF_SIZE + ADF_NET_WCMD_MICBUF_SIZE) /** * @brief key flags * XXX: enum's */ #define ADF_NET_WCMD_VAPKEY_XMIT 0x01/**< xmit */ #define ADF_NET_WCMD_VAPKEY_RECV 0x02/**< recv */ #define ADF_NET_WCMD_VAPKEY_GROUP 0x04/**< WPA group*/ #define ADF_NET_WCMD_VAPKEY_SWCRYPT 0x10/**< Encrypt/decrypt*/ #define ADF_NET_WCMD_VAPKEY_SWMIC 0x20/**< Enmic/Demic */ #define ADF_NET_WCMD_VAPKEY_DEFAULT 0x80/**< Default key */ #define ADF_NET_WCMD_MAX_SSID 32 #define ADF_NET_WCMD_CHAN_BYTES 32 #define ADF_NET_WCMD_RTS_DEFAULT 512 #define ADF_NET_WCMD_RTS_MIN 1 #define ADF_NET_WCMD_RTS_MAX 2346 #define ADF_NET_WCMD_FRAG_MIN 256 #define ADF_NET_WCMD_FRAG_MAX 2346 /** * @brief Maximum number of address that you may get in the * list of access ponts */ #define ADF_NET_WCMD_MAX_AP 64 #define ADF_NET_WCMD_RATE_MAXSIZE 30 #define ADF_NET_WCMD_NUM_TR_ENTS 128 /** * @brief Ethtool specific */ #define ADF_NET_WCMD_BUSINFO_LEN 32 #define ADF_NET_WCMD_DRIVSIZ 32 #define ADF_NET_WCMD_VERSIZ 32 #define ADF_NET_WCMD_FIRMSIZ 32 /** * *******************************Enums****************** */ typedef enum adf_net_wcmd_vapmode{ ADF_NET_WCMD_VAPMODE_AUTO, /**< Driver default*/ ADF_NET_WCMD_VAPMODE_ADHOC, /**< Single cell*/ ADF_NET_WCMD_VAPMODE_INFRA, /**< Multi Cell or Roaming*/ ADF_NET_WCMD_VAPMODE_MASTER, /**< Access Point*/ ADF_NET_WCMD_VAPMODE_REPEAT, /**< Wireless Repeater*/ ADF_NET_WCMD_VAPMODE_SECOND, /**< Secondary master or repeater*/ ADF_NET_WCMD_VAPMODE_MONITOR /**< Passive Monitor*/ }adf_net_wcmd_vapmode_t; /** * @brief key type */ typedef enum adf_net_wcmd_ciphermode{ ADF_NET_WCMD_CIPHERMODE_WEP, ADF_NET_WCMD_CIPHERMODE_TKIP, ADF_NET_WCMD_CIPHERMODE_AES_OCB, ADF_NET_WCMD_CIPHERMODE_AES_CCM , ADF_NET_WCMD_CIPHERMODE_RESERVE, ADF_NET_WCMD_CIPHERMODE_CKIP, ADF_NET_WCMD_CIPHERMODE_NONE }adf_net_wcmd_ciphermode_t; /** * @brief Get/Set wireless commands */ typedef enum adf_net_wcmd_type{ /* net80211 */ ADF_NET_WCMD_GET_RTS_THRES, ADF_NET_WCMD_SET_RTS_THRES, ADF_NET_WCMD_GET_FRAGMENT, ADF_NET_WCMD_SET_FRAGMENT, ADF_NET_WCMD_GET_VAPMODE, ADF_NET_WCMD_SET_VAPMODE, ADF_NET_WCMD_GET_BSSID, ADF_NET_WCMD_SET_BSSID, ADF_NET_WCMD_GET_NICKNAME, ADF_NET_WCMD_SET_NICKNAME, ADF_NET_WCMD_GET_FREQUENCY, ADF_NET_WCMD_SET_FREQUENCY, ADF_NET_WCMD_GET_ESSID, ADF_NET_WCMD_SET_ESSID, ADF_NET_WCMD_GET_TX_POWER, ADF_NET_WCMD_SET_TX_POWER, ADF_NET_WCMD_GET_PARAM, ADF_NET_WCMD_SET_PARAM, ADF_NET_WCMD_GET_OPT_IE, ADF_NET_WCMD_SET_OPT_IE, ADF_NET_WCMD_GET_APP_IE_BUF, ADF_NET_WCMD_SET_APP_IE_BUF, ADF_NET_WCMD_SET_ENC, ADF_NET_WCMD_GET_KEY, ADF_NET_WCMD_SET_KEY, ADF_NET_WCMD_GET_SCAN, ADF_NET_WCMD_SET_SCAN, ADF_NET_WCMD_GET_MODE, ADF_NET_WCMD_SET_MODE, ADF_NET_WCMD_GET_CHAN_LIST, ADF_NET_WCMD_SET_CHAN_LIST, ADF_NET_WCMD_GET_WMM_PARAM, ADF_NET_WCMD_SET_WMM_PARAM, ADF_NET_WCMD_GET_VAPNAME, ADF_NET_WCMD_GET_IC_CAPS, ADF_NET_WCMD_GET_RETRIES, ADF_NET_WCMD_GET_WAP_LIST, ADF_NET_WCMD_GET_ADDBA_STATUS, ADF_NET_WCMD_GET_CHAN_INFO, ADF_NET_WCMD_GET_WPA_IE, ADF_NET_WCMD_GET_WSC_IE, ADF_NET_WCMD_SET_TXPOWER_LIMIT, ADF_NET_WCMD_SET_TURBO, ADF_NET_WCMD_SET_FILTER, ADF_NET_WCMD_SET_ADDBA_RESPONSE, ADF_NET_WCMD_SET_MLME, ADF_NET_WCMD_SET_SEND_ADDBA, ADF_NET_WCMD_SET_SEND_DELBA, ADF_NET_WCMD_SET_DELKEY, ADF_NET_WCMD_SET_DELMAC, ADF_NET_WCMD_SET_ADD_MAC, ADF_NET_WCMD_GET_RANGE, ADF_NET_WCMD_GET_POWER, ADF_NET_WCMD_SET_POWER, ADF_NET_WCMD_GET_DEVSTATS, ADF_NET_WCMD_SET_MTU, ADF_NET_WCMD_SET_SYSCTL, ADF_NET_WCMD_GET_STA_STATS,/* stats_sta */ ADF_NET_WCMD_GET_VAP_STATS, /* stats_vap */ ADF_NET_WCMD_GET_STATION_LIST, /* station */ /* Device specific */ ADF_NET_WCMD_SET_DEV_VAP_CREATE, ADF_NET_WCMD_SET_DEV_TX_TIMEOUT, /* XXX:No data definition */ ADF_NET_WCMD_SET_DEV_MODE_INIT, /* XXX:No data definition */ ADF_NET_WCMD_GET_DEV_STATUS, ADF_NET_WCMD_GET_DEV_STATUS_CLR, /* XXX:No data definition */ ADF_NET_WCMD_GET_DEV_DIALOG, ADF_NET_WCMD_GET_DEV_PHYERR, ADF_NET_WCMD_GET_DEV_CWM, ADF_NET_WCMD_GET_DEV_ETHTOOL, ADF_NET_WCMD_SET_DEV_MAC, ADF_NET_WCMD_SET_DEV_CAP,/*ATH_CAP*/ /* Device write specific */ ADF_NET_WCMD_SET_DEV_EIFS_MASK, ADF_NET_WCMD_SET_DEV_EIFS_DUR, ADF_NET_WCMD_SET_DEV_SLOTTIME, ADF_NET_WCMD_SET_DEV_ACKTIMEOUT, ADF_NET_WCMD_SET_DEV_CTSTIMEOUT, ADF_NET_WCMD_SET_DEV_SOFTLED, ADF_NET_WCMD_SET_DEV_LEDPIN, ADF_NET_WCMD_SET_DEV_DEBUG, ADF_NET_WCMD_SET_DEV_TXANTENNA, ADF_NET_WCMD_SET_DEV_RXANTENNA, ADF_NET_WCMD_SET_DEV_DIVERSITY, ADF_NET_WCMD_SET_DEV_TXINTRPERIOD, ADF_NET_WCMD_SET_DEV_FFTXQMIN, ADF_NET_WCMD_SET_DEV_TKIPMIC, ADF_NET_WCMD_SET_DEV_GLOBALTXTIMEOUT, ADF_NET_WCMD_SET_DEV_SW_WSC_BUTTON, /* Device read specific */ ADF_NET_WCMD_GET_DEV_EIFS_MASK, ADF_NET_WCMD_GET_DEV_EIFS_DUR, ADF_NET_WCMD_GET_DEV_SLOTTIME, ADF_NET_WCMD_GET_DEV_ACKTIMEOUT, ADF_NET_WCMD_GET_DEV_CTSTIMEOUT, ADF_NET_WCMD_GET_DEV_SOFTLED, ADF_NET_WCMD_GET_DEV_LEDPIN, ADF_NET_WCMD_GET_DEV_COUNTRYCODE, ADF_NET_WCMD_GET_DEV_REGDOMAIN, ADF_NET_WCMD_GET_DEV_DEBUG, ADF_NET_WCMD_GET_DEV_TXANTENNA, ADF_NET_WCMD_GET_DEV_RXANTENNA, ADF_NET_WCMD_GET_DEV_DIVERSITY, ADF_NET_WCMD_GET_DEV_TXINTRPERIOD, ADF_NET_WCMD_GET_DEV_FFTXQMIN, ADF_NET_WCMD_GET_DEV_TKIPMIC, ADF_NET_WCMD_GET_DEV_GLOBALTXTIMEOUT, ADF_NET_WCMD_GET_DEV_SW_WSC_BUTTON }adf_net_wcmd_type_t; /** * @brief Opmodes for the VAP */ typedef enum adf_net_wcmd_opmode{ ADF_NET_WCMD_OPMODE_IBSS,/**< IBSS (adhoc) station */ ADF_NET_WCMD_OPMODE_STA,/**< Infrastructure station */ ADF_NET_WCMD_OPMODE_WDS,/**< WDS link */ ADF_NET_WCMD_OPMODE_AHDEMO,/**< Old lucent compatible adhoc demo */ ADF_NET_WCMD_OPMODE_RESERVE0,/** /** * @brief Atomic type of variable. * Use this when you want a simple resource counter etc. which is atomic * across multiple CPU's. These maybe slower than usual counters on some * platforms/OS'es, so use them with caution. */ typedef __adf_os_atomic_t adf_os_atomic_t; /** * @brief Initialize an atomic type variable * @param[in] v a pointer to an opaque atomic variable */ static inline void adf_os_atomic_init(adf_os_atomic_t *v) { __adf_os_atomic_init(v); } /** * @brief Read the value of an atomic variable. * @param[in] v a pointer to an opaque atomic variable * * @return the current value of the variable */ static inline a_uint32_t adf_os_atomic_read(adf_os_atomic_t *v) { return (__adf_os_atomic_read(v)); } /** * @brief Increment the value of an atomic variable. * @param[in] v a pointer to an opaque atomic variable */ static inline void adf_os_atomic_inc(adf_os_atomic_t *v) { return (__adf_os_atomic_inc(v)); } /** * @brief Decrement the value of an atomic variable. * @param v a pointer to an opaque atomic variable */ static inline void adf_os_atomic_dec(adf_os_atomic_t *v) { return (__adf_os_atomic_dec(v)); } #endif adf_os_defer.h000077500000000000000000000112271321570333100331200ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** * @ingroup adf_os_public * @file adf_os_defer.h * This file abstracts deferred execution contexts. */ #ifndef __ADF_OS_DEFER_H #define __ADF_OS_DEFER_H #include #include /** * TODO This implements work queues (worker threads, kernel threads etc.). * Note that there is no cancel on a scheduled work. You cannot free a work * item if its queued. You cannot know if a work item is queued or not unless * its running, whence you know its not queued. * * so if, say, a module is asked to unload itself, how exactly will it make * sure that the work's not queued, for OS'es that dont provide such a * mechanism?? */ /** * @brief Representation of a work queue. */ typedef __adf_os_work_t adf_os_work_t; /** * @brief Representation of a bottom half. */ typedef __adf_os_bh_t adf_os_bh_t; /** * @brief This initiallizes the Bottom half deferred handler * * @param[in] hdl OS handle * @param[in] bh bottom instance * @param[in] func deferred function to run at bottom half interrupt * context. * @param[in] arg argument for the deferred function */ static inline void adf_os_init_bh(adf_os_handle_t hdl, adf_os_bh_t *bh, adf_os_defer_fn_t func,void *arg) { __adf_os_init_bh(hdl, bh, func, arg); } /** * @brief schedule a bottom half (DPC) * * @param[in] hdl OS handle * @param[in] bh bottom instance */ static inline void adf_os_sched_bh(adf_os_handle_t hdl, adf_os_bh_t *bh) { __adf_os_sched_bh(hdl, bh); } /** * @brief disable the bh (synchronous) * * @param[in] hdl OS handle * @param[in] bh bottom instance */ static inline void adf_os_disable_bh(adf_os_handle_t hdl, adf_os_bh_t *bh) { __adf_os_disable_bh(hdl,bh); } /*********************Non-Interrupt Context deferred Execution***************/ /** * @brief allocate a work/task queue, This runs in non-interrupt * context, so can be preempted by H/W & S/W intr * * @param[in] hdl OS handle * @param[in] work work instance * @param[in] func deferred function to run at bottom half non-interrupt * context. * @param[in] arg argument for the deferred function */ static inline void adf_os_init_work(adf_os_handle_t hdl, adf_os_work_t *work, adf_os_defer_fn_t func, void *arg) { __adf_os_init_work(hdl, work, func, arg); } /** * @brief Schedule a deferred task on non-interrupt context * * @param[in] hdl OS handle * @param[in] work work instance */ static inline void adf_os_sched_work(adf_os_handle_t hdl, adf_os_work_t *work) { __adf_os_sched_work(hdl, work); } /** *@brief disable the deferred task (synchronous) * *@param[in] hdl OS handle *@param[in] work work instance */ static inline void adf_os_disable_work(adf_os_handle_t hdl, adf_os_work_t *work) { __adf_os_disable_work(hdl, work); } /** * XXX API to specify processor while scheduling a bh => only on vista */ #endif /*_ADF_OS_DEFER_H*/ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/adf_os_dma.h000077500000000000000000000100201321570333100326410ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** * @ingroup adf_os_public * @file adf_os_dma.h * This file abstracts DMA operations. */ #ifndef _ADF_OS_DMA_H #define _ADF_OS_DMA_H #include #include /* * @brief a dma address representation of a platform */ /** * @brief Allocate a DMA buffer and map it to local bus address space * * @param[in] osdev platform device instance * @param[in] size DMA buffer size * @param[in] coherent 0 => cached. * @param[out] dmap opaque coherent memory handle * * @return returns the virtual address of the memory */ static inline void * adf_os_dmamem_alloc(adf_os_device_t osdev, adf_os_size_t size, a_bool_t coherent, adf_os_dma_map_t *dmap) { return __adf_os_dmamem_alloc(osdev, size, coherent, dmap); } /** * @brief Free a previously mapped DMA buffer * * @param[in] osdev platform device instance * @param[in] size DMA buffer size * @param[in] coherent 0 => cached. * @param[in] vaddr virtual address of DMA buffer * @param[in] dmap memory handle */ static inline void adf_os_dmamem_free(adf_os_device_t osdev, adf_os_size_t size, a_bool_t coherent, void *vaddr, adf_os_dma_map_t dmap) { __adf_os_dmamem_free(osdev, size, coherent, vaddr, dmap); } /** * @brief given a dmamem map, returns the (bus) address * * @param[in] dmap memory handle * * @return the (bus) address */ static inline adf_os_dma_addr_t adf_os_dmamem_map2addr(adf_os_dma_map_t dmap) { return(__adf_os_dmamem_map2addr(dmap)); } /** * @brief Flush and invalidate cache for a given dmamem map * * @param[in] osdev platform device instance * @param[in] dmap mem handle * @param[in] op op code for sync type, (see @ref adf_os_types.h) */ static inline void adf_os_dmamem_cache_sync(adf_os_device_t osdev, adf_os_dma_map_t dmap, adf_os_cache_sync_t op) { __adf_os_dmamem_cache_sync(osdev, dmap, op); } /** * @brief Get the cpu cache line size * * @return The CPU cache line size in bytes. */ static inline adf_os_size_t adf_os_cache_line_size(void) { return __adf_os_cache_line_size(); } #endif open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/adf_os_io.h000077500000000000000000000117331321570333100325230ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** * @ingroup adf_os_public * @file adf_os_io.h * This file abstracts I/O operations. */ #ifndef _ADF_OS_IO_H #define _ADF_OS_IO_H #include static inline uint8_t ioread8(const volatile uint32_t addr) { return *(const volatile uint8_t *) addr; } static inline uint16_t ioread16(const volatile uint32_t addr) { return *(const volatile uint16_t *) addr; } static inline uint32_t ioread32(const volatile uint32_t addr) { return *(const volatile uint32_t *) addr; } static inline void iowrite8(volatile uint32_t addr, const uint8_t b) { *(volatile uint8_t *) addr = b; } static inline void iowrite16(volatile uint32_t addr, const uint16_t b) { *(volatile uint16_t *) addr = b; } static inline void iowrite32(volatile uint32_t addr, const uint32_t b) { *(volatile uint32_t *) addr = b; } static inline void io8_rmw(volatile uint32_t addr, const uint8_t set, const uint8_t clr) { uint8_t val; val = ioread8(addr); val &= ~clr; val |= set; iowrite8(addr, val); } static inline void io32_rmw(volatile uint32_t addr, const uint32_t set, const uint32_t clr) { uint32_t val; val = ioread32(addr); val &= ~clr; val |= set; iowrite32(addr, val); } /* generic functions */ #define io8_set(addr, s) io8_rmw((addr), (s), 0) #define io8_clr(addr, c) io8_rmw((addr), 0, (c)) #define io32_set(addr, s) io32_rmw((addr), (s), 0) #define io32_clr(addr, c) io32_rmw((addr), 0, (c)) /* mac specific functions */ #define ioread32_mac(addr) ioread32(WLAN_BASE_ADDRESS + (addr)) #define iowrite32_mac(addr, b) iowrite32(WLAN_BASE_ADDRESS + (addr), (b)) /* usb specific functions */ #define ioread8_usb(addr) ioread8(USB_CTRL_BASE_ADDRESS | (addr)^3) #define ioread16_usb(addr) ioread16(USB_CTRL_BASE_ADDRESS | (addr)) #define ioread32_usb(addr) ioread32(USB_CTRL_BASE_ADDRESS | (addr)) #define iowrite8_usb(addr, b) iowrite8(USB_CTRL_BASE_ADDRESS | (addr)^3, (b)) #define iowrite16_usb(addr, b) iowrite16(USB_CTRL_BASE_ADDRESS | (addr), (b)) #define iowrite32_usb(addr, b) iowrite32(USB_CTRL_BASE_ADDRESS | (addr), (b)) #define io8_rmw_usb(addr, s, c) \ io8_rmw(USB_CTRL_BASE_ADDRESS | (addr)^3, (s), (c)) #define io8_set_usb(addr, s) \ io8_rmw(USB_CTRL_BASE_ADDRESS | (addr)^3, (s), 0) #define io8_clr_usb(addr, c) \ io8_rmw(USB_CTRL_BASE_ADDRESS | (addr)^3, 0, (c)) #define io32_rmw_usb(addr, s, c) \ io32_rmw(USB_CTRL_BASE_ADDRESS | (addr), (s), (c)) #define io32_set_usb(addr, s) io32_rmw(USB_CTRL_BASE_ADDRESS | (addr), (s), 0) #define io32_clr_usb(addr, c) io32_rmw(USB_CTRL_BASE_ADDRESS | (addr), 0, (c)) /** * @brief Convert a 16-bit value from network byte order to host byte order */ #define adf_os_ntohs(x) __adf_os_ntohs(x) /** * @brief Convert a 32-bit value from network byte order to host byte order */ #define adf_os_ntohl(x) __adf_os_ntohl(x) /** * @brief Convert a 16-bit value from host byte order to network byte order */ #define adf_os_htons(x) __adf_os_htons(x) /** * @brief Convert a 32-bit value from host byte order to network byte order */ #define adf_os_htonl(x) __adf_os_htonl(x) /** * @brief Convert a 16-bit value from CPU byte order to little-endian byte order */ #define adf_os_cpu_to_le16(x) __adf_os_cpu_to_le16(x) #endif open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/adf_os_irq.h000077500000000000000000000040361321570333100327050ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __ADF_OS_IRQ_H #define __ADF_OS_IRQ_H #include #include static inline int adf_os_setup_intr(adf_os_device_t osdev, adf_os_drv_intr fn) { return __adf_os_setup_intr(osdev, fn); } static inline void adf_os_free_intr(adf_os_device_t osdev) { __adf_os_free_intr(osdev); } #endif adf_os_lock.h000077500000000000000000000107441321570333100327660ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** * @ingroup adf_os_public * @file adf_os_lock.h * This file abstracts locking operations. */ #ifndef _ADF_OS_LOCK_H #define _ADF_OS_LOCK_H #include #include /** * @brief Platform spinlock object */ typedef __adf_os_spinlock_t adf_os_spinlock_t; /** * @brief Platform mutex object */ typedef __adf_os_mutex_t adf_os_mutex_t; /** * @brief Initialize a mutex * * @param[in] m mutex to initialize */ static inline void adf_os_init_mutex(adf_os_mutex_t *m) { __adf_os_init_mutex(m); } /** * @brief Take the mutex * * @param[in] m mutex to take */ static inline int adf_os_mutex_acquire(adf_os_mutex_t *m) { return (__adf_os_mutex_acquire(m)); } /** * @brief Give the mutex * * @param[in] m mutex to give */ static inline void adf_os_mutex_release(adf_os_mutex_t *m) { __adf_os_mutex_release(m); } /** * @brief Initialize a spinlock * * @param[in] lock spinlock object pointer */ static inline void adf_os_spinlock_init(adf_os_spinlock_t *lock) { __adf_os_spinlock_init(lock); } /** * @brief Acquire a spinlock by disabling the interrupts * * @param[in] lock spinlock object pointer * @param[out] flags flags used to hold interrupt state */ static inline void adf_os_spin_lock_irq(adf_os_spinlock_t *lock, a_uint32_t *flags) { __adf_os_spin_lock_irq(lock,flags); } /** * @brief Release a spinlock & restore the irq * * @param[in] lock spinlock object pointer * @param[in] flags flags filled in by @ref adf_os_spin_lock_irq */ static inline void adf_os_spin_unlock_irq(adf_os_spinlock_t *lock, a_uint32_t *flags) { __adf_os_spin_unlock_irq(lock,flags); } /** * @brief locks the spinlock mutex in soft irq context * * @param[in] lock spinlock object pointer */ static inline void adf_os_spin_lock_bh(adf_os_spinlock_t *lock) { __adf_os_spin_lock_bh(lock); } /** * @brief unlocks the spinlock mutex in soft irq context * * @param[in] lock spinlock object pointer */ static inline void adf_os_spin_unlock_bh(adf_os_spinlock_t *lock) { __adf_os_spin_unlock_bh(lock); } /** * @brief Execute the input function with spinlock held and interrupt disabled. * * @param[in] hdl OS handle * @param[in] lock spinlock to be held for the critical region * @param[in] func critical region function that to be executed * @param[in] context context of the critical region function * * @return Boolean status returned by the critical region function */ static inline a_bool_t adf_os_spinlock_irq_exec(adf_os_handle_t hdl, adf_os_spinlock_t *lock, adf_os_irqlocked_func_t func, void *arg) { return __adf_os_spinlock_irq_exec(hdl, lock, func, arg); } #endif open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/adf_os_mem.h000077500000000000000000000074221321570333100326720ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** * @ingroup adf_os_public * @file adf_os_mem.h * This file abstracts memory operations. */ #ifndef _ADF_OS_MEM_H #define _ADF_OS_MEM_H #include #include /** * @brief Allocate a memory buffer. Note this call can block. * * @param[in] size buffer size * * @return Buffer pointer or NULL if there's not enough memory. */ static inline void * adf_os_mem_alloc(adf_os_size_t size) { return __adf_os_mem_alloc(size); } /** * @brief Free malloc'ed buffer * * @param[in] buf buffer pointer allocated by @ref adf_os_mem_alloc */ static inline void adf_os_mem_free(void *buf) { __adf_os_mem_free(buf); } /** * @brief Move a memory buffer. Overlapping regions are not allowed. * * @param[in] dst destination address * @param[in] src source address * @param[in] size buffer size */ static inline void adf_os_mem_copy(void *dst, const void *src, adf_os_size_t size) { __adf_os_mem_copy(dst, src, size); } /** * @brief Does a non-destructive copy of memory buffer * * @param[in] dst destination address * @param[in] src source address * @param[in] size buffer size */ static inline void adf_os_mem_move(void *dst, void *src, adf_os_size_t size) { __adf_os_mem_move(dst,src,size); } /** * @brief Fill a memory buffer * * @param[in] buf buffer to be filled * @param[in] b byte to fill * @param[in] size buffer size */ static inline void adf_os_mem_set(void *buf, a_uint8_t b, adf_os_size_t size) { __adf_os_mem_set(buf, b, size); } /** * @brief Zero a memory buffer * * @param[in] buf buffer to be zeroed * @param[in] size buffer size */ static inline void adf_os_mem_zero(void *buf, adf_os_size_t size) { __adf_os_mem_zero(buf, size); } /** * @brief Compare two memory buffers * * @param[in] buf1 first buffer * @param[in] buf2 second buffer * @param[in] size buffer size * * @retval 0 equal * @retval 1 not equal */ static inline int adf_os_mem_cmp(void *buf1, void *buf2, adf_os_size_t size) { return __adf_os_mem_cmp(buf1, buf2, size); } #endif adf_os_module.h000077500000000000000000000103471321570333100333220ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** * @ingroup adf_os_public * @file adf_os_module.h * This file abstracts "kernel module" semantics. */ #ifndef _ADF_OS_MODULE_H #define _ADF_OS_MODULE_H #include typedef a_status_t (*module_init_func_t)(void); /** * @brief Specify the module's entry point. */ #define adf_os_virt_module_init(_mod_init_func) __adf_os_virt_module_init(_mod_init_func) /** * @brief Specify the module's exit point. */ #define adf_os_virt_module_exit(_mod_exit_func) __adf_os_virt_module_exit(_mod_exit_func) /** * @brief Specify the module's dependency on another module. */ #define adf_os_module_dep(_name,_dep) __adf_os_module_dep(_name,_dep) /** * @brief Export a symbol from a module. */ #define adf_os_export_symbol(_sym) __adf_os_export_symbol(_sym) /** * @brief Module parameter of type integer. */ #define ADF_OS_PARAM_TYPE_INT32 __ADF_OS_PARAM_TYPE_INT32 /** * @brief Module parameter of type string. */ #define ADF_OS_PARAM_TYPE_STRING __ADF_OS_PARAM_TYPE_STRING /** * @brief Declare a module parameter. * * @param[in] name name of the parameter * @param[in] type type of the parameter * * @note These provide the config data defined by the userland * for this device. It can be queried at any time, given the name string * Only two types are supported * ADF_OS_PARAM_TYPE_STRING * ADF_OS_PARAM_TYPE_INT32 * For example, say, the parameters name "my_int" and "my_name" are of * variables of type int and string respectively. Then you would declare them * as follows: * @code * adf_os_declare_param(my_int, ADF_OS_PARAM_TYPE_INT32); * adf_os_declare_param(my_name, ADF_OS_PARAM_TYPE_STRING); * @endcode * To read the userland provided config value, you would do something like * * @code * adf_os_read_param(my_name, &softc->sc_my_name); * @endcode * * or * @code * st = adf_os_read_param(my_int, &softc->sc_my_int); * @endcode * st could be : * * A_STATUS_OK * A_STATUS_ENOMEM * A_STATUS_ENOENT * */ #define adf_os_declare_param(_name, _type) __adf_os_declare_param(_name, _type) /** * @brief Read a parameter's value * * @param[in] osdev os handle * @param[in] name name of parameter * @param[in] type type of parameter * @param[out] val value read * * @note pval is a point to the variable. Therefore, * for strings it is a_uint8_t ** * for integers it is a_int_t * */ #define adf_os_read_param(_osdev, _name, _type, _pval) \ __adf_os_read_param(_osdev, _name, _type, _pval) #endif /*_ADF_OS_MODULE_H*/ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/adf_os_pci.h000077500000000000000000000111531321570333100326630ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** * @ingroup adf_os_public * @file adf_os_pci.h * This file abstracts the PCI subsystem. */ #ifndef __ADF_OS_PCI_H #define __ADF_OS_PCI_H #include /** * @brief Define the entry point for the PCI module. */ #define adf_os_pci_module_init(_fn) __adf_os_pci_module_init(_fn) /** * @brief Define the exit point for the PCI module. */ #define adf_os_pci_module_exit(_fn) __adf_os_pci_module_exit(_fn) /** * @brief Setup the following driver information: name, PCI IDs of devices * supported and some device handlers. */ #define adf_os_pci_set_drv_info(_name, _pci_ids, _attach, _detach, _suspend, _resume) \ __adf_os_pci_set_drv_info(_name, _pci_ids, _attach, _detach, _suspend, _resume) /** * @brief Read a byte of PCI config space. * * @param[in] osdev platform device instance * @param[in] offset offset to read * @param[out] val value read * * @return status of operation */ static inline int adf_os_pci_config_read8(adf_os_device_t osdev, int offset, a_uint8_t *val) { return __adf_os_pci_config_read8(osdev, offset, val); } /** * @brief Write a byte to PCI config space. * * @param[in] osdev platform device instance * @param[in] offset offset to write * @param[in] val value to write * * @return status of operation */ static inline int adf_os_pci_config_write8(adf_os_device_t osdev, int offset, a_uint8_t val) { return __adf_os_pci_config_write8(osdev, offset, val); } /** * @brief Read 2 bytes of PCI config space. * * @param[in] osdev platform device instance * @param[in] offset offset to read * @param[out] val value read * * @return status of operation */ static inline int adf_os_pci_config_read16(adf_os_device_t osdev, int offset, a_uint16_t *val) { return __adf_os_pci_config_read16(osdev, offset, val); } /** * @brief Write 2 bytes to PCI config space. * * @param[in] osdev platform device instance * @param[in] offset offset to write * @param[in] val value to write * * @return status of operation */ static inline int adf_os_pci_config_write16(adf_os_device_t osdev, int offset, a_uint16_t val) { return __adf_os_pci_config_write16(osdev, offset, val); } /** * @brief Read 4 bytes of PCI config space. * * @param[in] osdev platform device instance * @param[in] offset offset to read * @param[out] val value read * * @return status of operation */ static inline int adf_os_pci_config_read32(adf_os_device_t osdev, int offset, a_uint32_t *val) { return __adf_os_pci_config_read32(osdev, offset, val); } /** * @brief Write 4 bytes to PCI config space. * * @param[in] osdev platform device instance * @param[in] offset offset to write * @param[in] val value to write * * @return status of operation */ static inline int adf_os_pci_config_write32(adf_os_device_t osdev, int offset, a_uint32_t val) { return __adf_os_pci_config_write32(osdev, offset, val); } #endif adf_os_stdtypes.h000077500000000000000000000044631321570333100337160ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** * @defgroup adf_os_public OS abstraction API */ /** * @ingroup adf_os_public * @file adf_os_stdtypes.h * This file defines standard types. */ #ifndef _ADF_OS_STDTYPES_H #define _ADF_OS_STDTYPES_H #include /** * @brief basic data types. */ typedef enum { A_FALSE, A_TRUE }a_bool_t; typedef __a_uint8_t a_uint8_t; typedef __a_int8_t a_int8_t; typedef __a_uint16_t a_uint16_t; typedef __a_int16_t a_int16_t; typedef __a_uint32_t a_uint32_t; typedef __a_int32_t a_int32_t; typedef __a_uint64_t a_uint64_t; typedef __a_int64_t a_int64_t; #endif adf_os_time.h000077500000000000000000000066151321570333100327760ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** * @ingroup adf_os_public * @file adf_os_time.h * This file abstracts time related functionality. */ #ifndef _ADF_OS_TIME_H #define _ADF_OS_TIME_H #include /** * @brief count the number of ticks elapsed from the time when * the system booted * * @return ticks */ static inline unsigned long adf_os_ticks(void) { return __adf_os_ticks(); } /** * @brief convert ticks to milliseconds * * @param[in] ticks number of ticks * @return time in milliseconds */ static inline a_uint32_t adf_os_ticks_to_msecs(unsigned long ticks) { return (__adf_os_ticks_to_msecs(ticks)); } /** * @brief convert milliseconds to ticks * * @param[in] time in milliseconds * @return number of ticks */ static inline unsigned long adf_os_msecs_to_ticks(a_uint32_t msecs) { return (__adf_os_msecs_to_ticks(msecs)); } /** * @brief Return a monotonically increasing time. This increments once per HZ ticks */ static inline unsigned long adf_os_getuptime(void) { return (__adf_os_getuptime()); } /** * @brief Delay in microseconds * * @param[in] microseconds to delay */ static inline void adf_os_udelay(int usecs) { __adf_os_udelay(usecs); } /** * @brief Delay in milliseconds. * * @param[in] milliseconds to delay */ static inline void adf_os_mdelay(int msecs) { __adf_os_mdelay(msecs); } /** * @brief Check if _a is later than _b. */ #define adf_os_time_after(_a, _b) __adf_os_time_after(_a, _b) /** * @brief Check if _a is prior to _b. */ #define adf_os_time_before(_a, _b) __adf_os_time_before(_a, _b) /** * @brief Check if _a atleast as recent as _b, if not later. */ #define adf_os_time_after_eq(_a, _b) __adf_os_time_after_eq(_a, _b) #endif adf_os_timer.h000077500000000000000000000060211321570333100331470ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** * @ingroup adf_os_public * @file adf_os_timer.h * This file abstracts OS timers. */ #ifndef _ADF_OS_TIMER_H #define _ADF_OS_TIMER_H #include #include /** * @brief Platform timer object */ typedef __adf_os_timer_t adf_os_timer_t; /** * @brief Initialize a timer * * @param[in] hdl OS handle * @param[in] timer timer object pointer * @param[in] func timer function * @param[in] context context of timer function */ static inline void adf_os_timer_init(adf_os_handle_t hdl, adf_os_timer_t *timer, adf_os_timer_func_t func, void *arg) { __adf_os_timer_init(hdl, timer, func, arg); } /** * @brief Start a one-shot timer * * @param[in] timer timer object pointer * @param[in] msec expiration period in milliseconds */ static inline void adf_os_timer_start(adf_os_timer_t *timer, int msec) { __adf_os_timer_start(timer, msec); } /** * @brief Cancel a timer * * @param[in] timer timer object pointer * * @retval TRUE timer was cancelled and deactived * @retval FALSE timer was cancelled but already got fired. */ static inline a_bool_t adf_os_timer_cancel(adf_os_timer_t *timer) { return __adf_os_timer_cancel(timer); } #endif adf_os_types.h000077500000000000000000000220211321570333100331710ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** * @ingroup adf_os_public * @file adf_os_types.h * This file defines types used in the OS abstraction API. */ #ifndef _ADF_OS_TYPES_H #define _ADF_OS_TYPES_H #include #include #define ADF_OS_MAX_SCATTER __ADF_OS_MAX_SCATTER /** * @brief Max number of scatter-gather segments. */ #define ADF_OS_MAX_SGLIST 4 /** * @brief denotes structure is packed. */ #define adf_os_packed __adf_os_packed /** * @brief handles opaque to each other */ typedef void * adf_net_handle_t; typedef void * adf_drv_handle_t; typedef void * adf_os_handle_t; /* * XXX FIXME For compilation only. * */ typedef void * adf_os_pm_t; /** * @brief Platform/bus generic handle. Used for bus specific functions. */ typedef __adf_os_device_t adf_os_device_t; /** * @brief size of an object */ typedef __adf_os_size_t adf_os_size_t; /** * @brief offset for API's that need them. */ typedef __adf_os_off_t adf_os_off_t; /** * @brief DMA mapping object. */ typedef __adf_os_dma_map_t adf_os_dma_map_t; /** * @brief DMA address. */ typedef __adf_os_dma_addr_t adf_os_dma_addr_t; /** * @brief DMA size. */ typedef __adf_os_dma_size_t adf_os_dma_size_t; /** * @brief Information inside a DMA map. */ typedef struct adf_os_dmamap_info{ a_uint32_t nsegs; /**< total number mapped segments*/ struct __dma_segs{ adf_os_dma_addr_t paddr; /**< physical(dma'able) address of the segment*/ adf_os_dma_size_t len; /**< length of the segment*/ } dma_segs[ADF_OS_MAX_SCATTER]; }adf_os_dmamap_info_t; /** * @brief Representation of a scatter-gather list. */ typedef struct adf_os_sglist{ a_uint32_t nsegs; /**< total number of segments*/ struct __sg_segs{ a_uint8_t *vaddr; /**< Virtual address of the segment*/ a_uint32_t len; /**< Length of the segment*/ } sg_segs[ADF_OS_MAX_SGLIST]; }adf_os_sglist_t; /** * @brief All operations specified below are performed from * the host memory point of view, where a read * implies data coming from the device to the host * memory, and a write implies data going from the * host memory to the device. Alternately, the * operations can be thought of in terms of driver * operations, where reading a network packet or * storage sector corresponds to a read operation in * bus_dma. * * ADF_SYNC_PREREAD Perform any synchronization * required prior to an update * of host memory by the DMA * read operation. * ADF_SYNC_PREWRITE Perform any synchronization * required after an update of * host memory by the CPU and * prior to DMA write * operations. * ADF_SYNC_POSTREAD Perform any synchronization * required after DMA read * operations and prior to CPU * access to host * memory. * ADF_SYNC_POSTWRITE Perform any synchronization * required after DMA write * operations. */ typedef enum adf_os_cache_sync{ ADF_SYNC_PREREAD=__ADF_SYNC_PREREAD, ADF_SYNC_PREWRITE=__ADF_SYNC_PREWRITE, ADF_SYNC_POSTREAD=__ADF_SYNC_POSTREAD, ADF_SYNC_POSTWRITE=__ADF_SYNC_POSTWRITE }adf_os_cache_sync_t; /** * @brief Generic status to be used by adf_drv. */ typedef enum { A_STATUS_OK, A_STATUS_FAILED, A_STATUS_ENOENT, A_STATUS_ENOMEM, A_STATUS_EINVAL, A_STATUS_EINPROGRESS, A_STATUS_ENOTSUPP, A_STATUS_EBUSY, A_STATUS_E2BIG, A_STATUS_EADDRNOTAVAIL, A_STATUS_ENXIO, A_STATUS_EFAULT, A_STATUS_EIO, } a_status_t; /** * @brief An ecore needs to provide a table of all pci device/vendor id's it * supports * * This table should be terminated by a NULL entry , i.e. {0} */ typedef struct { a_uint32_t vendor; a_uint32_t device; a_uint32_t subvendor; a_uint32_t subdevice; }adf_os_pci_dev_id_t; #define ADF_OS_PCI_ANY_ID (~0) /** * @brief Typically core's can use this macro to create a table of various device * ID's */ #define ADF_OS_PCI_DEVICE(_vendor, _device) \ (_vendor), (_device), ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID #define adf_os_iomem_t __adf_os_iomem_t; /** * @brief These define the hw resources the OS has allocated for the device * Note that start defines a mapped area. */ typedef enum { ADF_OS_RESOURCE_TYPE_MEM, ADF_OS_RESOURCE_TYPE_IO, }adf_os_resource_type_t; /** * @brief Representation of a h/w resource. */ typedef struct { a_uint64_t start; a_uint64_t end; adf_os_resource_type_t type; }adf_os_resource_t; #define ADF_OS_DEV_ID_TABLE_MAX 256 /** * @brief Representation of bus registration data. */ typedef union { adf_os_pci_dev_id_t *pci; void *raw; }adf_os_bus_reg_data_t; /** * @brief Representation of data required for attach. */ typedef union { adf_os_pci_dev_id_t pci; void *raw; }adf_os_attach_data_t; #define ADF_OS_REGIONS_MAX 5 /** * @brief Types of buses. */ typedef enum { ADF_OS_BUS_TYPE_PCI = 1, ADF_OS_BUS_TYPE_GENERIC, }adf_os_bus_type_t; /** * @brief IRQ handler response codes. */ typedef enum { ADF_OS_IRQ_NONE, ADF_OS_IRQ_HANDLED, }adf_os_irq_resp_t; /** * @brief DMA mask types. */ typedef enum { ADF_OS_DMA_MASK_32BIT, ADF_OS_DMA_MASK_64BIT, }adf_os_dma_mask_t; /** * @brief DMA directions * ADF_OS_DMA_TO_DEVICE (data going from device to memory) * ADF_OS_DMA_FROM_DEVICE (data going from memory to device) */ typedef enum { ADF_OS_DMA_TO_DEVICE = __ADF_OS_DMA_TO_DEVICE, ADF_OS_DMA_FROM_DEVICE = __ADF_OS_DMA_FROM_DEVICE, } adf_os_dma_dir_t; /* * Protoypes shared between public and private headers */ /** * @brief work queue(kernel thread)/DPC function callback */ typedef void (*adf_os_defer_fn_t)(void *); /** * @brief Prototype of the critical region function that is to be * executed with spinlock held and interrupt disalbed */ typedef a_bool_t (*adf_os_irqlocked_func_t)(void *); /** * @brief Prototype of timer function */ typedef void (*adf_os_timer_func_t)(void *); /** * @brief Prototype of IRQ function. */ typedef adf_os_irq_resp_t (*adf_os_drv_intr)(adf_drv_handle_t hdl); /** * @brief The OS print routine. */ #define adf_os_print __adf_os_print /** * @brief driver info structure needed while we do the register * for the driver to the shim. */ typedef struct _adf_drv_info{ /** * @brief driver specific functions */ adf_drv_handle_t (*drv_attach) (adf_os_resource_t *res, int count, adf_os_attach_data_t *data, adf_os_device_t osdev); void (*drv_detach) (adf_drv_handle_t hdl); void (*drv_suspend) (adf_drv_handle_t hdl, adf_os_pm_t pm); void (*drv_resume) (adf_drv_handle_t hdl); /** * @brief driver specific data */ adf_os_bus_type_t bus_type; adf_os_bus_reg_data_t bus_data; unsigned char *mod_name; unsigned char *ifname; }adf_drv_info_t; #endif adf_os_util.h000077500000000000000000000060051321570333100330060ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** * @ingroup adf_os_public * @file adf_os_util.h * This file defines utility functions. */ #ifndef _ADF_OS_UTIL_H #define _ADF_OS_UTIL_H #include /** * @brief Compiler-dependent macro denoting code likely to execute. */ #define adf_os_unlikely(_expr) __adf_os_unlikely(_expr) /** * @brief Compiler-dependent macro denoting code unlikely to execute. */ #define adf_os_likely(_expr) __adf_os_likely(_expr) /** * @brief read memory barrier. */ #define adf_os_wmb() __adf_os_wmb() /** * @brief write memory barrier. */ #define adf_os_rmb() __adf_os_rmb() /** * @brief read + write memory barrier. */ #define adf_os_mb() __adf_os_mb() /** * @brief return the lesser of a, b */ #define adf_os_min(_a, _b) __adf_os_min(_a, _b) /** * @brief return the larger of a, b */ #define adf_os_max(_a, _b) __adf_os_max(_a, _b) /** * @brief assert "expr" evaluates to true. */ #define adf_os_assert(expr) __adf_os_assert(expr) /** * @brief supply pseudo-random numbers */ static inline void adf_os_get_rand(adf_os_handle_t hdl, a_uint8_t *ptr, a_uint32_t len) { __adf_os_get_rand(hdl, ptr, len); } #endif /*_ADF_OS_UTIL_H*/ allocram_api.h000077500000000000000000000063051321570333100331440ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __ALLOCRAM_API_H__ #define __ALLOCRAM_API_H__ /* API for Target-side startup-time RAM allocations */ struct allocram_api { /* * Initialize allocram, providing it with a block of RAM * (an "arena") from which to allocate. * * If arena_start is 0, a default start -- the end of * the application's text & data -- is used. * * If arena_sz is 0, a default size -- which uses most * of physical RAM beyond arena_start -- is used. * * Return value is reserved for future use -- it's an arena handle. */ void *(* cmnos_allocram_init)(void *arena_start, A_UINT32 arena_sz); /* * Allocate nbytes of memory, returning a pointer to the start * of the allocated block. Allocation size is rounded up to the * nearest A_CACHE_LINE_SIZE and the returned address similarly * aligned. * * There is no need to check the return value from this function. * A failure to satisfy a RAM allocation request is treated as a * fatal error. * * Allocations are expected to occur only during startup; this * API does not, for instance, guarantee atomicity with respect * to allocations that might (foolishly) be attempted from * interrupt handlers. * * The "which_arena" parameter is currently unused, and should * be set to 0 -- only a single arena is currently supported. */ void *(* cmnos_allocram)(void *which_arena, A_UINT32 nbytes); void (* cmnos_allocram_debug)(void); }; extern void allocram_module_install(struct allocram_api *api); #endif /* __ALLOCRAM_API_H__ */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/asf_bitmap.h000077500000000000000000000060501321570333100327020ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _ASF_BITMAP_H_ #define _ASF_BITMAP_H_ #include "adf_os_types.h" #include "adf_os_mem.h" #define ASF_BYTESZ 8 typedef a_uint8_t * asf_bitmap_t; /* Bit map related macros. */ // setbit(a,i) ((a)[(i)/NBBY] |= 1<<((i)%NBBY)) // clrbit(a,i) ((a)[(i)/NBBY] &= ~(1<<((i)%NBBY))) // isset(a,i) ((a)[(i)/NBBY] & (1<<((i)%NBBY))) // isclr(a,i) (((a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0) #define asf_howmany(x, y) (((x)+((y)-1))/(y)) #define asf_roundup(x, y) ((((x)+((y)-1))/(y))*(y)) static inline a_uint8_t * asf_bitmap_alloc(int sz_bits) { a_uint8_t * bm; int sz_bytes = sz_bits / ASF_BYTESZ; bm = adf_os_mem_alloc(sz_bytes); if (bm == NULL) return NULL; adf_os_mem_zero(bm, sz_bytes); return bm; } static inline void asf_bitmap_free(a_uint8_t *bm) { adf_os_mem_free(bm); } static inline void asf_bitmap_setbit(a_uint8_t *bm, int pos) { bm[pos / ASF_BYTESZ] |= 1 << (pos % ASF_BYTESZ); } static inline void asf_bitmap_clrbit(a_uint8_t *bm, int pos) { bm[pos / ASF_BYTESZ] &= ~(1 << (pos % ASF_BYTESZ)); } static inline a_bool_t asf_bitmap_isset(a_uint8_t *bm, int pos) { return bm[pos / ASF_BYTESZ] & (1 << (pos % ASF_BYTESZ)); } static inline a_bool_t asf_bitmap_isclr(a_uint8_t *bm, int pos) { return ((bm[pos / ASF_BYTESZ] & (1 << (pos % ASF_BYTESZ))) == 0); } #endif /* _ASF_BITMAP_H */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/asf_queue.h000077500000000000000000000543111321570333100325550ustar00rootroot00000000000000/* * Copyright (c) 1991, 1993 * The Regents of the University of California. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * @(#)queue.h 8.5 (Berkeley) 8/20/94 * $FreeBSD: src/sys/sys/queue.h,v 1.58 2004/04/07 04:19:49 imp Exp $ * $Id: //depot/sw/branches/fusion_usb/target_firmware/magpie_fw_dev/asf/include/asf_queue.h#1 $ */ #ifndef _ASF_QUEUE_H_ #define _ASF_QUEUE_H_ /** * General purpose routines */ #define asf_offsetof(type, member) ((adf_os_size_t) &((type *)0)->member) #define asf_containerof(ptr, type, member) ({ \ const typeof( ((type *)0)->member ) *__lptr = (ptr); \ (type *)( (char *)__mptr - asf_offsetof(type,member) );}) /* * This file defines four types of data structures: singly-linked lists, * singly-linked tail queues, lists and tail queues. * * A singly-linked list is headed by a single forward pointer. The elements * are singly linked for minimum space and pointer manipulation overhead at * the expense of O(n) removal for arbitrary elements. New elements can be * added to the list after an existing element or at the head of the list. * Elements being removed from the head of the list should use the explicit * macro for this purpose for optimum efficiency. A singly-linked list may * only be traversed in the forward direction. Singly-linked lists are ideal * for applications with large datasets and few or no removals or for * implementing a LIFO queue. * * A singly-linked tail queue is headed by a pair of pointers, one to the * head of the list and the other to the tail of the list. The elements are * singly linked for minimum space and pointer manipulation overhead at the * expense of O(n) removal for arbitrary elements. New elements can be added * to the list after an existing element, at the head of the list, or at the * end of the list. Elements being removed from the head of the tail queue * should use the explicit macro for this purpose for optimum efficiency. * A singly-linked tail queue may only be traversed in the forward direction. * Singly-linked tail queues are ideal for applications with large datasets * and few or no removals or for implementing a FIFO queue. * * A list is headed by a single forward pointer (or an array of forward * pointers for a hash table header). The elements are doubly linked * so that an arbitrary element can be removed without a need to * traverse the list. New elements can be added to the list before * or after an existing element or at the head of the list. A list * may only be traversed in the forward direction. * * A tail queue is headed by a pair of pointers, one to the head of the * list and the other to the tail of the list. The elements are doubly * linked so that an arbitrary element can be removed without a need to * traverse the list. New elements can be added to the list before or * after an existing element, at the head of the list, or at the end of * the list. A tail queue may be traversed in either direction. * * For details on the use of these macros, see the queue(3) manual page. * * * asf_slist asf_list asf_stailq asf_tailq * _head + + + + * _head_initializer + + + + * _entry + + + + * _init + + + + * _empty + + + + * _first + + + + * _next + + + + * _prev - - - + * _last - - + + * _foreach + + + + * _foreach_safe + + + + * _foreach_reverse - - - + * _foreach_reverse_safe - - - + * _insert_head + + + + * _insert_before - + - + * _insert_after + + + + * _insert_tail - - + + * _concat - - + + * _remove_head + - + - * _remove + + + + * */ #define QUEUE_MACRO_DEBUG 0 #if QUEUE_MACRO_DEBUG /* Store the last 2 places the queue element or head was altered */ struct asf_qm_trace { char * lastfile; int lastline; char * prevfile; int prevline; }; #define TRACEBUF struct asf_qm_trace trace #define trashit(x) do {(x) = (void *)-1;} while (0) #define qmd_trace_head(head) do { \ (head)->trace.prevline = (head)->trace.lastline; \ (head)->trace.prevfile = (head)->trace.lastfile; \ (head)->trace.lastline = __LINE__; \ (head)->trace.lastfile = __FILE__; \ } while (0) #define qmd_trace_elem(elem) do { \ (elem)->trace.prevline = (elem)->trace.lastline; \ (elem)->trace.prevfile = (elem)->trace.lastfile; \ (elem)->trace.lastline = __LINE__; \ (elem)->trace.lastfile = __FILE__; \ } while (0) #else #define qmd_trace_elem(elem) #define qmd_trace_head(head) #define TRACEBUF #define trashit(x) #endif /* QUEUE_MACRO_DEBUG */ /* * Singly-linked List declarations. */ #define asf_slist_head(name, type) \ struct name { \ struct type *slh_first; /* first element */ \ } #define asf_slist_head_initializer(head) \ { NULL } #define asf_slist_entry(type) \ struct { \ struct type *sle_next; /* next element */ \ } /* * Singly-linked List functions. */ #define asf_slist_empty(head) ((head)->slh_first == NULL) #define asf_slist_first(head) ((head)->slh_first) #define asf_slist_foreach(var, head, field) \ for ((var) = asf_slist_first((head)); \ (var); \ (var) = asf_slist_next((var), field)) #define asf_slist_foreach_safe(var, head, field, tvar) \ for ((var) = asf_slist_first((head)); \ (var) && ((tvar) = asf_slist_next((var), field), 1); \ (var) = (tvar)) #define asf_slist_foreach_prevptr(var, varp, head, field) \ for ((varp) = &asf_slist_first((head)); \ ((var) = *(varp)) != NULL; \ (varp) = &asf_slist_next((var), field)) #define asf_slist_init(head) do { \ asf_slist_first((head)) = NULL; \ } while (0) #define asf_slist_insert_after(slistelm, elm, field) do { \ asf_slist_next((elm), field) = asf_slist_next((slistelm), field); \ asf_slist_next((slistelm), field) = (elm); \ } while (0) #define asf_slist_insert_head(head, elm, field) do { \ asf_slist_next((elm), field) = asf_slist_first((head)); \ asf_slist_first((head)) = (elm); \ } while (0) #define asf_slist_next(elm, field) ((elm)->field.sle_next) #define asf_slist_remove(head, elm, type, field) do { \ if (asf_slist_first((head)) == (elm)) { \ asf_slist_remove_head((head), field); \ } \ else { \ struct type *curelm = asf_slist_first((head)); \ while (asf_slist_next(curelm, field) != (elm)) \ curelm = asf_slist_next(curelm, field); \ asf_slist_next(curelm, field) = \ asf_slist_next(asf_slist_next(curelm, field), field); \ } \ } while (0) #define asf_slist_remove_head(head, field) do { \ asf_slist_first((head)) = asf_slist_next(asf_slist_first((head)), field); \ } while (0) /* * Singly-linked Tail queue declarations. */ #define asf_stailq_head(name, type) \ struct name { \ struct type *stqh_first;/* first element */ \ struct type **stqh_last;/* addr of last next element */ \ } #define asf_stailq_head_initializer(head) \ { NULL, &(head).stqh_first } #define asf_stailq_entry(type) \ struct { \ struct type *stqe_next; /* next element */ \ } /* * Singly-linked Tail queue functions. */ #define asf_stailq_concat(head1, head2) do { \ if (!asf_stailq_empty((head2))) { \ *(head1)->stqh_last = (head2)->stqh_first; \ (head1)->stqh_last = (head2)->stqh_last; \ asf_stailq_init((head2)); \ } \ } while (0) #define asf_stailq_empty(head) ((head)->stqh_first == NULL) #define asf_stailq_first(head) ((head)->stqh_first) #define asf_stailq_foreach(var, head, field) \ for((var) = asf_stailq_first((head)); \ (var); \ (var) = asf_stailq_next((var), field)) #define asf_stailq_foreach_safe(var, head, field, tvar) \ for ((var) = asf_stailq_first((head)); \ (var) && ((tvar) = asf_stailq_next((var), field), 1); \ (var) = (tvar)) #define asf_stailq_init(head) do { \ asf_stailq_first((head)) = NULL; \ (head)->stqh_last = &asf_stailq_first((head)); \ } while (0) #define asf_stailq_insert_after(head, tqelm, elm, field) do { \ if ((asf_stailq_next((elm), field) = asf_stailq_next((tqelm), field)) == NULL)\ (head)->stqh_last = &asf_stailq_next((elm), field); \ asf_stailq_next((tqelm), field) = (elm); \ } while (0) #define asf_stailq_insert_head(head, elm, field) do { \ if ((asf_stailq_next((elm), field) = asf_stailq_first((head))) == NULL) \ (head)->stqh_last = &asf_stailq_next((elm), field); \ asf_stailq_first((head)) = (elm); \ } while (0) #define asf_stailq_insert_tail(head, elm, field) do { \ asf_stailq_next((elm), field) = NULL; \ *(head)->stqh_last = (elm); \ (head)->stqh_last = &asf_stailq_next((elm), field); \ } while (0) #define asf_stailq_last(head, type, field) \ (asf_stailq_empty((head)) ? \ NULL : \ ((struct type *) \ ((char *)((head)->stqh_last) - __offsetof(struct type, field)))) #define asf_stailq_next(elm, field) ((elm)->field.stqe_next) #define asf_stailq_remove(head, elm, type, field) do { \ if (asf_stailq_first((head)) == (elm)) { \ asf_stailq_remove_head((head), field); \ } \ else { \ struct type *curelm = asf_stailq_first((head)); \ while (asf_stailq_next(curelm, field) != (elm)) \ curelm = asf_stailq_next(curelm, field); \ if ((asf_stailq_next(curelm, field) = \ asf_stailq_next(asf_stailq_next(curelm, field), field)) == NULL)\ (head)->stqh_last = &asf_stailq_next((curelm), field);\ } \ } while (0) #define asf_stailq_remove_after(head, elm, field) do { \ if (asf_stailq_next(elm, field)) { \ if ((asf_stailq_next(elm, field) = \ asf_stailq_next(asf_stailq_next(elm, field), field)) == NULL)\ (head)->stqh_last = &asf_stailq_next((elm), field); \ } \ } while (0) #define asf_stailq_remove_head(head, field) do { \ if ((asf_stailq_first((head)) = \ asf_stailq_next(asf_stailq_first((head)), field)) == NULL) \ (head)->stqh_last = &asf_stailq_first((head)); \ } while (0) #define asf_stailq_remove_head_until(head, elm, field) do { \ if ((asf_stailq_first((head)) = asf_stailq_next((elm), field)) == NULL) \ (head)->stqh_last = &asf_stailq_first((head)); \ } while (0) /* * List declarations. */ #define asf_list_head(name, type) \ struct name { \ struct type *lh_first; /* first element */ \ } #define asf_list_head_initializer(head) \ { NULL } #define asf_list_entry(type) \ struct { \ struct type *le_next; /* next element */ \ struct type **le_prev; /* address of previous next element */ \ } /* * List functions. */ #define asf_list_empty(head) ((head)->lh_first == NULL) #define asf_list_first(head) ((head)->lh_first) #define asf_list_foreach(var, head, field) \ for ((var) = asf_list_first((head)); \ (var); \ (var) = asf_list_next((var), field)) #define asf_list_foreach_safe(var, head, field, tvar) \ for ((var) = asf_list_first((head)); \ (var) && ((tvar) = asf_list_next((var), field), 1); \ (var) = (tvar)) #define asf_list_init(head) do { \ asf_list_first((head)) = NULL; \ } while (0) #define asf_list_insert_after(listelm, elm, field) do { \ if ((asf_list_next((elm), field) = asf_list_next((listelm), field)) != NULL)\ asf_list_next((listelm), field)->field.le_prev = \ &asf_list_next((elm), field); \ asf_list_next((listelm), field) = (elm); \ (elm)->field.le_prev = &asf_list_next((listelm), field); \ } while (0) #define asf_list_insert_before(listelm, elm, field) do { \ (elm)->field.le_prev = (listelm)->field.le_prev; \ asf_list_next((elm), field) = (listelm); \ *(listelm)->field.le_prev = (elm); \ (listelm)->field.le_prev = &asf_list_next((elm), field); \ } while (0) #define asf_list_insert_head(head, elm, field) do { \ if ((asf_list_next((elm), field) = asf_list_first((head))) != NULL) \ asf_list_first((head))->field.le_prev = &asf_list_next((elm), field);\ asf_list_first((head)) = (elm); \ (elm)->field.le_prev = &asf_list_first((head)); \ } while (0) #define asf_list_next(elm, field) ((elm)->field.le_next) #define asf_list_remove(elm, field) do { \ if (asf_list_next((elm), field) != NULL) \ asf_list_next((elm), field)->field.le_prev = \ (elm)->field.le_prev; \ *(elm)->field.le_prev = asf_list_next((elm), field); \ } while (0) /* * Tail queue declarations. */ #define asf_tailq_head(name, type) \ struct name { \ struct type *tqh_first; /* first element */ \ struct type **tqh_last; /* addr of last next element */ \ TRACEBUF; \ } #define asf_tailq_head_initializer(head) \ { NULL, &(head).tqh_first } #define asf_tailq_entry(type) \ struct { \ struct type *tqe_next; /* next element */ \ struct type **tqe_prev; /* address of previous next element */ \ TRACEBUF; \ } /* * Tail queue functions. */ #define asf_tailq_concat(head1, head2, field) do { \ if (!asf_tailq_empty(head2)) { \ *(head1)->tqh_last = (head2)->tqh_first; \ (head2)->tqh_first->field.tqe_prev = (head1)->tqh_last; \ (head1)->tqh_last = (head2)->tqh_last; \ asf_tailq_init((head2)); \ qmd_trace_head(head); \ qmd_trace_head(head2); \ } \ } while (0) #define asf_tailq_empty(head) ((head)->tqh_first == NULL) #define asf_tailq_first(head) ((head)->tqh_first) #define asf_tailq_foreach(var, head, field) \ for ((var) = asf_tailq_first((head)); \ (var); \ (var) = asf_tailq_next((var), field)) #define asf_tailq_foreach_safe(var, head, field, tvar) \ for ((var) = asf_tailq_first((head)); \ (var) && ((tvar) = asf_tailq_next((var), field), 1); \ (var) = (tvar)) #define asf_tailq_foreach_reverse(var, head, headname, field) \ for ((var) = asf_tailq_last((head), headname); \ (var); \ (var) = asf_tailq_prev((var), headname, field)) #define asf_tailq_foreach_reverse_safe(var, head, headname, field, tvar) \ for ((var) = asf_tailq_last((head), headname); \ (var) && ((tvar) = asf_tailq_prev((var), headname, field), 1); \ (var) = (tvar)) #define asf_tailq_init(head) do { \ asf_tailq_first((head)) = NULL; \ (head)->tqh_last = &asf_tailq_first((head)); \ qmd_trace_head(head); \ } while (0) #define asf_tailq_insert_after(head, listelm, elm, field) do { \ if ((asf_tailq_next((elm), field) = asf_tailq_next((listelm), field)) != NULL)\ asf_tailq_next((elm), field)->field.tqe_prev = \ &asf_tailq_next((elm), field); \ else { \ (head)->tqh_last = &asf_tailq_next((elm), field); \ qmd_trace_head(head); \ } \ asf_tailq_next((listelm), field) = (elm); \ (elm)->field.tqe_prev = &asf_tailq_next((listelm), field); \ qmd_trace_elem(&(elm)->field); \ qmd_trace_elem(&listelm->field); \ } while (0) #define asf_tailq_insert_before(listelm, elm, field) do { \ (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \ asf_tailq_next((elm), field) = (listelm); \ *(listelm)->field.tqe_prev = (elm); \ (listelm)->field.tqe_prev = &asf_tailq_next((elm), field); \ qmd_trace_elem(&(elm)->field); \ qmd_trace_elem(&listelm->field); \ } while (0) #define asf_tailq_insert_head(head, elm, field) do { \ if ((asf_tailq_next((elm), field) = asf_tailq_first((head))) != NULL) \ asf_tailq_first((head))->field.tqe_prev = \ &asf_tailq_next((elm), field); \ else \ (head)->tqh_last = &asf_tailq_next((elm), field); \ asf_tailq_first((head)) = (elm); \ (elm)->field.tqe_prev = &asf_tailq_first((head)); \ qmd_trace_head(head); \ qmd_trace_elem(&(elm)->field); \ } while (0) #define asf_tailq_insert_tail(head, elm, field) do { \ asf_tailq_next((elm), field) = NULL; \ (elm)->field.tqe_prev = (head)->tqh_last; \ *(head)->tqh_last = (elm); \ (head)->tqh_last = &asf_tailq_next((elm), field); \ qmd_trace_head(head); \ qmd_trace_elem(&(elm)->field); \ } while (0) #define asf_tailq_last(head, headname) \ (*(((struct headname *)((head)->tqh_last))->tqh_last)) #define asf_tailq_next(elm, field) ((elm)->field.tqe_next) #define asf_tailq_prev(elm, headname, field) \ (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last)) #define asf_tailq_remove(head, elm, field) do { \ if ((asf_tailq_next((elm), field)) != NULL) \ asf_tailq_next((elm), field)->field.tqe_prev = \ (elm)->field.tqe_prev; \ else { \ (head)->tqh_last = (elm)->field.tqe_prev; \ qmd_trace_head(head); \ } \ *(elm)->field.tqe_prev = asf_tailq_next((elm), field); \ trashit((elm)->field.tqe_next); \ trashit((elm)->field.tqe_prev); \ qmd_trace_elem(&(elm)->field); \ } while (0) #ifdef _KERNEL /* * XXX asf_insque() and remque() are an old way of handling certain queues. * They bogusly assumes that all queue heads look alike. */ struct asf_qhead { struct asf_qhead *qh_link; struct asf_qhead *qh_rlink; }; #if defined(__GNUC__) || defined(__INTEL_COMPILER) static __inline void asf_insque(void *a, void *b) { struct asf_qhead *element = (struct asf_qhead *)a, *head = (struct asf_qhead *)b; element->qh_link = head->qh_link; element->qh_rlink = head; head->qh_link = element; element->qh_link->qh_rlink = element; } static __inline void asf_remque(void *a) { struct asf_qhead *element = (struct asf_qhead *)a; element->qh_link->qh_rlink = element->qh_rlink; element->qh_rlink->qh_link = element->qh_link; element->qh_rlink = 0; } #else /* !(__GNUC__ || __INTEL_COMPILER) */ void asf_insque(void *a, void *b); void asf_remque(void *a); #endif /* __GNUC__ || __INTEL_COMPILER */ #endif /* _KERNEL */ #endif /* !_ASF_QUEUE_H_ */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/athos_api.h000077500000000000000000000105141321570333100325440ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __ATHOS_API_H__ #define __ATHOS_API_H__ /* * This file contains wrappers to OS operating system functions * that are available in the Athos version of the operating system. * * Target software must always use these wrappers to access OS * services -- it may not access any OS services directly. * * These wrappers are intended to provide OS-independence for applications. * Using this header file, an application should be able to compile and * fully link without any other OS header files, source files, or * binary files. */ #include #include "dt_defs.h" #include "cmnos_api.h" #include "Magpie_api.h" /* ROM Patch API */ /* save the ROM printf function point */ extern int (* save_cmnos_printf)(const char * fmt, ...); extern unsigned int _data_start_in_rom; extern unsigned int _data_start; extern unsigned int _data_end; extern unsigned int _bss_start; extern unsigned int _bss_end; extern unsigned int _stack_sentry; extern unsigned int __stack; extern unsigned int _fw_image_end; #if defined(__XTENSA__) #define START_DATA _data_start #define END_DATA _data_end #define START_BSS _bss_start #define END_BSS _bss_end #define STACK_START _stack_sentry #define STACK_END __stack #endif struct _A_os_linkage_check { int version; int table; }; /* * A_INIT() handles any initialization needed by the OS abstraction, * and it clears the application's BSS, if necessary. (Application BSS * is not cleared if the application is linked into a single image that * includes AthOS.) * * A_INIT() must be called first thing in the application (from app_start) * in order to guarantee that BSS has been cleared properly. */ static INLINE int A_INIT(void) { struct _A_os_linkage_check link_check; unsigned int *clrptr; if (&START_BSS != _A_MAGPIE_INDIRECTION_TABLE->cmnos.start_bss) { /* Clear BSS */ for (clrptr = &START_BSS; clrptr < &END_BSS; clrptr++) { *clrptr = 0; } } /* Copy writable data from flash to RAM. */ unsigned int *srcptr, *destptr; /* * The _data_start symbol points to the start of data IN FLASH. * It is defined by flash.ld at application link time. If flash.ld * is not used, it is defined (on the link line) as 0. */ static int *data_start_addr = &_data_start; if (data_start_addr != 0) { for (srcptr = &_data_start, destptr = &START_DATA; destptr < &END_DATA; srcptr++, destptr++) { *destptr = *srcptr; } } #define OS_LINKAGE_VERSION 4 link_check.version = OS_LINKAGE_VERSION; link_check.table = _A_MAGPIE_INDIRECTION_TABLE_SIZE; return A_CMN(hal_linkage_check(sizeof(link_check), &link_check)); } #endif /* __ATHOS_API_H__ */ dma_engine_api.h000077500000000000000000000075751321570333100334520ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * @File: dma_engine_api.h * * @Abstract: DMA Engine api * * @Notes: */ #ifndef _DMA_ENGINE_API_H #define _DMA_ENGINE_API_H #include #include struct zsDmaDesc { #if 1 // BIG_ENDIAN volatile u16_t ctrl; // Descriptor control volatile u16_t status; // Descriptor status volatile u16_t totalLen; // Total length volatile u16_t dataSize; // Data size #else volatile u16_t status; // Descriptor status volatile u16_t ctrl; // Descriptor control volatile u16_t dataSize; // Data size volatile u16_t totalLen; // Total length #endif struct zsDmaDesc* lastAddr; // Last address of this chain volatile u32_t dataAddr; // Data buffer address struct zsDmaDesc* nextAddr; // Next TD address }; struct zsDmaQueue { struct zsDmaDesc* head; struct zsDmaDesc* terminator; }; // Subclass of zsDmaQueue for TX struct zsTxDmaQueue { struct zsDmaDesc* head; struct zsDmaDesc* terminator; /* Below are fields specific to TX */ VBUF *xmited_buf_head; VBUF *xmited_buf_tail; }; /* hardware API table structure (API descriptions below) */ struct dma_engine_api { void (*_init)(); void (*_init_rx_queue)(struct zsDmaQueue *q); void (*_init_tx_queue)(struct zsTxDmaQueue *q); void (*_config_rx_queue)(struct zsDmaQueue *q, int num_desc, int buf_size); void (*_xmit_buf)(struct zsTxDmaQueue *q, VBUF *buf); void (*_flush_xmit)(struct zsDmaQueue *q); VBUF* (*_reap_recv_buf)(struct zsDmaQueue *q); void (*_return_recv_buf)(struct zsDmaQueue *q, VBUF *buf); VBUF* (*_reap_xmited_buf)(struct zsTxDmaQueue *q); void (*_swap_data)(struct zsDmaDesc* desc); int (*_has_compl_packets)(struct zsDmaQueue *q); void (*_desc_dump)(struct zsDmaQueue *q); /* The functions below are for patchable */ struct zsDmaDesc* (*_get_packet)(struct zsDmaQueue* q); void (*_reclaim_packet)(struct zsDmaQueue* q, struct zsDmaDesc* desc); void (*_put_packet)(struct zsDmaQueue* q, struct zsDmaDesc* desc); /* room to expand this table by another table */ void *pReserved; }; extern void dma_engine_module_install(struct dma_engine_api *apis); #endif /* #ifndef _DMA_ENGINE_API_H */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/dma_lib.h000077500000000000000000000064101321570333100321640ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __DMA_LIB_H #define __DMA_LIB_H /***********************External***************************/ /** * @brief DMA engine numbers, HIF need to map them to there * respective order */ typedef enum dma_engine{ DMA_ENGINE_RX0, DMA_ENGINE_RX1, DMA_ENGINE_RX2, DMA_ENGINE_RX3, DMA_ENGINE_TX0, DMA_ENGINE_TX1, DMA_ENGINE_MAX }dma_engine_t; /** * @brief Interface type, each HIF should call with its own interface type */ typedef enum dma_iftype{ DMA_IF_GMAC = 0x0,/* GMAC */ DMA_IF_PCI = 0x1,/*PCI */ DMA_IF_PCIE = 0x2 /*PCI Express */ }dma_iftype_t; struct dma_lib_api{ A_UINT16 (*tx_init)(dma_engine_t eng_no, dma_iftype_t if_type); void (*tx_start)(dma_engine_t eng_no); A_UINT16 (*rx_init)(dma_engine_t eng_no, dma_iftype_t if_type); void (*rx_config)(dma_engine_t eng_no, a_uint16_t num_desc, a_uint16_t gran); void (*rx_start)(dma_engine_t eng_no); A_UINT32 (*intr_status)(dma_iftype_t if_type); A_UINT16 (*hard_xmit)(dma_engine_t eng_no, VBUF *buf); void (*flush_xmit)(dma_engine_t eng_no); A_UINT16 (*xmit_done)(dma_engine_t eng_no); VBUF * (*reap_xmitted)(dma_engine_t eng_no); VBUF * (*reap_recv)(dma_engine_t eng_no); void (*return_recv)(dma_engine_t eng_no, VBUF *buf); A_UINT16 (*recv_pkt)(dma_engine_t eng_no); }; /** * @brief Install the DMA lib api's this for ROM patching * support * * @param apis */ void dma_lib_module_install(struct dma_lib_api *apis); #endif open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/dt_defs.h000077500000000000000000000101511321570333100322020ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /*************************************************************************/ /* Copyright (c) 2006 Atheros Communications, Inc., All Rights Reserved */ /* */ /* Module Name : dt_defs.h */ /* */ /* Abstract */ /* This file contains the common data structure definition. */ /* */ /* NOTES */ /* None */ /* */ /*************************************************************************/ #ifndef _DT_DEFS_H_ #define _DT_DEFS_H_ #ifndef LOCAL #define LOCAL static #endif /* data type definition */ typedef unsigned long uint32_t; typedef unsigned short uint16_t; typedef unsigned char uint8_t; typedef signed long int32_t; typedef signed short int16_t; typedef signed char int8_t; typedef uint16_t BOOLEAN; // Ray for porting /* Basic data type */ #define u32_t unsigned long #define s32_t signed long #define u16_t unsigned short #define s16_t signed short #define u8_t unsigned char #define s8_t signed char #define ptrData uint8_t * /* marco definition */ //#define SIZE_HASH_BUFFER 128 #ifndef TRUE #define TRUE (0==0) #endif #ifndef FALSE #define FALSE (0!=0) #endif #ifndef NULL #define NULL 0x0 #endif #define BIT0 (1<<0) #define BIT1 (1<<1) #define BIT2 (1<<2) #define BIT3 (1<<3) #define BIT4 (1<<4) #define BIT5 (1<<5) #define BIT6 (1<<6) #define BIT7 (1<<7) #define BIT8 (1<<8) #define BIT9 (1<<9) #define BIT10 (1<<10) #define BIT11 (1<<11) #define BIT12 (1<<12) #define BIT13 (1<<13) #define BIT14 (1<<14) #define BIT15 (1<<15) #define BIT16 (1<<16) #define BIT17 (1<<17) #define BIT18 (1<<18) #define BIT19 (1<<19) #define BIT20 (1<<20) #define BIT21 (1<<21) #define BIT22 (1<<22) #define BIT23 (1<<23) #define BIT24 (1<<24) #define BIT25 (1<<25) #define BIT26 (1<<26) #define BIT27 (1<<27) #define BIT28 (1<<28) #define BIT29 (1<<29) #define BIT30 (1<<30) #define BIT31 (1<<31) #endif open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/eeprom_api.h000077500000000000000000000042631321570333100327210ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __EEPROM_API_H__ #define __EEPROM_API_H__ typedef enum { RET_SUCCESS = 0, RET_NOT_INIT, RET_NOT_EXIST, RET_EEP_CORRUPT, RET_EEP_OVERFLOW, // add return code from here RET_UNKNOWN } T_EEP_RET; /*!- interface of eeprom access * */ struct eep_api { void (* _eep_init)(void); T_EEP_RET (* _eep_read)(uint16_t, uint16_t, uint16_t *); T_EEP_RET (* _eep_write)(uint16_t, uint16_t, uint16_t *); T_EEP_RET (*_eep_is_exist)(void); }; #endif /* __EEPROM_API_H__ */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/hif_api.h000077500000000000000000000070211321570333100321730ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * @File: HIF_api.h * * @Abstract: Host Interface api * * @Notes: */ #ifndef _HIF_API_H #define _HIF_API_H #include /* mailbox hw module configuration structure */ typedef struct _HIF_CONFIG { int dummy; } HIF_CONFIG; typedef struct _HIF_CALLBACK { /* callback when a buffer has be sent to the host*/ void (*send_buf_done)(adf_nbuf_t buf, void *context); /* callback when a receive message is received */ void (*recv_buf)(adf_nbuf_t hdr_buf, adf_nbuf_t buf, void *context); /* context used for all callbacks */ void *context; } HIF_CALLBACK; typedef void* hif_handle_t; /* hardware API table structure (API descriptions below) */ struct hif_api { hif_handle_t (*_init)(HIF_CONFIG *pConfig); void (* _shutdown)(hif_handle_t); void (*_register_callback)(hif_handle_t, HIF_CALLBACK *); int (*_get_total_credit_count)(hif_handle_t); void (*_start)(hif_handle_t); void (*_config_pipe)(hif_handle_t handle, int pipe, int creditCount); int (*_send_buffer)(hif_handle_t handle, int pipe, adf_nbuf_t buf); void (*_return_recv_buf)(hif_handle_t handle, int pipe, adf_nbuf_t buf); //void (*_set_recv_bufsz)(int pipe, int bufsz); //void (*_pause_recv)(int pipe); //void (*_resume_recv)(int pipe); int (*_is_pipe_supported)(hif_handle_t handle, int pipe); int (*_get_max_msg_len)(hif_handle_t handle, int pipe); int (*_get_reserved_headroom)(hif_handle_t handle); void (*_isr_handler)(hif_handle_t handle); void (*_get_default_pipe)(hif_handle_t handle, A_UINT8 *pipe_uplink, A_UINT8 *pipe_downlink); /* room to expand this table by another table */ void *pReserved; }; extern void hif_module_install(struct hif_api *apis); extern void generic_hif_module_install(struct hif_api *apis); #endif /* #ifndef _HIF_API_H */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/hif_gmac.h000077500000000000000000000047471321570333100323450ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __HIF_GMAC_H #define __HIF_GMAC_H #include #include #define ETH_ALEN 6 #define GMAC_MAX_PKT_LEN 1600 #define GMAC_MAX_DESC 5 #define GMAC_DISCV_PKT_SZ 60 #define GMAC_DISCV_WAIT 2000 #define ATH_P_MAGBOOT 0x12 /*Magpie GMAC 18 for boot downloader*/ #define ATH_P_MAGNORM 0x13 /*Magpie GMAC 19 for HTC & others*/ #define ETH_P_ATH 0x88bd typedef enum hif_gmac_pipe{ HIF_GMAC_PIPE_RX = 1, /*Normal Priority RX*/ HIF_GMAC_PIPE_TX = 2, /*Normal Priority TX*/ }hif_gmac_pipe_t; struct gmac_api{ void (*gmac_boot_init)(void); }; void cmnos_gmac_module_install(struct gmac_api *boot_apis); void hif_gmac_module_install(struct hif_api *apis); #endif open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/hif_pci.h000077500000000000000000000057711321570333100322070ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __HIF_PCI_H #define __HIF_PCI_H #include #include #define PCI_MAX_DATA_PKT_LEN 1664 #define PCI_MAX_CMD_PKT_LEN 512 #define PCI_MAX_BOOT_DESC 2 typedef enum hif_pci_pipe_rx{ HIF_PCI_PIPE_RX0, /*Normal Priority RX*/ HIF_PCI_PIPE_RX1, HIF_PCI_PIPE_RX2, HIF_PCI_PIPE_RX3, HIF_PCI_PIPE_RX_MAX }hif_pci_pipe_rx_t; typedef enum hif_pci_pipe_tx{ HIF_PCI_PIPE_TX0, /*Normal Priority TX*/ HIF_PCI_PIPE_TX1, HIF_PCI_PIPE_TX_MAX }hif_pci_pipe_tx_t; typedef struct __pci_softc{ HIF_CALLBACK sw; }__pci_softc_t; struct hif_pci_api{ void (*pci_boot_init)(void); hif_handle_t (*pci_init)(HIF_CONFIG *pConfig); void (*pci_reset)(void); void (*pci_enable)(void); void (*pci_reap_xmitted)(__pci_softc_t *sc, dma_engine_t eng_no); void (*pci_reap_recv)(__pci_softc_t *sc, dma_engine_t eng_no); A_UINT8 (*pci_get_pipe)(dma_engine_t eng); dma_engine_t (*pci_get_tx_eng)(hif_pci_pipe_tx_t pipe); dma_engine_t (*pci_get_rx_eng)(hif_pci_pipe_rx_t pipe); }; void hif_pci_api_install(struct hif_pci_api *apis); void hif_pci_module_install(struct hif_api *apis); #endif open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/hif_usb.h000077500000000000000000000054751321570333100322260ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * @File: mbox_hw.h * * @Abstract: mailbox hardware definitions * * @Notes: */ #ifndef __HIF_USB_H__ #define __HIF_USB_H__ #include #include //#include #include #define HIF_USB_PIPE_TX 1 #define HIF_USB_PIPE_RX 2 #define HIF_USB_PIPE_INTERRUPT 3 #define HIF_USB_PIPE_COMMAND 4 #define HIF_USB_PIPE_HP_TX 5 #define HIF_USB_PIPE_MP_TX 6 struct VBUF_QUEUE { VBUF *head; VBUF *tail; }; /* the mailbox hardware layer context */ typedef struct _HIF_USB_CONTEXT { HIF_CALLBACK hifCb; struct zsDmaQueue dnQ; struct zsTxDmaQueue upQ; #if SYSTEM_MODULE_HP_EP5 struct zsDmaQueue hpdnQ; // high priority #endif #if SYSTEM_MODULE_HP_EP6 struct zsDmaQueue mpdnQ; // medium priority #endif //struct VBUF_QUEUE upVbufQ; VBUF *cmdQueue; struct VBUF_QUEUE eventBufQ; // Left a door for extension the structure void *pReserved; } HIF_USB_CONTEXT; #endif open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/intr_api.h000077500000000000000000000155071321570333100324110ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __INTR_API_H__ #define __INTR_API_H__ /* * Interrupt handler, for application-managed interrupts. * When an interrupt occurs, it is automatically disabled. * See A_WMAC_INTR_ATTACH() and A_MBOX_INTR_ATTACH(). * * If a handler returns A_HANDLER_DONE, the interrupt is * re-enabled. The OS calls the handler next time service * is required. This is the normal case for a handler. * * If a handler returns A_HANDLER_YIELD, the interrupt * remains masked. The handler is called again when * it is "convenient". This gives the OS an opportunity * to run other code/handlers. A handler should return * A_HANDLER_YIELD if it might dominate the CPU for too * long. * * If a handler returns A_HANDLER_NOENABLE, the interrupt * remains disabled. It is up to the application to re-enable * the interrupt (via A_*_INTR_UNMASK) when it's appropriate. * * Note that many combinations of interrupt functions and * interrupt vectors are NOT supported: Callers should use * only the macros defined in cmnos_api.h to access the * interrupt API. */ #include "cmnos_api.h" typedef uint32_t A_old_intr_t; ////////////////////////////////////////////////////////////////// // this is copied from mercury/cmnos_xtensa.h /* * These are CMNOS interrupt manifest constants. * They have specially-chosen values that align with hardware and or * operating system values (see cmnos_interrupt_info). */ #if defined(__XTENSA__) /* * Enumeration of low and medium priority interrupt numbers * which match the CPU hardware configuration: */ /* XTensa Level 1 interrupt */ #define A_INUM_SOFTWARE 0 /* currently unused */ /* XTensa Level2 interrupts */ #define A_INUM_XTTIMER 1 /* Tensilica timer */ #define A_INUM_TBD_2 2 /* TBD */ #define A_INUM_CPU_WDT 3 /* RST_CPU watchodg interrupt */ #define A_INUM_TBD_4 4 /* TBD */ #define A_INUM_TBD_5 5 /* TBD */ #define A_INUM_TBD_6 6 /* TBD */ #define A_INUM_CPU_GEN_TIMER 7 /* CPU general timer */ #define A_INUM_TBD_8 8 /* TBD */ #define A_INUM_TBD_9 9 /* TBD */ #define A_INUM_USB_CTRL 10 /* USB core control */ #define A_INUM_USB_DMA 11 /* USB DMA */ #define A_INUM_TBD_12 12 /* TBD */ #define A_INUM_TBD_13 13 /* TBD */ #define A_INUM_TBD_14 14 /* TBD */ /* Level 3 interrupts */ #define A_INUM_ERROR 15 /* Errors (e.g. access illegal address) */ #define A_INUM_TBD_16 16 /* TBD */ #define A_INUM_MAC 17 /* MAC */ /* Level 5 interrupts */ #define A_INUM_CPU_NMI 18 /* CPU NMI */ /* Number of interrupts that map directly into CPU/hal interrupt bits. */ #define NUM_DIRECT_INTR 19 #endif ////////////////////////////////////////////////////////////////// #define CMNOS_IMASK_XTTIMER (1< #include #include "cmnos_api.h" #include "vbuf_api.h" #include "vdesc_api.h" #include "usbfifo_api.h" #include "hif_api.h" #include "htc_api.h" #include "wmi_svc_api.h" #include "buf_pool_api.h" #include "dma_engine_api.h" #include "dma_lib.h" #if defined(PROJECT_K2) #include "sflash_api.h" #endif #define A_INDIR(sym) _A_MAGPIE_INDIRECTION_TABLE->sym #if SYSTEM_MODULE_DBG /* debug Support */ #define DBG_MODULE_INSTALL() cmnos_dbg_module_install(&_A_MAGPIE_INDIRECTION_TABLE->dbg) #define A_DBG_INIT() A_INDIR(dbg._dbg_init()) #define A_DBG_TASK() A_INDIR(dbg._dbg_task()) #else #define DBG_MODULE_INSTALL() #define A_DBG_INIT() #define A_DBG_TASK() #endif /* Serial Flash support */ #if SYSTEM_MODULE_SFLASH #define SFLASH_MODULE_INSTALL() cmnos_sflash_module_install(&_A_MAGPIE_INDIRECTION_TABLE->sflash) #define A_SFLASH_INIT() A_INDIR(sflash._sflash_init()) #define A_SFLASH_ERASE(erase_type, addr) A_INDIR(sflash._sflash_erase(erase_type, addr)) #define A_SFLASH_PROG(addr, len, buf) A_INDIR(sflash._sflash_program(addr, len, buf)) #define A_SFLASH_READ(fast, addr, len, buf) A_INDIR(sflash._sflash_read(fast, addr, len, buf)) #define A_SFLASH_RDSR() A_INDIR(sflash._sflash_rdsr()) #else #define SFLASH_MODULE_INSTALL() #define A_SFLASH_INIT() #define A_SFLASH_ERASE(erase_type, addr) #define A_SFLASH_PROG(addr, len, buf) #define A_SFLASH_READ(fast, addr, len, buf) #define A_SFLASH_RDSR() #endif /* DMA Engine Interface */ #define DMA_ENGINE_MODULE_INSTALL() dma_engine_module_install(&_A_MAGPIE_INDIRECTION_TABLE->dma_engine); #define DMA_Engine_init() A_INDIR(dma_engine._init()) #define DMA_Engine_config_rx_queue(q, nDesc, size) A_INDIR(dma_engine._config_rx_queue(q, nDesc, size)) #define DMA_Engine_xmit_buf(q, buf) A_INDIR(dma_engine._xmit_buf(q, buf)) #define DMA_Engine_flush_xmit(q) A_INDIR(dma_engine._flush_xmit(q)) #define DMA_Engine_reap_recv_buf(q) A_INDIR(dma_engine._reap_recv_buf(q)) #define DMA_Engine_return_recv_buf(q,buf) A_INDIR(dma_engine._return_recv_buf(q, buf)) #define DMA_Engine_reap_xmited_buf(q) A_INDIR(dma_engine._reap_xmited_buf(q)) #define DMA_Engine_swap_data(desc) A_INDIR(dma_engine._swap_data(desc)) #define DMA_Engine_init_rx_queue(q) A_INDIR(dma_engine._init_rx_queue(q)) #define DMA_Engine_init_tx_queue(q) A_INDIR(dma_engine._init_tx_queue(q)) #define DMA_Engine_has_compl_packets(q) A_INDIR(dma_engine._has_compl_packets(q)) #define DMA_Engine_desc_dump(q) A_INDIR(dma_engine._desc_dump(q)) #define DMA_Engine_get_packet(q) A_INDIR(dma_engine._get_packet(q)) #define DMA_Engine_reclaim_packet(q,desc) A_INDIR(dma_engine._reclaim_packet(q,desc)) #define DMA_Engine_put_packet(q,desc) A_INDIR(dma_engine._put_packet(q,desc)) /*DMA Library support for GMAC & PCI(E)*/ #define DMA_LIB_MODULE_INSTALL() dma_lib_module_install(&_A_MAGPIE_INDIRECTION_TABLE->dma_lib) #define dma_lib_tx_init(eng_no, if_type) A_INDIR(dma_lib.tx_init(eng_no, if_type)) #define dma_lib_rx_init(eng_no, if_type) A_INDIR(dma_lib.rx_init(eng_no, if_type)) #define dma_lib_rx_config(eng_no, desc, gran) A_INDIR(dma_lib.rx_config(eng_no, desc, gran)) #define dma_lib_tx_start(eng_no) A_INDIR(dma_lib.tx_start(eng_no)) #define dma_lib_rx_start(eng_no) A_INDIR(dma_lib.rx_start(eng_no)) #define dma_lib_intr_status(if_type) A_INDIR(dma_lib.intr_status(if_type)) #define dma_lib_hard_xmit(eng_no, buf) A_INDIR(dma_lib.hard_xmit(eng_no, buf)) #define dma_lib_flush_xmit(eng_no) A_INDIR(dma_lib.flush_xmit(eng_no)) #define dma_lib_xmit_done(eng_no) A_INDIR(dma_lib.xmit_done(eng_no)) #define dma_lib_reap_xmitted(eng_no) A_INDIR(dma_lib.reap_xmitted(eng_no)) #define dma_lib_reap_recv(eng_no) A_INDIR(dma_lib.reap_recv(eng_no)) #define dma_lib_return_recv(eng_no, buf) A_INDIR(dma_lib.return_recv(eng_no, buf)) #define dma_lib_recv_pkt(eng_no) A_INDIR(dma_lib.recv_pkt(eng_no)) /* HIF support */ #define HIF_MODULE_INSTALL() hif_module_install(&_A_MAGPIE_INDIRECTION_TABLE->hif) #define HIF_init(pConfig) A_INDIR(hif._init(pConfig)) #define HIF_shutdown(h) A_INDIR(hif._shutdown(h)) #define HIF_register_callback(h, pConfig) A_INDIR(hif._register_callback(h, pConfig)) #define HIF_start(h) A_INDIR(hif._start(h)) #define HIF_config_pipe(h, pipe, desc_list) A_INDIR(hif._config_pipe(h, pipe, desc_list)) #define HIF_send_buffer(h, pipe, buf) A_INDIR(hif._send_buffer(h, pipe, buf)) #define HIF_return_recv_buf(h, pipe, buf) A_INDIR(hif._return_recv_buf(h, pipe, buf)) #define HIF_isr_handler(h) A_INDIR(hif._isr_handler(h)) #define HIF_is_pipe_supported(h, pipe) A_INDIR(hif._is_pipe_supported(h, pipe)) #define HIF_get_max_msg_len(h, pipe) A_INDIR(hif._get_max_msg_len(h, pipe)) #define HIF_get_reserved_headroom(h) A_INDIR(hif._get_reserved_headroom(h)) #define HIF_get_default_pipe(h,u,d) A_INDIR(hif._get_default_pipe(h,u,d)) /* VBUF APIs */ #define VBUF_MODULE_INSTALL() vbuf_module_install(&_A_MAGPIE_INDIRECTION_TABLE->vbuf) #define VBUF_init(nBuf) A_INDIR(vbuf._init(nBuf)) #define VBUF_alloc_vbuf() A_INDIR(vbuf._alloc_vbuf()) #define VBUF_free_vbuf(buf) A_INDIR(vbuf._free_vbuf(buf)) /* VDESC APIs */ #define VDESC_MODULE_INSTALL() vdesc_module_install(&_A_MAGPIE_INDIRECTION_TABLE->vdesc) #define VDESC_init(nDesc) A_INDIR(vdesc._init(nDesc)) #define VDESC_alloc_vdesc() A_INDIR(vdesc._alloc_vdesc()) #define VDESC_get_hw_desc(desc) A_INDIR(vdesc._get_hw_desc(desc)) #define VDESC_swap_vdesc(dst, src) A_INDIR(vdesc._swap_vdesc(dst, src)) #define HTC_MODULE_INSTALL() htc_module_install(&_A_MAGPIE_INDIRECTION_TABLE->htc) #define HTC_init(SetupComplete, pConfig) A_INDIR(htc._HTC_Init(SetupComplete, pConfig)) #define HTC_Shutdown(h) A_INDIR(htc._HTC_Shutdown(h)) #define HTC_RegisterService(h, s) A_INDIR(htc._HTC_RegisterService(h, s)) #define HTC_Ready(h) A_INDIR(htc._HTC_Ready(h)) #define HTC_SendMsg(h, endpt, buf) A_INDIR(htc._HTC_SendMsg(h, endpt, buf)) #define HTC_ReturnBuffers(h, endpt, buf) A_INDIR(htc._HTC_ReturnBuffers(h, endpt, buf)) #define HTC_ReturnBuffersList(h, endpt, hd) A_INDIR(htc._HTC_ReturnBuffersList(h, endpt, hd)) #define HTC_GetReservedHeadroom(h) A_INDIR(htc._HTC_GetReservedHeadroom(h)) #define HTC_NotifyTargetInserted(h) #define HTC_NotifyTargetDetached(h) /* WMI SVC module */ #define WMI_SERVICE_MODULE_INSTALL() WMI_service_module_install(&_A_MAGPIE_INDIRECTION_TABLE->wmi_svc_api) #define WMI_Init(pCfg) A_INDIR(wmi_svc_api._WMI_Init(pCfg)) #define WMI_RegisterDispatchTable(h,pT) A_INDIR(wmi_svc_api._WMI_RegisterDispatchTable(h, pT)) #define WMI_AllocEvent(h,ec,len) A_INDIR(wmi_svc_api._WMI_AllocEvent(h, ec, len)) #define WMI_SendEvent(h,ev,id,seq,len) A_INDIR(wmi_svc_api._WMI_SendEvent(h, ev, id, seq, len)) #define WMI_GetPendingEventsCount() A_INDIR(wmi_svc_api._WMI_GetPendingEventsCount()) #define WMI_GetControlEp() A_INDIR(wmi_svc_api._WMI_GetControlEp()) #define WMI_SendCompleteHandler(ep, buf) A_INDIR(wmi_svc_api._WMI_SendCompleteHandler(ep, buf)) #define WMI_Shutdown(h) A_INDIR(wmi_svc_api._WMI_Shutdown(h)) /* USB FIFO module */ #define USBFIFO_MODULE_INSTALL() usbfifo_module_install(&_A_MAGPIE_INDIRECTION_TABLE->usbfifo_api) #define USBFIFO_init(pConfig) A_INDIR(usbfifo_api._init(pConfig)) #define USBFIFO_enable_event_isr() A_INDIR(usbfifo_api._enable_event_isr()) /* BUF pool module */ #define BUF_POOL_MODULE_INSTALL() buf_pool_module_install(&_A_MAGPIE_INDIRECTION_TABLE->buf_pool) #define BUF_Pool_init(h) A_INDIR(buf_pool._init(h)) #define BUF_Pool_shutdown(h) A_INDIR(buf_pool._shutdown(h)) #define BUF_Pool_create_pool(h, id, nItems, nSize) A_INDIR(buf_pool._create_pool(h, id, nItems, nSize)) #define BUF_Pool_alloc_buf(h, id, reserve) A_INDIR(buf_pool._alloc_buf(h, id, reserve)) #define BUF_Pool_alloc_buf_align(h, id, reserve,align) A_INDIR(buf_pool._alloc_buf_align(h, id, reserve,align)) #define BUF_Pool_free_buf(h, id, buf) A_INDIR(buf_pool._free_buf(h, id, buf)) /* * This defines the layout of the indirection table, which * is used to access exported APIs of various modules. The * layout is shared across ROM and RAM code. RAM code may * call into ROM and ROM code may call into RAM. Because * of the latter, existing offsets must not change for the * lifetime of a revision of ROM; but new members may be * added at the end. */ typedef struct _A_magpie_indirection_table { _A_cmnos_indirection_table_t cmnos; struct dbg_api dbg; struct sflash_api sflash; struct hif_api hif; struct htc_apis htc; WMI_SVC_APIS wmi_svc_api; struct usbfifo_api usbfifo_api; struct buf_pool_api buf_pool; struct vbuf_api vbuf; struct vdesc_api vdesc; struct allocram_api allocram; struct dma_engine_api dma_engine; struct dma_lib_api dma_lib; } _A_magpie_indirection_table_t; extern _A_magpie_indirection_table_t _indir_tbl; #define _A_MAGPIE_INDIRECTION_TABLE_SIZE sizeof(_A_magpie_indirection_table_t) #if defined(__mips__) #define _A_MAGPIE_INDIRECTION_TABLE ((_A_magpie_indirection_table_t *)0x700) #else #define _A_MAGPIE_INDIRECTION_TABLE (&_indir_tbl) #endif #endif open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/k2/k2/000077500000000000000000000000001321570333100312505ustar00rootroot00000000000000reg_defs.h000077500000000000000000000325031321570333100331260ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/k2/k2/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /*************************************************************************/ /* Copyright (c) 2006 Atheros Communications, Inc., All Rights Reserved */ /* */ /* Module Name : reg_defs.h */ /* */ /* Abstract */ /* This file contains the register addr and marco definition. */ /* */ /* NOTES */ /* None */ /* */ /*************************************************************************/ #ifndef _REG_DEFS_H_ #define _REG_DEFS_H_ #include "dt_defs.h" #define BIT_SET(bit) (1< /************************* Resource DEFS ***********************/ #define MAX_DESC_NUM 100 #ifdef RX_SCATTER #define MAX_BUF_NUM 100 #else #define MAX_BUF_NUM 60 #endif #undef SYSTEM_MODULE_DBG #undef MOVE_PRINT_TO_RAM #ifdef _DEBUG_BUILD_ #define SYSTEM_MODULE_DBG 1 #define MOVE_PRINT_TO_RAM 1 #else #define SYSTEM_MODULE_DBG 0 #define MOVE_PRINT_TO_RAM 1 #endif #undef SYSTEM_MODULE_SFLASH #define SYSTEM_MODULE_SFLASH 0 /************************* WLAN DEFS ***************************/ #define MAGPIE_ENABLE_WLAN 1 #define MAGPIE_ENABLE_PCIE 0 #define MAGPIE_ENABLE_WLAN_IN_TARGET 0 #define MAGPIE_ENABLE_WLAN_SELF_TX 0 #define MAGPIE_ENABLE_WLAN_RATE_CTRL 1 /****************************** WATCH DOG *******************************/ #define WDT_DEFAULT_TIMEOUT_VALUE 3*ONE_MSEC*1000 // Initial value is 3 seconds, firmware changes it to 65 milliseconds #endif #endif /* _SYS_CFG_H_ */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/magpie/000077500000000000000000000000001321570333100316625ustar00rootroot00000000000000Magpie_api.h000077500000000000000000000326451321570333100340240ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/magpie/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * @File: Magpie_api.h * * @Abstract: Magpie FW api * * @Notes: */ #ifndef _MAGPIE_API_H #define _MAGPIE_API_H #define MAGPIE_FW_BUILD #include "cmnos_api.h" #ifdef MAGPIE_FW_BUILD #include "vbuf_api.h" #include "vdesc_api.h" #include "usbfifo_api.h" //#include "allocram_api.h" #endif #include "hif_api.h" #include "htc_api.h" #include "wmi_svc_api.h" #include "buf_pool_api.h" #include "dma_engine_api.h" #include "dma_lib.h" #if (SYSTEM_MODULE_SFLASH != 0) #include "sflash_api.h" #endif #define A_INDIR(sym) _A_MAGPIE_INDIRECTION_TABLE->sym #if SYSTEM_MODULE_DBG /* debug Support */ #define DBG_MODULE_INSTALL() cmnos_dbg_module_install(&_A_MAGPIE_INDIRECTION_TABLE->dbg) #define A_DBG_INIT() A_INDIR(dbg._dbg_init()) #define A_DBG_TASK() A_INDIR(dbg._dbg_task()) #else #define A_DBG_INIT() #define A_DBG_TASK() #endif /* Serial Flash support */ #if (SYSTEM_MODULE_SFLASH != 0) #define SFLASH_MODULE_INSTALL() cmnos_sflash_module_install(&_A_MAGPIE_INDIRECTION_TABLE->sflash) #define A_SFLASH_INIT() A_INDIR(sflash._sflash_init()) #define A_SFLASH_ERASE(erase_type, addr) A_INDIR(sflash._sflash_erase(erase_type, addr)) #define A_SFLASH_PROG(addr, len, buf) A_INDIR(sflash._sflash_program(addr, len, buf)) #define A_SFLASH_READ(fast, addr, len, buf) A_INDIR(sflash._sflash_read(fast, addr, len, buf)) #define A_SFLASH_RDSR() A_INDIR(sflash._sflash_rdsr()) #else #define A_SFLASH_INIT() #define A_SFLASH_ERASE(erase_type, addr) #define A_SFLASH_PROG(addr, len, buf) #define A_SFLASH_READ(fast, addr, len, buf) #define A_SFLASH_RDSR() #endif /* DMA Engine Interface */ #define DMA_ENGINE_MODULE_INSTALL() dma_engine_module_install(&_A_MAGPIE_INDIRECTION_TABLE->dma_engine); #define DMA_Engine_init() A_INDIR(dma_engine._init()) #define DMA_Engine_config_rx_queue(q, nDesc, size) A_INDIR(dma_engine._config_rx_queue(q, nDesc, size)) #define DMA_Engine_xmit_buf(q, buf) A_INDIR(dma_engine._xmit_buf(q, buf)) #define DMA_Engine_flush_xmit(q) A_INDIR(dma_engine._flush_xmit(q)) #define DMA_Engine_reap_recv_buf(q) A_INDIR(dma_engine._reap_recv_buf(q)) #define DMA_Engine_return_recv_buf(q,buf) A_INDIR(dma_engine._return_recv_buf(q, buf)) #define DMA_Engine_reap_xmited_buf(q) A_INDIR(dma_engine._reap_xmited_buf(q)) #define DMA_Engine_swap_data(desc) A_INDIR(dma_engine._swap_data(desc)) #define DMA_Engine_init_rx_queue(q) A_INDIR(dma_engine._init_rx_queue(q)) #define DMA_Engine_init_tx_queue(q) A_INDIR(dma_engine._init_tx_queue(q)) #define DMA_Engine_has_compl_packets(q) A_INDIR(dma_engine._has_compl_packets(q)) #define DMA_Engine_desc_dump(q) A_INDIR(dma_engine._desc_dump(q)) #define DMA_Engine_get_packet(q) A_INDIR(dma_engine._get_packet(q)) #define DMA_Engine_reclaim_packet(q,desc) A_INDIR(dma_engine._reclaim_packet(q,desc)) #define DMA_Engine_put_packet(q,desc) A_INDIR(dma_engine._put_packet(q,desc)) /*DMA Library support for GMAC & PCI(E)*/ #define DMA_LIB_MODULE_INSTALL() dma_lib_module_install(&_A_MAGPIE_INDIRECTION_TABLE->dma_lib) #define dma_lib_tx_init(eng_no, if_type) A_INDIR(dma_lib.tx_init(eng_no, if_type)) #define dma_lib_rx_init(eng_no, if_type) A_INDIR(dma_lib.rx_init(eng_no, if_type)) #define dma_lib_rx_config(eng_no, desc, gran) A_INDIR(dma_lib.rx_config(eng_no, desc, gran)) #define dma_lib_tx_start(eng_no) A_INDIR(dma_lib.tx_start(eng_no)) #define dma_lib_rx_start(eng_no) A_INDIR(dma_lib.rx_start(eng_no)) #define dma_lib_intr_status(if_type) A_INDIR(dma_lib.intr_status(if_type)) #define dma_lib_hard_xmit(eng_no, buf) A_INDIR(dma_lib.hard_xmit(eng_no, buf)) #define dma_lib_flush_xmit(eng_no) A_INDIR(dma_lib.flush_xmit(eng_no)) #define dma_lib_xmit_done(eng_no) A_INDIR(dma_lib.xmit_done(eng_no)) #define dma_lib_reap_xmitted(eng_no) A_INDIR(dma_lib.reap_xmitted(eng_no)) #define dma_lib_reap_recv(eng_no) A_INDIR(dma_lib.reap_recv(eng_no)) #define dma_lib_return_recv(eng_no, buf) A_INDIR(dma_lib.return_recv(eng_no, buf)) #define dma_lib_recv_pkt(eng_no) A_INDIR(dma_lib.recv_pkt(eng_no)) /* HIF PCI Api's */ #define hif_pci_boot_init() A_INDIR(hif_pci.pci_boot_init()) #define hif_pci_init(pConfig) A_INDIR(hif_pci.pci_init(pConfig)) #define hif_pci_reset() A_INDIR(hif_pci.pci_reset()) #define hif_pci_enable() A_INDIR(hif_pci.pci_enable()) #define hif_pci_get_pipe(eng) A_INDIR(hif_pci.pci_get_pipe(eng)) #define hif_pci_get_tx_eng(pipe) A_INDIR(hif_pci.pci_get_tx_eng(pipe)) #define hif_pci_get_rx_eng(pipe) A_INDIR(hif_pci.pci_get_rx_eng(pipe)) #define hif_pci_reap_recv(sc, eng_no) A_INDIR(hif_pci.pci_reap_recv(sc, eng_no)) #define hif_pci_reap_xmitted(sc, eng_no) A_INDIR(hif_pci.pci_reap_xmitted(sc, eng_no)) /* HIF support */ #define HIF_MODULE_INSTALL() generic_hif_module_install(&_A_MAGPIE_INDIRECTION_TABLE->hif) #define HIF_init(pConfig) A_INDIR(hif._init(pConfig)) #define HIF_shutdown(h) A_INDIR(hif._shutdown(h)) #define HIF_register_callback(h, pConfig) A_INDIR(hif._register_callback(h, pConfig)) #define HIF_start(h) A_INDIR(hif._start(h)) #define HIF_config_pipe(h, pipe, desc_list) A_INDIR(hif._config_pipe(h, pipe, desc_list)) #define HIF_send_buffer(h, pipe, buf) A_INDIR(hif._send_buffer(h, pipe, buf)) #define HIF_return_recv_buf(h, pipe, buf) A_INDIR(hif._return_recv_buf(h, pipe, buf)) #define HIF_isr_handler(h) A_INDIR(hif._isr_handler(h)) #define HIF_is_pipe_supported(h, pipe) A_INDIR(hif._is_pipe_supported(h, pipe)) #define HIF_get_max_msg_len(h, pipe) A_INDIR(hif._get_max_msg_len(h, pipe)) #define HIF_get_reserved_headroom(h) A_INDIR(hif._get_reserved_headroom(h)) #define HIF_get_default_pipe(h,u,d) A_INDIR(hif._get_default_pipe(h,u,d)) typedef void (*HIF_INSTALL_FUNC_T)(struct hif_api *apis); /* VBUF APIs */ #ifdef MAGPIE_FW_BUILD #define VBUF_MODULE_INSTALL() vbuf_module_install(&_A_MAGPIE_INDIRECTION_TABLE->vbuf) #define VBUF_init(nBuf) A_INDIR(vbuf._init(nBuf)) #define VBUF_alloc_vbuf() A_INDIR(vbuf._alloc_vbuf()) #define VBUF_free_vbuf(buf) A_INDIR(vbuf._free_vbuf(buf)) #endif /* VDESC APIs */ #ifdef MAGPIE_FW_BUILD #define VDESC_MODULE_INSTALL() vdesc_module_install(&_A_MAGPIE_INDIRECTION_TABLE->vdesc) #define VDESC_init(nDesc) A_INDIR(vdesc._init(nDesc)) #define VDESC_alloc_vdesc() A_INDIR(vdesc._alloc_vdesc()) #define VDESC_get_hw_desc(desc) A_INDIR(vdesc._get_hw_desc(desc)) #define VDESC_swap_vdesc(dst, src) A_INDIR(vdesc._swap_vdesc(dst, src)) #endif #define HTC_MODULE_INSTALL() htc_module_install(&_A_MAGPIE_INDIRECTION_TABLE->htc) #define HTC_init(SetupComplete, pConfig) A_INDIR(htc._HTC_Init(SetupComplete, pConfig)) #define HTC_Shutdown(h) A_INDIR(htc._HTC_Shutdown(h)) #define HTC_RegisterService(h, s) A_INDIR(htc._HTC_RegisterService(h, s)) #define HTC_Ready(h) A_INDIR(htc._HTC_Ready(h)) #define HTC_SendMsg(h, endpt, buf) A_INDIR(htc._HTC_SendMsg(h, endpt, buf)) #define HTC_ReturnBuffers(h, endpt, buf) A_INDIR(htc._HTC_ReturnBuffers(h, endpt, buf)) #define HTC_ReturnBuffersList(h, endpt, hd) A_INDIR(htc._HTC_ReturnBuffersList(h, endpt, hd)) #define HTC_GetReservedHeadroom(h) A_INDIR(htc._HTC_GetReservedHeadroom(h)) #define HTC_NotifyTargetInserted(h) #define HTC_NotifyTargetDetached(h) /* WMI SVC module */ #define WMI_SERVICE_MODULE_INSTALL() WMI_service_module_install(&_A_MAGPIE_INDIRECTION_TABLE->wmi_svc_api) #define WMI_Init(pCfg) A_INDIR(wmi_svc_api._WMI_Init(pCfg)) #define WMI_RegisterDispatchTable(h,pT) A_INDIR(wmi_svc_api._WMI_RegisterDispatchTable(h, pT)) #define WMI_AllocEvent(h,ec,len) A_INDIR(wmi_svc_api._WMI_AllocEvent(h, ec, len)) #define WMI_SendEvent(h,ev,id,seq,len) A_INDIR(wmi_svc_api._WMI_SendEvent(h, ev, id, seq, len)) #define WMI_GetPendingEventsCount() A_INDIR(wmi_svc_api._WMI_GetPendingEventsCount()) #define WMI_GetControlEp() A_INDIR(wmi_svc_api._WMI_GetControlEp()) #define WMI_SendCompleteHandler(ep, buf) A_INDIR(wmi_svc_api._WMI_SendCompleteHandler(ep, buf)) #define WMI_Shutdown(h) A_INDIR(wmi_svc_api._WMI_Shutdown(h)) /* USB FIFO module */ #define USBFIFO_MODULE_INSTALL() usbfifo_module_install(&_A_MAGPIE_INDIRECTION_TABLE->usbfifo_api) #define USBFIFO_init(pConfig) A_INDIR(usbfifo_api._init(pConfig)) #define USBFIFO_enable_event_isr() A_INDIR(usbfifo_api._enable_event_isr()) /* BUF pool module */ #define BUF_POOL_MODULE_INSTALL() buf_pool_module_install(&_A_MAGPIE_INDIRECTION_TABLE->buf_pool) #define BUF_Pool_init(h) A_INDIR(buf_pool._init(h)) #define BUF_Pool_shutdown(h) A_INDIR(buf_pool._shutdown(h)) #define BUF_Pool_create_pool(h, id, nItems, nSize) A_INDIR(buf_pool._create_pool(h, id, nItems, nSize)) #define BUF_Pool_alloc_buf(h, id, reserve) A_INDIR(buf_pool._alloc_buf(h, id, reserve)) #define BUF_Pool_alloc_buf_align(h, id, reserve,align) A_INDIR(buf_pool._alloc_buf_align(h, id, reserve,align)) #define BUF_Pool_free_buf(h, id, buf) A_INDIR(buf_pool._free_buf(h, id, buf)) /* * This defines the layout of the indirection table, which * is used to access exported APIs of various modules. The * layout is shared across ROM and RAM code. RAM code may * call into ROM and ROM code may call into RAM. Because * of the latter, existing offsets must not change for the * lifetime of a revision of ROM; but new members may be * added at the end. */ typedef struct _A_magpie_indirection_table { _A_cmnos_indirection_table_t cmnos; //#if SYSTEM_MODULE_DBG struct dbg_api dbg; // move to firmware not in cmnos //#endif struct hif_api hif; struct htc_apis htc; WMI_SVC_APIS wmi_svc_api; struct usbfifo_api usbfifo_api; struct buf_pool_api buf_pool; #ifdef MAGPIE_FW_BUILD struct vbuf_api vbuf; struct vdesc_api vdesc; struct allocram_api allocram; #endif struct dma_engine_api dma_engine; struct dma_lib_api dma_lib; #if SYSTEM_MODULE_PCI struct hif_pci_api hif_pci; #endif // structure to be added after this.... #if (SYSTEM_MODULE_SFLASH != 0) struct sflash_api sflash; #endif } _A_magpie_indirection_table_t; extern _A_magpie_indirection_table_t _indir_tbl; #define _A_MAGPIE_INDIRECTION_TABLE_SIZE sizeof(_A_magpie_indirection_table_t) #if defined(__mips__) #define _A_MAGPIE_INDIRECTION_TABLE ((_A_magpie_indirection_table_t *)0x700) #else #define _A_MAGPIE_INDIRECTION_TABLE (&_indir_tbl) #endif #endif magpie/000077500000000000000000000000001321570333100330455ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/magpiereg_defs.h000077500000000000000000000361101321570333100350000ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/magpie/magpie/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /*************************************************************************/ /* Copyright (c) 2006 Atheros Communications, Inc., All Rights Reserved */ /* */ /* Module Name : reg_defs.h */ /* */ /* Abstract */ /* This file contains the register addr and marco definition. */ /* */ /* NOTES */ /* None */ /* */ /*************************************************************************/ #ifndef _REG_DEFS_H_ #define _REG_DEFS_H_ #include "dt_defs.h" #define BIT_SET(bit) (1<>2)) #endif /* _MEM_ADDRS_H_ */ sys_cfg.h000077500000000000000000000077331321570333100334260ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/magpie/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /*************************************************************************/ /* Copyright (c) 2006 Atheros Communications, Inc., All Rights Reserved */ /* */ /* Module Name : sys_cfg.h */ /* */ /* Abstract */ /* This file contains definition of platform and sysmte config . */ /* */ /* NOTES */ /* None */ /* */ /*************************************************************************/ #ifndef _SYS_CFG_H_ #define _SYS_CFG_H_ /************************** FPGA version **************************/ #define MAGPIE_FPGA_RAM_256K 1 /************************** ROM DEFINE ***************************/ #if defined(_ROM_) #include "rom_cfg.h" #if MAGPIE_FPGA_RAM_256K == 1 #undef MAX_BUF_NUM #define MAX_BUF_NUM 100 #endif #elif defined(_RAM_) #include "rom_cfg.h" #include "magpie_mem.h" /************************* Resource DEFS ***********************/ #define MAX_DESC_NUM 100 #ifdef RX_SCATTER #define MAX_BUF_NUM 60 #else #define MAX_BUF_NUM 40 #endif #if MAGPIE_FPGA_RAM_256K == 1 #undef MAX_BUF_NUM #define MAX_BUF_NUM 100 #endif #undef SYSTEM_MODULE_DBG #define SYSTEM_MODULE_DBG 1 /************************* WLAN DEFS ***************************/ #define MAGPIE_ENABLE_WLAN 1 #define MAGPIE_ENABLE_PCIE 1 #define MAGPIE_ENABLE_WLAN_IN_TARGET 0 #define MAGPIE_ENABLE_WLAN_SELF_TX 0 #define MAGPIE_ENABLE_WLAN_RATE_CTRL 1 #define WLAN_MAX_RXBUF 15 #define WLAN_MAX_TXBUF 10 /****************************** WATCH DOG *******************************/ #define WDT_DEFAULT_TIMEOUT_VALUE 3*ONE_MSEC*1000 // Initial value is 3 seconds, firmware changes it to 65 milliseconds #endif #endif /* _SYS_CFG_H_ */ magpie_regdump.h000077500000000000000000000047641321570333100335150ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __MAGPIE_REGDUMP_H__ #define __MAGPIE_REGDUMP_H__ #if !defined(__ASSEMBLER__) /* * XTensa CPU state * This must match the state saved by the target exception handler. */ struct XTensa_exception_frame_s { uint32_t xt_pc; uint32_t xt_ps; uint32_t xt_sar; uint32_t xt_vpri; uint32_t xt_a2; uint32_t xt_a3; uint32_t xt_a4; uint32_t xt_a5; uint32_t xt_exccause; uint32_t xt_lcount; uint32_t xt_lbeg; uint32_t xt_lend; /* Extra info to simplify post-mortem stack walkback */ #define MAGPIE_REGDUMP_FRAMES 5 struct { uint32_t a0; /* pc */ uint32_t a1; /* sp */ uint32_t a2; uint32_t a3; } wb[MAGPIE_REGDUMP_FRAMES]; }; typedef struct XTensa_exception_frame_s CPU_exception_frame_t; #define RD_SIZE sizeof(CPU_exception_frame_t) #endif #endif /* __MAGPIE_REGDUMP_H__ */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/mem_api.h000077500000000000000000000040461321570333100322070ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __MEM_API_H__ #define __MEM_API_H__ struct mem_api { void (* _mem_init)(void); void *(* _memset)(void *, int, unsigned int); void *(* _memcpy)(void *, const void *, unsigned int); void *(* _memmove)(void *, const void *, unsigned int); int (* _memcmp)(const void *, const void *, unsigned int); }; #endif /* __MEM_API_H__ */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/misc_api.h000077500000000000000000000045331321570333100323650ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __MISC_API_H__ #define __MISC_API_H__ enum hostif_s{ HIF_USB = 0, HIF_PCIE, HIF_GMAC, HIF_PCI, // HIF should be added above here HIF_NUM, HIF_NONE }; typedef enum hostif_s A_HOSTIF; struct register_dump_s; struct misc_api { void (* _system_reset)(void); void (* _mac_reset)(void); void (* _assfail)(struct register_dump_s *); void (* _misaligned_load_handler)(struct register_dump_s *); void (* _report_failure_to_host)(struct register_dump_s *, int); int (* _target_id_get)(void); A_HOSTIF (* _is_host_present)(void); uint8_t (*_kbhit)(uint8_t); uint16_t (* _rom_version_get)(void); }; #endif /* __MISC_API_H__ */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/osapi.h000077500000000000000000000213171321570333100317130ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __OSAPI_H__ #define __OSAPI_H__ #define A_COMPILE_TIME_ASSERT(assertion_name, predicate) \ typedef char assertion_name[(predicate) ? 1 : -1]; #if !defined(LOCAL) #if 0 /* At least for now, simplify debugging. */ #define LOCAL static #else #define LOCAL #endif #endif #if !defined(NULL) #define NULL (void *)0 #endif #if !defined(FALSE) #define FALSE 0 #endif #if !defined(TRUE) #define TRUE 1 #endif #ifdef __GNUC__ #define __ATTRIB_PACK __attribute__ ((packed)) #define __ATTRIB_PRINTF __attribute__ ((format (printf, 1, 2))) #define __ATTRIB_NORETURN __attribute__ ((noreturn)) #define __ATTRIB_ALIGN(x) __attribute__ ((aligned((x)))) #define INLINE __inline__ #else /* Not GCC */ #define __ATTRIB_PACK #define __ATTRIB_PRINTF #define __ATTRIB_NORETURN #define __ATTRIB_ALIGN(x) #define INLINE __inline #endif /* End __GNUC__ */ #define PREPACK #define POSTPACK __ATTRIB_PACK /* Utility macros */ #define A_SWAB32(_x) ( \ ((A_UINT32)( \ (((A_UINT32)(_x) & (A_UINT32)0x000000ffUL) << 24) | \ (((A_UINT32)(_x) & (A_UINT32)0x0000ff00UL) << 8) | \ (((A_UINT32)(_x) & (A_UINT32)0x00ff0000UL) >> 8) | \ (((A_UINT32)(_x) & (A_UINT32)0xff000000UL) >> 24) )) \ ) #define A_SWAB16(_x) \ ((A_UINT16)( \ (((A_UINT16)(_x) & (A_UINT16)0x00ffU) << 8) | \ (((A_UINT16)(_x) & (A_UINT16)0xff00U) >> 8) )) /* unaligned little endian access */ #define A_LE_READ_2(p) \ ((A_UINT16)( \ (((A_UINT8 *)(p))[0]) | (((A_UINT8 *)(p))[1] << 8))) #define A_LE_READ_4(p) \ ((A_UINT32)( \ (((A_UINT8 *)(p))[0] ) | (((A_UINT8 *)(p))[1] << 8) | \ (((A_UINT8 *)(p))[2] << 16) | (((A_UINT8 *)(p))[3] << 24))) #define A_LE64_TO_CPU(_x) ((A_UINT64)(_x)) #define A_LE32_TO_CPU(_x) ((A_UINT32)(_x)) #define A_CPU_TO_LE32(_x) ((A_UINT32)(_x)) #define A_BE32_TO_CPU(_x) A_SWAB32(_x) #define A_CPU_TO_BE32(_x) A_SWAB32(_x) #define A_LE16_TO_CPU(_x) ((A_UINT16)(_x)) #define A_CPU_TO_LE16(_x) ((A_UINT16)(_x)) #define A_BE16_TO_CPU(_x) A_SWAB16(_x) #define A_CPU_TO_BE16(_x) A_SWAB16(_x) #define A_LE32TOH(_x) A_LE32_TO_CPU(_x) #define A_HTOLE32(_x) A_CPU_TO_LE32(_x) #define A_BE32TOH(_x) A_BE32_TO_CPU(_x) #define A_HTOBE32(_x) A_CPU_TO_BE32(_x) #define A_LE16TOH(_x) A_LE16_TO_CPU(_x) #define A_HTOLE16(_x) A_CPU_TO_LE16(_x) #define A_BE16TOH(_x) A_BE16_TO_CPU(_x) #define A_HTOBE16(_x) A_CPU_TO_BE16(_x) #define A_MAX(x, y) (((x) > (y)) ? (x) : (y)) #define A_MIN(x, y) (((x) < (y)) ? (x) : (y)) #define A_ABS(x) (((x) >= 0) ? (x) : (-(x))) #define A_ROUND_UP(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) #define A_ROUND_UP_PAD(x, y) (A_ROUND_UP(x, y) - (x)) #define A_ROUND_UP_PWR2(x, align) (((int) (x) + ((align)-1)) & ~((align)-1)) #define A_ROUND_DOWN_PWR2(x, align) ((int)(x) & ~((align)-1)) #define A_TOLOWER(c) (((c) >= 'A' && (c) <= 'Z') ? ((c)-'A'+'a') : (c)) #define A_TOUPPER(c) (((c) >= 'a' && (c) <= 'z') ? ((c)-'a'+'A') : (c)) #define A_ARRAY_NUM_ENTRIES(a) (sizeof(a)/sizeof(*(a))) #define A_FIELD_OFFSET(type, field) ((int)(&((type *)0)->field)) #define A_MSECS_PER_SECOND 1000 /* Milliseconds */ #define A_USECS_PER_SECOND 1000000 /* Microseconds */ #define A_NSECS_PER_SECOND 1000000000 /* Nanoseconds */ /* * Intentional Misaligned Load special "addresses". * Loads from misaligned addresses have special semantics, * handled by the OS, depending on the lower nibble. * * NOTE1: word-aligned nibbles will not cause any exception, * so they must not be used. * * NOTE2: On AR6002, the Xtensa CPU may issue a load speculatively. * If this load accesses an unmapped region of SOC (such as the * lower 4KB), AR6002 hardware generates an Address Error interrupt * even before the instruction has actually executed and therefore * before it has a chance to generate the expected Misaligned Load * error. To avoid this, we make these IML accesses be to an address * range that is valid....ROM. */ #if 0 #define IML_SIGNAL_UNUSED0_ADDR TARG_ROM_ADDRS(0) /* Cannot be used -- aligned */ #define IML_SIGNAL_ASSERT_ADDR TARG_ROM_ADDRS(1) /* Signal an assertion failure */ #define IML_SIGNAL_PRINTF_ADDR TARG_ROM_ADDRS(2) /* Signal a printf request */ #define IML_SIGNAL_UNUSED4_ADDR TARG_ROM_ADDRS(4) /* Cannot be used -- aligned */ #define IML_SIGNAL_UNUSED8_ADDR TARG_ROM_ADDRS(8) /* Cannot be used -- aligned */ #define IML_SIGNAL_UNUSEDC_ADDR TARG_ROM_ADDRS(0xc) /* Cannot be used -- aligned */ #define IML_SIGNAL_MASK 0xfffe000f #define IML_LINENUM_SHIFT 4 #endif #ifdef HTC_TRACE_MBOX_PAUSE #define A_ASSERT( __bool ) #else /* * Code space dedicated to asserts is minimal. We use an Intentional * Misaligned Load to signal an assert failure. We embed the line * number in the misaligned address as a debugging aid. This may * make it a bit more difficult to recognize a bona fide misaligned * load, but that's an acceptable tradeoff. * * Bits 3..0 encodes the IML_SIGNAL_* number. * Bits 16..4 encode the LINE number of the ASSERTion. * Upper nibbles are the start of ROM. */ #if defined(__XTENSA__) #define _A_BARRIER asm volatile("memw") #else #define _A_BARRIER #endif #define A_ASSERT( __bool ) \ do { \ if (0 == (__bool)) { \ (void)*((volatile int *)(IML_SIGNAL_ASSERT_ADDR+(__LINE__<<4)));\ _A_BARRIER; \ } \ } while (0) #endif #define A_IML_IS_ASSERT(vaddr) \ (((vaddr) & IML_SIGNAL_MASK) == (IML_SIGNAL_ASSERT_ADDR & IML_SIGNAL_MASK)) /* * The A_ASSERT macro encodes line number in the Intentionally Misaligned * Address that it uses to signal a failure. This macro extracts that * line number information. * * Note: ASSERTs up to line 8191 (13 bits) of a file are supported. * Beyond that an assertion failure appears as a misaligned load. */ #define A_IML_ASSLINE(vaddr) (((vaddr) & ~IML_SIGNAL_MASK) >> IML_LINENUM_SHIFT) /* Prevent compiler code movement */ #define A_REORDER_BARRIER() asm volatile ( "" : : : "memory" ) /* * Some general system settings may depend on which wireless band is * to be used. For example, on AR6K the system PLL setting is * band-dependent. * * These constants are used with A_WLAN_BAND_SET. */ #define A_BAND_24GHZ 0 #define A_BAND_5GHZ 1 #define A_NUM_BANDS 2 #define OTUS #if defined(AR6K) //#include #elif defined(OTUS) #include #else #error "Unsupported platform" #endif //#include "os/athos_api.h" #endif /* __OSAPI_H__ */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/regdump.h000077500000000000000000000050701321570333100322410ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __REGDUMP_H__ #define __REGDUMP_H__ #include "magpie_regdump.h" #if !defined(__ASSEMBLER__) /* * XTensa CPU state * This must match the state saved by the target exception handler. */ #define RD_SIZE sizeof(CPU_exception_frame_t) /* * Target CPU state at the time of failure is reflected * in a register dump, which the Host can fetch through * the diagnostic window. */ struct register_dump_s { uint32_t target_id; /* Target ID */ uint32_t assline; /* Line number (if assertion failure) */ uint32_t pc; /* Program Counter at time of exception */ uint32_t badvaddr; /* Virtual address causing exception */ CPU_exception_frame_t exc_frame; /* CPU-specific exception info */ /* Could copy top of stack here, too.... */ }; #endif /* __ASSEMBLER__ */ #endif /* __REGDUMP_H__ */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/romp_api.h000077500000000000000000000066131321570333100324100ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /*************************************************************************/ /* Copyright (c) 2008 Atheros Communications, Inc., All Rights Reserved */ /* */ /* Module Name : romp_api.h */ /* */ /* Abstract */ /* This file contains definition of data structure and interface */ /* */ /* NOTES */ /* None */ /* */ /*************************************************************************/ #ifndef _ROMP_API_H_ #define _ROMP_API_H_ #include "dt_defs.h" /******** hardware API table structure (API descriptions below) *************/ struct romp_api { void (*_romp_init)(void); BOOLEAN (*_romp_download)(uint16_t ); BOOLEAN (*_romp_install)(void); BOOLEAN (*_romp_decode)(uint32_t ); }; #define _ROMP_MAGIC_ "[PaTcH]" struct rom_patch_st { uint16_t crc16; // crc filed to maintain the integrity uint16_t len; // length of the patch code uint32_t ld_addr; // load address of the patch code uint32_t fun_addr; // entry address of the patch code uint8_t *pfun; // patch code }; struct eep_redir_addr { uint16_t offset; uint16_t size; }; /************************* EXPORT function ***************************/ uint16_t cal_crc16(uint32_t sz, uint8_t *p); #endif // end of _UART_API_H_ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/string_api.h000077500000000000000000000041071321570333100327350ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __STRING_API_H__ #define __STRING_API_H__ struct string_api { void (* _string_init)(void); char *(* _strcpy)(char *, const char *); char *(* _strncpy)(char *, const char *, unsigned int); int (* _strlen)(const char *); int (* _strcmp)(const char *, const char *); int (* _strncmp)(const char *, const char *, unsigned int); }; #endif /* __STRING_API_H__ */ tasklet_api.h000077500000000000000000000045111321570333100330160ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __TASKLET_API_H__ #define __TASKLET_API_H__ typedef void (*A_TASKLET_FUNC)(void *arg); #define A_TASKLET_STATE_DISABLE 0 #define A_TASKLET_STATE_SCHEDULED 1 #define A_TASKLET_STATE_RUNNING 2 struct _tasklet { A_TASKLET_FUNC func; void *arg; int state; struct _tasklet *next; }; typedef struct _tasklet A_tasklet_t; struct tasklet_api { void (* _tasklet_init)(void); void (* _tasklet_init_task)(A_TASKLET_FUNC, void * arg, A_tasklet_t *); void (* _tasklet_disable)(A_tasklet_t *); void (* _tasklet_schedule)(A_tasklet_t *); void (* _tasklet_run)(void); }; #endif /* __TASKLET_API_H__ */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/timer_api.h000077500000000000000000000046161321570333100325540ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __TIMER_API_H__ #define __TIMER_API_H__ /* * In order to remain completely independent of OS header files, * "_SPACE" structures are declared with sufficient room to hold * corresponding OS structures. */ typedef unsigned int _A_TIMER_SPACE[5]; typedef _A_TIMER_SPACE A_timer_t; #define A_TIMER A_timer_t /* historical */ typedef unsigned int A_HANDLE; /* historical */ typedef void A_TIMER_FUNC(A_HANDLE timer_handle, void *arg); struct timer_api { void (* _timer_init)(void); void (* _timer_arm)(A_timer_t *, unsigned int); void (* _timer_disarm)(A_timer_t *); void (* _timer_setfn)(A_timer_t *, A_TIMER_FUNC, void *); void (* _timer_run)(void); }; #endif /* __TIMER_API_H__ */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/uart_api.h000077500000000000000000000462541321570333100324130ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /*************************************************************************/ /* Copyright (c) 2006 Atheros Communications, Inc., All Rights Reserved */ /* */ /* Module Name : uart.h */ /* */ /* Abstract */ /* This file contains definition of uart registers, marco and api. */ /* */ /* NOTES */ /* None */ /* */ /*************************************************************************/ #ifndef _UART_API_H_ #define _UART_API_H_ #include "reg_defs.h" /************************** Register deinition ***************************/ #define RBR_ADDRESS 0x00051000 #define RBR_OFFSET 0x00000000 #define RBR_RBR_MSB 7 #define RBR_RBR_LSB 0 #define RBR_RBR_MASK 0x000000ff #define RBR_RBR_GET(x) (((x) & RBR_RBR_MASK) >> RBR_RBR_LSB) #define RBR_RBR_SET(x) (((x) << RBR_RBR_LSB) & RBR_RBR_MASK) #define THR_ADDRESS 0x00051000 #define THR_OFFSET 0x00000000 #define THR_THR_MSB 7 #define THR_THR_LSB 0 #define THR_THR_MASK 0x000000ff #define THR_THR_GET(x) (((x) & THR_THR_MASK) >> THR_THR_LSB) #define THR_THR_SET(x) (((x) << THR_THR_LSB) & THR_THR_MASK) #define DLL_ADDRESS 0x00051000 #define DLL_OFFSET 0x00000000 #define DLL_DLL_MSB 7 #define DLL_DLL_LSB 0 #define DLL_DLL_MASK 0x000000ff #define DLL_DLL_GET(x) (((x) & DLL_DLL_MASK) >> DLL_DLL_LSB) #define DLL_DLL_SET(x) (((x) << DLL_DLL_LSB) & DLL_DLL_MASK) #define DLH_ADDRESS 0x00051004 #define DLH_OFFSET 0x00000004 #define DLH_DLH_MSB 7 #define DLH_DLH_LSB 0 #define DLH_DLH_MASK 0x000000ff #define DLH_DLH_GET(x) (((x) & DLH_DLH_MASK) >> DLH_DLH_LSB) #define DLH_DLH_SET(x) (((x) << DLH_DLH_LSB) & DLH_DLH_MASK) #define IER_ADDRESS 0x00051004 #define IER_OFFSET 0x00000004 #define IER_EDDSI_MSB 3 #define IER_EDDSI_LSB 3 #define IER_EDDSI_MASK 0x00000008 #define IER_EDDSI_GET(x) (((x) & IER_EDDSI_MASK) >> IER_EDDSI_LSB) #define IER_EDDSI_SET(x) (((x) << IER_EDDSI_LSB) & IER_EDDSI_MASK) #define IER_ELSI_MSB 2 #define IER_ELSI_LSB 2 #define IER_ELSI_MASK 0x00000004 #define IER_ELSI_GET(x) (((x) & IER_ELSI_MASK) >> IER_ELSI_LSB) #define IER_ELSI_SET(x) (((x) << IER_ELSI_LSB) & IER_ELSI_MASK) #define IER_ETBEI_MSB 1 #define IER_ETBEI_LSB 1 #define IER_ETBEI_MASK 0x00000002 #define IER_ETBEI_GET(x) (((x) & IER_ETBEI_MASK) >> IER_ETBEI_LSB) #define IER_ETBEI_SET(x) (((x) << IER_ETBEI_LSB) & IER_ETBEI_MASK) #define IER_ERBFI_MSB 0 #define IER_ERBFI_LSB 0 #define IER_ERBFI_MASK 0x00000001 #define IER_ERBFI_GET(x) (((x) & IER_ERBFI_MASK) >> IER_ERBFI_LSB) #define IER_ERBFI_SET(x) (((x) << IER_ERBFI_LSB) & IER_ERBFI_MASK) #define IIR_ADDRESS 0x00051008 #define IIR_OFFSET 0x00000008 #define IIR_FIFO_STATUS_MSB 7 #define IIR_FIFO_STATUS_LSB 6 #define IIR_FIFO_STATUS_MASK 0x000000c0 #define IIR_FIFO_STATUS_GET(x) (((x) & IIR_FIFO_STATUS_MASK) >> IIR_FIFO_STATUS_LSB) #define IIR_FIFO_STATUS_SET(x) (((x) << IIR_FIFO_STATUS_LSB) & IIR_FIFO_STATUS_MASK) #define IIR_IID_MSB 3 #define IIR_IID_LSB 0 #define IIR_IID_MASK 0x0000000f #define IIR_IID_GET(x) (((x) & IIR_IID_MASK) >> IIR_IID_LSB) #define IIR_IID_SET(x) (((x) << IIR_IID_LSB) & IIR_IID_MASK) #define FCR_ADDRESS 0x00051008 #define FCR_OFFSET 0x00000008 #define FCR_RCVR_TRIG_MSB 7 #define FCR_RCVR_TRIG_LSB 6 #define FCR_RCVR_TRIG_MASK 0x000000c0 #define FCR_RCVR_TRIG_GET(x) (((x) & FCR_RCVR_TRIG_MASK) >> FCR_RCVR_TRIG_LSB) #define FCR_RCVR_TRIG_SET(x) (((x) << FCR_RCVR_TRIG_LSB) & FCR_RCVR_TRIG_MASK) #define FCR_DMA_MODE_MSB 3 #define FCR_DMA_MODE_LSB 3 #define FCR_DMA_MODE_MASK 0x00000008 #define FCR_DMA_MODE_GET(x) (((x) & FCR_DMA_MODE_MASK) >> FCR_DMA_MODE_LSB) #define FCR_DMA_MODE_SET(x) (((x) << FCR_DMA_MODE_LSB) & FCR_DMA_MODE_MASK) #define FCR_XMIT_FIFO_RST_MSB 2 #define FCR_XMIT_FIFO_RST_LSB 2 #define FCR_XMIT_FIFO_RST_MASK 0x00000004 #define FCR_XMIT_FIFO_RST_GET(x) (((x) & FCR_XMIT_FIFO_RST_MASK) >> FCR_XMIT_FIFO_RST_LSB) #define FCR_XMIT_FIFO_RST_SET(x) (((x) << FCR_XMIT_FIFO_RST_LSB) & FCR_XMIT_FIFO_RST_MASK) #define FCR_RCVR_FIFO_RST_MSB 1 #define FCR_RCVR_FIFO_RST_LSB 1 #define FCR_RCVR_FIFO_RST_MASK 0x00000002 #define FCR_RCVR_FIFO_RST_GET(x) (((x) & FCR_RCVR_FIFO_RST_MASK) >> FCR_RCVR_FIFO_RST_LSB) #define FCR_RCVR_FIFO_RST_SET(x) (((x) << FCR_RCVR_FIFO_RST_LSB) & FCR_RCVR_FIFO_RST_MASK) #define FCR_FIFO_EN_MSB 0 #define FCR_FIFO_EN_LSB 0 #define FCR_FIFO_EN_MASK 0x00000001 #define FCR_FIFO_EN_GET(x) (((x) & FCR_FIFO_EN_MASK) >> FCR_FIFO_EN_LSB) #define FCR_FIFO_EN_SET(x) (((x) << FCR_FIFO_EN_LSB) & FCR_FIFO_EN_MASK) #define LCR_ADDRESS 0x0005100c #define LCR_OFFSET 0x0000000c #define LCR_DLAB_MSB 7 #define LCR_DLAB_LSB 7 #define LCR_DLAB_MASK 0x00000080 #define LCR_DLAB_GET(x) (((x) & LCR_DLAB_MASK) >> LCR_DLAB_LSB) #define LCR_DLAB_SET(x) (((x) << LCR_DLAB_LSB) & LCR_DLAB_MASK) #define LCR_BREAK_MSB 6 #define LCR_BREAK_LSB 6 #define LCR_BREAK_MASK 0x00000040 #define LCR_BREAK_GET(x) (((x) & LCR_BREAK_MASK) >> LCR_BREAK_LSB) #define LCR_BREAK_SET(x) (((x) << LCR_BREAK_LSB) & LCR_BREAK_MASK) #define LCR_EPS_MSB 4 #define LCR_EPS_LSB 4 #define LCR_EPS_MASK 0x00000010 #define LCR_EPS_GET(x) (((x) & LCR_EPS_MASK) >> LCR_EPS_LSB) #define LCR_EPS_SET(x) (((x) << LCR_EPS_LSB) & LCR_EPS_MASK) #define LCR_PEN_MSB 3 #define LCR_PEN_LSB 3 #define LCR_PEN_MASK 0x00000008 #define LCR_PEN_GET(x) (((x) & LCR_PEN_MASK) >> LCR_PEN_LSB) #define LCR_PEN_SET(x) (((x) << LCR_PEN_LSB) & LCR_PEN_MASK) #define LCR_STOP_MSB 2 #define LCR_STOP_LSB 2 #define LCR_STOP_MASK 0x00000004 #define LCR_STOP_GET(x) (((x) & LCR_STOP_MASK) >> LCR_STOP_LSB) #define LCR_STOP_SET(x) (((x) << LCR_STOP_LSB) & LCR_STOP_MASK) #define LCR_CLS_MSB 1 #define LCR_CLS_LSB 0 #define LCR_CLS_MASK 0x00000003 #define LCR_CLS_GET(x) (((x) & LCR_CLS_MASK) >> LCR_CLS_LSB) #define LCR_CLS_SET(x) (((x) << LCR_CLS_LSB) & LCR_CLS_MASK) #define MCR_ADDRESS 0x00051010 #define MCR_OFFSET 0x00000010 #define MCR_LOOPBACK_MSB 5 #define MCR_LOOPBACK_LSB 5 #define MCR_LOOPBACK_MASK 0x00000020 #define MCR_LOOPBACK_GET(x) (((x) & MCR_LOOPBACK_MASK) >> MCR_LOOPBACK_LSB) #define MCR_LOOPBACK_SET(x) (((x) << MCR_LOOPBACK_LSB) & MCR_LOOPBACK_MASK) #define MCR_OUT2_MSB 3 #define MCR_OUT2_LSB 3 #define MCR_OUT2_MASK 0x00000008 #define MCR_OUT2_GET(x) (((x) & MCR_OUT2_MASK) >> MCR_OUT2_LSB) #define MCR_OUT2_SET(x) (((x) << MCR_OUT2_LSB) & MCR_OUT2_MASK) #define MCR_OUT1_MSB 2 #define MCR_OUT1_LSB 2 #define MCR_OUT1_MASK 0x00000004 #define MCR_OUT1_GET(x) (((x) & MCR_OUT1_MASK) >> MCR_OUT1_LSB) #define MCR_OUT1_SET(x) (((x) << MCR_OUT1_LSB) & MCR_OUT1_MASK) #define MCR_RTS_MSB 1 #define MCR_RTS_LSB 1 #define MCR_RTS_MASK 0x00000002 #define MCR_RTS_GET(x) (((x) & MCR_RTS_MASK) >> MCR_RTS_LSB) #define MCR_RTS_SET(x) (((x) << MCR_RTS_LSB) & MCR_RTS_MASK) #define MCR_DTR_MSB 0 #define MCR_DTR_LSB 0 #define MCR_DTR_MASK 0x00000001 #define MCR_DTR_GET(x) (((x) & MCR_DTR_MASK) >> MCR_DTR_LSB) #define MCR_DTR_SET(x) (((x) << MCR_DTR_LSB) & MCR_DTR_MASK) #define LSR_ADDRESS 0x00051014 #define LSR_OFFSET 0x00000014 #define LSR_FERR_MSB 7 #define LSR_FERR_LSB 7 #define LSR_FERR_MASK 0x00000080 #define LSR_FERR_GET(x) (((x) & LSR_FERR_MASK) >> LSR_FERR_LSB) #define LSR_FERR_SET(x) (((x) << LSR_FERR_LSB) & LSR_FERR_MASK) #define LSR_TEMT_MSB 6 #define LSR_TEMT_LSB 6 #define LSR_TEMT_MASK 0x00000040 #define LSR_TEMT_GET(x) (((x) & LSR_TEMT_MASK) >> LSR_TEMT_LSB) #define LSR_TEMT_SET(x) (((x) << LSR_TEMT_LSB) & LSR_TEMT_MASK) #define LSR_THRE_MSB 5 #define LSR_THRE_LSB 5 #define LSR_THRE_MASK 0x00000020 #define LSR_THRE_GET(x) (((x) & LSR_THRE_MASK) >> LSR_THRE_LSB) #define LSR_THRE_SET(x) (((x) << LSR_THRE_LSB) & LSR_THRE_MASK) #define LSR_BI_MSB 4 #define LSR_BI_LSB 4 #define LSR_BI_MASK 0x00000010 #define LSR_BI_GET(x) (((x) & LSR_BI_MASK) >> LSR_BI_LSB) #define LSR_BI_SET(x) (((x) << LSR_BI_LSB) & LSR_BI_MASK) #define LSR_FE_MSB 3 #define LSR_FE_LSB 3 #define LSR_FE_MASK 0x00000008 #define LSR_FE_GET(x) (((x) & LSR_FE_MASK) >> LSR_FE_LSB) #define LSR_FE_SET(x) (((x) << LSR_FE_LSB) & LSR_FE_MASK) #define LSR_PE_MSB 2 #define LSR_PE_LSB 2 #define LSR_PE_MASK 0x00000004 #define LSR_PE_GET(x) (((x) & LSR_PE_MASK) >> LSR_PE_LSB) #define LSR_PE_SET(x) (((x) << LSR_PE_LSB) & LSR_PE_MASK) #define LSR_OE_MSB 1 #define LSR_OE_LSB 1 #define LSR_OE_MASK 0x00000002 #define LSR_OE_GET(x) (((x) & LSR_OE_MASK) >> LSR_OE_LSB) #define LSR_OE_SET(x) (((x) << LSR_OE_LSB) & LSR_OE_MASK) #define LSR_DR_MSB 0 #define LSR_DR_LSB 0 #define LSR_DR_MASK 0x00000001 #define LSR_DR_GET(x) (((x) & LSR_DR_MASK) >> LSR_DR_LSB) #define LSR_DR_SET(x) (((x) << LSR_DR_LSB) & LSR_DR_MASK) #define MSR_ADDRESS 0x00051018 #define MSR_OFFSET 0x00000018 #define MSR_DCD_MSB 7 #define MSR_DCD_LSB 7 #define MSR_DCD_MASK 0x00000080 #define MSR_DCD_GET(x) (((x) & MSR_DCD_MASK) >> MSR_DCD_LSB) #define MSR_DCD_SET(x) (((x) << MSR_DCD_LSB) & MSR_DCD_MASK) #define MSR_RI_MSB 6 #define MSR_RI_LSB 6 #define MSR_RI_MASK 0x00000040 #define MSR_RI_GET(x) (((x) & MSR_RI_MASK) >> MSR_RI_LSB) #define MSR_RI_SET(x) (((x) << MSR_RI_LSB) & MSR_RI_MASK) #define MSR_DSR_MSB 5 #define MSR_DSR_LSB 5 #define MSR_DSR_MASK 0x00000020 #define MSR_DSR_GET(x) (((x) & MSR_DSR_MASK) >> MSR_DSR_LSB) #define MSR_DSR_SET(x) (((x) << MSR_DSR_LSB) & MSR_DSR_MASK) #define MSR_CTS_MSB 4 #define MSR_CTS_LSB 4 #define MSR_CTS_MASK 0x00000010 #define MSR_CTS_GET(x) (((x) & MSR_CTS_MASK) >> MSR_CTS_LSB) #define MSR_CTS_SET(x) (((x) << MSR_CTS_LSB) & MSR_CTS_MASK) #define MSR_DDCD_MSB 3 #define MSR_DDCD_LSB 3 #define MSR_DDCD_MASK 0x00000008 #define MSR_DDCD_GET(x) (((x) & MSR_DDCD_MASK) >> MSR_DDCD_LSB) #define MSR_DDCD_SET(x) (((x) << MSR_DDCD_LSB) & MSR_DDCD_MASK) #define MSR_TERI_MSB 2 #define MSR_TERI_LSB 2 #define MSR_TERI_MASK 0x00000004 #define MSR_TERI_GET(x) (((x) & MSR_TERI_MASK) >> MSR_TERI_LSB) #define MSR_TERI_SET(x) (((x) << MSR_TERI_LSB) & MSR_TERI_MASK) #define MSR_DDSR_MSB 1 #define MSR_DDSR_LSB 1 #define MSR_DDSR_MASK 0x00000002 #define MSR_DDSR_GET(x) (((x) & MSR_DDSR_MASK) >> MSR_DDSR_LSB) #define MSR_DDSR_SET(x) (((x) << MSR_DDSR_LSB) & MSR_DDSR_MASK) #define MSR_DCTS_MSB 0 #define MSR_DCTS_LSB 0 #define MSR_DCTS_MASK 0x00000001 #define MSR_DCTS_GET(x) (((x) & MSR_DCTS_MASK) >> MSR_DCTS_LSB) #define MSR_DCTS_SET(x) (((x) << MSR_DCTS_LSB) & MSR_DCTS_MASK) /************************** config definition ***************************/ #define UART_FIFO_SIZE 512 //Must be 2^N #define USE_POST_BUFFER 0 // ENABLE a tx buffer for post processing, /*********************** data struction definition ************************/ // data struction definition struct uart_fifo { #if USE_POST_BUFFER uint8_t buf[UART_FIFO_SIZE]; #endif uint16_t start_index; uint16_t end_index; uint32_t overrun_err; }; struct uart_blk { uint16_t debug_mode; uint16_t baud; struct uart_api *_uart; struct uart_fifo _tx; }; /******** hardware API table structure (API descriptions below) *************/ struct uart_api { uint32_t (*_uart_init)(void); void (*_uart_char_put)(uint8_t ch); uint16_t (*_uart_char_get)(uint8_t* ch); void (*_uart_str_out)(uint8_t* str); void (*_uart_task)(void); uint32_t (*_uart_status)(void); void (*_uart_config)(uint16_t flag); void (*_uart_hwinit)(uint32_t freq, uint32_t baud); //void (*_uart_config)(uint8_t cmd, void *pData); }; /************************* EXPORT function ***************************/ #endif // end of _UART_API_H_ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/usb_api.h000077500000000000000000000057341321570333100322270ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef USB_API_H #define USB_API_H #include "dt_defs.h" /******** hardware API table structure (API descriptions below) *************/ struct usb_api { void (*_usb_init)(void); void (*_usb_rom_task)(void); void (*_usb_fw_task)(void); void (*_usb_init_phy)(void); // ep0 operation void (*_usb_ep0_setup)(void); void (*_usb_ep0_tx)(void); void (*_usb_ep0_rx)(void); // get/set interface BOOLEAN (*_usb_get_interface)(void); BOOLEAN (*_usb_set_interface)(void); // get/set configuration BOOLEAN (*_usb_get_configuration)(void); BOOLEAN (*_usb_set_configuration)(void); // standard/vendor command BOOLEAN (*_usb_standard_cmd)(void); void (*_usb_vendor_cmd)(void); void (*_usb_power_off)(void); void (*_usb_reset_fifo)(void); void (*_usb_gen_wdt)(void); void (*_usb_jump_boot)(void); BOOLEAN (*_usb_clr_feature)(void); BOOLEAN (*_usb_set_feature)(void); BOOLEAN (*_usb_set_address)(void); BOOLEAN (*_usb_get_descriptor)(void); BOOLEAN (*_usb_get_status)(void); void (*_usb_setup_desc)(void); void (*_usb_reg_out)(void); void (*_usb_status_in)(void); void (*_usb_ep0_tx_data)(void); void (*_usb_ep0_rx_data)(void); void (*_usb_clk_init)(void); }; #endif open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/usb_defs.h000077500000000000000000001464001321570333100323730ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef USB_DEFS_H #define USB_DEFS_H #include "usb_table.h" #include "dt_defs.h" #include "reg_defs.h" #define CHECK_SWITCH_BY_BOOTCODE 1 //to be verified for ZD1215, OK for ZD1211 #define VERIFY_CHECKSUM_BY_BOOTCODE 1 /***********************************************************************/ /* for SEEPROM Boot */ /***********************************************************************/ #define WLAN_BOOT_SIGNATURE (0x19710303) #define WLAN_SIGNATURE_ADDR (0x102000) #define cMAX_ADDR 0x10000 #define cEEPROM_SIZE 0x800 // 2k word (4k byte) #define cRESERVE_LOAD_SPACE 0 // start addr. of boot code #define cBOOT_CODE_ADDR (cMAX_ADDR - cEEPROM_SIZE) // 0xF800 /************************** Register Addr Process *********************/ #define mpADDR(addr) ((volatile uint16_t*) (addr)) #define mADDR(addr) (*mpADDR(addr)) #define muADDR(addr) ((uint16_t) (&(addr))) #define USB_BYTE_REG_WRITE(addr, val) iowrite8_usb(addr, val) #define USB_BYTE_REG_READ(addr) ioread8_usb(addr) #define USB_HALF_WORD_REG_WRITE(addr, val) iowrite16_usb(addr, val) #define USB_HALF_WORD_REG_READ(addr) ioread16_usb(addr) #define USB_WORD_REG_WRITE(addr, val) iowrite32_usb(addr, val) #define USB_WORD_REG_READ(addr) ioread32_usb(addr) /************************** Register Deinition ***************************/ //#define USB_BASE_ADDR_SOC 0x8000 //#define SOC_Reg mpADDR(USB_BASE_ADDR_SOC) #define cSOC_USB_OFST (0x100) #define ZM_CBUS_FIFO_SIZE_OFFSET (cSOC_USB_OFST) //OFFSET 0 #define cSOC_CBUS_CTL_OFFSET 0xF0 #define ZM_FUSB_BASE USB_CTRL_BASE_ADDRESS #define ZM_MAIN_CTRL_OFFSET 0x00 #define ZM_DEVICE_ADDRESS_OFFSET 0x01 #define ZM_TEST_OFFSET 0x02 #define ZM_PHY_TEST_SELECT_OFFSET 0x08 #define ZM_VDR_SPECIFIC_MODE_OFFSET 0x0A #define ZM_CX_CONFIG_STATUS_OFFSET 0x0B #define ZM_EP0_DATA1_OFFSET 0x0C #define ZM_EP0_DATA2_OFFSET 0x0D #define ZM_EP0_DATA_OFFSET 0x0C #define ZM_INTR_MASK_BYTE_0_OFFSET 0x11 #define ZM_INTR_MASK_BYTE_1_OFFSET 0x12 #define ZM_INTR_MASK_BYTE_2_OFFSET 0x13 #define ZM_INTR_MASK_BYTE_3_OFFSET 0x14 #define ZM_INTR_MASK_BYTE_4_OFFSET 0x15 #define ZM_INTR_MASK_BYTE_5_OFFSET 0x16 #define ZM_INTR_MASK_BYTE_6_OFFSET 0x17 #define ZM_INTR_MASK_BYTE_7_OFFSET 0x18 #define ZM_INTR_GROUP_OFFSET 0x20 #define ZM_INTR_SOURCE_0_OFFSET 0x21 #define ZM_INTR_SOURCE_1_OFFSET 0x22 #define ZM_INTR_SOURCE_2_OFFSET 0x23 #define ZM_INTR_SOURCE_3_OFFSET 0x24 #define ZM_INTR_SOURCE_4_OFFSET 0x25 #define ZM_INTR_SOURCE_5_OFFSET 0x26 #define ZM_INTR_SOURCE_6_OFFSET 0x27 #define ZM_INTR_SOURCE_7_OFFSET 0x28 #define ZM_EP_IN_MAX_SIZE_HIGH_OFFSET 0x3F #define ZM_EP_IN_MAX_SIZE_LOW_OFFSET 0x3E #define ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET 0x5F #define ZM_EP_OUT_MAX_SIZE_LOW_OFFSET 0x5E #define ZM_EP3_BYTE_COUNT_HIGH_OFFSET 0xAE #define ZM_EP3_BYTE_COUNT_LOW_OFFSET 0xBE #define ZM_EP4_BYTE_COUNT_HIGH_OFFSET 0xAF #define ZM_EP4_BYTE_COUNT_LOW_OFFSET 0xBF #define ZM_EP3_DATA_OFFSET 0xF8 #define ZM_EP4_DATA_OFFSET 0xFC #define ZM_SOC_USB_MODE_CTRL_OFFSET 0x108 #define ZM_SOC_USB_MAX_AGGREGATE_OFFSET 0x110 #define ZM_SOC_USB_TIME_CTRL_OFFSET 0x114 #define ZM_SOC_USB_DMA_RESET_OFFSET 0x118 #define ZM_ADDR_CONV 0x0 #define ZM_CBUS_FIFO_SIZE_REG (ZM_CBUS_FIFO_SIZE_OFFSET^ZM_ADDR_CONV) #define ZM_CBUS_CTRL_REG (cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET^ZM_ADDR_CONV) #define ZM_MAIN_CTRL_REG (ZM_MAIN_CTRL_OFFSET^ZM_ADDR_CONV) #define ZM_DEVICE_ADDRESS_REG (ZM_DEVICE_ADDRESS_OFFSET^ZM_ADDR_CONV) #define ZM_TEST_REG (ZM_TEST_OFFSET^ZM_ADDR_CONV) #define ZM_PHY_TEST_SELECT_REG (ZM_PHY_TEST_SELECT_OFFSET^ZM_ADDR_CONV))) #define ZM_CX_CONFIG_STATUS_REG (ZM_CX_CONFIG_STATUS_OFFSET^ZM_ADDR_CONV) #define ZM_EP0_DATA1_REG (ZM_EP0_DATA1_OFFSET^ZM_ADDR_CONV))) #define ZM_EP0_DATA2_REG (ZM_EP0_DATA2_OFFSET^ZM_ADDR_CONV) #define ZM_EP0_DATA_REG (ZM_EP0_DATA_OFFSET^ZM_ADDR_CONV) #define ZM_INTR_MASK_BYTE_0_REG (ZM_INTR_MASK_BYTE_0_OFFSET^ZM_ADDR_CONV) #define ZM_INTR_MASK_BYTE_1_REG (ZM_INTR_MASK_BYTE_1_OFFSET^ZM_ADDR_CONV) #define ZM_INTR_MASK_BYTE_2_REG (ZM_INTR_MASK_BYTE_2_OFFSET^ZM_ADDR_CONV) #define ZM_INTR_MASK_BYTE_3_REG (ZM_INTR_MASK_BYTE_3_OFFSET^ZM_ADDR_CONV) #define ZM_INTR_MASK_BYTE_4_REG (ZM_INTR_MASK_BYTE_4_OFFSET^ZM_ADDR_CONV) #define ZM_INTR_MASK_BYTE_5_REG (ZM_INTR_MASK_BYTE_5_OFFSET^ZM_ADDR_CONV) #define ZM_INTR_MASK_BYTE_6_REG (ZM_INTR_MASK_BYTE_6_OFFSET^ZM_ADDR_CONV) #define ZM_INTR_MASK_BYTE_7_REG (ZM_INTR_MASK_BYTE_7_OFFSET^ZM_ADDR_CONV) #define ZM_INTR_SOURCE_0_REG (ZM_INTR_SOURCE_0_OFFSET^ZM_ADDR_CONV) #define ZM_INTR_SOURCE_1_REG (ZM_INTR_SOURCE_1_OFFSET^ZM_ADDR_CONV) #define ZM_INTR_SOURCE_2_REG (ZM_INTR_SOURCE_2_OFFSET^ZM_ADDR_CONV) #define ZM_INTR_SOURCE_3_REG (ZM_INTR_SOURCE_3_OFFSET^ZM_ADDR_CONV) #define ZM_INTR_SOURCE_4_REG (ZM_INTR_SOURCE_4_OFFSET^ZM_ADDR_CONV) #define ZM_INTR_SOURCE_5_REG (ZM_INTR_SOURCE_5_OFFSET^ZM_ADDR_CONV) #define ZM_INTR_SOURCE_6_REG (ZM_INTR_SOURCE_6_OFFSET^ZM_ADDR_CONV) #define ZM_INTR_SOURCE_7_REG (ZM_INTR_SOURCE_7_OFFSET^ZM_ADDR_CONV) #define ZM_INTR_GROUP_REG (ZM_INTR_GROUP_OFFSET^ZM_ADDR_CONV))) #define ZM_EP3_BYTE_COUNT_HIGH_REG (ZM_EP3_BYTE_COUNT_HIGH_OFFSET^ZM_ADDR_CONV) #define ZM_EP3_BYTE_COUNT_LOW_REG (ZM_EP3_BYTE_COUNT_LOW_OFFSET^ZM_ADDR_CONV) #define ZM_EP4_BYTE_COUNT_HIGH_REG (ZM_EP4_BYTE_COUNT_HIGH_OFFSET^ZM_ADDR_CONV) #define ZM_EP4_BYTE_COUNT_LOW_REG (ZM_EP4_BYTE_COUNT_LOW_OFFSET^ZM_ADDR_CONV) #define ZM_EP3_DATA_REG (ZM_EP3_DATA_OFFSET) #define ZM_EP4_DATA_REG (ZM_EP4_DATA_OFFSET) #define ZM_SOC_USB_MODE_CTRL_REG (ZM_SOC_USB_MODE_CTRL_OFFSET) #define ZM_SOC_USB_MAX_AGGREGATE_REG (ZM_SOC_USB_MAX_AGGREGATE_OFFSET) #define ZM_SOC_USB_TIME_CTRL_REG (ZM_SOC_USB_TIME_CTRL_OFFSET) #define bmHIGH_SPEED BIT6 #define bmCWR_BUF_END BIT1 #define mUsbEP0DataRd1() (USB_BYTE_REG_READ(ZM_EP0_DATA1_OFFSET)) //#define mUsbEP0DataRd2() ZM_EP0_DATA2_REG //#define mUsbEP0DataRd3() ZM_EP0_DATA3_REG //#define mUsbEP0DataRd4() ZM_EP0_DATA4_REG #define mUsbEP0DataWr1(data) (USB_BYTE_REG_WRITE(ZM_EP0_DATA1_OFFSET, data)) #define mUsbEP0DataWr2(data) (USB_BYTE_REG_WRITE(ZM_EP0_DATA2_OFFSET, data)) #define mGetByte0(data) ( data & 0xff ) #define mGetByte1(data) ( (data >> 8) & 0xff ) #define mGetByte2(data) ( (data >> 16) & 0xff ) #define mGetByte3(data) ( (data >> 24) & 0xff ) //#define mUsbHighSpeedST() (ZM_MAIN_CTRL_REG & BIT6) //#define mUsbCfgST() (ZM_DEVICE_ADDRESS_REG & BIT7) //#define mUsbApWrEnd() (ZM_CBUS_CTRL_REG = bmCWR_BUF_END) //#define mUsbApRdEnd() (ZM_CBUS_CTRL_REG = bmCWR_BUF_END) #define mUsbHighSpeedST() (USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET) & BIT6) #define mUsbCfgST() (USB_BYTE_REG_READ(ZM_DEVICE_ADDRESS_OFFSET) & BIT7) #define mUsbApWrEnd() (USB_BYTE_REG_WRITE((cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET), bmCWR_BUF_END) #define mUsbApRdEnd() (USB_BYTE_REG_WRITE((cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET), bmCWR_BUF_END) #define mUsbRmWkupST() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \ USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)&BIT0) #define mUsbRmWkupClr() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \ USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)&~BIT0) #define mUsbRmWkupSet() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \ USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)|BIT0) #define mUsbGlobIntEnable() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \ USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)|BIT2) #define mUSB_REG_OUT_INT_ENABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_4_OFFSET, \ USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_4_OFFSET)&0x3f) #define mUSB_REG_OUT_INT_DISABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_4_OFFSET, \ USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_4_OFFSET)|0xc0) #define mUSB_STATUS_IN_INT_ENABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, \ USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)&0xbf) #define mUSB_STATUS_IN_INT_DISABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, \ USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)|0xc0) // USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)|0x40) #define mUSB_EP3_XFER_DONE() USB_BYTE_REG_WRITE(ZM_EP3_BYTE_COUNT_HIGH_OFFSET, \ USB_BYTE_REG_READ(ZM_EP3_BYTE_COUNT_HIGH_OFFSET)|0x08) #define HS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_512 #define HS_C1_I0_A0_EP1_bInterval 00 #define HS_C1_I0_A0_EP_NUMBER 0x06 #define HS_C1_I0_A0_EP_LENGTH (EP_LENGTH * HS_C1_I0_A0_EP_NUMBER) #define HS_C1_I0_ALT_LENGTH (HS_C1_I0_A0_EP_LENGTH) #define HS_C1_INTERFACE_LENGTH (HS_C1_I0_ALT_LENGTH) #define HS_C1_CONFIG_TOTAL_LENGTH (CONFIG_LENGTH + INTERFACE_LENGTH + HS_C1_INTERFACE_LENGTH) #define FS_C1_CONFIG_TOTAL_LENGTH (CONFIG_LENGTH + INTERFACE_LENGTH + FS_C1_INTERFACE_LENGTH) #define FS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_64 //#define FS_C1_I0_A0_EP1_bInterval HS_C1_I0_A0_EP1_bInterval #define HS_CONFIGURATION_NUMBER 1 #define FS_CONFIGURATION_NUMBER 1 #define fDOUBLE_BUF 1 #define fDOUBLE_BUF_IN 1 #define fFLASH_DISK 0 #define fENABLE_ISO 0 #if (HS_CONFIGURATION_NUMBER >= 1) // Configuration 0X01 #define HS_C1_INTERFACE_NUMBER 0x01 #define HS_C1 0x01 #define HS_C1_iConfiguration 0x00 #define HS_C1_bmAttribute 0x80 #if !(fFLASH_DISK && !fFLASH_BOOT) #define HS_C1_iMaxPower 0xFA #else #define HS_C1_iMaxPower 0x32 #endif #if (HS_C1_INTERFACE_NUMBER >= 1) // Interface 0 #define HS_C1_I0_ALT_NUMBER 0X01 #if (HS_C1_I0_ALT_NUMBER >= 1) // AlternateSetting 0X00 #define HS_C1_I0_A0_bInterfaceNumber 0X00 #define HS_C1_I0_A0_bAlternateSetting 0X00 //JWEI 2003/07/14 //#if fINDEPEND_REG_RW && !(fFLASH_DISK && !fFLASH_BOOT) #define HS_C1_I0_A0_EP_NUMBER 0x06 //#else //#define HS_C1_I0_A0_EP_NUMBER 0X03 //#endif #if !(fFLASH_DISK && !fFLASH_BOOT) #define HS_C1_I0_A0_bInterfaceClass 0XFF #define HS_C1_I0_A0_bInterfaceSubClass 0X00 #define HS_C1_I0_A0_bInterfaceProtocol 0X00 #else #define HS_C1_I0_A0_bInterfaceClass 0X08 #define HS_C1_I0_A0_bInterfaceSubClass 0X06 #define HS_C1_I0_A0_bInterfaceProtocol 0X50 #endif #define HS_C1_I0_A0_iInterface 0X00 #if (HS_C1_I0_A0_EP_NUMBER >= 1) //EP0X01 #define HS_C1_I0_A0_EP1_BLKSIZE BLK512BYTE //JWEI 2003/05/19 #if fDOUBLE_BUF #define HS_C1_I0_A0_EP1_BLKNO DOUBLE_BLK #else #define HS_C1_I0_A0_EP1_BLKNO SINGLE_BLK #endif #define HS_C1_I0_A0_EP1_DIRECTION DIRECTION_OUT #define HS_C1_I0_A0_EP1_TYPE TF_TYPE_BULK //JWEI 2003/05/07 #define HS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_512 #define HS_C1_I0_A0_EP1_bInterval 00 #endif #if (HS_C1_I0_A0_EP_NUMBER >= 2) //EP0X02 #define HS_C1_I0_A0_EP2_BLKSIZE BLK512BYTE //JWEI 2003/08/20 #if fDOUBLE_BUF_IN #define HS_C1_I0_A0_EP2_BLKNO DOUBLE_BLK #else #define HS_C1_I0_A0_EP2_BLKNO SINGLE_BLK #endif #define HS_C1_I0_A0_EP2_DIRECTION DIRECTION_IN #define HS_C1_I0_A0_EP2_TYPE TF_TYPE_BULK #define HS_C1_I0_A0_EP2_MAX_PACKET MX_PA_SZ_512 #define HS_C1_I0_A0_EP2_bInterval 00 #endif #if (HS_C1_I0_A0_EP_NUMBER >= 3) //EP0X03 #define HS_C1_I0_A0_EP3_BLKSIZE BLK64BYTE #define HS_C1_I0_A0_EP3_BLKNO SINGLE_BLK #define HS_C1_I0_A0_EP3_DIRECTION DIRECTION_IN #define HS_C1_I0_A0_EP3_TYPE TF_TYPE_INTERRUPT #define HS_C1_I0_A0_EP3_MAX_PACKET 0x0040 #define HS_C1_I0_A0_EP3_bInterval 01 #endif // Note: HS Bulk type require max pkt size = 512 // ==> must use Interrupt type for max pkt size = 64 #if (HS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK //EP0X04 #define HS_C1_I0_A0_EP4_BLKSIZE BLK64BYTE #define HS_C1_I0_A0_EP4_BLKNO SINGLE_BLK #define HS_C1_I0_A0_EP4_DIRECTION DIRECTION_OUT #define HS_C1_I0_A0_EP4_TYPE TF_TYPE_INTERRUPT #define HS_C1_I0_A0_EP4_MAX_PACKET 0x0040 #define HS_C1_I0_A0_EP4_bInterval 01 #endif #if (HS_C1_I0_A0_EP_NUMBER >= 5) //EP0X04 #define HS_C1_I0_A0_EP5_BLKSIZE BLK512BYTE #if fDOUBLE_BUF #define HS_C1_I0_A0_EP5_BLKNO DOUBLE_BLK #else #define HS_C1_I0_A0_EP5_BLKNO SINGLE_BLK #endif #define HS_C1_I0_A0_EP5_DIRECTION DIRECTION_OUT #define HS_C1_I0_A0_EP5_TYPE TF_TYPE_BULK #define HS_C1_I0_A0_EP5_MAX_PACKET MX_PA_SZ_512 #define HS_C1_I0_A0_EP5_bInterval 00 #endif #if (HS_C1_I0_A0_EP_NUMBER >= 6) //EP0X04 #define HS_C1_I0_A0_EP6_BLKSIZE BLK512BYTE #if fDOUBLE_BUF #define HS_C1_I0_A0_EP6_BLKNO DOUBLE_BLK #else #define HS_C1_I0_A0_EP6_BLKNO SINGLE_BLK #endif #define HS_C1_I0_A0_EP6_DIRECTION DIRECTION_OUT #define HS_C1_I0_A0_EP6_TYPE TF_TYPE_BULK #define HS_C1_I0_A0_EP6_MAX_PACKET MX_PA_SZ_512 #define HS_C1_I0_A0_EP6_bInterval 00 #endif #endif #endif #endif #if (HS_CONFIGURATION_NUMBER >= 1) // Configuration 1 #if (HS_C1_INTERFACE_NUMBER >= 1) // Interface 0 #if (HS_C1_I0_ALT_NUMBER >= 1) // AlternateSetting 0 #define HS_C1_I0_A0_EP_LENGTH (EP_LENGTH * HS_C1_I0_A0_EP_NUMBER) #if (HS_C1_I0_A0_EP_NUMBER >= 1) // EP1 #define HS_C1_I0_A0_EP1_FIFO_START FIFO0 #define HS_C1_I0_A0_EP1_FIFO_NO (HS_C1_I0_A0_EP1_BLKNO * HS_C1_I0_A0_EP1_BLKSIZE) #define HS_C1_I0_A0_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP1_BLKNO - 1) << 2) | HS_C1_I0_A0_EP1_TYPE) #define HS_C1_I0_A0_EP1_FIFO_MAP (((1 - HS_C1_I0_A0_EP1_DIRECTION) << 4) | EP1) #define HS_C1_I0_A0_EP1_MAP (HS_C1_I0_A0_EP1_FIFO_START | (HS_C1_I0_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP1_DIRECTION))) #endif #if (HS_C1_I0_A0_EP_NUMBER >= 2) // EP2 #if fDOUBLE_BUF #define HS_C1_I0_A0_EP2_FIFO_START (HS_C1_I0_A0_EP1_FIFO_START + HS_C1_I0_A0_EP1_FIFO_NO) #else #define HS_C1_I0_A0_EP2_FIFO_START FIFO2 #endif #define HS_C1_I0_A0_EP2_FIFO_NO (HS_C1_I0_A0_EP2_BLKNO * HS_C1_I0_A0_EP2_BLKSIZE) #define HS_C1_I0_A0_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP2_BLKNO - 1) << 2) | HS_C1_I0_A0_EP2_TYPE) #define HS_C1_I0_A0_EP2_FIFO_MAP (((1 - HS_C1_I0_A0_EP2_DIRECTION) << 4) | EP2) #define HS_C1_I0_A0_EP2_MAP (HS_C1_I0_A0_EP2_FIFO_START | (HS_C1_I0_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP2_DIRECTION))) #endif #if (HS_C1_I0_A0_EP_NUMBER >= 3) // EP3 //JWEI 2003/07/15 // #define HS_C1_I0_A0_EP3_FIFO_START (HS_C1_I0_A0_EP2_FIFO_START + HS_C1_I0_A0_EP2_FIFO_NO) #define HS_C1_I0_A0_EP3_FIFO_START FIFO14 #define HS_C1_I0_A0_EP3_FIFO_NO (HS_C1_I0_A0_EP3_BLKNO * HS_C1_I0_A0_EP3_BLKSIZE) #define HS_C1_I0_A0_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP3_BLKNO - 1) << 2) | HS_C1_I0_A0_EP3_TYPE) #define HS_C1_I0_A0_EP3_FIFO_MAP (((1 - HS_C1_I0_A0_EP3_DIRECTION) << 4) | EP3) #define HS_C1_I0_A0_EP3_MAP (HS_C1_I0_A0_EP3_FIFO_START | (HS_C1_I0_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP3_DIRECTION))) #endif #if (HS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK // EP4 #define HS_C1_I0_A0_EP4_FIFO_START (HS_C1_I0_A0_EP3_FIFO_START + HS_C1_I0_A0_EP3_FIFO_NO) #define HS_C1_I0_A0_EP4_FIFO_NO (HS_C1_I0_A0_EP4_BLKNO * HS_C1_I0_A0_EP4_BLKSIZE) #define HS_C1_I0_A0_EP4_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP4_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP4_BLKNO - 1) << 2) | HS_C1_I0_A0_EP4_TYPE) #define HS_C1_I0_A0_EP4_FIFO_MAP (((1 - HS_C1_I0_A0_EP4_DIRECTION) << 4) | EP4) #define HS_C1_I0_A0_EP4_MAP (HS_C1_I0_A0_EP4_FIFO_START | (HS_C1_I0_A0_EP4_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP4_DIRECTION))) #endif #if (HS_C1_I0_A0_EP_NUMBER >= 5) // EP5 #define HS_C1_I0_A0_EP5_FIFO_START (HS_C1_I0_A0_EP2_FIFO_START + HS_C1_I0_A0_EP2_FIFO_NO) #define HS_C1_I0_A0_EP5_FIFO_NO (HS_C1_I0_A0_EP5_BLKNO * HS_C1_I0_A0_EP5_BLKSIZE) #define HS_C1_I0_A0_EP5_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP5_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP5_BLKNO - 1) << 2) | HS_C1_I0_A0_EP5_TYPE) #define HS_C1_I0_A0_EP5_FIFO_MAP (((1 - HS_C1_I0_A0_EP5_DIRECTION) << 4) | EP5) #define HS_C1_I0_A0_EP5_MAP (HS_C1_I0_A0_EP5_FIFO_START | (HS_C1_I0_A0_EP5_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP5_DIRECTION))) #endif #if (HS_C1_I0_A0_EP_NUMBER >= 6) // EP5 #define HS_C1_I0_A0_EP6_FIFO_START (HS_C1_I0_A0_EP5_FIFO_START + HS_C1_I0_A0_EP5_FIFO_NO) #define HS_C1_I0_A0_EP6_FIFO_NO (HS_C1_I0_A0_EP6_BLKNO * HS_C1_I0_A0_EP6_BLKSIZE) #define HS_C1_I0_A0_EP6_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP6_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP6_BLKNO - 1) << 2) | HS_C1_I0_A0_EP6_TYPE) #define HS_C1_I0_A0_EP6_FIFO_MAP (((1 - HS_C1_I0_A0_EP6_DIRECTION) << 4) | EP6) #define HS_C1_I0_A0_EP6_MAP (HS_C1_I0_A0_EP6_FIFO_START | (HS_C1_I0_A0_EP6_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP6_DIRECTION))) #endif #endif #if (HS_C1_I0_ALT_NUMBER >= 2) // AlternateSetting 1 #define HS_C1_I0_A1_EP_LENGTH (EP_LENGTH * HS_C1_I0_A1_EP_NUMBER) #if (HS_C1_I0_A1_EP_NUMBER >= 1) // EP1 #define HS_C1_I0_A1_EP1_FIFO_START FIFO0 #define HS_C1_I0_A1_EP1_FIFO_NO (HS_C1_I0_A1_EP1_BLKNO * HS_C1_I0_A1_EP1_BLKSIZE) #define HS_C1_I0_A1_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I0_A1_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I0_A1_EP1_BLKNO - 1) << 2) | HS_C1_I0_A1_EP1_TYPE) #define HS_C1_I0_A1_EP1_FIFO_MAP (((1 - HS_C1_I0_A1_EP1_DIRECTION) << 4) | EP1) #define HS_C1_I0_A1_EP1_MAP (HS_C1_I0_A1_EP1_FIFO_START | (HS_C1_I0_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A1_EP1_DIRECTION))) #endif #if (HS_C1_I0_A1_EP_NUMBER >= 2) // EP2 #define HS_C1_I0_A1_EP2_FIFO_START (HS_C1_I0_A1_EP1_FIFO_START + HS_C1_I0_A1_EP1_FIFO_NO) #define HS_C1_I0_A1_EP2_FIFO_NO (HS_C1_I0_A1_EP2_BLKNO * HS_C1_I0_A1_EP2_BLKSIZE) #define HS_C1_I0_A1_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I0_A1_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I0_A1_EP2_BLKNO - 1) << 2) | HS_C1_I0_A1_EP2_TYPE) #define HS_C1_I0_A1_EP2_FIFO_MAP (((1 - HS_C1_I0_A1_EP2_DIRECTION) << 4) | EP2) #define HS_C1_I0_A1_EP2_MAP (HS_C1_I0_A1_EP2_FIFO_START | (HS_C1_I0_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A1_EP2_DIRECTION))) #endif #if (HS_C1_I0_A1_EP_NUMBER >= 3) // EP3 #define HS_C1_I0_A1_EP3_FIFO_START (HS_C1_I0_A1_EP2_FIFO_START + HS_C1_I0_A1_EP2_FIFO_NO) #define HS_C1_I0_A1_EP3_FIFO_NO (HS_C1_I0_A1_EP3_BLKNO * HS_C1_I0_A1_EP3_BLKSIZE) #define HS_C1_I0_A1_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I0_A1_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I0_A1_EP3_BLKNO - 1) << 2) | HS_C1_I0_A1_EP3_TYPE) #define HS_C1_I0_A1_EP3_FIFO_MAP (((1 - HS_C1_I0_A1_EP3_DIRECTION) << 4) | EP3) #define HS_C1_I0_A1_EP3_MAP (HS_C1_I0_A1_EP3_FIFO_START | (HS_C1_I0_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A1_EP3_DIRECTION))) #endif #endif #if (HS_C1_I0_ALT_NUMBER == 1) #define HS_C1_I0_ALT_LENGTH (HS_C1_I0_A0_EP_LENGTH) #elif (HS_C1_I0_ALT_NUMBER == 2) #define HS_C1_I0_ALT_LENGTH (HS_C1_I0_A0_EP_LENGTH + HS_C1_I0_A1_EP_LENGTH) #endif #endif #if (HS_C1_INTERFACE_NUMBER >= 2) // Interface 1 #if (HS_C1_I1_ALT_NUMBER >= 1) // AlternateSetting 0 #define HS_C1_I1_A0_EP_LENGTH (EP_LENGTH * HS_C1_I1_A0_EP_NUMBER) #if (HS_C1_I1_A0_EP_NUMBER >= 1) // EP1 #define HS_C1_I1_A0_EP1_FIFO_START FIFO0 #define HS_C1_I1_A0_EP1_FIFO_NO (HS_C1_I1_A0_EP1_BLKNO * HS_C1_I1_A0_EP1_BLKSIZE) #define HS_C1_I1_A0_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I1_A0_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I1_A0_EP1_BLKNO - 1) << 2) | HS_C1_I1_A0_EP1_TYPE) #define HS_C1_I1_A0_EP1_FIFO_MAP (((1 - HS_C1_I1_A0_EP1_DIRECTION) << 4) | EP1) #define HS_C1_I1_A0_EP1_MAP (HS_C1_I1_A0_EP1_FIFO_START | (HS_C1_I1_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A0_EP1_DIRECTION))) #endif #if (HS_C1_I1_A0_EP_NUMBER >= 2) // EP2 #define HS_C1_I1_A0_EP2_FIFO_START (HS_C1_I1_A0_EP1_FIFO_START + HS_C1_I1_A0_EP1_FIFO_NO) #define HS_C1_I1_A0_EP2_FIFO_NO (HS_C1_I1_A0_EP2_BLKNO * HS_C1_I1_A0_EP2_BLKSIZE) #define HS_C1_I1_A0_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I1_A0_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I1_A0_EP2_BLKNO - 1) << 2) | HS_C1_I1_A0_EP2_TYPE) #define HS_C1_I1_A0_EP2_FIFO_MAP (((1 - HS_C1_I1_A0_EP2_DIRECTION) << 4) | EP2) #define HS_C1_I1_A0_EP2_MAP (HS_C1_I1_A0_EP2_FIFO_START | (HS_C1_I1_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A0_EP2_DIRECTION))) #endif #if (HS_C1_I1_A0_EP_NUMBER >= 3) // EP3 #define HS_C1_I1_A0_EP3_FIFO_START (HS_C1_I1_A0_EP2_FIFO_START + HS_C1_I1_A0_EP2_FIFO_NO) #define HS_C1_I1_A0_EP3_FIFO_NO (HS_C1_I1_A0_EP3_BLKNO * HS_C1_I1_A0_EP3_BLKSIZE) #define HS_C1_I1_A0_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I1_A0_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I1_A0_EP3_BLKNO - 1) << 2) | HS_C1_I1_A0_EP3_TYPE) #define HS_C1_I1_A0_EP3_FIFO_MAP (((1 - HS_C1_I1_A0_EP3_DIRECTION) << 4) | EP3) #define HS_C1_I1_A0_EP3_MAP (HS_C1_I1_A0_EP3_FIFO_START | (HS_C1_I1_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A0_EP3_DIRECTION))) #endif #endif #if (HS_C1_I1_ALT_NUMBER >= 2) // AlternateSetting 1 #define HS_C1_I1_A1_EP_LENGTH (EP_LENGTH * HS_C1_I1_A1_EP_NUMBER) #if (HS_C1_I1_A1_EP_NUMBER >= 1) // EP1 #define HS_C1_I1_A1_EP1_FIFO_START FIFO0 #define HS_C1_I1_A1_EP1_FIFO_NO (HS_C1_I1_A1_EP1_BLKNO * HS_C1_I1_A1_EP1_BLKSIZE) #define HS_C1_I1_A1_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I1_A1_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I1_A1_EP1_BLKNO - 1) << 2) | HS_C1_I1_A1_EP1_TYPE) #define HS_C1_I1_A1_EP1_FIFO_MAP (((1 - HS_C1_I1_A1_EP1_DIRECTION) << 4) | EP1) #define HS_C1_I1_A1_EP1_MAP (HS_C1_I1_A1_EP1_FIFO_START | (HS_C1_I1_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A1_EP1_DIRECTION))) #endif #if (HS_C1_I1_A1_EP_NUMBER >= 2) // EP2 #define HS_C1_I1_A1_EP2_FIFO_START (HS_C1_I1_A1_EP1_FIFO_START + HS_C1_I1_A1_EP1_FIFO_NO) #define HS_C1_I1_A1_EP2_FIFO_NO (HS_C1_I1_A1_EP2_BLKNO * HS_C1_I1_A1_EP2_BLKSIZE) #define HS_C1_I1_A1_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I1_A1_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I1_A1_EP2_BLKNO - 1) << 2) | HS_C1_I1_A1_EP2_TYPE) #define HS_C1_I1_A1_EP2_FIFO_MAP (((1 - HS_C1_I1_A1_EP2_DIRECTION) << 4) | EP2) #define HS_C1_I1_A1_EP2_MAP (HS_C1_I1_A1_EP2_FIFO_START | (HS_C1_I1_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A1_EP2_DIRECTION))) #endif #if (HS_C1_I1_A1_EP_NUMBER >= 3) // EP3 #define HS_C1_I1_A1_EP3_FIFO_START (HS_C1_I1_A1_EP2_FIFO_START + HS_C1_I1_A1_EP2_FIFO_NO) #define HS_C1_I1_A1_EP3_FIFO_NO (HS_C1_I1_A1_EP3_BLKNO * HS_C1_I1_A1_EP3_BLKSIZE) #define HS_C1_I1_A1_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I1_A1_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I1_A1_EP3_BLKNO - 1) << 2) | HS_C1_I1_A1_EP3_TYPE) #define HS_C1_I1_A1_EP3_FIFO_MAP (((1 - HS_C1_I1_A1_EP3_DIRECTION) << 4) | EP3) #define HS_C1_I1_A1_EP3_MAP (HS_C1_I1_A1_EP3_FIFO_START | (HS_C1_I1_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A1_EP3_DIRECTION))) #endif #endif #if (HS_C1_I1_ALT_NUMBER == 1) #define HS_C1_I1_ALT_LENGTH (HS_C1_I1_A0_EP_LENGTH) #elif (HS_C1_I1_ALT_NUMBER == 2) #define HS_C1_I1_ALT_LENGTH (HS_C1_I1_A0_EP_LENGTH + HS_C1_I1_A1_EP_LENGTH) #endif #endif #if (HS_C1_INTERFACE_NUMBER == 1) #define HS_C1_INTERFACE_LENGTH (HS_C1_I0_ALT_LENGTH) #elif (HS_C1_INTERFACE_NUMBER == 2) #define HS_C1_INTERFACE_LENGTH (HS_C1_I0_ALT_LENGTH + HS_C1_I1_ALT_LENGTH) #endif #endif #if (FS_CONFIGURATION_NUMBER >= 1) // Configuration 0X01 #define FS_C1_INTERFACE_NUMBER 0X01 #define FS_C1 0X01 #define FS_C1_iConfiguration 0X00 #define FS_C1_bmAttribute 0X80 #define FS_C1_iMaxPower 0XFA #if (FS_C1_INTERFACE_NUMBER >= 1) // Interface 0 #define FS_C1_I0_ALT_NUMBER 0X01 #if (FS_C1_I0_ALT_NUMBER >= 1) // AlternateSetting 0X00 #define FS_C1_I0_A0_bInterfaceNumber 0X00 #define FS_C1_I0_A0_bAlternateSetting 0X00 //JWEI 2003/07/14 //#if fINDEPEND_REG_RW && !(fFLASH_DISK && !fFLASH_BOOT) #define FS_C1_I0_A0_EP_NUMBER 0x05 //#else //#define FS_C1_I0_A0_EP_NUMBER 0X03 //#endif #if !(fFLASH_DISK && !fFLASH_BOOT) #define FS_C1_I0_A0_bInterfaceClass 0XFF #define FS_C1_I0_A0_bInterfaceSubClass 0X00 #define FS_C1_I0_A0_bInterfaceProtocol 0X00 #else #define FS_C1_I0_A0_bInterfaceClass 0X08 #define FS_C1_I0_A0_bInterfaceSubClass 0X06 #define FS_C1_I0_A0_bInterfaceProtocol 0X50 #endif #define FS_C1_I0_A0_iInterface 0X00 #if (FS_C1_I0_A0_EP_NUMBER >= 1) //EP0X01 #define FS_C1_I0_A0_EP1_BLKSIZE BLK512BYTE //JWEI 2003/05/19 #if fDOUBLE_BUF #define FS_C1_I0_A0_EP1_BLKNO DOUBLE_BLK #else #define FS_C1_I0_A0_EP1_BLKNO SINGLE_BLK #endif #define FS_C1_I0_A0_EP1_DIRECTION DIRECTION_OUT #define FS_C1_I0_A0_EP1_TYPE TF_TYPE_BULK //JWEI 2003/05/07 #define FS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_64 #define FS_C1_I0_A0_EP1_bInterval 00 #endif #if (FS_C1_I0_A0_EP_NUMBER >= 2) //EP0X02 #define FS_C1_I0_A0_EP2_BLKSIZE BLK512BYTE //JWEI 2003/08/20 #if fDOUBLE_BUF_IN #define FS_C1_I0_A0_EP2_BLKNO DOUBLE_BLK #else #define FS_C1_I0_A0_EP2_BLKNO SINGLE_BLK #endif #define FS_C1_I0_A0_EP2_DIRECTION DIRECTION_IN #define FS_C1_I0_A0_EP2_TYPE TF_TYPE_BULK #define FS_C1_I0_A0_EP2_MAX_PACKET MX_PA_SZ_64 #define FS_C1_I0_A0_EP2_bInterval 00 #endif #if (FS_C1_I0_A0_EP_NUMBER >= 3) //EP0X03 #define FS_C1_I0_A0_EP3_BLKSIZE BLK64BYTE #define FS_C1_I0_A0_EP3_BLKNO SINGLE_BLK #define FS_C1_I0_A0_EP3_DIRECTION DIRECTION_IN #define FS_C1_I0_A0_EP3_TYPE TF_TYPE_INTERRUPT #define FS_C1_I0_A0_EP3_MAX_PACKET 0x0040 #define FS_C1_I0_A0_EP3_bInterval 01 #endif #if (FS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK //EP0X04 #define FS_C1_I0_A0_EP4_BLKSIZE BLK64BYTE #define FS_C1_I0_A0_EP4_BLKNO SINGLE_BLK #define FS_C1_I0_A0_EP4_DIRECTION DIRECTION_OUT #define FS_C1_I0_A0_EP4_TYPE TF_TYPE_BULK #define FS_C1_I0_A0_EP4_MAX_PACKET 0x0040 #define FS_C1_I0_A0_EP4_bInterval 00 #endif #if (FS_C1_I0_A0_EP_NUMBER >= 5) //EP0X04 #define FS_C1_I0_A0_EP5_BLKSIZE BLK512BYTE #if fDOUBLE_BUF_IN #define FS_C1_I0_A0_EP5_BLKNO DOUBLE_BLK #else #define FS_C1_I0_A0_EP5_BLKNO SINGLE_BLK #endif #define FS_C1_I0_A0_EP5_DIRECTION DIRECTION_OUT #define FS_C1_I0_A0_EP5_TYPE TF_TYPE_BULK #define FS_C1_I0_A0_EP5_MAX_PACKET 0x0040 #define FS_C1_I0_A0_EP5_bInterval 00 #endif #if (FS_C1_I0_A0_EP_NUMBER >= 6) //EP0X04 #define FS_C1_I0_A0_EP6_BLKSIZE BLK512BYTE #if fDOUBLE_BUF_IN #define FS_C1_I0_A0_EP6_BLKNO DOUBLE_BLK #else #define FS_C1_I0_A0_EP6_BLKNO SINGLE_BLK #endif #define FS_C1_I0_A0_EP6_DIRECTION DIRECTION_OUT #define FS_C1_I0_A0_EP6_TYPE TF_TYPE_BULK #define FS_C1_I0_A0_EP6_MAX_PACKET 0x0040 #define FS_C1_I0_A0_EP6_bInterval 00 #endif #endif #endif #endif #if (FS_CONFIGURATION_NUMBER >= 1) // Configuration 1 #if (FS_C1_INTERFACE_NUMBER >= 1) // Interface 0 #if (FS_C1_I0_ALT_NUMBER >= 1) // AlternateSetting 0 #define FS_C1_I0_A0_EP_LENGTH (EP_LENGTH * FS_C1_I0_A0_EP_NUMBER) #if (FS_C1_I0_A0_EP_NUMBER >= 1) // EP1 #define FS_C1_I0_A0_EP1_FIFO_START FIFO0 #define FS_C1_I0_A0_EP1_FIFO_NO (FS_C1_I0_A0_EP1_BLKNO * FS_C1_I0_A0_EP1_BLKSIZE) #define FS_C1_I0_A0_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP1_BLKNO - 1) << 2) | FS_C1_I0_A0_EP1_TYPE) #define FS_C1_I0_A0_EP1_FIFO_MAP (((1 - FS_C1_I0_A0_EP1_DIRECTION) << 4) | EP1) #define FS_C1_I0_A0_EP1_MAP (FS_C1_I0_A0_EP1_FIFO_START | (FS_C1_I0_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP1_DIRECTION))) #endif #if (FS_C1_I0_A0_EP_NUMBER >= 2) // EP2 #define FS_C1_I0_A0_EP2_FIFO_START (FS_C1_I0_A0_EP1_FIFO_START + FS_C1_I0_A0_EP1_FIFO_NO) #define FS_C1_I0_A0_EP2_FIFO_NO (FS_C1_I0_A0_EP2_BLKNO * FS_C1_I0_A0_EP2_BLKSIZE) #define FS_C1_I0_A0_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP2_BLKNO - 1) << 2) | FS_C1_I0_A0_EP2_TYPE) #define FS_C1_I0_A0_EP2_FIFO_MAP (((1 - FS_C1_I0_A0_EP2_DIRECTION) << 4) | EP2) #define FS_C1_I0_A0_EP2_MAP (FS_C1_I0_A0_EP2_FIFO_START | (FS_C1_I0_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP2_DIRECTION))) #endif #if (FS_C1_I0_A0_EP_NUMBER >= 3) // EP3 //JWEI 2003/07/15 // #define FS_C1_I0_A0_EP3_FIFO_START (FS_C1_I0_A0_EP2_FIFO_START + FS_C1_I0_A0_EP2_FIFO_NO) #define FS_C1_I0_A0_EP3_FIFO_START FIFO14 #define FS_C1_I0_A0_EP3_FIFO_NO (FS_C1_I0_A0_EP3_BLKNO * FS_C1_I0_A0_EP3_BLKSIZE) #define FS_C1_I0_A0_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP3_BLKNO - 1) << 2) | FS_C1_I0_A0_EP3_TYPE) #define FS_C1_I0_A0_EP3_FIFO_MAP (((1 - FS_C1_I0_A0_EP3_DIRECTION) << 4) | EP3) #define FS_C1_I0_A0_EP3_MAP (FS_C1_I0_A0_EP3_FIFO_START | (FS_C1_I0_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP3_DIRECTION))) #endif #if (FS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK // EP4 #define FS_C1_I0_A0_EP4_FIFO_START (FS_C1_I0_A0_EP3_FIFO_START + FS_C1_I0_A0_EP3_FIFO_NO) #define FS_C1_I0_A0_EP4_FIFO_NO (FS_C1_I0_A0_EP4_BLKNO * FS_C1_I0_A0_EP4_BLKSIZE) #define FS_C1_I0_A0_EP4_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP4_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP4_BLKNO - 1) << 2) | FS_C1_I0_A0_EP4_TYPE) #define FS_C1_I0_A0_EP4_FIFO_MAP (((1 - FS_C1_I0_A0_EP4_DIRECTION) << 4) | EP4) #define FS_C1_I0_A0_EP4_MAP (FS_C1_I0_A0_EP4_FIFO_START | (FS_C1_I0_A0_EP4_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP4_DIRECTION))) #endif #if (FS_C1_I0_A0_EP_NUMBER >= 5) // EP5 #define FS_C1_I0_A0_EP5_FIFO_START (FS_C1_I0_A0_EP2_FIFO_START + FS_C1_I0_A0_EP2_FIFO_NO) #define FS_C1_I0_A0_EP5_FIFO_NO (FS_C1_I0_A0_EP5_BLKNO * FS_C1_I0_A0_EP5_BLKSIZE) #define FS_C1_I0_A0_EP5_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP5_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP5_BLKNO - 1) << 2) | FS_C1_I0_A0_EP5_TYPE) #define FS_C1_I0_A0_EP5_FIFO_MAP (((1 - FS_C1_I0_A0_EP5_DIRECTION) << 4) | EP5) #define FS_C1_I0_A0_EP5_MAP (FS_C1_I0_A0_EP5_FIFO_START | (FS_C1_I0_A0_EP5_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP5_DIRECTION))) #endif #if (FS_C1_I0_A0_EP_NUMBER >= 6) // EP5 #define FS_C1_I0_A0_EP6_FIFO_START (FS_C1_I0_A0_EP5_FIFO_START + FS_C1_I0_A0_EP5_FIFO_NO) #define FS_C1_I0_A0_EP6_FIFO_NO (FS_C1_I0_A0_EP6_BLKNO * FS_C1_I0_A0_EP6_BLKSIZE) #define FS_C1_I0_A0_EP6_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP6_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP6_BLKNO - 1) << 2) | FS_C1_I0_A0_EP6_TYPE) #define FS_C1_I0_A0_EP6_FIFO_MAP (((1 - FS_C1_I0_A0_EP6_DIRECTION) << 4) | EP6) #define FS_C1_I0_A0_EP6_MAP (FS_C1_I0_A0_EP6_FIFO_START | (FS_C1_I0_A0_EP6_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP6_DIRECTION))) #endif #endif #if (FS_C1_I0_ALT_NUMBER >= 2) // AlternateSetting 1 #define FS_C1_I0_A1_EP_LENGTH (EP_LENGTH * FS_C1_I0_A1_EP_NUMBER) #if (FS_C1_I0_A1_EP_NUMBER >= 1) // EP1 #define FS_C1_I0_A1_EP1_FIFO_START FIFO0 #define FS_C1_I0_A1_EP1_FIFO_NO (FS_C1_I0_A1_EP1_BLKNO * FS_C1_I0_A1_EP1_BLKSIZE) #define FS_C1_I0_A1_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I0_A1_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I0_A1_EP1_BLKNO - 1) << 2) | FS_C1_I0_A1_EP1_TYPE) #define FS_C1_I0_A1_EP1_FIFO_MAP (((1 - FS_C1_I0_A1_EP1_DIRECTION) << 4) | EP1) #define FS_C1_I0_A1_EP1_MAP (FS_C1_I0_A1_EP1_FIFO_START | (FS_C1_I0_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A1_EP1_DIRECTION))) #endif #if (FS_C1_I0_A1_EP_NUMBER >= 2) // EP2 #define FS_C1_I0_A1_EP2_FIFO_START (FS_C1_I0_A1_EP1_FIFO_START + FS_C1_I0_A1_EP1_FIFO_NO) #define FS_C1_I0_A1_EP2_FIFO_NO (FS_C1_I0_A1_EP2_BLKNO * FS_C1_I0_A1_EP2_BLKSIZE) #define FS_C1_I0_A1_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I0_A1_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I0_A1_EP2_BLKNO - 1) << 2) | FS_C1_I0_A1_EP2_TYPE) #define FS_C1_I0_A1_EP2_FIFO_MAP (((1 - FS_C1_I0_A1_EP2_DIRECTION) << 4) | EP2) #define FS_C1_I0_A1_EP2_MAP (FS_C1_I0_A1_EP2_FIFO_START | (FS_C1_I0_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A1_EP2_DIRECTION))) #endif #if (FS_C1_I0_A1_EP_NUMBER >= 3) // EP3 #define FS_C1_I0_A1_EP3_FIFO_START (FS_C1_I0_A1_EP2_FIFO_START + FS_C1_I0_A1_EP2_FIFO_NO) #define FS_C1_I0_A1_EP3_FIFO_NO (FS_C1_I0_A1_EP3_BLKNO * FS_C1_I0_A1_EP3_BLKSIZE) #define FS_C1_I0_A1_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I0_A1_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I0_A1_EP3_BLKNO - 1) << 2) | FS_C1_I0_A1_EP3_TYPE) #define FS_C1_I0_A1_EP3_FIFO_MAP (((1 - FS_C1_I0_A1_EP3_DIRECTION) << 4) | EP3) #define FS_C1_I0_A1_EP3_MAP (FS_C1_I0_A1_EP3_FIFO_START | (FS_C1_I0_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A1_EP3_DIRECTION))) #endif #endif #if (FS_C1_I0_ALT_NUMBER == 1) #define FS_C1_I0_ALT_LENGTH (FS_C1_I0_A0_EP_LENGTH) #elif (FS_C1_I0_ALT_NUMBER == 2) #define FS_C1_I0_ALT_LENGTH (FS_C1_I0_A0_EP_LENGTH + FS_C1_I0_A1_EP_LENGTH) #endif #endif #if (FS_C1_INTERFACE_NUMBER >= 2) // Interface 1 #if (FS_C1_I1_ALT_NUMBER >= 1) // AlternateSetting 0 #define FS_C1_I1_A0_EP_LENGTH (EP_LENGTH * FS_C1_I1_A0_EP_NUMBER) #if (FS_C1_I1_A0_EP_NUMBER >= 1) // EP1 #define FS_C1_I1_A0_EP1_FIFO_START FIFO0 #define FS_C1_I1_A0_EP1_FIFO_NO (FS_C1_I1_A0_EP1_BLKNO * FS_C1_I1_A0_EP1_BLKSIZE) #define FS_C1_I1_A0_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I1_A0_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I1_A0_EP1_BLKNO - 1) << 2) | FS_C1_I1_A0_EP1_TYPE) #define FS_C1_I1_A0_EP1_FIFO_MAP (((1 - FS_C1_I1_A0_EP1_DIRECTION) << 4) | EP1) #define FS_C1_I1_A0_EP1_MAP (FS_C1_I1_A0_EP1_FIFO_START | (FS_C1_I1_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A0_EP1_DIRECTION))) #endif #if (FS_C1_I1_A0_EP_NUMBER >= 2) // EP2 #define FS_C1_I1_A0_EP2_FIFO_START (FS_C1_I1_A0_EP1_FIFO_START + FS_C1_I1_A0_EP1_FIFO_NO) #define FS_C1_I1_A0_EP2_FIFO_NO (FS_C1_I1_A0_EP2_BLKNO * FS_C1_I1_A0_EP2_BLKSIZE) #define FS_C1_I1_A0_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I1_A0_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I1_A0_EP2_BLKNO - 1) << 2) | FS_C1_I1_A0_EP2_TYPE) #define FS_C1_I1_A0_EP2_FIFO_MAP (((1 - FS_C1_I1_A0_EP2_DIRECTION) << 4) | EP2) #define FS_C1_I1_A0_EP2_MAP (FS_C1_I1_A0_EP2_FIFO_START | (FS_C1_I1_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A0_EP2_DIRECTION))) #endif #if (FS_C1_I1_A0_EP_NUMBER >= 3) // EP3 #define FS_C1_I1_A0_EP3_FIFO_START (FS_C1_I1_A0_EP2_FIFO_START + FS_C1_I1_A0_EP2_FIFO_NO) #define FS_C1_I1_A0_EP3_FIFO_NO (FS_C1_I1_A0_EP3_BLKNO * FS_C1_I1_A0_EP3_BLKSIZE) #define FS_C1_I1_A0_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I1_A0_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I1_A0_EP3_BLKNO - 1) << 2) | FS_C1_I1_A0_EP3_TYPE) #define FS_C1_I1_A0_EP3_FIFO_MAP (((1 - FS_C1_I1_A0_EP3_DIRECTION) << 4) | EP3) #define FS_C1_I1_A0_EP3_MAP (FS_C1_I1_A0_EP3_FIFO_START | (FS_C1_I1_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A0_EP3_DIRECTION))) #endif #endif #if (FS_C1_I1_ALT_NUMBER >= 2) // AlternateSetting 1 #define FS_C1_I1_A1_EP_LENGTH (EP_LENGTH * FS_C1_I1_A1_EP_NUMBER) #if (FS_C1_I1_A1_EP_NUMBER >= 1) // EP1 #define FS_C1_I1_A1_EP1_FIFO_START FIFO0 #define FS_C1_I1_A1_EP1_FIFO_NO (FS_C1_I1_A1_EP1_BLKNO * FS_C1_I1_A1_EP1_BLKSIZE) #define FS_C1_I1_A1_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I1_A1_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I1_A1_EP1_BLKNO - 1) << 2) | FS_C1_I1_A1_EP1_TYPE) #define FS_C1_I1_A1_EP1_FIFO_MAP (((1 - FS_C1_I1_A1_EP1_DIRECTION) << 4) | EP1) #define FS_C1_I1_A1_EP1_MAP (FS_C1_I1_A1_EP1_FIFO_START | (FS_C1_I1_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A1_EP1_DIRECTION))) #endif #if (FS_C1_I1_A1_EP_NUMBER >= 2) // EP2 #define FS_C1_I1_A1_EP2_FIFO_START (FS_C1_I1_A1_EP1_FIFO_START + FS_C1_I1_A1_EP1_FIFO_NO) #define FS_C1_I1_A1_EP2_FIFO_NO (FS_C1_I1_A1_EP2_BLKNO * FS_C1_I1_A1_EP2_BLKSIZE) #define FS_C1_I1_A1_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I1_A1_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I1_A1_EP2_BLKNO - 1) << 2) | FS_C1_I1_A1_EP2_TYPE) #define FS_C1_I1_A1_EP2_FIFO_MAP (((1 - FS_C1_I1_A1_EP2_DIRECTION) << 4) | EP2) #define FS_C1_I1_A1_EP2_MAP (FS_C1_I1_A1_EP2_FIFO_START | (FS_C1_I1_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A1_EP2_DIRECTION))) #endif #if (FS_C1_I1_A1_EP_NUMBER >= 3) // EP3 #define FS_C1_I1_A1_EP3_FIFO_START (FS_C1_I1_A1_EP2_FIFO_START + FS_C1_I1_A1_EP2_FIFO_NO) #define FS_C1_I1_A1_EP3_FIFO_NO (FS_C1_I1_A1_EP3_BLKNO * FS_C1_I1_A1_EP3_BLKSIZE) #define FS_C1_I1_A1_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I1_A1_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I1_A1_EP3_BLKNO - 1) << 2) | FS_C1_I1_A1_EP3_TYPE) #define FS_C1_I1_A1_EP3_FIFO_MAP (((1 - FS_C1_I1_A1_EP3_DIRECTION) << 4) | EP3) #define FS_C1_I1_A1_EP3_MAP (FS_C1_I1_A1_EP3_FIFO_START | (FS_C1_I1_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A1_EP3_DIRECTION))) #endif #endif #if (FS_C1_I1_ALT_NUMBER == 1) #define FS_C1_I1_ALT_LENGTH (FS_C1_I1_A0_EP_LENGTH) #elif (FS_C1_I1_ALT_NUMBER == 2) #define FS_C1_I1_ALT_LENGTH (FS_C1_I1_A0_EP_LENGTH + FS_C1_I1_A1_EP_LENGTH) #endif #endif #if (FS_C1_INTERFACE_NUMBER == 1) #define FS_C1_INTERFACE_LENGTH (FS_C1_I0_ALT_LENGTH) #elif (FS_C1_INTERFACE_NUMBER == 2) #define FS_C1_INTERFACE_LENGTH (FS_C1_I0_ALT_LENGTH + HS_FS_C1_I1_ALT_LENGTH) #endif #endif /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// #define USB_ENABLE_UP_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT0)) // upstream DMA enable #define USB_DISABLE_UP_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT0))) // upstream DMA disable #define USB_UP_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT3))) // upQ stream mode #define USB_UP_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT3)) // upQ packet mode /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// #define USB_ENABLE_LP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT1)) // lp downstream DMA enable #define USB_DISABLE_LP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT1))) // lp downstream DMA disable #define USB_LP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT6))) // lpQ packet mode #define USB_LP_DN_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT6)) // lpQ stream mode /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// #define USB_ENABLE_HP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT8)) // hp downstream DMA enable #define USB_DISABLE_HP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT8))) // hp downstream DMA disable #define USB_HP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT7))) // hpQ packet mode #define USB_HP_DN_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT7)) // hpQ stream mode /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// #define USB_ENABLE_MP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT9)) // mp downstream DMA enable #define USB_DISABLE_MP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT9))) // mp downstream DMA disable #define USB_MP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT10))) // hpQ packet mode #define USB_MP_DN_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT10)) // hpQ stream mode /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// #define USB_ENABLE_UP_PACKET_MODE() USB_DISABLE_UP_DMA(); \ USB_UP_PACKET_MODE(); \ USB_ENABLE_UP_DMA(); #define USB_ENABLE_LP_DN_PACKET_MODE() USB_DISABLE_LP_DN_DMA(); \ USB_LP_DN_PACKET_MODE(); \ USB_ENABLE_LP_DN_DMA() #define USB_ENABLE_MP_DN_PACKET_MODE() USB_DISABLE_MP_DN_DMA(); \ USB_MP_DN_PACKET_MODE(); \ USB_ENABLE_MP_DN_DMA(); #define USB_ENABLE_HP_DN_PACKET_MODE() USB_DISABLE_HP_DN_DMA(); \ USB_HP_DN_PACKET_MODE(); \ USB_ENABLE_HP_DN_DMA(); /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// #define USB_ENABLE_UP_STREAM_MODE() USB_DISABLE_UP_DMA(); \ USB_UP_STREAM_MODE(); \ USB_ENABLE_UP_DMA(); #define USB_ENABLE_LP_DN_STREAM_MODE() USB_DISABLE_LP_DN_DMA(); \ USB_LP_DN_STREAM_MODE(); \ USB_ENABLE_LP_DN_DMA() #define USB_ENABLE_MP_DN_STREAM_MODE() USB_DISABLE_MP_DN_DMA(); \ USB_MP_DN_STREAM_MODE(); \ USB_ENABLE_MP_DN_DMA(); #define USB_ENABLE_HP_DN_STREAM_MODE() USB_DISABLE_HP_DN_DMA(); \ USB_HP_DN_STREAM_MODE(); \ USB_ENABLE_HP_DN_DMA(); #define USB_STREAM_HOST_BUF_SIZE(size) USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(size))); #define USB_STREAM_TIMEOUT(time_cnt) USB_WORD_REG_WRITE(ZM_SOC_USB_TIME_CTRL_OFFSET, time_cnt); // set stream mode timeout critirea #define USB_STREAM_AGG_PKT_CNT(cnt) USB_WORD_REG_WRITE(ZM_SOC_USB_MAX_AGGREGATE_OFFSET, cnt); // set stream mode packet buffer critirea #endif open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/usb_extr.h000077500000000000000000000051461321570333100324350ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef USB_EXTR_H #define USB_EXTR_H #if 0 #include "dt_defs.h" #include "usb_type.h" /* Variable for USB EP0 pipe (USB.c) */ uint16_t *pu8DescriptorEX; uint16_t u16TxRxCounter; uint16_t *u8ConfigDescriptorEX; //extern BOOLEAN bUsbEP0HaltSt; Action eUsbCxFinishAction; CommandType eUsbCxCommand; BOOLEAN UsbChirpFinish; uint16_t u8UsbConfigValue; uint16_t u8UsbInterfaceValue; uint16_t u8UsbInterfaceAlternateSetting; uint16_t u16FirmwareComplete; uint16_t *UsbDeviceDescriptor; uint16_t *String00Descriptor; uint16_t *String10Descriptor; uint16_t *String20Descriptor; uint16_t *String30Descriptor; uint16_t *u8DeviceQualifierDescriptorEX; uint16_t *u8OtherSpeedConfigDescriptorEX; uint16_t *u8UsbDeviceDescriptor; uint16_t *u8String00Descriptor; uint16_t *u8String10Descriptor; uint16_t *u8String20Descriptor; uint16_t *u8String30Descriptor; #endif #endif open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/usb_pre.h000077500000000000000000000103611321570333100322340ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __USB_USER_PRE_H #define __USB_USER_PRE_H #define FUSB200_MAX_EP 10 // 1..10 #define FUSB200_MAX_FIFO 10 // 0.. 9 #define EP0MAXPACKETSIZE 0x40 // #define EP0FIFOSIZE 64 // EP0_FIFO //JWEI 2003/04/29 //#define EP0MAXPACKETSIZE 0x08 // Max. Packet Size define #define MX_PA_SZ_8 8 #define MX_PA_SZ_16 16 #define MX_PA_SZ_32 32 #define MX_PA_SZ_64 64 #define MX_PA_SZ_128 128 #define MX_PA_SZ_256 256 #define MX_PA_SZ_512 512 #define MX_PA_SZ_1024 1024 #define MASK_F0 0xF0 // Block Size define #define BLK512BYTE 1 #define BLK1024BYTE 2 #define BLK64BYTE 1 #define BLK128BYTE 2 // Block toggle number define #define SINGLE_BLK 1 #define DOUBLE_BLK 2 #define TRIBLE_BLK 3 // Endpoint transfer type #define TF_TYPE_ISOCHRONOUS 1 #define TF_TYPE_BULK 2 #define TF_TYPE_INTERRUPT 3 // Endpoint or FIFO direction define #define DIRECTION_IN 0 #define DIRECTION_OUT 1 // FIFO number define #define FIFO0 0x0 #define FIFO1 0x1 #define FIFO2 0x2 #define FIFO3 0x3 #define FIFO4 0x4 #define FIFO5 0x5 #define FIFO6 0x6 #define FIFO7 0x7 #define FIFO8 0x8 #define FIFO9 0x9 #define FIFO10 10 #define FIFO11 11 #define FIFO12 12 #define FIFO13 13 #define FIFO14 14 #define FIFO15 15 // Descriptor Table uses the following parameters : fixed #define DEVICE_LENGTH 0x12 #define CONFIG_LENGTH 0x09 #define INTERFACE_LENGTH 0x09 #define EP_LENGTH 0x07 #define DEVICE_QUALIFIER_LENGTH 0x0A //JWEI 2003/04/29 // Endpoint number define #define EP0 0 #define EP1 1 #define EP2 2 #define EP3 3 #define EP4 4 #define EP5 5 #define EP6 6 #define EP7 7 #define EP8 8 #define EP9 9 #define EP10 10 #define EP11 11 #define EP12 12 #define EP13 13 #define EP14 14 #define EP15 15 #define STRING_00_LENGTH 0x04 #define STRING_10_LENGTH 0x0c #define STRING_20_LENGTH 0x18 #define STRING_30_LENGTH 0x18 #define STRING_40_LENGTH 0x04 #define STRING_50_LENGTH 0x04 #define STRING_60_LENGTH 0x04 #define STRING_70_LENGTH 0x04 #define STRING_80_LENGTH 0x04 #define STRING_90_LENGTH 0x00 #endif open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/usb_std.h000077500000000000000000000123301321570333100322360ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef USB_STD_H #define USB_STD_H #define mDEV_REQ_REQ_DIR() (ControlCmd.Direction) #define mDEV_REQ_REQ_TYPE() (ControlCmd.Type) #define mDEV_REQ_REQ_RECI() (ControlCmd.Object) #define mDEV_REQ_REQ() (ControlCmd.Request) #define mDEV_REQ_VALUE() (ControlCmd.Value) #define mDEV_REQ_VALUE_LOW() (mLOW_BYTE(mDEV_REQ_VALUE())) #define mDEV_REQ_VALUE_HIGH() (mHIGH_BYTE(mDEV_REQ_VALUE())) #define mDEV_REQ_INDEX() (ControlCmd.Index) #define mDEV_REQ_LENGTH() (ControlCmd.Length) /******************** USB Protocol Definition *************************/ /* Standard Request Code (Table 9-4) */ #define USB_GET_STATUS 0 #define USB_CLEAR_FEATURE 1 #define USB_SET_FEATURE 3 #define USB_SET_ADDRESS 5 #define USB_GET_DESCRIPTOR 6 #define USB_SET_DESCRIPTOR 7 #define USB_GET_CONFIGURATION 8 #define USB_SET_CONFIGURATION 9 #define USB_GET_INTERFACE 10 #define USB_SET_INTERFACE 11 #define USB_SYNCH_FRAME 12 /* Descriptor Type (Table 9-5) */ #define USB_DESC_TYPE_DEVICE 1 #define USB_DESC_TYPE_CONFIG 2 #define USB_DESC_TYPE_STRING 3 #define USB_DESC_TYPE_INTERFACE 4 #define USB_DESC_TYPE_ENDPOINT 5 /* Endpoint Attribute (Table 9-10) */ #define USB_EP_ATTR_CTRL 0 #define USB_EP_ATTR_ISOCH 1 #define USB_EP_ATTR_BULK 2 #define USB_EP_ATTR_INTRPT 3 /*********************** for USB 2.0 **********************************/ // Table 9-5. Descriptor Types #define DT_DEVICE 1 #define DT_CONFIGURATION 2 #define DT_STRING 3 #define DT_INTERFACE 4 #define DT_ENDPOINT 5 #define DT_DEVICE_QUALIFIER 6 #define DT_OTHER_SPEED_CONFIGURATION 7 #define DT_INTERFACE_POWER 8 /**********************************************************************/ // Values for bmAttributes Field in USB_CONFIGURATION_DESCRIPTOR #define USB_BUS_POWERED 0x80 #define USB_SELF_POWERED 0x40 #define USB_REMOTE_WAKEUP 0x20 #define cUSB_REQTYPE_DIR_POS 7 #define cUSB_REQTYPE_DIR_LEN 1 #define cUSB_REQTYPE_TYPE_POS 5 #define cUSB_REQTYPE_TYPE_LEN 2 #define cUSB_REQTYPE_RX_POS 0 #define cUSB_REQTYPE_RX_LEN 5 /* for USB State */ #define cUSB_DEFAULT_STATE 0 #define cUSB_ADDRESS_STATE 1 #define cUSB_CONFIG_STATE 2 /* for Data transfer direction */ #define bmUSB_HOST_DIR 7 /* Bit 7 */ #define cUSB_DIR_HOST_OUT 0 #define cUSB_DIR_HOST_IN 1 /* for Type */ #define cUSB_REQTYPE_STD 0 #define cUSB_REQTYPE_CLASS 1 #define cUSB_REQTYPE_VENDOR 2 /* for Recipient */ #define cUSB_REQTYPE_DEVICE 0 #define cUSB_REQTYPE_INTERFACE 1 #define cUSB_REQTYPE_ENDPOINT 2 #define cUSB_REQTYPE_OTHER 3 /* for Descriptor Type */ #define cUSB_DESTYPE_DEVICE 1 #define cUSB_DESTYPE_CONFIG 2 #define cUSB_DESTYPE_STRING 3 #define cUSB_DESTYPE_INTERFACE 4 #define cUSB_DESTYPE_ENDPOINT 5 #define cUSB_DESTYPE_END cUSB_DESTYPE_ENDPOINT // for range check /* for Feature selector */ #define cUSB_FEATSEL_RMWAKEUP 0 #define cUSB_FEATSEL_EPHAL 1 #define cUSB_FEATSEL_END cUSB_FEATSEL_EPHAL // for range check #define bmREQ_RECI 0 #define bmwREQ_RECI 5 // mMASKS(bmwREQ_RECI, bmREQ_RECI) #define bmREQ_TYPE 5 #define bmwREQ_TYPE 2 // mMASKS(bmwREQ_TYPE, bmREQ_TYPE) #define bmREQ_DIR 7 #define bmwREQ_DIR 1 #endif open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/usb_table.h000077500000000000000000000166741321570333100325520ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _USB_TABLE_H_ #define _USB_TABLE_H_ #include "sys_cfg.h" // UsbDeviceDescriptor #define USB_DEVICE_DESC_TYPE 0x01 #define USB_DEVICE_DESC_LEN 0x12 #define USB_SPEC_VERSION 0x0200 #define USB_DEVICE_CLASS 0xFF #define USB_DEVICE_SUB_CLASS 0xFF #define USB_DEVICE_PROTOCOL 0xFF #define USB_MAX_PKT_SIZE 0x40 #define USB_VENDOR_ID 0x0CF3 #define USB_PRODUCT_ID 0x9271 #if 1 /* USB Device Descriptor : byte 12, 13 Device BCD -> Device release number in binary-coded decimal. */ #define USB_DEVICE_BCD BOOTROM_VER #else #define USB_DEVICE_BCD 0x0106 #endif #define USB_MANUFACTURER_INDEX 0x10 #define USB_PRODUCT_INDEX 0x20 #define USB_SERIAL_INDEX 0x30 #define USB_CONFIGURATION_NUM 0x01 // end UsbDeviceDescriptor #define USB_CONFIG_DESC_TYPE 0x02 #define USB_CONFIG_DESC_LEN 0x09 //#define USB_TOTAL_DESC_LEN 0x002E // 4 ep //#define USB_TOTAL_DESC_LEN 0x0035 // 5 ep #define USB_TOTAL_DESC_LEN 0x003C // 6 ep #define USB_INTERFACE_NUM 0x01 #define USB_CONFIG_NUM 0x01 #define USB_STRING_INDEX 0x00 #define USB_ATTRIBUTE 0x80 #define USB_MAX_POWER 0xFA #define USB_INTERFACE_DESC_TYPE 0x04 #define USB_INTERFACE_DESC_LEN 0x09 #define USB_INTERFACE_INDEX_NUM 0x00 #define USB_INTERFACE_ALT_SETTING 0x00 //#define USB_INTERFACE_EP_NUM 0x04 //#define USB_INTERFACE_EP_NUM 0x05 #define USB_INTERFACE_EP_NUM 0x06 #define USB_INTERFACE_CLASS 0xFF #define USB_INTERFACE_SUB_CLASS 0x00 #define USB_INTERFACE_PROTOCOL 0x00 #define USB_INTERFACE_STRING_INDEX 0x00 #define USB_EP_DESC_TYPE 0x05 #define USB_EP_DESC_LEN 0x07 /* USB Endpoint attribute */ #define bUSB_EP1_NUM 0x01 #define bUSB_EP2_NUM 0x02 #define bUSB_EP3_NUM 0x03 #define bUSB_EP4_NUM 0x04 #define bUSB_EP5_NUM 0x05 #define bUSB_EP6_NUM 0x06 #define bUSB_EP_DIRECTION_IN 0x80 #define bUSB_EP_DIRECTION_OUT 0x00 #define bUSB_EP_TYPE_CONTROL 0x00 #define bUSB_EP_TYPE_ISOCHRONOUS 0x01 #define bUSB_EP_TYPE_BULK 0x02 #define bUSB_EP_TYPE_INTERRUPT 0x03 #define bUSB_EP_MAX_PKT_SIZE_64 0x0040 #define bUSB_EP_MAX_PKT_SIZE_512 0x0200 /* High Speed Endpoint */ #define USB_HS_EP1_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP1_NUM) #define USB_HS_EP1_ATTRIBUTE bUSB_EP_TYPE_BULK #define USB_HS_EP1_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_512 #define USB_HS_EP1_INTERVAL 0x00 #define USB_HS_EP2_ADDRESS (bUSB_EP_DIRECTION_IN | bUSB_EP2_NUM) #define USB_HS_EP2_ATTRIBUTE bUSB_EP_TYPE_BULK #define USB_HS_EP2_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_512 #define USB_HS_EP2_INTERVAL 0x00 #define USB_HS_EP3_ADDRESS (bUSB_EP_DIRECTION_IN | bUSB_EP3_NUM) #define USB_HS_EP3_ATTRIBUTE bUSB_EP_TYPE_INTERRUPT #define USB_HS_EP3_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 #define USB_HS_EP3_INTERVAL 0x01 #define USB_HS_EP4_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP4_NUM) #define USB_HS_EP4_ATTRIBUTE bUSB_EP_TYPE_INTERRUPT //bUSB_EP_TYPE_BULK #define USB_HS_EP4_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 #define USB_HS_EP4_INTERVAL 0x01 //0x00 #define USB_HS_EP5_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP5_NUM) #define USB_HS_EP5_ATTRIBUTE bUSB_EP_TYPE_BULK #define USB_HS_EP5_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_512 #define USB_HS_EP5_INTERVAL 0x00 #define USB_HS_EP6_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP6_NUM) #define USB_HS_EP6_ATTRIBUTE bUSB_EP_TYPE_BULK #define USB_HS_EP6_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_512 #define USB_HS_EP6_INTERVAL 0x00 /* Full Speed Endpoint */ #define USB_FS_EP1_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP1_NUM) #define USB_FS_EP1_ATTRIBUTE bUSB_EP_TYPE_BULK #define USB_FS_EP1_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 #define USB_FS_EP1_INTERVAL 0x00 #define USB_FS_EP2_ADDRESS (bUSB_EP_DIRECTION_IN | bUSB_EP2_NUM) #define USB_FS_EP2_ATTRIBUTE bUSB_EP_TYPE_BULK #define USB_FS_EP2_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 #define USB_FS_EP2_INTERVAL 0x00 #define USB_FS_EP3_ADDRESS (bUSB_EP_DIRECTION_IN | bUSB_EP3_NUM) #define USB_FS_EP3_ATTRIBUTE bUSB_EP_TYPE_INTERRUPT #define USB_FS_EP3_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 #define USB_FS_EP3_INTERVAL 0x01 #define USB_FS_EP4_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP4_NUM) #define USB_FS_EP4_ATTRIBUTE bUSB_EP_TYPE_BULK #define USB_FS_EP4_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 #define USB_FS_EP4_INTERVAL 0x00 #define USB_FS_EP5_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP5_NUM) #define USB_FS_EP5_ATTRIBUTE bUSB_EP_TYPE_BULK #define USB_FS_EP5_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 #define USB_FS_EP5_INTERVAL 0x00 #define USB_FS_EP6_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP6_NUM) #define USB_FS_EP6_ATTRIBUTE bUSB_EP_TYPE_BULK #define USB_FS_EP6_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 #define USB_FS_EP6_INTERVAL 0x00 //#define USB_QUALIFIER_DESC_ADDR 0x8cff00 //#define USB_OTHER_SPEED_DESC_ADDR 0x8cffA #endif // end of _USB_TABLE_H_ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/usb_type.h000077500000000000000000000066441321570333100324400ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef USB_TYPE_H #define USB_TYPE_H #include "dt_defs.h" /*********************** for Faraday USB controller *******************/ typedef enum { CMD_VOID, // No command CMD_GET_DESCRIPTOR, // Get_Descriptor command CMD_SET_DESCRIPTOR // Set_Descriptor command } CommandType; typedef enum { ACT_IDLE, ACT_DONE, ACT_STALL } Action; typedef struct Setup_Packet { uint8_t Direction; /* Data transfer direction: IN, OUT */ uint8_t Type; /* Request Type: Standard, Class, Vendor */ uint8_t Object; /* Recipient: Device, Interface, Endpoint,other */ uint16_t Request; /* Refer to Table 9-3 */ uint16_t Value; uint16_t Index; uint16_t Length; } SetupPacket; #define mBIT(b) (1 << (b)) #define mMASK(w) (mBIT(w) - 1) #define mWORD_IDX(bsize) ((bsize) >> 1) #define mWORD_SIZE(bsize) (((bsize) + 1) >> 1) #define mTABLE_WID mWORD_SIZE #define mTABLE_IDX mWORD_IDX #define mTABLE_LEN mLOW_BYTE #define mLOW_MASK(u16) ((uint8_t) ((u16) & mMASK(8))) #define mHIGH_MASK(u16) ((uint8_t) ((u16) & ~mMASK(8))) #define mLOW2HIGH(u16) (((uint8_t) (u16)) << 8) /* (1234) -> 0034 */ //#define mLOW_BYTE(u16) ((U_8)(u16)) #define mLOW_BYTE(u16) mLOW_MASK(u16) /* (1234) -> 0012 */ #define mHIGH_BYTE(u16) ((uint8_t) (((uint16_t) (u16)) >> 8)) #define mGET_REG1(var0, reg0) { var0 = reg0; } /* (1234, 5678) -> 7834 */ #define m2BYTE(ch1L, ch2H) (mLOW_MASK(ch1L) | mLOW2HIGH(ch2H)) #define mREAD_WORD(var0, reg0, reg1) \ { var0 = reg0; var0 += mLOW2HIGH(reg1); } #endif usbfifo_api.h000077500000000000000000000053241321570333100330070ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * @File: HIF_api.h * * @Abstract: Host Interface api * * @Notes: */ #ifndef _USB_FIFO_API_H #define _USB_FIFO_API_H #include "vbuf_api.h" typedef struct _USB_FIFO_CONFIG { /* callback to get the buf for receiving commands from USB FIFO */ VBUF* (*get_command_buf)(void); /* callback when receiving a command */ void (*recv_command)(VBUF *cmd); /* callback to get the buf for event to send to the host */ VBUF* (*get_event_buf)(void); /* callback to indicate the event has been sent to the host */ void (*send_event_done)(VBUF *buf); /* context used for all callbacks */ //void *context; } USB_FIFO_CONFIG; /* hardware API table structure (API descriptions below) */ struct usbfifo_api { void (*_init)(USB_FIFO_CONFIG *pConfig); void (*_enable_event_isr)(void); /* room to expand this table by another table */ void *pReserved; }; extern void usbfifo_module_install(struct usbfifo_api *apis); #endif /* #ifndef _USB_FIFO_API_H */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/vbuf_api.h000077500000000000000000000050431321570333100323710ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * @File: VBUF_api.h * * @Abstract: Host Interface api * * @Notes: */ #ifndef _VBUF_API_H #define _VBUF_API_H #include #define MAX_BUF_CTX_LEN 20 typedef struct _VBUF { VDESC *desc_list; struct _VBUF *next_buf; A_UINT16 buf_length; A_UINT8 reserved[2]; A_UINT8 ctx[MAX_BUF_CTX_LEN]; } VBUF; #define VBUF_GET_DATA_ADDR(vbuf) (vbuf->desc_list->buf_addr + vbuf->desc_list->data_offset) /* hardware API table structure (API descriptions below) */ struct vbuf_api { void (*_init)(int nBuf); VBUF* (*_alloc_vbuf)(void); VBUF* (*_alloc_vbuf_with_size)(int size, int reserve); void (*_free_vbuf)(VBUF *buf); /* room to expand this table by another table */ void *pReserved; }; extern void vbuf_module_install(struct vbuf_api *apis); #endif /* #ifndef _HIF_API_H */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/vdesc_api.h000077500000000000000000000047661321570333100325460ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * @File: VBUF_api.h * * @Abstract: Host Interface api * * @Notes: */ #ifndef _VDESC_API_H #define _VDESC_API_H #define MAX_HW_DESC_SIZE 20 typedef struct _VDESC { struct _VDESC *next_desc; A_UINT8 *buf_addr; A_UINT16 buf_size; A_UINT16 data_offset; A_UINT16 data_size; A_UINT16 control; A_UINT8 hw_desc_buf[MAX_HW_DESC_SIZE]; } VDESC; #define VDESC_HW_TO_VDESC(hwdesc) ((VDESC *)(((A_UINT32 *)hwdesc - 4))) struct vdesc_api { void (*_init)(int nDesc); VDESC* (*_alloc_vdesc)(); A_UINT8* (*_get_hw_desc)(VDESC *desc); void (*_swap_vdesc)(VDESC *dest, VDESC *src); /* room to expand this table by another table */ void *pReserved; }; extern void vdesc_module_install(struct vdesc_api *apis); #endif open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/wdt_api.h000077500000000000000000000050721321570333100322270ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __WDT_API_H__ #define __WDT_API_H__ typedef enum { WDT_ACTION_NO = 0, // bit1, bit0: 00 WDT_ACTION_INTR, // bit1, bit0: 01 WDT_ACTION_NMI, // bit1, bit0: 10 WDT_ACTION_RESET, // bit1, bit0: 11 WDT_ACTION_UNKNOWN } T_WDT_ACTION_TYPE; typedef enum { WDT_TIMEOUT = 1, WDT_ACTION, WDT_UNKNOWN } T_WDT_CMD_TYPE; typedef struct { uint32_t cmd; union { uint32_t timeout; uint32_t action; }; }T_WDT_CMD; typedef enum { ENUM_WDT_BOOT = 1, ENUM_COLD_BOOT, ENUM_SUSP_BOOT, // add above here ENUM_UNKNOWN_BOOT } T_BOOT_TYPE; /*!- interface of watchdog timer * */ struct wdt_api { void (* _wdt_init)(void); void (* _wdt_enable)(void); void (* _wdt_disable)(void); void (* _wdt_set)(T_WDT_CMD); void (* _wdt_task)(void); void (* _wdt_reset)(void); T_BOOT_TYPE (*_wdt_last_boot)(void); }; #endif /* __WDT_API_H__ */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/xtensa-elf/000077500000000000000000000000001321570333100324665ustar00rootroot00000000000000xtensa/000077500000000000000000000000001321570333100337115ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/xtensa-elfconfig/000077500000000000000000000000001321570333100351565ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/xtensa-elf/xtensacore.h000066400000000000000000001325761321570333100362750ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/xtensa-elf/xtensa/config/* * Copyright (c) 2013 Tensilica Inc. * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sublicense, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /* * xtensa/config/core.h -- HAL definitions dependent on CORE configuration * * This header file is sometimes referred to as the "compile-time HAL" or CHAL. * It pulls definitions tailored for a specific Xtensa processor configuration. * * Sources for binaries meant to be configuration-independent generally avoid * including this file (they may use the configuration-specific HAL library). * It is normal for the HAL library source itself to include this file. */ #ifndef XTENSA_CONFIG_CORE_H #define XTENSA_CONFIG_CORE_H /* CONFIGURATION INDEPENDENT DEFINITIONS: */ #ifdef __XTENSA__ #include #else #include "../hal.h" #endif /* CONFIGURATION SPECIFIC DEFINITIONS: */ #ifdef __XTENSA__ #include #include #include #else #include "core-isa.h" #include "core-matmap.h" #include "tie.h" #endif #if defined (_ASMLANGUAGE) || defined (__ASSEMBLER__) #ifdef __XTENSA__ #include #else #include "tie-asm.h" #endif #endif /*_ASMLANGUAGE or __ASSEMBLER__*/ /*---------------------------------------------------------------------- GENERAL ----------------------------------------------------------------------*/ /* * Separators for macros that expand into arrays. * These can be predefined by files that #include this one, * when different separators are required. */ /* Element separator for macros that expand into 1-dimensional arrays: */ #ifndef XCHAL_SEP #define XCHAL_SEP , #endif /* Array separator for macros that expand into 2-dimensional arrays: */ #ifndef XCHAL_SEP2 #define XCHAL_SEP2 },{ #endif /*---------------------------------------------------------------------- ISA ----------------------------------------------------------------------*/ #if XCHAL_HAVE_BE # define XCHAL_HAVE_LE 0 # define XCHAL_MEMORY_ORDER XTHAL_BIGENDIAN #else # define XCHAL_HAVE_LE 1 # define XCHAL_MEMORY_ORDER XTHAL_LITTLEENDIAN #endif /*---------------------------------------------------------------------- INTERRUPTS ----------------------------------------------------------------------*/ /* Indexing macros: */ #define _XCHAL_INTLEVEL_MASK(n) XCHAL_INTLEVEL ## n ## _MASK #define XCHAL_INTLEVEL_MASK(n) _XCHAL_INTLEVEL_MASK(n) /* n = 0 .. 15 */ #define _XCHAL_INTLEVEL_ANDBELOWMASK(n) XCHAL_INTLEVEL ## n ## _ANDBELOW_MASK #define XCHAL_INTLEVEL_ANDBELOW_MASK(n) _XCHAL_INTLEVEL_ANDBELOWMASK(n) /* n = 0 .. 15 */ #define _XCHAL_INTLEVEL_NUM(n) XCHAL_INTLEVEL ## n ## _NUM #define XCHAL_INTLEVEL_NUM(n) _XCHAL_INTLEVEL_NUM(n) /* n = 0 .. 15 */ #define _XCHAL_INT_LEVEL(n) XCHAL_INT ## n ## _LEVEL #define XCHAL_INT_LEVEL(n) _XCHAL_INT_LEVEL(n) /* n = 0 .. 31 */ #define _XCHAL_INT_TYPE(n) XCHAL_INT ## n ## _TYPE #define XCHAL_INT_TYPE(n) _XCHAL_INT_TYPE(n) /* n = 0 .. 31 */ #define _XCHAL_TIMER_INTERRUPT(n) XCHAL_TIMER ## n ## _INTERRUPT #define XCHAL_TIMER_INTERRUPT(n) _XCHAL_TIMER_INTERRUPT(n) /* n = 0 .. 3 */ #define XCHAL_HAVE_HIGHLEVEL_INTERRUPTS XCHAL_HAVE_HIGHPRI_INTERRUPTS #define XCHAL_NUM_LOWPRI_LEVELS 1 /* number of low-priority interrupt levels (always 1) */ #define XCHAL_FIRST_HIGHPRI_LEVEL (XCHAL_NUM_LOWPRI_LEVELS+1) /* level of first high-priority interrupt (always 2) */ /* Note: 1 <= LOWPRI_LEVELS <= EXCM_LEVEL < DEBUGLEVEL <= NUM_INTLEVELS < NMILEVEL <= 15 */ /* These values are constant for existing Xtensa processor implementations: */ #define XCHAL_INTLEVEL0_MASK 0x00000000 #define XCHAL_INTLEVEL8_MASK 0x00000000 #define XCHAL_INTLEVEL9_MASK 0x00000000 #define XCHAL_INTLEVEL10_MASK 0x00000000 #define XCHAL_INTLEVEL11_MASK 0x00000000 #define XCHAL_INTLEVEL12_MASK 0x00000000 #define XCHAL_INTLEVEL13_MASK 0x00000000 #define XCHAL_INTLEVEL14_MASK 0x00000000 #define XCHAL_INTLEVEL15_MASK 0x00000000 /* Array of masks of interrupts at each interrupt level: */ #define XCHAL_INTLEVEL_MASKS XCHAL_INTLEVEL0_MASK \ XCHAL_SEP XCHAL_INTLEVEL1_MASK \ XCHAL_SEP XCHAL_INTLEVEL2_MASK \ XCHAL_SEP XCHAL_INTLEVEL3_MASK \ XCHAL_SEP XCHAL_INTLEVEL4_MASK \ XCHAL_SEP XCHAL_INTLEVEL5_MASK \ XCHAL_SEP XCHAL_INTLEVEL6_MASK \ XCHAL_SEP XCHAL_INTLEVEL7_MASK \ XCHAL_SEP XCHAL_INTLEVEL8_MASK \ XCHAL_SEP XCHAL_INTLEVEL9_MASK \ XCHAL_SEP XCHAL_INTLEVEL10_MASK \ XCHAL_SEP XCHAL_INTLEVEL11_MASK \ XCHAL_SEP XCHAL_INTLEVEL12_MASK \ XCHAL_SEP XCHAL_INTLEVEL13_MASK \ XCHAL_SEP XCHAL_INTLEVEL14_MASK \ XCHAL_SEP XCHAL_INTLEVEL15_MASK /* These values are constant for existing Xtensa processor implementations: */ #define XCHAL_INTLEVEL0_ANDBELOW_MASK 0x00000000 #define XCHAL_INTLEVEL8_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK #define XCHAL_INTLEVEL9_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK #define XCHAL_INTLEVEL10_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK #define XCHAL_INTLEVEL11_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK #define XCHAL_INTLEVEL12_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK #define XCHAL_INTLEVEL13_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK #define XCHAL_INTLEVEL14_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK #define XCHAL_INTLEVEL15_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK /* Mask of all low-priority interrupts: */ #define XCHAL_LOWPRI_MASK XCHAL_INTLEVEL1_ANDBELOW_MASK /* Mask of all interrupts masked by PS.EXCM (or CEXCM): */ #define XCHAL_EXCM_MASK XCHAL_INTLEVEL_ANDBELOW_MASK(XCHAL_EXCM_LEVEL) /* Array of masks of interrupts at each range 1..n of interrupt levels: */ #define XCHAL_INTLEVEL_ANDBELOW_MASKS XCHAL_INTLEVEL0_ANDBELOW_MASK \ XCHAL_SEP XCHAL_INTLEVEL1_ANDBELOW_MASK \ XCHAL_SEP XCHAL_INTLEVEL2_ANDBELOW_MASK \ XCHAL_SEP XCHAL_INTLEVEL3_ANDBELOW_MASK \ XCHAL_SEP XCHAL_INTLEVEL4_ANDBELOW_MASK \ XCHAL_SEP XCHAL_INTLEVEL5_ANDBELOW_MASK \ XCHAL_SEP XCHAL_INTLEVEL6_ANDBELOW_MASK \ XCHAL_SEP XCHAL_INTLEVEL7_ANDBELOW_MASK \ XCHAL_SEP XCHAL_INTLEVEL8_ANDBELOW_MASK \ XCHAL_SEP XCHAL_INTLEVEL9_ANDBELOW_MASK \ XCHAL_SEP XCHAL_INTLEVEL10_ANDBELOW_MASK \ XCHAL_SEP XCHAL_INTLEVEL11_ANDBELOW_MASK \ XCHAL_SEP XCHAL_INTLEVEL12_ANDBELOW_MASK \ XCHAL_SEP XCHAL_INTLEVEL13_ANDBELOW_MASK \ XCHAL_SEP XCHAL_INTLEVEL14_ANDBELOW_MASK \ XCHAL_SEP XCHAL_INTLEVEL15_ANDBELOW_MASK #if 0 /*XCHAL_HAVE_NMI*/ /* NMI "interrupt level" (for use with EXCSAVE_n, EPS_n, EPC_n, RFI n): */ # define XCHAL_NMILEVEL (XCHAL_NUM_INTLEVELS+1) #endif /* Array of levels of each possible interrupt: */ #define XCHAL_INT_LEVELS XCHAL_INT0_LEVEL \ XCHAL_SEP XCHAL_INT1_LEVEL \ XCHAL_SEP XCHAL_INT2_LEVEL \ XCHAL_SEP XCHAL_INT3_LEVEL \ XCHAL_SEP XCHAL_INT4_LEVEL \ XCHAL_SEP XCHAL_INT5_LEVEL \ XCHAL_SEP XCHAL_INT6_LEVEL \ XCHAL_SEP XCHAL_INT7_LEVEL \ XCHAL_SEP XCHAL_INT8_LEVEL \ XCHAL_SEP XCHAL_INT9_LEVEL \ XCHAL_SEP XCHAL_INT10_LEVEL \ XCHAL_SEP XCHAL_INT11_LEVEL \ XCHAL_SEP XCHAL_INT12_LEVEL \ XCHAL_SEP XCHAL_INT13_LEVEL \ XCHAL_SEP XCHAL_INT14_LEVEL \ XCHAL_SEP XCHAL_INT15_LEVEL \ XCHAL_SEP XCHAL_INT16_LEVEL \ XCHAL_SEP XCHAL_INT17_LEVEL \ XCHAL_SEP XCHAL_INT18_LEVEL \ XCHAL_SEP XCHAL_INT19_LEVEL \ XCHAL_SEP XCHAL_INT20_LEVEL \ XCHAL_SEP XCHAL_INT21_LEVEL \ XCHAL_SEP XCHAL_INT22_LEVEL \ XCHAL_SEP XCHAL_INT23_LEVEL \ XCHAL_SEP XCHAL_INT24_LEVEL \ XCHAL_SEP XCHAL_INT25_LEVEL \ XCHAL_SEP XCHAL_INT26_LEVEL \ XCHAL_SEP XCHAL_INT27_LEVEL \ XCHAL_SEP XCHAL_INT28_LEVEL \ XCHAL_SEP XCHAL_INT29_LEVEL \ XCHAL_SEP XCHAL_INT30_LEVEL \ XCHAL_SEP XCHAL_INT31_LEVEL /* Array of types of each possible interrupt: */ #define XCHAL_INT_TYPES XCHAL_INT0_TYPE \ XCHAL_SEP XCHAL_INT1_TYPE \ XCHAL_SEP XCHAL_INT2_TYPE \ XCHAL_SEP XCHAL_INT3_TYPE \ XCHAL_SEP XCHAL_INT4_TYPE \ XCHAL_SEP XCHAL_INT5_TYPE \ XCHAL_SEP XCHAL_INT6_TYPE \ XCHAL_SEP XCHAL_INT7_TYPE \ XCHAL_SEP XCHAL_INT8_TYPE \ XCHAL_SEP XCHAL_INT9_TYPE \ XCHAL_SEP XCHAL_INT10_TYPE \ XCHAL_SEP XCHAL_INT11_TYPE \ XCHAL_SEP XCHAL_INT12_TYPE \ XCHAL_SEP XCHAL_INT13_TYPE \ XCHAL_SEP XCHAL_INT14_TYPE \ XCHAL_SEP XCHAL_INT15_TYPE \ XCHAL_SEP XCHAL_INT16_TYPE \ XCHAL_SEP XCHAL_INT17_TYPE \ XCHAL_SEP XCHAL_INT18_TYPE \ XCHAL_SEP XCHAL_INT19_TYPE \ XCHAL_SEP XCHAL_INT20_TYPE \ XCHAL_SEP XCHAL_INT21_TYPE \ XCHAL_SEP XCHAL_INT22_TYPE \ XCHAL_SEP XCHAL_INT23_TYPE \ XCHAL_SEP XCHAL_INT24_TYPE \ XCHAL_SEP XCHAL_INT25_TYPE \ XCHAL_SEP XCHAL_INT26_TYPE \ XCHAL_SEP XCHAL_INT27_TYPE \ XCHAL_SEP XCHAL_INT28_TYPE \ XCHAL_SEP XCHAL_INT29_TYPE \ XCHAL_SEP XCHAL_INT30_TYPE \ XCHAL_SEP XCHAL_INT31_TYPE /* Array of masks of interrupts for each type of interrupt: */ #define XCHAL_INTTYPE_MASKS XCHAL_INTTYPE_MASK_UNCONFIGURED \ XCHAL_SEP XCHAL_INTTYPE_MASK_SOFTWARE \ XCHAL_SEP XCHAL_INTTYPE_MASK_EXTERN_EDGE \ XCHAL_SEP XCHAL_INTTYPE_MASK_EXTERN_LEVEL \ XCHAL_SEP XCHAL_INTTYPE_MASK_TIMER \ XCHAL_SEP XCHAL_INTTYPE_MASK_NMI \ XCHAL_SEP XCHAL_INTTYPE_MASK_WRITE_ERROR /* Interrupts that can be cleared using the INTCLEAR special register: */ #define XCHAL_INTCLEARABLE_MASK (XCHAL_INTTYPE_MASK_SOFTWARE+XCHAL_INTTYPE_MASK_EXTERN_EDGE+XCHAL_INTTYPE_MASK_WRITE_ERROR) /* Interrupts that can be triggered using the INTSET special register: */ #define XCHAL_INTSETTABLE_MASK XCHAL_INTTYPE_MASK_SOFTWARE /* Array of interrupts assigned to each timer (CCOMPARE0 to CCOMPARE3): */ #define XCHAL_TIMER_INTERRUPTS XCHAL_TIMER0_INTERRUPT \ XCHAL_SEP XCHAL_TIMER1_INTERRUPT \ XCHAL_SEP XCHAL_TIMER2_INTERRUPT \ XCHAL_SEP XCHAL_TIMER3_INTERRUPT /* For backward compatibility and for the array macros, define macros for * each unconfigured interrupt number (unfortunately, the value of * XTHAL_INTTYPE_UNCONFIGURED is not zero): */ #if XCHAL_NUM_INTERRUPTS == 0 # define XCHAL_INT0_LEVEL 0 # define XCHAL_INT0_TYPE XTHAL_INTTYPE_UNCONFIGURED #endif #if XCHAL_NUM_INTERRUPTS <= 1 # define XCHAL_INT1_LEVEL 0 # define XCHAL_INT1_TYPE XTHAL_INTTYPE_UNCONFIGURED #endif #if XCHAL_NUM_INTERRUPTS <= 2 # define XCHAL_INT2_LEVEL 0 # define XCHAL_INT2_TYPE XTHAL_INTTYPE_UNCONFIGURED #endif #if XCHAL_NUM_INTERRUPTS <= 3 # define XCHAL_INT3_LEVEL 0 # define XCHAL_INT3_TYPE XTHAL_INTTYPE_UNCONFIGURED #endif #if XCHAL_NUM_INTERRUPTS <= 4 # define XCHAL_INT4_LEVEL 0 # define XCHAL_INT4_TYPE XTHAL_INTTYPE_UNCONFIGURED #endif #if XCHAL_NUM_INTERRUPTS <= 5 # define XCHAL_INT5_LEVEL 0 # define XCHAL_INT5_TYPE XTHAL_INTTYPE_UNCONFIGURED #endif #if XCHAL_NUM_INTERRUPTS <= 6 # define XCHAL_INT6_LEVEL 0 # define XCHAL_INT6_TYPE XTHAL_INTTYPE_UNCONFIGURED #endif #if XCHAL_NUM_INTERRUPTS <= 7 # define XCHAL_INT7_LEVEL 0 # define XCHAL_INT7_TYPE XTHAL_INTTYPE_UNCONFIGURED #endif #if XCHAL_NUM_INTERRUPTS <= 8 # define XCHAL_INT8_LEVEL 0 # define XCHAL_INT8_TYPE XTHAL_INTTYPE_UNCONFIGURED #endif #if XCHAL_NUM_INTERRUPTS <= 9 # define XCHAL_INT9_LEVEL 0 # define XCHAL_INT9_TYPE XTHAL_INTTYPE_UNCONFIGURED #endif #if XCHAL_NUM_INTERRUPTS <= 10 # define XCHAL_INT10_LEVEL 0 # define XCHAL_INT10_TYPE XTHAL_INTTYPE_UNCONFIGURED #endif #if XCHAL_NUM_INTERRUPTS <= 11 # define XCHAL_INT11_LEVEL 0 # define XCHAL_INT11_TYPE XTHAL_INTTYPE_UNCONFIGURED #endif #if XCHAL_NUM_INTERRUPTS <= 12 # define XCHAL_INT12_LEVEL 0 # define XCHAL_INT12_TYPE XTHAL_INTTYPE_UNCONFIGURED #endif #if XCHAL_NUM_INTERRUPTS <= 13 # define XCHAL_INT13_LEVEL 0 # define XCHAL_INT13_TYPE XTHAL_INTTYPE_UNCONFIGURED #endif #if XCHAL_NUM_INTERRUPTS <= 14 # define XCHAL_INT14_LEVEL 0 # define XCHAL_INT14_TYPE XTHAL_INTTYPE_UNCONFIGURED #endif #if XCHAL_NUM_INTERRUPTS <= 15 # define XCHAL_INT15_LEVEL 0 # define XCHAL_INT15_TYPE XTHAL_INTTYPE_UNCONFIGURED #endif #if XCHAL_NUM_INTERRUPTS <= 16 # define XCHAL_INT16_LEVEL 0 # define XCHAL_INT16_TYPE XTHAL_INTTYPE_UNCONFIGURED #endif #if XCHAL_NUM_INTERRUPTS <= 17 # define XCHAL_INT17_LEVEL 0 # define XCHAL_INT17_TYPE XTHAL_INTTYPE_UNCONFIGURED #endif #if XCHAL_NUM_INTERRUPTS <= 18 # define XCHAL_INT18_LEVEL 0 # define XCHAL_INT18_TYPE XTHAL_INTTYPE_UNCONFIGURED #endif #if XCHAL_NUM_INTERRUPTS <= 19 # define XCHAL_INT19_LEVEL 0 # define XCHAL_INT19_TYPE XTHAL_INTTYPE_UNCONFIGURED #endif #if XCHAL_NUM_INTERRUPTS <= 20 # define XCHAL_INT20_LEVEL 0 # define XCHAL_INT20_TYPE XTHAL_INTTYPE_UNCONFIGURED #endif #if XCHAL_NUM_INTERRUPTS <= 21 # define XCHAL_INT21_LEVEL 0 # define XCHAL_INT21_TYPE XTHAL_INTTYPE_UNCONFIGURED #endif #if XCHAL_NUM_INTERRUPTS <= 22 # define XCHAL_INT22_LEVEL 0 # define XCHAL_INT22_TYPE XTHAL_INTTYPE_UNCONFIGURED #endif #if XCHAL_NUM_INTERRUPTS <= 23 # define XCHAL_INT23_LEVEL 0 # define XCHAL_INT23_TYPE XTHAL_INTTYPE_UNCONFIGURED #endif #if XCHAL_NUM_INTERRUPTS <= 24 # define XCHAL_INT24_LEVEL 0 # define XCHAL_INT24_TYPE XTHAL_INTTYPE_UNCONFIGURED #endif #if XCHAL_NUM_INTERRUPTS <= 25 # define XCHAL_INT25_LEVEL 0 # define XCHAL_INT25_TYPE XTHAL_INTTYPE_UNCONFIGURED #endif #if XCHAL_NUM_INTERRUPTS <= 26 # define XCHAL_INT26_LEVEL 0 # define XCHAL_INT26_TYPE XTHAL_INTTYPE_UNCONFIGURED #endif #if XCHAL_NUM_INTERRUPTS <= 27 # define XCHAL_INT27_LEVEL 0 # define XCHAL_INT27_TYPE XTHAL_INTTYPE_UNCONFIGURED #endif #if XCHAL_NUM_INTERRUPTS <= 28 # define XCHAL_INT28_LEVEL 0 # define XCHAL_INT28_TYPE XTHAL_INTTYPE_UNCONFIGURED #endif #if XCHAL_NUM_INTERRUPTS <= 29 # define XCHAL_INT29_LEVEL 0 # define XCHAL_INT29_TYPE XTHAL_INTTYPE_UNCONFIGURED #endif #if XCHAL_NUM_INTERRUPTS <= 30 # define XCHAL_INT30_LEVEL 0 # define XCHAL_INT30_TYPE XTHAL_INTTYPE_UNCONFIGURED #endif #if XCHAL_NUM_INTERRUPTS <= 31 # define XCHAL_INT31_LEVEL 0 # define XCHAL_INT31_TYPE XTHAL_INTTYPE_UNCONFIGURED #endif /* * Masks and levels corresponding to each *external* interrupt. */ #define XCHAL_EXTINT0_MASK (1 << XCHAL_EXTINT0_NUM) #define XCHAL_EXTINT0_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT0_NUM) #define XCHAL_EXTINT1_MASK (1 << XCHAL_EXTINT1_NUM) #define XCHAL_EXTINT1_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT1_NUM) #define XCHAL_EXTINT2_MASK (1 << XCHAL_EXTINT2_NUM) #define XCHAL_EXTINT2_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT2_NUM) #define XCHAL_EXTINT3_MASK (1 << XCHAL_EXTINT3_NUM) #define XCHAL_EXTINT3_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT3_NUM) #define XCHAL_EXTINT4_MASK (1 << XCHAL_EXTINT4_NUM) #define XCHAL_EXTINT4_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT4_NUM) #define XCHAL_EXTINT5_MASK (1 << XCHAL_EXTINT5_NUM) #define XCHAL_EXTINT5_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT5_NUM) #define XCHAL_EXTINT6_MASK (1 << XCHAL_EXTINT6_NUM) #define XCHAL_EXTINT6_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT6_NUM) #define XCHAL_EXTINT7_MASK (1 << XCHAL_EXTINT7_NUM) #define XCHAL_EXTINT7_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT7_NUM) #define XCHAL_EXTINT8_MASK (1 << XCHAL_EXTINT8_NUM) #define XCHAL_EXTINT8_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT8_NUM) #define XCHAL_EXTINT9_MASK (1 << XCHAL_EXTINT9_NUM) #define XCHAL_EXTINT9_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT9_NUM) #define XCHAL_EXTINT10_MASK (1 << XCHAL_EXTINT10_NUM) #define XCHAL_EXTINT10_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT10_NUM) #define XCHAL_EXTINT11_MASK (1 << XCHAL_EXTINT11_NUM) #define XCHAL_EXTINT11_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT11_NUM) #define XCHAL_EXTINT12_MASK (1 << XCHAL_EXTINT12_NUM) #define XCHAL_EXTINT12_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT12_NUM) #define XCHAL_EXTINT13_MASK (1 << XCHAL_EXTINT13_NUM) #define XCHAL_EXTINT13_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT13_NUM) #define XCHAL_EXTINT14_MASK (1 << XCHAL_EXTINT14_NUM) #define XCHAL_EXTINT14_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT14_NUM) #define XCHAL_EXTINT15_MASK (1 << XCHAL_EXTINT15_NUM) #define XCHAL_EXTINT15_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT15_NUM) #define XCHAL_EXTINT16_MASK (1 << XCHAL_EXTINT16_NUM) #define XCHAL_EXTINT16_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT16_NUM) #define XCHAL_EXTINT17_MASK (1 << XCHAL_EXTINT17_NUM) #define XCHAL_EXTINT17_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT17_NUM) #define XCHAL_EXTINT18_MASK (1 << XCHAL_EXTINT18_NUM) #define XCHAL_EXTINT18_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT18_NUM) #define XCHAL_EXTINT19_MASK (1 << XCHAL_EXTINT19_NUM) #define XCHAL_EXTINT19_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT19_NUM) #define XCHAL_EXTINT20_MASK (1 << XCHAL_EXTINT20_NUM) #define XCHAL_EXTINT20_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT20_NUM) #define XCHAL_EXTINT21_MASK (1 << XCHAL_EXTINT21_NUM) #define XCHAL_EXTINT21_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT21_NUM) #define XCHAL_EXTINT22_MASK (1 << XCHAL_EXTINT22_NUM) #define XCHAL_EXTINT22_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT22_NUM) #define XCHAL_EXTINT23_MASK (1 << XCHAL_EXTINT23_NUM) #define XCHAL_EXTINT23_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT23_NUM) #define XCHAL_EXTINT24_MASK (1 << XCHAL_EXTINT24_NUM) #define XCHAL_EXTINT24_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT24_NUM) #define XCHAL_EXTINT25_MASK (1 << XCHAL_EXTINT25_NUM) #define XCHAL_EXTINT25_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT25_NUM) #define XCHAL_EXTINT26_MASK (1 << XCHAL_EXTINT26_NUM) #define XCHAL_EXTINT26_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT26_NUM) #define XCHAL_EXTINT27_MASK (1 << XCHAL_EXTINT27_NUM) #define XCHAL_EXTINT27_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT27_NUM) #define XCHAL_EXTINT28_MASK (1 << XCHAL_EXTINT28_NUM) #define XCHAL_EXTINT28_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT28_NUM) #define XCHAL_EXTINT29_MASK (1 << XCHAL_EXTINT29_NUM) #define XCHAL_EXTINT29_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT29_NUM) #define XCHAL_EXTINT30_MASK (1 << XCHAL_EXTINT30_NUM) #define XCHAL_EXTINT30_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT30_NUM) #define XCHAL_EXTINT31_MASK (1 << XCHAL_EXTINT31_NUM) #define XCHAL_EXTINT31_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT31_NUM) /*---------------------------------------------------------------------- EXCEPTIONS and VECTORS ----------------------------------------------------------------------*/ /* For backward compatibility ONLY -- DO NOT USE (will be removed in future release): */ #define XCHAL_HAVE_OLD_EXC_ARCH XCHAL_HAVE_XEA1 /* (DEPRECATED) 1 if old exception architecture (XEA1), 0 otherwise (eg. XEA2) */ #define XCHAL_HAVE_EXCM XCHAL_HAVE_XEA2 /* (DEPRECATED) 1 if PS.EXCM bit exists (currently equals XCHAL_HAVE_TLBS) */ #ifdef XCHAL_USER_VECTOR_VADDR #define XCHAL_PROGRAMEXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR #define XCHAL_USEREXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR #endif #ifdef XCHAL_USER_VECTOR_PADDR # define XCHAL_PROGRAMEXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR # define XCHAL_USEREXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR #endif #ifdef XCHAL_KERNEL_VECTOR_VADDR # define XCHAL_STACKEDEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR # define XCHAL_KERNELEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR #endif #ifdef XCHAL_KERNEL_VECTOR_PADDR # define XCHAL_STACKEDEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR # define XCHAL_KERNELEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR #endif #if 0 #if XCHAL_HAVE_DEBUG # define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL_VECTOR_VADDR(XCHAL_DEBUGLEVEL) /* This one should only get defined if the corresponding intlevel paddr macro exists: */ # define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL_VECTOR_PADDR(XCHAL_DEBUGLEVEL) #endif #endif /* Indexing macros: */ #define _XCHAL_INTLEVEL_VECTOR_VADDR(n) XCHAL_INTLEVEL ## n ## _VECTOR_VADDR #define XCHAL_INTLEVEL_VECTOR_VADDR(n) _XCHAL_INTLEVEL_VECTOR_VADDR(n) /* n = 0 .. 15 */ /* * General Exception Causes * (values of EXCCAUSE special register set by general exceptions, * which vector to the user, kernel, or double-exception vectors). * * DEPRECATED. Please use the equivalent EXCCAUSE_xxx macros * defined in . (Note that these have slightly * different names, they don't just have the XCHAL_ prefix removed.) */ #define XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION 0 /* Illegal Instruction */ #define XCHAL_EXCCAUSE_SYSTEM_CALL 1 /* System Call */ #define XCHAL_EXCCAUSE_INSTRUCTION_FETCH_ERROR 2 /* Instruction Fetch Error */ #define XCHAL_EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */ #define XCHAL_EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */ #define XCHAL_EXCCAUSE_ALLOCA 5 /* Stack Extension Assist */ #define XCHAL_EXCCAUSE_INTEGER_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */ #define XCHAL_EXCCAUSE_SPECULATION 7 /* Speculation */ #define XCHAL_EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */ #define XCHAL_EXCCAUSE_UNALIGNED 9 /* Unaligned Load Store */ /*10..15 reserved*/ #define XCHAL_EXCCAUSE_ITLB_MISS 16 /* ITlb Miss Exception */ #define XCHAL_EXCCAUSE_ITLB_MULTIHIT 17 /* ITlb Mutltihit Exception */ #define XCHAL_EXCCAUSE_ITLB_PRIVILEGE 18 /* ITlb Privilege Exception */ #define XCHAL_EXCCAUSE_ITLB_SIZE_RESTRICTION 19 /* ITlb Size Restriction Exception */ #define XCHAL_EXCCAUSE_FETCH_CACHE_ATTRIBUTE 20 /* Fetch Cache Attribute Exception */ /*21..23 reserved*/ #define XCHAL_EXCCAUSE_DTLB_MISS 24 /* DTlb Miss Exception */ #define XCHAL_EXCCAUSE_DTLB_MULTIHIT 25 /* DTlb Multihit Exception */ #define XCHAL_EXCCAUSE_DTLB_PRIVILEGE 26 /* DTlb Privilege Exception */ #define XCHAL_EXCCAUSE_DTLB_SIZE_RESTRICTION 27 /* DTlb Size Restriction Exception */ #define XCHAL_EXCCAUSE_LOAD_CACHE_ATTRIBUTE 28 /* Load Cache Attribute Exception */ #define XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE 29 /* Store Cache Attribute Exception */ /*30..31 reserved*/ #define XCHAL_EXCCAUSE_COPROCESSOR0_DISABLED 32 /* Coprocessor 0 disabled */ #define XCHAL_EXCCAUSE_COPROCESSOR1_DISABLED 33 /* Coprocessor 1 disabled */ #define XCHAL_EXCCAUSE_COPROCESSOR2_DISABLED 34 /* Coprocessor 2 disabled */ #define XCHAL_EXCCAUSE_COPROCESSOR3_DISABLED 35 /* Coprocessor 3 disabled */ #define XCHAL_EXCCAUSE_COPROCESSOR4_DISABLED 36 /* Coprocessor 4 disabled */ #define XCHAL_EXCCAUSE_COPROCESSOR5_DISABLED 37 /* Coprocessor 5 disabled */ #define XCHAL_EXCCAUSE_COPROCESSOR6_DISABLED 38 /* Coprocessor 6 disabled */ #define XCHAL_EXCCAUSE_COPROCESSOR7_DISABLED 39 /* Coprocessor 7 disabled */ #define XCHAL_EXCCAUSE_FLOATING_POINT 40 /* Floating Point Exception */ /*40..63 reserved*/ /* * Miscellaneous special register fields. * * For each special register, and each field within each register: * XCHAL__VALIDMASK is the set of bits defined in the register. * XCHAL___BITS is the number of bits in the field. * XCHAL___NUM is 2^bits, the number of possible values * of the field. * XCHAL___SHIFT is the position of the field within * the register, starting from the least significant bit. * * DEPRECATED. Please use the equivalent macros defined in * . (Note that these have different names.) */ /* DBREAKC (special register number 160): */ #define XCHAL_DBREAKC_VALIDMASK 0xC000003F #define XCHAL_DBREAKC_MASK_BITS 6 #define XCHAL_DBREAKC_MASK_NUM 64 #define XCHAL_DBREAKC_MASK_SHIFT 0 #define XCHAL_DBREAKC_MASK_MASK 0x0000003F #define XCHAL_DBREAKC_LOADBREAK_BITS 1 #define XCHAL_DBREAKC_LOADBREAK_NUM 2 #define XCHAL_DBREAKC_LOADBREAK_SHIFT 30 #define XCHAL_DBREAKC_LOADBREAK_MASK 0x40000000 #define XCHAL_DBREAKC_STOREBREAK_BITS 1 #define XCHAL_DBREAKC_STOREBREAK_NUM 2 #define XCHAL_DBREAKC_STOREBREAK_SHIFT 31 #define XCHAL_DBREAKC_STOREBREAK_MASK 0x80000000 /* PS (special register number 230): */ #define XCHAL_PS_VALIDMASK 0x00070F3F #define XCHAL_PS_INTLEVEL_BITS 4 #define XCHAL_PS_INTLEVEL_NUM 16 #define XCHAL_PS_INTLEVEL_SHIFT 0 #define XCHAL_PS_INTLEVEL_MASK 0x0000000F #define XCHAL_PS_EXCM_BITS 1 #define XCHAL_PS_EXCM_NUM 2 #define XCHAL_PS_EXCM_SHIFT 4 #define XCHAL_PS_EXCM_MASK 0x00000010 #define XCHAL_PS_UM_BITS 1 #define XCHAL_PS_UM_NUM 2 #define XCHAL_PS_UM_SHIFT 5 #define XCHAL_PS_UM_MASK 0x00000020 #define XCHAL_PS_RING_BITS 2 #define XCHAL_PS_RING_NUM 4 #define XCHAL_PS_RING_SHIFT 6 #define XCHAL_PS_RING_MASK 0x000000C0 #define XCHAL_PS_OWB_BITS 4 #define XCHAL_PS_OWB_NUM 16 #define XCHAL_PS_OWB_SHIFT 8 #define XCHAL_PS_OWB_MASK 0x00000F00 #define XCHAL_PS_CALLINC_BITS 2 #define XCHAL_PS_CALLINC_NUM 4 #define XCHAL_PS_CALLINC_SHIFT 16 #define XCHAL_PS_CALLINC_MASK 0x00030000 #define XCHAL_PS_WOE_BITS 1 #define XCHAL_PS_WOE_NUM 2 #define XCHAL_PS_WOE_SHIFT 18 #define XCHAL_PS_WOE_MASK 0x00040000 /* EXCCAUSE (special register number 232): */ #define XCHAL_EXCCAUSE_VALIDMASK 0x0000003F #define XCHAL_EXCCAUSE_BITS 6 #define XCHAL_EXCCAUSE_NUM 64 #define XCHAL_EXCCAUSE_SHIFT 0 #define XCHAL_EXCCAUSE_MASK 0x0000003F /* DEBUGCAUSE (special register number 233): */ #define XCHAL_DEBUGCAUSE_VALIDMASK 0x0000003F #define XCHAL_DEBUGCAUSE_ICOUNT_BITS 1 #define XCHAL_DEBUGCAUSE_ICOUNT_NUM 2 #define XCHAL_DEBUGCAUSE_ICOUNT_SHIFT 0 #define XCHAL_DEBUGCAUSE_ICOUNT_MASK 0x00000001 #define XCHAL_DEBUGCAUSE_IBREAK_BITS 1 #define XCHAL_DEBUGCAUSE_IBREAK_NUM 2 #define XCHAL_DEBUGCAUSE_IBREAK_SHIFT 1 #define XCHAL_DEBUGCAUSE_IBREAK_MASK 0x00000002 #define XCHAL_DEBUGCAUSE_DBREAK_BITS 1 #define XCHAL_DEBUGCAUSE_DBREAK_NUM 2 #define XCHAL_DEBUGCAUSE_DBREAK_SHIFT 2 #define XCHAL_DEBUGCAUSE_DBREAK_MASK 0x00000004 #define XCHAL_DEBUGCAUSE_BREAK_BITS 1 #define XCHAL_DEBUGCAUSE_BREAK_NUM 2 #define XCHAL_DEBUGCAUSE_BREAK_SHIFT 3 #define XCHAL_DEBUGCAUSE_BREAK_MASK 0x00000008 #define XCHAL_DEBUGCAUSE_BREAKN_BITS 1 #define XCHAL_DEBUGCAUSE_BREAKN_NUM 2 #define XCHAL_DEBUGCAUSE_BREAKN_SHIFT 4 #define XCHAL_DEBUGCAUSE_BREAKN_MASK 0x00000010 #define XCHAL_DEBUGCAUSE_DEBUGINT_BITS 1 #define XCHAL_DEBUGCAUSE_DEBUGINT_NUM 2 #define XCHAL_DEBUGCAUSE_DEBUGINT_SHIFT 5 #define XCHAL_DEBUGCAUSE_DEBUGINT_MASK 0x00000020 /*---------------------------------------------------------------------- TIMERS ----------------------------------------------------------------------*/ /*#define XCHAL_HAVE_TIMERS XCHAL_HAVE_CCOUNT*/ /*---------------------------------------------------------------------- INTERNAL I/D RAM/ROMs and XLMI ----------------------------------------------------------------------*/ #define XCHAL_NUM_IROM XCHAL_NUM_INSTROM /* (DEPRECATED) */ #define XCHAL_NUM_IRAM XCHAL_NUM_INSTRAM /* (DEPRECATED) */ #define XCHAL_NUM_DROM XCHAL_NUM_DATAROM /* (DEPRECATED) */ #define XCHAL_NUM_DRAM XCHAL_NUM_DATARAM /* (DEPRECATED) */ #define XCHAL_IROM0_VADDR XCHAL_INSTROM0_VADDR /* (DEPRECATED) */ #define XCHAL_IROM0_PADDR XCHAL_INSTROM0_PADDR /* (DEPRECATED) */ #define XCHAL_IROM0_SIZE XCHAL_INSTROM0_SIZE /* (DEPRECATED) */ #define XCHAL_IROM1_VADDR XCHAL_INSTROM1_VADDR /* (DEPRECATED) */ #define XCHAL_IROM1_PADDR XCHAL_INSTROM1_PADDR /* (DEPRECATED) */ #define XCHAL_IROM1_SIZE XCHAL_INSTROM1_SIZE /* (DEPRECATED) */ #define XCHAL_IRAM0_VADDR XCHAL_INSTRAM0_VADDR /* (DEPRECATED) */ #define XCHAL_IRAM0_PADDR XCHAL_INSTRAM0_PADDR /* (DEPRECATED) */ #define XCHAL_IRAM0_SIZE XCHAL_INSTRAM0_SIZE /* (DEPRECATED) */ #define XCHAL_IRAM1_VADDR XCHAL_INSTRAM1_VADDR /* (DEPRECATED) */ #define XCHAL_IRAM1_PADDR XCHAL_INSTRAM1_PADDR /* (DEPRECATED) */ #define XCHAL_IRAM1_SIZE XCHAL_INSTRAM1_SIZE /* (DEPRECATED) */ #define XCHAL_DROM0_VADDR XCHAL_DATAROM0_VADDR /* (DEPRECATED) */ #define XCHAL_DROM0_PADDR XCHAL_DATAROM0_PADDR /* (DEPRECATED) */ #define XCHAL_DROM0_SIZE XCHAL_DATAROM0_SIZE /* (DEPRECATED) */ #define XCHAL_DROM1_VADDR XCHAL_DATAROM1_VADDR /* (DEPRECATED) */ #define XCHAL_DROM1_PADDR XCHAL_DATAROM1_PADDR /* (DEPRECATED) */ #define XCHAL_DROM1_SIZE XCHAL_DATAROM1_SIZE /* (DEPRECATED) */ #define XCHAL_DRAM0_VADDR XCHAL_DATARAM0_VADDR /* (DEPRECATED) */ #define XCHAL_DRAM0_PADDR XCHAL_DATARAM0_PADDR /* (DEPRECATED) */ #define XCHAL_DRAM0_SIZE XCHAL_DATARAM0_SIZE /* (DEPRECATED) */ #define XCHAL_DRAM1_VADDR XCHAL_DATARAM1_VADDR /* (DEPRECATED) */ #define XCHAL_DRAM1_PADDR XCHAL_DATARAM1_PADDR /* (DEPRECATED) */ #define XCHAL_DRAM1_SIZE XCHAL_DATARAM1_SIZE /* (DEPRECATED) */ /*---------------------------------------------------------------------- CACHE ----------------------------------------------------------------------*/ /* Max for both I-cache and D-cache (used for general alignment): */ #if XCHAL_ICACHE_LINESIZE > XCHAL_DCACHE_LINESIZE # define XCHAL_CACHE_LINEWIDTH_MAX XCHAL_ICACHE_LINEWIDTH # define XCHAL_CACHE_LINESIZE_MAX XCHAL_ICACHE_LINESIZE #else # define XCHAL_CACHE_LINEWIDTH_MAX XCHAL_DCACHE_LINEWIDTH # define XCHAL_CACHE_LINESIZE_MAX XCHAL_DCACHE_LINESIZE #endif #define XCHAL_ICACHE_SETSIZE (1< XCHAL_DCACHE_SETWIDTH # define XCHAL_CACHE_SETWIDTH_MAX XCHAL_ICACHE_SETWIDTH # define XCHAL_CACHE_SETSIZE_MAX XCHAL_ICACHE_SETSIZE #else # define XCHAL_CACHE_SETWIDTH_MAX XCHAL_DCACHE_SETWIDTH # define XCHAL_CACHE_SETSIZE_MAX XCHAL_DCACHE_SETSIZE #endif /* Instruction cache tag bits: */ #define XCHAL_ICACHE_TAG_V_SHIFT 0 #define XCHAL_ICACHE_TAG_V 0x1 /* valid bit */ #if XCHAL_ICACHE_WAYS > 1 # define XCHAL_ICACHE_TAG_F_SHIFT 1 # define XCHAL_ICACHE_TAG_F 0x2 /* fill (LRU) bit */ #else # define XCHAL_ICACHE_TAG_F_SHIFT 0 # define XCHAL_ICACHE_TAG_F 0 /* no fill (LRU) bit */ #endif #if XCHAL_ICACHE_LINE_LOCKABLE # define XCHAL_ICACHE_TAG_L_SHIFT (XCHAL_ICACHE_TAG_F_SHIFT+1) # define XCHAL_ICACHE_TAG_L (1 << XCHAL_ICACHE_TAG_L_SHIFT) /* lock bit */ #else # define XCHAL_ICACHE_TAG_L_SHIFT XCHAL_ICACHE_TAG_F_SHIFT # define XCHAL_ICACHE_TAG_L 0 /* no lock bit */ #endif /* Data cache tag bits: */ #define XCHAL_DCACHE_TAG_V_SHIFT 0 #define XCHAL_DCACHE_TAG_V 0x1 /* valid bit */ #if XCHAL_DCACHE_WAYS > 1 # define XCHAL_DCACHE_TAG_F_SHIFT 1 # define XCHAL_DCACHE_TAG_F 0x2 /* fill (LRU) bit */ #else # define XCHAL_DCACHE_TAG_F_SHIFT 0 # define XCHAL_DCACHE_TAG_F 0 /* no fill (LRU) bit */ #endif #if XCHAL_DCACHE_IS_WRITEBACK # define XCHAL_DCACHE_TAG_D_SHIFT (XCHAL_DCACHE_TAG_F_SHIFT+1) # define XCHAL_DCACHE_TAG_D (1 << XCHAL_DCACHE_TAG_D_SHIFT) /* dirty bit */ #else # define XCHAL_DCACHE_TAG_D_SHIFT XCHAL_DCACHE_TAG_F_SHIFT # define XCHAL_DCACHE_TAG_D 0 /* no dirty bit */ #endif #if XCHAL_DCACHE_LINE_LOCKABLE # define XCHAL_DCACHE_TAG_L_SHIFT (XCHAL_DCACHE_TAG_D_SHIFT+1) # define XCHAL_DCACHE_TAG_L (1 << XCHAL_DCACHE_TAG_D_SHIFT) /* lock bit */ #else # define XCHAL_DCACHE_TAG_L_SHIFT XCHAL_DCACHE_TAG_D_SHIFT # define XCHAL_DCACHE_TAG_L 0 /* no lock bit */ #endif /*---------------------------------------------------------------------- MMU ----------------------------------------------------------------------*/ /* See for more details. */ #define XCHAL_HAVE_MMU XCHAL_HAVE_TLBS /* (DEPRECATED; use XCHAL_HAVE_TLBS instead; will be removed in future release) */ /* Indexing macros: */ #define _XCHAL_ITLB_SET(n,_what) XCHAL_ITLB_SET ## n ## _what #define XCHAL_ITLB_SET(n,what) _XCHAL_ITLB_SET(n, _ ## what ) #define _XCHAL_ITLB_SET_E(n,i,_what) XCHAL_ITLB_SET ## n ## _E ## i ## _what #define XCHAL_ITLB_SET_E(n,i,what) _XCHAL_ITLB_SET_E(n,i, _ ## what ) #define _XCHAL_DTLB_SET(n,_what) XCHAL_DTLB_SET ## n ## _what #define XCHAL_DTLB_SET(n,what) _XCHAL_DTLB_SET(n, _ ## what ) #define _XCHAL_DTLB_SET_E(n,i,_what) XCHAL_DTLB_SET ## n ## _E ## i ## _what #define XCHAL_DTLB_SET_E(n,i,what) _XCHAL_DTLB_SET_E(n,i, _ ## what ) /* * Example use: XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,ENTRIES) * to get the value of XCHAL_ITLB_SET_ENTRIES where is the first auto-refill set. */ /* Number of entries per autorefill way: */ #define XCHAL_ITLB_ARF_ENTRIES (1< 0 && XCHAL_DTLB_ARF_WAYS > 0 && XCHAL_MMU_RINGS >= 2 # define XCHAL_HAVE_PTP_MMU 1 /* have full MMU (with page table [autorefill] and protection) */ #else # define XCHAL_HAVE_PTP_MMU 0 /* don't have full MMU */ #endif #endif /* * For full MMUs, report kernel RAM segment and kernel I/O segment static page mappings: */ #if XCHAL_HAVE_PTP_MMU #define XCHAL_KSEG_CACHED_VADDR 0xD0000000 /* virt.addr of kernel RAM cached static map */ #define XCHAL_KSEG_CACHED_PADDR 0x00000000 /* phys.addr of kseg_cached */ #define XCHAL_KSEG_CACHED_SIZE 0x08000000 /* size in bytes of kseg_cached (assumed power of 2!!!) */ #define XCHAL_KSEG_BYPASS_VADDR 0xD8000000 /* virt.addr of kernel RAM bypass (uncached) static map */ #define XCHAL_KSEG_BYPASS_PADDR 0x00000000 /* phys.addr of kseg_bypass */ #define XCHAL_KSEG_BYPASS_SIZE 0x08000000 /* size in bytes of kseg_bypass (assumed power of 2!!!) */ #define XCHAL_KIO_CACHED_VADDR 0xE0000000 /* virt.addr of kernel I/O cached static map */ #define XCHAL_KIO_CACHED_PADDR 0xF0000000 /* phys.addr of kio_cached */ #define XCHAL_KIO_CACHED_SIZE 0x10000000 /* size in bytes of kio_cached (assumed power of 2!!!) */ #define XCHAL_KIO_BYPASS_VADDR 0xF0000000 /* virt.addr of kernel I/O bypass (uncached) static map */ #define XCHAL_KIO_BYPASS_PADDR 0xF0000000 /* phys.addr of kio_bypass */ #define XCHAL_KIO_BYPASS_SIZE 0x10000000 /* size in bytes of kio_bypass (assumed power of 2!!!) */ #define XCHAL_SEG_MAPPABLE_VADDR 0x00000000 /* start of largest non-static-mapped virtual addr area */ #define XCHAL_SEG_MAPPABLE_SIZE 0xD0000000 /* size in bytes of " */ /* define XCHAL_SEG_MAPPABLE2_xxx if more areas present, sorted in order of descending size. */ #endif /*---------------------------------------------------------------------- MISC ----------------------------------------------------------------------*/ /* Data alignment required if used for instructions: */ #if XCHAL_INST_FETCH_WIDTH > XCHAL_DATA_WIDTH # define XCHAL_ALIGN_MAX XCHAL_INST_FETCH_WIDTH #else # define XCHAL_ALIGN_MAX XCHAL_DATA_WIDTH #endif /* * Names kept for backward compatibility. * (Here "RELEASE" is now a misnomer; these are product *versions*, not the releases * under which they are released. In the T10##.# era there was no distinction.) */ #define XCHAL_HW_RELEASE_MAJOR XCHAL_HW_VERSION_MAJOR #define XCHAL_HW_RELEASE_MINOR XCHAL_HW_VERSION_MINOR #define XCHAL_HW_RELEASE_NAME XCHAL_HW_VERSION_NAME /*---------------------------------------------------------------------- COPROCESSORS and EXTRA STATE ----------------------------------------------------------------------*/ #define XCHAL_EXTRA_SA_SIZE XCHAL_NCP_SA_SIZE #define XCHAL_EXTRA_SA_ALIGN XCHAL_NCP_SA_ALIGN #define XCHAL_CPEXTRA_SA_SIZE XCHAL_TOTAL_SA_SIZE #define XCHAL_CPEXTRA_SA_ALIGN XCHAL_TOTAL_SA_ALIGN #if defined (_ASMLANGUAGE) || defined (__ASSEMBLER__) #define xchal_extratie_load xchal_ncptie_load #define xchal_extratie_store xchal_ncptie_store #define xchal_extratie_load_a2 xchal_ncptie_load_a2 #define xchal_extratie_store_a2 xchal_ncptie_store_a2 #define xchal_extra_load xchal_ncp_load #define xchal_extra_store xchal_ncp_store #define xchal_extra_load_a2 xchal_ncp_load_a2 #define xchal_extra_store_a2 xchal_ncp_store_a2 #define xchal_extra_load_funcbody xchal_ncp_load_a2 #define xchal_extra_store_funcbody xchal_ncp_store_a2 /* Empty placeholder macros for undefined coprocessors: */ # ifndef XCHAL_CP0_NAME # define xchal_cp0_store_a2 xchal_cp0_store a2, a3 # define xchal_cp0_load_a2 xchal_cp0_load a2, a3 .macro xchal_cp0_store ptr tmp .endm .macro xchal_cp0_load ptr tmp .endm # endif # ifndef XCHAL_CP1_NAME # define xchal_cp1_store_a2 xchal_cp1_store a2, a3 # define xchal_cp1_load_a2 xchal_cp1_load a2, a3 .macro xchal_cp1_store ptr tmp .endm .macro xchal_cp1_load ptr tmp .endm # endif # ifndef XCHAL_CP2_NAME # define xchal_cp2_store_a2 xchal_cp2_store a2, a3 # define xchal_cp2_load_a2 xchal_cp2_load a2, a3 .macro xchal_cp2_store ptr tmp .endm .macro xchal_cp2_load ptr tmp .endm # endif # ifndef XCHAL_CP3_NAME # define xchal_cp3_store_a2 xchal_cp3_store a2, a3 # define xchal_cp3_load_a2 xchal_cp3_load a2, a3 .macro xchal_cp3_store ptr tmp .endm .macro xchal_cp3_load ptr tmp .endm # endif # ifndef XCHAL_CP4_NAME # define xchal_cp4_store_a2 xchal_cp4_store a2, a3 # define xchal_cp4_load_a2 xchal_cp4_load a2, a3 .macro xchal_cp4_store ptr tmp .endm .macro xchal_cp4_load ptr tmp .endm # endif # ifndef XCHAL_CP5_NAME # define xchal_cp5_store_a2 xchal_cp5_store a2, a3 # define xchal_cp5_load_a2 xchal_cp5_load a2, a3 .macro xchal_cp5_store ptr tmp .endm .macro xchal_cp5_load ptr tmp .endm # endif # ifndef XCHAL_CP6_NAME # define xchal_cp6_store_a2 xchal_cp6_store a2, a3 # define xchal_cp6_load_a2 xchal_cp6_load a2, a3 .macro xchal_cp6_store ptr tmp .endm .macro xchal_cp6_load ptr tmp .endm # endif # ifndef XCHAL_CP7_NAME # define xchal_cp7_store_a2 xchal_cp7_store a2, a3 # define xchal_cp7_load_a2 xchal_cp7_load a2, a3 .macro xchal_cp7_store ptr tmp .endm .macro xchal_cp7_load ptr tmp .endm # endif /******************** * Macros to create functions that save and restore the state of *any* TIE * coprocessor (by dynamic index). */ /* * Macro that expands to the body of a function * that stores the selected coprocessor's state (registers etc). * Entry: a2 = ptr to save area in which to save cp state * a3 = coprocessor number * Exit: any register a2-a15 (?) may have been clobbered. */ .macro xchal_cpi_store_funcbody # ifdef XCHAL_CP0_NAME bnez a3, 99f xchal_cp0_store_a2 j 90f 99: # endif # ifdef XCHAL_CP1_NAME bnei a3, 1, 99f xchal_cp1_store_a2 j 90f 99: # endif # ifdef XCHAL_CP2_NAME bnei a3, 2, 99f xchal_cp2_store_a2 j 90f 99: # endif # ifdef XCHAL_CP3_NAME bnei a3, 3, 99f xchal_cp3_store_a2 j 90f 99: # endif # ifdef XCHAL_CP4_NAME bnei a3, 4, 99f xchal_cp4_store_a2 j 90f 99: # endif # ifdef XCHAL_CP5_NAME bnei a3, 5, 99f xchal_cp5_store_a2 j 90f 99: # endif # ifdef XCHAL_CP6_NAME bnei a3, 6, 99f xchal_cp6_store_a2 j 90f 99: # endif # ifdef XCHAL_CP7_NAME bnei a3, 7, 99f xchal_cp7_store_a2 j 90f 99: # endif 90: .endm /* * Macro that expands to the body of a function * that loads the selected coprocessor's state (registers etc). * Entry: a2 = ptr to save area from which to restore cp state * a3 = coprocessor number * Exit: any register a2-a15 (?) may have been clobbered. */ .macro xchal_cpi_load_funcbody # ifdef XCHAL_CP0_NAME bnez a3, 99f xchal_cp0_load_a2 j 90f 99: # endif # ifdef XCHAL_CP1_NAME bnei a3, 1, 99f xchal_cp1_load_a2 j 90f 99: # endif # ifdef XCHAL_CP2_NAME bnei a3, 2, 99f xchal_cp2_load_a2 j 90f 99: # endif # ifdef XCHAL_CP3_NAME bnei a3, 3, 99f xchal_cp3_load_a2 j 90f 99: # endif # ifdef XCHAL_CP4_NAME bnei a3, 4, 99f xchal_cp4_load_a2 j 90f 99: # endif # ifdef XCHAL_CP5_NAME bnei a3, 5, 99f xchal_cp5_load_a2 j 90f 99: # endif # ifdef XCHAL_CP6_NAME bnei a3, 6, 99f xchal_cp6_load_a2 j 90f 99: # endif # ifdef XCHAL_CP7_NAME bnei a3, 7, 99f xchal_cp7_load_a2 j 90f 99: # endif 90: .endm #endif /*_ASMLANGUAGE or __ASSEMBLER__*/ /* Other default macros for undefined coprocessors: */ #ifndef XCHAL_CP0_NAME # define XCHAL_CP0_SA_SIZE 0 # define XCHAL_CP0_SA_ALIGN 1 # define XCHAL_CP0_NAME 0 # define XCHAL_CP0_SA_CONTENTS_LIBDB_NUM 0 # define XCHAL_CP0_SA_CONTENTS_LIBDB /* empty */ #endif #ifndef XCHAL_CP1_NAME # define XCHAL_CP1_SA_SIZE 0 # define XCHAL_CP1_SA_ALIGN 1 # define XCHAL_CP1_NAME 0 # define XCHAL_CP1_SA_CONTENTS_LIBDB_NUM 0 # define XCHAL_CP1_SA_CONTENTS_LIBDB /* empty */ #endif #ifndef XCHAL_CP2_NAME # define XCHAL_CP2_SA_SIZE 0 # define XCHAL_CP2_SA_ALIGN 1 # define XCHAL_CP2_NAME 0 # define XCHAL_CP2_SA_CONTENTS_LIBDB_NUM 0 # define XCHAL_CP2_SA_CONTENTS_LIBDB /* empty */ #endif #ifndef XCHAL_CP3_NAME # define XCHAL_CP3_SA_SIZE 0 # define XCHAL_CP3_SA_ALIGN 1 # define XCHAL_CP3_NAME 0 # define XCHAL_CP3_SA_CONTENTS_LIBDB_NUM 0 # define XCHAL_CP3_SA_CONTENTS_LIBDB /* empty */ #endif #ifndef XCHAL_CP4_NAME # define XCHAL_CP4_SA_SIZE 0 # define XCHAL_CP4_SA_ALIGN 1 # define XCHAL_CP4_NAME 0 # define XCHAL_CP4_SA_CONTENTS_LIBDB_NUM 0 # define XCHAL_CP4_SA_CONTENTS_LIBDB /* empty */ #endif #ifndef XCHAL_CP5_NAME # define XCHAL_CP5_SA_SIZE 0 # define XCHAL_CP5_SA_ALIGN 1 # define XCHAL_CP5_NAME 0 # define XCHAL_CP5_SA_CONTENTS_LIBDB_NUM 0 # define XCHAL_CP5_SA_CONTENTS_LIBDB /* empty */ #endif #ifndef XCHAL_CP6_NAME # define XCHAL_CP6_SA_SIZE 0 # define XCHAL_CP6_SA_ALIGN 1 # define XCHAL_CP6_NAME 0 # define XCHAL_CP6_SA_CONTENTS_LIBDB_NUM 0 # define XCHAL_CP6_SA_CONTENTS_LIBDB /* empty */ #endif #ifndef XCHAL_CP7_NAME # define XCHAL_CP7_SA_SIZE 0 # define XCHAL_CP7_SA_ALIGN 1 # define XCHAL_CP7_NAME 0 # define XCHAL_CP7_SA_CONTENTS_LIBDB_NUM 0 # define XCHAL_CP7_SA_CONTENTS_LIBDB /* empty */ #endif /* Indexing macros: */ #define _XCHAL_CP_SA_SIZE(n) XCHAL_CP ## n ## _SA_SIZE #define XCHAL_CP_SA_SIZE(n) _XCHAL_CP_SA_SIZE(n) /* n = 0 .. 7 */ #define _XCHAL_CP_SA_ALIGN(n) XCHAL_CP ## n ## _SA_ALIGN #define XCHAL_CP_SA_ALIGN(n) _XCHAL_CP_SA_ALIGN(n) /* n = 0 .. 7 */ #define XCHAL_CPEXTRA_SA_SIZE_TOR2 XCHAL_CPEXTRA_SA_SIZE /* Tor2Beta only - do not use */ /* Link-time HAL global variables that report coprocessor numbers by name (names are case-preserved from the original TIE): */ #if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__) # define _XCJOIN(a,b) a ## b # define XCJOIN(a,b) _XCJOIN(a,b) # ifdef XCHAL_CP0_NAME extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP0_IDENT); extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP0_IDENT); # endif # ifdef XCHAL_CP1_NAME extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP1_IDENT); extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP1_IDENT); # endif # ifdef XCHAL_CP2_NAME extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP2_IDENT); extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP2_IDENT); # endif # ifdef XCHAL_CP3_NAME extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP3_IDENT); extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP3_IDENT); # endif # ifdef XCHAL_CP4_NAME extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP4_IDENT); extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP4_IDENT); # endif # ifdef XCHAL_CP5_NAME extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP5_IDENT); extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP5_IDENT); # endif # ifdef XCHAL_CP6_NAME extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP6_IDENT); extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP6_IDENT); # endif # ifdef XCHAL_CP7_NAME extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP7_IDENT); extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP7_IDENT); # endif #endif /*---------------------------------------------------------------------- DERIVED ----------------------------------------------------------------------*/ #if XCHAL_HAVE_BE #define XCHAL_INST_ILLN 0xD60F /* 2-byte illegal instruction, msb-first */ #define XCHAL_INST_ILLN_BYTE0 0xD6 /* 2-byte illegal instruction, 1st byte */ #define XCHAL_INST_ILLN_BYTE1 0x0F /* 2-byte illegal instruction, 2nd byte */ #else #define XCHAL_INST_ILLN 0xF06D /* 2-byte illegal instruction, lsb-first */ #define XCHAL_INST_ILLN_BYTE0 0x6D /* 2-byte illegal instruction, 1st byte */ #define XCHAL_INST_ILLN_BYTE1 0xF0 /* 2-byte illegal instruction, 2nd byte */ #endif /* Belongs in xtensa/hal.h: */ #define XTHAL_INST_ILL 0x000000 /* 3-byte illegal instruction */ /* * Because information as to exactly which hardware version is targeted * by a given software build is not always available, compile-time HAL * Hardware-Release "_AT" macros are fuzzy (return 0, 1, or XCHAL_MAYBE): * (Here "RELEASE" is now a misnomer; these are product *versions*, not the releases * under which they are released. In the T10##.# era there was no distinction.) */ #if XCHAL_HW_CONFIGID_RELIABLE # define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) (XTHAL_REL_LE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0) # define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) (XTHAL_REL_GE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0) # define XCHAL_HW_RELEASE_AT(major,minor) (XTHAL_REL_EQ( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0) # define XCHAL_HW_RELEASE_MAJOR_AT(major) ((XCHAL_HW_VERSION_MAJOR == (major)) ? 1 : 0) #else # define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) ( ((major) < 1040 && XCHAL_HAVE_XEA2) ? 0 \ : ((major) > 1050 && XCHAL_HAVE_XEA1) ? 1 \ : XTHAL_MAYBE ) # define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) ( ((major) >= 2000 && XCHAL_HAVE_XEA1) ? 0 \ : (XTHAL_REL_LE(major,minor, 1040,0) && XCHAL_HAVE_XEA2) ? 1 \ : XTHAL_MAYBE ) # define XCHAL_HW_RELEASE_AT(major,minor) ( (((major) < 1040 && XCHAL_HAVE_XEA2) || \ ((major) >= 2000 && XCHAL_HAVE_XEA1)) ? 0 : XTHAL_MAYBE) # define XCHAL_HW_RELEASE_MAJOR_AT(major) XCHAL_HW_RELEASE_AT(major,0) #endif /* * Specific errata: */ /* * Erratum T1020.H13, T1030.H7, T1040.H10, T1050.H4 (fixed in T1040.3 and T1050.1; * relevant only in XEA1, kernel-vector mode, level-one interrupts and overflows enabled): */ #define XCHAL_MAYHAVE_ERRATUM_XEA1KWIN (XCHAL_HAVE_XEA1 && \ (XCHAL_HW_RELEASE_AT_OR_BELOW(1040,2) != 0 \ || XCHAL_HW_RELEASE_AT(1050,0))) #endif /*XTENSA_CONFIG_CORE_H*/ corebits.h000066400000000000000000000162601321570333100357010ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/xtensa-elf/xtensa/* * Copyright (c) 2013 Tensilica Inc. * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sublicense, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /* * xtensa/corebits.h - Xtensa Special Register field positions, masks, values. */ #ifndef XTENSA_COREBITS_H #define XTENSA_COREBITS_H /* EXCCAUSE register fields: */ #define EXCCAUSE_EXCCAUSE_SHIFT 0 #define EXCCAUSE_EXCCAUSE_MASK 0x3F /* EXCCAUSE register values: */ /* * General Exception Causes * (values of EXCCAUSE special register set by general exceptions, * which vector to the user, kernel, or double-exception vectors). */ #define EXCCAUSE_ILLEGAL 0 /* Illegal Instruction */ #define EXCCAUSE_SYSCALL 1 /* System Call (SYSCALL instruction) */ #define EXCCAUSE_INSTR_ERROR 2 /* Instruction Fetch Error */ # define EXCCAUSE_IFETCHERROR 2 /* (backward compatibility macro, deprecated, avoid) */ #define EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */ # define EXCCAUSE_LOADSTOREERROR 3 /* (backward compatibility macro, deprecated, avoid) */ #define EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */ # define EXCCAUSE_LEVEL1INTERRUPT 4 /* (backward compatibility macro, deprecated, avoid) */ #define EXCCAUSE_ALLOCA 5 /* Stack Extension Assist (MOVSP instruction) for alloca */ #define EXCCAUSE_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */ #define EXCCAUSE_SPECULATION 7 /* Use of Failed Speculative Access (not implemented) */ #define EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */ #define EXCCAUSE_UNALIGNED 9 /* Unaligned Load or Store */ /* Reserved 10..11 */ #define EXCCAUSE_INSTR_DATA_ERROR 12 /* PIF Data Error on Instruction Fetch (RB-200x and later) */ #define EXCCAUSE_LOAD_STORE_DATA_ERROR 13 /* PIF Data Error on Load or Store (RB-200x and later) */ #define EXCCAUSE_INSTR_ADDR_ERROR 14 /* PIF Address Error on Instruction Fetch (RB-200x and later) */ #define EXCCAUSE_LOAD_STORE_ADDR_ERROR 15 /* PIF Address Error on Load or Store (RB-200x and later) */ #define EXCCAUSE_ITLB_MISS 16 /* ITLB Miss (no ITLB entry matches, hw refill also missed) */ #define EXCCAUSE_ITLB_MULTIHIT 17 /* ITLB Multihit (multiple ITLB entries match) */ #define EXCCAUSE_INSTR_RING 18 /* Ring Privilege Violation on Instruction Fetch */ /* Reserved 19 */ /* Size Restriction on IFetch (not implemented) */ #define EXCCAUSE_INSTR_PROHIBITED 20 /* Cache Attribute does not allow Instruction Fetch */ /* Reserved 21..23 */ #define EXCCAUSE_DTLB_MISS 24 /* DTLB Miss (no DTLB entry matches, hw refill also missed) */ #define EXCCAUSE_DTLB_MULTIHIT 25 /* DTLB Multihit (multiple DTLB entries match) */ #define EXCCAUSE_LOAD_STORE_RING 26 /* Ring Privilege Violation on Load or Store */ /* Reserved 27 */ /* Size Restriction on Load/Store (not implemented) */ #define EXCCAUSE_LOAD_PROHIBITED 28 /* Cache Attribute does not allow Load */ #define EXCCAUSE_STORE_PROHIBITED 29 /* Cache Attribute does not allow Store */ /* Reserved 30..31 */ #define EXCCAUSE_CP_DISABLED(n) (32+(n)) /* Access to Coprocessor 'n' when disabled */ #define EXCCAUSE_CP0_DISABLED 32 /* Access to Coprocessor 0 when disabled */ #define EXCCAUSE_CP1_DISABLED 33 /* Access to Coprocessor 1 when disabled */ #define EXCCAUSE_CP2_DISABLED 34 /* Access to Coprocessor 2 when disabled */ #define EXCCAUSE_CP3_DISABLED 35 /* Access to Coprocessor 3 when disabled */ #define EXCCAUSE_CP4_DISABLED 36 /* Access to Coprocessor 4 when disabled */ #define EXCCAUSE_CP5_DISABLED 37 /* Access to Coprocessor 5 when disabled */ #define EXCCAUSE_CP6_DISABLED 38 /* Access to Coprocessor 6 when disabled */ #define EXCCAUSE_CP7_DISABLED 39 /* Access to Coprocessor 7 when disabled */ /*#define EXCCAUSE_FLOATING_POINT 40*/ /* Floating Point Exception (not implemented) */ /* Reserved 40..63 */ /* PS register fields: */ #define PS_WOE_SHIFT 18 #define PS_WOE_MASK 0x00040000 #define PS_WOE PS_WOE_MASK #define PS_CALLINC_SHIFT 16 #define PS_CALLINC_MASK 0x00030000 #define PS_CALLINC(n) (((n)&3)<4) 0 2 or >3 (TBD) * T1030.0 0 1 (HAL beta) * T1030.{1,2} 0 3 Equivalent to first release. * T1030.n (n>=3) 0 >= 3 (TBD) * T1040.n 1040 n Full CHAL available from T1040.2 * T1050.n 1050 n . * 6.0.n 6000 n Xtensa Tools v6 (RA-200x.n) * 7.0.n 7000 n Xtensa Tools v7 (RB-200x.n) * 7.1.n 7010 n Xtensa Tools v7.1 (RB-200x.(n+2)) * * * Note: there is a distinction between the software version with * which something is compiled (accessible using XTHAL_RELEASE_* macros) * and the software version with which the HAL library was compiled * (accessible using Xthal_release_* global variables). This * distinction is particularly relevant for vendors that distribute * configuration-independent binaries (eg. an OS), where their customer * might link it with a HAL of a different Xtensa software version. * In this case, it may be appropriate for the OS to verify at run-time * whether XTHAL_RELEASE_* and Xthal_release_* are compatible. * [Guidelines as to which version is compatible with which are not * currently provided explicitly, but might be inferred from reading * OSKit documentation for all releases -- compatibility is also highly * dependent on which HAL features are used. Each version is usually * backward compatible, with very few exceptions if any.] * * Notes: * Tornado 2.0 supported in T1020.3+, T1030.1+, and T1040.{0,1} only. * Tornado 2.0.2 supported in T1040.2+, T1050, and 6.0. * Compile-time HAL port of NucleusPlus supported by T1040.2 and later. */ /* Version comparison operators (among major/minor pairs): */ #define XTHAL_REL_GE(maja,mina, majb,minb) ((maja) > (majb) || \ ((maja) == (majb) && (mina) >= (minb))) #define XTHAL_REL_GT(maja,mina, majb,minb) ((maja) > (majb) || \ ((maja) == (majb) && (mina) > (minb))) #define XTHAL_REL_LE(maja,mina, majb,minb) ((maja) < (majb) || \ ((maja) == (majb) && (mina) <= (minb))) #define XTHAL_REL_LT(maja,mina, majb,minb) ((maja) < (majb) || \ ((maja) == (majb) && (mina) < (minb))) #define XTHAL_REL_EQ(maja,mina, majb,minb) ((maja) == (majb) && (mina) == (minb)) /* Fuzzy (3-way) logic operators: */ #define XTHAL_MAYBE -1 /* 0=NO, 1=YES, -1=MAYBE */ #define XTHAL_FUZZY_AND(a,b) (((a)==0 || (b)==0) ? 0 : ((a)==1 && (b)==1) ? 1 : XTHAL_MAYBE) #define XTHAL_FUZZY_OR(a,b) (((a)==1 || (b)==1) ? 1 : ((a)==0 && (b)==0) ? 0 : XTHAL_MAYBE) #define XTHAL_FUZZY_NOT(a) (((a)==0 || (a)==1) ? (1-(a)) : XTHAL_MAYBE) /* * Architectural limit, independent of configuration: */ #define XTHAL_MAX_CPS 8 /* max number of coprocessors (0..7) */ /* Misc: */ #define XTHAL_LITTLEENDIAN 0 #define XTHAL_BIGENDIAN 1 #if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__) #ifdef __cplusplus extern "C" { #endif /*---------------------------------------------------------------------- HAL ----------------------------------------------------------------------*/ /* Constant to be checked in build = (XTHAL_MAJOR_REV<<16)|XTHAL_MINOR_REV */ extern const unsigned int Xthal_rev_no; /*---------------------------------------------------------------------- Optional/Custom Processor State ----------------------------------------------------------------------*/ /* save & restore the extra processor state */ extern void xthal_save_extra(void *base); extern void xthal_restore_extra(void *base); extern void xthal_save_cpregs(void *base, int); extern void xthal_restore_cpregs(void *base, int); /* versions specific to each coprocessor id */ extern void xthal_save_cp0(void *base); extern void xthal_save_cp1(void *base); extern void xthal_save_cp2(void *base); extern void xthal_save_cp3(void *base); extern void xthal_save_cp4(void *base); extern void xthal_save_cp5(void *base); extern void xthal_save_cp6(void *base); extern void xthal_save_cp7(void *base); extern void xthal_restore_cp0(void *base); extern void xthal_restore_cp1(void *base); extern void xthal_restore_cp2(void *base); extern void xthal_restore_cp3(void *base); extern void xthal_restore_cp4(void *base); extern void xthal_restore_cp5(void *base); extern void xthal_restore_cp6(void *base); extern void xthal_restore_cp7(void *base); /* pointers to each of the functions above */ extern void* Xthal_cpregs_save_fn[XTHAL_MAX_CPS]; extern void* Xthal_cpregs_restore_fn[XTHAL_MAX_CPS]; /* similarly for non-windowed ABI (may be same or different) */ extern void* Xthal_cpregs_save_nw_fn[XTHAL_MAX_CPS]; extern void* Xthal_cpregs_restore_nw_fn[XTHAL_MAX_CPS]; /*extern void xthal_save_all_extra(void *base);*/ /*extern void xthal_restore_all_extra(void *base);*/ /* space for processor state */ extern const unsigned int Xthal_extra_size; extern const unsigned int Xthal_extra_align; extern const unsigned int Xthal_cpregs_size[XTHAL_MAX_CPS]; extern const unsigned int Xthal_cpregs_align[XTHAL_MAX_CPS]; extern const unsigned int Xthal_all_extra_size; extern const unsigned int Xthal_all_extra_align; /* coprocessor names */ extern const char * const Xthal_cp_names[XTHAL_MAX_CPS]; /* initialize the extra processor */ /*extern void xthal_init_extra(void);*/ /* initialize the TIE coprocessor */ /*extern void xthal_init_cp(int);*/ /* initialize the extra processor */ extern void xthal_init_mem_extra(void *); /* initialize the TIE coprocessor */ extern void xthal_init_mem_cp(void *, int); /* the number of TIE coprocessors contiguous from zero (for Tor2) */ extern const unsigned int Xthal_num_coprocessors; /* actual number of coprocessors */ extern const unsigned char Xthal_cp_num; /* index of highest numbered coprocessor, plus one */ extern const unsigned char Xthal_cp_max; /* index of highest allowed coprocessor number, per cfg, plus one */ /*extern const unsigned char Xthal_cp_maxcfg;*/ /* bitmask of which coprocessors are present */ extern const unsigned int Xthal_cp_mask; /* read & write extra state register */ /*extern int xthal_read_extra(void *base, unsigned reg, unsigned *value);*/ /*extern int xthal_write_extra(void *base, unsigned reg, unsigned value);*/ /* read & write a TIE coprocessor register */ /*extern int xthal_read_cpreg(void *base, int cp, unsigned reg, unsigned *value);*/ /*extern int xthal_write_cpreg(void *base, int cp, unsigned reg, unsigned value);*/ /* return coprocessor number based on register */ /*extern int xthal_which_cp(unsigned reg);*/ /*---------------------------------------------------------------------- Register Windows ----------------------------------------------------------------------*/ /* number of registers in register window */ extern const unsigned int Xthal_num_aregs; extern const unsigned char Xthal_num_aregs_log2; /*---------------------------------------------------------------------- Cache ----------------------------------------------------------------------*/ /* size of the cache lines in log2(bytes) */ extern const unsigned char Xthal_icache_linewidth; extern const unsigned char Xthal_dcache_linewidth; /* size of the cache lines in bytes (2^linewidth) */ extern const unsigned short Xthal_icache_linesize; extern const unsigned short Xthal_dcache_linesize; /* size of the caches in bytes (ways * 2^(linewidth + setwidth)) */ extern const unsigned int Xthal_icache_size; extern const unsigned int Xthal_dcache_size; /* cache features */ extern const unsigned char Xthal_dcache_is_writeback; /* invalidate the caches */ extern void xthal_icache_region_invalidate( void *addr, unsigned size ); extern void xthal_dcache_region_invalidate( void *addr, unsigned size ); extern void xthal_icache_line_invalidate(void *addr); extern void xthal_dcache_line_invalidate(void *addr); /* write dirty data back */ extern void xthal_dcache_region_writeback( void *addr, unsigned size ); extern void xthal_dcache_line_writeback(void *addr); /* write dirty data back and invalidate */ extern void xthal_dcache_region_writeback_inv( void *addr, unsigned size ); extern void xthal_dcache_line_writeback_inv(void *addr); /* sync icache and memory */ extern void xthal_icache_sync( void ); /* sync dcache and memory */ extern void xthal_dcache_sync( void ); /*---------------------------------------------------------------------- Debug ----------------------------------------------------------------------*/ /* 1 if debug option configured, 0 if not: */ extern const int Xthal_debug_configured; /* Set (plant) and remove software breakpoint, both synchronizing cache: */ extern unsigned int xthal_set_soft_break(void *addr); extern void xthal_remove_soft_break(void *addr, unsigned int); /*---------------------------------------------------------------------- Disassembler ----------------------------------------------------------------------*/ /* Max expected size of the return buffer for a disassembled instruction (hint only): */ #define XTHAL_DISASM_BUFSIZE 80 /* Disassembly option bits for selecting what to return: */ #define XTHAL_DISASM_OPT_ADDR 0x0001 /* display address */ #define XTHAL_DISASM_OPT_OPHEX 0x0002 /* display opcode bytes in hex */ #define XTHAL_DISASM_OPT_OPCODE 0x0004 /* display opcode name (mnemonic) */ #define XTHAL_DISASM_OPT_PARMS 0x0008 /* display parameters */ #define XTHAL_DISASM_OPT_ALL 0x0FFF /* display everything */ /* routine to get a string for the disassembled instruction */ extern int xthal_disassemble( unsigned char *instr_buf, void *tgt_addr, char *buffer, unsigned buflen, unsigned options ); /* routine to get the size of the next instruction. Returns 0 for illegal instruction */ extern int xthal_disassemble_size( unsigned char *instr_buf ); /*---------------------------------------------------------------------- Instruction/Data RAM/ROM Access ----------------------------------------------------------------------*/ extern void* xthal_memcpy(void *dst, const void *src, unsigned len); extern void* xthal_bcopy(const void *src, void *dst, unsigned len); /*---------------------------------------------------------------------- MP Synchronization ----------------------------------------------------------------------*/ extern int xthal_compare_and_set( int *addr, int test_val, int compare_val ); /*extern const char Xthal_have_s32c1i;*/ /*---------------------------------------------------------------------- Miscellaneous ----------------------------------------------------------------------*/ extern const unsigned int Xthal_release_major; extern const unsigned int Xthal_release_minor; extern const char * const Xthal_release_name; extern const char * const Xthal_release_internal; extern const unsigned char Xthal_memory_order; extern const unsigned char Xthal_have_windowed; extern const unsigned char Xthal_have_density; extern const unsigned char Xthal_have_booleans; extern const unsigned char Xthal_have_loops; extern const unsigned char Xthal_have_nsa; extern const unsigned char Xthal_have_minmax; extern const unsigned char Xthal_have_sext; extern const unsigned char Xthal_have_clamps; extern const unsigned char Xthal_have_mac16; extern const unsigned char Xthal_have_mul16; extern const unsigned char Xthal_have_fp; extern const unsigned char Xthal_have_speculation; extern const unsigned char Xthal_have_threadptr; extern const unsigned char Xthal_have_pif; extern const unsigned short Xthal_num_writebuffer_entries; extern const unsigned int Xthal_build_unique_id; /* Version info for hardware targeted by software upgrades: */ extern const unsigned int Xthal_hw_configid0; extern const unsigned int Xthal_hw_configid1; extern const unsigned int Xthal_hw_release_major; extern const unsigned int Xthal_hw_release_minor; extern const char * const Xthal_hw_release_name; extern const char * const Xthal_hw_release_internal; #ifdef __cplusplus } #endif #endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */ /**************************************************************************** Definitions Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code ****************************************************************************/ #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY /*---------------------------------------------------------------------- Constant Definitions (shared with assembly) ----------------------------------------------------------------------*/ /* * Architectural limits, independent of configuration. * Note that these are ISA-defined limits, not micro-architecture implementation * limits enforced by the Xtensa Processor Generator (which may be stricter than * these below). */ #define XTHAL_MAX_INTERRUPTS 32 /* max number of interrupts (0..31) */ #define XTHAL_MAX_INTLEVELS 16 /* max number of interrupt levels (0..15) */ /* (as of T1040, implementation limit is 7: 0..6) */ #define XTHAL_MAX_TIMERS 4 /* max number of timers (CCOMPARE0..CCOMPARE3) */ /* (as of T1040, implementation limit is 3: 0..2) */ /* Interrupt types: */ #define XTHAL_INTTYPE_UNCONFIGURED 0 #define XTHAL_INTTYPE_SOFTWARE 1 #define XTHAL_INTTYPE_EXTERN_EDGE 2 #define XTHAL_INTTYPE_EXTERN_LEVEL 3 #define XTHAL_INTTYPE_TIMER 4 #define XTHAL_INTTYPE_NMI 5 #define XTHAL_INTTYPE_WRITE_ERROR 6 #define XTHAL_MAX_INTTYPES 7 /* number of interrupt types */ /* Timer related: */ #define XTHAL_TIMER_UNCONFIGURED -1 /* Xthal_timer_interrupt[] value for non-existent timers */ #define XTHAL_TIMER_UNASSIGNED XTHAL_TIMER_UNCONFIGURED /* (for backwards compatibility only) */ /* Local Memory ECC/Parity: */ #define XTHAL_MEMEP_PARITY 1 #define XTHAL_MEMEP_ECC 2 /* Flags parameter to xthal_memep_inject_error(): */ #define XTHAL_MEMEP_F_LOCAL 0 /* local memory (default) */ #define XTHAL_MEMEP_F_DCACHE_DATA 4 /* data cache data */ #define XTHAL_MEMEP_F_DCACHE_TAG 5 /* data cache tag */ #define XTHAL_MEMEP_F_ICACHE_DATA 6 /* instruction cache data */ #define XTHAL_MEMEP_F_ICACHE_TAG 7 /* instruction cache tag */ #define XTHAL_MEMEP_F_CORRECTABLE 16 /* inject correctable error (default is non-corr.) */ /* Access Mode bits (tentative): */ /* bit abbr unit short_name PPC equ - Description */ #define XTHAL_AMB_EXCEPTION 0 /* 001 E EX fls: EXception none exception on any access (aka "illegal") */ #define XTHAL_AMB_HITCACHE 1 /* 002 C CH fls: use Cache on Hit ~(I CI) [or H HC] way from tag match; [or U UC] (ISA: same except Isolate case) */ #define XTHAL_AMB_ALLOCATE 2 /* 004 A AL fl?: ALlocate none [or F FI fill] refill cache on miss, way from LRU (ISA: Read/Write Miss Refill) */ #define XTHAL_AMB_WRITETHRU 3 /* 008 W WT --s: WriteThrough W WT store immediately to memory (ISA: same) */ #define XTHAL_AMB_ISOLATE 4 /* 010 I IS fls: ISolate none use cache regardless of hit-vs-miss, way from vaddr (ISA: use-cache-on-miss+hit) */ #define XTHAL_AMB_GUARD 5 /* 020 G GU ?l?: GUard G * non-speculative; spec/replay refs not permitted */ #if 0 #define XTHAL_AMB_COHERENT 6 /* 040 M MC ?ls: Mem/MP Coherent M on read, other CPU/bus-master may need to supply data; on write, maybe redirect to or flush other CPU dirty line; etc */ #define XTHAL_AMB_ORDERED x /* 000 O OR fls: ORdered G * mem accesses cannot be out of order */ #define XTHAL_AMB_FUSEWRITES x /* 000 F FW --s: FuseWrites none allow combining/merging multiple writes (to same datapath data unit) into one (implied by writeback) */ #define XTHAL_AMB_TRUSTED x /* 000 T TR ?l?: TRusted none memory will not bus error (if it does, handle as fatal imprecise interrupt) */ #define XTHAL_AMB_PREFETCH x /* 000 P PR fl?: PRefetch none on refill, read line+1 into prefetch buffers */ #define XTHAL_AMB_STREAM x /* 000 S ST ???: STreaming none access one of N stream buffers */ #endif /*0*/ #define XTHAL_AM_EXCEPTION (1< = bit is set * '-' = bit is clear * '.' = bit is irrelevant / don't care, as follows: * E=1 makes all others irrelevant * W,F relevant only for stores * "2345" * Indicates which Xtensa releases support the corresponding * access mode. Releases for each character column are: * 2 = prior to T1020.2: T1015 (V1.5), T1020.0, T1020.1 * 3 = T1020.2 and later: T1020.2+, T1030 * 4 = T1040 * 5 = T1050 (maybe), LX1, LX2, LX2.1 * 7 = LX2.2 * And the character column contents are: * = support by release(s) * "." = unsupported by release(s) * "?" = support unknown */ /* FOMGIWACE 23457 */ /* For instruction fetch: */ #define XTHAL_FAM_EXCEPTION 0x001 /* ........E 23457 exception */ #define XTHAL_FAM_ISOLATE 0x012 /* .---I.-C- ..... isolate */ #define XTHAL_FAM_BYPASS 0x000 /* .----.--- 23457 bypass */ #define XTHAL_FAM_NACACHED 0x002 /* .----.-C- ..... cached no-allocate (frozen) */ #define XTHAL_FAM_CACHED 0x006 /* .----.AC- 23457 cached */ /* For data load: */ #define XTHAL_LAM_EXCEPTION 0x001 /* ........E 23457 exception */ #define XTHAL_LAM_ISOLATE 0x012 /* .---I.-C- 23457 isolate */ #define XTHAL_LAM_BYPASS 0x000 /* .O---.--- 2.... bypass speculative */ #define XTHAL_LAM_BYPASSG 0x020 /* .O-G-.--- .3457 bypass guarded */ #define XTHAL_LAM_NACACHED 0x002 /* .O---.-C- 2.... cached no-allocate speculative */ #define XTHAL_LAM_NACACHEDG 0x022 /* .O-G-.-C- .3457 cached no-allocate guarded */ #define XTHAL_LAM_CACHED 0x006 /* .----.AC- 23457 cached speculative */ #define XTHAL_LAM_CACHEDG 0x026 /* .?-G-.AC- ..... cached guarded */ #define XTHAL_LAM_CACHEDM 0x046 /* .-M--.AC- ....7 cached MP-coherent (experimental) */ /* For data store: */ #define XTHAL_SAM_EXCEPTION 0x001 /* ........E 23457 exception */ #define XTHAL_SAM_ISOLATE 0x032 /* .--GI--C- 23457 isolate */ #define XTHAL_SAM_BYPASS 0x028 /* -O-G-W--- 23457 bypass */ /*efine XTHAL_SAM_BYPASSF 0x028*/ /* F--G-W--- ..... bypass write-combined */ #define XTHAL_SAM_WRITETHRU 0x02A /* -O-G-W-C- 23457 writethrough */ /*efine XTHAL_SAM_WRITETHRUF 0x02A*/ /* F--G-W-C- ..... writethrough write-combined */ #define XTHAL_SAM_WRITEALLOC 0x02E /* -O-G-WAC- ..... writethrough-allocate */ /*efine XTHAL_SAM_WRITEALLOCF 0x02E*/ /* F--G-WAC- ..... writethrough-allocate write-combined */ #define XTHAL_SAM_WRITEBACK 0x066 /* F-MG--AC- ...57 writeback (MP-coherent if configured) */ #if 0 /* Cache attribute encoding for CACHEATTR (per ISA): (Note: if this differs from ISA Ref Manual, ISA has precedence) Inst-fetches Loads Stores ------------- ------------ ------------- 0x0 FCA_EXCEPTION ?LCA_NACACHED_G* SCA_WRITETHRU "uncached" (cached no-allocate) 0x1 FCA_CACHED LCA_CACHED SCA_WRITETHRU cached 0x2 FCA_BYPASS LCA_BYPASS_G* SCA_BYPASS bypass 0x3 FCA_CACHED LCA_CACHED SCA_WRITEALLOCF write-allocate or LCA_EXCEPTION SCA_EXCEPTION (if unimplemented) 0x4 FCA_CACHED LCA_CACHED SCA_WRITEBACK write-back or LCA_EXCEPTION SCA_EXCEPTION (if unimplemented) 0x5..D FCA_EXCEPTION LCA_EXCEPTION SCA_EXCEPTION (reserved) 0xE FCA_EXCEPTION LCA_ISOLATE SCA_ISOLATE isolate 0xF FCA_EXCEPTION LCA_EXCEPTION SCA_EXCEPTION illegal * Prior to T1020.2?, guard feature not supported, this defaulted to speculative (no _G) */ #endif /*0*/ #if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__) #ifdef __cplusplus extern "C" { #endif /*---------------------------------------------------------------------- Register Windows ----------------------------------------------------------------------*/ /* This spill any live register windows (other than the caller's): * (NOTE: current implementation require privileged code, but * a user-callable implementation is possible.) */ extern void xthal_window_spill( void ); /*---------------------------------------------------------------------- Optional/Custom Processor State ----------------------------------------------------------------------*/ /* validate & invalidate the TIE register file */ extern void xthal_validate_cp(int); extern void xthal_invalidate_cp(int); /* read and write cpenable register */ extern void xthal_set_cpenable(unsigned); extern unsigned xthal_get_cpenable(void); /*---------------------------------------------------------------------- Interrupts ----------------------------------------------------------------------*/ /* the number of interrupt levels */ extern const unsigned char Xthal_num_intlevels; /* the number of interrupts */ extern const unsigned char Xthal_num_interrupts; /* mask for level of interrupts */ extern const unsigned int Xthal_intlevel_mask[XTHAL_MAX_INTLEVELS]; /* mask for level 0 to N interrupts */ extern const unsigned int Xthal_intlevel_andbelow_mask[XTHAL_MAX_INTLEVELS]; /* level of each interrupt */ extern const unsigned char Xthal_intlevel[XTHAL_MAX_INTERRUPTS]; /* type per interrupt */ extern const unsigned char Xthal_inttype[XTHAL_MAX_INTERRUPTS]; /* masks of each type of interrupt */ extern const unsigned int Xthal_inttype_mask[XTHAL_MAX_INTTYPES]; /* interrupt numbers assigned to each timer interrupt */ extern const int Xthal_timer_interrupt[XTHAL_MAX_TIMERS]; /* INTENABLE,INTERRUPT,INTSET,INTCLEAR register access functions: */ extern unsigned xthal_get_intenable( void ); extern void xthal_set_intenable( unsigned ); extern unsigned xthal_get_interrupt( void ); #define xthal_get_intread xthal_get_interrupt /* backward compatibility */ extern void xthal_set_intset( unsigned ); extern void xthal_set_intclear( unsigned ); /*---------------------------------------------------------------------- Debug ----------------------------------------------------------------------*/ /* Number of instruction and data break registers: */ extern const int Xthal_num_ibreak; extern const int Xthal_num_dbreak; /*---------------------------------------------------------------------- Core Counter ----------------------------------------------------------------------*/ /* counter info */ extern const unsigned char Xthal_have_ccount; /* set if CCOUNT register present */ extern const unsigned char Xthal_num_ccompare; /* number of CCOMPAREn registers */ /* get CCOUNT register (if not present return 0) */ extern unsigned xthal_get_ccount(void); /* set and get CCOMPAREn registers (if not present, get returns 0) */ extern void xthal_set_ccompare(int, unsigned); extern unsigned xthal_get_ccompare(int); /*---------------------------------------------------------------------- Miscellaneous ----------------------------------------------------------------------*/ extern const unsigned char Xthal_have_prid; extern const unsigned char Xthal_have_exceptions; extern const unsigned char Xthal_xea_version; extern const unsigned char Xthal_have_interrupts; extern const unsigned char Xthal_have_highlevel_interrupts; extern const unsigned char Xthal_have_nmi; extern unsigned xthal_get_prid( void ); /*---------------------------------------------------------------------- Virtual interrupt prioritization (DEPRECATED) ----------------------------------------------------------------------*/ /* Convert between interrupt levels (as per PS.INTLEVEL) and virtual interrupt priorities: */ extern unsigned xthal_vpri_to_intlevel(unsigned vpri); extern unsigned xthal_intlevel_to_vpri(unsigned intlevel); /* Enables/disables given set (mask) of interrupts; returns previous enabled-mask of all ints: */ extern unsigned xthal_int_enable(unsigned); extern unsigned xthal_int_disable(unsigned); /* Set/get virtual priority of an interrupt: */ extern int xthal_set_int_vpri(int intnum, int vpri); extern int xthal_get_int_vpri(int intnum); /* Set/get interrupt lockout level for exclusive access to virtual priority data structures: */ extern void xthal_set_vpri_locklevel(unsigned intlevel); extern unsigned xthal_get_vpri_locklevel(void); /* Set/get current virtual interrupt priority: */ extern unsigned xthal_set_vpri(unsigned vpri); extern unsigned xthal_get_vpri(void); extern unsigned xthal_set_vpri_intlevel(unsigned intlevel); extern unsigned xthal_set_vpri_lock(void); /*---------------------------------------------------------------------- Generic Interrupt Trampolining Support (DEPRECATED) ----------------------------------------------------------------------*/ typedef void (XtHalVoidFunc)(void); /* Bitmask of interrupts currently trampolining down: */ extern unsigned Xthal_tram_pending; /* * Bitmask of which interrupts currently trampolining down synchronously are * actually enabled; this bitmask is necessary because INTENABLE cannot hold * that state (sync-trampolining interrupts must be kept disabled while * trampolining); in the current implementation, any bit set here is not set * in INTENABLE, and vice-versa; once a sync-trampoline is handled (at level * one), its enable bit must be moved from here to INTENABLE: */ extern unsigned Xthal_tram_enabled; /* Bitmask of interrupts configured for sync trampolining: */ extern unsigned Xthal_tram_sync; /* Trampoline support functions: */ extern unsigned xthal_tram_pending_to_service( void ); extern void xthal_tram_done( unsigned serviced_mask ); extern int xthal_tram_set_sync( int intnum, int sync ); extern XtHalVoidFunc* xthal_set_tram_trigger_func( XtHalVoidFunc *trigger_fn ); /*---------------------------------------------------------------------- Internal Memories ----------------------------------------------------------------------*/ extern const unsigned char Xthal_num_instrom; extern const unsigned char Xthal_num_instram; extern const unsigned char Xthal_num_datarom; extern const unsigned char Xthal_num_dataram; extern const unsigned char Xthal_num_xlmi; /* Each of the following arrays contains at least one entry, * or as many entries as needed if more than one: */ extern const unsigned int Xthal_instrom_vaddr[]; extern const unsigned int Xthal_instrom_paddr[]; extern const unsigned int Xthal_instrom_size []; extern const unsigned int Xthal_instram_vaddr[]; extern const unsigned int Xthal_instram_paddr[]; extern const unsigned int Xthal_instram_size []; extern const unsigned int Xthal_datarom_vaddr[]; extern const unsigned int Xthal_datarom_paddr[]; extern const unsigned int Xthal_datarom_size []; extern const unsigned int Xthal_dataram_vaddr[]; extern const unsigned int Xthal_dataram_paddr[]; extern const unsigned int Xthal_dataram_size []; extern const unsigned int Xthal_xlmi_vaddr[]; extern const unsigned int Xthal_xlmi_paddr[]; extern const unsigned int Xthal_xlmi_size []; /*---------------------------------------------------------------------- Cache ----------------------------------------------------------------------*/ /* number of cache sets in log2(lines per way) */ extern const unsigned char Xthal_icache_setwidth; extern const unsigned char Xthal_dcache_setwidth; /* cache set associativity (number of ways) */ extern const unsigned int Xthal_icache_ways; extern const unsigned int Xthal_dcache_ways; /* cache features */ extern const unsigned char Xthal_icache_line_lockable; extern const unsigned char Xthal_dcache_line_lockable; /* cache attribute register control (used by other HAL routines) */ extern unsigned xthal_get_cacheattr( void ); extern unsigned xthal_get_icacheattr( void ); extern unsigned xthal_get_dcacheattr( void ); extern void xthal_set_cacheattr( unsigned ); extern void xthal_set_icacheattr( unsigned ); extern void xthal_set_dcacheattr( unsigned ); /* set cache attribute (access modes) for a range of memory */ extern int xthal_set_region_attribute( void *addr, unsigned size, unsigned cattr, unsigned flags ); /* Bits of flags parameter to xthal_set_region_attribute(): */ #define XTHAL_CAFLAG_EXPAND 0x000100 /* only expand allowed access to range, don't reduce it */ #define XTHAL_CAFLAG_EXACT 0x000200 /* return error if can't apply change to exact range specified */ #define XTHAL_CAFLAG_NO_PARTIAL 0x000400 /* don't apply change to regions partially covered by range */ #define XTHAL_CAFLAG_NO_AUTO_WB 0x000800 /* don't writeback data after leaving writeback attribute */ #define XTHAL_CAFLAG_NO_AUTO_INV 0x001000 /* don't invalidate after disabling cache (entering bypass) */ /* enable caches */ extern void xthal_icache_enable( void ); /* DEPRECATED */ extern void xthal_dcache_enable( void ); /* DEPRECATED */ /* disable caches */ extern void xthal_icache_disable( void ); /* DEPRECATED */ extern void xthal_dcache_disable( void ); /* DEPRECATED */ /* invalidate the caches */ extern void xthal_icache_all_invalidate( void ); extern void xthal_dcache_all_invalidate( void ); /* write dirty data back */ extern void xthal_dcache_all_writeback( void ); /* write dirty data back and invalidate */ extern void xthal_dcache_all_writeback_inv( void ); /* prefetch and lock specified memory range into cache */ extern void xthal_icache_region_lock( void *addr, unsigned size ); extern void xthal_dcache_region_lock( void *addr, unsigned size ); extern void xthal_icache_line_lock(void *addr); extern void xthal_dcache_line_lock(void *addr); /* unlock from cache */ extern void xthal_icache_all_unlock( void ); extern void xthal_dcache_all_unlock( void ); extern void xthal_icache_region_unlock( void *addr, unsigned size ); extern void xthal_dcache_region_unlock( void *addr, unsigned size ); extern void xthal_icache_line_unlock(void *addr); extern void xthal_dcache_line_unlock(void *addr); /*---------------------------------------------------------------------- Local Memory ECC/Parity ----------------------------------------------------------------------*/ /* Inject memory errors; flags is bit combination of XTHAL_MEMEP_F_xxx: */ extern void xthal_memep_inject_error(void *addr, int size, int flags); /*---------------------------------------------------------------------- Memory Management Unit ----------------------------------------------------------------------*/ extern const unsigned char Xthal_have_spanning_way; extern const unsigned char Xthal_have_identity_map; extern const unsigned char Xthal_have_mimic_cacheattr; extern const unsigned char Xthal_have_xlt_cacheattr; extern const unsigned char Xthal_have_cacheattr; extern const unsigned char Xthal_have_tlbs; extern const unsigned char Xthal_mmu_asid_bits; /* 0 .. 8 */ extern const unsigned char Xthal_mmu_asid_kernel; extern const unsigned char Xthal_mmu_rings; /* 1 .. 4 (perhaps 0 if no MMU and/or no protection?) */ extern const unsigned char Xthal_mmu_ring_bits; extern const unsigned char Xthal_mmu_sr_bits; extern const unsigned char Xthal_mmu_ca_bits; extern const unsigned int Xthal_mmu_max_pte_page_size; extern const unsigned int Xthal_mmu_min_pte_page_size; extern const unsigned char Xthal_itlb_way_bits; extern const unsigned char Xthal_itlb_ways; extern const unsigned char Xthal_itlb_arf_ways; extern const unsigned char Xthal_dtlb_way_bits; extern const unsigned char Xthal_dtlb_ways; extern const unsigned char Xthal_dtlb_arf_ways; /* Convert between virtual and physical addresses (through static maps only): */ /*** WARNING: these two functions may go away in a future release; don't depend on them! ***/ extern int xthal_static_v2p( unsigned vaddr, unsigned *paddrp ); extern int xthal_static_p2v( unsigned paddr, unsigned *vaddrp, unsigned cached ); #ifdef __cplusplus } #endif #endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */ #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ /**************************************************************************** EXPERIMENTAL and DEPRECATED Definitions ****************************************************************************/ #if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__) #ifdef __cplusplus extern "C" { #endif #ifdef INCLUDE_DEPRECATED_HAL_CODE extern const unsigned char Xthal_have_old_exc_arch; extern const unsigned char Xthal_have_mmu; extern const unsigned int Xthal_num_regs; extern const unsigned char Xthal_num_iroms; extern const unsigned char Xthal_num_irams; extern const unsigned char Xthal_num_droms; extern const unsigned char Xthal_num_drams; extern const unsigned int Xthal_configid0; extern const unsigned int Xthal_configid1; #endif #ifdef INCLUDE_DEPRECATED_HAL_DEBUG_CODE #define XTHAL_24_BIT_BREAK 0x80000000 #define XTHAL_16_BIT_BREAK 0x40000000 extern const unsigned short Xthal_ill_inst_16[16]; #define XTHAL_DEST_REG 0xf0000000 /* Mask for destination register */ #define XTHAL_DEST_REG_INST 0x08000000 /* Branch address is in register */ #define XTHAL_DEST_REL_INST 0x04000000 /* Branch address is relative */ #define XTHAL_RFW_INST 0x00000800 #define XTHAL_RFUE_INST 0x00000400 #define XTHAL_RFI_INST 0x00000200 #define XTHAL_RFE_INST 0x00000100 #define XTHAL_RET_INST 0x00000080 #define XTHAL_BREAK_INST 0x00000040 #define XTHAL_SYSCALL_INST 0x00000020 #define XTHAL_LOOP_END 0x00000010 /* Not set by xthal_inst_type */ #define XTHAL_JUMP_INST 0x00000008 /* Call or jump instruction */ #define XTHAL_BRANCH_INST 0x00000004 /* Branch instruction */ #define XTHAL_24_BIT_INST 0x00000002 #define XTHAL_16_BIT_INST 0x00000001 typedef struct xthal_state { unsigned pc; unsigned ar[16]; unsigned lbeg; unsigned lend; unsigned lcount; unsigned extra_ptr; unsigned cpregs_ptr[XTHAL_MAX_CPS]; } XTHAL_STATE; extern unsigned int xthal_inst_type(void *addr); extern unsigned int xthal_branch_addr(void *addr); extern unsigned int xthal_get_npc(XTHAL_STATE *user_state); #endif /* INCLUDE_DEPRECATED_HAL_DEBUG_CODE */ #ifdef __cplusplus } #endif #endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */ #endif /*XTENSA_HAL_H*/ xtruntime.h000066400000000000000000000174071321570333100361320ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/xtensa-elf/xtensa/* * Copyright (c) 2013 Tensilica Inc. * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sublicense, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef XTRUNTIME_H #define XTRUNTIME_H #include #include #ifndef XTSTR #define _XTSTR(x) # x #define XTSTR(x) _XTSTR(x) #endif #define _xtos_set_execption_handler _xtos_set_exception_handler /* backward compatibility */ #define _xtos_set_saved_intenable _xtos_ints_on /* backward compatibility */ #define _xtos_clear_saved_intenable _xtos_ints_off /* backward compatibility */ #if !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__) #ifdef __cplusplus extern "C" { #endif /*typedef void (_xtos_timerdelta_func)(int);*/ #ifdef __cplusplus typedef void (_xtos_handler_func)(...); #else typedef void (_xtos_handler_func)(); #endif typedef _xtos_handler_func *_xtos_handler; /* * unsigned XTOS_SET_INTLEVEL(int intlevel); * This macro sets the current interrupt level. * The 'intlevel' parameter must be a constant. * This macro returns a 32-bit value that must be passed to * XTOS_RESTORE_INTLEVEL() to restore the previous interrupt level. * XTOS_RESTORE_JUST_INTLEVEL() also does this, but in XEA2 configs * it restores only PS.INTLEVEL rather than the entire PS register * and thus is slower. */ #if !XCHAL_HAVE_INTERRUPTS # define XTOS_SET_INTLEVEL(intlevel) # define XTOS_SET_MIN_INTLEVEL(intlevel) # define XTOS_RESTORE_INTLEVEL(restoreval) # define XTOS_RESTORE_JUST_INTLEVEL(restoreval) #elif XCHAL_HAVE_XEA2 /* In XEA2, we can simply safely set PS.INTLEVEL directly: */ /* NOTE: these asm macros don't modify memory, but they are marked * as such to act as memory access barriers to the compiler because * these macros are sometimes used to delineate critical sections; * function calls are natural barriers (the compiler does not know * whether a function modifies memory) unless declared to be inlined. */ # define XTOS_SET_INTLEVEL(intlevel) ({ unsigned __tmp; \ __asm__ __volatile__( "rsil %0, " XTSTR(intlevel) "\n" \ : "=a" (__tmp) : : "memory" ); \ __tmp;}) # define XTOS_SET_MIN_INTLEVEL(intlevel) ({ unsigned __tmp, __tmp2, __tmp3; \ __asm__ __volatile__( "rsr %0, " XTSTR(PS) "\n" /* get old (current) PS.INTLEVEL */ \ "movi %2, " XTSTR(intlevel) "\n" \ "extui %1, %0, 0, 4\n" /* keep only INTLEVEL bits of parameter */ \ "blt %2, %1, 1f\n" \ "rsil %0, " XTSTR(intlevel) "\n" \ "1:\n" \ : "=a" (__tmp), "=&a" (__tmp2), "=&a" (__tmp3) : : "memory" ); \ __tmp;}) # define XTOS_RESTORE_INTLEVEL(restoreval) do{ unsigned __tmp = (restoreval); \ __asm__ __volatile__( "wsr %0, " XTSTR(PS) " ; rsync\n" \ : : "a" (__tmp) : "memory" ); \ }while(0) # define XTOS_RESTORE_JUST_INTLEVEL(restoreval) _xtos_set_intlevel(restoreval) #else /* In XEA1, we have to rely on INTENABLE register virtualization: */ extern unsigned _xtos_set_vpri( unsigned vpri ); extern unsigned _xtos_vpri_enabled; /* current virtual priority */ # define XTOS_SET_INTLEVEL(intlevel) _xtos_set_vpri(~XCHAL_INTLEVEL_ANDBELOW_MASK(intlevel)) # define XTOS_SET_MIN_INTLEVEL(intlevel) _xtos_set_vpri(_xtos_vpri_enabled & ~XCHAL_INTLEVEL_ANDBELOW_MASK(intlevel)) # define XTOS_RESTORE_INTLEVEL(restoreval) _xtos_set_vpri(restoreval) # define XTOS_RESTORE_JUST_INTLEVEL(restoreval) _xtos_set_vpri(restoreval) #endif /* * The following macros build upon the above. They are generally used * instead of invoking the SET_INTLEVEL and SET_MIN_INTLEVEL macros directly. * They all return a value that can be used with XTOS_RESTORE_INTLEVEL() * or _xtos_restore_intlevel() or _xtos_restore_just_intlevel() to restore * the effective interrupt level to what it was before the macro was invoked. * In XEA2, the DISABLE macros are much faster than the MASK macros * (in all configs, DISABLE sets the effective interrupt level, whereas MASK * makes ensures the effective interrupt level is at least the level given * without lowering it; in XEA2 with INTENABLE virtualization, these macros * affect PS.INTLEVEL only, not the virtual priority, so DISABLE has partial * MASK semantics). * * A typical critical section sequence might be: * unsigned rval = XTOS_DISABLE_EXCM_INTERRUPTS; * ... critical section ... * XTOS_RESTORE_INTLEVEL(rval); */ /* Enable all interrupts (those activated with _xtos_ints_on()): */ #define XTOS_ENABLE_INTERRUPTS XTOS_SET_INTLEVEL(0) /* Disable low priority level interrupts (they can interact with the OS): */ #define XTOS_DISABLE_LOWPRI_INTERRUPTS XTOS_SET_INTLEVEL(XCHAL_NUM_LOWPRI_LEVELS) #define XTOS_MASK_LOWPRI_INTERRUPTS XTOS_SET_MIN_INTLEVEL(XCHAL_NUM_LOWPRI_LEVELS) /* Disable interrupts that can interact with the OS: */ #define XTOS_DISABLE_EXCM_INTERRUPTS XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL) #define XTOS_MASK_EXCM_INTERRUPTS XTOS_SET_MIN_INTLEVEL(XCHAL_EXCM_LEVEL) #if 0 /* XTOS_LOCK_LEVEL is not exported to applications */ /* Disable interrupts that can interact with the OS, or manipulate virtual INTENABLE: */ #define XTOS_DISABLE_LOCK_INTERRUPTS XTOS_SET_INTLEVEL(XTOS_LOCK_LEVEL) #define XTOS_MASK_LOCK_INTERRUPTS XTOS_SET_MIN_INTLEVEL(XTOS_LOCK_LEVEL) #endif /* Disable ALL interrupts (not for common use, particularly if one's processor * configuration has high-level interrupts and one cares about their latency): */ #define XTOS_DISABLE_ALL_INTERRUPTS XTOS_SET_INTLEVEL(15) extern unsigned int _xtos_ints_off( unsigned int mask ); extern unsigned int _xtos_ints_on( unsigned int mask ); extern unsigned _xtos_set_intlevel( int intlevel ); extern unsigned _xtos_set_min_intlevel( int intlevel ); extern unsigned _xtos_restore_intlevel( unsigned restoreval ); extern unsigned _xtos_restore_just_intlevel( unsigned restoreval ); extern _xtos_handler _xtos_set_interrupt_handler( int n, _xtos_handler f ); extern _xtos_handler _xtos_set_interrupt_handler_arg( int n, _xtos_handler f, void *arg ); extern _xtos_handler _xtos_set_exception_handler( int n, _xtos_handler f ); extern void _xtos_memep_initrams( void ); extern void _xtos_memep_enable( int flags ); /* Deprecated (but kept because they were documented): */ extern unsigned int _xtos_read_ints( void ); /* use xthal_get_interrupt() instead */ extern void _xtos_clear_ints( unsigned int mask ); /* use xthal_set_intclear() instead */ #if XCHAL_NUM_CONTEXTS > 1 extern unsigned _xtos_init_context(int context_num, int stack_size, _xtos_handler_func *start_func, int arg1); #endif /* Deprecated: */ #if XCHAL_NUM_TIMERS > 0 extern void _xtos_timer_0_delta( int cycles ); #endif #if XCHAL_NUM_TIMERS > 1 extern void _xtos_timer_1_delta( int cycles ); #endif #if XCHAL_NUM_TIMERS > 2 extern void _xtos_timer_2_delta( int cycles ); #endif #if XCHAL_NUM_TIMERS > 3 extern void _xtos_timer_3_delta( int cycles ); #endif #ifdef __cplusplus } #endif #endif /* !_ASMLANGUAGE && !__ASSEMBLER__ */ #endif /* XTRUNTIME_H */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/xtensa/000077500000000000000000000000001321570333100317225ustar00rootroot00000000000000config/000077500000000000000000000000001321570333100331105ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/xtensacore-isa.h000066400000000000000000000446701321570333100347760ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/xtensa/config/* * Copyright (c) 2013 Tensilica Inc. * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sublicense, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /* * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa * processor CORE configuration * * See , which includes this file, for more details. */ #ifndef _XTENSA_CORE_CONFIGURATION_H #define _XTENSA_CORE_CONFIGURATION_H /**************************************************************************** Parameters Useful for Any Code, USER or PRIVILEGED ****************************************************************************/ /* * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is * configured, and a value of 0 otherwise. These macros are always defined. */ /*---------------------------------------------------------------------- ISA ----------------------------------------------------------------------*/ #define XCHAL_HAVE_BE 1 /* big-endian byte ordering */ #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ #define XCHAL_NUM_AREGS 32 /* num of physical addr regs */ #define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */ #define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */ #define XCHAL_HAVE_DEBUG 1 /* debug option */ #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ #define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ #define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ #define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ #define XCHAL_HAVE_CLAMPS 0 /* CLAMPS instruction */ #define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ #define XCHAL_HAVE_MUL32 1 /* MULL instruction */ #define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */ #define XCHAL_HAVE_DIV32 0 /* QUOS/QUOU/REMS/REMU instructions */ #define XCHAL_HAVE_L32R 1 /* L32R instruction */ #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */ #define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ #define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ #define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ #define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ #define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ #define XCHAL_HAVE_ABS 1 /* ABS instruction */ /*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ /*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ #define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ #define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ #define XCHAL_HAVE_SPECULATION 0 /* speculation */ #define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ #define XCHAL_NUM_CONTEXTS 1 /* */ #define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */ #define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ #define XCHAL_HAVE_PRID 1 /* processor ID register */ #define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ #define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */ #define XCHAL_HAVE_CP 0 /* CPENABLE reg (coprocessor) */ #define XCHAL_CP_MAXCFG 0 /* max allowed cp id plus one */ #define XCHAL_HAVE_MAC16 0 /* MAC16 package */ #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ #define XCHAL_HAVE_FP 0 /* floating point pkg */ #define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ #define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ #define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ /*---------------------------------------------------------------------- MISC ----------------------------------------------------------------------*/ #define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */ #define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */ #define XCHAL_DATA_WIDTH 4 /* data width in bytes */ /* In T1050, applies to selected core load and store instructions (see ISA): */ #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ #define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ #define XCHAL_CORE_ID "Magpie_P0" /* alphanum core name (CoreID) set in the Xtensa Processor Generator */ #define XCHAL_BUILD_UNIQUE_ID 0x0002230F /* 22-bit sw build ID */ /* * These definitions describe the hardware targeted by this software. */ #define XCHAL_HW_CONFIGID0 0xC280DBFF /* ConfigID hi 32 bits*/ #define XCHAL_HW_CONFIGID1 0x0D02230F /* ConfigID lo 32 bits*/ #define XCHAL_HW_VERSION_NAME "LX2.1.0" /* full version name */ #define XCHAL_HW_VERSION_MAJOR 2210 /* major ver# of targeted hw */ #define XCHAL_HW_VERSION_MINOR 0 /* minor ver# of targeted hw */ #define XCHAL_HW_VERSION 221000 /* major*100+minor */ #define XCHAL_HW_REL_LX2 1 #define XCHAL_HW_REL_LX2_1 1 #define XCHAL_HW_REL_LX2_1_0 1 #define XCHAL_HW_CONFIGID_RELIABLE 1 /* If software targets a *range* of hardware versions, these are the bounds: */ #define XCHAL_HW_MIN_VERSION_MAJOR 2210 /* major v of earliest tgt hw */ #define XCHAL_HW_MIN_VERSION_MINOR 0 /* minor v of earliest tgt hw */ #define XCHAL_HW_MIN_VERSION 221000 /* earliest targeted hw */ #define XCHAL_HW_MAX_VERSION_MAJOR 2210 /* major v of latest tgt hw */ #define XCHAL_HW_MAX_VERSION_MINOR 0 /* minor v of latest tgt hw */ #define XCHAL_HW_MAX_VERSION 221000 /* latest targeted hw */ /*---------------------------------------------------------------------- CACHE ----------------------------------------------------------------------*/ #define XCHAL_ICACHE_LINESIZE 16 /* I-cache line size in bytes */ #define XCHAL_DCACHE_LINESIZE 16 /* D-cache line size in bytes */ #define XCHAL_ICACHE_LINEWIDTH 4 /* log2(I line size in bytes) */ #define XCHAL_DCACHE_LINEWIDTH 4 /* log2(D line size in bytes) */ #define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */ #define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */ #define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */ /**************************************************************************** Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code ****************************************************************************/ #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY /*---------------------------------------------------------------------- CACHE ----------------------------------------------------------------------*/ #define XCHAL_HAVE_PIF 1 /* any outbound PIF present */ /* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ /* Number of cache sets in log2(lines per way): */ #define XCHAL_ICACHE_SETWIDTH 0 #define XCHAL_DCACHE_SETWIDTH 0 /* Cache set associativity (number of ways): */ #define XCHAL_ICACHE_WAYS 1 #define XCHAL_DCACHE_WAYS 1 /* Cache features: */ #define XCHAL_ICACHE_LINE_LOCKABLE 0 #define XCHAL_DCACHE_LINE_LOCKABLE 0 #define XCHAL_ICACHE_ECC_PARITY 0 #define XCHAL_DCACHE_ECC_PARITY 0 /* Number of encoded cache attr bits (see for decoded bits): */ #define XCHAL_CA_BITS 4 /*---------------------------------------------------------------------- INTERNAL I/D RAM/ROMs and XLMI ----------------------------------------------------------------------*/ #define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ #define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */ #define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ #define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */ #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ #define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ /* Instruction RAM 0: */ #define XCHAL_INSTRAM0_VADDR 0x00800000 #define XCHAL_INSTRAM0_PADDR 0x00800000 #define XCHAL_INSTRAM0_SIZE 4194304 #define XCHAL_INSTRAM0_ECC_PARITY 0 /* Data RAM 0: */ #define XCHAL_DATARAM0_VADDR 0x00400000 #define XCHAL_DATARAM0_PADDR 0x00400000 #define XCHAL_DATARAM0_SIZE 4194304 #define XCHAL_DATARAM0_ECC_PARITY 0 /*---------------------------------------------------------------------- INTERRUPTS and TIMERS ----------------------------------------------------------------------*/ #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ #define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ #define XCHAL_NUM_TIMERS 1 /* number of CCOMPAREn regs */ #define XCHAL_NUM_INTERRUPTS 19 /* number of interrupts */ #define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ #define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */ #define XCHAL_NUM_INTLEVELS 4 /* number of interrupt levels (not including level zero) */ #define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ /* Masks of interrupts at each interrupt level: */ #define XCHAL_INTLEVEL1_MASK 0x00000001 #define XCHAL_INTLEVEL2_MASK 0x00007FFE #define XCHAL_INTLEVEL3_MASK 0x00038000 #define XCHAL_INTLEVEL4_MASK 0x00000000 #define XCHAL_INTLEVEL5_MASK 0x00040000 #define XCHAL_INTLEVEL6_MASK 0x00000000 #define XCHAL_INTLEVEL7_MASK 0x00000000 /* Masks of interrupts at each range 1..n of interrupt levels: */ #define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x00000001 #define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x00007FFF #define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x0003FFFF #define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x0003FFFF #define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x0007FFFF #define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x0007FFFF #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x0007FFFF /* Level of each interrupt: */ #define XCHAL_INT0_LEVEL 1 #define XCHAL_INT1_LEVEL 2 #define XCHAL_INT2_LEVEL 2 #define XCHAL_INT3_LEVEL 2 #define XCHAL_INT4_LEVEL 2 #define XCHAL_INT5_LEVEL 2 #define XCHAL_INT6_LEVEL 2 #define XCHAL_INT7_LEVEL 2 #define XCHAL_INT8_LEVEL 2 #define XCHAL_INT9_LEVEL 2 #define XCHAL_INT10_LEVEL 2 #define XCHAL_INT11_LEVEL 2 #define XCHAL_INT12_LEVEL 2 #define XCHAL_INT13_LEVEL 2 #define XCHAL_INT14_LEVEL 2 #define XCHAL_INT15_LEVEL 3 #define XCHAL_INT16_LEVEL 3 #define XCHAL_INT17_LEVEL 3 #define XCHAL_INT18_LEVEL 5 #define XCHAL_DEBUGLEVEL 4 /* debug interrupt level */ #define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ #define XCHAL_NMILEVEL 5 /* NMI "level" (for use with EXCSAVE/EPS/EPC_n, RFI n) */ /* Type of each interrupt: */ #define XCHAL_INT0_TYPE XTHAL_INTTYPE_SOFTWARE #define XCHAL_INT1_TYPE XTHAL_INTTYPE_TIMER #define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT7_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT11_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT14_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT18_TYPE XTHAL_INTTYPE_NMI /* Masks of interrupts for each type of interrupt: */ #define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFF80000 #define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000001 #define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000000 #define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0003FFFC #define XCHAL_INTTYPE_MASK_TIMER 0x00000002 #define XCHAL_INTTYPE_MASK_NMI 0x00040000 #define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 /* Interrupt numbers assigned to specific interrupt sources: */ #define XCHAL_TIMER0_INTERRUPT 1 /* CCOMPARE0 */ #define XCHAL_TIMER1_INTERRUPT XTHAL_TIMER_UNCONFIGURED #define XCHAL_TIMER2_INTERRUPT XTHAL_TIMER_UNCONFIGURED #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED #define XCHAL_NMI_INTERRUPT 18 /* non-maskable interrupt */ /* Interrupt numbers for levels at which only one interrupt is configured: */ #define XCHAL_INTLEVEL1_NUM 0 #define XCHAL_INTLEVEL5_NUM 18 /* (There are many interrupts each at level(s) 2, 3.) */ /* * External interrupt vectors/levels. * These macros describe how Xtensa processor interrupt numbers * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) * map to external BInterrupt pins, for those interrupts * configured as external (level-triggered, edge-triggered, or NMI). * See the Xtensa processor databook for more details. */ /* Core interrupt numbers mapped to each EXTERNAL interrupt number: */ #define XCHAL_EXTINT0_NUM 2 /* (intlevel 2) */ #define XCHAL_EXTINT1_NUM 3 /* (intlevel 2) */ #define XCHAL_EXTINT2_NUM 4 /* (intlevel 2) */ #define XCHAL_EXTINT3_NUM 5 /* (intlevel 2) */ #define XCHAL_EXTINT4_NUM 6 /* (intlevel 2) */ #define XCHAL_EXTINT5_NUM 7 /* (intlevel 2) */ #define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */ #define XCHAL_EXTINT7_NUM 9 /* (intlevel 2) */ #define XCHAL_EXTINT8_NUM 10 /* (intlevel 2) */ #define XCHAL_EXTINT9_NUM 11 /* (intlevel 2) */ #define XCHAL_EXTINT10_NUM 12 /* (intlevel 2) */ #define XCHAL_EXTINT11_NUM 13 /* (intlevel 2) */ #define XCHAL_EXTINT12_NUM 14 /* (intlevel 2) */ #define XCHAL_EXTINT13_NUM 15 /* (intlevel 3) */ #define XCHAL_EXTINT14_NUM 16 /* (intlevel 3) */ #define XCHAL_EXTINT15_NUM 17 /* (intlevel 3) */ #define XCHAL_EXTINT16_NUM 18 /* (intlevel 5) */ /*---------------------------------------------------------------------- EXCEPTIONS and VECTORS ----------------------------------------------------------------------*/ #define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture number: 1 == XEA1 (old) 2 == XEA2 (new) 0 == XEAX (extern) */ #define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ #define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ #define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ #define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ #define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ #define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ #define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ #define XCHAL_VECBASE_RESET_VADDR 0x008E0800 /* VECBASE reset value */ #define XCHAL_VECBASE_RESET_PADDR 0x008E0800 #define XCHAL_RESET_VECBASE_OVERLAP 0 #define XCHAL_RESET_VECTOR0_VADDR 0x008E0000 #define XCHAL_RESET_VECTOR0_PADDR 0x008E0000 #define XCHAL_RESET_VECTOR1_VADDR 0x0F000000 #define XCHAL_RESET_VECTOR1_PADDR 0x0F000000 #define XCHAL_RESET_VECTOR_VADDR 0x008E0000 #define XCHAL_RESET_VECTOR_PADDR 0x008E0000 #define XCHAL_USER_VECOFS 0x00000620 #define XCHAL_USER_VECTOR_VADDR 0x008E0E20 #define XCHAL_USER_VECTOR_PADDR 0x008E0E20 #define XCHAL_KERNEL_VECOFS 0x00000540 #define XCHAL_KERNEL_VECTOR_VADDR 0x008E0D40 #define XCHAL_KERNEL_VECTOR_PADDR 0x008E0D40 #define XCHAL_DOUBLEEXC_VECOFS 0x00000720 #define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x008E0F20 #define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x008E0F20 #define XCHAL_WINDOW_OF4_VECOFS 0x00000000 #define XCHAL_WINDOW_UF4_VECOFS 0x00000040 #define XCHAL_WINDOW_OF8_VECOFS 0x00000080 #define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 #define XCHAL_WINDOW_OF12_VECOFS 0x00000100 #define XCHAL_WINDOW_UF12_VECOFS 0x00000140 #define XCHAL_WINDOW_VECTORS_VADDR 0x008E0800 #define XCHAL_WINDOW_VECTORS_PADDR 0x008E0800 #define XCHAL_INTLEVEL2_VECOFS 0x00000220 #define XCHAL_INTLEVEL2_VECTOR_VADDR 0x008E0A20 #define XCHAL_INTLEVEL2_VECTOR_PADDR 0x008E0A20 #define XCHAL_INTLEVEL3_VECOFS 0x00000320 #define XCHAL_INTLEVEL3_VECTOR_VADDR 0x008E0B20 #define XCHAL_INTLEVEL3_VECTOR_PADDR 0x008E0B20 #define XCHAL_INTLEVEL4_VECOFS 0x00000420 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0x008E0C20 #define XCHAL_INTLEVEL4_VECTOR_PADDR 0x008E0C20 #define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL4_VECOFS #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR #define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL4_VECTOR_PADDR #define XCHAL_NMI_VECOFS 0x000004E4 #define XCHAL_NMI_VECTOR_VADDR 0x008E0CE4 #define XCHAL_NMI_VECTOR_PADDR 0x008E0CE4 #define XCHAL_INTLEVEL5_VECOFS XCHAL_NMI_VECOFS #define XCHAL_INTLEVEL5_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR #define XCHAL_INTLEVEL5_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR /*---------------------------------------------------------------------- DEBUG ----------------------------------------------------------------------*/ #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ #define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ #define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */ /*---------------------------------------------------------------------- MMU ----------------------------------------------------------------------*/ /* See core-matmap.h header file for more details. */ #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ #define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ #define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ #define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ #define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table [autorefill] and protection) usable for an MMU-based OS */ /* If none of the above last 4 are set, it's a custom TLB configuration. */ #define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ #define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ #define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ #endif /* _XTENSA_CORE_CONFIGURATION_H */ core-matmap.h000066400000000000000000000367151321570333100355020ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/xtensa/config/* * Copyright (c) 2013 Tensilica Inc. * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sublicense, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /* * xtensa/config/core-matmap.h -- Memory access and translation mapping * parameters (CHAL) of the Xtensa processor core configuration. * * If you are using Xtensa Tools, see (which includes * this file) for more details. * * In the Xtensa processor products released to date, all parameters * defined in this file are derivable (at least in theory) from * information contained in the core-isa.h header file. * In particular, the following core configuration parameters are relevant: * XCHAL_HAVE_CACHEATTR * XCHAL_HAVE_MIMIC_CACHEATTR * XCHAL_HAVE_XLT_CACHEATTR * XCHAL_HAVE_PTP_MMU * XCHAL_ITLB_ARF_ENTRIES_LOG2 * XCHAL_DTLB_ARF_ENTRIES_LOG2 * XCHAL_DCACHE_IS_WRITEBACK * XCHAL_ICACHE_SIZE (presence of I-cache) * XCHAL_DCACHE_SIZE (presence of D-cache) * XCHAL_HW_VERSION_MAJOR * XCHAL_HW_VERSION_MINOR */ #ifndef XTENSA_CONFIG_CORE_MATMAP_H #define XTENSA_CONFIG_CORE_MATMAP_H /*---------------------------------------------------------------------- CACHE (MEMORY ACCESS) ATTRIBUTES ----------------------------------------------------------------------*/ /* Cache Attribute encodings -- lists of access modes for each cache attribute: */ #define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \ XTHAL_FAM_BYPASS XCHAL_SEP \ XTHAL_FAM_BYPASS XCHAL_SEP \ XTHAL_FAM_BYPASS XCHAL_SEP \ XTHAL_FAM_BYPASS XCHAL_SEP \ XTHAL_FAM_EXCEPTION XCHAL_SEP \ XTHAL_FAM_EXCEPTION XCHAL_SEP \ XTHAL_FAM_EXCEPTION XCHAL_SEP \ XTHAL_FAM_EXCEPTION XCHAL_SEP \ XTHAL_FAM_EXCEPTION XCHAL_SEP \ XTHAL_FAM_EXCEPTION XCHAL_SEP \ XTHAL_FAM_EXCEPTION XCHAL_SEP \ XTHAL_FAM_EXCEPTION XCHAL_SEP \ XTHAL_FAM_EXCEPTION XCHAL_SEP \ XTHAL_FAM_EXCEPTION XCHAL_SEP \ XTHAL_FAM_EXCEPTION #define XCHAL_LCA_LIST XTHAL_LAM_BYPASSG XCHAL_SEP \ XTHAL_LAM_BYPASSG XCHAL_SEP \ XTHAL_LAM_BYPASSG XCHAL_SEP \ XTHAL_LAM_EXCEPTION XCHAL_SEP \ XTHAL_LAM_BYPASSG XCHAL_SEP \ XTHAL_LAM_EXCEPTION XCHAL_SEP \ XTHAL_LAM_EXCEPTION XCHAL_SEP \ XTHAL_LAM_EXCEPTION XCHAL_SEP \ XTHAL_LAM_EXCEPTION XCHAL_SEP \ XTHAL_LAM_EXCEPTION XCHAL_SEP \ XTHAL_LAM_EXCEPTION XCHAL_SEP \ XTHAL_LAM_EXCEPTION XCHAL_SEP \ XTHAL_LAM_EXCEPTION XCHAL_SEP \ XTHAL_LAM_EXCEPTION XCHAL_SEP \ XTHAL_LAM_BYPASSG XCHAL_SEP \ XTHAL_LAM_EXCEPTION #define XCHAL_SCA_LIST XTHAL_SAM_BYPASS XCHAL_SEP \ XTHAL_SAM_BYPASS XCHAL_SEP \ XTHAL_SAM_BYPASS XCHAL_SEP \ XTHAL_SAM_EXCEPTION XCHAL_SEP \ XTHAL_SAM_BYPASS XCHAL_SEP \ XTHAL_SAM_EXCEPTION XCHAL_SEP \ XTHAL_SAM_EXCEPTION XCHAL_SEP \ XTHAL_SAM_EXCEPTION XCHAL_SEP \ XTHAL_SAM_EXCEPTION XCHAL_SEP \ XTHAL_SAM_EXCEPTION XCHAL_SEP \ XTHAL_SAM_EXCEPTION XCHAL_SEP \ XTHAL_SAM_EXCEPTION XCHAL_SEP \ XTHAL_SAM_EXCEPTION XCHAL_SEP \ XTHAL_SAM_EXCEPTION XCHAL_SEP \ XTHAL_SAM_BYPASS XCHAL_SEP \ XTHAL_SAM_EXCEPTION /* * Specific encoded cache attribute values of general interest. * If a specific cache mode is not available, the closest available * one is returned instead (eg. writethru instead of writeback, * bypass instead of writethru). */ #define XCHAL_CA_BYPASS 2 /* cache disabled (bypassed) mode */ #define XCHAL_CA_WRITETHRU 2 /* cache enabled (write-through) mode */ #define XCHAL_CA_WRITEBACK 2 /* cache enabled (write-back) mode */ #define XCHAL_CA_BYPASS_RW 0 /* cache disabled (bypassed) mode (no exec) */ #define XCHAL_CA_WRITETHRU_RW 0 /* cache enabled (write-through) mode (no exec) */ #define XCHAL_CA_WRITEBACK_RW 0 /* cache enabled (write-back) mode (no exec) */ #define XCHAL_CA_ILLEGAL 15 /* no access allowed (all cause exceptions) mode */ #define XCHAL_CA_ISOLATE 0 /* cache isolate (accesses go to cache not memory) mode */ /*---------------------------------------------------------------------- MMU ----------------------------------------------------------------------*/ /* * General notes on MMU parameters. * * Terminology: * ASID = address-space ID (acts as an "extension" of virtual addresses) * VPN = virtual page number * PPN = physical page number * CA = encoded cache attribute (access modes) * TLB = translation look-aside buffer (term is stretched somewhat here) * I = instruction (fetch accesses) * D = data (load and store accesses) * way = each TLB (ITLB and DTLB) consists of a number of "ways" * that simultaneously match the virtual address of an access; * a TLB successfully translates a virtual address if exactly * one way matches the vaddr; if none match, it is a miss; * if multiple match, one gets a "multihit" exception; * each way can be independently configured in terms of number of * entries, page sizes, which fields are writable or constant, etc. * set = group of contiguous ways with exactly identical parameters * ARF = auto-refill; hardware services a 1st-level miss by loading a PTE * from the page table and storing it in one of the auto-refill ways; * if this PTE load also misses, a miss exception is posted for s/w. * min-wired = a "min-wired" way can be used to map a single (minimum-sized) * page arbitrarily under program control; it has a single entry, * is non-auto-refill (some other way(s) must be auto-refill), * all its fields (VPN, PPN, ASID, CA) are all writable, and it * supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current * restriction is that this be the only page size it supports). * * TLB way entries are virtually indexed. * TLB ways that support multiple page sizes: * - must have all writable VPN and PPN fields; * - can only use one page size at any given time (eg. setup at startup), * selected by the respective ITLBCFG or DTLBCFG special register, * whose bits n*4+3 .. n*4 index the list of page sizes for way n * (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n); * this list may be sparse for auto-refill ways because auto-refill * ways have independent lists of supported page sizes sharing a * common encoding with PTE entries; the encoding is the index into * this list; unsupported sizes for a given way are zero in the list; * selecting unsupported sizes results in undefined hardware behaviour; * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition). */ #define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */ #define XCHAL_MMU_ASID_KERNEL 0 /* ASID value indicating kernel (ring 0) address space */ #define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */ #define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */ #define XCHAL_MMU_MAX_PTE_PAGE_SIZE 29 /* max page size in a PTE structure (log2) */ #define XCHAL_MMU_MIN_PTE_PAGE_SIZE 29 /* min page size in a PTE structure (log2) */ /*** Instruction TLB: ***/ #define XCHAL_ITLB_WAY_BITS 0 /* number of bits holding the ways */ #define XCHAL_ITLB_WAYS 1 /* number of ways (n-way set-associative TLB) */ #define XCHAL_ITLB_ARF_WAYS 0 /* number of auto-refill ways */ #define XCHAL_ITLB_SETS 1 /* number of sets (groups of ways with identical settings) */ /* Way set to which each way belongs: */ #define XCHAL_ITLB_WAY0_SET 0 /* Ways sets that are used by hardware auto-refill (ARF): */ #define XCHAL_ITLB_ARF_SETS 0 /* number of auto-refill sets */ /* Way sets that are "min-wired" (see terminology comment above): */ #define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */ /* ITLB way set 0 (group of ways 0 thru 0): */ #define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */ #define XCHAL_ITLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */ #define XCHAL_ITLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */ #define XCHAL_ITLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */ #define XCHAL_ITLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ #define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */ #define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */ #define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */ #define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */ #define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP; 2^PAGESZ_BITS entries in list, unsupported entries are zero */ #define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ #define XCHAL_ITLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */ #define XCHAL_ITLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */ #define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ #define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ #define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ #define XCHAL_ITLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ #define XCHAL_ITLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */ /* Constant VPN values for each entry of ITLB way set 0 (because VPN_CONSTMASK is non-zero): */ #define XCHAL_ITLB_SET0_E0_VPN_CONST 0x00000000 #define XCHAL_ITLB_SET0_E1_VPN_CONST 0x20000000 #define XCHAL_ITLB_SET0_E2_VPN_CONST 0x40000000 #define XCHAL_ITLB_SET0_E3_VPN_CONST 0x60000000 #define XCHAL_ITLB_SET0_E4_VPN_CONST 0x80000000 #define XCHAL_ITLB_SET0_E5_VPN_CONST 0xA0000000 #define XCHAL_ITLB_SET0_E6_VPN_CONST 0xC0000000 #define XCHAL_ITLB_SET0_E7_VPN_CONST 0xE0000000 /* Constant PPN values for each entry of ITLB way set 0 (because PPN_CONSTMASK is non-zero): */ #define XCHAL_ITLB_SET0_E0_PPN_CONST 0x00000000 #define XCHAL_ITLB_SET0_E1_PPN_CONST 0x20000000 #define XCHAL_ITLB_SET0_E2_PPN_CONST 0x40000000 #define XCHAL_ITLB_SET0_E3_PPN_CONST 0x60000000 #define XCHAL_ITLB_SET0_E4_PPN_CONST 0x80000000 #define XCHAL_ITLB_SET0_E5_PPN_CONST 0xA0000000 #define XCHAL_ITLB_SET0_E6_PPN_CONST 0xC0000000 #define XCHAL_ITLB_SET0_E7_PPN_CONST 0xE0000000 /* Reset CA values for each entry of ITLB way set 0 (because SET0_CA_RESET is non-zero): */ #define XCHAL_ITLB_SET0_E0_CA_RESET 0x02 #define XCHAL_ITLB_SET0_E1_CA_RESET 0x02 #define XCHAL_ITLB_SET0_E2_CA_RESET 0x02 #define XCHAL_ITLB_SET0_E3_CA_RESET 0x02 #define XCHAL_ITLB_SET0_E4_CA_RESET 0x02 #define XCHAL_ITLB_SET0_E5_CA_RESET 0x02 #define XCHAL_ITLB_SET0_E6_CA_RESET 0x02 #define XCHAL_ITLB_SET0_E7_CA_RESET 0x02 /*** Data TLB: ***/ #define XCHAL_DTLB_WAY_BITS 0 /* number of bits holding the ways */ #define XCHAL_DTLB_WAYS 1 /* number of ways (n-way set-associative TLB) */ #define XCHAL_DTLB_ARF_WAYS 0 /* number of auto-refill ways */ #define XCHAL_DTLB_SETS 1 /* number of sets (groups of ways with identical settings) */ /* Way set to which each way belongs: */ #define XCHAL_DTLB_WAY0_SET 0 /* Ways sets that are used by hardware auto-refill (ARF): */ #define XCHAL_DTLB_ARF_SETS 0 /* number of auto-refill sets */ /* Way sets that are "min-wired" (see terminology comment above): */ #define XCHAL_DTLB_MINWIRED_SETS 0 /* number of "min-wired" sets */ /* DTLB way set 0 (group of ways 0 thru 0): */ #define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */ #define XCHAL_DTLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */ #define XCHAL_DTLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */ #define XCHAL_DTLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */ #define XCHAL_DTLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ #define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */ #define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */ #define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */ #define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */ #define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP; 2^PAGESZ_BITS entries in list, unsupported entries are zero */ #define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ #define XCHAL_DTLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */ #define XCHAL_DTLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */ #define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ #define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ #define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ #define XCHAL_DTLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ #define XCHAL_DTLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */ /* Constant VPN values for each entry of DTLB way set 0 (because VPN_CONSTMASK is non-zero): */ #define XCHAL_DTLB_SET0_E0_VPN_CONST 0x00000000 #define XCHAL_DTLB_SET0_E1_VPN_CONST 0x20000000 #define XCHAL_DTLB_SET0_E2_VPN_CONST 0x40000000 #define XCHAL_DTLB_SET0_E3_VPN_CONST 0x60000000 #define XCHAL_DTLB_SET0_E4_VPN_CONST 0x80000000 #define XCHAL_DTLB_SET0_E5_VPN_CONST 0xA0000000 #define XCHAL_DTLB_SET0_E6_VPN_CONST 0xC0000000 #define XCHAL_DTLB_SET0_E7_VPN_CONST 0xE0000000 /* Constant PPN values for each entry of DTLB way set 0 (because PPN_CONSTMASK is non-zero): */ #define XCHAL_DTLB_SET0_E0_PPN_CONST 0x00000000 #define XCHAL_DTLB_SET0_E1_PPN_CONST 0x20000000 #define XCHAL_DTLB_SET0_E2_PPN_CONST 0x40000000 #define XCHAL_DTLB_SET0_E3_PPN_CONST 0x60000000 #define XCHAL_DTLB_SET0_E4_PPN_CONST 0x80000000 #define XCHAL_DTLB_SET0_E5_PPN_CONST 0xA0000000 #define XCHAL_DTLB_SET0_E6_PPN_CONST 0xC0000000 #define XCHAL_DTLB_SET0_E7_PPN_CONST 0xE0000000 /* Reset CA values for each entry of DTLB way set 0 (because SET0_CA_RESET is non-zero): */ #define XCHAL_DTLB_SET0_E0_CA_RESET 0x02 #define XCHAL_DTLB_SET0_E1_CA_RESET 0x02 #define XCHAL_DTLB_SET0_E2_CA_RESET 0x02 #define XCHAL_DTLB_SET0_E3_CA_RESET 0x02 #define XCHAL_DTLB_SET0_E4_CA_RESET 0x02 #define XCHAL_DTLB_SET0_E5_CA_RESET 0x02 #define XCHAL_DTLB_SET0_E6_CA_RESET 0x02 #define XCHAL_DTLB_SET0_E7_CA_RESET 0x02 #endif /*XTENSA_CONFIG_CORE_MATMAP_H*/ specreg.h000066400000000000000000000051321321570333100347120ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/xtensa/config/* * Copyright (c) 2013 Tensilica Inc. * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sublicense, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /* * Xtensa Special Register symbolic names */ #ifndef XTENSA_SPECREG_H #define XTENSA_SPECREG_H /* Include these special register bitfield definitions, for historical reasons: */ #include /* Special registers: */ #define LBEG 0 #define LEND 1 #define LCOUNT 2 #define SAR 3 #define LITBASE 5 #define SCOMPARE1 12 #define WINDOWBASE 72 #define WINDOWSTART 73 #define IBREAKENABLE 96 #define DDR 104 #define IBREAKA_0 128 #define IBREAKA_1 129 #define DBREAKA_0 144 #define DBREAKA_1 145 #define DBREAKC_0 160 #define DBREAKC_1 161 #define EPC_1 177 #define EPC_2 178 #define EPC_3 179 #define EPC_4 180 #define EPC_5 181 #define DEPC 192 #define EPS_2 194 #define EPS_3 195 #define EPS_4 196 #define EPS_5 197 #define EXCSAVE_1 209 #define EXCSAVE_2 210 #define EXCSAVE_3 211 #define EXCSAVE_4 212 #define EXCSAVE_5 213 #define INTERRUPT 226 #define INTENABLE 228 #define PS 230 #define VECBASE 231 #define EXCCAUSE 232 #define DEBUGCAUSE 233 #define CCOUNT 234 #define PRID 235 #define ICOUNT 236 #define ICOUNTLEVEL 237 #define EXCVADDR 238 #define CCOMPARE_0 240 #define MISC_REG_0 244 #define MISC_REG_1 245 /* Special cases (bases of special register series): */ #define IBREAKA 128 #define DBREAKA 144 #define DBREAKC 160 #define EPC 176 #define EPS 192 #define EXCSAVE 208 #define CCOMPARE 240 /* Special names for read-only and write-only interrupt registers: */ #define INTREAD 226 #define INTSET 226 #define INTCLEAR 227 #endif /* XTENSA_SPECREG_H */ tie.h000066400000000000000000000054611321570333100340500ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/inc/xtensa/config/* * Copyright (c) 2013 Tensilica Inc. * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sublicense, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /* * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration * * NOTE: This header file is not meant to be included directly. */ /* * This header file describes this specific Xtensa processor's TIE extensions * that extend basic Xtensa core functionality. It is customized to this * Xtensa processor configuration. */ #ifndef _XTENSA_CORE_TIE_H #define _XTENSA_CORE_TIE_H #define XCHAL_CP_NUM 0 /* number of coprocessors */ #define XCHAL_CP_MAX 0 /* max CP ID + 1 (0 if none) */ #define XCHAL_CP_MASK 0x00 /* bitmask of all CPs by ID */ #define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ /* Save area for non-coprocessor optional and custom (TIE) state: */ #define XCHAL_NCP_SA_SIZE 4 #define XCHAL_NCP_SA_ALIGN 4 /* Total save area for optional and custom state (NCP + CPn): */ #define XCHAL_TOTAL_SA_SIZE 16 /* with 16-byte align padding */ #define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */ /* * Detailed contents of save areas. * NOTE: caller must define the XCHAL_SA_{UREG,SREG,REGF} macros (they * are not defined here) before expanding the XCHAL_SA_xxx_LIST macros. * * XCHAL_SA_SREG(dbnum,offset,size,contentsz,align,name,sregnum,bitmask,x,x) * XCHAL_SA_UREG(dbnum,offset,size,contentsz,align,name,uregnum,bitmask,x,x) * XCHAL_SA_REGF(dbnum,offset,size,contentsz,align,name,index,span,x,x, * basename,regf_name,regf_numentries) */ #define XCHAL_SA_NCP_NUM 1 #define XCHAL_SA_NCP_LIST \ XCHAL_SA_SREG(0x020C, 0, 4, 4, 4, scompare1, 12,0xFFFFFFFF,0,0) /* Byte length of instruction from its first nibble (op0 field), per FLIX. */ #define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3 #endif /*_XTENSA_CORE_TIE_H*/ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/init/000077500000000000000000000000001321570333100306125ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/init/app_start.c000066400000000000000000000225661321570333100327660ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include "dt_defs.h" #include "athos_api.h" #include "regdump.h" #include "usb_defs.h" #include "adf_os_io.h" #include "init.h" #include "app_start.h" // @TODO: Should define the memory region later~ #define ALLOCRAM_START ( ((unsigned int)&_fw_image_end) + 4) #define ALLOCRAM_SIZE ( SYS_RAM_SZIE - ( ALLOCRAM_START - SYS_D_RAM_REGION_0_BASE) - SYS_D_RAM_STACK_SIZE) // support for more than 64 bytes on command pipe extern void usb_reg_out_patch(void); extern int _HIFusb_get_max_msg_len_patch(hif_handle_t handle, int pipe); extern void _HIFusb_isr_handler_patch(hif_handle_t h); extern BOOLEAN bSet_configuration_patch(void); extern void vUSBFIFO_EP6Cfg_FS_patch(void); extern void usb_status_in_patch(void); extern void _fw_usbfifo_init(USB_FIFO_CONFIG *pConfig); extern void zfTurnOffPower_patch(void); extern void zfResetUSBFIFO_patch(void); extern void _HIFusb_start_patch(hif_handle_t handle); extern void hif_pci_patch_install(struct hif_api *apis); extern BOOLEAN bGet_descriptor_patch(void); extern BOOLEAN bStandardCommand_patch(void); // patch for clock extern void cmnos_clock_init_patch(a_uint32_t refclk); extern a_uint32_t cmnos_refclk_speed_get_patch(void); extern void cmnos_delay_us_patch(int us); extern void cmnos_tick_patch(void); extern a_uint32_t cmnos_milliseconds_patch(void); extern BOOLEAN bJumptoFlash; extern BOOLEAN bEepromExist; void __section(boot) __noreturn __visible app_start(void) { uint32_t rst_status; A_HOSTIF hostif; #if defined(PROJECT_MAGPIE) T_EEP_RET retEEP; #endif /* Zero BSS segment & dynamic memory section. */ init_mem(); #if defined(PROJECT_MAGPIE) fatal_exception_func(); #endif if( IS_FLASHBOOT() ) { athos_indirection_table_install(); DBG_MODULE_INSTALL(); A_CLOCK_INIT(SYSTEM_CLK); A_UART_INIT(); A_PRINTF_INIT(); A_DBG_INIT(); A_EEP_INIT(); A_TASKLET_INIT(); _indir_tbl.cmnos.timer._timer_init(); #if defined(PROJECT_K2) /* * WAR: these variable is not initialized when boot from flash * either re-enumeration or config them to default value = 0 would fix the issue */ u8UsbInterfaceAlternateSetting = u8UsbConfigValue = u8UsbInterfaceValue = 0; #endif } #ifdef ROM_VER_1_1 else A_EEP_INIT(); /*Required for 1_1*/ #endif #if defined(PROJECT_MAGPIE) retEEP = A_EEP_IS_EXIST(); bJumptoFlash = FALSE; if ( RET_SUCCESS == retEEP ) { bEepromExist = TRUE; } else { bEepromExist = FALSE; } #endif hostif = A_IS_HOST_PRESENT(); #if defined(PROJECT_MAGPIE) rst_status = ioread32(WATCH_DOG_MAGIC_PATTERN_ADDR); #elif defined(PROJECT_K2) rst_status = ioread32(MAGPIE_REG_RST_STATUS_ADDR); #endif /* #if defined(PROJECT_MAGPIE) */ A_PRINTF(" A_WDT_INIT()\n\r"); #if defined(PROJECT_K2) save_cmnos_printf = fw_cmnos_printf; #endif if( hostif == HIF_USB ) { #if defined(PROJECT_K2) #if MOVE_PRINT_TO_RAM save_cmnos_printf = _indir_tbl.cmnos.printf._printf; _indir_tbl.cmnos.printf._printf = fw_cmnos_printf; #endif _indir_tbl.cmnos.usb._usb_fw_task = _fw_usb_fw_task; _indir_tbl.cmnos.usb._usb_reset_fifo = _fw_usb_reset_fifo; #endif } if( rst_status == WDT_MAGIC_PATTERN ) { A_PRINTF(" ==>WDT reset<==\n"); #if defined(PROJECT_MAGPIE) reset_EP4_FIFO(); #endif *((volatile uint32_t*)WATCH_DOG_RESET_COUNTER_ADDR)+=1; } else if (rst_status == SUS_MAGIC_PATTERN) { A_PRINTF(" ==>warm start<==\n"); } else A_PRINTF(" ==>cold start<==\n"); #if defined(PROJECT_MAGPIE) *((volatile uint32_t*)WATCH_DOG_MAGIC_PATTERN_ADDR)=WDT_MAGIC_PATTERN; #elif defined(PROJECT_K2) iowrite32(MAGPIE_REG_RST_STATUS_ADDR, WDT_MAGIC_PATTERN); #endif /* #if defined(PROJECT_MAGPIE) */ /* intr enable would left for firmware */ /* athos_interrupt_init(); */ DBG_MODULE_INSTALL(); #if defined(PROJECT_K2) A_DBG_INIT(); #endif #if defined(PROJECT_K2) #if SYSTEM_MODULE_SFLASH SFLASH_MODULE_INSTALL(); A_SFLASH_INIT(); #endif #endif HIF_MODULE_INSTALL(); HTC_MODULE_INSTALL(); WMI_SERVICE_MODULE_INSTALL(); BUF_POOL_MODULE_INSTALL(); VBUF_MODULE_INSTALL(); VDESC_MODULE_INSTALL(); //init each module, should be put together.. A_PRINTF("ALLOCRAM start 0x%x size %d\n", ALLOCRAM_START, ALLOCRAM_SIZE); A_ALLOCRAM_INIT(ALLOCRAM_START, ALLOCRAM_SIZE); if( hostif == HIF_USB ) { _indir_tbl.hif._get_max_msg_len = _HIFusb_get_max_msg_len_patch; _indir_tbl.cmnos.usb._usb_reg_out = usb_reg_out_patch; _indir_tbl.hif._isr_handler = _HIFusb_isr_handler_patch; _indir_tbl.cmnos.usb._usb_set_configuration = bSet_configuration_patch; _indir_tbl.cmnos.usb._usb_status_in = usb_status_in_patch; _indir_tbl.cmnos.usb._usb_get_descriptor = bGet_descriptor_patch; _indir_tbl.cmnos.usb._usb_standard_cmd = bStandardCommand_patch; _indir_tbl.usbfifo_api._init = _fw_usbfifo_init; #if defined(PROJECT_MAGPIE) _indir_tbl.cmnos.usb._usb_power_off = zfTurnOffPower_patch; _indir_tbl.cmnos.usb._usb_reset_fifo = zfResetUSBFIFO_patch; _indir_tbl.hif._start = _HIFusb_start_patch; _indir_tbl.htc._HTC_MsgRecvHandler = HTCMsgRecvHandler_patch; _indir_tbl.htc._HTC_ControlSvcProcessMsg = HTCControlSvcProcessMsg_patch; #endif if (!(ioread8_usb(ZM_MAIN_CTRL_OFFSET) & BIT6)) vUSBFIFO_EP6Cfg_FS_patch(); #ifdef FUSION_USB_ENABLE_TX_STREAM // For K2, enable tx stream mode A_PRINTF("Enable Tx Stream mode: 0x%x\r\n", ioread32_usb(ZM_SOC_USB_MODE_CTRL_OFFSET)); /* Patch for K2 USB STREAM mode */ /* disable down stream DMA mode */ io32_rmw_usb(ZM_SOC_USB_MODE_CTRL_OFFSET, BIT6, BIT0); #if SYSTEM_MODULE_HP_EP5 io32_set_usb(ZM_SOC_USB_MODE_CTRL_OFFSET, BIT8); #endif #if SYSTEM_MODULE_HP_EP6 io32_set_usb(ZM_SOC_USB_MODE_CTRL_OFFSET, BIT9); #endif /* enable down stream DMA mode */ io32_set_usb(ZM_SOC_USB_MODE_CTRL_OFFSET, BIT0); #endif #ifdef FUSION_USB_ENABLE_RX_STREAM /* Patch for K2 USB STREAM mode */ /* disable upstream DMA mode and enable upstream stream mode */ io32_clr_usb(ZM_SOC_USB_MODE_CTRL_OFFSET, BIT1 | BIT3); /* K2, Set maximum IN transfer to 8K */ io32_rmw_usb(ZM_SOC_USB_MODE_CTRL_OFFSET, 0x20, 0x30); /* enable upstream DMA mode */ io32_set_usb(ZM_SOC_USB_MODE_CTRL_OFFSET, BIT1); /* set stream mode timeout critirea */ iowrite32_usb(ZM_SOC_USB_TIME_CTRL_OFFSET, 0xa0); #if defined(PROJECT_K2) /*0x10004020 is vaild in k2 but could be invaild in other chip*/ if ((ioread32(0x10004020) & 0x2000) != 0) { /* disable stream mode for AR9270 */ iowrite32_usb(ZM_SOC_USB_MAX_AGGREGATE_OFFSET, 0); } else { /* enable stream mode for AR9271 */ iowrite32_usb(ZM_SOC_USB_MAX_AGGREGATE_OFFSET, 9); } #else iowrite32_usb(ZM_SOC_USB_MAX_AGGREGATE_OFFSET, 9); #endif #endif } #if defined(PROJECT_MAGPIE) && !defined(ROM_VER_1_1) else if (hostif == HIF_PCI ) hif_pci_patch_install(&_indir_tbl.hif); #endif A_PRINTF("USB mode: 0x%x\r\n", ioread32_usb(0x100)); // patch the clock function if(1) { _indir_tbl.cmnos.clock._clock_init = cmnos_clock_init_patch; _indir_tbl.cmnos.clock._refclk_speed_get = cmnos_refclk_speed_get_patch; _indir_tbl.cmnos.clock._delay_us = cmnos_delay_us_patch; _indir_tbl.cmnos.clock._clock_tick = cmnos_tick_patch; _indir_tbl.cmnos.clock._milliseconds = cmnos_milliseconds_patch; //default clock, setup initial variable, SYSTEM_FREQ=40 A_CLOCK_INIT(SYSTEM_FREQ); } Magpie_init(); #if MAGPIE_ENABLE_WLAN == 1 io32_clr(MAGPIE_REG_RST_RESET_ADDR, BIT10 | BIT8 | BIT7 | BIT6); #if defined(PROJECT_MAGPIE) io32_set(MAGPIE_REG_AHB_ARB_ADDR, BIT1); #endif wlan_pci_module_init(); wlan_pci_probe(); #endif A_PRINTF("Tgt running\n\r"); #if defined(PROJECT_MAGPIE) if(1) { A_PRINTF("======= Apply MISC Assert patch\n\r"); _assfail_ori = _indir_tbl.cmnos.misc._assfail; _indir_tbl.cmnos.misc._assfail = exception_reset; } change_magpie_clk(); #endif wlan_task(); //never return } open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/init/app_start.h000066400000000000000000000041411321570333100327600ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * Copyright (c) 2016 Oleksij Rempel * * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _ATH_APP_START_H_ #define _ATH_APP_START_H_ #define __noreturn __attribute__((noreturn)) #define __section(s) __attribute__((section("." # s))) #define __visible __attribute__((externally_visible)) void __section(boot) __noreturn __visible app_start(void); void Magpie_init(void); #endif /* _ATH_APP_START_H_ */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/init/init.c000077500000000000000000000252121321570333100317260ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #if defined(_RAM_) #include #include #include "athos_api.h" #include "usb_defs.h" #include "adf_os_io.h" #if defined(PROJECT_MAGPIE) #include "regdump.h" extern uint32_t *init_htc_handle; uint8_t htc_complete_setup = 0; void reset_EP4_FIFO(void); #endif #include "init.h" void Magpie_init(void); #if defined(PROJECT_MAGPIE) extern BOOLEAN bEepromExist; extern BOOLEAN bJumptoFlash; #endif static uint32_t loop_low, loop_high; // reference idle count at the beginning uint32_t idle_cnt = 0; #if defined(PROJECT_K2) // save the ROM printf function point int (* save_cmnos_printf)(const char * fmt, ...); #endif static void idle_task(); #if defined(PROJECT_MAGPIE) void fatal_exception_func() { // patch for execption (void)_xtos_set_exception_handler(EXCCAUSE_UNALIGNED, AR6002_fatal_exception_handler_patch); (void)_xtos_set_exception_handler(EXCCAUSE_LOAD_STORE_ERROR, AR6002_fatal_exception_handler_patch); (void)_xtos_set_exception_handler(EXCCAUSE_ILLEGAL, AR6002_fatal_exception_handler_patch); (void)_xtos_set_exception_handler(EXCCAUSE_INSTR_ERROR, AR6002_fatal_exception_handler_patch); (void)_xtos_set_exception_handler(EXCCAUSE_PRIVILEGED, AR6002_fatal_exception_handler_patch); (void)_xtos_set_exception_handler(EXCCAUSE_INSTR_DATA_ERROR, AR6002_fatal_exception_handler_patch); (void)_xtos_set_exception_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR, AR6002_fatal_exception_handler_patch); (void)_xtos_set_exception_handler(EXCCAUSE_DIVIDE_BY_ZERO, AR6002_fatal_exception_handler_patch); } #endif #if defined(PROJECT_MAGPIE) void change_magpie_clk(void) { iowrite32(0x00056004, BIT4 | BIT0); /* Wait for the update bit (BIT0) to get cleared */ while (ioread32(0x00056004) & BIT0) ; /* Put the PLL into reset */ io32_set(0x00050010, BIT1); /* * XXX: statically set the CPU clock to 200Mhz */ /* Setting PLL to 400MHz */ iowrite32(0x00056000, 0x325); /* Pull CPU PLL out of Reset */ io32_clr(0x00050010, BIT1); A_DELAY_USECS(60); // wait for stable /* CPU & AHB settings */ /* * AHB clk = ( CPU clk / 2 ) */ iowrite32(0x00056004, 0x00001 | BIT16 | BIT8); /* set plldiv to 2 */ while (ioread32(0x00056004) & BIT0) ; /* UART Setting */ A_UART_HWINIT((100*1000*1000), 115200); } void exception_reset(struct register_dump_s *dump) { A_PRINTF("exception_reset \n"); /* phase I dump info */ A_PRINTF("exception reset-phase 1\n"); if(_assfail_ori) _assfail_ori(dump); /* phase II reset */ A_PRINTF("exception reset-phase 2\n"); iowrite32(WATCH_DOG_MAGIC_PATTERN_ADDR, WDT_MAGIC_PATTERN); io32_set(MAGPIE_REG_RST_RESET_ADDR, BIT10 | BIT8 | BIT7 | BIT6); io32_set(MAGPIE_REG_AHB_ARB_ADDR, BIT1); iowrite32_usb(ZM_SOC_USB_DMA_RESET_OFFSET, 0x0); io32_set(0x50010, BIT4); A_DELAY_USECS(5); io32_clr(0x50010, BIT4); A_DELAY_USECS(5); iowrite32_usb(ZM_SOC_USB_DMA_RESET_OFFSET, BIT0); // set clock to bypass mode - 40Mhz from XTAL iowrite32(MAGPIE_REG_CPU_PLL_BYPASS_ADDR, BIT0 | BIT4); A_DELAY_USECS(100); // wait for stable iowrite32(MAGPIE_REG_CPU_PLL_ADDR, BIT16); A_UART_HWINIT((40*1000*1000), 115200); A_PRINTF("do TX/RX swap\n"); MAGPIE_REG_USB_RX0_SWAP_DATA = 0x1; MAGPIE_REG_USB_TX0_SWAP_DATA = 0x1; MAGPIE_REG_USB_RX1_SWAP_DATA = 0x1; MAGPIE_REG_USB_RX2_SWAP_DATA = 0x1; A_PRINTF("Cold reboot initiated."); #if defined(PROJECT_MAGPIE) iowrite32(WATCH_DOG_MAGIC_PATTERN_ADDR, 0); #elif defined(PROJECT_K2) iowrite32(MAGPIE_REG_RST_STATUS_ADDR, 0); #endif /* #if defined(PROJECT_MAGPIE) */ A_USB_JUMP_BOOT(); } void reset_EP4_FIFO(void) { int i; /* reset EP4 FIFO */ io8_set_usb(ZM_EP4_BYTE_COUNT_HIGH_OFFSET, BIT4); for(i = 0; i < 100; i++) {} io8_clr_usb(ZM_EP4_BYTE_COUNT_HIGH_OFFSET, BIT4); } LOCAL void zfGenExceptionEvent(uint32_t exccause, uint32_t pc, uint32_t badvaddr) { uint32_t pattern = 0x33221199; A_PRINTF("Tgt Drv send an event 44332211 to Host Drv\n"); mUSB_STATUS_IN_INT_DISABLE(); iowrite32_usb(ZM_CBUS_FIFO_SIZE_OFFSET, 0x0f); iowrite32_usb(ZM_EP3_DATA_OFFSET, pattern); iowrite32_usb(ZM_EP3_DATA_OFFSET, exccause); iowrite32_usb(ZM_EP3_DATA_OFFSET, pc); iowrite32_usb(ZM_EP3_DATA_OFFSET, badvaddr); mUSB_EP3_XFER_DONE(); } LOCAL void zfGenWrongEpidEvent(uint32_t epid) { uint32_t pattern = 0x33221299; A_PRINTF("Tgt Drv send an event 44332212 to Host Drv\n"); mUSB_STATUS_IN_INT_DISABLE(); iowrite32_usb(ZM_CBUS_FIFO_SIZE_OFFSET, 0x0f); iowrite32_usb(ZM_EP3_DATA_OFFSET, pattern); iowrite32_usb(ZM_EP3_DATA_OFFSET, epid); mUSB_EP3_XFER_DONE(); } void AR6002_fatal_exception_handler_patch(CPU_exception_frame_t *exc_frame) { struct register_dump_s dump; uint32_t exc_cause, exc_vaddr; asm volatile("rsr %0,%1" : "=r" (exc_cause) : "n" (EXCCAUSE)); asm volatile("rsr %0,%1" : "=r" (exc_vaddr) : "n" (EXCVADDR)); dump.exc_frame = *exc_frame; /* structure copy */ dump.badvaddr = exc_vaddr; dump.exc_frame.xt_exccause = exc_cause; dump.pc = exc_frame->xt_pc; dump.assline = 0; zfGenExceptionEvent(dump.exc_frame.xt_exccause, dump.pc, dump.badvaddr); #if SYSTEM_MODULE_PRINT A_PRINTF("\nFatal exception (%d): \tpc=0x%x \n\r\tbadvaddr=0x%x \n\r\tdump area=0x%x\n", dump.exc_frame.xt_exccause, dump.pc, dump.badvaddr, &dump); PRINT_FAILURE_STATE(); #else A_PUTS("Fatal exception\n\r"); #endif A_ASSFAIL(&dump); #if defined(_ROM_) A_WDT_ENABLE(); #endif while(1) ; } void HTCControlSvcProcessMsg_patch(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t hdr_buf, adf_nbuf_t pBuffers, void *arg) { a_uint8_t *anbdata; a_uint32_t anblen; HTC_UNKNOWN_MSG *pMsg; /* we assume buffers are aligned such that we can access the message * parameters directly*/ adf_nbuf_peek_header(pBuffers, &anbdata, &anblen); pMsg = (HTC_UNKNOWN_MSG *)anbdata; if (pMsg->MessageID == HTC_MSG_SETUP_COMPLETE_ID) { htc_complete_setup = 1; } HTCControlSvcProcessMsg(EndpointID, hdr_buf, pBuffers, arg); } /* Patch callback for check the endpoint ID is correct or not */ void HTCMsgRecvHandler_patch(adf_nbuf_t hdr_buf, adf_nbuf_t buffer, void *context) { int eid; a_uint8_t *anbdata; a_uint32_t anblen; adf_nbuf_t tmp_nbuf; HTC_FRAME_HDR *pHTCHdr; if (hdr_buf == ADF_NBUF_NULL) { /* HTC hdr is not in the hdr_buf */ tmp_nbuf = buffer; } else { tmp_nbuf = hdr_buf; } adf_nbuf_peek_header(tmp_nbuf, &anbdata, &anblen); pHTCHdr = (HTC_FRAME_HDR *)anbdata; eid = pHTCHdr->EndpointID; if ((eid != 0) && (htc_complete_setup == 0)) { A_PRINTF("\nHTC Hdr EndpointID = %d, anblen = %d\n", pHTCHdr->EndpointID, anblen); A_PRINTF("HTC Hder : %2x-%2x-%2x-%2x-%2x-%2x-%2x-%2x-%2x-%2x-%2x-%2x\n", *anbdata, *(anbdata+1), *(anbdata+2), *(anbdata+3), *(anbdata+4), *(anbdata+5), *(anbdata+6), *(anbdata+7), *(anbdata+8), *(anbdata+9), *(anbdata+10), *(anbdata+11)); A_PRINTF("init_htc_handle = 0x%8x\n", init_htc_handle); if (pHTCHdr->EndpointID == 1) { A_PRINTF("Return WMI Command buffer\n"); HTC_ReturnBuffers(init_htc_handle, 1, tmp_nbuf); } else if ((pHTCHdr->EndpointID == 5) || (pHTCHdr->EndpointID == 6)) { A_PRINTF("Return Data buffer\n"); HTC_ReturnBuffers(init_htc_handle, 6, tmp_nbuf); } else { } } else { if ((pHTCHdr->EndpointID < 0) || (pHTCHdr->EndpointID >= ENDPOINT_MAX)) { A_PRINTF("HTC Hdr EndpointID = %d, anblen = %d\n", pHTCHdr->EndpointID, anblen); A_PRINTF("HTC Hder : %2x-%2x-%2x-%2x-%2x-%2x-%2x-%2x\n", *anbdata, *(anbdata+1), *(anbdata+2), *(anbdata+3), *(anbdata+4), *(anbdata+5), *(anbdata+6), *(anbdata+7)); if (anblen > 64) { A_PRINTF("EP1-Tx-Data with Wrong Htc Header Endpoint ID, WAR free this buffer\n"); HTC_ReturnBuffers(init_htc_handle, 6, tmp_nbuf); A_PRINTF("EP1-Tx-Data > Free this buffer successfully\n"); } else { A_PRINTF("EP4-WMI-Cmd with Wrong Htc Header Endpoint ID, WAR free this buffer\n"); zfGenWrongEpidEvent((a_uint32_t)pHTCHdr->EndpointID); HTC_ReturnBuffers(init_htc_handle, 1, tmp_nbuf); A_PRINTF("EP4-WMI-Cmd > Free this buffer successfully\n"); } } else HTCMsgRecvHandler( hdr_buf, buffer, context); } } #endif void init_mem() { int i = 0; uint32_t *temp = (uint32_t *)ALLOCRAM_START; /* clear bss segment */ for(temp = (uint32_t *)&START_BSS; temp < (uint32_t *)&END_BSS; temp++) *temp = 0; /* clear heap segment */ for(i = 0; i < ((ALLOCRAM_SIZE - 4)/4); i++) temp[i] = 0; } static void idle_task() { if (loop_low == 0xffffffff) { loop_low = 0; loop_high++; } else { loop_low++; } return; } void __noreturn wlan_task(void) { loop_low=loop_high=0; while(1) { /* update wdt timer */ A_WDT_TASK(); /* UPDATE cticks - to be moved to idle_tsk, put here will be easier to read */ A_CLOCK_TICK(); HIF_isr_handler(NULL); #if MAGPIE_ENABLE_WLAN == 1 wlan_pci_isr(); #endif A_TASKLET_RUN(); A_TIMER_RUN(); /* Very low priority tasks */ if ((loop_low & 0x1fff) == 0x7) A_DBG_TASK(); idle_task(); } } #endif /* #if defined(_RAM_) */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/init/init.h000066400000000000000000000057211321570333100317330ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ // @TODO: Should define the memory region later~ #define ALLOCRAM_START ( ((unsigned int)&_fw_image_end) + 4) #define ALLOCRAM_SIZE ( SYS_RAM_SZIE - ( ALLOCRAM_START - SYS_D_RAM_REGION_0_BASE) - SYS_D_RAM_STACK_SIZE) #include "app_start.h" #include "regdump.h" #define SBOOT_PATTERN 0x5342 #define IS_FLASHBOOT() (((DEBUG_SYSTEM_STATE&~(0x0000ffff))>>16==SBOOT_PATTERN)) // patch for exception handle void AR6002_fatal_exception_handler_patch(CPU_exception_frame_t *exc_frame); void exception_reset(struct register_dump_s *dump); void (* _assfail_ori)(struct register_dump_s *); void HTCMsgRecvHandler_patch(adf_nbuf_t hdr_buf, adf_nbuf_t buffer, void *context); void HTCControlSvcProcessMsg_patch(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t hdr_buf, adf_nbuf_t pBuffers, void *arg); #if defined(PROJECT_K2) #if MOVE_PRINT_TO_RAM extern int fw_cmnos_printf(const char *fmt, ...); extern uint16_t u8UsbConfigValue; extern uint16_t u8UsbInterfaceValue; extern uint16_t u8UsbInterfaceAlternateSetting; #endif extern void _fw_usb_fw_task(void); extern void _fw_usb_reset_fifo(void); #endif #if defined(PROJECT_MAGPIE) void change_magpie_clk(void); #endif void fatal_exception_func(); void init_mem(); void __noreturn wlan_task(); void reset_EP4_FIFO(void); open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/init/magpie.c000077500000000000000000000125041321570333100322250ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "sys_cfg.h" #include "app_start.h" #if defined(_RAM_) #include "dt_defs.h" #include "athos_api.h" #include "adf_os_mem.h" #define MAGPIE 1 #if MAGPIE==1 void htc_setup_comp(void) { } /* target WMI command related globals */ static void dispatch_magpie_sys_cmds(void *pContext, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *buffer, int Length); #if MAGPIE_ENABLE_WLAN == 0 static WMI_DISPATCH_ENTRY Magpie_Sys_DispatchEntries[] = { {dispatch_magpie_sys_cmds, WMI_ECHO_CMDID, 0}, {dispatch_magpie_sys_cmds, WMI_ACCESS_MEMORY_CMDID, 0} }; static WMI_DECLARE_DISPATCH_TABLE(Magpie_Sys_Commands_Tbl, Magpie_Sys_DispatchEntries); #endif htc_handle_t htc_handle; extern void HTC_Loopback_Init(htc_handle_t handle); extern void _wmi_cmd_rsp(void *pContext, WMI_COMMAND_ID cmd_id, A_UINT16 SeqNo, A_UINT8 *buffer, int Length); static void handle_echo_command(void *pContext, A_UINT16 SeqNo, A_UINT8 *buffer, int Length) { _wmi_cmd_rsp(pContext, WMI_ECHO_CMDID, SeqNo, buffer, Length); } static void dispatch_magpie_sys_cmds(void *pContext, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *buffer, int Length) { switch(Command) { case WMI_ECHO_CMDID: handle_echo_command(pContext, SeqNo, buffer, Length); break; case WMI_ACCESS_MEMORY_CMDID: break; } } void _wmi_cmd_rsp(void *pContext, WMI_COMMAND_ID cmd_id, A_UINT16 SeqNo, A_UINT8 *buffer, int Length) { adf_nbuf_t netbuf = ADF_NBUF_NULL; A_UINT8 *pData; netbuf = WMI_AllocEvent(pContext, WMI_EVT_CLASS_CMD_REPLY, sizeof(WMI_CMD_HDR) + Length); if (netbuf == ADF_NBUF_NULL) { adf_os_print("%s: buffer allocation for event_id %x failed!\n", __FUNCTION__, cmd_id); adf_os_assert(0); return; } if (Length != 0 && buffer != NULL) { pData = (A_UINT8 *)adf_nbuf_put_tail(netbuf, Length); adf_os_mem_copy(pData, buffer, Length); } WMI_SendEvent(pContext, netbuf, cmd_id, SeqNo, Length); } void Magpie_init(void) { A_PRINTF("[+++Magpie_init]\n\r"); A_PRINTF("[+++VBUF_init(%d)]\n\r", MAX_BUF_NUM); VBUF_init(MAX_BUF_NUM); A_PRINTF("[+++VBUF_init(%d)]\n\r", MAX_DESC_NUM); VDESC_init(MAX_DESC_NUM); #if MAGPIE_ENABLE_WLAN == 0 aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa hif_handle = HIF_init(0); #if ZM_FM_LOOPBACK == 1 HIF_config_pipe(hif_handle, HIF_USB_PIPE_TX, 5); HIF_config_pipe(hif_handle, HIF_USB_PIPE_COMMAND, 2); #if SYSTEM_MODULE_HP_EP5 HIF_config_pipe(hif_handle, HIF_USB_PIPE_HP_TX, 3); #endif #if SYSTEM_MODULE_HP_EP6 HIF_config_pipe(hif_handle, HIF_USB_PIPE_MP_TX, 3); #endif A_PRINTF("[+++HIF_init(0)]\n\r"); HIF_start(hif_handle); #else /* ZM_FM_LOOPBACK == 0 */ // initialize HTC htcConf.CreditSize = 320; htcConf.CreditNumber = 10; #if 1 htcConf.ControlDownLinkPipeID = HIF_USB_PIPE_INTERRUPT; // Target -> Host htcConf.ControlUpLinkPipeID = HIF_USB_PIPE_COMMAND; // Host -> Target #else htcConf.ControlDownLinkPipeID = HIF_USB_PIPE_RX; htcConf.ControlUpLinkPipeID = HIF_USB_PIPE_TX; #endif htcConf.HIFHandle = hif_handle; htcConf.OSHandle = 0; // not used htcConf.PoolHandle = pool_handle; htc_handle = HTC_init(htc_setup_comp, &htcConf); // Initialize HTC services HTC_Loopback_Init(htc_handle); adf_os_mem_zero(&wmiConfig, sizeof(WMI_SVC_CONFIG)); wmiConfig.HtcHandle = htc_handle; wmiConfig.PoolHandle = pool_handle; wmiConfig.MaxCmdReplyEvts = 1; wmiConfig.MaxEventEvts = 1; wmi_handle = WMI_Init(&wmiConfig); Magpie_Sys_Commands_Tbl.pContext = wmi_handle; WMI_RegisterDispatchTable(Magpie_Sys_Commands_Tbl.pContext, &Magpie_Sys_Commands_Tbl); #endif/* ZM_FM_LOOPBACK == 0 */ #endif /* MAGPIE_ENABLE_WLAN */ } #endif /* #if MAGPIE==1 */ #endif /* #if defined(_RAM_) */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/rompatch/000077500000000000000000000000001321570333100314645ustar00rootroot00000000000000HIF_usb_patch.c000077500000000000000000000064271321570333100342230ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/rompatch/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "sys_cfg.h" #include "dt_defs.h" #include "reg_defs.h" #include #include #include #include #include #include #include #include "hif_usb.h" /* * -- support more than 64 bytes command on ep4 -- */ int _HIFusb_get_max_msg_len_patch(hif_handle_t handle, int pipe) { switch(pipe) { case HIF_USB_PIPE_INTERRUPT: case HIF_USB_PIPE_COMMAND: return 512; default: return 1600; } } /* * -- move the usb_task to here -- */ void _HIFusb_isr_handler_patch(hif_handle_t h) { A_USB_FW_TASK(); _HIFusb_isr_handler(h); } /* * -- reset usb dma -- * * - make sure DMA_START bit0 is zero * - update DMA_START bit4 to 1 * - update DESC_START_ADDR * - update DMA_START bit 0 */ void _HIFusb_start_patch(hif_handle_t handle) { MAGPIE_REG_USB_TX0_DMA_START = 0x0; MAGPIE_REG_USB_RX0_DMA_START = 0x0; MAGPIE_REG_USB_RX1_DMA_START = 0x0; MAGPIE_REG_USB_RX2_DMA_START = 0x0; while( 1 ) { if(!MAGPIE_REG_USB_TX0_DMA_START && !MAGPIE_REG_USB_RX0_DMA_START && !MAGPIE_REG_USB_RX1_DMA_START && !MAGPIE_REG_USB_RX2_DMA_START ) { MAGPIE_REG_USB_TX0_DMA_START = MAGPIE_REG_USB_TX0_DMA_START|BIT4; MAGPIE_REG_USB_RX0_DMA_START = MAGPIE_REG_USB_RX0_DMA_START|BIT4; MAGPIE_REG_USB_RX1_DMA_START = MAGPIE_REG_USB_RX1_DMA_START|BIT4; MAGPIE_REG_USB_RX2_DMA_START = MAGPIE_REG_USB_RX2_DMA_START|BIT4; break; } } _HIFusb_start(handle); } cmnos_clock_patch.c000077500000000000000000000053561321570333100352360ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/rompatch/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "athos_api.h" #include "sys_cfg.h" a_uint32_t ref_clk = 0; extern a_uint32_t cticks; // clock change // void cmnos_clock_init_patch(a_uint32_t refclk) { ref_clk = refclk; } // retrieve current clock setting a_uint32_t cmnos_refclk_speed_get_patch(void) { return ref_clk; } // software emulate delay function void cmnos_delay_us_patch(int us) { a_uint32_t start_time = NOW(); unsigned int num_ticks = us*ref_clk; // system_freq == number of ticks per 1us while ( (NOW() - start_time) < num_ticks) { /* busy spin */ ; } } // software emulate microsecond ticks void cmnos_tick_patch(void) { static a_uint32_t last_tick = 0; a_uint32_t current_tick = NOW(); a_uint32_t delta_tick; delta_tick = (A_UINT32 ) (current_tick - last_tick)/(ref_clk<<10); if( delta_tick > 0 ) last_tick = current_tick; cticks += delta_tick; } // get current sysmem up time in milliseconds based a_uint32_t cmnos_milliseconds_patch(void) { cmnos_tick_patch(); return (cticks); } open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/wlan/000077500000000000000000000000001321570333100306105ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/wlan/wlan_pci.c000077500000000000000000000105621321570333100325570ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #if MAGPIE_ENABLE_WLAN == 0 A_PCI_INIT_FUNC g_pci_init_func; #endif #if MAGPIE_ENABLE_PCIE == 0 #define EMULATE_PCI_CONFIG #endif #define PCI_CONFIG_BASE_ADDR 0x14000000 extern A_PCI_INIT_FUNC g_pci_init_func; adf_drv_info_t* g_wlan_drv = NULL; adf_drv_handle_t g_wlan_drv_handle = NULL; adf_os_drv_intr g_wlan_intr = NULL; void wlan_pci_module_init(void) { if (g_pci_init_func != NULL) { g_pci_init_func(); } } void wlan_pci_register_drv(adf_drv_info_t *drv) { g_wlan_drv = drv; } #define ATHEROS_VENDOR_ID 0x168c #define AR5416_DEVID_PCIE 0x24 void wlan_pci_probe(void) { __adf_softc_t *sc; adf_os_resource_t drv_res = {0}; adf_os_attach_data_t drv_data = {{0}}; int vendor_id; int device_id; A_PRINTF(": Attaching the driver\n"); #if MAGPIE_ENABLE_PCIE == 0 vendor_id = ATHEROS_VENDOR_ID; device_id = AR5416_DEVID_PCIE; #else vendor_id = wlan_pci_config_read(0, 2); device_id = wlan_pci_config_read(2, 2); #endif A_PRINTF(": Vendor id 0x%x Dev id 0x%x\n", vendor_id, device_id); if (vendor_id != ATHEROS_VENDOR_ID) { A_PRINTF(": Atheros card not found\n"); return; } /** * Allocate the sc & zero down */ sc = A_ALLOCRAM(sizeof(__adf_softc_t)); if (!sc) { A_PRINTF("Cannot malloc softc\n"); goto mem_fail; } #define AR5416_DEVID_PCIE 0x24 drv_data.pci.device = AR5416_DEVID_PCIE; drv_data.pci.vendor = 0x168c; drv_data.pci.subvendor = 0; drv_data.pci.subdevice = 0; drv_res.start = (a_uint32_t) 0; drv_res.end = 0; drv_res.type = ADF_OS_RESOURCE_TYPE_MEM; g_wlan_drv_handle = g_wlan_drv->drv_attach(&drv_res, 1, &drv_data, NULL); return; mem_fail: return; } int wlan_pci_config_write(int offset, a_uint32_t val, int width) { #if MAGPIE_ENABLE_PCIE == 1 unsigned long addr = ( PCI_CONFIG_BASE_ADDR + offset ) & 0xfffffffc; A_UINT8 *ptr = (A_UINT8 *)addr; A_UINT8 *valptr = (A_UINT8 *)&val; int idx = offset & 0x3; int i; for (i = 0; i < width; i++) { ptr[idx + i] = valptr[3-i]; } #endif return 0; } int wlan_pci_config_read(int offset, int width) { #if MAGPIE_ENABLE_PCIE == 0 return 0; #else unsigned long addr = ( PCI_CONFIG_BASE_ADDR + offset ) & 0xfffffffc; unsigned long value = *((unsigned long *)addr); A_UINT8 *ptr = (A_UINT8 *)&value; int idx = offset & 0x3; int result = 0; int i; for (i = 0; i < width; i++) { result |= (ptr[ 3 - (idx + i)] << (8*i)); } return result; #endif } void wlan_pci_isr() { if (g_wlan_intr != NULL && g_wlan_drv_handle != NULL) { g_wlan_intr(g_wlan_drv_handle); } } open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/wlan/wlan_pci.h000077500000000000000000000043321321570333100325620ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * @File: wlan_pci.h * * @Abstract: * * @Notes: */ #ifndef _WLAN_PCI_H #define _WLAN_PCI_H #include #include typedef int (*A_PCI_INIT_FUNC)(void); //extern A_PCI_INIT_FUNC g_pci_init_func; void wlan_pci_module_init(void); void wlan_pci_register_drv(adf_drv_info_t *drv); void wlan_pci_probe(void); int wlan_pci_config_write(int offset, a_uint32_t val, int width); int wlan_pci_config_read(int offset, int width); void wlan_pci_isr(); #endif /* #ifndef _WLAN_PCI_H */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/wmi/000077500000000000000000000000001321570333100304435ustar00rootroot00000000000000wmi_internal.h000077500000000000000000000072141321570333100332340ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/wmi/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * @File: * * @Abstract: internal data and structure definitions for WMI service * * @Notes: */ #ifndef WMI_INTERNAL_H_ #define WMI_INTERNAL_H_ #define WMI_CMD_ALIGNMENT_SIZE 128 #ifdef WMI_DEBUG /* WMI debug log definitions */ #define WMI_DBG0_LOG(debugid) \ DBGLOG_ARG0_RECORD(DBGLOG_HEADER_UPPER_HALF(debugid, \ DBGLOG_MODULEID_WMI, 0)) #define WMI_DBG1_LOG(debugid, arg1) \ DBGLOG_ARG1_RECORD(DBGLOG_HEADER_UPPER_HALF(debugid, \ DBGLOG_MODULEID_WMI, 1), arg1) #define WMI_DBG2_LOG(debugid, arg1, arg2) \ DBGLOG_ARG2_RECORD(DBGLOG_HEADER_UPPER_HALF(debugid, \ DBGLOG_MODULEID_WMI, 2), arg1, arg2) #else #define WMI_DBG0_LOG(debugid) #define WMI_DBG1_LOG(debugid, arg1) #define WMI_DBG2_LOG(debugid, arg1, arg2) #endif /* WMI_DEBUG */ #define EVT_PKT_IN_USE (1 << 0) #define EVT_PKT_IS_FREE(e) !((e)->Flags & EVT_PKT_IN_USE) #define EVT_MARK_FREE(e) (e)->Flags &= ~EVT_PKT_IN_USE; #define EVT_MARK_INUSE(e) (e)->Flags |= EVT_PKT_IN_USE #define IS_EVT_CLASS_BUFFERED(ec) ((ec) != WMI_EVT_CLASS_DIRECT_BUFFER) typedef struct _WMI_POOL_STATE { int MaxAllocation; /* maximum allocations allowed for this pool */ int CurrentAllocation; /* current allocations outstanding */ } WMI_POOL_STATE; typedef struct _WMI_SVC_CONTEXT { htc_handle_t HtcHandle; pool_handle_t PoolHandle; int PendingEvents; /* no. of pending events */ HTC_SERVICE WMIControlService; /* registered control service */ HTC_ENDPOINT_ID ControlEp; /* endpoint assigned to us */ WMI_DISPATCH_TABLE *pDispatchHead; /* dispatch list head ptr */ WMI_DISPATCH_TABLE *pDispatchTail; /* dispatch list tail ptr */ // Left a door for extension the structure void *pReserved; } WMI_SVC_CONTEXT; #endif /*WMI_INTERNAL_H_*/ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/wmi/wmi_svc.c000077500000000000000000000222731321570333100322670ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * @File: * * @Abstract: Wireless Module Interface Service Implementation * * @Notes: */ #include #include #include #include #include #include #include #include "wmi_internal.h" static void WMIRecvMessageHandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf, adf_nbuf_t pHTCBuf, void *arg) { void *pContext; WMI_SVC_CONTEXT *pWMI = (WMI_SVC_CONTEXT *)arg; WMI_DISPATCH_TABLE *pCurrentTable; WMI_DISPATCH_ENTRY*pCurrentEntry; WMI_CMD_HANDLER pCmdHandler; A_UINT8* pCmdBuffer; int i; A_UINT16 cmd; A_UINT16 seq; int length; a_uint8_t *anbdata; a_uint32_t anblen; WMI_CMD_HDR *cmdHdr; adf_os_assert(hdr_buf == ADF_NBUF_NULL); do { length = adf_nbuf_len(pHTCBuf); if (length < sizeof(WMI_CMD_HDR)) { break; } adf_nbuf_peek_header(pHTCBuf, &anbdata, &anblen); pCurrentTable = pWMI->pDispatchHead; length = length - sizeof(WMI_CMD_HDR); cmdHdr = (WMI_CMD_HDR *)anbdata; cmd = adf_os_ntohs(cmdHdr->commandId); seq = adf_os_ntohs(cmdHdr->seqNo); pCmdBuffer = anbdata + sizeof(WMI_CMD_HDR); pCmdHandler = NULL; while (pCurrentTable != NULL) { pContext = pCurrentTable->pContext; pCurrentEntry = pCurrentTable->pTable; /* scan table entries */ for (i = 0; i < pCurrentTable->NumberOfEntries; i++, pCurrentEntry++) { if (pCurrentEntry->CmdID == cmd) { /* found a match */ pCmdHandler = pCurrentEntry->pCmdHandler; /* optionally check length */ if ((pCurrentEntry->CheckLength != 0) && (length < pCurrentEntry->CheckLength)) { /* do not process command */ pCmdHandler = NULL; } /* end search */ break; } } if (pCmdHandler != NULL) { /* found a handler */ break; } /* scan next table */ pCurrentTable = pCurrentTable->pNext; } if (NULL == pCmdHandler) { break; } /* if we get here, we have a command handler to dispatch */ /* call dispatch function */ pCmdHandler(pContext, cmd, seq, pCmdBuffer, length); } while (FALSE); /* Invalidate the buffer (including HTC header). Note : we only need to invalidate up to the portion * that was used (cache invalidate will also round up to the nearest cache line). * The rest of the buffer should still be coherent. * */ HTC_ReturnBuffers(pWMI->HtcHandle, EndPt, pHTCBuf); } /* send completion handler when any HTC buffers are returned */ static void _WMI_SendCompleteHandler(HTC_ENDPOINT_ID Endpt, adf_nbuf_t pHTCBuf, void *arg) { WMI_SVC_CONTEXT *pWMI = (WMI_SVC_CONTEXT *)arg; WMI_BUF_CONTEXT *ctx; BUF_POOL_ID poolId; ctx = (WMI_BUF_CONTEXT *)adf_nbuf_get_priv(pHTCBuf); if ( ctx->EventClass == WMI_EVT_CLASS_CMD_EVENT ) { poolId = POOL_ID_WMI_SVC_EVENT; } else { poolId = POOL_ID_WMI_SVC_CMD_REPLY; } BUF_Pool_free_buf(pWMI->PoolHandle, poolId, pHTCBuf); } static A_UINT8 WMIServiceConnect(HTC_SERVICE *pService, HTC_ENDPOINT_ID eid, A_UINT8 *pDataIn, int LengthIn, A_UINT8 *pDataOut, int *pLengthOut) { WMI_SVC_CONTEXT *pWMI = (WMI_SVC_CONTEXT *)pService->ServiceCtx; /* save the eid to use */ pWMI->ControlEp = eid; return HTC_SERVICE_SUCCESS; } /************** public APIS ********************************************/ static wmi_handle_t _WMI_Init(WMI_SVC_CONFIG *pWmiConfig) { WMI_SVC_CONTEXT *pWMI = NULL; int eventSize = WMI_SVC_MAX_BUFFERED_EVENT_SIZE + sizeof(WMI_CMD_HDR) + HTC_HDR_SZ; pWMI = (WMI_SVC_CONTEXT *)adf_os_mem_alloc(sizeof(WMI_SVC_CONTEXT)); if (pWMI == NULL) { return NULL; } pWMI->pDispatchHead = NULL; pWMI->PoolHandle = pWmiConfig->PoolHandle; pWMI->HtcHandle = pWmiConfig->HtcHandle; BUF_Pool_create_pool(pWmiConfig->PoolHandle, POOL_ID_WMI_SVC_CMD_REPLY, pWmiConfig->MaxCmdReplyEvts, eventSize); BUF_Pool_create_pool(pWmiConfig->PoolHandle, POOL_ID_WMI_SVC_EVENT, pWmiConfig->MaxEventEvts, eventSize); /* NOTE: since RAM allocation is zero-initialized, there is nothing to do for the * direct event pool */ /* register the WMI control service */ pWMI->WMIControlService.ProcessRecvMsg = A_INDIR(wmi_svc_api._WMI_RecvMessageHandler); pWMI->WMIControlService.ProcessSendBufferComplete = A_INDIR(wmi_svc_api._WMI_SendCompleteHandler); pWMI->WMIControlService.ProcessConnect = A_INDIR(wmi_svc_api._WMI_ServiceConnect); pWMI->WMIControlService.MaxSvcMsgSize = WMI_SVC_MSG_SIZE + sizeof(WMI_CMD_HDR); /* all buffers that are sent through the control endpoint are at least WMI_SVC_MAX_BUFFERED_EVENT_SIZE * in size. Any WMI event that supplies a data buffer must insure that the space in the buffer * is at least this size. */ pWMI->WMIControlService.TrailerSpcCheckLimit = WMI_SVC_MAX_BUFFERED_EVENT_SIZE; pWMI->WMIControlService.ServiceID = WMI_CONTROL_SVC; pWMI->WMIControlService.ServiceCtx = pWMI; HTC_RegisterService(pWmiConfig->HtcHandle, &pWMI->WMIControlService); return pWMI; } static int _WMI_GetPendingEventsCount(wmi_handle_t handle) { WMI_SVC_CONTEXT *pWMI = (WMI_SVC_CONTEXT *)handle; return pWMI->PendingEvents; } static int _WMI_GetControlEp(wmi_handle_t handle) { WMI_SVC_CONTEXT *pWMI = (WMI_SVC_CONTEXT *)handle; return pWMI->ControlEp; } static void _WMI_RegisterDispatchTable(wmi_handle_t handle, WMI_DISPATCH_TABLE *pDispatchTable) { WMI_SVC_CONTEXT *pWMI = (WMI_SVC_CONTEXT *)handle; if (NULL == pWMI->pDispatchHead) { pWMI->pDispatchHead = pDispatchTable; pWMI->pDispatchTail = pDispatchTable; } else { /* link to the tail */ pWMI->pDispatchTail->pNext = pDispatchTable; pWMI->pDispatchTail = pDispatchTable; } } static adf_nbuf_t _WMI_AllocEvent(wmi_handle_t handle, WMI_EVT_CLASS EventClass, int Length) { BUF_POOL_ID poolId; WMI_SVC_CONTEXT *pWMI = (WMI_SVC_CONTEXT *)handle; adf_nbuf_t buf; WMI_BUF_CONTEXT *ctx; if ( EventClass == WMI_EVT_CLASS_CMD_EVENT ) { poolId = POOL_ID_WMI_SVC_EVENT; } else { poolId = POOL_ID_WMI_SVC_CMD_REPLY; } buf = BUF_Pool_alloc_buf(pWMI->PoolHandle, poolId, sizeof(WMI_CMD_HDR) + HTC_GetReservedHeadroom(pWMI->HtcHandle)); if ( buf != NULL ) { ctx = (WMI_BUF_CONTEXT *)adf_nbuf_get_priv(buf); ctx->EventClass = EventClass; } return buf; } static void _WMI_SendEvent(wmi_handle_t handle, adf_nbuf_t pEvt, A_UINT16 EventId, A_UINT16 SeqNo, int Length) { WMI_SVC_CONTEXT *pWMI = (WMI_SVC_CONTEXT *)handle; A_UINT8 *pBuffer; pBuffer = adf_nbuf_push_head(pEvt, sizeof(WMI_CMD_HDR)); A_SET_UINT16_FIELD(pBuffer, WMI_CMD_HDR, commandId, adf_os_htons(EventId)); A_SET_UINT16_FIELD(pBuffer, WMI_CMD_HDR, seqNo, adf_os_htons(SeqNo)); HTC_SendMsg(pWMI->HtcHandle, pWMI->ControlEp, pEvt); } static void _WMI_Shutdown(wmi_handle_t handle) { WMI_SVC_CONTEXT *pWMI = (WMI_SVC_CONTEXT *)handle; adf_os_mem_free(pWMI); } void WMI_service_module_install(WMI_SVC_APIS *pTbl) { pTbl->_WMI_Init = _WMI_Init; pTbl->_WMI_RegisterDispatchTable = _WMI_RegisterDispatchTable; pTbl->_WMI_AllocEvent = _WMI_AllocEvent; pTbl->_WMI_SendEvent = _WMI_SendEvent; pTbl->_WMI_SendCompleteHandler = _WMI_SendCompleteHandler; pTbl->_WMI_GetPendingEventsCount = _WMI_GetPendingEventsCount; pTbl->_WMI_GetControlEp = _WMI_GetControlEp; pTbl->_WMI_Shutdown = _WMI_Shutdown; pTbl->_WMI_RecvMessageHandler = WMIRecvMessageHandler; pTbl->_WMI_ServiceConnect = WMIServiceConnect; } wmi_svc_api.h000077500000000000000000000135641321570333100330510ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/magpie_fw_dev/target/wmi/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * This file contains the API for the Wireless Module Interface (WMI) Service */ #ifndef WMI_SVC_API_H_ #define WMI_SVC_API_H_ #include #include #include #include #include #define WMI_SVC_MAX_BUFFERED_EVENT_SIZE 100 #define WMI_SVC_MSG_SIZE 1536 /* maximum size of any WMI control or event message */ /* event classes */ typedef enum WMI_EVT_CLASS { WMI_EVT_CLASS_NONE = -1, WMI_EVT_CLASS_CMD_EVENT = 0, WMI_EVT_CLASS_CMD_REPLY = 1, WMI_EVT_CLASS_MAX } WMI_EVT_CLASS; /* command handler callback when a message is dispatched */ typedef void (* WMI_CMD_HANDLER)(void *pContext, /* application supplied context from dispatch table */ A_UINT16 Command, /* command ID that was dispatched */ A_UINT16 SeqNo, A_UINT8 *pCmdBuffer, /* command data, 256 bytes max, 32-bit aligned */ int Length); /* length of command (excludes WMI header) */ /* configuration settings for the WMI service */ typedef struct _WMI_SVC_CONFIG { htc_handle_t HtcHandle; pool_handle_t PoolHandle; int MaxCmdReplyEvts; /* total buffers for command replies */ int MaxEventEvts; /* total buffers for low priority events */ } WMI_SVC_CONFIG; /* command dispatch entry */ typedef struct _WMI_DISPATCH_ENTRY { WMI_CMD_HANDLER pCmdHandler; /* dispatch function */ A_UINT16 CmdID; /* WMI command to dispatch from */ A_UINT16 CheckLength; /* expected length of command, set to 0 to bypass check */ } WMI_DISPATCH_ENTRY; /* dispatch table that is used to register a set of dispatch entries */ typedef struct _WMI_DISPATCH_TABLE { struct _WMI_DISPATCH_TABLE *pNext; /* next dispatch, WMI-reserved */ void *pContext; /* optional context that is passed to command handlers assigned to this dispatch table */ int NumberOfEntries; /* number of elements pointed to by pTable */ WMI_DISPATCH_ENTRY *pTable; /* start of table */ } WMI_DISPATCH_TABLE; #define WMI_DISPATCH_ENTRY_COUNT(table) \ (sizeof((table)) / sizeof(WMI_DISPATCH_ENTRY)) /* handy macro to declare a dispatch table */ #define WMI_DECLARE_DISPATCH_TABLE(name,dispatchEntries) \ WMI_DISPATCH_TABLE name = \ { NULL, NULL, WMI_DISPATCH_ENTRY_COUNT(dispatchEntries), dispatchEntries } /* macro to programatically set the dispatch table context */ #define WMI_SET_DISPATCH_CONTEXT(pDispTable, pCtxt) (pDispTable)->pContext = (pCtxt) typedef struct _WMI_BUF_CONTEXT { HTC_BUF_CONTEXT HtcBufCtx; WMI_EVT_CLASS EventClass; /* the event class this packet belongs to */ A_UINT16 Flags; /* internal flags reserved for WMI */ } WMI_BUF_CONTEXT; /* ROM-version, eventually. For now, in RAM */ typedef void* wmi_handle_t; /* the API table */ typedef struct _wmi_svc_apis { wmi_handle_t (* _WMI_Init)(WMI_SVC_CONFIG *pWmiConfig); void (* _WMI_RegisterDispatchTable)(wmi_handle_t h, WMI_DISPATCH_TABLE *pDispatchTable); adf_nbuf_t (* _WMI_AllocEvent)(wmi_handle_t h, WMI_EVT_CLASS EventClass, int Length); void (* _WMI_SendEvent)(wmi_handle_t h, adf_nbuf_t pEvt, A_UINT16 EventId, A_UINT16 SeqNo, int Length); int (* _WMI_GetPendingEventsCount)(wmi_handle_t handle); void (* _WMI_SendCompleteHandler)(HTC_ENDPOINT_ID Endpt, adf_nbuf_t pHTCBuf, void *arg); int (* _WMI_GetControlEp)(wmi_handle_t h); void (* _WMI_Shutdown)(wmi_handle_t h); /* */ void (*_WMI_RecvMessageHandler)(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf, adf_nbuf_t pHTCBuf, void *arg); A_UINT8 (*_WMI_ServiceConnect)(HTC_SERVICE *pService, HTC_ENDPOINT_ID eid, A_UINT8 *pDataIn, int LengthIn, A_UINT8 *pDataOut, int *pLengthOut); void *pReserved; /* for expansion if need be */ } WMI_SVC_APIS; extern void WMI_service_module_install(WMI_SVC_APIS *pAPIs); #endif /*WMI_SVC_API_H_*/ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/ram-k2.ld000077500000000000000000000176511321570333100252140ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* Linker script for Magpie RAM-based applications */ /* Currently, ROM code reserves the first 8KB of RAM for its data/bss. The next 12KB or RAM is used for RAM software's literals and read-only data. After that comes 64KB reserved for RAM software's data and bss. Then 92KB of RAM is reserved for text (code). The last 8KB of RAM is reserved for ROM patches, customer DataSets, and RAM software expansion. (There is also some additional RAM between segments that can be used, if needed.) ROM reserved: 0x00500000..0x00501fff Literals: 0x00502000..0x00504fff Data: 0x00505000..0x00514fff Text: 0x00915000..0x0092bfff TBD: May want to use a 2-pass link approach in order to eliminate fixed boundaries. Support for physical addressing in Tensilica tools would be helpful, but it's not coming any time soon. */ /* dram_seg: 0x504000, see target.rom.ld */ /* ***** */ MEMORY { lit_seg : org = 0x004E5200, len = 0x1DE00 iram_seg : org = 0x00903000, len = 0x9B40 dram_seg : org = 0x0050CB40, len = 0x1800 } PHDRS { lit_phdr PT_LOAD; dram_phdr PT_LOAD; iram_phdr PT_LOAD; } /* Default entry point: */ ENTRY(app_start) SECTIONS { /* * This empty section is used to convince RAM linkage * to share litbase with ROM code. */ .lit4 (NOLOAD) : { _rom_literal_start = ABSOLUTE(.); . += 0x1BE00; /* Reserved virtual space for physical mem gap and ROM */ _lit4_start = ABSOLUTE(.); _lit4_end = ABSOLUTE(.); _rom_literal_end = ABSOLUTE(.); } >lit_seg :NONE .dport0.rodata : { _dport0_rodata_start = ABSOLUTE(.); /* 0x505000 */ *(.dport0.rodata) *(.dport.rodata) _dport0_rodata_end = ABSOLUTE(.); } >lit_seg :lit_phdr .dport0.literal : { _dport0_literal_start = ABSOLUTE(.); *(.dport0.literal) *(.dport.literal) _dport0_literal_end = ABSOLUTE(.); } >lit_seg :lit_phdr .dram0.rodata : { _dram0_rodata_start = ABSOLUTE(.); *(.dram0.rodata) *(.dram.rodata) _dram0_rodata_end = ABSOLUTE(.); } >lit_seg :lit_phdr .rodata : { _rodata_start = ABSOLUTE(.); *(.rodata) *(.rodata.*) *(.gnu.linkonce.r.*) *(.rodata1) __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); *(.xt_except_table) *(.gcc_except_table) *(.gnu.linkonce.e.*) *(.gnu.version_r) . = ALIGN(4); /* this table MUST be 4-byte aligned */ _bss_table_start = ABSOLUTE(.); LONG(_dport0_bss_start) LONG(_dport0_bss_end) LONG(_bss_start) LONG(_bss_end) _bss_table_end = ABSOLUTE(.); _rodata_end = ABSOLUTE(.); } >lit_seg :lit_phdr .literals : { _literals_start = ABSOLUTE(.); *(*.lit4) *(.gnu.linkonce.lit4.*) _literals_end = ABSOLUTE(.); } >lit_seg :lit_phdr .dram0.literal : { _dram0_literal_start = ABSOLUTE(.); *(.dram0.literal) *(.dram.literal) _dram0_literal_end = ABSOLUTE(.); } >lit_seg :lit_phdr .dport0.data : { _dport0_data_start = ABSOLUTE(.); *(.dport0.data) *(.dport.data) _dport0_data_end = ABSOLUTE(.); } >dram_seg :dram_phdr .dport0.bss : { . = ALIGN (8); _dport0_bss_start = ABSOLUTE(.); *(.dport0.bss) . = ALIGN (8); _dport0_bss_end = ABSOLUTE(.); } >dram_seg :dram_phdr .dram0.data : { _dram0_data_start = ABSOLUTE(.); *(.dram0.data) *(.dram.data) _dram0_data_end = ABSOLUTE(.); } >dram_seg :dram_phdr .data : { _data_start = ABSOLUTE(.); *(.data) *(.data.*) *(.gnu.linkonce.d.*) *(.data1) *(.sdata) *(.sdata.*) *(.gnu.linkonce.s.*) *(.sdata2) *(.sdata2.*) *(.gnu.linkonce.s2.*) *(.jcr) *(.eh_frame) /* C++ constructor and destructor tables, properly ordered: */ KEEP (*crtbegin.o(.ctors)) KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) KEEP (*crtbegin.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) /* C++ exception handlers table: */ __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); *(.xt_except_desc) *(.gnu.linkonce.h.*) __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); *(.xt_except_desc_end) *(.dynamic) *(.gnu.version_d) _data_end = ABSOLUTE(.); } >dram_seg :dram_phdr .bss : { . = ALIGN (8); _bss_start = ABSOLUTE(.); *(.dynsbss) *(.sbss) *(.sbss.*) *(.gnu.linkonce.sb.*) *(.scommon) *(.sbss2) *(.sbss2.*) *(.gnu.linkonce.sb2.*) *(.dynbss) *(.bss) *(.bss.*) *(.gnu.linkonce.b.*) *(COMMON) *(.dram0.bss) . = ALIGN (8); _bss_end = ABSOLUTE(.); _end = ALIGN(0x8); PROVIDE(end = ALIGN(0x8)); _fw_image_end = ABSOLUTE(.); /*_stack_sentry = ALIGN(0x8);*/ } >dram_seg :dram_phdr .boot : { *(.boot) } > iram_seg :iram_phdr .text : { _stext = .; _text_start = ABSOLUTE(.); *(.entry.text) *(.init.literal) *(.init) *(.literal .text .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) *(.fini.literal) *(.fini) *(.gnu.version) _text_end = ABSOLUTE(.); _etext = .; } >iram_seg :iram_phdr .iram0.text : { _iram0_text_start = ABSOLUTE(.); *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) _iram0_text_end = ABSOLUTE(.); } >iram_seg :iram_phdr .debug 0 : { *(.debug) } .line 0 : { *(.line) } .debug_srcinfo 0 : { *(.debug_srcinfo) } .debug_sfnames 0 : { *(.debug_sfnames) } .debug_aranges 0 : { *(.debug_aranges) } .debug_pubnames 0 : { *(.debug_pubnames) } .debug_info 0 : { *(.debug_info) } .debug_abbrev 0 : { *(.debug_abbrev) } .debug_line 0 : { *(.debug_line) } .debug_frame 0 : { *(.debug_frame) } .debug_str 0 : { *(.debug_str) } .debug_loc 0 : { *(.debug_loc) } .debug_macinfo 0 : { *(.debug_macinfo) } .debug_weaknames 0 : { *(.debug_weaknames) } .debug_funcnames 0 : { *(.debug_funcnames) } .debug_typenames 0 : { *(.debug_typenames) } .debug_varnames 0 : { *(.debug_varnames) } .xt.insn 0 : { KEEP (*(.xt.insn)) KEEP (*(.gnu.linkonce.x.*)) } .xt.prop 0 : { KEEP (*(.xt.prop)) KEEP (*(.gnu.linkonce.prop.*)) } .xt.lit 0 : { KEEP (*(.xt.lit)) KEEP (*(.gnu.linkonce.p.*)) } } open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/ram-magpie.ld000077500000000000000000000176521321570333100261430ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* Linker script for Magpie RAM-based applications */ /* Currently, ROM code reserves the first 8KB of RAM for its data/bss. The next 12KB or RAM is used for RAM software's literals and read-only data. After that comes 64KB reserved for RAM software's data and bss. Then 92KB of RAM is reserved for text (code). The last 8KB of RAM is reserved for ROM patches, customer DataSets, and RAM software expansion. (There is also some additional RAM between segments that can be used, if needed.) ROM reserved: 0x00500000..0x00501fff Literals: 0x00502000..0x00504fff Data: 0x00505000..0x00514fff Text: 0x00915000..0x0092bfff TBD: May want to use a 2-pass link approach in order to eliminate fixed boundaries. Support for physical addressing in Tensilica tools would be helpful, but it's not coming any time soon. */ /* dram_seg: 0x504000, see target.rom.ld */ /* ***** */ MEMORY { lit_seg : org = 0x004E8000, len = 0x1f600 iram_seg : org = 0x00906000, len = 0xad00 dram_seg : org = 0x00510d00, len = 0x6000 } PHDRS { lit_phdr PT_LOAD; dram_phdr PT_LOAD; iram_phdr PT_LOAD; } /* Default entry point: */ ENTRY(app_start) SECTIONS { /* * This empty section is used to convince RAM linkage * to share litbase with ROM code. */ .lit4 (NOLOAD) : { _rom_literal_start = ABSOLUTE(.); . += 0x19000; /* Reserved virtual space for physical mem gap and ROM */ _lit4_start = ABSOLUTE(.); _lit4_end = ABSOLUTE(.); _rom_literal_end = ABSOLUTE(.); } >lit_seg :NONE .dport0.rodata : { _dport0_rodata_start = ABSOLUTE(.); /* 0x505000 */ *(.dport0.rodata) *(.dport.rodata) _dport0_rodata_end = ABSOLUTE(.); } >lit_seg :lit_phdr .dport0.literal : { _dport0_literal_start = ABSOLUTE(.); *(.dport0.literal) *(.dport.literal) _dport0_literal_end = ABSOLUTE(.); } >lit_seg :lit_phdr .dram0.rodata : { _dram0_rodata_start = ABSOLUTE(.); *(.dram0.rodata) *(.dram.rodata) _dram0_rodata_end = ABSOLUTE(.); } >lit_seg :lit_phdr .rodata : { _rodata_start = ABSOLUTE(.); *(.rodata) *(.rodata.*) *(.gnu.linkonce.r.*) *(.rodata1) __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); *(.xt_except_table) *(.gcc_except_table) *(.gnu.linkonce.e.*) *(.gnu.version_r) . = ALIGN(4); /* this table MUST be 4-byte aligned */ _bss_table_start = ABSOLUTE(.); LONG(_dport0_bss_start) LONG(_dport0_bss_end) LONG(_bss_start) LONG(_bss_end) _bss_table_end = ABSOLUTE(.); _rodata_end = ABSOLUTE(.); } >lit_seg :lit_phdr .literals : { _literals_start = ABSOLUTE(.); *(*.lit4) *(.gnu.linkonce.lit4.*) _literals_end = ABSOLUTE(.); } >lit_seg :lit_phdr .dram0.literal : { _dram0_literal_start = ABSOLUTE(.); *(.dram0.literal) *(.dram.literal) _dram0_literal_end = ABSOLUTE(.); } >lit_seg :lit_phdr .dport0.data : { _dport0_data_start = ABSOLUTE(.); *(.dport0.data) *(.dport.data) _dport0_data_end = ABSOLUTE(.); } >dram_seg :dram_phdr .dport0.bss : { . = ALIGN (8); _dport0_bss_start = ABSOLUTE(.); *(.dport0.bss) . = ALIGN (8); _dport0_bss_end = ABSOLUTE(.); } >dram_seg :dram_phdr .dram0.data : { _dram0_data_start = ABSOLUTE(.); *(.dram0.data) *(.dram.data) _dram0_data_end = ABSOLUTE(.); } >dram_seg :dram_phdr .data : { _data_start = ABSOLUTE(.); *(.data) *(.data.*) *(.gnu.linkonce.d.*) *(.data1) *(.sdata) *(.sdata.*) *(.gnu.linkonce.s.*) *(.sdata2) *(.sdata2.*) *(.gnu.linkonce.s2.*) *(.jcr) *(.eh_frame) /* C++ constructor and destructor tables, properly ordered: */ KEEP (*crtbegin.o(.ctors)) KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) KEEP (*crtbegin.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) /* C++ exception handlers table: */ __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); *(.xt_except_desc) *(.gnu.linkonce.h.*) __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); *(.xt_except_desc_end) *(.dynamic) *(.gnu.version_d) _data_end = ABSOLUTE(.); } >dram_seg :dram_phdr .bss : { . = ALIGN (8); _bss_start = ABSOLUTE(.); *(.dynsbss) *(.sbss) *(.sbss.*) *(.gnu.linkonce.sb.*) *(.scommon) *(.sbss2) *(.sbss2.*) *(.gnu.linkonce.sb2.*) *(.dynbss) *(.bss) *(.bss.*) *(.gnu.linkonce.b.*) *(COMMON) *(.dram0.bss) . = ALIGN (8); _bss_end = ABSOLUTE(.); _end = ALIGN(0x8); PROVIDE(end = ALIGN(0x8)); _fw_image_end = ABSOLUTE(.); /*_stack_sentry = ALIGN(0x8);*/ } >dram_seg :dram_phdr .boot : { *(.boot) } > iram_seg :iram_phdr .text : { _stext = .; _text_start = ABSOLUTE(.); *(.entry.text) *(.init.literal) *(.init) *(.literal .text .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) *(.fini.literal) *(.fini) *(.gnu.version) _text_end = ABSOLUTE(.); _etext = .; } >iram_seg :iram_phdr .iram0.text : { _iram0_text_start = ABSOLUTE(.); *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) _iram0_text_end = ABSOLUTE(.); } >iram_seg :iram_phdr .debug 0 : { *(.debug) } .line 0 : { *(.line) } .debug_srcinfo 0 : { *(.debug_srcinfo) } .debug_sfnames 0 : { *(.debug_sfnames) } .debug_aranges 0 : { *(.debug_aranges) } .debug_pubnames 0 : { *(.debug_pubnames) } .debug_info 0 : { *(.debug_info) } .debug_abbrev 0 : { *(.debug_abbrev) } .debug_line 0 : { *(.debug_line) } .debug_frame 0 : { *(.debug_frame) } .debug_str 0 : { *(.debug_str) } .debug_loc 0 : { *(.debug_loc) } .debug_macinfo 0 : { *(.debug_macinfo) } .debug_weaknames 0 : { *(.debug_weaknames) } .debug_funcnames 0 : { *(.debug_funcnames) } .debug_typenames 0 : { *(.debug_typenames) } .debug_varnames 0 : { *(.debug_varnames) } .xt.insn 0 : { KEEP (*(.xt.insn)) KEEP (*(.gnu.linkonce.x.*)) } .xt.prop 0 : { KEEP (*(.xt.prop)) KEEP (*(.gnu.linkonce.prop.*)) } .xt.lit 0 : { KEEP (*(.xt.lit)) KEEP (*(.gnu.linkonce.p.*)) } } open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/rom-addrs-k2.ld000077500000000000000000000112171321570333100263150ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ PROVIDE ( _indir_tbl = 0x00500000 ); PROVIDE (athos_indirection_table_install = 0x008e1548); PROVIDE ( memcpy = 0x008e4eb8 ); PROVIDE ( memset = 0x008e519c ); PROVIDE ( __divsi3 = 0x008e4cec ); PROVIDE ( __udivsi3 = 0x008e4da0 ); PROVIDE ( __umodsi3 = 0x008e4df0 ); PROVIDE ( __modsi3 = 0x008e4d54 ); PROVIDE ( athos_interrupt_init = 0x008e1600 ); PROVIDE ( athos_unblock_all_intrlvl = 0x008e1460 ); PROVIDE ( athos_interrupt_handler = 0x008e15f0 ); PROVIDE ( _xtos_set_interrupt_handler = 0x008e1230 ); PROVIDE ( hif_module_install = 0x008e2bd4 ); PROVIDE ( strcmp = 0x008e48b4 ); PROVIDE ( strlen = 0x008e4a64 ); PROVIDE ( strcpy = 0x008e49cc ); PROVIDE ( strncpy = 0x008e4b90 ); PROVIDE ( Xthal_num_ccompare = 0x004e5869 ); PROVIDE ( cticks = 0x0050088c ); PROVIDE ( UsbDeviceDescriptor = 0x004e0100 ); PROVIDE ( String00Descriptor = 0x004e01a0 ); PROVIDE ( String10Descriptor = 0x004e01b0 ); PROVIDE ( String20Descriptor = 0x004e01c0 ); PROVIDE ( String30Descriptor = 0x004e01e0 ); PROVIDE ( HIFusb_DescTraceDump = 0x008e2c18 ); PROVIDE ( xthal_get_intenable = 0x008e4cd4 ); PROVIDE ( xthal_set_intenable = 0x008e4ce4 ); PROVIDE ( xthal_get_interrupt = 0x008e4cdc ); PROVIDE ( xthal_get_ccompare = 0x008e4cc4 ); PROVIDE ( xthal_set_ccompare = 0x008e4cb4 ); PROVIDE ( xthal_get_ccount = 0x008e4cac ); PROVIDE ( Xthal_num_ccompare = 0x004e5869 ); PROVIDE ( zfDmaReclaimPacket = 0x008e4568 ); PROVIDE ( zfDmaPutPacket = 0x008e45fc ); PROVIDE ( zfDmaGetPacket = 0x008e452c ); PROVIDE ( handle_hp_rx_complete_isr = 0x008e2b18 ); PROVIDE ( handle_mp_rx_complete_isr = 0x008e2b38 ); PROVIDE ( handle_tx_complete_isr = 0x008e2adc ); PROVIDE ( u16TxRxCounter = 0x005009e4 ); PROVIDE ( pu8DescriptorEX = 0x005009e0 ); PROVIDE ( fwCheckSum = 0x005009dc ); PROVIDE ( eUsbCxCommand = 0x005009f0 ); PROVIDE ( ControlCmd = 0x005009c0 ); PROVIDE ( eUsbCxFinishAction = 0x005009ec ); PROVIDE ( UsbChirpFinish = 0x005009f4 ); PROVIDE ( cmnos_allocram_debug = 0x008e1ae8 ); PROVIDE ( g_hifUSBCtx = 0x00500978 ); PROVIDE ( _HIFusb_return_recv_buf = 0x008e2a74 ); PROVIDE ( vdesc_module_install = 0x008e413c ); PROVIDE ( vbuf_module_install = 0x008e408c ); PROVIDE ( mUsbFIFOConfig = 0x008e3ca4 ); PROVIDE ( mUsbEPMxPtSzHigh = 0x008e3cc4 ); PROVIDE ( mUsbEPMxPtSzLow = 0x008e3cec ); PROVIDE ( mUsbEPinHighBandSet = 0x008e3d10 ); PROVIDE ( mUsbFIFOConfig = 0x008e3ca4 ); PROVIDE ( mUsbFIFOMap = 0x008e3c84 ); PROVIDE ( mUsbEPMap = 0x008e3c68 ); PROVIDE ( usbFifoConf = 0x005009cc ); PROVIDE ( u8UsbInterfaceValue = 0x005009f8 ); PROVIDE ( u8UsbConfigValue = 0x005009f6 ); PROVIDE ( u8UsbInterfaceAlternateSetting = 0x005009fa ); PROVIDE ( ControlCmd = 0x005009c0 ); PROVIDE ( vUsbFIFO_EPxCfg_HS = 0x008e3d5c ); PROVIDE ( vUsbClrEPx = 0x008e2d00 ); PROVIDE ( bSet_configuration = 0x008e2f7c ); PROVIDE ( _HIFusb_isr_handler = 0x008e2b58 ); PROVIDE ( bGet_descriptor = 0x008e2ec4 ); PROVIDE ( u8ConfigDescriptorEX = 0x005009e8 ); PROVIDE ( bStandardCommand = 0x008e328c ); PROVIDE ( u8UsbDeviceDescriptor = 0x00500a00 ); open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/rom-addrs-magpie.ld000077500000000000000000000114221321570333100272410ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ PROVIDE ( _indir_tbl = 0x00500000 ); PROVIDE ( memcpy = 0x008e6b64 ); PROVIDE ( memset = 0x008e6e48 ); PROVIDE ( __divsi3 = 0x008e6998 ); PROVIDE ( __udivsi3 = 0x008e6a4c ); PROVIDE ( __umodsi3 = 0x008e6a9c ); PROVIDE ( __modsi3 = 0x008e6a00 ); PROVIDE ( athos_interrupt_init = 0x008e1614 ); PROVIDE ( athos_unblock_all_intrlvl = 0x008e1460 ); PROVIDE ( athos_interrupt_handler = 0x008e1604 ); PROVIDE ( _xtos_set_interrupt_handler = 0x008e1230 ); PROVIDE ( generic_hif_module_install = 0x008e1548 ); PROVIDE ( htc_module_install = 0x008e54a8 ); PROVIDE ( buf_pool_module_install = 0x008e6264 ); PROVIDE ( vbuf_module_install = 0x008e4f60 ); PROVIDE ( vdesc_module_install = 0x008e5010 ); PROVIDE ( strcmp = 0x008e6560 ); PROVIDE ( strlen = 0x008e6710 ); PROVIDE ( strcpy = 0x008e6678 ); PROVIDE ( strncpy = 0x008e683c ); PROVIDE ( Xthal_num_ccompare = 0x004e87f9 ); PROVIDE ( cticks = 0x0050095c ); PROVIDE ( UsbDeviceDescriptor = 0x004e0100 ); PROVIDE ( String00Descriptor = 0x004e01a0 ); PROVIDE ( String10Descriptor = 0x004e01b0 ); PROVIDE ( String20Descriptor = 0x004e01c0 ); PROVIDE ( String30Descriptor = 0x004e01e0 ); PROVIDE ( HIFusb_DescTraceDump = 0x008e37e8 ); PROVIDE ( xthal_get_intenable = 0x008e6980 ); PROVIDE ( xthal_set_intenable = 0x008e6990 ); PROVIDE ( xthal_get_interrupt = 0x008e6988 ); PROVIDE ( xthal_get_ccompare = 0x008e6970 ); PROVIDE ( xthal_set_ccompare = 0x008e6960 ); PROVIDE ( xthal_get_ccount = 0x008e6958 ); PROVIDE ( Xthal_num_ccompare = 0x004e87f9 ); PROVIDE ( zfDmaReclaimPacket = 0x008e5d2c ); PROVIDE ( zfDmaPutPacket = 0x008e5dc0 ); PROVIDE ( zfDmaGetPacket = 0x008e5cf0 ); PROVIDE ( fwd_init = 0x008e5e78 ); PROVIDE ( usbFifoConf = 0x00500aa4 ); PROVIDE ( _HIFusb_isr_handler = 0x008e36e4 ); PROVIDE ( mUsbFIFOConfig = 0x008e4934 ); PROVIDE ( mUsbEPMxPtSzHigh = 0x008e4954 ); PROVIDE ( mUsbEPMxPtSzLow = 0x008e497c ); PROVIDE ( mUsbEPinHighBandSet = 0x008e49a0 ); PROVIDE ( mUsbFIFOConfig = 0x008e4934 ); PROVIDE ( mUsbFIFOMap = 0x008e4914 ); PROVIDE ( mUsbEPMap = 0x008e48f8 ); PROVIDE ( u8UsbInterfaceValue = 0x00500ad0 ); PROVIDE ( u8UsbConfigValue = 0x00500ace ); PROVIDE ( u8UsbInterfaceAlternateSetting = 0x00500ad2 ); PROVIDE ( ControlCmd = 0x00500a98 ); PROVIDE ( vUsbFIFO_EPxCfg_HS = 0x008e49ec ); PROVIDE ( vUsbClrEPx = 0x008e38d0 ); PROVIDE ( bSet_configuration = 0x008e3b54 ); PROVIDE ( eUsbCxFinishAction = 0x00500ac4 ); PROVIDE ( pci_sc = 0x00500708 ); PROVIDE ( __pci_reap_recv = 0x008e31e8 ); PROVIDE ( __pci_reap_xmitted = 0x008e31bc ); PROVIDE ( _HIFusb_start = 0x008e34a0 ); PROVIDE ( g_hifUSBCtx = 0x00500a54 ); PROVIDE ( _HIFusb_return_recv_buf = 0x008e367c ); PROVIDE ( athos_indirection_table_install = 0x008e1574 ); PROVIDE ( u8ConfigDescriptorEX = 0x00500ac0 ); PROVIDE ( bStandardCommand = 0x008e3e64 ); PROVIDE ( u16TxRxCounter = 0x00500abc ); PROVIDE ( pu8DescriptorEX = 0x00500ab8 ); PROVIDE ( bGet_descriptor = 0x008e3a9c ); PROVIDE ( _xtos_set_exception_handler = 0x008e6348 ); PROVIDE (HTCMsgRecvHandler = 0x008e581c); PROVIDE (HTCControlSvcProcessMsg = 0x008e56f4); PROVIDE (HTCFreeMsgBuffer = 0x008e54ec); PROVIDE ( u8UsbDeviceDescriptor = 0x00500ad8 ); open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/000077500000000000000000000000001321570333100245265ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/_ieee80211.h000077500000000000000000000071651321570333100263550ustar00rootroot00000000000000/*- * Copyright (c) 2001 Atsushi Onoe * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * Alternatively, this software may be distributed under the terms of the * GNU General Public License ("GPL") version 2 as published by the Free * Software Foundation. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD: src/sys/net80211/_ieee80211.h,v 1.2 2004/12/31 22:42:38 sam Exp $ * $Id: //depot/sw/branches/fusion_usb/target_firmware/wlan/target/madwifi/net80211/_ieee80211.h#1 $ */ #ifndef _NET80211__IEEE80211_H_ #define _NET80211__IEEE80211_H_ enum ieee80211_phytype { IEEE80211_T_DS, /* direct sequence spread spectrum */ IEEE80211_T_FH, /* frequency hopping */ IEEE80211_T_OFDM, /* frequency division multiplexing */ IEEE80211_T_TURBO, /* high rate OFDM, aka turbo mode */ IEEE80211_T_HT, /* HT - full GI */ IEEE80211_T_MAX }; #define IEEE80211_T_CCK IEEE80211_T_DS /* more common nomenclature */ /* XXX nOt really a mode; there are really multiple PHY's */ enum ieee80211_phymode { IEEE80211_MODE_11NA = 0, IEEE80211_MODE_11NG = 1, }; #define IEEE80211_MODE_MAX (IEEE80211_MODE_11NG+1) enum ieee80211_opmode { IEEE80211_M_STA = 1, /* infrastructure station */ IEEE80211_M_IBSS = 0, /* IBSS (adhoc) station */ IEEE80211_M_AHDEMO = 3, /* Old lucent compatible adhoc demo */ IEEE80211_M_HOSTAP = 6, /* Software Access Point */ IEEE80211_M_MONITOR = 8, /* Monitor mode */ IEEE80211_M_WDS = 2 /* WDS link */ }; /* * 802.11g protection mode. */ enum ieee80211_protmode { IEEE80211_PROT_NONE = 0, /* no protection */ IEEE80211_PROT_CTSONLY = 1, /* CTS to self */ IEEE80211_PROT_RTSCTS = 2, /* RTS-CTS */ }; /* * 802.11 rate set. */ #define IEEE80211_RATE_SIZE 8 /* 802.11 standard */ #define IEEE80211_RATE_MAXSIZE 30 /* max rates we'll handle */ #define IEEE80211_HT_RATE_SIZE 128 /* * 11n A-MPDU & A-MSDU limits */ #define IEEE80211_AMPDU_LIMIT_MIN (1 * 1024) #define IEEE80211_AMPDU_LIMIT_MAX (64 * 1024 - 1) #define IEEE80211_AMPDU_SUBFRAME_MIN 2 #define IEEE80211_AMPDU_SUBFRAME_MAX 64 #define IEEE80211_AMPDU_SUBFRAME_DEFAULT 32 #define IEEE80211_AMSDU_LIMIT_MAX 4096 struct ieee80211_rateset { a_uint8_t rs_nrates; a_uint8_t rs_rates[IEEE80211_RATE_MAXSIZE]; }; #endif /* _NET80211__IEEE80211_H_ */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/ah.c000077500000000000000000000126361321570333100252750ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "ah.h" #include "ah_internal.h" #include extern struct ath_hal *ar5416Attach(HAL_SOFTC sc, adf_os_device_t dev, HAL_STATUS *status); struct ath_hal* ath_hal_attach_tgt(a_uint32_t devid,HAL_SOFTC sc, adf_os_device_t dev, a_uint32_t flags, HAL_STATUS *error) { struct ath_hal *ah = AH_NULL; ah = ar5416Attach(sc, dev, error); return ah; } HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type) { const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; switch (type) { case HAL_CAP_TSF_ADJUST: return HAL_ENOTSUPP; case HAL_CAP_BSSIDMASK: return pCap->halBssIdMaskSupport ? HAL_OK : HAL_ENOTSUPP; case HAL_CAP_VEOL: return pCap->halVEOLSupport ? HAL_OK : HAL_ENOTSUPP; default: return HAL_EINVAL; } } #define CCK_SIFS_TIME 10 #define CCK_PREAMBLE_BITS 144 #define CCK_PLCP_BITS 48 #define OFDM_SIFS_TIME 16 #define OFDM_PREAMBLE_TIME 20 #define OFDM_PLCP_BITS 22 #define OFDM_SYMBOL_TIME 4 #define OFDM_SIFS_TIME_HALF 32 #define OFDM_PREAMBLE_TIME_HALF 40 #define OFDM_PLCP_BITS_HALF 22 #define OFDM_SYMBOL_TIME_HALF 8 #define OFDM_SIFS_TIME_QUARTER 64 #define OFDM_PREAMBLE_TIME_QUARTER 80 #define OFDM_PLCP_BITS_QUARTER 22 #define OFDM_SYMBOL_TIME_QUARTER 16 a_uint16_t ath_hal_computetxtime(struct ath_hal *ah, const HAL_RATE_TABLE *rates, a_uint32_t frameLen, a_uint16_t rateix, HAL_BOOL shortPreamble) { a_uint32_t bitsPerSymbol, numBits, numSymbols, phyTime, txTime; a_uint32_t kbps; kbps = rates->info[rateix].rateKbps; /* * index can be invalid duting dynamic Turbo transitions. */ if(kbps == 0) return 0; switch (rates->info[rateix].phy) { case IEEE80211_T_CCK: phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; if (shortPreamble && rates->info[rateix].shortPreamble) phyTime >>= 1; numBits = frameLen << 3; txTime = phyTime + ((numBits * 1000)/kbps); /* TODO: make sure the same value of txTime can use in all device */ if (ath_hal_getcapability(ah, HAL_CAP_HT) != HAL_OK) txTime = txTime + CCK_SIFS_TIME; break; case IEEE80211_T_OFDM: /* full rate channel */ bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; HALASSERT(bitsPerSymbol != 0); numBits = OFDM_PLCP_BITS + (frameLen << 3); numSymbols = asf_howmany(numBits, bitsPerSymbol); txTime = OFDM_PREAMBLE_TIME + (numSymbols * OFDM_SYMBOL_TIME); /* TODO: make sure the same value of txTime can use in all device */ if (ath_hal_getcapability(ah, HAL_CAP_HT) != HAL_OK) txTime = txTime + OFDM_SIFS_TIME; break; default: txTime = 0; break; } return txTime; } #undef CCK_SIFS_TIME #undef CCK_PREAMBLE_BITS #undef CCK_PLCP_BITS #undef OFDM_SIFS_TIME #undef OFDM_PREAMBLE_TIME #undef OFDM_PLCP_BITS #undef OFDM_SYMBOL_TIME #ifdef MAGPIE_MERLIN a_uint32_t ath_hal_get_curmode(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan) { if (!chan) return HAL_MODE_11NG; if (IS_CHAN_NA(chan)) return HAL_MODE_11NA; if (IS_CHAN_A(chan)) return HAL_MODE_11A; if (IS_CHAN_NG(chan)) return HAL_MODE_11NG; if (IS_CHAN_G(chan)) return HAL_MODE_11G; if (IS_CHAN_B(chan)) return HAL_MODE_11B; HALASSERT(0); return HAL_MODE_11NG; } #endif HAL_BOOL ath_hal_wait(struct ath_hal *ah, a_uint32_t reg, a_uint32_t mask, a_uint32_t val) { #define AH_TIMEOUT_11N 100000 #define AH_TIMEOUT_11G 1000 a_int32_t i; if (ath_hal_getcapability(ah, HAL_CAP_HT) == HAL_OK) { for (i = 0; i < AH_TIMEOUT_11N; i++) { if ((ioread32_mac(reg) & mask) == val) return AH_TRUE; OS_DELAY(10); } } else { for (i = 0; i < AH_TIMEOUT_11G; i++) { if ((ioread32_mac(reg) & mask) == val) return AH_TRUE; OS_DELAY(10); } } return AH_FALSE; #undef AH_TIMEOUT_11N #undef AH_TIMEOUT_11G } open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/ah.h000077500000000000000000000400451321570333100252750ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _ATH_AH_H_ #define _ATH_AH_H_ #include #include #ifndef __ahdecl #define __ahdecl #endif #define AR5416_DEVID_PCIE 0x0024 /* AR5416 PCI-E (XB) (Owl) */ #define HAL_RATE_TABLE_SIZE 33 typedef enum { HAL_OK = 0, /* No error */ HAL_ENXIO = 1, /* No hardware present */ HAL_ENOMEM = 2, /* Memory allocation failed */ HAL_EIO = 3, /* Hardware didn't respond as expected */ HAL_EEMAGIC = 4, /* EEPROM magic number invalid */ HAL_EEVERSION = 5, /* EEPROM version invalid */ HAL_EELOCKED = 6, /* EEPROM unreadable */ HAL_EEBADSUM = 7, /* EEPROM checksum invalid */ HAL_EEREAD = 8, /* EEPROM read problem */ HAL_EEBADMAC = 9, /* EEPROM mac address invalid */ HAL_EESIZE = 10, /* EEPROM size not supported */ HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ HAL_EINVAL = 12, /* Invalid parameter to function */ HAL_ENOTSUPP = 13, /* Hardware revision not supported */ HAL_ESELFTEST = 14, /* Hardware self-test failed */ HAL_EINPROGRESS = 15, /* Operation incomplete */ HAL_FULL_RESET = 16, /* Full reset done */ } HAL_STATUS; typedef enum { AH_FALSE = 0, AH_TRUE = 1, } HAL_BOOL; typedef enum { HAL_CAP_VEOL = 0, HAL_CAP_BSSIDMASK = 1, HAL_CAP_TSF_ADJUST = 2, HAL_CAP_HT = 5, HAL_CAP_RTS_AGGR_LIMIT = 6, } HAL_CAPABILITY_TYPE; typedef enum { HAL_TX_QUEUE_INACTIVE = 0, HAL_TX_QUEUE_DATA = 1, HAL_TX_QUEUE_BEACON = 2, HAL_TX_QUEUE_CAB = 3, HAL_TX_QUEUE_PSPOLL = 4, HAL_TX_QUEUE_UAPSD = 5, } HAL_TX_QUEUE; typedef enum { HAL_WME_AC_BK = 0, HAL_WME_AC_BE = 1, HAL_WME_AC_VI = 2, HAL_WME_AC_VO = 3, HAL_WME_UPSD = 4, HAL_XR_DATA = 5, } HAL_TX_QUEUE_SUBTYPE; #define HAL_NUM_TX_QUEUES 10 typedef enum { HAL_PKT_TYPE_NORMAL = 0, HAL_PKT_TYPE_ATIM = 1, HAL_PKT_TYPE_PSPOLL = 2, HAL_PKT_TYPE_BEACON = 3, HAL_PKT_TYPE_PROBE_RESP = 4, HAL_PKT_TYPE_CHIRP = 5, HAL_PKT_TYPE_GRP_POLL = 6, } HAL_PKT_TYPE; typedef enum { HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */ HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */ } HAL_HT_RXCLEAR; typedef enum { HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */ HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */ HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */ HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */ HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */ HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */ HAL_RX_FILTER_XRPOLL = 0x00000040, /* Allow XR poll frmae */ HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ #ifdef MAGPIE_MERLIN HAL_RX_FILTER_PHYRADAR = 0x00002000, /* Allow phy radar errors*/ HAL_RX_FILTER_PSPOLL = 0x00004000, /* Allow PSPOLL frames */ /* ** PHY "Pseudo bits" should be in the upper 16 bits since the lower ** 16 bits actually correspond to register 0x803c bits */ #else HAL_RX_FILTER_PHYRADAR = 0x00000200, /* Allow phy radar errors*/ #endif } HAL_RX_FILTER; #define CHANNEL_QUARTER 0x8000 /* Quarter rate channel */ #define CHANNEL_HALF 0x4000 /* Half rate channel */ typedef enum { HAL_INT_RX = 0x00000001, /* Non-common mapping */ HAL_INT_RXDESC = 0x00000002, HAL_INT_RXNOFRM = 0x00000008, HAL_INT_RXEOL = 0x00000010, HAL_INT_RXORN = 0x00000020, HAL_INT_TX = 0x00000040, /* Non-common mapping */ HAL_INT_TXDESC = 0x00000080, HAL_INT_TXURN = 0x00000800, HAL_INT_MIB = 0x00001000, HAL_INT_RXPHY = 0x00004000, HAL_INT_RXKCM = 0x00008000, HAL_INT_SWBA = 0x00010000, HAL_INT_BMISS = 0x00040000, HAL_INT_BNR = 0x00100000, /* Non-common mapping */ HAL_INT_GPIO = 0x01000000, HAL_INT_CST = 0x02000000, /* Non-common mapping */ HAL_INT_GTT = 0x20000000, /* Non-common mapping */ HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ HAL_INT_GLOBAL = 0x80000000, /* Set/clear IER */ HAL_INT_GENTIMER =0x08000000, /* Non-common mapping */ /* Interrupt bits that map directly to ISR/IMR bits */ HAL_INT_COMMON = HAL_INT_RXNOFRM | HAL_INT_RXDESC | HAL_INT_RXEOL | HAL_INT_RXORN | HAL_INT_TXURN | HAL_INT_TXDESC | HAL_INT_MIB | HAL_INT_RXPHY | HAL_INT_RXKCM | HAL_INT_SWBA | HAL_INT_BMISS | HAL_INT_GPIO, HAL_INT_NOCARD = 0xffffffff /* To signal the card was removed */ } HAL_INT; #ifdef MAGPIE_MERLIN #define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */ #define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */ #define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */ #define HAL_RATESERIES_STBC 0x0008 /* use STBC for series */ /* 11n */ typedef enum { HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */ HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */ } HAL_HT_MACMODE; typedef enum { HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */ HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */ } HAL_HT_PHYMODE; typedef enum { HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */ HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */ } HAL_HT_EXTPROTSPACING; typedef struct { HAL_HT_MACMODE ht_macmode; /* MAC - 20/40 mode */ HAL_HT_PHYMODE ht_phymode; /* PHY - 20/40 mode */ a_int8_t ht_extoff; /* ext channel offset */ HAL_HT_EXTPROTSPACING ht_extprotspacing; /* ext channel protection spacing */ } HAL_HT_CWM; typedef struct { a_uint8_t ht_txchainmask; /* tx chain mask */ a_uint8_t ht_rxchainmask; /* rx chain mask */ } HAL_HT_MISC; typedef struct { HAL_HT_CWM cwm; HAL_HT_MISC misc; } HAL_HT; /* channelFlags */ #define CHANNEL_CW_INT 0x0002 /* CW interference detected on channel */ #define CHANNEL_TURBO 0x0010 /* Turbo Channel */ #define CHANNEL_CCK 0x0020 /* CCK channel */ #define CHANNEL_OFDM 0x0040 /* OFDM channel */ #define CHANNEL_2GHZ 0x0080 /* 2 GHz spectrum channel. */ #define CHANNEL_5GHZ 0x0100 /* 5 GHz spectrum channel */ #define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed in the channel */ #define CHANNEL_DYN 0x0400 /* dynamic CCK-OFDM channel */ #define CHANNEL_XR 0x0800 /* XR channel */ #define CHANNEL_STURBO 0x2000 /* Static turbo, no 11a-only usage */ #define CHANNEL_HALF 0x4000 /* Half rate channel */ #define CHANNEL_QUARTER 0x8000 /* Quarter rate channel */ #define CHANNEL_HT20 0x10000 /* HT20 channel */ #define CHANNEL_HT40 0x20000 /* HT40 channel */ #define CHANNEL_HT40U 0x40000 /* control channel can be upper channel */ #define CHANNEL_HT40L 0x80000 /* control channel can be lower channel */ /* privFlags */ #define CHANNEL_INTERFERENCE 0x01 #define CHANNEL_DFS 0x02 /* DFS required on channel */ #define CHANNEL_4MS_LIMIT 0x04 /* 4msec packet limit on this channel */ #define CHANNEL_DFS_CLEAR 0x08 /* if channel has been checked for DFS */ #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) #define CHANNEL_PUREG (CHANNEL_2GHZ|CHANNEL_OFDM) #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) #define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO) #define CHANNEL_ST (CHANNEL_T|CHANNEL_STURBO) #define CHANNEL_108G (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO) #define CHANNEL_108A CHANNEL_T #define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20) #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20) #define CHANNEL_G_HT40 (CHANNEL_2GHZ|CHANNEL_HT20|CHANNEL_HT40) #define CHANNEL_A_HT40 (CHANNEL_5GHZ|CHANNEL_HT20|CHANNEL_HT40) #define CHANNEL_ALL \ (CHANNEL_OFDM | \ CHANNEL_CCK | \ CHANNEL_2GHZ | \ CHANNEL_5GHZ | \ CHANNEL_TURBO | \ CHANNEL_HT20 | \ CHANNEL_HT40) #define CHANNEL_ALL_NOTURBO (CHANNEL_ALL &~ CHANNEL_TURBO) typedef struct { a_int32_t rateCount; a_uint8_t rateCodeToIndex[HAL_RATE_TABLE_SIZE]; struct { a_uint8_t valid; a_uint8_t phy; a_int16_t txPower; a_int16_t txPower2Chains; a_int16_t txPower3Chains; a_uint32_t rateKbps; a_uint8_t rateCode; a_uint8_t shortPreamble; a_uint8_t dot11Rate; a_uint8_t controlRate; a_uint16_t lpAckDuration; a_uint16_t spAckDuration; } info[HAL_RATE_TABLE_SIZE]; } HAL_RATE_TABLE; typedef struct { a_uint32_t Tries; a_uint32_t Rate; a_uint32_t PktDuration; a_uint32_t ChSel; a_uint32_t RateFlags; a_uint32_t RateIndex; a_uint32_t TxPowerCap; /* in 1/2 dBm units */ } HAL_11N_RATE_SERIES; #else typedef struct { a_int32_t rateCount; a_uint8_t rateCodeToIndex[HAL_RATE_TABLE_SIZE]; struct { a_uint8_t valid; a_uint8_t phy; a_uint32_t rateKbps; a_uint8_t rateCode; a_uint8_t shortPreamble; a_uint8_t dot11Rate; a_uint8_t controlRate; a_uint16_t lpAckDuration; a_uint16_t spAckDuration; } info[HAL_RATE_TABLE_SIZE]; } HAL_RATE_TABLE; #define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */ #define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */ #define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */ #define HAL_RATESERIES_STBC 0x0008 /* use STBC for series */ typedef struct { a_uint32_t Tries; a_uint32_t Rate; a_uint32_t PktDuration; a_uint32_t ChSel; a_uint32_t RateFlags; } HAL_11N_RATE_SERIES; #endif enum { HAL_MODE_11A = 0x001, /* 11a channels */ HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */ HAL_MODE_11B = 0x004, /* 11b channels */ HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */ HAL_MODE_11G = 0x008, /* XXX historical */ HAL_MODE_108G = 0x020, /* 11a+Turbo channels */ HAL_MODE_108A = 0x040, /* 11g+Turbo channels */ HAL_MODE_XR = 0x100, /* XR channels */ HAL_MODE_11A_HALF_RATE = 0x200, /* 11A half rate channels */ HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11A quarter rate channels */ HAL_MODE_11NG = 0x4000, /* 11ng channels */ HAL_MODE_11NA = 0x8000, /* 11na channels */ HAL_MODE_ALL = 0xffff }; typedef enum { HAL_KEY_TYPE_CLEAR, HAL_KEY_TYPE_WEP, HAL_KEY_TYPE_AES, HAL_KEY_TYPE_TKIP, HAL_KEY_TYPE_WAPI, } HAL_KEY_TYPE; struct ath_desc; struct ath_rx_status; struct ath_hal { a_uint32_t ah_magic; HAL_SOFTC ah_sc; adf_os_device_t ah_dev; a_uint32_t ah_macVersion; a_uint16_t ah_macRev; a_uint16_t ah_phyRev; const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *, a_uint32_t mode); void __ahdecl(*ah_detach)(struct ath_hal*); HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*, HAL_BOOL incTrigLevel); /* Misc Functions */ void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, a_uint32_t); void __ahdecl(*ah_setRxFilter)(struct ath_hal*, a_uint32_t); /* Target Transmit Functions */ HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, a_uint32_t, a_uint32_t txdp); a_uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, a_uint32_t q); HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, a_uint32_t); HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, a_uint32_t); HAL_BOOL __ahdecl(*ah_abortTxDma)(struct ath_hal *); void __ahdecl(*ah_set11nTxDesc)(struct ath_tx_desc *ds, a_uint32_t pktLen, HAL_PKT_TYPE type, a_uint32_t txPower, a_uint32_t keyIx, HAL_KEY_TYPE keyType, a_uint32_t flags); void __ahdecl(*ah_set11nRateScenario)(struct ath_tx_desc *ds, a_uint32_t durUpdateEn, a_uint32_t rtsctsRate, HAL_11N_RATE_SERIES series[], a_uint32_t nseries, a_uint32_t flags); void __ahdecl(*ah_set11nAggrFirst)(struct ath_tx_desc *ds, a_uint32_t aggrLen, a_uint32_t numDelims); void __ahdecl(*ah_set11nAggrMiddle)(struct ath_tx_desc *ds, a_uint32_t numDelims); void __ahdecl(*ah_set11nAggrLast)(struct ath_tx_desc *ds); void __ahdecl(*ah_clr11nAggr)(struct ath_tx_desc *ds); void __ahdecl(*ah_set11nBurstDuration)(struct ath_tx_desc *ds, a_uint32_t burstDuration); void __ahdecl(*ah_set11nVirtualMoreFrag)(struct ath_tx_desc *ds, a_uint32_t vmf); HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_tx_desc *, a_uint32_t pktLen, a_uint32_t hdrLen, HAL_PKT_TYPE type, a_uint32_t txPower, a_uint32_t txRate0, a_uint32_t txTries0, a_uint32_t keyIx, a_uint32_t flags, a_uint32_t rtsctsRate, a_uint32_t rtsctsDuration); HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_tx_desc *, a_uint32_t segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg, const struct ath_tx_desc *); HAL_BOOL __ahdecl (*ah_fillKeyTxDesc) (struct ath_tx_desc *, HAL_KEY_TYPE); HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, struct ath_tx_desc *); HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const a_uint8_t*); void __ahdecl(*ah_setPCUConfig)(struct ath_hal *); void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*, a_uint32_t filter0, a_uint32_t filter1); u_int64_t __ahdecl(*ah_getTsf64)(struct ath_hal*); /* Target receive Functions */ void __ahdecl(*ah_setRxDP)(struct ath_hal*, a_uint32_t rxdp); HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_rx_desc *, a_uint32_t size, a_uint32_t flags); HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, struct ath_desc *, a_uint32_t phyAddr, struct ath_desc *next, u_int64_t tsf); HAL_STATUS __ahdecl(*ah_procRxDescFast)(struct ath_hal *ah, struct ath_rx_desc *ds, a_uint32_t pa, struct ath_desc *nds, struct ath_rx_status *rx_stats); HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*); void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*); void __ahdecl(*ah_enableReceive)(struct ath_hal*); /* Interrupt functions */ HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*); HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*); HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT); }; extern struct ath_hal * __ahdecl ath_hal_attach_tgt(a_uint32_t devid, HAL_SOFTC, adf_os_device_t dev, a_uint32_t flags, HAL_STATUS* status); extern a_uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *, const HAL_RATE_TABLE *rates, a_uint32_t frameLen, a_uint16_t rateix, HAL_BOOL shortPreamble); #endif /* _ATH_AH_H_ */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/ah_desc.h000077500000000000000000000126121321570333100262720ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _DEV_ATH_DESC_H #define _DEV_ATH_DESC_H #include #include #define HAL_TXSTAT_ALTRATE 0x80 #define ts_rssi ts_rssi_combined struct ath_tx_status { a_uint32_t ts_tstamp; a_uint16_t ts_seqnum; a_uint8_t ts_status; a_uint8_t ts_flags; a_uint8_t ts_rate; int8_t ts_rssi_combined; int8_t ts_rssi_ctl0; int8_t ts_rssi_ctl1; int8_t ts_rssi_ctl2; int8_t ts_rssi_ext0; int8_t ts_rssi_ext1; int8_t ts_rssi_ext2; a_uint8_t ts_shortretry; a_uint8_t ts_longretry; a_uint8_t ts_virtcol; a_uint8_t ts_antenna; a_uint32_t ba_low; a_uint32_t ba_high; a_uint32_t evm0; a_uint32_t evm1; a_uint32_t evm2; }; #define HAL_TXERR_XRETRY 0x01 #define HAL_TXERR_FILT 0x02 #define HAL_TXERR_FIFO 0x04 #define HAL_TXERR_XTXOP 0x08 #define HAL_TXERR_TIMER_EXPIRED 0x10 #define HAL_TX_BA 0x01 #define HAL_TX_PWRMGMT 0x02 #define HAL_TX_DESC_CFG_ERR 0x04 #define HAL_TX_DATA_UNDERRUN 0x08 #define HAL_TX_DELIM_UNDERRUN 0x10 #define HAL_TX_SW_FILTERED 0x80 struct ath_rx_status { a_uint64_t rs_tstamp; a_uint16_t rs_datalen; a_uint8_t rs_status; a_uint8_t rs_phyerr; int8_t rs_rssi_combined; int8_t rs_rssi_ctl0; int8_t rs_rssi_ctl1; int8_t rs_rssi_ctl2; int8_t rs_rssi_ext0; int8_t rs_rssi_ext1; int8_t rs_rssi_ext2; a_uint8_t rs_keyix; a_uint8_t rs_rate; a_uint8_t rs_antenna; a_uint8_t rs_more; a_uint8_t rs_isaggr; a_uint8_t rs_moreaggr; a_uint8_t rs_num_delims; a_uint8_t rs_flags; a_uint8_t rs_dummy; a_uint32_t evm0; a_uint32_t evm1; a_uint32_t evm2; }; #define rs_rssi rs_rssi_combined #define HAL_RXERR_CRC 0x01 #define HAL_RXERR_PHY 0x02 #define HAL_RXERR_FIFO 0x04 #define HAL_RXERR_DECRYPT 0x08 #define HAL_RXERR_MIC 0x10 #define HAL_RX_MORE 0x01 #define HAL_RX_MORE_AGGR 0x02 #define HAL_RX_GI 0x04 #define HAL_RX_2040 0x08 #define HAL_RX_DELIM_CRC_PRE 0x10 #define HAL_RX_DELIM_CRC_POST 0x20 #define HAL_RX_DECRYPT_BUSY 0x40 #define HAL_RXKEYIX_INVALID ((a_uint8_t) -1) #define HAL_TXKEYIX_INVALID ((a_uint8_t) -1) /* * The following definitions are passed directly * the hardware and managed by the HAL. Drivers * should not touch those elements marked opaque. */ #define ATH_GENERIC_DESC \ a_uint32_t ds_link; \ a_uint32_t ds_data; \ a_uint32_t ds_ctl0; \ a_uint32_t ds_ctl1; struct ath_desc { ATH_GENERIC_DESC } adf_os_packed; struct ath_rx_desc { ATH_GENERIC_DESC a_uint32_t ds_hw[9]; adf_nbuf_t ds_nbuf; adf_os_dma_map_t ds_dmap; adf_os_dmamap_info_t ds_dmap_info; adf_os_dma_addr_t ds_daddr; asf_tailq_entry(ath_rx_desc) ds_list; } adf_os_packed; struct ath_tx_desc { ATH_GENERIC_DESC a_uint32_t ds_hw[20]; union { struct ath_tx_status tx; } ds_us; } adf_os_packed; #define ds_txstat ds_us.tx #define HAL_TXDESC_CLRDMASK 0x0001 #define HAL_TXDESC_NOACK 0x0002 #define HAL_TXDESC_RTSENA 0x0004 #define HAL_TXDESC_CTSENA 0x0008 #define HAL_TXDESC_INTREQ 0x0010 #define HAL_TXDESC_VEOL 0x0020 #define HAL_TXDESC_EXT_ONLY 0x0040 #define HAL_TXDESC_EXT_AND_CTL 0x0080 #define HAL_TXDESC_VMF 0x0100 #define HAL_RXDESC_INTREQ 0x0020 #endif open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/ah_internal.h000077500000000000000000000236331321570333100271750ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting * Copyright (c) 2002-2005 Atheros Communications, Inc. * All rights reserved. * * $Id: //depot/sw/branches/fusion_usb/target_firmware/wlan/target/hal/main/ah_internal.h#2 $ */ #ifndef _ATH_AH_INTERAL_H_ #define _ATH_AH_INTERAL_H_ #include #define IEEE80211_AMPDU_LIMIT_MAX (64 * 1024 - 1) #define AH_NULL 0 #define AH_MIN(a,b) ((a)<(b)?(a):(b)) #define AH_MAX(a,b) ((a)>(b)?(a):(b)) /* * Common assertion interface. Note: it is a bad idea to generate * an assertion failure for any recoverable event. Instead catch * the violation and, if possible, fix it up or recover from it; either * with an error return value or a diagnostic messages. System software * does not panic unless the situation is hopeless. */ #ifdef AH_ASSERT #define HALASSERT(_x) do { \ adf_os_assert(_x) \ } while (0) #else #define HALASSERT(_x) #endif /* AH_ASSERT */ #ifndef NBBY #define NBBY 8 /* number of bits/byte */ #endif #define IEEE80211_ADDR_LEN 6 /* * Internal form of a HAL_CHANNEL. Note that the structure * must be defined such that you can cast references to a * HAL_CHANNEL so don't shuffle the first two members. */ typedef struct { a_uint16_t channel; /* NB: must be first for casting */ a_uint32_t channelFlags; a_uint8_t privFlags; int8_t maxRegTxPower; int8_t maxTxPower; int8_t minTxPower; /* as above... */ a_uint8_t regClassId; /* Regulatory class id */ HAL_BOOL bssSendHere; a_uint8_t gainI; HAL_BOOL iqCalValid; HAL_BOOL oneTimeCalsDone; int8_t iCoff; int8_t qCoff; a_int16_t rawNoiseFloor; a_int16_t finalNoiseFloor; int8_t antennaMax; a_uint32_t regDmnFlags; /* Flags for channel use in reg */ a_uint32_t conformanceTestLimit; /* conformance test limit from reg domain */ a_uint16_t mainSpur; /* cached spur value for this cahnnel */ u_int64_t ah_tsf_last; /* tsf @ which time accured is computed */ u_int64_t ah_channel_time; /* time on the channel */ u_int64_t dfsTsf; /* Tsf when channel leaves NOL */ } HAL_CHANNEL_INTERNAL; typedef struct { a_uint32_t halChanSpreadSupport : 1, halSleepAfterBeaconBroken : 1, halCompressSupport : 1, halBurstSupport : 1, halFastFramesSupport : 1, halChapTuningSupport : 1, halTurboGSupport : 1, halTurboPrimeSupport : 1, halXrSupport : 1, halMicAesCcmSupport : 1, halMicCkipSupport : 1, halMicTkipSupport : 1, halCipherAesCcmSupport : 1, halCipherCkipSupport : 1, halCipherTkipSupport : 1, halPSPollBroken : 1, halVEOLSupport : 1, halBssIdMaskSupport : 1, halMcastKeySrchSupport : 1, halTsfAddSupport : 1, halChanHalfRate : 1, halChanQuarterRate : 1, halHTSupport : 1, halGTTSupport : 1, halFastCCSupport : 1, halExtChanDfsSupport : 1, halUseCombinedRadarRssi : 1, halCSTSupport : 1, halRifsRxSupport : 1, halRifsTxSupport : 1, #ifdef MAGPIE_MERLIN halforcePpmSupport : 1, halAutoSleepSupport : 1, hal4kbSplitTransSupport : 1, halEnhancedPmSupport : 1, halMbssidAggrSupport : 1, halTkipWepHtRateSupport : 1, #endif halRfSilentSupport : 1; a_uint32_t halWirelessModes; a_uint16_t halTotalQueues; a_uint16_t halKeyCacheSize; a_uint16_t halLow5GhzChan, halHigh5GhzChan; a_uint16_t halLow2GhzChan, halHigh2GhzChan; a_uint16_t halNumMRRetries; a_uint8_t halTxChainMask; a_uint8_t halRxChainMask; a_uint16_t halRtsAggrLimit; a_uint16_t halJapanRegCap; a_uint8_t halNumGpioPins; } HAL_CAPABILITIES; #if !defined(_NET_IF_IEEE80211_H_) && !defined(_NET80211__IEEE80211_H_) /* * Stuff that would naturally come from _ieee80211.h */ #define IEEE80211_ADDR_LEN 6 #define IEEE80211_WEP_KEYLEN 5 /* 40bit */ #define IEEE80211_WEP_IVLEN 3 /* 24bit */ #define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ #define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ #define IEEE80211_CRC_LEN 4 #define IEEE80211_MTU 1500 #define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) #define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ enum { IEEE80211_T_DS, /* direct sequence spread spectrum */ IEEE80211_T_FH, /* frequency hopping */ IEEE80211_T_OFDM, /* frequency division multiplexing */ IEEE80211_T_TURBO, /* high rate DS */ IEEE80211_T_HT, /* HT - full GI */ IEEE80211_T_MAX }; #define IEEE80211_T_CCK IEEE80211_T_DS /* more common nomenclatur */ #endif /* _NET_IF_IEEE80211_H_ */ /* NB: these are defined privately until XR support is announced */ enum { ATHEROS_T_XR = IEEE80211_T_MAX, /* extended range */ }; struct ath_hal_private { struct ath_hal h; a_uint32_t ah_macVersion; a_uint16_t ah_macRev; a_uint16_t ah_phyRev; HAL_CAPABILITIES ah_caps; /* device capabilities */ HAL_CHANNEL_INTERNAL *ah_curchan; /* current channel */ }; #define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) #define IS_CHAN_A(_c) ((((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) || \ (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20)) #define IS_CHAN_B(_c) (((_c)->channelFlags & CHANNEL_B) == CHANNEL_B) #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_108G|CHANNEL_G)) == CHANNEL_G) || \ (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20)) #define IS_CHAN_108G(_c)(((_c)->channelFlags & CHANNEL_108G) == CHANNEL_108G) #define IS_CHAN_T(_c) (((_c)->channelFlags & CHANNEL_T) == CHANNEL_T) #define IS_CHAN_X(_c) (((_c)->channelFlags & CHANNEL_X) == CHANNEL_X) #define IS_CHAN_PUREG(_c) \ (((_c)->channelFlags & CHANNEL_PUREG) == CHANNEL_PUREG) #define IS_CHAN_NA(_c) (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20) #define IS_CHAN_NG(_c) (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) #define IS_CHAN_TURBO(_c) (((_c)->channelFlags & CHANNEL_TURBO) != 0) #define IS_CHAN_CCK(_c) (((_c)->channelFlags & CHANNEL_CCK) != 0) #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0) #define IS_CHAN_XR(_c) (((_c)->channelFlags & CHANNEL_XR) != 0) #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0) #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0) #define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0) #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0) #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0) #define IS_CHAN_HT(_c) (((_c)->channelFlags & CHANNEL_HT20) != 0) #define IS_CHAN_HT20(_c) (((_c)->channelFlags & CHANNEL_HT20) != 0) #define IS_CHAN_HT40(_c) (((_c)->channelFlags & CHANNEL_HT40) != 0) #define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) /* * Register manipulation macros that expect bit field defines * to follow the convention that an _S suffix is appended for * a shift count, while the field mask has no suffix. */ #define SM(_v, _f) (((_v) << _f##_S) & _f) #define MS(_v, _f) (((_v) & _f) >> _f##_S) #define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ iowrite32_mac(_r, \ (ioread32_mac(_r) & ~_f) \ | (((_v) << _f##_S) & _f)) #define OS_REG_RMW(_a, _r, _set, _clr) \ iowrite32_mac(_r, \ (ioread32_mac(_r) & ~(_clr)) | (_set)) #define OS_REG_SET_BIT(_a, _r, _f) \ iowrite32_mac(_r, ioread32_mac(_r) | _f) #define OS_REG_CLR_BIT(_a, _r, _f) \ iowrite32_mac(_r, ioread32_mac(_r) & ~_f) /* wait for the register contents to have the specified value */ extern HAL_BOOL ath_hal_wait(struct ath_hal *, a_uint32_t reg, a_uint32_t mask, a_uint32_t val); /* allocate and free memory */ extern void *ath_hal_malloc(size_t); extern void ath_hal_free(void *); /* * Generic get/set capability support. Each chip overrides * this routine to support chip-specific capabilities. */ extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type); extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, a_uint32_t capability, a_uint32_t setting, HAL_STATUS *status); #endif /* _ATH_AH_INTERAL_H_ */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/ah_osdep.c000077500000000000000000000061611321570333100264630ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "ah.h" #include #include "ah_osdep.h" a_uint32_t __ahdecl ath_hal_getuptime(struct ath_hal *ah) { return adf_os_getuptime(); } struct ath_hal * _ath_hal_attach_tgt(a_uint32_t devid, HAL_SOFTC sc, adf_os_device_t dev, a_uint32_t flags, void* s) { HAL_STATUS status; struct ath_hal *ah = ath_hal_attach_tgt(devid, sc, dev, flags, &status); adf_os_print(" ath_hal = %p \n",ah); *(HAL_STATUS *)s = status; return ah; } extern void *global_hdl; /* * Delay n microseconds. */ void __ahdecl ath_hal_delay(a_int32_t n) { adf_os_udelay(n); } /* * Allocate/free memory. */ void * __ahdecl ath_hal_malloc(adf_os_size_t size) { void *p; p = adf_os_mem_alloc(size); if (p) adf_os_mem_zero(p, size); return p; } void __ahdecl ath_hal_free(void* p) { adf_os_mem_free(p); } void * __ahdecl ath_hal_memcpy(void *dst, const void *src, adf_os_size_t n) { adf_os_mem_copy(dst, src, n); return 0; } enum { DEV_ATH = 9, /* XXX must match driver */ }; adf_os_module_dep(hal, adf_net); adf_os_module_dep(hal, hal); open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/ah_osdep.h000077500000000000000000000116611321570333100264710ustar00rootroot00000000000000/* * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting, Atheros * Communications, Inc. All rights reserved. * Copyright (c) 2013 Qualcomm Atheros, Inc. * * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _ATH_AH_OSDEP_H_ #define _ATH_AH_OSDEP_H_ /* * Atheros Hardware Access Layer (HAL) OS Dependent Definitions. */ /* * Starting with 2.6.4 the kernel supports a configuration option * to pass parameters in registers. If this is enabled we must * mark all function interfaces in+out of the HAL to pass parameters * on the stack as this is the convention used internally (for * maximum portability). * * XXX A lot of functions have __ahdecl in their definition but not declaration * So compile breaks. * Since This is only an issue for i386 which has regparam enabled, instead of * changing the vanilla FC3 kernel, for now, remove the regparm * disabling. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include /* CONFIG_REGPARM has been removed from 2.6.20 onwards. * Since this is relevant only for i386 architectures, changing check to * i386. */ #ifdef __adf_i386__ #define __ahdecl __attribute__((regparm(0))) #else #define __ahdecl #endif #ifndef adf_os_packed #define adf_os_packed __attribute__((__packed__)) #endif #ifdef __FreeBSD__ /* * When building the HAL proper we use no GPL-contaminated include * files and must define these types ourself. Beware of these being * mismatched against the contents of */ /* NB: arm defaults to unsigned so be explicit */ /* cometothis later when seperating os deps */ typedef __va_list va_list; // typedef void *va_list; #define va_start(ap, last) \ __builtin_stdarg_start((ap), (last)) #define va_end(ap) \ __builtin_va_end(ap) #endif /* * Linux/BSD gcc compatibility shims. */ #ifdef TODO //freebsd has definition #define __printflike(_a,_b) \ __attribute__ ((__format__ (__printf__, _a, _b))) #endif #ifndef __va_list #define __va_list va_list #endif #ifdef TODO //freebsd has definition #define OS_INLINE __inline #endif typedef void* HAL_SOFTC; typedef a_int32_t HAL_BUS_TAG; typedef void* HAL_BUS_HANDLE; typedef a_uint32_t HAL_BUS_ADDR; /* XXX architecture dependent */ /* * Delay n microseconds. */ extern void __ahdecl ath_hal_delay(a_int32_t); #define OS_DELAY(_n) ath_hal_delay(_n) extern void* __ahdecl ath_hal_ioremap(a_uint32_t addr, a_uint32_t len); #define OS_REMAP(_addr, _len) ath_hal_ioremap(_addr, _len) #define OS_MEMCPY(_d, _s, _n) ath_hal_memcpy(_d,_s,_n) extern void * __ahdecl ath_hal_memcpy(void *, const void *, size_t); #ifndef abs #define abs(_a) __builtin_abs(_a) #endif struct ath_hal; extern a_uint32_t __ahdecl ath_hal_getuptime(struct ath_hal *); #define OS_GETUPTIME(_ah) ath_hal_getuptime(_ah) #ifndef __bswap32 #define __bswap32(_x) (_x) #endif #ifndef __bswap16 #define __bswap16(_x) (_x) #endif #define AH_USE_EEPROM 0x00000001 extern struct ath_hal *_ath_hal_attach_tgt( a_uint32_t, HAL_SOFTC, adf_os_device_t, a_uint32_t flags, void* status); #endif /* _ATH_AH_OSDEP_H_ */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/ar5416.h000077500000000000000000000110261321570333100256240ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include extern HAL_STATUS ar5416GetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE, a_uint32_t, a_uint32_t *); extern const HAL_RATE_TABLE *ar5416GetRateTable(struct ath_hal *, a_uint32_t mode); extern HAL_BOOL ar5416IsInterruptPending(struct ath_hal *ah); extern HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *); extern HAL_INT ar5416GetInterrupts(struct ath_hal *ah); extern HAL_INT ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints); extern a_uint32_t ar5416Get11nExtBusy(struct ath_hal *ah); extern HAL_HT_RXCLEAR ar5416Get11nRxClear(struct ath_hal *ah); extern void ar5416Set11nRxClear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear); extern a_uint32_t ar5416GetTsf32(struct ath_hal *ah); extern u_int64_t ar5416GetTsf64(struct ath_hal *ah); extern void ar5416ResetTsf(struct ath_hal *ah); extern void ar5416Detach(struct ath_hal *ah); typedef enum Ar5416_Rates { rate6mb, rate9mb, rate12mb, rate18mb, rate24mb, rate36mb, rate48mb, rate54mb, rate1l, rate2l, rate2s, rate5_5l, rate5_5s, rate11l, rate11s, rateXr, rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3, rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7, rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3, rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7, rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm, Ar5416RateSize } AR5416_RATES; #ifdef MAGPIE_MERLIN #define AR_SREV_HOWL(ah) ((AH_PRIVATE(ah)->ah_macVersion) == AR_SREV_VERSION_HOWL) #define IS_5416_HOWL AR_SREV_HOWL #define AR5416_RATES_OFDM_OFFSET 0 #define AR5416_RATES_CCK_OFFSET 8 #define AR5416_RATES_HT20_OFFSET 16 #define AR5416_RATES_HT40_OFFSET 24 /* Delta from which to start power to pdadc table */ #define AR5416_PWR_TABLE_OFFSET -5 #define AR5416_LEGACY_CHAINMASK 1 #define AR5416_1_CHAINMASK 1 #define AR5416_2LOHI_CHAINMASK 5 #define AR5416_2LOMID_CHAINMASK 3 #define AR5416_3_CHAINMASK 7 #define AH5416(_ah) ((struct ath_hal_5416 *)(_ah)) #else // For Owl #endif // MAGPIE_MERLIN #define AR5416_LEGACY_CHAINMASK 1 #define AH5416(_ah) ((struct ath_hal_5416 *)(_ah)) /* * Various fifo fill before Tx start, in 64-byte units * i.e. put the frame in the air while still DMAing */ #define MIN_TX_FIFO_THRESHOLD 0x1 #define MAX_TX_FIFO_THRESHOLD (( 4096 / 64) - 1) #define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD struct ath_hal_5416 { struct ath_hal_private ah_priv; /* base class */ a_uint16_t ah_antennaSwitchSwap; /* Controls mapping of OID request */ a_uint32_t ah_maskReg; /* copy of AR_IMR */ a_uint32_t ah_slottime; /* user-specified slot time */ a_int16_t ah_txPowerIndexOffset; a_uint32_t ah_intrTxqs; void *ah_cal_mem; a_uint16_t ah_ratesArray[Ar5416RateSize]; #ifdef MAGPIE_MERLIN /* HT CWM state */ HAL_HT_CWM ah_htcwm; #endif }; open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/ar5416Phy.c000077500000000000000000000776031321570333100263150ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ident "$Id: //depot/sw/branches/fusion_usb/target_firmware/wlan/target/ratectrl11n/ar5416Phy.c#5 $" #include "ratectrl.h" #include "ratectrl11n.h" #define SHORT_PRE 1 #define LONG_PRE 0 #define WLAN_PHY_HT_20_SS WLAN_RC_PHY_HT_20_SS #define WLAN_PHY_HT_20_SS_HGI WLAN_RC_PHY_HT_20_SS_HGI #define WLAN_PHY_HT_20_DS WLAN_RC_PHY_HT_20_DS #define WLAN_PHY_HT_20_DS_HGI WLAN_RC_PHY_HT_20_DS_HGI #define WLAN_PHY_HT_40_SS WLAN_RC_PHY_HT_40_SS #define WLAN_PHY_HT_40_DS WLAN_RC_PHY_HT_40_DS #define WLAN_PHY_HT_40_DS_HGI WLAN_RC_PHY_HT_40_DS_HGI #define WLAN_PHY_HT_40_SS_HGI WLAN_RC_PHY_HT_40_SS_HGI /* TRUE_ALL_11N - valid for 20/40/Legacy, TRUE - Legacy only, TRUE_20 - HT 20 only, TRUE_40 - HT 40 only */ /* 4ms frame limit not used for NG mode. The values filled for HT are the 64K max aggregate limit */ #ifndef MAGPIE_MERLIN // K2 RATE_TABLE_11N ar5416_11ngRateTable = { 54, /* number of rates - should match the no. of rows below */ 100, /* probe interval */ 50, /* rssi reduce interval */ WLAN_RC_HT_FLAG, /* Phy rates allowed initially */ {/* Multiple Single */ /* stream stream short dot11 ctrl RssiAck RssiAck Base CW40 SGI Ht tx chain 4ms tx valid for*/ /* valid valid Kbps uKbps RC Preamble Rate Rate ValidMin DeltaMin Idx Idx Idx Idx mask limit UAPSD */ /* 1 Mb [0] */ { TRUE_ALL_11N, TRUE_ALL_11N, WLAN_PHY_CCK, 1000, 900, 0x1b, 0x00, 2, 0, 0, 1, 0, 0, 0, 0, 3, 7, 0, TRUE }, /* 2 Mb [1] */ { TRUE_ALL_11N, TRUE_ALL_11N, WLAN_PHY_CCK, 2000, 1900, 0x1a, 0x04, 4, 1, 1, 1, 1, 1, 1, 1, 3, 7, 0, FALSE}, /* 5.5 Mb [2] */ { TRUE_ALL_11N, TRUE_ALL_11N, WLAN_PHY_CCK, 5500, 4900, 0x19, 0x04, 11, 2, 2, 2, 2, 2, 2, 2, 3, 7, 0, FALSE}, /* 11 Mb [3] */ { TRUE_ALL_11N, TRUE_ALL_11N, WLAN_PHY_CCK, 11000, 8100, 0x18, 0x04, 22, 3, 3, 2, 3, 3, 3, 3, 3, 7, 0, TRUE}, /* 6 Mb [4] */ { FALSE, FALSE, WLAN_PHY_OFDM, 6000, 5400, 0x0b, 0x00, 12, 4, 2, 1, 4, 4, 4, 4, 3, 7, 0, FALSE}, /* 9 Mb [5] */ { FALSE, FALSE, WLAN_PHY_OFDM, 9000, 7800, 0x0f, 0x00, 18, 4, 3, 1, 5, 5, 5, 5, 3, 7, 0, FALSE}, /* 12 Mb [6] */ { TRUE, TRUE, WLAN_PHY_OFDM, 12000, 10100, 0x0a, 0x00, 24, 6, 4, 1, 6, 6, 6, 6, 3, 7, 0, FALSE}, /* 18 Mb [7] */ { TRUE, TRUE, WLAN_PHY_OFDM, 18000, 14100, 0x0e, 0x00, 36, 6, 6, 2, 7, 7, 7, 7, 3, 7, 0, FALSE}, /* 24 Mb [8] */ { TRUE, TRUE, WLAN_PHY_OFDM, 24000, 17700, 0x09, 0x00, 48, 8, 10, 3, 8, 8, 8, 8, 3, 7, 0, TRUE}, /* 36 Mb [9] */ { TRUE, TRUE, WLAN_PHY_OFDM, 36000, 23700, 0x0d, 0x00, 72, 8, 14, 3, 9, 9, 9, 9, 3, 7, 0, FALSE}, /* 48 Mb [10] */ { TRUE, TRUE, WLAN_PHY_OFDM, 48000, 27400, 0x08, 0x00, 96, 8, 20, 3, 10, 10, 10, 10, 1, 1, 0, FALSE}, /* 54 Mb [11] */ { TRUE, TRUE, WLAN_PHY_OFDM, 54000, 30900, 0x0c, 0x00, 108, 8, 23, 3, 11, 11, 11, 11, 1, 1, 0, TRUE}, /* 6.5 Mb [12] */ { FALSE, FALSE, WLAN_PHY_HT_20_SS,6500, 6400, 0x80, 0x00, 0, 4, 2, 3, 12, 33, 12, 33, 3, 7, 3216, TRUE}, /* 13 Mb [13] */ { TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS,13000, 12700, 0x81, 0x00, 1, 6, 4, 3, 13, 34, 13, 34, 3, 7, 6434, TRUE}, /* 19.5 Mb [14] */ { TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS,19500, 18800, 0x82, 0x00, 2, 6, 6, 3, 14, 35, 14, 35, 3, 7, 9650, FALSE}, /* 26 Mb [15] */ { TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS,26000, 25000, 0x83, 0x00, 3, 8, 10, 3, 15, 36, 15, 36, 3, 7, 12868, FALSE}, /* 39 Mb [16] */ { TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS,39000, 36700, 0x84, 0x00, 4, 8, 14, 3, 16, 37, 17, 38, 3, 7, 19304, TRUE}, /* 43.3 Mb [17] */ { FALSE, TRUE_20, WLAN_PHY_HT_20_SS_HGI,43300, 39200, 0x84, 0x00, 4, 8, 14, 3, 16, 37, 17, 38, 3, 7, 21460, TRUE}, /* 52 Mb [18] */ { FALSE, TRUE_20, WLAN_PHY_HT_20_SS,52000, 48100, 0x85, 0x00, 5, 8, 20, 3, 18, 39, 19, 40, 1, 1, 25740, FALSE}, /* 57.8 Mb [19] */ { FALSE, TRUE_20, WLAN_PHY_HT_20_SS_HGI,57800, 52300, 0x85, 0x00, 5, 8, 20, 3, 18, 39, 19, 40, 1, 1, 28620, FALSE}, /* 58.5 Mb [20] */ { FALSE, TRUE_20, WLAN_PHY_HT_20_SS,58500, 53500, 0x86, 0x00, 6, 8, 23, 3, 20, 41, 21, 42, 1, 1, 28956, FALSE}, /* 65 Mb [21] */ { FALSE, TRUE_20, WLAN_PHY_HT_20_SS_HGI,65000, 58800, 0x86, 0x00, 6, 8, 23, 3, 20, 41, 21, 42, 1, 1, 32200, FALSE}, /* 65 Mb [22] */ { FALSE, TRUE_20, WLAN_PHY_HT_20_SS,65000, 58801, 0x87, 0x00, 7, 8, 25, 3, 22, 43, 23, 44, 1, 1, 32200, TRUE}, /* 72.2 Mb [23] */ { FALSE, TRUE_20, WLAN_PHY_HT_20_SS_HGI,72200, 65400, 0x87, 0x00, 7, 8, 25, 3, 22, 43, 23, 44, 1, 1, 35750, TRUE}, /* 52 Mb [24] */ { TRUE_20, FALSE, WLAN_PHY_HT_20_DS,52000, 48100, 0x8b, 0x00, 11, 8, 10, 3, 24, 45, 24, 45, 3, 7, 25736, FALSE}, /* 78 Mb [25] */ { TRUE_20, FALSE, WLAN_PHY_HT_20_DS,78000, 69500, 0x8c, 0x00, 12, 8, 14, 3, 25, 46, 26, 47, 3, 7, 38600, TRUE}, /* 86.7 Mb [26] */ { FALSE, FALSE, WLAN_PHY_HT_20_DS_HGI,86700, 78400, 0x8c, 0x00, 12, 8, 14, 3, 25, 46, 26, 47, 3, 7, 42890, TRUE}, /* 104 Mb [27] */ { TRUE_20, FALSE, WLAN_PHY_HT_20_DS,104000,89500, 0x8d, 0x00, 13, 8, 20, 3, 27, 48, 28, 49, 3, 5, 51472, FALSE}, /* 115.6Mb [28] */ { FALSE, FALSE, WLAN_PHY_HT_20_DS_HGI,115600,103900,0x8d, 0x00, 13, 8, 20, 3, 27, 48, 28, 49, 3, 5, 57190, FALSE}, /* 117 Mb [29] */ { TRUE_20, FALSE, WLAN_PHY_HT_20_DS,117000,105200,0x8e, 0x00, 14, 8, 23, 3, 29, 50, 30, 51, 3, 5, 57890, FALSE}, /* 130 Mb [30] */ { FALSE, FALSE, WLAN_PHY_HT_20_DS_HGI,130000,116090,0x8e, 0x00, 14, 8, 23, 3, 29, 50, 30, 51, 3, 5, 64320, FALSE}, /* 130 Mb [31] */ { TRUE_20, FALSE, WLAN_PHY_HT_20_DS,130000,116100,0x8f, 0x00, 15, 8, 25, 3, 31, 52, 32, 53, 3, 5, 64320, TRUE}, /* 144.4Mb [32] */ { TRUE_20, FALSE, WLAN_PHY_HT_20_DS_HGI,144400,128100,0x8f, 0x00, 15, 8, 25, 3, 31, 52, 32, 53, 3, 5, 71490, TRUE}, /* 13.5 Mb [33] */ { TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,13500, 13200, 0x80, 0x00, 0, 8, 2, 3, 12, 33, 33, 33, 3, 7, 6684, TRUE}, /* 27.0 Mb [34] */ { TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,27500, 25900, 0x81, 0x00, 1, 8, 4, 3, 13, 34, 34, 34, 3, 7, 13368, TRUE}, /* 40.5 Mb [35] */ { TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,40500, 38600, 0x82, 0x00, 2, 8, 6, 3, 14, 35, 35, 35, 3, 7, 20052, FALSE}, /* 54 Mb [36] */ { TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,54000, 49800, 0x83, 0x00, 3, 8, 10, 3, 15, 36, 36, 36, 3, 7, 26738, FALSE}, /* 81 Mb [37] */ { TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,81500, 72200, 0x84, 0x00, 4, 8, 14, 3, 16, 37, 38, 38, 3, 7, 40104, TRUE}, /* 90 Mb [38] */ { FALSE, TRUE_40, WLAN_PHY_HT_40_SS_HGI,90000, 81500, 0x84, 0x00, 4, 8, 14, 3, 16, 37, 38, 38, 3, 7, 44590, TRUE}, /* 108 Mb [39] */ { FALSE, TRUE_40, WLAN_PHY_HT_40_SS,108000,92900, 0x85, 0x00, 5, 8, 20, 3, 18, 39, 40, 40, 1, 1, 53476, FALSE}, /* 120 Mb [40] */ { FALSE, TRUE_40, WLAN_PHY_HT_40_SS_HGI,120000,102100,0x85, 0x00, 5, 8, 20, 3, 18, 39, 40, 40, 1, 1, 59450, FALSE}, /* 121.5Mb [41] */ { FALSE, TRUE_40, WLAN_PHY_HT_40_SS,121500,102700,0x86, 0x00, 6, 8, 23, 3, 20, 41, 42, 42, 1, 1, 60156, FALSE}, /* 135 Mb [42] */ { FALSE, TRUE_40, WLAN_PHY_HT_40_SS_HGI,135000,111900,0x86, 0x00, 6, 8, 23, 3, 20, 41, 42, 42, 1, 1, 66840, FALSE}, /* 135 Mb [43] */ { FALSE, TRUE_40, WLAN_PHY_HT_40_SS,135000,112000,0x87, 0x00, 7, 8, 25, 3, 22, 43, 44, 44, 1, 1, 66840, TRUE}, /* 150 Mb [44] */ { FALSE, TRUE_40, WLAN_PHY_HT_40_SS_HGI,150000,122000,0x87, 0x00, 7, 8, 25, 3, 22, 43, 44, 44, 1, 1, 74200, TRUE}, /* 108 Mb [45] */ { TRUE_40, FALSE, WLAN_PHY_HT_40_DS,108000,92500, 0x8b, 0x00, 11, 8, 10, 3, 24, 45, 45, 45, 3, 7, 53440, FALSE}, /* 162 Mb [46] */ { TRUE_40, FALSE, WLAN_PHY_HT_40_DS,162000,130300,0x8c, 0x00, 12, 8, 14, 3, 25, 46, 47, 47, 3, 7, 80160, TRUE}, /* 180 Mb [47] */ { FALSE, FALSE, WLAN_PHY_HT_40_DS_HGI,180000,156900,0x8c, 0x00, 12, 8, 14, 3, 25, 46, 47, 47, 3, 7, 89090, TRUE}, /* 216 Mb [48] */ { TRUE_40, FALSE, WLAN_PHY_HT_40_DS,216000,162800,0x8d, 0x00, 13, 8, 20, 3, 27, 48, 49, 49, 3, 5, 106880, FALSE}, /* 240 Mb [49] */ { FALSE, FALSE, WLAN_PHY_HT_40_DS_HGI,240000,178000,0x8d, 0x00, 13, 8, 20, 3, 27, 48, 49, 49, 3, 5, 118790, FALSE}, /* 243 Mb [50] */ { TRUE_40, FALSE, WLAN_PHY_HT_40_DS,243000,178200,0x8e, 0x00, 14, 8, 23, 3, 29, 50, 51, 51, 3, 5, 120240, FALSE}, /* 270 Mb [51] */ { FALSE, FALSE, WLAN_PHY_HT_40_DS_HGI,270000,192050,0x8e, 0x00, 14, 8, 23, 3, 29, 50, 51, 51, 3, 5, 133600, FALSE}, /* 270 Mb [52] */ { TRUE_40, FALSE, WLAN_PHY_HT_40_DS,270000,192100,0x8f, 0x00, 15, 8, 23, 3, 31, 52, 53, 53, 3, 5, 133600, FALSE}, /* 300 Mb [53] */ { TRUE_40, FALSE, WLAN_PHY_HT_40_DS_HGI,300000,207000,0x8f, 0x00, 15, 8, 25, 3, 31, 52, 53, 53, 3, 5, 148400, TRUE}, /* Multiple Single */ /* stream stream short dot11 ctrl RssiAck RssiAck Base CW40 SGI Ht tx chain 4ms tx valid for*/ /* valid valid Kbps uKbps RC Preamble Rate Rate ValidMin DeltaMin Idx Idx Idx Idx mask limit UAPSD */ }, }; #else RATE_TABLE_11N ar5416_11ngRateTable = { 46, /* number of rates - should match the no. of rows below */ 50, /* probe interval */ 50, /* rssi reduce interval */ WLAN_RC_HT_FLAG, /* Phy rates allowed initially */ {/* Multiple Single Single */ /* stream stream stream short dot11 ctrl RssiAck RssiAck Base CW40 SGI Ht tx chain 4ms tx valid for*/ /* valid valid STBC Kbps uKbps RC Preamble Rate Rate ValidMin DeltaMin Idx Idx Idx Idx mask limit UAPSD */ /* 1 Mb [0] */ { TRUE_ALL_11N, TRUE_ALL_11N, TRUE_ALL_11N, WLAN_PHY_CCK, 1000, 900, 0x1b, 0x00, 2, 0, 0, 1, 0, 0, 0, 0, 3, 7, 0, TRUE }, /* 2 Mb [1] */ { TRUE_ALL_11N, TRUE_ALL_11N, TRUE_ALL_11N, WLAN_PHY_CCK, 2000, 1900, 0x1a, 0x04, 4, 1, 1, 1, 1, 1, 1, 1, 3, 7, 0, FALSE}, /* 5.5 Mb [2] */ { TRUE_ALL_11N, TRUE_ALL_11N, TRUE_ALL_11N, WLAN_PHY_CCK, 5500, 4900, 0x19, 0x04, 11, 2, 2, 2, 2, 2, 2, 2, 3, 7, 0, FALSE}, /* 11 Mb [3] */ { TRUE_ALL_11N, TRUE_ALL_11N, TRUE_ALL_11N, WLAN_PHY_CCK, 11000, 8100, 0x18, 0x04, 22, 3, 3, 2, 3, 3, 3, 3, 3, 7, 0, TRUE}, /* 6 Mb [4] */ { FALSE, FALSE, FALSE, WLAN_PHY_OFDM, 6000, 5400, 0x0b, 0x00, 12, 4, 2, 1, 4, 4, 4, 4, 3, 7, 0, FALSE}, /* 9 Mb [5] */ { FALSE, FALSE, FALSE, WLAN_PHY_OFDM, 9000, 7800, 0x0f, 0x00, 18, 4, 3, 1, 5, 5, 5, 5, 3, 7, 0, FALSE}, /* 12 Mb [6] */ { TRUE, TRUE, TRUE, WLAN_PHY_OFDM, 12000, 10100, 0x0a, 0x00, 24, 6, 4, 1, 6, 6, 6, 6, 3, 7, 0, FALSE}, /* 18 Mb [7] */ { TRUE, TRUE, TRUE, WLAN_PHY_OFDM, 18000, 14100, 0x0e, 0x00, 36, 6, 6, 2, 7, 7, 7, 7, 3, 7, 0, FALSE}, /* 24 Mb [8] */ { TRUE, TRUE, TRUE, WLAN_PHY_OFDM, 24000, 17700, 0x09, 0x00, 48, 8, 10, 3, 8, 8, 8, 8, 3, 7, 0, TRUE}, /* 36 Mb [9] */ { TRUE, TRUE, TRUE, WLAN_PHY_OFDM, 36000, 23700, 0x0d, 0x00, 72, 8, 14, 3, 9, 9, 9, 9, 3, 7, 0, FALSE}, /* 48 Mb [10] */ { TRUE, TRUE, TRUE, WLAN_PHY_OFDM, 48000, 27400, 0x08, 0x00, 96, 8, 20, 3, 10, 10, 10, 10, 1, 1, 0, FALSE}, /* 54 Mb [11] */ { TRUE, TRUE, TRUE, WLAN_PHY_OFDM, 54000, 30900, 0x0c, 0x00, 108, 8, 23, 3, 11, 11, 11, 11, 1, 1, 0, TRUE}, /* 6.5 Mb [12] */ { FALSE, FALSE, FALSE, WLAN_PHY_HT_20_SS,6500, 6400, 0x80, 0x00, 0, 4, 2, 3, 12, 28, 12, 28, 3, 7, 3216, TRUE}, /* 13 Mb [13] */ { TRUE_20, TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS,13000, 12700, 0x81, 0x00, 1, 6, 4, 3, 13, 29, 13, 29, 3, 7, 6434, TRUE}, /* 19.5 Mb [14] */ { TRUE_20, TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS,19500, 18800, 0x82, 0x00, 2, 6, 6, 3, 14, 30, 14, 30, 3, 7, 9650, FALSE}, /* 26 Mb [15] */ { TRUE_20, TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS,26000, 25000, 0x83, 0x00, 3, 8, 10, 3, 15, 31, 15, 31, 3, 7, 12868, FALSE}, /* 39 Mb [16] */ { TRUE_20, TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS,39000, 36700, 0x84, 0x00, 4, 8, 14, 3, 16, 32, 16, 32, 3, 7, 19304, TRUE}, /* 52 Mb [17] */ { FALSE, TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS,52000, 48100, 0x85, 0x00, 5, 8, 20, 3, 17, 33, 17, 33, 1, 1, 25740, FALSE}, /* 58.5 Mb [18] */ { FALSE, TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS,58500, 53500, 0x86, 0x00, 6, 8, 23, 3, 18, 34, 18, 34, 1, 1, 28956, FALSE}, /* 65 Mb [19] */ { FALSE, TRUE_20, FALSE, WLAN_PHY_HT_20_SS,65000, 59000, 0x87, 0x00, 7, 8, 25, 3, 19, 35, 19, 36, 1, 1, 32180, TRUE}, /* 13 Mb [20] */ { FALSE, FALSE, FALSE, WLAN_PHY_HT_20_DS,13000, 12700, 0x88, 0x00, 8, 4, 2, 3, 20, 37, 20, 37, 3, 7, 6430, TRUE}, /* 26 Mb [21] */ { FALSE, FALSE, FALSE, WLAN_PHY_HT_20_DS,26000, 24800, 0x89, 0x00, 9, 6, 4, 3, 21, 38, 21, 38, 3, 7, 12860, FALSE}, /* 39 Mb [22] */ { FALSE, FALSE, FALSE, WLAN_PHY_HT_20_DS,39000, 36600, 0x8a, 0x00, 10, 6, 6, 3, 22, 39, 22, 39, 3, 7, 19300, TRUE}, /* 52 Mb [23] */ { TRUE_20, FALSE, FALSE, WLAN_PHY_HT_20_DS,52000, 48100, 0x8b, 0x00, 11, 8, 10, 3, 23, 40, 23, 40, 3, 7, 25736, FALSE}, /* 78 Mb [24] */ { TRUE_20, FALSE, TRUE_20, WLAN_PHY_HT_20_DS,78000, 69500, 0x8c, 0x00, 12, 8, 14, 3, 24, 41, 24, 41, 3, 7, 38600, TRUE}, /* 104 Mb [25] */ { TRUE_20, FALSE, TRUE_20, WLAN_PHY_HT_20_DS,104000,89500, 0x8d, 0x00, 13, 8, 20, 3, 25, 42, 25, 42, 3, 5, 51472, FALSE}, /* 117 Mb [26] */ { TRUE_20, FALSE, TRUE_20, WLAN_PHY_HT_20_DS,117000,98900, 0x8e, 0x00, 14, 8, 23, 3, 26, 43, 26, 44, 3, 5, 57890, FALSE}, /* 130 Mb [27] */ { TRUE_20, FALSE, TRUE_20, WLAN_PHY_HT_20_DS,130000,108300,0x8f, 0x00, 15, 8, 25, 3, 27, 44, 27, 45, 3, 5, 64320, TRUE}, /* 13.5 Mb [28] */ { TRUE_40, TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,13500, 13200, 0x80, 0x00, 0, 8, 2, 3, 12, 28, 28, 28, 3, 7, 6684, TRUE}, /* 27.0 Mb [29] */ { TRUE_40, TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,27500, 25900, 0x81, 0x00, 1, 8, 4, 3, 13, 29, 29, 29, 3, 7, 13368, TRUE}, /* 40.5 Mb [30] */ { TRUE_40, TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,40500, 38600, 0x82, 0x00, 2, 8, 6, 3, 14, 30, 30, 30, 3, 7, 20052, FALSE}, /* 54 Mb [31] */ { TRUE_40, TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,54000, 49800, 0x83, 0x00, 3, 8, 10, 3, 15, 31, 31, 31, 3, 7, 26738, FALSE}, /* 81 Mb [32] */ { TRUE_40, TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,81500, 72200, 0x84, 0x00, 4, 8, 14, 3, 16, 32, 32, 32, 3, 7, 40104, TRUE}, /* 108 Mb [33] */ { FALSE, TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,108000,92900, 0x85, 0x00, 5, 8, 20, 3, 17, 33, 33, 33, 1, 1, 53476, FALSE}, /* 121.5Mb [34] */ { FALSE, TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,121500,102700,0x86, 0x00, 6, 8, 23, 3, 18, 34, 34, 34, 1, 1, 60156, FALSE}, /* 135 Mb [35] */ { FALSE, TRUE_40, FALSE, WLAN_PHY_HT_40_SS,135000,112000,0x87, 0x00, 7, 8, 25, 3, 19, 35, 36, 36, 1, 1, 66840, TRUE}, /* 150 Mb [36] */ { FALSE, TRUE_40, FALSE, WLAN_PHY_HT_40_SS_HGI,150000,122000,0x87, 0x00, 7, 8, 25, 3, 19, 35, 36, 36, 1, 1, 74200, TRUE}, /* 27 Mb [37] */ { FALSE, FALSE, FALSE, WLAN_PHY_HT_40_DS,27000, 25800, 0x88, 0x00, 8, 8, 2, 3, 20, 37, 37, 37, 3, 7, 13360, TRUE}, /* 54 Mb [38] */ { FALSE, FALSE, FALSE, WLAN_PHY_HT_40_DS,54000, 49800, 0x89, 0x00, 9, 8, 4, 3, 21, 38, 38, 38, 3, 7, 26720, FALSE}, /* 81 Mb [39] */ { FALSE, FALSE, FALSE, WLAN_PHY_HT_40_DS,81000, 71900, 0x8a, 0x00, 10, 8, 6, 3, 22, 39, 39, 39, 3, 7, 40080, TRUE}, /* 108 Mb [40] */ { TRUE_40, FALSE, FALSE, WLAN_PHY_HT_40_DS,108000,92500, 0x8b, 0x00, 11, 8, 10, 3, 23, 40, 40, 40, 3, 7, 53440, FALSE}, /* 162 Mb [41] */ { TRUE_40, FALSE, TRUE_40, WLAN_PHY_HT_40_DS,162000,130300,0x8c, 0x00, 12, 8, 14, 3, 24, 41, 41, 41, 3, 7, 80160, TRUE}, /* 216 Mb [42] */ { TRUE_40, FALSE, TRUE_40, WLAN_PHY_HT_40_DS,216000,162800,0x8d, 0x00, 13, 8, 20, 3, 25, 42, 42, 42, 3, 5, 106880, FALSE}, /* 243 Mb [43] */ { TRUE_40, FALSE, TRUE_40, WLAN_PHY_HT_40_DS,243000,178200,0x8e, 0x00, 14, 8, 23, 3, 26, 43, 43, 43, 3, 5, 120240, FALSE}, /* 270 Mb [44] */ { TRUE_40, FALSE, TRUE_40, WLAN_PHY_HT_40_DS,270000,192100,0x8f, 0x00, 15, 8, 23, 3, 27, 44, 45, 45, 3, 5, 133600, FALSE}, /* 300 Mb [45] */ { TRUE_40, FALSE, TRUE_40, WLAN_PHY_HT_40_DS_HGI,300000,207000,0x8f, 0x00, 15, 8, 25, 3, 27, 44, 45, 45, 3, 5, 148400, TRUE}, /* Multiple Single */ /* stream stream short dot11 ctrl RssiAck RssiAck Base CW40 SGI Ht tx chain 4ms tx valid for*/ /* valid valid Kbps uKbps RC Preamble Rate Rate ValidMin DeltaMin Idx Idx Idx Idx mask limit UAPSD */ }, }; #ifdef ATH_SUPPORT_A_MODE //static RATE_TABLE_11N ar5416_11naRateTable = { RATE_TABLE_11N ar5416_11naRateTable = { 42, /* number of rates */ 50, /* probe interval */ 50, /* rssi reduce interval */ WLAN_RC_HT_FLAG, /* Phy rates allowed initially */ {/* Multiple Single Single*/ /* stream stream stream rate short dot11 ctrl RssiAck RssiAck Base CW40 SGI Ht tx chain 4ms tx valid for */ /* valid valid STBC Kbps uKbps Code Preamble Rate Rate ValidMin DeltaMin Idx Idx Idx Idx mask limit UAPSD */ /* 6 Mb [0] */ { TRUE, TRUE, TRUE, WLAN_PHY_OFDM, 6000, 5400, 0x0b, 0x00, 12, 0, 2, 1, 0, 0, 0, 0, 3, 7, 0, TRUE}, /* 9 Mb [1] */ { TRUE, TRUE, TRUE, WLAN_PHY_OFDM, 9000, 7800, 0x0f, 0x00, 18, 0, 3, 1, 1, 1, 1, 1, 3, 7, 0, FALSE}, /* 12 Mb [2] */ { TRUE, TRUE, TRUE, WLAN_PHY_OFDM, 12000, 10000, 0x0a, 0x00, 24, 2, 4, 2, 2, 2, 2, 2, 3, 7, 0, TRUE}, /* 18 Mb [3] */ { TRUE, TRUE, TRUE, WLAN_PHY_OFDM, 18000, 13900, 0x0e, 0x00, 36, 2, 6, 2, 3, 3, 3, 3, 3, 7, 0, FALSE}, /* 24 Mb [4] */ { TRUE, TRUE, TRUE, WLAN_PHY_OFDM, 24000, 17300, 0x09, 0x00, 48, 4, 10, 3, 4, 4, 4, 4, 3, 7, 0, TRUE}, /* 36 Mb [5] */ { TRUE, TRUE, TRUE, WLAN_PHY_OFDM, 36000, 23000, 0x0d, 0x00, 72, 4, 14, 3, 5, 5, 5, 5, 3, 7, 0, FALSE}, /* 48 Mb [6] */ { TRUE, TRUE, TRUE, WLAN_PHY_OFDM, 48000, 27400, 0x08, 0x00, 96, 4, 20, 3, 6, 6, 6, 6, 1, 1, 0, FALSE}, /* 54 Mb [7] */ { TRUE, TRUE, TRUE, WLAN_PHY_OFDM, 54000, 29300, 0x0c, 0x00, 108, 4, 23, 3, 7, 7, 7, 7, 1, 1, 0, TRUE}, /* 6.5 Mb [8] */ { TRUE_20, TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS, 6500, 6400, 0x80, 0x00, 0, 0, 2, 3, 8, 24, 8, 24, 3, 7, 3216, TRUE}, /* 13 Mb [9] */ { TRUE_20, TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS,13000, 12700, 0x81, 0x00, 1, 2, 4, 3, 9, 25, 9, 25, 3, 7, 6434, TRUE}, /* 19.5 Mb [10] */ { TRUE_20, TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS,19500, 18800, 0x82, 0x00, 2, 2, 6, 3, 10, 26, 10, 26, 3, 7, 9650, FALSE}, /* 26 Mb [11] */ { TRUE_20, TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS,26000, 25000, 0x83, 0x00, 3, 4, 10, 3, 11, 27, 11, 27, 3, 7, 12868, FALSE}, /* 39 Mb [12] */ { TRUE_20, TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS,39000, 36700, 0x84, 0x00, 4, 4, 14, 3, 12, 28, 12, 28, 3, 7, 19304, TRUE}, /* 52 Mb [13] */ { FALSE, TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS,52000, 48100, 0x85, 0x00, 5, 4, 20, 3, 13, 29, 13, 29, 1, 1, 25740, FALSE}, /* 58.5 Mb [14] */ { FALSE, TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS,58500, 53500, 0x86, 0x00, 6, 4, 23, 3, 14, 30, 14, 30, 1, 1, 28956, FALSE}, /* 65 Mb [15] */ { FALSE, TRUE_20, FALSE, WLAN_PHY_HT_20_SS,65000, 59000, 0x87, 0x00, 7, 4, 25, 3, 15, 31, 15, 32, 1, 1, 32180, TRUE}, /* 13 Mb [16] */ { FALSE, FALSE, FALSE, WLAN_PHY_HT_20_DS,13000, 12700, 0x88, 0x00, 8, 0, 2, 3, 16, 33, 16, 33, 3, 7, 6430, TRUE}, /* 26 Mb [17] */ { FALSE, FALSE, FALSE, WLAN_PHY_HT_20_DS,26000, 24800, 0x89, 0x00, 9, 2, 4, 3, 17, 34, 17, 34, 3, 7, 12860, FALSE}, /* 39 Mb [18] */ { FALSE, FALSE, FALSE, WLAN_PHY_HT_20_DS,39000, 36600, 0x8a, 0x00, 10, 2, 6, 3, 18, 35, 18, 35, 3, 7, 19300, TRUE}, /* 52 Mb [19] */ { TRUE_20, FALSE, FALSE, WLAN_PHY_HT_20_DS,52000, 48100, 0x8b, 0x00, 11, 4, 10, 3, 19, 36, 19, 36, 3, 7, 25736, FALSE}, /* 78 Mb [20] */ { TRUE_20, FALSE, TRUE_20, WLAN_PHY_HT_20_DS,78000, 69500, 0x8c, 0x00, 12, 4, 14, 3, 20, 37, 20, 37, 3, 7, 38600, TRUE}, /* 104 Mb [21] */ { TRUE_20, FALSE, TRUE_20, WLAN_PHY_HT_20_DS,104000,89500, 0x8d, 0x00, 13, 4, 20, 3, 21, 38, 21, 38, 3, 5, 51472, FALSE}, /* 117 Mb [22] */ { TRUE_20, FALSE, TRUE_20, WLAN_PHY_HT_20_DS,117000,98900, 0x8e, 0x00, 14, 4, 23, 3, 22, 39, 22, 39, 3, 5, 57890, FALSE}, /* 130 Mb [23] */ { TRUE_20, FALSE, TRUE_20, WLAN_PHY_HT_20_DS,130000,108300,0x8f, 0x00, 15, 4, 25, 3, 23, 40, 23, 41, 3, 5, 64320, TRUE}, /* 13.5 Mb [24] */ { TRUE_40, TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,13500, 13200, 0x80, 0x00, 0, 0, 2, 3, 8, 24, 24, 24, 3, 7, 6684, TRUE}, /* 27.0 Mb [25] */ { TRUE_40, TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,27500, 25900, 0x81, 0x00, 1, 2, 4, 3, 9, 25, 25, 25, 3, 7, 13368, TRUE}, /* 40.5 Mb [26] */ { TRUE_40, TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,40500, 38600, 0x82, 0x00, 2, 2, 6, 3, 10, 26, 26, 26, 3, 7, 20052, FALSE}, /* 54 Mb [27] */ { TRUE_40, TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,54000, 49800, 0x83, 0x00, 3, 4, 10, 3, 11, 27, 27, 27, 3, 7, 26738, FALSE}, /* 81 Mb [28] */ { TRUE_40, TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,81500, 72200, 0x84, 0x00, 4, 4, 14, 3, 12, 28, 28, 28, 3, 7, 40104, TRUE}, /* 108 Mb [29] */ { FALSE, TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,108000,92900, 0x85, 0x00, 5, 4, 20, 3, 13, 29, 29, 29, 1, 1, 53476, FALSE}, /* 121.5Mb [30] */ { FALSE, TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,121500,102700,0x86, 0x00, 6, 4, 23, 3, 14, 30, 30, 30, 1, 1, 60156, FALSE}, /* 135 Mb [31] */ { FALSE, TRUE_40, FALSE, WLAN_PHY_HT_40_SS,135000,112000,0x87, 0x00, 7, 4, 25, 3, 15, 31, 32, 32, 1, 1, 66840, TRUE}, /* 150 Mb [32] */ { FALSE, TRUE_40, FALSE, WLAN_PHY_HT_40_SS_HGI,150000,122000,0x87, 0x00, 7, 8, 25, 3, 15, 31, 32, 32, 1, 1, 65535, TRUE}, /* 27 Mb [33] */ { FALSE, FALSE, FALSE, WLAN_PHY_HT_40_DS,27000, 25800, 0x88, 0x00, 8, 0, 2, 3, 16, 33, 33, 33, 3, 7, 13360, TRUE}, /* 54 Mb [34] */ { FALSE, FALSE, FALSE, WLAN_PHY_HT_40_DS,54000, 49800, 0x89, 0x00, 9, 2, 4, 3, 17, 34, 34, 34, 3, 7, 26720, FALSE}, /* 81 Mb [35] */ { FALSE, FALSE, FALSE, WLAN_PHY_HT_40_DS,81000, 71900, 0x8a, 0x00, 10, 2, 6, 3, 18, 35, 35, 35, 3, 7, 40080, TRUE}, /* 108 Mb [36] */ { TRUE_40, FALSE, FALSE, WLAN_PHY_HT_40_DS,108000,92500, 0x8b, 0x00, 11, 4, 10, 3, 19, 36, 36, 36, 3, 7, 53440, FALSE}, /* 162 Mb [37] */ { TRUE_40, FALSE, TRUE_40, WLAN_PHY_HT_40_DS,162000,130300,0x8c, 0x00, 12, 4, 14, 3, 20, 37, 37, 37, 3, 7, 80160, TRUE}, /* 216 Mb [38] */ { TRUE_40, FALSE, TRUE_40, WLAN_PHY_HT_40_DS,216000,162800,0x8d, 0x00, 13, 4, 20, 3, 21, 38, 38, 38, 3, 5, 106880, FALSE}, /* 243 Mb [39] */ { TRUE_40, FALSE, TRUE_40, WLAN_PHY_HT_40_DS,243000,178200,0x8e, 0x00, 14, 4, 23, 3, 22, 39, 39, 39, 3, 5, 120240, FALSE}, /* 270 Mb [40] */ { TRUE_40, FALSE, TRUE_40, WLAN_PHY_HT_40_DS,270000,192100,0x8f, 0x00, 15, 4, 25, 3, 23, 40, 41, 41, 3, 5, 133600, TRUE}, /* 300 Mb [41] */ { TRUE_40, FALSE, TRUE_40, WLAN_PHY_HT_40_DS_HGI,300000,207000,0x8f, 0x00, 15, 4, 25, 3, 23, 40, 41, 41, 3, 5, 148400, TRUE}, /* stream stream rate short dot11 ctrl RssiAck RssiAck Base CW40 SGI Ht tx chain 4ms tx valid for */ /* valid valid Kbps uKbps Code Preamble Rate Rate ValidMin DeltaMin Idx Idx Idx Idx mask limit UAPSD */ }, }; #endif //ATH_SUPPORT_A_MODE #endif //#ifdef MAGPIE_MERLIN // MAGPIE_MERLIN void ar5416AttachRateTables(struct atheros_softc *sc) { sc->hwRateTable[WIRELESS_MODE_11NG] = &ar5416_11ngRateTable; #ifdef ATH_SUPPORT_A_MODE sc->hwRateTable[WIRELESS_MODE_11NA] = &ar5416_11naRateTable; #endif } open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/ar5416_hw.c000066400000000000000000000673361321570333100263310ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "ah.h" #include "ah_internal.h" #include "ar5416.h" #include "ar5416reg.h" #include "ar5416desc.h" #define N(a) (sizeof(a)/sizeof(a[0])) #define AR_INTR_SPURIOUS 0xffffffff #define ar5416_desc ar5416_desc_20 #define AR5416_ABORT_LOOPS 1000 #define AR5416_ABORT_WAIT 5 #define AR5416DESC AR5416DESC_20 #define AR5416DESC_CONST AR5416DESC_CONST_20 /*****************/ /* Attach/Detach */ /*****************/ static const struct ath_hal_private ar5416hal_10 = {{ .ah_getRateTable = ar5416GetRateTable, .ah_detach = ar5416Detach, /* Transmit functions */ .ah_updateTxTrigLevel = ar5416UpdateTxTrigLevel, .ah_setTxDP = ar5416SetTxDP, .ah_numTxPending = ar5416NumTxPending, .ah_startTxDma = ar5416StartTxDma, .ah_stopTxDma = ar5416StopTxDma, .ah_abortTxDma = ar5416AbortTxDma, /* Misc Functions */ .ah_getTsf64 = ar5416GetTsf64, .ah_setRxFilter = ar5416SetRxFilter, /* RX Functions */ .ah_setRxDP = ar5416SetRxDP, .ah_stopDmaReceive = ar5416StopDmaReceive, .ah_enableReceive = ar5416EnableReceive, .ah_stopPcuReceive = ar5416StopPcuReceive, /* Interrupt Functions */ .ah_isInterruptPending = ar5416IsInterruptPending, .ah_getPendingInterrupts = ar5416GetPendingInterrupts, .ah_setInterrupts = ar5416SetInterrupts, }, }; void ar5416Detach(struct ath_hal *ah) { HALASSERT(ah != AH_NULL); ath_hal_free(ah); } struct ath_hal * ar5416Attach(HAL_SOFTC sc, adf_os_device_t dev, HAL_STATUS *status) { struct ath_hal_5416 *ahp; struct ath_hal *ah; ahp = ath_hal_malloc(sizeof (struct ath_hal_5416)); if (ahp == AH_NULL) { *status = HAL_ENOMEM; return AH_NULL; } ah = &ahp->ah_priv.h; OS_MEMCPY(&ahp->ah_priv, &ar5416hal_10, sizeof(struct ath_hal_private)); ah->ah_dev = dev; ah->ah_sc = sc; ah->ah_set11nTxDesc = ar5416Set11nTxDesc_20; ah->ah_set11nRateScenario = ar5416Set11nRateScenario_20; ah->ah_set11nAggrFirst = ar5416Set11nAggrFirst_20; ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle_20; ah->ah_set11nAggrLast = ar5416Set11nAggrLast_20; ah->ah_clr11nAggr = ar5416Clr11nAggr_20; ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration_20; ah->ah_setupRxDesc = ar5416SetupRxDesc_20; ah->ah_procRxDescFast = ar5416ProcRxDescFast_20; ah->ah_setupTxDesc = ar5416SetupTxDesc_20; ah->ah_fillTxDesc = ar5416FillTxDesc_20; ah->ah_fillKeyTxDesc = ar5416FillKeyTxDesc_20; ah->ah_procTxDesc = ar5416ProcTxDesc_20; ah->ah_set11nVirtualMoreFrag = ar5416Set11nVirtualMoreFrag_20; return ah; } /**********************/ /* Interrupt Handling */ /**********************/ HAL_BOOL ar5416IsInterruptPending(struct ath_hal *ah) { a_uint32_t host_isr = ioread32_mac(AR_INTR_ASYNC_CAUSE); /* * Some platforms trigger our ISR before applying power to * the card, so make sure. */ return ((host_isr != AR_INTR_SPURIOUS) && (host_isr & AR_INTR_MAC_IRQ)); } HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked) { a_uint32_t isr; #ifndef AR9100 HAL_BOOL fatal_int = AH_FALSE; a_uint32_t sync_cause; if (ioread32_mac(AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { if ((ioread32_mac(AR_RTC_STATUS) & AR_RTC_STATUS_M) != AR_RTC_STATUS_ON) { *masked = 0; return AH_FALSE; } } else { *masked = 0; return AH_FALSE; } #endif isr = ioread32_mac(AR_ISR_RAC); if (isr == 0xffffffff) { *masked = 0; return AH_FALSE; } *masked = isr & HAL_INT_COMMON; #ifdef AR5416_INT_MITIGATION if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) { *masked |= HAL_INT_RX; } if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM)) { *masked |= HAL_INT_TX; } #endif if (isr & AR_ISR_BCNMISC) { a_uint32_t s2_s; s2_s = ioread32_mac(AR_ISR_S2_S); if (s2_s & AR_ISR_S2_GTT) { *masked |= HAL_INT_GTT; } if (s2_s & AR_ISR_S2_CST) { *masked |= HAL_INT_CST; } } if (isr & (AR_ISR_RXOK | AR_ISR_RXERR)) *masked |= HAL_INT_RX; if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL)) { struct ath_hal_5416 *ahp = AH5416(ah); a_uint32_t s0_s, s1_s; *masked |= HAL_INT_TX; s0_s = ioread32_mac(AR_ISR_S0_S); s1_s = ioread32_mac(AR_ISR_S1_S); ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK); ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC); ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR); ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL); } #ifndef AR9100 sync_cause = ioread32_mac(AR_INTR_SYNC_CAUSE); fatal_int = ((sync_cause != AR_INTR_SPURIOUS) && (sync_cause & (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))) ? AH_TRUE : AH_FALSE; if (AH_TRUE == fatal_int) { iowrite32_mac(AR_INTR_SYNC_CAUSE_CLR, sync_cause); (void) ioread32_mac(AR_INTR_SYNC_CAUSE_CLR); } #endif return AH_TRUE; } HAL_INT ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints) { struct ath_hal_5416 *ahp = AH5416(ah); a_uint32_t omask = ahp->ah_maskReg; a_uint32_t mask; if (omask & HAL_INT_GLOBAL) { iowrite32_mac(AR_IER, AR_IER_DISABLE); (void) ioread32_mac(AR_IER); } mask = ints & HAL_INT_COMMON; if (ints & HAL_INT_TX) { #ifdef AR5416_INT_MITIGATION mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM; #else mask |= AR_IMR_TXOK; mask |= AR_IMR_TXDESC; #endif mask |= AR_IMR_TXERR; mask |= AR_IMR_TXEOL; } if (ints & HAL_INT_RX) { mask |= AR_IMR_RXERR; #ifdef AR5416_INT_MITIGATION mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; #else mask |= AR_IMR_RXOK | AR_IMR_RXDESC; #endif } if (ints & (HAL_INT_GTT | HAL_INT_CST)) { mask |= AR_IMR_BCNMISC; } iowrite32_mac(AR_IMR, mask); (void) ioread32_mac(AR_IMR); ahp->ah_maskReg = ints; /* Re-enable interrupts if they were enabled before. */ if (ints & HAL_INT_GLOBAL) { iowrite32_mac(AR_IER, AR_IER_ENABLE); /* See explanation above... */ (void) ioread32_mac(AR_IER); } iowrite32_mac(AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ); iowrite32_mac(AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); iowrite32_mac(AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_ALL); return omask; } /****************/ /* TSF Handling */ /****************/ #define ATH9K_HTC_MAX_TSF_READ 3 u_int64_t ar5416GetTsf64(struct ath_hal *ah) { a_uint32_t tsf_lower, tsf_upper1, tsf_upper2; a_int32_t i; tsf_upper1 = ioread32_mac(AR_TSF_U32); for (i = 0; i < ATH9K_HTC_MAX_TSF_READ; i++) { tsf_lower = ioread32_mac(AR_TSF_L32); tsf_upper2 = ioread32_mac(AR_TSF_U32); if (tsf_upper2 == tsf_upper1) break; tsf_upper1 = tsf_upper2; } return (((u_int64_t)tsf_upper2 << 32) | tsf_lower); } /******/ /* RX */ /******/ void ar5416SetRxDP(struct ath_hal *ah, a_uint32_t rxdp) { iowrite32_mac(AR_RXDP, rxdp); HALASSERT(ioread32_mac(AR_RXDP) == rxdp); } HAL_BOOL ar5416StopDmaReceive(struct ath_hal *ah) { iowrite32_mac(AR_CR, AR_CR_RXD); /* Set receive disable bit */ if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) { return AH_FALSE; } else { return AH_TRUE; } } void ar5416SetRxFilter(struct ath_hal *ah, a_uint32_t bits) { a_uint32_t phybits; iowrite32_mac(AR_RX_FILTER, (bits & 0xff) | AR_RX_COMPR_BAR); phybits = 0; if (bits & HAL_RX_FILTER_PHYRADAR) phybits |= AR_PHY_ERR_RADAR; if (bits & HAL_RX_FILTER_PHYERR) phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; iowrite32_mac(AR_PHY_ERR, phybits); if (phybits) { iowrite32_mac(AR_RXCFG, ioread32_mac(AR_RXCFG) | AR_RXCFG_ZLFDMA); } else { iowrite32_mac(AR_RXCFG, ioread32_mac(AR_RXCFG) & ~AR_RXCFG_ZLFDMA); } } void ar5416EnableReceive(struct ath_hal *ah) { iowrite32_mac(AR_CR, AR_CR_RXE); } void ar5416StopPcuReceive(struct ath_hal *ah) { OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); } HAL_BOOL ar5416SetupRxDesc_20(struct ath_rx_desc *ds, a_uint32_t size, a_uint32_t flags) { struct ar5416_desc *ads = AR5416DESC(ds); HALASSERT((size &~ AR_BufLen) == 0); ads->ds_ctl1 = size & AR_BufLen; if (flags & HAL_RXDESC_INTREQ) ads->ds_ctl1 |= AR_RxIntrReq; /* this should be enough */ ads->ds_rxstatus8 &= ~AR_RxDone; return AH_TRUE; } HAL_STATUS ar5416ProcRxDescFast_20(struct ath_hal *ah, struct ath_rx_desc *ds, a_uint32_t pa, struct ath_desc *nds, struct ath_rx_status *rx_stats) { struct ar5416_desc ads; struct ar5416_desc *adsp = AR5416DESC(ds); struct ar5416_desc *ands = AR5416DESC(nds); if ((adsp->ds_rxstatus8 & AR_RxDone) == 0) return HAL_EINPROGRESS; /* * Given the use of a self-linked tail be very sure that the hw is * done with this descriptor; the hw may have done this descriptor * once and picked it up again...make sure the hw has moved on. */ if ((ands->ds_rxstatus8 & AR_RxDone) == 0 && ioread32_mac(AR_RXDP) == pa) return HAL_EINPROGRESS; /* * Now we need to get the stats from the descriptor. Since desc are * uncached, lets make a copy of the stats first. Note that, since we * touch most of the rx stats, a memcpy would always be more efficient * * Next we fill in all values in a caller passed stack variable. * This reduces the number of uncached accesses. * Do this copy here, after the check so that when the checks fail, we * dont end up copying the entire stats uselessly. */ ads.u.rx = adsp->u.rx; rx_stats->rs_status = 0; rx_stats->rs_flags = 0; rx_stats->rs_datalen = ads.ds_rxstatus1 & AR_DataLen; rx_stats->rs_tstamp = ads.AR_RcvTimestamp; /* XXX what about KeyCacheMiss? */ rx_stats->rs_rssi_combined = MS(ads.ds_rxstatus4, AR_RxRSSICombined); rx_stats->rs_rssi_ctl0 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt00); rx_stats->rs_rssi_ctl1 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt01); rx_stats->rs_rssi_ctl2 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt02); rx_stats->rs_rssi_ext0 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt10); rx_stats->rs_rssi_ext1 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt11); rx_stats->rs_rssi_ext2 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt12); if (ads.ds_rxstatus8 & AR_RxKeyIdxValid) rx_stats->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx); else rx_stats->rs_keyix = HAL_RXKEYIX_INVALID; /* NB: caller expected to do rate table mapping */ rx_stats->rs_rate = RXSTATUS_RATE(ah, (&ads)); rx_stats->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0; rx_stats->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0; rx_stats->rs_moreaggr = (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0; rx_stats->rs_flags |= (ads.ds_rxstatus3 & AR_GI) ? HAL_RX_GI : 0; rx_stats->rs_flags |= (ads.ds_rxstatus3 & AR_2040) ? HAL_RX_2040 : 0; if (ads.ds_rxstatus8 & AR_PreDelimCRCErr) rx_stats->rs_flags |= HAL_RX_DELIM_CRC_PRE; if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) rx_stats->rs_flags |= HAL_RX_DELIM_CRC_POST; if (ads.ds_rxstatus8 & AR_DecryptBusyErr) rx_stats->rs_flags |= HAL_RX_DECRYPT_BUSY; if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) { /* * These four bits should not be set together. The * 5416 spec states a Michael error can only occur if * DecryptCRCErr not set (and TKIP is used). Experience * indicates however that you can also get Michael errors * when a CRC error is detected, but these are specious. * Consequently we filter them out here so we don't * confuse and/or complicate drivers. */ if (ads.ds_rxstatus8 & AR_CRCErr) rx_stats->rs_status |= HAL_RXERR_CRC; else if (ads.ds_rxstatus8 & AR_PHYErr) { a_uint32_t phyerr; rx_stats->rs_status |= HAL_RXERR_PHY; phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode); rx_stats->rs_phyerr = phyerr; } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr) rx_stats->rs_status |= HAL_RXERR_DECRYPT; else if (ads.ds_rxstatus8 & AR_MichaelErr) rx_stats->rs_status |= HAL_RXERR_MIC; } rx_stats->evm0=ads.AR_RxEVM0; rx_stats->evm1=ads.AR_RxEVM1; rx_stats->evm2=ads.AR_RxEVM2; return HAL_OK; } /******/ /* TX */ /******/ HAL_BOOL ar5416UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel) { struct ath_hal_5416 *ahp = AH5416(ah); a_uint32_t txcfg, curLevel, newLevel; HAL_INT omask; /* * Disable interrupts while futzing with the fifo level. */ omask = ar5416SetInterrupts(ah, ahp->ah_maskReg &~ HAL_INT_GLOBAL); txcfg = ioread32_mac(AR_TXCFG); curLevel = MS(txcfg, AR_FTRIG); newLevel = curLevel; if (bIncTrigLevel) { if (curLevel < MAX_TX_FIFO_THRESHOLD) newLevel ++; } else if (curLevel > MIN_TX_FIFO_THRESHOLD) newLevel--; if (newLevel != curLevel) iowrite32_mac(AR_TXCFG, (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG)); /* re-enable chip interrupts */ ar5416SetInterrupts(ah, omask); return (newLevel != curLevel); } HAL_BOOL ar5416SetTxDP(struct ath_hal *ah, a_uint32_t q, a_uint32_t txdp) { HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues); HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); /* * Make sure that TXE is deasserted before setting the TXDP. If TXE * is still asserted, setting TXDP will have no effect. */ HALASSERT((ioread32_mac(AR_Q_TXE) & (1 << q)) == 0); iowrite32_mac(AR_QTXDP(q), txdp); return AH_TRUE; } HAL_BOOL ar5416StartTxDma(struct ath_hal *ah, a_uint32_t q) { HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues); HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); /* Check to be sure we're not enabling a q that has its TXD bit set. */ HALASSERT((ioread32_mac(AR_Q_TXD) & (1 << q)) == 0); iowrite32_mac(AR_Q_TXE, 1 << q); return AH_TRUE; } a_uint32_t ar5416NumTxPending(struct ath_hal *ah, a_uint32_t q) { a_uint32_t npend; HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues); HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); npend = ioread32_mac(AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT; if (npend == 0) { /* * Pending frame count (PFC) can momentarily go to zero * while TXE remains asserted. In other words a PFC of * zero is not sufficient to say that the queue has stopped. */ if (ioread32_mac(AR_Q_TXE) & (1 << q)) npend = 1; } #ifdef DEBUG if (npend && (AH5416(ah)->ah_txq[q].tqi_type == HAL_TX_QUEUE_CAB)) { if (ioread32_mac(AR_Q_RDYTIMESHDN) & (1 << q)) { isrPrintf("RTSD on CAB queue\n"); /* Clear the ReadyTime shutdown status bits */ iowrite32_mac(AR_Q_RDYTIMESHDN, 1 << q); } } #endif return npend; } HAL_BOOL ar5416AbortTxDma(struct ath_hal *ah) { a_int32_t i, q; /* * set txd on all queues */ iowrite32_mac(AR_Q_TXD, AR_Q_TXD_M); /* * set tx abort bits */ OS_REG_SET_BIT(ah, AR_PCU_MISC, (AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF)); OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); OS_REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); /* * wait on all tx queues */ for (q = 0; q < AR_NUM_QCU; q++) { for (i = 0; i < AR5416_ABORT_LOOPS; i++) { if (!ar5416NumTxPending(ah, q)) break; OS_DELAY(AR5416_ABORT_WAIT); } if (i == AR5416_ABORT_LOOPS) { return AH_FALSE; } } /* * clear tx abort bits */ OS_REG_CLR_BIT(ah, AR_PCU_MISC, (AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF)); OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); OS_REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); /* * clear txd */ iowrite32_mac(AR_Q_TXD, 0); return AH_TRUE; } HAL_BOOL ar5416StopTxDma(struct ath_hal*ah, a_uint32_t q) { a_uint32_t i; HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues); HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); iowrite32_mac(AR_Q_TXD, 1 << q); for (i = 1000; i != 0; i--) { if (ar5416NumTxPending(ah, q) == 0) break; OS_DELAY(100); /* XXX get actual value */ } iowrite32_mac(AR_Q_TXD, 0); return (i != 0); } HAL_BOOL ar5416SetupTxDesc_20(struct ath_tx_desc *ds, a_uint32_t pktLen, a_uint32_t hdrLen, HAL_PKT_TYPE type, a_uint32_t txPower, a_uint32_t txRate0, a_uint32_t txTries0, a_uint32_t keyIx, a_uint32_t flags, a_uint32_t rtsctsRate, a_uint32_t rtsctsDuration) { #define RTSCTS (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA) struct ar5416_desc *ads = AR5416DESC(ds); (void) hdrLen; ads->ds_txstatus9 &= ~AR_TxDone; HALASSERT(txTries0 != 0); HALASSERT(isValidPktType(type)); HALASSERT(isValidTxRate(txRate0)); HALASSERT((flags & RTSCTS) != RTSCTS); if (txPower > 63) txPower=63; ads->ds_ctl0 = (pktLen & AR_FrameLen) | (txPower << AR_XmitPower_S) | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0) | (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0) | (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0); ads->ds_ctl1 = (type << AR_FrameType_S) | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0); ads->ds_ctl2 = SM(txTries0, AR_XmitDataTries0); ads->ds_ctl3 = (txRate0 << AR_XmitRate0_S); ads->ds_ctl7 = SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel0) | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel1) | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel2) | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel3); if (keyIx != HAL_TXKEYIX_INVALID) { /* XXX validate key index */ ads->ds_ctl1 |= SM(keyIx, AR_DestIdx); ads->ds_ctl0 |= AR_DestIdxValid; } if (flags & RTSCTS) { if (!isValidTxRate(rtsctsRate)) { return AH_FALSE; } /* XXX validate rtsctsDuration */ ads->ds_ctl0 |= (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0) | (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0); ads->ds_ctl2 |= SM(rtsctsDuration, AR_BurstDur); ads->ds_ctl3 |= (rtsctsRate << AR_RTSCTSRate_S); } return AH_TRUE; #undef RTSCTS } HAL_BOOL ar5416FillTxDesc_20(struct ath_tx_desc *ds, a_uint32_t segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg, const struct ath_tx_desc *ds0) { struct ar5416_desc *ads = AR5416DESC(ds); HALASSERT((segLen &~ AR_BufLen) == 0); if (firstSeg) { /* * First descriptor, don't clobber xmit control data * setup by ar5416SetupTxDesc. */ ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore); } else if (lastSeg) { /* * Last descriptor in a multi-descriptor frame, * copy the multi-rate transmit parameters from * the first frame for processing on completion. */ ads->ds_ctl0 = 0; ads->ds_ctl1 = segLen; ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2; ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3; } else { /* * Intermediate descriptor in a multi-descriptor frame. */ ads->ds_ctl0 = 0; ads->ds_ctl1 = segLen | AR_TxMore; ads->ds_ctl2 = 0; ads->ds_ctl3 = 0; } ads->ds_txstatus0 = ads->ds_txstatus1 = 0; return AH_TRUE; } HAL_BOOL ar5416FillKeyTxDesc_20(struct ath_tx_desc *ds, HAL_KEY_TYPE keyType) { struct ar5416_desc *ads = AR5416DESC(ds); ads->ds_ctl6 = SM(keyType, AR_EncrType); return AH_TRUE; } HAL_STATUS ar5416ProcTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *gds) { struct ar5416_desc *ads = AR5416DESC(gds); struct ath_tx_desc *ds = (struct ath_tx_desc *)gds; if ((ads->ds_txstatus9 & AR_TxDone) == 0) return HAL_EINPROGRESS; ads->ds_txstatus9 &= ~AR_TxDone; /* Update software copies of the HW status */ ds->ds_txstat.ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum); ds->ds_txstat.ts_tstamp = ads->AR_SendTimestamp; ds->ds_txstat.ts_status = 0; ds->ds_txstat.ts_flags = 0; if (ads->ds_txstatus1 & AR_ExcessiveRetries) ds->ds_txstat.ts_status |= HAL_TXERR_XRETRY; if (ads->ds_txstatus1 & AR_Filtered) ds->ds_txstat.ts_status |= HAL_TXERR_FILT; if (ads->ds_txstatus1 & AR_FIFOUnderrun) ds->ds_txstat.ts_status |= HAL_TXERR_FIFO; if (ads->ds_txstatus9 & AR_TxOpExceeded) ds->ds_txstat.ts_status |= HAL_TXERR_XTXOP; if (ads->ds_txstatus1 & AR_TxTimerExpired) ds->ds_txstat.ts_status |= HAL_TXERR_TIMER_EXPIRED; if (ads->ds_txstatus1 & AR_DescCfgErr) ds->ds_txstat.ts_flags |= HAL_TX_DESC_CFG_ERR; if (ads->ds_txstatus1 & AR_TxDataUnderrun) { ds->ds_txstat.ts_flags |= HAL_TX_DATA_UNDERRUN; ar5416UpdateTxTrigLevel(ah, AH_TRUE); } if (ads->ds_txstatus1 & AR_TxDelimUnderrun) { ds->ds_txstat.ts_flags |= HAL_TX_DELIM_UNDERRUN; ar5416UpdateTxTrigLevel(ah, AH_TRUE); } if (ads->ds_txstatus0 & AR_TxBaStatus) { ds->ds_txstat.ts_flags |= HAL_TX_BA; ds->ds_txstat.ba_low = ads->AR_BaBitmapLow; ds->ds_txstat.ba_high = ads->AR_BaBitmapHigh; } /* * Extract the transmit rate used and mark the rate as * ``alternate'' if it wasn't the series 0 rate. */ ds->ds_txstat.ts_rate = MS(ads->ds_txstatus9, AR_FinalTxIdx); ds->ds_txstat.ts_rssi_combined = MS(ads->ds_txstatus5, AR_TxRSSICombined); ds->ds_txstat.ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00); ds->ds_txstat.ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01); ds->ds_txstat.ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02); ds->ds_txstat.ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10); ds->ds_txstat.ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11); ds->ds_txstat.ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12); ds->ds_txstat.evm0 = ads->AR_TxEVM0; ds->ds_txstat.evm1 = ads->AR_TxEVM1; ds->ds_txstat.evm2 = ads->AR_TxEVM2; ds->ds_txstat.ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt); ds->ds_txstat.ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt); ds->ds_txstat.ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt); ds->ds_txstat.ts_antenna = 0; /* ignored for owl */ return HAL_OK; } void ar5416Set11nTxDesc_20(struct ath_tx_desc *ds, a_uint32_t pktLen, HAL_PKT_TYPE type, a_uint32_t txPower, a_uint32_t keyIx, HAL_KEY_TYPE keyType, a_uint32_t flags) { struct ar5416_desc *ads = AR5416DESC(ds); HALASSERT(isValidPktType(type)); HALASSERT(isValidKeyType(keyType)); if (txPower > 63) txPower = 63; ads->ds_ctl0 = (pktLen & AR_FrameLen) | (flags & HAL_TXDESC_VMF ? AR_VirtMoreFrag : 0) | SM(txPower, AR_XmitPower) | (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0) | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0) | (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0) | (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0) | (keyIx != HAL_TXKEYIX_INVALID ? AR_DestIdxValid : 0) | (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0); ads->ds_ctl1 = (keyIx != HAL_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0) | SM(type, AR_FrameType) | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0) | (flags & HAL_TXDESC_EXT_ONLY ? AR_ExtOnly : 0) | (flags & HAL_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0); ads->ds_ctl6 = SM(keyType, AR_EncrType); } void ar5416Set11nRateScenario_20(struct ath_tx_desc *ds, a_uint32_t durUpdateEn, a_uint32_t rtsctsRate, HAL_11N_RATE_SERIES series[], a_uint32_t nseries, a_uint32_t flags) { struct ar5416_desc *ads = AR5416DESC(ds); a_uint32_t ds_ctl0; HALASSERT(nseries == 4); (void)nseries; /* * Rate control settings override */ ds_ctl0 = ads->ds_ctl0; if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) { if (flags & HAL_TXDESC_RTSENA) { ds_ctl0 &= ~AR_CTSEnable; ds_ctl0 |= AR_RTSEnable; } else { ds_ctl0 &= ~AR_RTSEnable; ds_ctl0 |= AR_CTSEnable; } } else { /* this line is only difference between merlin and k2 * Current one is for merlin */ ds_ctl0 = (ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable)); } ads->ds_ctl0 = ds_ctl0; ads->ds_ctl2 = set11nTries(series, 0) | set11nTries(series, 1) | set11nTries(series, 2) | set11nTries(series, 3) | (durUpdateEn ? AR_DurUpdateEn : 0); ads->ds_ctl3 = set11nRate(series, 0) | set11nRate(series, 1) | set11nRate(series, 2) | set11nRate(series, 3); ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0) | set11nPktDurRTSCTS(series, 1); ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2) | set11nPktDurRTSCTS(series, 3); ads->ds_ctl7 = set11nRateFlags(series, 0) | set11nRateFlags(series, 1) | set11nRateFlags(series, 2) | set11nRateFlags(series, 3) | SM(rtsctsRate, AR_RTSCTSRate); } void ar5416Set11nAggrFirst_20(struct ath_tx_desc *ds, a_uint32_t aggrLen, a_uint32_t numDelims) { struct ar5416_desc *ads = AR5416DESC(ds); ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr); ads->ds_ctl6 &= ~(AR_AggrLen | AR_PadDelim); ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen) | SM(numDelims, AR_PadDelim); } void ar5416Set11nAggrMiddle_20(struct ath_tx_desc *ds, a_uint32_t numDelims) { struct ar5416_desc *ads = AR5416DESC(ds); a_uint32_t ctl6; ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr); /* * We use a stack variable to manipulate ctl6 to reduce uncached * read modify, modfiy, write. */ ctl6 = ads->ds_ctl6; ctl6 &= ~AR_PadDelim; ctl6 |= SM(numDelims, AR_PadDelim); ads->ds_ctl6 = ctl6; } void ar5416Set11nAggrLast_20(struct ath_tx_desc *ds) { struct ar5416_desc *ads = AR5416DESC(ds); ads->ds_ctl1 |= AR_IsAggr; ads->ds_ctl1 &= ~AR_MoreAggr; ads->ds_ctl6 &= ~AR_PadDelim; } void ar5416Clr11nAggr_20(struct ath_tx_desc *ds) { struct ar5416_desc *ads = AR5416DESC(ds); ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr); } void ar5416Set11nBurstDuration_20(struct ath_tx_desc *ds, a_uint32_t burstDuration) { struct ar5416_desc *ads = AR5416DESC(ds); ads->ds_ctl2 &= ~AR_BurstDur; ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur); } void ar5416Set11nVirtualMoreFrag_20(struct ath_tx_desc *ds, a_uint32_t vmf) { struct ar5416_desc *ads = AR5416DESC(ds); if (vmf) { ads->ds_ctl0 |= AR_VirtMoreFrag; } else { ads->ds_ctl0 &= ~AR_VirtMoreFrag; } } open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/ar5416_phy.c000077500000000000000000000403671321570333100265110ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "ah.h" #include "ah_internal.h" #include "ar5416.h" #ifdef MAGPIE_MERLIN #define OFDM IEEE80211_T_OFDM #define CCK IEEE80211_T_CCK #define TURBO IEEE80211_T_TURBO #define XR ATHEROS_T_XR #define HT IEEE80211_T_HT HAL_RATE_TABLE ar5416_11a_table = { 8, /* number of rates */ { 0 }, { /* short ctrl */ /* valid rateCode Preamble dot11Rate Rate */ /* 6 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 6000, 0x0b, 0x00, (0x80|12), 0 }, /* 9 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 9000, 0x0f, 0x00, 18, 0 }, /* 12 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 12000, 0x0a, 0x00, (0x80|24), 2 }, /* 18 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 18000, 0x0e, 0x00, 36, 2 }, /* 24 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 24000, 0x09, 0x00, (0x80|48), 4 }, /* 36 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 36000, 0x0d, 0x00, 72, 4 }, /* 48 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 48000, 0x08, 0x00, 96, 4 }, /* 54 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 54000, 0x0c, 0x00, 108, 4 } }, }; HAL_RATE_TABLE ar5416_11b_table = { 4, /* number of rates */ { 0 }, { /* short ctrl */ /* valid rateCode Preamble dot11Rate Rate */ /* 1 Mb */ { AH_TRUE, CCK, 60, 60, 60, 1000, 0x1b, 0x00, (0x80| 2), 0 }, /* 2 Mb */ { AH_TRUE, CCK, 60, 60, 60, 2000, 0x1a, 0x04, (0x80| 4), 1 }, /* 5.5 Mb */ { AH_TRUE, CCK, 60, 60, 60, 5500, 0x19, 0x04, (0x80|11), 1 }, /* 11 Mb */ { AH_TRUE, CCK, 60, 60, 60, 11000, 0x18, 0x04, (0x80|22), 1 } }, }; HAL_RATE_TABLE ar5416_11g_table = { 12, /* number of rates */ { 0 }, { /* short ctrl */ /* valid rateCode Preamble dot11Rate Rate */ /* 1 Mb */ { AH_TRUE, CCK, 60, 60, 60, 1000, 0x1b, 0x00, (0x80| 2), 0 }, /* 2 Mb */ { AH_TRUE, CCK, 60, 60, 60, 2000, 0x1a, 0x04, (0x80| 4), 1 }, /* 5.5 Mb */ { AH_TRUE, CCK, 60, 60, 60, 5500, 0x19, 0x04, (0x80|11), 2 }, /* 11 Mb */ { AH_TRUE, CCK, 60, 60, 60, 11000, 0x18, 0x04, (0x80|22), 3 }, /* Hardware workaround - remove rates 6, 9 from rate ctrl */ /* 6 Mb */ { AH_FALSE, OFDM, 60, 60, 60, 6000, 0x0b, 0x00, 12, 4 }, /* 9 Mb */ { AH_FALSE, OFDM, 60, 60, 60, 9000, 0x0f, 0x00, 18, 4 }, /* 12 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 12000, 0x0a, 0x00, 24, 6 }, /* 18 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 18000, 0x0e, 0x00, 36, 6 }, /* 24 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 24000, 0x09, 0x00, 48, 8 }, /* 36 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 36000, 0x0d, 0x00, 72, 8 }, /* 48 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 48000, 0x08, 0x00, 96, 8 }, /* 54 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 54000, 0x0c, 0x00, 108, 8 } }, }; HAL_RATE_TABLE ar5416_11ng_table = { 28, /* number of rates */ { -1 }, { /* short ctrl */ /* valid rateCode Preamble dot11Rate Rate */ /* 1 Mb */ { AH_TRUE, CCK, 60, 60, 60, 1000, 0x1b, 0x00, (0x80| 2), 0 }, /* 2 Mb */ { AH_TRUE, CCK, 60, 60, 60, 2000, 0x1a, 0x04, (0x80| 4), 1 }, /* 5.5 Mb */ { AH_TRUE, CCK, 60, 60, 60, 5500, 0x19, 0x04, (0x80|11), 2 }, /* 11 Mb */ { AH_TRUE, CCK, 60, 60, 60, 11000, 0x18, 0x04, (0x80|22), 3 }, /* Hardware workaround - remove rates 6, 9 from rate ctrl */ /* 6 Mb */ { AH_FALSE, OFDM, 60, 60, 60, 6000, 0x0b, 0x00, 12, 4 }, /* 9 Mb */ { AH_FALSE, OFDM, 60, 60, 60, 9000, 0x0f, 0x00, 18, 4 }, /* 12 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 12000, 0x0a, 0x00, 24, 6 }, /* 18 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 18000, 0x0e, 0x00, 36, 6 }, /* 24 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 24000, 0x09, 0x00, 48, 8 }, /* 36 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 36000, 0x0d, 0x00, 72, 8 }, /* 48 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 48000, 0x08, 0x00, 96, 8 }, /* 54 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 54000, 0x0c, 0x00, 108, 8 }, /* 6.5 Mb */ { AH_TRUE, HT, 60,60, 60, 6500, 0x80, 0x00, 0, 4 }, /* 13 Mb */ { AH_TRUE, HT, 60, 60, 60, 13000, 0x81, 0x00, 1, 6 }, /*19.5 Mb */ { AH_TRUE, HT, 60,60, 60, 19500, 0x82, 0x00, 2, 6 }, /* 26 Mb */ { AH_TRUE, HT, 60, 60, 60, 26000, 0x83, 0x00, 3, 8 }, /* 39 Mb */ { AH_TRUE, HT, 60, 60, 60, 39000, 0x84, 0x00, 4, 8 }, /* 52 Mb */ { AH_TRUE, HT, 60, 60, 60, 52000, 0x85, 0x00, 5, 8 }, /*58.5 Mb */ { AH_TRUE, HT, 60,60,60, 58500, 0x86, 0x00, 6, 8 }, /* 65 Mb */ { AH_TRUE, HT, 60, 60, 60, 65000, 0x87, 0x00, 7, 8 }, /* 13 Mb */ { AH_TRUE, HT, 60, 60, 60, 13000, 0x88, 0x00, 8, 4 }, /* 26 Mb */ { AH_TRUE, HT, 60, 60, 60, 26000, 0x89, 0x00, 9, 6 }, /* 39 Mb */ { AH_TRUE, HT, 60, 60, 60, 39000, 0x8a, 0x00, 10, 6 }, /* 52 Mb */ { AH_TRUE, HT, 60, 60, 60, 52000, 0x8b, 0x00, 11, 8 }, /* 78 Mb */ { AH_TRUE, HT, 60, 60, 60, 78000, 0x8c, 0x00, 12, 8 }, /* 104 Mb */ { AH_TRUE, HT, 60, 60, 60, 104000, 0x8d, 0x00, 13, 8 }, /* 117 Mb */ { AH_TRUE, HT, 60, 60, 60, 117000, 0x8e, 0x00, 14, 8 }, /* 130 Mb */ { AH_TRUE, HT, 60, 60, 60, 130000, 0x8f, 0x00, 15, 8 }, }, }; HAL_RATE_TABLE ar5416_11na_table = { 24, /* number of rates */ { -1 }, { /* short ctrl */ /* valid rateCode Preamble dot11Rate Rate */ /* 6 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 6000, 0x0b, 0x00, (0x80|12), 0 }, /* 9 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 9000, 0x0f, 0x00, 18, 0 }, /* 12 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 12000, 0x0a, 0x00, (0x80|24), 2 }, /* 18 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 18000, 0x0e, 0x00, 36, 2 }, /* 24 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 24000, 0x09, 0x00, (0x80|48), 4 }, /* 36 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 36000, 0x0d, 0x00, 72, 4 }, /* 48 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 48000, 0x08, 0x00, 96, 4 }, /* 54 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 54000, 0x0c, 0x00, 108, 4 }, /* 6.5 Mb */ { AH_TRUE, HT, 60, 60, 60, 6500, 0x80, 0x00, 0, 0 }, /* 13 Mb */ { AH_TRUE, HT, 60, 60, 60, 13000, 0x81, 0x00, 1, 2 }, /*19.5 Mb */ { AH_TRUE, HT, 60, 60, 60, 19500, 0x82, 0x00, 2, 2 }, /* 26 Mb */ { AH_TRUE, HT, 60, 60, 60, 26000, 0x83, 0x00, 3, 4 }, /* 39 Mb */ { AH_TRUE, HT, 60, 60, 60, 39000, 0x84, 0x00, 4, 4 }, /* 52 Mb */ { AH_TRUE, HT, 60, 60, 60, 52000, 0x85, 0x00, 5, 4 }, /*58.5 Mb */ { AH_TRUE, HT, 60, 60, 60, 58500, 0x86, 0x00, 6, 4 }, /* 65 Mb */ { AH_TRUE, HT, 60, 60, 60, 65000, 0x87, 0x00, 7, 4 }, /* 13 Mb */ { AH_TRUE, HT, 60, 60, 60, 13000, 0x88, 0x00, 8, 0 }, /* 26 Mb */ { AH_TRUE, HT, 60, 60, 60, 26000, 0x89, 0x00, 9, 2 }, /* 39 Mb */ { AH_TRUE, HT, 60, 60, 60, 39000, 0x8a, 0x00, 10, 2 }, /* 52 Mb */ { AH_TRUE, HT, 60, 60, 60, 52000, 0x8b, 0x00, 11, 4 }, /* 78 Mb */ { AH_TRUE, HT, 60, 60, 60, 78000, 0x8c, 0x00, 12, 4 }, /* 104 Mb */ { AH_TRUE, HT, 60, 60, 60, 104000, 0x8d, 0x00, 13, 4 }, /* 117 Mb */ { AH_TRUE, HT, 60, 60, 60, 117000, 0x8e, 0x00, 14, 4 }, /* 130 Mb */ { AH_TRUE, HT, 60, 60, 60, 130000, 0x8f, 0x00, 15, 4 }, }, }; #undef OFDM #undef CCK #undef TURBO #undef XR #undef HT #undef HT_HGI const HAL_RATE_TABLE * ar5416GetRateTable(struct ath_hal *ah, a_uint32_t mode) { HAL_RATE_TABLE *rt; switch (mode) { case HAL_MODE_11A: rt = &ar5416_11a_table; break; case HAL_MODE_11B: rt = &ar5416_11b_table; break; case HAL_MODE_11G: rt = &ar5416_11g_table; break; case HAL_MODE_11NG: rt = &ar5416_11ng_table; break; case HAL_MODE_11NA: rt = &ar5416_11na_table; break; default: return AH_NULL; } return rt; } #else #define OFDM IEEE80211_T_OFDM #define CCK IEEE80211_T_CCK #define TURBO IEEE80211_T_TURBO #define XR ATHEROS_T_XR #define HT IEEE80211_T_HT HAL_RATE_TABLE ar5416_11ng_table = { 33, /* number of rates */ { -1 }, { /* short ctrl */ /* valid rateCode Preamble dot11Rate Rate */ /*[ 0] 1 Mb */ { AH_TRUE, CCK, 1000, 0x1b, 0x00, (0x80| 2), 0 }, /*[ 1] 2 Mb */ { AH_TRUE, CCK, 2000, 0x1a, 0x04, (0x80| 4), 1 }, /*[ 2] 5.5 Mb */ { AH_TRUE, CCK, 5500, 0x19, 0x04, (0x80|11), 2 }, /*[ 3] 11 Mb */ { AH_TRUE, CCK, 11000, 0x18, 0x04, (0x80|22), 3 }, /* Hardware workaround - remove rates 6, 9 from rate ctrl */ /*[ 4] 6 Mb */ { AH_FALSE, OFDM, 6000, 0x0b, 0x00, 12, 4 }, /*[ 5] 9 Mb */ { AH_FALSE, OFDM, 9000, 0x0f, 0x00, 18, 4 }, /*[ 6] 12 Mb */ { AH_TRUE, OFDM, 12000, 0x0a, 0x00, 24, 6 }, /*[ 7] 18 Mb */ { AH_TRUE, OFDM, 18000, 0x0e, 0x00, 36, 6 }, /*[ 8] 24 Mb */ { AH_TRUE, OFDM, 24000, 0x09, 0x00, 48, 8 }, /*[ 9] 36 Mb */ { AH_TRUE, OFDM, 36000, 0x0d, 0x00, 72, 8 }, /*[10] 48 Mb */ { AH_TRUE, OFDM, 48000, 0x08, 0x00, 96, 8 }, /*[11] 54 Mb */ { AH_TRUE, OFDM, 54000, 0x0c, 0x00, 108, 8 }, /*[12] 6.5 Mb */ { AH_TRUE, HT, 6500, 0x80, 0x00, 0, 4 }, /*[13] 13 Mb */ { AH_TRUE, HT, 13000, 0x81, 0x00, 1, 6 }, /*[14]19.5 Mb */ { AH_TRUE, HT, 19500, 0x82, 0x00, 2, 6 }, /*[15] 26 Mb */ { AH_TRUE, HT, 26000, 0x83, 0x00, 3, 8 }, /*[16] 39 Mb */ { AH_TRUE, HT, 39000, 0x84, 0x00, 4, 8 }, /*[17] 39 Mb */ { AH_TRUE, HT, 39000, 0x84, 0x00, 4, 8 }, /*[18] 52 Mb */ { AH_TRUE, HT, 52000, 0x85, 0x00, 5, 8 }, /*[19] 52 Mb */ { AH_TRUE, HT, 52000, 0x85, 0x00, 5, 8 }, /*[20]58.5 Mb */ { AH_TRUE, HT, 58500, 0x86, 0x00, 6, 8 }, /*[21]58.5 Mb */ { AH_TRUE, HT, 58500, 0x86, 0x00, 6, 8 }, /*[22] 65 Mb */ { AH_TRUE, HT, 65000, 0x87, 0x00, 7, 8 }, /*[23] 65 Mb */ { AH_TRUE, HT, 65000, 0x87, 0x00, 7, 8 }, /*[24] 52 Mb */ { AH_TRUE, HT, 52000, 0x8b, 0x00, 11, 8 }, /*[25] 78 Mb */ { AH_TRUE, HT, 78000, 0x8c, 0x00, 12, 8 }, /*[26] 78 Mb */ { AH_TRUE, HT, 78000, 0x8c, 0x00, 12, 8 }, /*[27] 104 Mb */ { AH_TRUE, HT, 104000, 0x8d, 0x00, 13, 8 }, /*[28] 104 Mb */ { AH_TRUE, HT, 104000, 0x8d, 0x00, 13, 8 }, /*[29] 117 Mb */ { AH_TRUE, HT, 117000, 0x8e, 0x00, 14, 8 }, /*[30] 117 Mb */ { AH_TRUE, HT, 117000, 0x8e, 0x00, 14, 8 }, /*[31] 130 Mb */ { AH_TRUE, HT, 130000, 0x8f, 0x00, 15, 8 }, /*[32] 130 Mb */ { AH_TRUE, HT, 130000, 0x8f, 0x00, 15, 8 }, }, }; #ifdef ATH_SUPPORT_A_MODE HAL_RATE_TABLE ar5416_11na_table = { 28, /* number of rates */ { -1 }, { /* short ctrl */ /* valid rateCode Preamble dot11Rate Rate */ /*[ 0] 6 Mb */ { AH_TRUE, OFDM, 6000, 0x0b, 0x00, (0x80|12), 0 }, /*[ 1] 9 Mb */ { AH_TRUE, OFDM, 9000, 0x0f, 0x00, 18, 0 }, /*[ 2] 12 Mb */ { AH_TRUE, OFDM, 12000, 0x0a, 0x00, (0x80|24), 2 }, /*[ 3] 18 Mb */ { AH_TRUE, OFDM, 18000, 0x0e, 0x00, 36, 2 }, /*[ 4] 24 Mb */ { AH_TRUE, OFDM, 24000, 0x09, 0x00, (0x80|48), 4 }, /*[ 5] 36 Mb */ { AH_TRUE, OFDM, 36000, 0x0d, 0x00, 72, 4 }, /*[ 6] 48 Mb */ { AH_TRUE, OFDM, 48000, 0x08, 0x00, 96, 4 }, /*[ 7] 54 Mb */ { AH_TRUE, OFDM, 54000, 0x0c, 0x00, 108, 4 }, /*[ 8] 6.5 Mb */ { AH_TRUE, HT, 6500, 0x80, 0x00, 0, 0 }, /*[ 9] 13 Mb */ { AH_TRUE, HT, 13000, 0x81, 0x00, 1, 2 }, /*[10]19.5 Mb */ { AH_TRUE, HT, 19500, 0x82, 0x00, 2, 2 }, /*[11] 26 Mb */ { AH_TRUE, HT, 26000, 0x83, 0x00, 3, 4 }, /*[12] 39 Mb */ { AH_TRUE, HT, 39000, 0x84, 0x00, 4, 4 }, /*[13] 39 Mb */ { AH_TRUE, HT, 39000, 0x84, 0x00, 4, 4 }, /*[14] 52 Mb */ { AH_TRUE, HT, 52000, 0x85, 0x00, 5, 4 }, /*[15] 52 Mb */ { AH_TRUE, HT, 52000, 0x85, 0x00, 5, 4 }, /*[16]58.5 Mb */ { AH_TRUE, HT, 58500, 0x86, 0x00, 6, 4 }, /*[17]58.5 Mb */ { AH_TRUE, HT, 58500, 0x86, 0x00, 6, 4 }, /*[18] 65 Mb */ { AH_TRUE, HT, 65000, 0x87, 0x00, 7, 4 }, /*[19] 65 Mb */ { AH_TRUE, HT, 65000, 0x87, 0x00, 7, 4 }, /*[20] 52 Mb */ { AH_TRUE, HT, 52000, 0x8b, 0x00, 11, 4 }, /*[21] 78 Mb */ { AH_TRUE, HT, 78000, 0x8c, 0x00, 12, 4 }, /*[22] 78 Mb */ { AH_TRUE, HT, 78000, 0x8c, 0x00, 12, 4 }, /*[23] 104 Mb */ { AH_TRUE, HT, 104000, 0x8d, 0x00, 13, 4 }, /*[24] 104 Mb */ { AH_TRUE, HT, 104000, 0x8d, 0x00, 13, 4 }, /*[25] 117 Mb */ { AH_TRUE, HT, 117000, 0x8e, 0x00, 14, 4 }, /*[26] 117 Mb */ { AH_TRUE, HT, 117000, 0x8e, 0x00, 14, 4 }, /*[27] 130 Mb */ { AH_TRUE, HT, 130000, 0x8f, 0x00, 15, 4 }, }, }; #endif #undef OFDM #undef CCK #undef TURBO #undef XR #undef HT #undef HT_HGI const HAL_RATE_TABLE * ar5416GetRateTable(struct ath_hal *ah, a_uint32_t mode) { HAL_RATE_TABLE *rt; switch (mode) { case HAL_MODE_11NG: rt = &ar5416_11ng_table; break; #ifdef ATH_SUPPORT_A_MODE case HAL_MODE_11NA: rt = &ar5416_11na_table; break; #endif default: return AH_NULL; } return rt; } #endif open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/ar5416desc.h000077500000000000000000000417241321570333100264730ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _ATH_AR5416_DESC_H_ #define _ATH_AR5416_DESC_H_ #define ds_ctl8 u.tx.ctl8 #define ds_ctl9 u.tx.ctl9 #define ds_ctl10 u.tx.ctl10 #define ds_ctl11 u.tx.ctl11 struct ar5416_desc_20 { a_uint32_t ds_link; /* link pointer */ a_uint32_t ds_data; /* data buffer pointer */ a_uint32_t ds_ctl0; /* DMA control 0 */ a_uint32_t ds_ctl1; /* DMA control 1 */ union { struct { a_uint32_t ctl2; a_uint32_t ctl3; a_uint32_t ctl4; a_uint32_t ctl5; a_uint32_t ctl6; a_uint32_t ctl7; a_uint32_t ctl8; a_uint32_t ctl9; a_uint32_t ctl10; a_uint32_t ctl11; a_uint32_t status0; a_uint32_t status1; a_uint32_t status2; a_uint32_t status3; a_uint32_t status4; a_uint32_t status5; a_uint32_t status6; a_uint32_t status7; a_uint32_t status8; a_uint32_t status9; } tx; struct { /* rx desc has 2 control words + 9 status words */ a_uint32_t status0; a_uint32_t status1; a_uint32_t status2; a_uint32_t status3; a_uint32_t status4; a_uint32_t status5; a_uint32_t status6; a_uint32_t status7; a_uint32_t status8; } rx; } u; } adf_os_packed; #define AR5416DESC_20(_ds) ((struct ar5416_desc_20 *)(_ds)) #define AR5416DESC_CONST_20(_ds) ((const struct ar5416_desc_20 *)(_ds)) #define ds_ctl2 u.tx.ctl2 #define ds_ctl3 u.tx.ctl3 #define ds_ctl4 u.tx.ctl4 #define ds_ctl5 u.tx.ctl5 #define ds_ctl6 u.tx.ctl6 #define ds_ctl7 u.tx.ctl7 #define ds_txstatus0 u.tx.status0 #define ds_txstatus1 u.tx.status1 #define ds_txstatus2 u.tx.status2 #define ds_txstatus3 u.tx.status3 #define ds_txstatus4 u.tx.status4 #define ds_txstatus5 u.tx.status5 #define ds_txstatus6 u.tx.status6 #define ds_txstatus7 u.tx.status7 #define ds_txstatus8 u.tx.status8 #define ds_txstatus9 u.tx.status9 #define ds_rxstatus0 u.rx.status0 #define ds_rxstatus1 u.rx.status1 #define ds_rxstatus2 u.rx.status2 #define ds_rxstatus3 u.rx.status3 #define ds_rxstatus4 u.rx.status4 #define ds_rxstatus5 u.rx.status5 #define ds_rxstatus6 u.rx.status6 #define ds_rxstatus7 u.rx.status7 #define ds_rxstatus8 u.rx.status8 /*********** * TX Desc * ***********/ /* ds_ctl0 */ #define AR_FrameLen 0x00000fff #define AR_VirtMoreFrag 0x00001000 #define AR_TxCtlRsvd00 0x0000e000 #define AR_XmitPower 0x003f0000 #define AR_XmitPower_S 16 #define AR_RTSEnable 0x00400000 #define AR_VEOL 0x00800000 #define AR_ClrDestMask 0x01000000 #define AR_TxCtlRsvd01 0x1e000000 #define AR_TxIntrReq 0x20000000 #define AR_DestIdxValid 0x40000000 #define AR_CTSEnable 0x80000000 /* ds_ctl1 */ #define AR_BufLen 0x00000fff #define AR_TxMore 0x00001000 #define AR_DestIdx 0x000fe000 #define AR_DestIdx_S 13 #define AR_FrameType 0x00f00000 #define AR_FrameType_S 20 #define AR_NoAck 0x01000000 #define AR_InsertTS 0x02000000 #define AR_CorruptFCS 0x04000000 #define AR_ExtOnly 0x08000000 #define AR_ExtAndCtl 0x10000000 #define AR_MoreAggr 0x20000000 #define AR_IsAggr 0x40000000 #define AR_MoreRifs 0x80000000 /* ds_ctl2 */ #define AR_BurstDur 0x00007fff #define AR_BurstDur_S 0 #define AR_DurUpdateEn 0x00008000 #define AR_XmitDataTries0 0x000f0000 #define AR_XmitDataTries0_S 16 #define AR_XmitDataTries1 0x00f00000 #define AR_XmitDataTries1_S 20 #define AR_XmitDataTries2 0x0f000000 #define AR_XmitDataTries2_S 24 #define AR_XmitDataTries3 0xf0000000 #define AR_XmitDataTries3_S 28 /* ds_ctl3 */ #define AR_XmitRate0 0x000000ff #define AR_XmitRate0_S 0 #define AR_XmitRate1 0x0000ff00 #define AR_XmitRate1_S 8 #define AR_XmitRate2 0x00ff0000 #define AR_XmitRate2_S 16 #define AR_XmitRate3 0xff000000 #define AR_XmitRate3_S 24 /* ds_ctl4 */ #define AR_PacketDur0 0x00007fff #define AR_PacketDur0_S 0 #define AR_RTSCTSQual0 0x00008000 #define AR_PacketDur1 0x7fff0000 #define AR_PacketDur1_S 16 #define AR_RTSCTSQual1 0x80000000 /* ds_ctl5 */ #define AR_PacketDur2 0x00007fff #define AR_PacketDur2_S 0 #define AR_RTSCTSQual2 0x00008000 #define AR_PacketDur3 0x7fff0000 #define AR_PacketDur3_S 16 #define AR_RTSCTSQual3 0x80000000 /* ds_ctl6 */ #define AR_AggrLen 0x0000ffff #define AR_AggrLen_S 0 #define AR_TxCtlRsvd60 0x00030000 #define AR_PadDelim 0x03fc0000 #define AR_PadDelim_S 18 #define AR_EncrType 0x1c000000 #define AR_EncrType_S 26 #define AR_TxCtlRsvd61 0xf0000000 /* ds_ctl 7 */ #define AR_2040_0 0x00000001 #define AR_GI0 0x00000002 #define AR_ChainSel0 0x0000001c #define AR_ChainSel0_S 2 #define AR_2040_1 0x00000020 #define AR_GI1 0x00000040 #define AR_ChainSel1 0x00000380 #define AR_ChainSel1_S 7 #define AR_2040_2 0x00000400 #define AR_GI2 0x00000800 #define AR_ChainSel2 0x00007000 #define AR_ChainSel2_S 12 #define AR_2040_3 0x00008000 #define AR_GI3 0x00010000 #define AR_ChainSel3 0x000e0000 #define AR_ChainSel3_S 17 #define AR_RTSCTSRate 0x0ff00000 #define AR_RTSCTSRate_S 20 #define AR_TxCtlRsvd70 0xf0000000 #define AR_STBC0 0x10000000 #define AR_STBC1 0x20000000 #define AR_STBC2 0x40000000 #define AR_STBC3 0x80000000 #ifdef MAGPIE_MERLIN /* ds_ctl 8 */ #define AR_TxCtlRsvd80 0xffffffff /* ds_ctl 9 */ #define AR_TxCtlRsvd90 0x00ffffff #define AR_XmitPower1 0x3f000000 #define AR_XmitPower1_S 24 #define AR_TxCtlRsvd91 0xc0000000 /* ds_ctl 10 */ #define AR_TxCtlRsvd100 0x00ffffff #define AR_XmitPower2 0x3f000000 #define AR_XmitPower2_S 24 #define AR_TxCtlRsvd101 0xc0000000 /* ds_ctl 11 */ #define AR_TxCtlRsvd110 0x00ffffff #define AR_XmitPower3 0x3f000000 #define AR_XmitPower3_S 24 #define AR_TxCtlRsvd111 0xc0000000 #endif /************* * TX Status * *************/ /* ds_status0 */ #define AR_TxRSSIAnt00 0x000000ff #define AR_TxRSSIAnt00_S 0 #define AR_TxRSSIAnt01 0x0000ff00 #define AR_TxRSSIAnt01_S 8 #define AR_TxRSSIAnt02 0x00ff0000 #define AR_TxRSSIAnt02_S 16 #define AR_TxStatusRsvd00 0x3f000000 #define AR_TxBaStatus 0x40000000 #define AR_TxStatusRsvd01 0x80000000 /* ds_status1 */ #define AR_FrmXmitOK 0x00000001 #define AR_ExcessiveRetries 0x00000002 #define AR_FIFOUnderrun 0x00000004 #define AR_Filtered 0x00000008 #define AR_RTSFailCnt 0x000000f0 #define AR_RTSFailCnt_S 4 #define AR_DataFailCnt 0x00000f00 #define AR_DataFailCnt_S 8 #define AR_VirtRetryCnt 0x0000f000 #define AR_VirtRetryCnt_S 12 #define AR_TxDelimUnderrun 0x00010000 #define AR_TxDataUnderrun 0x00020000 #define AR_DescCfgErr 0x00040000 #define AR_TxTimerExpired 0x00080000 #define AR_TxStatusRsvd10 0xfff00000 /* ds_status2 */ #define AR_SendTimestamp ds_txstatus2 /* ds_status3 */ #define AR_BaBitmapLow ds_txstatus3 /* ds_status4 */ #define AR_BaBitmapHigh ds_txstatus4 /* ds_status5 */ #define AR_TxRSSIAnt10 0x000000ff #define AR_TxRSSIAnt10_S 0 #define AR_TxRSSIAnt11 0x0000ff00 #define AR_TxRSSIAnt11_S 8 #define AR_TxRSSIAnt12 0x00ff0000 #define AR_TxRSSIAnt12_S 16 #define AR_TxRSSICombined 0xff000000 #define AR_TxRSSICombined_S 24 /* ds_status6 */ #define AR_TxEVM0 ds_txstatus5 /* ds_status7 */ #define AR_TxEVM1 ds_txstatus6 /* ds_status8 */ #define AR_TxEVM2 ds_txstatus7 /* ds_status9 */ #define AR_TxDone 0x00000001 #define AR_SeqNum 0x00001ffe #define AR_SeqNum_S 1 #define AR_TxStatusRsvd80 0x0001e000 #define AR_TxOpExceeded 0x00020000 #define AR_TxStatusRsvd81 0x001c0000 #define AR_FinalTxIdx 0x00600000 #define AR_FinalTxIdx_S 21 #define AR_TxStatusRsvd82 0x01800000 #define AR_PowerMgmt 0x02000000 #define AR_TxStatusRsvd83 0xfc000000 /*********** * RX Desc * ***********/ /* ds_ctl0 */ #define AR_RxCTLRsvd00 0xffffffff /* ds_ctl1 */ #define AR_BufLen 0x00000fff #define AR_RxCtlRsvd00 0x00001000 #define AR_RxIntrReq 0x00002000 #define AR_RxCtlRsvd01 0xffffc000 /************* * Rx Status * *************/ /* ds_status0 */ #define AR_RxRSSIAnt00 0x000000ff #define AR_RxRSSIAnt00_S 0 #define AR_RxRSSIAnt01 0x0000ff00 #define AR_RxRSSIAnt01_S 8 #define AR_RxRSSIAnt02 0x00ff0000 #define AR_RxRSSIAnt02_S 16 #define AR_RxRate 0xff000000 #define AR_RxRate_S 24 #define AR_RxStatusRsvd00 0xff000000 /* ds_status1 */ #define AR_DataLen 0x00000fff #define AR_RxMore 0x00001000 #define AR_NumDelim 0x003fc000 #define AR_NumDelim_S 14 #define AR_RxStatusRsvd10 0xff800000 /* ds_status2 */ #define AR_RcvTimestamp ds_rxstatus2 /* ds_status3 */ #define AR_GI 0x00000001 #define AR_2040 0x00000002 #define AR_Parallel40 0x00000004 #define AR_Parallel40_S 2 #define AR_RxStatusRsvd30 0x000000f8 #define AR_RxAntenna 0xffffff00 #define AR_RxAntenna_S 8 /* ds_status4 */ #define AR_RxRSSIAnt10 0x000000ff #define AR_RxRSSIAnt10_S 0 #define AR_RxRSSIAnt11 0x0000ff00 #define AR_RxRSSIAnt11_S 8 #define AR_RxRSSIAnt12 0x00ff0000 #define AR_RxRSSIAnt12_S 16 #define AR_RxRSSICombined 0xff000000 #define AR_RxRSSICombined_S 24 /* ds_status5 */ #define AR_RxEVM0 ds_rxstatus4 /* ds_status6 */ #define AR_RxEVM1 ds_rxstatus5 /* ds_status7 */ #define AR_RxEVM2 ds_rxstatus6 /* ds_status8 */ #define AR_RxDone 0x00000001 #define AR_RxFrameOK 0x00000002 #define AR_CRCErr 0x00000004 #define AR_DecryptCRCErr 0x00000008 #define AR_PHYErr 0x00000010 #define AR_MichaelErr 0x00000020 #define AR_PreDelimCRCErr 0x00000040 #define AR_RxStatusRsvd70 0x00000080 #define AR_RxKeyIdxValid 0x00000100 #define AR_KeyIdx 0x0000fe00 #define AR_KeyIdx_S 9 #define AR_PHYErrCode 0x0000ff00 #define AR_PHYErrCode_S 8 #define AR_RxMoreAggr 0x00010000 #define AR_RxAggr 0x00020000 #define AR_PostDelimCRCErr 0x00040000 #define AR_RxStatusRsvd71 0x3ff80000 #define AR_DecryptBusyErr 0x40000000 #define AR_KeyMiss 0x80000000 #define RXSTATUS_RATE(ah, ads) (MS(ads->ds_rxstatus0, AR_RxRate)) #define VALID_TX_RATES \ ((1<<0x0b)|(1<<0x0f)|(1<<0x0a)|(1<<0x0e)|(1<<0x09)|(1<<0x0d)| \ (1<<0x08)|(1<<0x0c)|(1<<0x1b)|(1<<0x1a)|(1<<0x1e)|(1<<0x19)| \ (1<<0x1d)|(1<<0x18)|(1<<0x1c)) #define isValidTxRate(_r) ((1<<(_r)) & VALID_TX_RATES) #define set11nTries(_series, _index) \ (SM((_series)[_index].Tries, AR_XmitDataTries##_index)) #define set11nRate(_series, _index) \ (SM((_series)[_index].Rate, AR_XmitRate##_index)) #define set11nPktDurRTSCTS(_series, _index) \ (SM((_series)[_index].PktDuration, AR_PacketDur##_index) |\ ((_series)[_index].RateFlags & HAL_RATESERIES_RTS_CTS ?\ AR_RTSCTSQual##_index : 0)) #define set11nRateFlags(_series, _index) \ ((_series)[_index].RateFlags & HAL_RATESERIES_2040 ? AR_2040_##_index : 0) \ |((_series)[_index].RateFlags & HAL_RATESERIES_HALFGI ? AR_GI##_index : 0) \ |((_series)[_index].RateFlags & HAL_RATESERIES_STBC ? AR_STBC##_index : 0) \ |SM((_series)[_index].ChSel, AR_ChainSel##_index) #define set11nTxPower(_index, _txpower) \ SM(_txpower, AR_XmitPower##_index) extern HAL_BOOL ar5416UpdateTxTrigLevel(struct ath_hal *, HAL_BOOL IncTrigLevel); extern a_uint32_t ar5416GetTxDP(struct ath_hal *ah, a_uint32_t q); extern HAL_BOOL ar5416SetTxDP(struct ath_hal *ah, a_uint32_t q, a_uint32_t txdp); extern HAL_BOOL ar5416StartTxDma(struct ath_hal *ah, a_uint32_t q); extern a_uint32_t ar5416NumTxPending(struct ath_hal *ah, a_uint32_t q); extern HAL_BOOL ar5416StopTxDma(struct ath_hal *ah, a_uint32_t q); extern HAL_BOOL ar5416AbortTxDma(struct ath_hal *ah); extern void ar5416GetTxIntrQueue(struct ath_hal *ah, a_uint32_t *); extern HAL_BOOL ar5416SetGlobalTxTimeout(struct ath_hal *, a_uint32_t); extern a_uint32_t ar5416GetGlobalTxTimeout(struct ath_hal *); extern HAL_BOOL ar5416AbortTxDma(struct ath_hal *ah); extern a_uint32_t ar5416GetRxDP(struct ath_hal *ath); extern void ar5416SetRxDP(struct ath_hal *ah, a_uint32_t rxdp); extern void ar5416EnableReceive(struct ath_hal *ah); extern HAL_BOOL ar5416StopDmaReceive(struct ath_hal *ah); extern void ar5416StartPcuReceive(struct ath_hal *ah); extern void ar5416StopPcuReceive(struct ath_hal *ah); extern void ar5416AbortPcuReceive(struct ath_hal *ah); extern a_uint32_t ar5416GetRxFilter(struct ath_hal *ah); extern void ar5416SetRxFilter(struct ath_hal *ah, a_uint32_t bits); extern HAL_BOOL ar5416UpdateCTSForBursting_20(struct ath_hal *, struct ath_desc *, struct ath_desc *,struct ath_desc *, struct ath_desc *, a_uint32_t, a_uint32_t); extern HAL_BOOL ar5416SetupTxDesc_20(struct ath_tx_desc *ds, a_uint32_t pktLen, a_uint32_t hdrLen, HAL_PKT_TYPE type, a_uint32_t txPower, a_uint32_t txRate0, a_uint32_t txTries0, a_uint32_t keyIx, a_uint32_t flags, a_uint32_t rtsctsRate, a_uint32_t rtsctsDuration); extern HAL_BOOL ar5416FillTxDesc_20(struct ath_tx_desc *ds, a_uint32_t segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg, const struct ath_tx_desc *ds0); extern HAL_BOOL ar5416FillKeyTxDesc_20(struct ath_tx_desc *,HAL_KEY_TYPE); extern HAL_STATUS ar5416ProcTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *); extern void ar5416Set11nTxDesc_20(struct ath_tx_desc *ds, a_uint32_t pktLen, HAL_PKT_TYPE type, a_uint32_t txPower, a_uint32_t keyIx, HAL_KEY_TYPE keyType, a_uint32_t flags); extern void ar5416Set11nRateScenario_20(struct ath_tx_desc *ds, a_uint32_t durUpdateEn, a_uint32_t rtsctsRate, HAL_11N_RATE_SERIES series[], a_uint32_t nseries, a_uint32_t flags); extern void ar5416Set11nAggrFirst_20(struct ath_tx_desc *ds, a_uint32_t aggrLen, a_uint32_t numDelims); extern void ar5416Set11nAggrMiddle_20(struct ath_tx_desc *ds, a_uint32_t numDelims); extern void ar5416Set11nAggrLast_20(struct ath_tx_desc *ds); extern void ar5416Clr11nAggr_20(struct ath_tx_desc *ds); extern void ar5416Set11nBurstDuration_20(struct ath_tx_desc *ds, a_uint32_t burstDuration); extern void ar5416Set11nVirtualMoreFrag_20(struct ath_tx_desc *ds, a_uint32_t vmf); extern HAL_BOOL ar5416SetupRxDesc_20(struct ath_rx_desc *, a_uint32_t size, a_uint32_t flags); extern HAL_STATUS ar5416ProcRxDescFast_20(struct ath_hal *ah, struct ath_rx_desc *, a_uint32_t, struct ath_desc *, struct ath_rx_status *); #endif open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/ar5416reg.h000077500000000000000000002445271321570333100263400ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _DEV_ATH_AR5416REG_H #define _DEV_ATH_AR5416REG_H /* DMA Control and Interrupt Registers */ #define AR_CR 0x0008 // MAC Control Register - only write values of 1 have effect #define AR_CR_RXE 0x00000004 // Receive enable #define AR_CR_RXD 0x00000020 // Receive disable #define AR_CR_SWI 0x00000040 // One-shot software interrupt #define AR_RXDP 0x000C // MAC receive queue descriptor pointer #define AR_CFG 0x0014 // MAC configuration and status register #define AR_CFG_SWTD 0x00000001 // byteswap tx descriptor words #define AR_CFG_SWTB 0x00000002 // byteswap tx data buffer words #define AR_CFG_SWRD 0x00000004 // byteswap rx descriptor words #define AR_CFG_SWRB 0x00000008 // byteswap rx data buffer words #define AR_CFG_SWRG 0x00000010 // byteswap register access data words #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 // AP/adhoc indication (0-AP 1-Adhoc) #define AR_CFG_PHOK 0x00000100 // PHY OK status #define AR_CFG_CLK_GATE_DIS 0x00000400 // Clock gating disable #define AR_CFG_EEBS 0x00000200 // EEPROM busy #define AR_CFG_PCI_MASTER_REQ_Q_THRESH 0x00060000 // Mask of PCI core master request queue full threshold #define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 17 // Shift for PCI core master request queue full threshold #define AR_MIRT 0x0020 // Mac Interrupt rate threshold register #define AR_MIRT_VAL 0x0000ffff // in uS #define AR_MIRT_VAL_S 16 #define AR_IER 0x0024 // MAC Interrupt enable register #define AR_IER_ENABLE 0x00000001 // Global interrupt enable #define AR_IER_DISABLE 0x00000000 // Global interrupt disable #define AR_TIMT 0x0028 // Mac Tx Interrupt mitigation threshold #define AR_TIMT_LAST 0x0000ffff // Last packet threshold #define AR_TIMT_LAST_S 0 #define AR_TIMT_FIRST 0xffff0000 // First packet threshold #define AR_TIMT_FIRST_S 16 #define AR_RIMT 0x002C // Mac Rx Interrupt mitigation threshold #define AR_RIMT_LAST 0x0000ffff // Last packet threshold #define AR_RIMT_LAST_S 0 #define AR_RIMT_FIRST 0xffff0000 // First packet threshold #define AR_RIMT_FIRST_S 16 #define AR_DMASIZE_4B 0x00000000 // DMA size 4 bytes (TXCFG + RXCFG) #define AR_DMASIZE_8B 0x00000001 // DMA size 8 bytes #define AR_DMASIZE_16B 0x00000002 // DMA size 16 bytes #define AR_DMASIZE_32B 0x00000003 // DMA size 32 bytes #define AR_DMASIZE_64B 0x00000004 // DMA size 64 bytes #define AR_DMASIZE_128B 0x00000005 // DMA size 128 bytes #define AR_DMASIZE_256B 0x00000006 // DMA size 256 bytes #define AR_DMASIZE_512B 0x00000007 // DMA size 512 bytes #define AR_TXCFG 0x0030 // MAC tx DMA size config register #define AR_TXCFG_DMASZ_MASK 0x00000003 #define AR_TXCFG_DMASZ_4B 0 #define AR_TXCFG_DMASZ_8B 1 #define AR_TXCFG_DMASZ_16B 2 #define AR_TXCFG_DMASZ_32B 3 #define AR_TXCFG_DMASZ_64B 4 #define AR_TXCFG_DMASZ_128B 5 #define AR_TXCFG_DMASZ_256B 6 #define AR_TXCFG_DMASZ_512B 7 #define AR_FTRIG 0x000003F0 // Mask for Frame trigger level #define AR_FTRIG_S 4 // Shift for Frame trigger level #define AR_FTRIG_IMMED 0x00000000 // bytes in PCU TX FIFO before air #define AR_FTRIG_64B 0x00000010 // default #define AR_FTRIG_128B 0x00000020 #define AR_FTRIG_192B 0x00000030 #define AR_FTRIG_256B 0x00000040 // 5 bits total #define AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY 0x00000800 #define AR_RXCFG 0x0034 // MAC rx DMA size config register #define AR_RXCFG_CHIRP 0x00000008 // Only double chirps #define AR_RXCFG_ZLFDMA 0x00000010 // Enable DMA of zero-length frame #define AR_RXCFG_DMASZ_MASK 0x00000007 #define AR_RXCFG_DMASZ_4B 0 #define AR_RXCFG_DMASZ_8B 1 #define AR_RXCFG_DMASZ_16B 2 #define AR_RXCFG_DMASZ_32B 3 #define AR_RXCFG_DMASZ_64B 4 #define AR_RXCFG_DMASZ_128B 5 #define AR_RXCFG_DMASZ_256B 6 #define AR_RXCFG_DMASZ_512B 7 #define AR_MIBC 0x0040 // MAC MIB control register #define AR_MIBC_COW 0x00000001 // counter overflow warning #define AR_MIBC_FMC 0x00000002 // freeze MIB counters #define AR_MIBC_CMC 0x00000004 // clear MIB counters #define AR_MIBC_MCS 0x00000008 // MIB counter strobe increment all #define AR_TOPS 0x0044 // MAC timeout prescale count #define AR_TOPS_MASK 0x0000FFFF // Mask for timeout prescale #define AR_RXNPTO 0x0048 // MAC no frame received timeout #define AR_RXNPTO_MASK 0x000003FF // Mask for no frame received timeout #define AR_TXNPTO 0x004C // MAC no frame trasmitted timeout #define AR_TXNPTO_MASK 0x000003FF // Mask for no frame transmitted timeout #define AR_TXNPTO_QCU_MASK 0x000FFC00 // Mask indicating the set of QCUs // for which frame completions will cause // a reset of the no frame transmitted timeout #define AR_RPGTO 0x0050 // MAC receive frame gap timeout #define AR_RPGTO_MASK 0x000003FF // Mask for receive frame gap timeout #define AR_RPCNT 0x0054 // MAC receive frame count limit #define AR_RPCNT_MASK 0x0000001F // Mask for receive frame count limit #define AR_MACMISC 0x0058 // MAC miscellaneous control/status register #define AR_MACMISC_PCI_EXT_FORCE 0x00000010 //force msb to 10 to ahb #define AR_MACMISC_DMA_OBS 0x000001E0 // Mask for DMA observation bus mux select #define AR_MACMISC_DMA_OBS_S 5 // Shift for DMA observation bus mux select #define AR_MACMISC_MISC_OBS 0x00000E00 // Mask for MISC observation bus mux select #define AR_MACMISC_MISC_OBS_S 9 // Shift for MISC observation bus mux select #define AR_MACMISC_MISC_OBS_BUS_LSB 0x00007000 // Mask for MAC observation bus mux select (lsb) #define AR_MACMISC_MISC_OBS_BUS_LSB_S 12 // Shift for MAC observation bus mux select (lsb) #define AR_MACMISC_MISC_OBS_BUS_MSB 0x00038000 // Mask for MAC observation bus mux select (msb) #define AR_MACMISC_MISC_OBS_BUS_MSB_S 15 // Shift for MAC observation bus mux select (msb) #define AR_GTXTO 0x0064 // MAC global transmit timeout #define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) #define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) #define AR_GTXTO_TIMEOUT_LIMIT_S 16 // Shift for timeout limit #define AR_GTTM 0x0068 // MAC global transmit timeout mode #define AR_GTTM_USEC 0x00000001 // usec strobe #define AR_GTTM_IGNORE_IDLE 0x00000002 // ignore channel idle #define AR_GTTM_RESET_IDLE 0x00000004 // reset counter on channel idle low #define AR_GTTM_CST_USEC 0x00000008 // CST usec strobe #define AR_CST 0x006C // MAC carrier sense timeout #define AR_CST_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) #define AR_CST_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) #define AR_CST_TIMEOUT_LIMIT_S 16 // Shift for timeout limit #define AR_SREV_VERSION_HOWL 0x014 #define AR_SREV_5416_V20_OR_LATER(_ah) (AR_SREV_HOWL((_ah)) || AR_SREV_OWL_20_OR_LATER(_ah)) #define AR_SREV_5416_V22_OR_LATER(_ah) (AR_SREV_HOWL((_ah)) || AR_SREV_OWL_22_OR_LATER(_ah)) #ifdef AR5416_EMULATION /* XXX - AR5416 Emulation only * XXX - TODO - remove when emulation complete */ #define AR_EMU 0x0070 // MAC - special emulation only register #define AR_EMU_RATETHROT 0x00000001 // rate throttling (enabled = 1) #define AR_EMU_CTL 0x00000002 // ctl channel busy (busy = 1) #define AR_EMU_EXT 0x00000004 // ext channel busy (busy = 1) #define AR_EMU_HALF_RATE 0x00000080 // run at half-rate for encryption #define AR_EMU_VERSION 0xFFFFFF00 // Mask for version (read only) #define AR_EMU_VERSION_S 8 // Shift for timeout limit #endif //AR5416_EMULATION /* Interrupt Status Registers */ #define AR_ISR 0x0080 // MAC Primary interrupt status register #define AR_ISR_RXOK 0x00000001 // At least one frame received sans errors #define AR_ISR_RXDESC 0x00000002 // Receive interrupt request #define AR_ISR_RXERR 0x00000004 // Receive error interrupt #define AR_ISR_RXNOPKT 0x00000008 // No frame received within timeout clock #define AR_ISR_RXEOL 0x00000010 // Received descriptor empty interrupt #define AR_ISR_RXORN 0x00000020 // Receive FIFO overrun interrupt #define AR_ISR_TXOK 0x00000040 // Transmit okay interrupt #define AR_ISR_TXDESC 0x00000080 // Transmit interrupt request #define AR_ISR_TXERR 0x00000100 // Transmit error interrupt #define AR_ISR_TXNOPKT 0x00000200 // No frame transmitted interrupt #define AR_ISR_TXEOL 0x00000400 // Transmit descriptor empty interrupt #define AR_ISR_TXURN 0x00000800 // Transmit FIFO underrun interrupt #define AR_ISR_MIB 0x00001000 // MIB interrupt - see MIBC #define AR_ISR_SWI 0x00002000 // Software interrupt #define AR_ISR_RXPHY 0x00004000 // PHY receive error interrupt #define AR_ISR_RXKCM 0x00008000 // Key-cache miss interrupt #define AR_ISR_SWBA 0x00010000 // Software beacon alert interrupt #define AR_ISR_BRSSI 0x00020000 // Beacon threshold interrupt #define AR_ISR_BMISS 0x00040000 // Beacon missed interrupt #define AR_ISR_BNR 0x00100000 // Beacon not ready interrupt #define AR_ISR_RXCHIRP 0x00200000 // Phy received a 'chirp' #define AR_ISR_BCNMISC 0x00800000 // In venice 'or' of TIM CABEND DTIMSYNC BCNTO CABTO DTIM bits from ISR_S2 #define AR_ISR_TIM 0x00800000 // TIM interrupt #define AR_ISR_QCBROVF 0x02000000 // QCU CBR overflow interrupt #define AR_ISR_QCBRURN 0x04000000 // QCU CBR underrun interrupt #define AR_ISR_QTRIG 0x08000000 // QCU scheduling trigger interrupt #define AR_ISR_GENTMR 0x10000000 // OR of generic timer bits in ISR 5 #ifdef AR5416_INT_MITIGATION #define AR_ISR_TXMINTR 0x00080000 // Maximum interrupt transmit rate #define AR_ISR_RXMINTR 0x01000000 // Maximum interrupt receive rate #define AR_ISR_TXINTM 0x40000000 // Tx interrupt after mitigation #define AR_ISR_RXINTM 0x80000000 // Rx interrupt after mitigation #endif #define AR_ISR_S0 0x0084 // MAC Secondary interrupt status register 0 #define AR_ISR_S0_QCU_TXOK 0x000003FF // Mask for TXOK (QCU 0-9) #define AR_ISR_S0_QCU_TXOK_S 0 // Shift for TXOK (QCU 0-9) #define AR_ISR_S0_QCU_TXDESC 0x03FF0000 // Mask for TXDESC (QCU 0-9) #define AR_ISR_S0_QCU_TXDESC_S 16 // Shift for TXDESC (QCU 0-9) #define AR_ISR_S1 0x0088 // MAC Secondary interrupt status register 1 #define AR_ISR_S1_QCU_TXERR 0x000003FF // Mask for TXERR (QCU 0-9) #define AR_ISR_S1_QCU_TXERR_S 0 // Shift for TXERR (QCU 0-9) #define AR_ISR_S1_QCU_TXEOL 0x03FF0000 // Mask for TXEOL (QCU 0-9) #define AR_ISR_S1_QCU_TXEOL_S 16 // Shift for TXEOL (QCU 0-9) #define AR_ISR_S2 0x008c // MAC Secondary interrupt status register 2 #define AR_ISR_S2_QCU_TXURN 0x000003FF // Mask for TXURN (QCU 0-9) #define AR_ISR_S2_CST 0x00400000 // Carrier sense timeout #define AR_ISR_S2_GTT 0x00800000 // Global transmit timeout #define AR_ISR_S2_TIM 0x01000000 // TIM #define AR_ISR_S2_CABEND 0x02000000 // CABEND #define AR_ISR_S2_DTIMSYNC 0x04000000 // DTIMSYNC #define AR_ISR_S2_BCNTO 0x08000000 // BCNTO #define AR_ISR_S2_CABTO 0x10000000 // CABTO #define AR_ISR_S2_DTIM 0x20000000 // DTIM #define AR_ISR_S2_TSFOOR 0x40000000 // Rx TSF out of range #define AR_ISR_S2_TBTT_TIME 0x80000000 // TBTT-referenced timer #define AR_ISR_S3 0x0090 // MAC Secondary interrupt status register 3 #define AR_ISR_S3_QCU_QCBROVF 0x000003FF // Mask for QCBROVF (QCU 0-9) #define AR_ISR_S3_QCU_QCBRURN 0x03FF0000 // Mask for QCBRURN (QCU 0-9) #define AR_ISR_S4 0x0094 // MAC Secondary interrupt status register 4 #define AR_ISR_S4_QCU_QTRIG 0x000003FF // Mask for QTRIG (QCU 0-9) #define AR_ISR_S4_RESV0 0xFFFFFC00 // Reserved #define AR_ISR_S5 0x0098 // MAC Secondary interrupt status register 5 #define AR_ISR_S5_TIMER_TRIG 0x000000FF // Mask for timer trigger (0-7) #define AR_ISR_S5_TIMER_THRESH 0x0007FE00 // Mask for timer threshold(0-7) #define AR_ISR_S5_GENTIMER7 0x80 //Timer 7 does not have a dedicated function /* Interrupt Mask Registers */ #define AR_IMR 0x00a0 // MAC Primary interrupt mask register #define AR_IMR_RXOK 0x00000001 // At least one frame received sans errors #define AR_IMR_RXDESC 0x00000002 // Receive interrupt request #define AR_IMR_RXERR 0x00000004 // Receive error interrupt #define AR_IMR_RXNOPKT 0x00000008 // No frame received within timeout clock #define AR_IMR_RXEOL 0x00000010 // Received descriptor empty interrupt #define AR_IMR_RXORN 0x00000020 // Receive FIFO overrun interrupt #define AR_IMR_TXOK 0x00000040 // Transmit okay interrupt #define AR_IMR_TXDESC 0x00000080 // Transmit interrupt request #define AR_IMR_TXERR 0x00000100 // Transmit error interrupt #define AR_IMR_TXNOPKT 0x00000200 // No frame transmitted interrupt #define AR_IMR_TXEOL 0x00000400 // Transmit descriptor empty interrupt #define AR_IMR_TXURN 0x00000800 // Transmit FIFO underrun interrupt #define AR_IMR_MIB 0x00001000 // MIB interrupt - see MIBC #define AR_IMR_SWI 0x00002000 // Software interrupt #define AR_IMR_RXPHY 0x00004000 // PHY receive error interrupt #define AR_IMR_RXKCM 0x00008000 // Key-cache miss interrupt #define AR_IMR_SWBA 0x00010000 // Software beacon alert interrupt #define AR_IMR_BRSSI 0x00020000 // Beacon threshold interrupt #define AR_IMR_BMISS 0x00040000 // Beacon missed interrupt #define AR_IMR_BNR 0x00100000 // BNR interrupt #define AR_IMR_RXCHIRP 0x00200000 // RXCHIRP interrupt #define AR_IMR_BCNMISC 0x00800000 // Venice: BCNMISC #define AR_IMR_TIM 0x00800000 // TIM interrupt #define AR_IMR_QCBROVF 0x02000000 // QCU CBR overflow interrupt #define AR_IMR_QCBRURN 0x04000000 // QCU CBR underrun interrupt #define AR_IMR_QTRIG 0x08000000 // QCU scheduling trigger interrupt #define AR_IMR_GENTMR 0x10000000 // Generic timer interrupt #ifdef AR5416_INT_MITIGATION #define AR_IMR_TXMINTR 0x00080000 // Maximum interrupt transmit rate #define AR_IMR_RXMINTR 0x01000000 // Maximum interrupt receive rate #define AR_IMR_TXINTM 0x40000000 // Tx interrupt after mitigation #define AR_IMR_RXINTM 0x80000000 // Rx interrupt after mitigation #endif #define AR_IMR_S0 0x00a4 // MAC Secondary interrupt mask register 0 #define AR_IMR_S0_QCU_TXOK 0x000003FF // Mask for TXOK (QCU 0-9) #define AR_IMR_S0_QCU_TXOK_S 0 // Shift for TXOK (QCU 0-9) #define AR_IMR_S0_QCU_TXDESC 0x03FF0000 // Mask for TXDESC (QCU 0-9) #define AR_IMR_S0_QCU_TXDESC_S 16 // Shift for TXDESC (QCU 0-9) #define AR_IMR_S1 0x00a8 // MAC Secondary interrupt mask register 1 #define AR_IMR_S1_QCU_TXERR 0x000003FF // Mask for TXERR (QCU 0-9) #define AR_IMR_S1_QCU_TXERR_S 0 // Shift for TXERR (QCU 0-9) #define AR_IMR_S1_QCU_TXEOL 0x03FF0000 // Mask for TXEOL (QCU 0-9) #define AR_IMR_S1_QCU_TXEOL_S 16 // Shift for TXEOL (QCU 0-9) #define AR_IMR_S2 0x00ac // MAC Secondary interrupt mask register 2 #define AR_IMR_S2_QCU_TXURN 0x000003FF // Mask for TXURN (QCU 0-9) #define AR_IMR_S2_QCU_TXURN_S 0 // Shift for TXURN (QCU 0-9) #define AR_IMR_S2_CST 0x00400000 // Carrier sense timeout #define AR_IMR_S2_GTT 0x00800000 // Global transmit timeout #define AR_IMR_S2_TIM 0x01000000 // TIM #define AR_IMR_S2_CABEND 0x02000000 // CABEND #define AR_IMR_S2_DTIMSYNC 0x04000000 // DTIMSYNC #define AR_IMR_S2_BCNTO 0x08000000 // BCNTO #define AR_IMR_S2_CABTO 0x10000000 // CABTO #define AR_IMR_S2_DTIM 0x20000000 // DTIM #define AR_IMR_S2_TSFOOR 0x40000000 // TSF overrun #define AR_IMR_S3 0x00b0 // MAC Secondary interrupt mask register 3 #define AR_IMR_S3_QCU_QCBROVF 0x000003FF // Mask for QCBROVF (QCU 0-9) #define AR_IMR_S3_QCU_QCBRURN 0x03FF0000 // Mask for QCBRURN (QCU 0-9) #define AR_IMR_S3_QCU_QCBRURN_S 16 // Shift for QCBRURN (QCU 0-9) #define AR_IMR_S4 0x00b4 // MAC Secondary interrupt mask register 4 #define AR_IMR_S4_QCU_QTRIG 0x000003FF // Mask for QTRIG (QCU 0-9) #define AR_IMR_S4_RESV0 0xFFFFFC00 // Reserved #define AR_IMR_S5 0x00b8 // MAC Secondary interrupt mask register 5 #define AR_IMR_S5_TIMER_TRIG 0x000000FF // Mask for timer trigger (0-7) #define AR_IMR_S5_TIMER_THRESH 0x0000FF00 // Mask for timer threshold(0-7) #define AR_IMR_S5_GENTIMER7 0x80 //Timer 7 does not have a dedicated function /* Interrupt status registers (read-and-clear access secondary shadow copies) */ #define AR_ISR_RAC 0x00c0 // MAC Primary interrupt status register // read-and-clear access #define AR_ISR_S0_S 0x00c4 // MAC Secondary interrupt status register 0 /* Interrupt status registers (read-and-clear access secondary shadow copies) */ #define AR_ISR_RAC 0x00c0 // MAC Primary interrupt status register // read-and-clear access #define AR_ISR_S0_S 0x00c4 // MAC Secondary interrupt status register 0 // shadow copy #define AR_ISR_S0_QCU_TXOK 0x000003FF // Mask for TXOK (QCU 0-9) #define AR_ISR_S0_QCU_TXOK_S 0 // Shift for TXOK (QCU 0-9) #define AR_ISR_S0_QCU_TXDESC 0x03FF0000 // Mask for TXDESC (QCU 0-9) #define AR_ISR_S0_QCU_TXDESC_S 16 // Shift for TXDESC (QCU 0-9) #define AR_ISR_S1_S 0x00c8 // MAC Secondary interrupt status register 1 // shadow copy #define AR_ISR_S1_QCU_TXERR 0x000003FF // Mask for TXERR (QCU 0-9) #define AR_ISR_S1_QCU_TXERR_S 0 // Shift for TXERR (QCU 0-9) #define AR_ISR_S1_QCU_TXEOL 0x03FF0000 // Mask for TXEOL (QCU 0-9) #define AR_ISR_S1_QCU_TXEOL_S 16 // Shift for TXEOL (QCU 0-9) #define AR_ISR_S2_S 0x00cc // MAC Secondary interrupt status register 2 // shadow copy #define AR_ISR_S3_S 0x00d0 // MAC Secondary interrupt status register 3 // shadow copy #define AR_ISR_S4_S 0x00d4 // MAC Secondary interrupt status register 4 // shadow copy #define AR_ISR_S5_S 0x00d8 // MAC Secondary interrupt status register 5 // shadow copy #define AR_DMADBG_0 0x00e0 // MAC DMA Debug Registers #define AR_DMADBG_1 0x00e4 #define AR_DMADBG_2 0x00e8 #define AR_DMADBG_3 0x00ec #define AR_DMADBG_4 0x00f0 #define AR_DMADBG_5 0x00f4 #define AR_DMADBG_6 0x00f8 #define AR_DMADBG_7 0x00fc /* QCU registers */ #define AR_NUM_QCU 10 // Only use QCU 0-9 for forward QCU compatibility #define AR_QCU_0 0x0001 #define AR_QCU_1 0x0002 #define AR_QCU_2 0x0004 #define AR_QCU_3 0x0008 #define AR_QCU_4 0x0010 #define AR_QCU_5 0x0020 #define AR_QCU_6 0x0040 #define AR_QCU_7 0x0080 #define AR_QCU_8 0x0100 #define AR_QCU_9 0x0200 #define AR_Q0_TXDP 0x0800 // MAC Transmit Queue descriptor pointer #define AR_Q1_TXDP 0x0804 // MAC Transmit Queue descriptor pointer #define AR_Q2_TXDP 0x0808 // MAC Transmit Queue descriptor pointer #define AR_Q3_TXDP 0x080c // MAC Transmit Queue descriptor pointer #define AR_Q4_TXDP 0x0810 // MAC Transmit Queue descriptor pointer #define AR_Q5_TXDP 0x0814 // MAC Transmit Queue descriptor pointer #define AR_Q6_TXDP 0x0818 // MAC Transmit Queue descriptor pointer #define AR_Q7_TXDP 0x081c // MAC Transmit Queue descriptor pointer #define AR_Q8_TXDP 0x0820 // MAC Transmit Queue descriptor pointer #define AR_Q9_TXDP 0x0824 // MAC Transmit Queue descriptor pointer #define AR_QTXDP(_i) (AR_Q0_TXDP + ((_i)<<2)) #define AR_Q_TXE 0x0840 // MAC Transmit Queue enable #define AR_Q_TXE_M 0x000003FF // Mask for TXE (QCU 0-9) #define AR_Q_TXD 0x0880 // MAC Transmit Queue disable #define AR_Q_TXD_M 0x000003FF // Mask for TXD (QCU 0-9) #define AR_Q0_CBRCFG 0x08c0 // MAC CBR configuration #define AR_Q1_CBRCFG 0x08c4 // MAC CBR configuration #define AR_Q2_CBRCFG 0x08c8 // MAC CBR configuration #define AR_Q3_CBRCFG 0x08cc // MAC CBR configuration #define AR_Q4_CBRCFG 0x08d0 // MAC CBR configuration #define AR_Q5_CBRCFG 0x08d4 // MAC CBR configuration #define AR_Q6_CBRCFG 0x08d8 // MAC CBR configuration #define AR_Q7_CBRCFG 0x08dc // MAC CBR configuration #define AR_Q8_CBRCFG 0x08e0 // MAC CBR configuration #define AR_Q9_CBRCFG 0x08e4 // MAC CBR configuration #define AR_QCBRCFG(_i) (AR_Q0_CBRCFG + ((_i)<<2)) #define AR_Q_CBRCFG_INTERVAL 0x00FFFFFF // Mask for CBR interval (us) #define AR_Q_CBRCFG_INTERVAL_S 0 // Shift for CBR interval (us) #define AR_Q_CBRCFG_OVF_THRESH 0xFF000000 // Mask for CBR overflow threshold #define AR_Q_CBRCFG_OVF_THRESH_S 24 // Shift for CBR overflow threshold #define AR_Q0_RDYTIMECFG 0x0900 // MAC ReadyTime configuration #define AR_Q1_RDYTIMECFG 0x0904 // MAC ReadyTime configuration #define AR_Q2_RDYTIMECFG 0x0908 // MAC ReadyTime configuration #define AR_Q3_RDYTIMECFG 0x090c // MAC ReadyTime configuration #define AR_Q4_RDYTIMECFG 0x0910 // MAC ReadyTime configuration #define AR_Q5_RDYTIMECFG 0x0914 // MAC ReadyTime configuration #define AR_Q6_RDYTIMECFG 0x0918 // MAC ReadyTime configuration #define AR_Q7_RDYTIMECFG 0x091c // MAC ReadyTime configuration #define AR_Q8_RDYTIMECFG 0x0920 // MAC ReadyTime configuration #define AR_Q9_RDYTIMECFG 0x0924 // MAC ReadyTime configuration #define AR_QRDYTIMECFG(_i) (AR_Q0_RDYTIMECFG + ((_i)<<2)) #define AR_Q_RDYTIMECFG_DURATION 0x00FFFFFF // Mask for ReadyTime duration (us) #define AR_Q_RDYTIMECFG_DURATION_S 0 // Shift for ReadyTime duration (us) #define AR_Q_RDYTIMECFG_EN 0x01000000 // ReadyTime enable #define AR_Q_ONESHOTARM_SC 0x0940 // MAC OneShotArm set control #define AR_Q_ONESHOTARM_SC_M 0x000003FF // Mask for #define AR_Q_ONESHOTARM_SC (QCU 0-9) #define AR_Q_ONESHOTARM_SC_RESV0 0xFFFFFC00 // Reserved #define AR_Q_ONESHOTARM_CC 0x0980 // MAC OneShotArm clear control #define AR_Q_ONESHOTARM_CC_M 0x000003FF // Mask for #define AR_Q_ONESHOTARM_CC (QCU 0-9) #define AR_Q_ONESHOTARM_CC_RESV0 0xFFFFFC00 // Reserved #define AR_Q0_MISC 0x09c0 // MAC Miscellaneous QCU settings #define AR_Q1_MISC 0x09c4 // MAC Miscellaneous QCU settings #define AR_Q2_MISC 0x09c8 // MAC Miscellaneous QCU settings #define AR_Q3_MISC 0x09cc // MAC Miscellaneous QCU settings #define AR_Q4_MISC 0x09d0 // MAC Miscellaneous QCU settings #define AR_Q5_MISC 0x09d4 // MAC Miscellaneous QCU settings #define AR_Q6_MISC 0x09d8 // MAC Miscellaneous QCU settings #define AR_Q7_MISC 0x09dc // MAC Miscellaneous QCU settings #define AR_Q8_MISC 0x09e0 // MAC Miscellaneous QCU settings #define AR_Q9_MISC 0x09e4 // MAC Miscellaneous QCU settings #define AR_QMISC(_i) (AR_Q0_MISC + ((_i)<<2)) #define AR_Q_MISC_FSP 0x0000000F // Mask for Frame Scheduling Policy #define AR_Q_MISC_FSP_ASAP 0 // ASAP #define AR_Q_MISC_FSP_CBR 1 // CBR #define AR_Q_MISC_FSP_DBA_GATED 2 // DMA Beacon Alert gated #define AR_Q_MISC_FSP_TIM_GATED 3 // TIM gated #define AR_Q_MISC_FSP_BEACON_SENT_GATED 4 // Beacon-sent-gated #define AR_Q_MISC_FSP_BEACON_RCVD_GATED 5 // Beacon-received-gated #define AR_Q_MISC_ONE_SHOT_EN 0x00000010 // OneShot enable #define AR_Q_MISC_CBR_INCR_DIS1 0x00000020 // Disable CBR expired counter incr (empty q) #define AR_Q_MISC_CBR_INCR_DIS0 0x00000040 // Disable CBR expired counter incr (empty beacon q) #define AR_Q_MISC_BEACON_USE 0x00000080 // Beacon use indication #define AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN 0x00000100 // CBR expired counter limit enable #define AR_Q_MISC_RDYTIME_EXP_POLICY 0x00000200 // Enable TXE cleared on ReadyTime expired or VEOL #define AR_Q_MISC_RESET_CBR_EXP_CTR 0x00000400 // Reset CBR expired counter #define AR_Q_MISC_DCU_EARLY_TERM_REQ 0x00000800 // DCU frame early termination request control #define AR_Q_MISC_RESV0 0xFFFFF000 // Reserved #define AR_Q0_STS 0x0a00 // MAC Miscellaneous QCU status #define AR_Q1_STS 0x0a04 // MAC Miscellaneous QCU status #define AR_Q2_STS 0x0a08 // MAC Miscellaneous QCU status #define AR_Q3_STS 0x0a0c // MAC Miscellaneous QCU status #define AR_Q4_STS 0x0a10 // MAC Miscellaneous QCU status #define AR_Q5_STS 0x0a14 // MAC Miscellaneous QCU status #define AR_Q6_STS 0x0a18 // MAC Miscellaneous QCU status #define AR_Q7_STS 0x0a1c // MAC Miscellaneous QCU status #define AR_Q8_STS 0x0a20 // MAC Miscellaneous QCU status #define AR_Q9_STS 0x0a24 // MAC Miscellaneous QCU status #define AR_QSTS(_i) (AR_Q0_STS + ((_i)<<2)) #define AR_Q_STS_PEND_FR_CNT 0x00000003 // Mask for Pending Frame Count #define AR_Q_STS_RESV0 0x000000FC // Reserved #define AR_Q_STS_CBR_EXP_CNT 0x0000FF00 // Mask for CBR expired counter #define AR_Q_STS_RESV1 0xFFFF0000 // Reserved #define AR_Q_RDYTIMESHDN 0x0a40 // MAC ReadyTimeShutdown status #define AR_Q_RDYTIMESHDN_M 0x000003FF // Mask for ReadyTimeShutdown status (QCU 0-9) /* DCU registers */ #define AR_NUM_DCU 10 // Only use 10 DCU's for forward QCU/DCU compatibility #define AR_DCU_0 0x0001 #define AR_DCU_1 0x0002 #define AR_DCU_2 0x0004 #define AR_DCU_3 0x0008 #define AR_DCU_4 0x0010 #define AR_DCU_5 0x0020 #define AR_DCU_6 0x0040 #define AR_DCU_7 0x0080 #define AR_DCU_8 0x0100 #define AR_DCU_9 0x0200 #define AR_D0_QCUMASK 0x1000 // MAC QCU Mask #define AR_D1_QCUMASK 0x1004 // MAC QCU Mask #define AR_D2_QCUMASK 0x1008 // MAC QCU Mask #define AR_D3_QCUMASK 0x100c // MAC QCU Mask #define AR_D4_QCUMASK 0x1010 // MAC QCU Mask #define AR_D5_QCUMASK 0x1014 // MAC QCU Mask #define AR_D6_QCUMASK 0x1018 // MAC QCU Mask #define AR_D7_QCUMASK 0x101c // MAC QCU Mask #define AR_D8_QCUMASK 0x1020 // MAC QCU Mask #define AR_D9_QCUMASK 0x1024 // MAC QCU Mask #define AR_DQCUMASK(_i) (AR_D0_QCUMASK + ((_i)<<2)) #define AR_D_QCUMASK 0x000003FF // Mask for QCU Mask (QCU 0-9) #define AR_D_QCUMASK_RESV0 0xFFFFFC00 // Reserved #define AR_D_TXBLK_CMD 0x1038 /* DCU transmit filter cmd (w/only) */ #define AR_D_TXBLK_DATA(i) (AR_D_TXBLK_CMD+(i)) /* DCU transmit filter data */ #define AR_D0_LCL_IFS 0x1040 // MAC DCU-specific IFS settings #define AR_D1_LCL_IFS 0x1044 // MAC DCU-specific IFS settings #define AR_D2_LCL_IFS 0x1048 // MAC DCU-specific IFS settings #define AR_D3_LCL_IFS 0x104c // MAC DCU-specific IFS settings #define AR_D4_LCL_IFS 0x1050 // MAC DCU-specific IFS settings #define AR_D5_LCL_IFS 0x1054 // MAC DCU-specific IFS settings #define AR_D6_LCL_IFS 0x1058 // MAC DCU-specific IFS settings #define AR_D7_LCL_IFS 0x105c // MAC DCU-specific IFS settings #define AR_D8_LCL_IFS 0x1060 // MAC DCU-specific IFS settings #define AR_D9_LCL_IFS 0x1064 // MAC DCU-specific IFS settings #define AR_DLCL_IFS(_i) (AR_D0_LCL_IFS + ((_i)<<2)) #define AR_D_LCL_IFS_CWMIN 0x000003FF // Mask for CW_MIN #define AR_D_LCL_IFS_CWMIN_S 0 // Shift for CW_MIN #define AR_D_LCL_IFS_CWMAX 0x000FFC00 // Mask for CW_MAX #define AR_D_LCL_IFS_CWMAX_S 10 // Shift for CW_MAX #define AR_D_LCL_IFS_AIFS 0x0FF00000 // Mask for AIFS #define AR_D_LCL_IFS_AIFS_S 20 // Shift for AIFS /* * Note: even though this field is 8 bits wide the * maximum supported AIFS value is 0xfc. Setting the AIFS value * to 0xfd 0xfe or 0xff will not work correctly and will cause * the DCU to hang. */ #define AR_D_LCL_IFS_RESV0 0xF0000000 // Reserved #define AR_D0_RETRY_LIMIT 0x1080 // MAC Retry limits #define AR_D1_RETRY_LIMIT 0x1084 // MAC Retry limits #define AR_D2_RETRY_LIMIT 0x1088 // MAC Retry limits #define AR_D3_RETRY_LIMIT 0x108c // MAC Retry limits #define AR_D4_RETRY_LIMIT 0x1090 // MAC Retry limits #define AR_D5_RETRY_LIMIT 0x1094 // MAC Retry limits #define AR_D6_RETRY_LIMIT 0x1098 // MAC Retry limits #define AR_D7_RETRY_LIMIT 0x109c // MAC Retry limits #define AR_D8_RETRY_LIMIT 0x10a0 // MAC Retry limits #define AR_D9_RETRY_LIMIT 0x10a4 // MAC Retry limits #define AR_DRETRY_LIMIT(_i) (AR_D0_RETRY_LIMIT + ((_i)<<2)) #define AR_D_RETRY_LIMIT_FR_SH 0x0000000F // Mask for frame short retry limit #define AR_D_RETRY_LIMIT_FR_SH_S 0 // Shift for frame short retry limit #define AR_D_RETRY_LIMIT_STA_SH 0x00003F00 // Mask for station short retry limit #define AR_D_RETRY_LIMIT_STA_SH_S 8 // Shift for station short retry limit #define AR_D_RETRY_LIMIT_STA_LG 0x000FC000 // Mask for station short retry limit #define AR_D_RETRY_LIMIT_STA_LG_S 14 // Shift for station short retry limit #define AR_D_RETRY_LIMIT_RESV0 0xFFF00000 // Reserved #define AR_D0_CHNTIME 0x10c0 // MAC ChannelTime settings #define AR_D1_CHNTIME 0x10c4 // MAC ChannelTime settings #define AR_D2_CHNTIME 0x10c8 // MAC ChannelTime settings #define AR_D3_CHNTIME 0x10cc // MAC ChannelTime settings #define AR_D4_CHNTIME 0x10d0 // MAC ChannelTime settings #define AR_D5_CHNTIME 0x10d4 // MAC ChannelTime settings #define AR_D6_CHNTIME 0x10d8 // MAC ChannelTime settings #define AR_D7_CHNTIME 0x10dc // MAC ChannelTime settings #define AR_D8_CHNTIME 0x10e0 // MAC ChannelTime settings #define AR_D9_CHNTIME 0x10e4 // MAC ChannelTime settings #define AR_DCHNTIME(_i) (AR_D0_CHNTIME + ((_i)<<2)) #define AR_D_CHNTIME_DUR 0x000FFFFF // Mask for ChannelTime duration (us) #define AR_D_CHNTIME_DUR_S 0 // Shift for ChannelTime duration (us) #define AR_D_CHNTIME_EN 0x00100000 // ChannelTime enable #define AR_D_CHNTIME_RESV0 0xFFE00000 // Reserved #define AR_D0_MISC 0x1100 // MAC Miscellaneous DCU-specific settings #define AR_D1_MISC 0x1104 // MAC Miscellaneous DCU-specific settings #define AR_D2_MISC 0x1108 // MAC Miscellaneous DCU-specific settings #define AR_D3_MISC 0x110c // MAC Miscellaneous DCU-specific settings #define AR_D4_MISC 0x1110 // MAC Miscellaneous DCU-specific settings #define AR_D5_MISC 0x1114 // MAC Miscellaneous DCU-specific settings #define AR_D6_MISC 0x1118 // MAC Miscellaneous DCU-specific settings #define AR_D7_MISC 0x111c // MAC Miscellaneous DCU-specific settings #define AR_D8_MISC 0x1120 // MAC Miscellaneous DCU-specific settings #define AR_D9_MISC 0x1124 // MAC Miscellaneous DCU-specific settings #define AR_DMISC(_i) (AR_D0_MISC + ((_i)<<2)) #define AR_D_MISC_BKOFF_THRESH 0x0000003F // Mask for Backoff threshold setting #define AR_D_MISC_RETRY_CNT_RESET_EN 0x00000040 // End of tx series station RTS/data failure count reset policy #define AR_D_MISC_CW_RESET_EN 0x00000080 // End of tx series CW reset enable #define AR_D_MISC_FRAG_WAIT_EN 0x00000100 // Fragment Starvation Policy #define AR_D_MISC_FRAG_BKOFF_EN 0x00000200 // Backoff during a frag burst #define AR_D_MISC_CW_BKOFF_EN 0x00001000 // Use binary exponential CW backoff #define AR_D_MISC_VIR_COL_HANDLING 0x0000C000 // Mask for Virtual collision handling policy #define AR_D_MISC_VIR_COL_HANDLING_S 14 // Shift for Virtual collision handling policy #define AR_D_MISC_VIR_COL_HANDLING_DEFAULT 0 // Normal #define AR_D_MISC_VIR_COL_HANDLING_IGNORE 1 // Ignore #define AR_D_MISC_BEACON_USE 0x00010000 // Beacon use indication #define AR_D_MISC_ARB_LOCKOUT_CNTRL 0x00060000 // Mask for DCU arbiter lockout control #define AR_D_MISC_ARB_LOCKOUT_CNTRL_S 17 // Shift for DCU arbiter lockout control #define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0 // No lockout #define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 // Intra-frame #define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2 // Global #define AR_D_MISC_ARB_LOCKOUT_IGNORE 0x00080000 // DCU arbiter lockout ignore control #define AR_D_MISC_SEQ_NUM_INCR_DIS 0x00100000 // Sequence number increment disable #define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000 // Post-frame backoff disable #define AR_D_MISC_VIT_COL_CW_BKOFF_EN 0x00400000 // Virtual coll. handling policy #define AR_D_MISC_BLOWN_IFS_RETRY_EN 0x00800000 // Initiate Retry procedure on Blown IFS #define AR_D_MISC_RESV0 0xFF000000 // Reserved #define AR_D_SEQNUM 0x1140 // MAC Frame sequence number control/status #define AR_D_GBL_IFS_SIFS 0x1030 // MAC DCU-global IFS settings: SIFS duration #define AR_D_GBL_IFS_SIFS_M 0x0000FFFF // Mask for SIFS duration (core clocks) #define AR_D_GBL_IFS_SIFS_RESV0 0xFFFFFFFF // Reserved #define AR_D_TXBLK_BASE 0x1038 // MAC DCU-global transmit filter bits #define AR_D_TXBLK_WRITE_BITMASK 0x0000FFFF // Mask for bitmask #define AR_D_TXBLK_WRITE_BITMASK_S 0 // Shift for bitmask #define AR_D_TXBLK_WRITE_SLICE 0x000F0000 // Mask for slice #define AR_D_TXBLK_WRITE_SLICE_S 16 // Shift for slice #define AR_D_TXBLK_WRITE_DCU 0x00F00000 // Mask for DCU number #define AR_D_TXBLK_WRITE_DCU_S 20 // Shift for DCU number #define AR_D_TXBLK_WRITE_COMMAND 0x0F000000 // Mask for command #define AR_D_TXBLK_WRITE_COMMAND_S 24 // Shift for command #define AR_D_GBL_IFS_SLOT 0x1070 // MAC DCU-global IFS settings: slot duration #define AR_D_GBL_IFS_SLOT_M 0x0000FFFF // Mask for Slot duration (core clocks) #define AR_D_GBL_IFS_SLOT_RESV0 0xFFFF0000 // Reserved #define AR_D_GBL_IFS_EIFS 0x10b0 // MAC DCU-global IFS settings: EIFS duration #define AR_D_GBL_IFS_EIFS_M 0x0000FFFF // Mask for Slot duration (core clocks) #define AR_D_GBL_IFS_EIFS_RESV0 0xFFFF0000 // Reserved #define AR_D_GBL_IFS_MISC 0x10f0 // MAC DCU-global IFS settings: Miscellaneous #define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007 // Mask forLFSR slice select #define AR_D_GBL_IFS_MISC_TURBO_MODE 0x00000008 // Turbo mode indication #define AR_D_GBL_IFS_MISC_USEC_DURATION 0x000FFC00 // Mask for microsecond duration #define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY 0x00300000 // Mask for DCU arbiter delay #define AR_D_GBL_IFS_MISC_RANDOM_LFSR_SLICE_DIS 0x01000000 // Random LSFR slice disable #define AR_D_GBL_IFS_MISC_SLOT_XMIT_WIND_LEN 0x06000000 // Slot transmission window length mask #define AR_D_GBL_IFS_MISC_FORCE_XMIT_SLOT_BOUND 0x08000000 // Force transmission on slot boundaries #define AR_D_GBL_IFS_MISC_IGNORE_BACKOFF 0x10000000 // Ignore backoff #define AR_D_FPCTL 0x1230 // DCU frame prefetch settings #define AR_D_FPCTL_DCU 0x0000000F // Mask for DCU for which prefetch is enabled #define AR_D_FPCTL_DCU_S 0 // Shift for DCU for which prefetch is enabled #define AR_D_FPCTL_PREFETCH_EN 0x00000010 // Enable prefetch for normal (non-burst) operation #define AR_D_FPCTL_BURST_PREFETCH 0x00007FE0 // Mask for Burst frame prefetch per DCU #define AR_D_FPCTL_BURST_PREFETCH_S 5 // Shift for Burst frame prefetch per DCU #define AR_D_TXPSE 0x1270 // MAC DCU transmit pause control/status #define AR_D_TXPSE_CTRL 0x000003FF // Mask of DCUs to pause (DCUs 0-9) #define AR_D_TXPSE_RESV0 0x0000FC00 // Reserved #define AR_D_TXPSE_STATUS 0x00010000 // Transmit pause status #define AR_D_TXPSE_RESV1 0xFFFE0000 // Reserved #define AR_D_TXSLOTMASK 0x12f0 // MAC DCU transmission slot mask #define AR_D_TXSLOTMASK_NUM 0x0000000F // slot numbers #define AR_MAC_LED 0x1f04 /* LED control */ #define AR_MAC_SCLK_RATE_IND 0x00000003 /* sleep clock indication */ #define AR_MAC_SCLK_RATE_IND_S 0 #define AR_MAC_SCLK_32MHZ 0x00000000 /* Sleep clock rate */ #define AR_MAC_SCLK_4MHZ 0x00000001 /* Sleep clock rate */ #define AR_MAC_SCLK_1MHZ 0x00000002 /* Sleep clock rate */ #define AR_MAC_SCLK_32KHZ 0x00000003 /* Sleep clock rate */ #define AR_MAC_LED_BLINK_SLOW 0x00000008 /* LED slowest blink rate mode */ #define AR_MAC_LED_BLINK_THRESH_SEL 0x00000070 /* LED blink threshold select */ #define AR_MAC_LED_MODE_SEL 0x00000380 /* LED mode select */ #define AR_MAC_LED_MODE_SEL_S 7 #define AR_MAC_LED_MODE_PROP 0 /* Blink prop to filtered tx/rx */ #define AR_MAC_LED_MODE_RPROP 1 /* Blink prop to unfiltered tx/rx */ #define AR_MAC_LED_MODE_SPLIT 2 /* Blink power for tx/net for rx */ #define AR_MAC_LED_MODE_RAND 3 /* Blink randomly */ #define AR_MAC_LED_ASSOC_CTL 0x00000c00 #define AR_MAC_LED_ASSOC_NONE 0x00000000 /* STA is not associated or trying */ #define AR_MAC_LED_ASSOC_ACTIVE 0x00000400 /* STA is associated */ #define AR_MAC_LED_ASSOC_PENDING 0x00000800 /* STA is trying to associate */ #define AR_MAC_SLEEP 0x1ff0 #define AR_MAC_SLEEP_MAC_AWAKE 0x00000000 // mac is now awake #define AR_MAC_SLEEP_MAC_ASLEEP 0x00000001 // mac is now asleep // DMA & PCI Registers in PCI space (usable during sleep) #define AR_RC 0x4000 // Warm reset control register #define AR_RC_AHB 0x00000001 // ahb reset #define AR_RC_APB 0x00000002 // apb reset #define AR_WA 0x4004 // PCI express work-arounds #define AR_PM_STATE 0x4008 // power management state #define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000 //for wow #define AR_HOST_TIMEOUT 0x4018 // dma xfer timeout #define AR_HOST_APB_TIMEOUT 0x0000FFFF // apb bus timeout #define AR_HOST_LB_TIMEOUT 0xFFFF0000 // local bus timeout #define AR_EEPROM 0x401c // eeprom info #define AR_EEPROM_ABSENT 0x00000100 #define AR_EEPROM_CORRUPT 0x00000200 #define AR_EEPROM_PROT_MASK 0x03FFFC00 #define AR_EEPROM_PROT_MASK_S 10 // Protect Bits RP is read protect WP is write protect #define EEPROM_PROTECT_RP_0_31 0x0001 #define EEPROM_PROTECT_WP_0_31 0x0002 #define EEPROM_PROTECT_RP_32_63 0x0004 #define EEPROM_PROTECT_WP_32_63 0x0008 #define EEPROM_PROTECT_RP_64_127 0x0010 #define EEPROM_PROTECT_WP_64_127 0x0020 #define EEPROM_PROTECT_RP_128_191 0x0040 #define EEPROM_PROTECT_WP_128_191 0x0080 #define EEPROM_PROTECT_RP_192_255 0x0100 #define EEPROM_PROTECT_WP_192_255 0x0200 #define EEPROM_PROTECT_RP_256_511 0x0400 #define EEPROM_PROTECT_WP_256_511 0x0800 #define EEPROM_PROTECT_RP_512_1023 0x1000 #define EEPROM_PROTECT_WP_512_1023 0x2000 #define EEPROM_PROTECT_RP_1024_2047 0x4000 #define EEPROM_PROTECT_WP_1024_2047 0x8000 #ifdef AR9100 #define AR_SREV 0x0600 /*mac silicon rev (expanded from 8 bits to 16 bits for Sowl) */ #define AR_SREV_ID 0x00000FFF /* Mask to read SREV info */ #else #define AR_SREV 0x4020 // mac silicon rev #define AR_SREV_ID 0x000000FF /* Mask to read SREV info */ #endif #define AR_SREV_VERSION 0x000000F0 /* Mask for Chip version */ #define AR_SREV_VERSION_S 4 /* Mask to shift Major Rev Info */ #define AR_SREV_REVISION 0x00000007 /* Mask for Chip revision level */ /* Sowl extension to SREV. AR_SREV_ID must be 0xFF */ #define AR_SREV_ID2 0xFFFFFFFF /* Mask to read SREV info */ #define AR_SREV_VERSION2 0xFFFC0000 /* Mask for Chip version */ #define AR_SREV_VERSION2_S 18 /* Mask to shift Major Rev Info */ #define AR_SREV_TYPE2 0x0003F000 /* Mask for Chip type */ #define AR_SREV_TYPE2_S 12 /* Mask to shift Major Rev Info */ #define AR_SREV_TYPE2_CHAIN 0x00001000 /* chain mode (1 = 3 chains, 0 = 2 chains) */ #define AR_SREV_TYPE2_HOST_MODE 0x00002000 /* host mode (1 = PCI, 0 = PCIe) */ #define AR_SREV_REVISION2 0x00000F00 #define AR_SREV_REVISION2_S 8 #define AR_SREV_VERSION_OWL_PCI 0xD #define AR_SREV_VERSION_OWL_PCIE 0xC #define AR_SREV_REVISION_OWL_10 0 /* Owl 1.0 */ #define AR_SREV_REVISION_OWL_20 1 /* Owl 2.0/2.1 */ #define AR_SREV_REVISION_OWL_22 2 /* Owl 2.2 */ #ifdef AR9100 #define AR_SREV_VERSION_SOWL 0x43 #else #define AR_SREV_VERSION_SOWL 0x1F #endif #define AR_SREV_REVISION_SOWL_10 0 /* Sowl 1.0 */ #define AR_SREV_REVISION_SOWL_11 1 /* Sowl 1.1 */ #define AR_SREV_VERSION_MERLIN 0x2f /* Merlin Version,0x2F for fusion_merlin branch */ #define AR_SREV_REVISION_MERLIN_10 0 /* Merlin 1.0 */ #define AR_SREV_REVISION_MERLIN_20 1 /* Merlin 2.0 */ #define AR_SREV_REVISION_MERLIN_21 2 /* Merlin 2.1 */ #define AR_SREV_OWL_10(_ah) (((_ah)->ah_macVersion == AR_SREV_VERSION_OWL_PCI) || \ ((_ah)->ah_macVersion == AR_SREV_VERSION_OWL_PCIE)) #define AR_SREV_OWL_20_OR_LATER(_ah) ((AH_PRIVATE((_ah))->ah_macVersion >= AR_SREV_VERSION_SOWL) || \ (AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_OWL_20)) #define AR_SREV_OWL_22_OR_LATER(_ah) ((AH_PRIVATE((_ah))->ah_macVersion >= AR_SREV_VERSION_SOWL) || \ (AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_OWL_22)) #define AR_SREV_SOWL_10_OR_LATER(_ah) ((AH_PRIVATE((_ah))->ah_macVersion >= AR_SREV_VERSION_SOWL)) #define AR_SREV_MERLIN(_ah) ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_MERLIN)) #define AR_SREV_MERLIN_10_OR_LATER(_ah) ((AH_PRIVATE((_ah))->ah_macVersion >= AR_SREV_VERSION_MERLIN)) #define AR_SREV_MERLIN_20(_ah) ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_MERLIN) && \ (AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_MERLIN_20)) #define AR_SREV_MERLIN_20_OR_LATER(_ah) ((AH_PRIVATE((_ah))->ah_macVersion > AR_SREV_VERSION_MERLIN) || \ ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_MERLIN) && \ (AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_MERLIN_20))) #define AR_SREV_SOWL(_ah) ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_SOWL)) #define AR_SREV_SOWL_11(_ah) (AR_SREV_SOWL(_ah) && (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_SOWL_11)) #define AR_RADIO_SREV_MAJOR 0xf0 #define AR_RAD5133_SREV_MAJOR 0xc0 /* Fowl: 2+5G/3x3 */ #define AR_RAD2133_SREV_MAJOR 0xd0 /* Fowl: 2G/3x3 */ #define AR_RAD5122_SREV_MAJOR 0xe0 /* Fowl: 5G/2x2 */ #define AR_RAD2122_SREV_MAJOR 0xf0 /* Fowl: 2+5G/2x2 */ #define AR_AHB_MODE 0x4024 // ahb mode for dma #define AR_AHB_EXACT_WR_EN 0x00000000 // write exact bytes #define AR_AHB_BUF_WR_EN 0x00000001 // buffer write upto cacheline #define AR_AHB_EXACT_RD_EN 0x00000000 // read exact bytes #define AR_AHB_CACHELINE_RD_EN 0x00000002 // read upto end of cacheline #define AR_AHB_PREFETCH_RD_EN 0x00000004 // prefetch upto page boundary #define AR_AHB_PAGE_SIZE_1K 0x00000000 // set page-size as 1k #define AR_AHB_PAGE_SIZE_2K 0x00000008 // set page-size as 2k #define AR_AHB_PAGE_SIZE_4K 0x00000010 // set page-size as 4k #define AR_INTR_RTC_IRQ 0x00000001 // rtc in shutdown state #define AR_INTR_MAC_IRQ 0x00000002 // pending mac interrupt #define AR_INTR_EEP_PROT_ACCESS 0x00000004 // eeprom protected area access #define AR_INTR_MAC_AWAKE 0x00020000 // mac is awake #define AR_INTR_MAC_ASLEEP 0x00040000 // mac is asleep /* TODO: fill in other values */ #define AR_INTR_GPIO 0x3FF00000 // gpio interrupted #define AR_INTR_GPIO_S 20 #define AR_INTR_SYNC_CAUSE_CLR 0x4028 // clear interrupt #define AR_INTR_SYNC_CAUSE 0x4028 // check pending interrupts #define AR_INTR_SYNC_ENABLE 0x402c // enable interrupts #define AR_INTR_ASYNC_MASK 0x4030 // asynchronous interrupt mask #define AR_INTR_SYNC_MASK 0x4034 // synchronous interrupt mask #define AR_INTR_ASYNC_CAUSE 0x4038 // check pending interrupts #define AR_INTR_ASYNC_ENABLE 0x403c // enable interrupts /* * synchronous interrupt signals */ enum { AR_INTR_SYNC_RTC_IRQ = 0x00000001, AR_INTR_SYNC_MAC_IRQ = 0x00000002, AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS = 0x00000004, AR_INTR_SYNC_APB_TIMEOUT = 0x00000008, AR_INTR_SYNC_PCI_MODE_CONFLICT = 0x00000010, AR_INTR_SYNC_HOST1_FATAL = 0x00000020, AR_INTR_SYNC_HOST1_PERR = 0x00000040, AR_INTR_SYNC_TRCV_FIFO_PERR = 0x00000080, AR_INTR_SYNC_RADM_CPL_EP = 0x00000100, AR_INTR_SYNC_RADM_CPL_DLLP_ABORT = 0x00000200, AR_INTR_SYNC_RADM_CPL_DLP_ABORT = 0x00000400, AR_INTR_SYNC_RADM_CPL_ECRC_ERR = 0x00000800, AR_INTR_SYNC_RADM_CPL_TIMEOUT = 0x00001000, AR_INTR_SYNC_LOCAL_TIMEOUT = 0x00002000, AR_INTR_SYNC_PM_ACCESS = 0x00004000, AR_INTR_SYNC_MAC_AWAKE = 0x00008000, AR_INTR_SYNC_MAC_ASLEEP = 0x00010000, AR_INTR_SYNC_MAC_SLEEP_ACCESS = 0x00020000, AR_INTR_SYNC_ALL = 0x0003FFFF, }; #define AR_NUM_GPIO 10 // Ten numbered 0 to 9. #ifdef MAGPIE_MERLIN #define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000 // enable interrupts: bits 18..31 #define AR_INTR_ASYNC_ENABLE_GPIO_S 18 // enable interrupts: bits 18..31 /* PCIe defines */ #define AR_PCIE_SERDES 0x4040 #define AR_PCIE_SERDES2 0x4044 #define AR_PCIE_PM_CTRL 0x4014 #define AR_PCIE_PM_CTRL_ENA 0x00080000 #define AR928X_NUM_GPIO 10 // Ten numbered 0 to 9 for Merlin. #define AR_GPIO_IN_OUT 0x4048 // GPIO input / output register #define AR_GPIO_IN_VAL 0x0FFFC000 #define AR_GPIO_IN_VAL_S 14 #define AR928X_GPIO_IN_VAL 0x000FFC00 // added for Merlin #define AR928X_GPIO_IN_VAL_S 10 // added for Merlin /* Added for Merlin */ #define AR_GPIO_OE_OUT 0x404c // GPIO output register #define AR_GPIO_OE_OUT_DRV 0x3 // 2 bit field mask, shifted by 2*bitpos #define AR_GPIO_OE_OUT_DRV_NO 0x0 // tristate #define AR_GPIO_OE_OUT_DRV_LOW 0x1 // drive if low #define AR_GPIO_OE_OUT_DRV_HI 0x2 // drive if high #define AR_GPIO_OE_OUT_DRV_ALL 0x3 // drive always /* 4050-405C added for Merlin */ #define AR_GPIO_INTR_POL 0x4050 // GPIO interrup polarity: 0 == high level, 1 == lo level #define AR_GPIO_INTR_POL_VAL 0x00001FFF // bits 13:0 correspond to gpio 13:0 #define AR_GPIO_INTR_POL_VAL_S 0 // bits 13:0 correspond to gpio 13:0 #define AR_GPIO_INPUT_EN_VAL 0x4054 // GPIO input enable and value #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080 // default value for rfsilent_bb_l #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S 7 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000 // 0 == set rfsilent_bb_l to default, 1 == connect rfsilent_bb_l to baseband #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S 15 #define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000 #define AR_GPIO_JTAG_DISABLE 0x00020000 // 1 == disable JTAG #define AR_GPIO_INPUT_MUX1 0x4058 #define AR_GPIO_INPUT_MUX2 0x405c #define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f // bits 0..3: input mux for clk25 input #define AR_GPIO_INPUT_MUX2_CLK25_S 0 // bits 0..3: input mux for clk25 input #define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f0 // bits 4..7: input mux for rfsilent_bb_l input #define AR_GPIO_INPUT_MUX2_RFSILENT_S 4 // bits 4..7: input mux for rfsilent_bb_l input #define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f00 // bits 8..11: input mux for RTC Reset input #define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8 // bits 8..11: input mux for RTC Reset input #define AR_GPIO_OUTPUT_MUX1 0x4060 /* 4064-4068 added for Merlin */ #define AR_GPIO_OUTPUT_MUX2 0x4064 #define AR_GPIO_OUTPUT_MUX3 0x4068 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 #define AR_INPUT_STATE 0x406c #define AR_GPIO_PDPU 0x4088 /* 4094 added for Merlin */ #define AR_PCIE_MSI 0x4094 #define AR_PCIE_MSI_ENABLE 0x00000001 // RTC register #define AR_RTC_RESET_EN 0x00000001 /* Reset RTC bit */ // AR9280: rf long shift registers #define AR_AN_RF2G1_CH0 0x7810 #define AR_AN_RF2G1_CH0_OB 0x03800000 #define AR_AN_RF2G1_CH0_OB_S 23 #define AR_AN_RF2G1_CH0_DB 0x1C000000 #define AR_AN_RF2G1_CH0_DB_S 26 #define AR_AN_RF5G1_CH0 0x7818 #define AR_AN_RF5G1_CH0_OB5 0x00070000 #define AR_AN_RF5G1_CH0_OB5_S 16 #define AR_AN_RF5G1_CH0_DB5 0x00380000 #define AR_AN_RF5G1_CH0_DB5_S 19 #define AR_AN_RF2G1_CH1 0x7834 #define AR_AN_RF2G1_CH1_OB 0x03800000 #define AR_AN_RF2G1_CH1_OB_S 23 #define AR_AN_RF2G1_CH1_DB 0x1C000000 #define AR_AN_RF2G1_CH1_DB_S 26 #define AR_AN_RF5G1_CH1 0x783C #define AR_AN_RF5G1_CH1_OB5 0x00070000 #define AR_AN_RF5G1_CH1_OB5_S 16 #define AR_AN_RF5G1_CH1_DB5 0x00380000 #define AR_AN_RF5G1_CH1_DB5_S 19 #define AR_AN_TOP2 0x7894 #define AR_AN_TOP2_XPABIAS_LVL 0xC0000000 #define AR_AN_TOP2_XPABIAS_LVL_S 30 #define AR_AN_TOP2_LOCALBIAS 0x00200000 #define AR_AN_TOP2_LOCALBIAS_S 21 #define AR_AN_TOP2_PWDCLKIND 0x00400000 #define AR_AN_TOP2_PWDCLKIND_S 22 #define AR_AN_SYNTH9 0x7868 #define AR_AN_SYNTH9_REFDIVA 0xf8000000 #define AR_AN_SYNTH9_REFDIVA_S 27 #endif // MAGPIE_MERLIN #define AR_GPIO_IN 0x4048 // GPIO input register #define AR_GPIO_INTR_OUT 0x404c // GPIO output register #define AR_GPIO_OUT_CTRL 0x000003FF // 0 = out, 1 = in #define AR_GPIO_OUT_VAL 0x000FFC00 #define AR_GPIO_OUT_VAL_S 10 #define AR_GPIO_INTR_CTRL 0x3FF00000 #define AR_GPIO_INTR_CTRL_S 20 #define AR_GPIO_OUTPUT_MUX1 0x4060 #define AR_EEPROM_STATUS_DATA 0x407c #define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff #define AR_EEPROM_STATUS_DATA_VAL_S 0 #define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 #define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000 #define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 #define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 #define AR_OBS 0x4080 // RTC registers /* Sowl */ #define AR_RTC_SOWL_PLL_DIV 0x000003ff #define AR_RTC_SOWL_PLL_DIV_S 0 #define AR_RTC_SOWL_PLL_REFDIV 0x00003C00 #define AR_RTC_SOWL_PLL_REFDIV_S 10 #define AR_RTC_SOWL_PLL_CLKSEL 0x0000C000 #define AR_RTC_SOWL_PLL_CLKSEL_S 14 #ifndef AR9100 #define AR_RTC_RC 0x7000 /* reset control */ #define AR_RTC_RC_M 0x00000003 #define AR_RTC_RC_MAC_WARM 0x00000001 #define AR_RTC_RC_MAC_COLD 0x00000002 #define AR_RTC_PLL_CONTROL 0x7014 /* Owl */ #define AR_RTC_PLL_DIV 0x0000001f #define AR_RTC_PLL_DIV_S 0 #define AR_RTC_PLL_DIV2 0x00000020 #define AR_RTC_PLL_REFDIV_5 0x000000c0 #define AR_RTC_PLL_CLKSEL_S 8 #define AR_RTC_PLL_CLKSEL 0x00000300 #define AR_RTC_RESET 0x7040 /* reset RTC */ #define AR_RTC_STATUS 0x7044 /* system sleep status */ #define AR_RTC_STATUS_M 0x0000000f #define AR_RTC_STATUS_SHUTDOWN 0x00000001 #define AR_RTC_STATUS_ON 0x00000002 #define AR_RTC_STATUS_SLEEP 0x00000004 #define AR_RTC_STATUS_WAKEUP 0x00000008 #define AR_RTC_SLEEP_CLK 0x7048 #define AR_RTC_FORCE_DERIVED_CLK 0x2 #define AR_RTC_FORCE_WAKE 0x704c /* control MAC force wake */ #define AR_RTC_FORCE_WAKE_EN 0x00000001 /* enable force wake */ #define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 /* auto-wake on MAC interrupt */ #define AR_RTC_INTR_CAUSE 0x7050 /* RTC interrupt cause/clear */ #define AR_RTC_INTR_ENABLE 0x7054 /* RTC interrupt enable */ #define AR_RTC_INTR_MASK 0x7058 /* RTC interrupt mask */ #else #define AR_SEQ_MASK 0x8060 /* MAC AES mute mask */ #define AR_RTC_BASE 0x00020000 #define AR_RTC_RC (AR_RTC_BASE + 0x0000) /* reset control */ #define AR_RTC_RC_M 0x00000003 #define AR_RTC_RC_MAC_WARM 0x00000001 #define AR_RTC_RC_MAC_COLD 0x00000002 #define AR_RTC_RC_COLD_RESET 0x00000004 #define AR_RTC_RC_WARM_RESET 0x00000008 #define AR_RTC_PLL_CONTROL (AR_RTC_BASE + 0x0014) #define AR_RTC_PLL_DIV 0x0000001f #define AR_RTC_PLL_DIV_S 0 #define AR_RTC_PLL_DIV2 0x00000020 #define AR_RTC_PLL_REFDIV_5 0x000000c0 #define AR_RTC_PLL_CLKSEL_S 8 #define AR_RTC_PLL_CLKSEL 0x00000300 #define AR_RTC_RESET (AR_RTC_BASE + 0x0040) /* reset RTC */ #define AR_RTC_RESET_EN 0x00000001 /* Reset RTC bit */ #define AR_RTC_STATUS (AR_RTC_BASE + 0x0044) /* system sleep status */ #define AR_RTC_PM_STATUS_M 0x0000000f /* Pwr Mgmt Status is the last 4 bits */ #define AR_RTC_STATUS_M 0x0000003f /* RTC Status is the last 6 bits */ #define AR_RTC_STATUS_SHUTDOWN 0x00000001 #define AR_RTC_STATUS_ON 0x00000002 #define AR_RTC_STATUS_SLEEP 0x00000004 #define AR_RTC_STATUS_WAKEUP 0x00000008 #define AR_RTC_SLEEP_CLK (AR_RTC_BASE + 0x0048) #define AR_RTC_FORCE_DERIVED_CLK 0x2 #define AR_RTC_FORCE_WAKE (AR_RTC_BASE + 0x004c) /* control MAC force wake */ #define AR_RTC_FORCE_WAKE_EN 0x00000001 /* enable force wake */ #define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 /* auto-wake on MAC interrupt */ #define AR_RTC_INTR_CAUSE (AR_RTC_BASE + 0x0050) /* RTC interrupt cause/clear */ #define AR_RTC_INTR_ENABLE (AR_RTC_BASE + 0x0054) /* RTC interrupt enable */ #define AR_RTC_INTR_MASK (AR_RTC_BASE + 0x0058) /* RTC interrupt mask */ #endif //HOWL // MAC PCU Registers #define AR_STA_ID0 0x8000 // MAC station ID0 - low 32 bits #define AR_STA_ID1 0x8004 // MAC station ID1 - upper 16 bits #define AR_STA_ID1_SADH_MASK 0x0000FFFF // Mask for 16 msb of MAC addr #define AR_STA_ID1_STA_AP 0x00010000 // Device is AP #define AR_STA_ID1_ADHOC 0x00020000 // Device is ad-hoc #define AR_STA_ID1_PWR_SAV 0x00040000 // Power save in generated frames #define AR_STA_ID1_KSRCHDIS 0x00080000 // Key search disable #define AR_STA_ID1_PCF 0x00100000 // Observe PCF #define AR_STA_ID1_USE_DEFANT 0x00200000 // Use default antenna #define AR_STA_ID1_DEFANT_UPDATE 0x00400000 // Update default ant w/TX antenna #define AR_STA_ID1_RTS_USE_DEF 0x00800000 // Use default antenna to send RTS #define AR_STA_ID1_ACKCTS_6MB 0x01000000 // Use 6Mb/s rate for ACK & CTS #define AR_STA_ID1_BASE_RATE_11B 0x02000000 // Use 11b base rate for ACK & CTS #define AR_STA_ID1_SECTOR_SELF_GEN 0x04000000 // default ant for generated frames #define AR_STA_ID1_CRPT_MIC_ENABLE 0x08000000 // Enable Michael #define AR_STA_ID1_KSRCH_MODE 0x10000000 // Look-up unique key when !keyID #define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 // Don't replace seq num #define AR_STA_ID1_CBCIV_ENDIAN 0x40000000 // IV endian-ness in CBC nonce #define AR_STA_ID1_MCAST_KSRCH 0x80000000 // Adhoc key search enable #define AR_BSS_ID0 0x8008 // MAC BSSID low 32 bits #define AR_BSS_ID1 0x800C // MAC BSSID upper 16 bits / AID #define AR_BSS_ID1_U16 0x0000FFFF // Mask for upper 16 bits of BSSID #define AR_BSS_ID1_AID 0x07FF0000 // Mask for association ID #define AR_BSS_ID1_AID_S 16 // Shift for association ID #define AR_BCN_RSSI_AVE 0x8010 // MAC Beacon average RSSI #define AR_BCN_RSSI_AVE_MASK 0x00000FFF // Beacon RSSI mask #define AR_TIME_OUT 0x8014 // MAC ACK & CTS time-out #define AR_TIME_OUT_ACK 0x00003FFF // Mask for ACK time-out #define AR_TIME_OUT_ACK_S 0 #define AR_TIME_OUT_CTS 0x3FFF0000 // Mask for CTS time-out #define AR_TIME_OUT_CTS_S 16 #define AR_RSSI_THR 0x8018 // beacon RSSI warning / bmiss threshold #define AR_RSSI_THR_MASK 0x000000FF // Beacon RSSI warning threshold #define AR_RSSI_THR_BM_THR 0x0000FF00 // Mask for Missed beacon threshold #define AR_RSSI_THR_BM_THR_S 8 // Shift for Missed beacon threshold #define AR_RSSI_BCN_WEIGHT 0x1F000000 // RSSI average weight #define AR_RSSI_BCN_WEIGHT_S 24 #define AR_RSSI_BCN_RSSI_RST 0x20000000 // Reset RSSI value #define AR_USEC 0x801c // MAC transmit latency register #define AR_USEC_USEC 0x0000007F // Mask for clock cycles in 1 usec #define AR_USEC_TX_LAT 0x007FC000 // tx latency to start of SIGNAL (usec) #define AR_USEC_TX_LAT_S 14 // tx latency to start of SIGNAL (usec) #define AR_USEC_RX_LAT 0x1F800000 // rx latency to start of SIGNAL (usec) #define AR_USEC_RX_LAT_S 23 // rx latency to start of SIGNAL (usec) #define AR_RESET_TSF 0x8020 #define AR_RESET_TSF_ONCE 0x01000000 // reset tsf once ; self-clears bit #define AR_MAX_CFP_DUR 0x8038 // MAC maximum CFP duration #define AR_CFP_VAL 0x0000FFFF // CFP value in uS #define AR_RX_FILTER 0x803C // MAC receive filter register #define AR_RX_FILTER_ALL 0x00000000 // Disallow all frames #define AR_RX_UCAST 0x00000001 // Allow unicast frames #define AR_RX_MCAST 0x00000002 // Allow multicast frames #define AR_RX_BCAST 0x00000004 // Allow broadcast frames #define AR_RX_CONTROL 0x00000008 // Allow control frames #define AR_RX_BEACON 0x00000010 // Allow beacon frames #define AR_RX_PROM 0x00000020 // Promiscuous mode all packets #define AR_RX_PROBE_REQ 0x00000080 // Any probe request frameA #define AR_RX_MY_BEACON 0x00000200 // Any beacon frame with matching BSSID #define AR_RX_COMPR_BAR 0x00000400 // Compressed directed block ack request #define AR_RX_COMPR_BA 0x00000800 // Compressed directed block ack #define AR_RX_UNCOM_BA_BAR 0x00001000 // Uncompressed directed BA or BAR #if 0 #define AR_RX_XR_POLL 0x00000040 // Allow XR Poll frames #endif #define AR_RX_PROBE_REQ 0x00000080 // Allow probe request frames #define AR_RX_MY_BEACON 0x00000200 // Allow beacons with matching BSSID #define AR_MCAST_FIL0 0x8040 // MAC multicast filter lower 32 bits #define AR_MCAST_FIL1 0x8044 // MAC multicast filter upper 32 bits #define AR_DIAG_SW 0x8048 // MAC PCU control register #define AR_DIAG_CACHE_ACK 0x00000001 // disable ACK when no valid key #define AR_DIAG_ACK_DIS 0x00000002 // disable ACK generation #define AR_DIAG_CTS_DIS 0x00000004 // disable CTS generation #define AR_DIAG_ENCRYPT_DIS 0x00000008 // disable encryption #define AR_DIAG_DECRYPT_DIS 0x00000010 // disable decryption #define AR_DIAG_RX_DIS 0x00000020 // disable receive #define AR_DIAG_LOOP_BACK 0x00000040 // enable loopback #define AR_DIAG_CORR_FCS 0x00000080 // corrupt FCS #define AR_DIAG_CHAN_INFO 0x00000100 // dump channel info #if 0 #define AR_DIAG_EN_SCRAMSD 0x00000200 // enable fixed scrambler seed #endif #define AR_DIAG_SCRAM_SEED 0x0001FE00 // Mask for fixed scrambler seed #define AR_DIAG_SCRAM_SEED_S 8 // Shift for fixed scrambler seed #define AR_DIAG_FRAME_NV0 0x00020000 // accept w/protocol version !0 #define AR_DIAG_OBS_PT_SEL1 0x000C0000 // observation point select #define AR_DIAG_OBS_PT_SEL1_S 18 // Shift for observation point select #define AR_DIAG_FORCE_RX_CLEAR 0x00100000 // force rx_clear high #define AR_DIAG_IGNORE_VIRT_CS 0x00200000 // ignore virtual carrier sense #define AR_DIAG_FORCE_CH_IDLE_HIGH 0x00400000 // force channel idle high #define AR_DIAG_EIFS_CTRL_ENA 0x00800000 // use framed and ~wait_wep if 0 #define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 // dual chain channel info #define AR_DIAG_RX_ABORT 0x02000000 // abort rx #define AR_DIAG_SATURATE_CYCLE_CNT 0x04000000 // saturate cycle cnts (no shift) #define AR_DIAG_OBS_PT_SEL2 0x08000000 // Mask for observation point sel #define AR_DIAG_RX_CLEAR_CTL_LOW 0x10000000 // force rx_clear (ctl) low (i.e. busy) #define AR_DIAG_RX_CLEAR_EXT_LOW 0x20000000 // force rx_clear (ext) low (i.e. busy) #define AR_TSF_L32 0x804c // MAC local clock lower 32 bits #define AR_TSF_U32 0x8050 // MAC local clock upper 32 bits #define AR_TST_ADDAC 0x8054 // ADDAC test register #define AR_DEF_ANTENNA 0x8058 // default antenna register #if 0 #define AR_DEF_ANT_CHN_SEL 0x4 // Default Ant Chain Select bit #define AR_DEF_ANT_CHN0_ANT 0x1 // Def Ant Chain 0 Antenna Select bit #define AR_DEF_ANT_CHN1_ANT 0x2 // Def Ant Chain 1 Antenna Select bit #endif #define AR_AES_MUTE_MASK0 0x805c // MAC AES mute mask #define AR_AES_MUTE_MASK0_FC 0x0000FFFF // frame ctrl mask bits #define AR_AES_MUTE_MASK0_QOS 0xFFFF0000 // qos ctrl mask bits #define AR_AES_MUTE_MASK0_QOS_S 16 #define AR_AES_MUTE_MASK1 0x8060 // MAC AES mute mask #define AR_AES_MUTE_MASK1_SEQ 0x0000FFFF // seq + frag mask bits #define AR_GATED_CLKS 0x8064 // control clock domain #define AR_GATED_CLKS_TX 0x00000002 #define AR_GATED_CLKS_RX 0x00000004 #define AR_GATED_CLKS_REG 0x00000008 #define AR_OBS_BUS_CTRL 0x8068 // select a bus for observation #define AR_OBS_BUS_SEL_1 0x00040000 #define AR_OBS_BUS_SEL_2 0x00080000 #define AR_OBS_BUS_SEL_3 0x000C0000 #define AR_OBS_BUS_SEL_4 0x08040000 #define AR_OBS_BUS_SEL_5 0x08080000 #define AR_OBS_BUS_1 0x806c // mac debug observation bus #define AR_OBS_BUS_1_PCU 0x00000001 #define AR_OBS_BUS_1_RX_END 0x00000002 #define AR_OBS_BUS_1_RX_WEP 0x00000004 #define AR_OBS_BUS_1_RX_BEACON 0x00000008 #define AR_OBS_BUS_1_RX_FILTER 0x00000010 #define AR_OBS_BUS_1_TX_HCF 0x00000020 #define AR_OBS_BUS_1_QUIET_TIME 0x00000040 #define AR_OBS_BUS_1_CHAN_IDLE 0x00000080 #define AR_OBS_BUS_1_TX_HOLD 0x00000100 #define AR_OBS_BUS_1_TX_FRAME 0x00000200 #define AR_OBS_BUS_1_RX_FRAME 0x00000400 #define AR_OBS_BUS_1_RX_CLEAR 0x00000800 #define AR_OBS_BUS_1_WEP_STATE 0x0003F000 #define AR_OBS_BUS_1_WEP_STATE_S 12 #define AR_OBS_BUS_1_RX_STATE 0x01F00000 #define AR_OBS_BUS_1_RX_STATE_S 20 #define AR_OBS_BUS_1_TX_STATE 0x7E000000 #define AR_OBS_BUS_1_TX_STATE_S 25 #define AR_LAST_TSTP 0x8080 // MAC Time stamp of the last beacon received #define AR_NAV 0x8084 // MAC current NAV value #define AR_RTS_OK 0x8088 // MAC RTS exchange success counter #define AR_RTS_FAIL 0x808c // MAC RTS exchange failure counter #define AR_ACK_FAIL 0x8090 // MAC ACK failure counter #define AR_FCS_FAIL 0x8094 // FCS check failure counter #define AR_BEACON_CNT 0x8098 // Valid beacon counter #if 0 #define AR_XRMODE 0x80c0 // Extended range mode #define AR_XRMODE_XR_POLL_TYPE_M 0x00000003 // poll type mask #define AR_XRMODE_XR_POLL_TYPE_S 0 #define AR_XRMODE_XR_POLL_SUBTYPE_M 0x0000003c // poll type mask #define AR_XRMODE_XR_POLL_SUBTYPE_S 2 #define AR_XRMODE_XR_WAIT_FOR_POLL 0x00000080 // wait for poll sta only #define AR_XRMODE_XR_FRAME_HOLD_M 0xfff00000 // cycles hold for chirps #define AR_XRMODE_XR_FRAME_HOLD_S 20 #define AR_XRDEL 0x80c4 // Extended range delay #define AR_XRDEL_SLOT_DELAY_M 0x0000ffff // cycles #define AR_XRDEL_SLOT_DELAY_S 0 #define AR_XRDEL_CHIRP_DATA_DELAY_M 0xffff0000 // cycles #define AR_XRDEL_CHIRP_DATA_DELAY_S 16 #define AR_XRTO 0x80c8 // Extended range timeout #define AR_XRTO_CHIRP_TO_M 0x0000ffff // cycles #define AR_XRTO_CHIRP_TO_S 0 #define AR_XRTO_POLL_TO_M 0xffff0000 // cycles #define AR_XRTO_POLL_TO_S 16 #define AR_XRCRP 0x80cc // Extended range chirp #define AR_XRCRP_SEND_CHIRP 0x00000001 // generate stand alone chirp #define AR_XRCRP_CHIRP_GAP_M 0xffff0000 // cycles #define AR_XRCRP_CHIRP_GAP_S 16 #define AR_XRSTMP 0x80d0 // Extended range stomp #define AR_XRSTMP_RX_ABORT_RSSI 0x00000001 // stomp low rssi receive #define AR_XRSTMP_RX_ABORT_BSSID 0x00000002 // stomp foreign bssid receive #define AR_XRSTMP_TX_STOMP_RSSI 0x00000004 // xmit stomp low rssi receive #define AR_XRSTMP_TX_STOMP_BSSID 0x00000008 // xmit stomp foreign bssid rx #define AR_XRSTMP_TX_STOMP_DATA 0x00000010 // xmit stomp receive data #define AR_XRSTMP_RX_ABORT_DATA 0x00000020 // stomp receive data #define AR_XRSTMP_TX_RSSI_THRESH_M 0x0000FF00 // threshold for tx stomp #define AR_XRSTMP_TX_RSSI_THRESH_S 8 #define AR_XRSTMP_RX_RSSI_THRESH_M 0x00FF0000 // threshold for tx stomp #define AR_XRSTMP_RX_RSSI_THRESH_S 16 #endif #define AR_SLEEP1 0x80d4 // Enhanced sleep control 1 #if 0 #define AR_SLEEP1_NEXT_DTIM_M 0x0007ffff // Absolute time(1/8TU) for next dtim mask #define AR_SLEEP1_NEXT_DTIM_S 0 // Absolute time(1/8TU) for next dtim shift #endif #define AR_SLEEP1_ASSUME_DTIM 0x00080000 // Assume DTIM on missed beacon #if 0 #define AR_SLEEP1_ENH_SLEEP_ENABLE 0x00100000 // Enables Venice sleep logic #endif #define AR_SLEEP1_CAB_TIMEOUT 0xFFE00000 // Cab timeout(TU) mask #define AR_SLEEP1_CAB_TIMEOUT_S 21 // Cab timeout(TU) shift #define AR_SLEEP2 0x80d8 // Enhanced sleep control 2 #if 0 #define AR_SLEEP2_NEXT_TIM_M 0x0007ffff // Absolute time(1/8TU) for next tim/beacon mask #define AR_SLEEP2_NEXT_TIM_S 0 // Absolute time(1/8TU) for next tim/beacon shift #endif #define AR_SLEEP2_BEACON_TIMEOUT 0xFFE00000 // Beacon timeout(TU) mask #define AR_SLEEP2_BEACON_TIMEOUT_S 21 // Beacon timeout(TU) shift #if 0 #define AR_SLEEP3 0x80dc // Enhanced sleep control 3 #define AR_SLEEP3_TIM_PERIOD_M 0x0000ffff // Tim/Beacon period(TU) mask #define AR_SLEEP3_TIM_PERIOD_S 0 // Tim/Beacon period(TU) shift #define AR_SLEEP3_DTIM_PERIOD_M 0xffff0000 // DTIM period(TU) mask #define AR_SLEEP3_DTIM_PERIOD_S 16 // DTIM period(TU) shift #endif #define AR_BSSMSKL 0x80e0 // BSSID mask lower 32 bits #define AR_BSSMSKU 0x80e4 // BSSID mask upper 16 bits #define AR_TPC 0x80e8 // Transmit power control for gen frames #define AR_TPC_ACK 0x0000003f // ack frames mask #define AR_TPC_ACK_S 0x00 // ack frames shift #define AR_TPC_CTS 0x00003f00 // cts frames mask #define AR_TPC_CTS_S 0x08 // cts frames shift #define AR_TPC_CHIRP 0x003f0000 // chirp frames mask #define AR_TPC_CHIRP_S 0x16 // chirp frames shift #define AR_TFCNT 0x80ec // Profile count transmit frames #define AR_RFCNT 0x80f0 // Profile count receive frames #define AR_RCCNT 0x80f4 // Profile count receive clear #define AR_CCCNT 0x80f8 // Profile count cycle counter #define AR_QUIET1 0x80fc // Quiet time programming for TGh #if 0 #define AR_QUIET1_NEXT_QUIET_S 0 // TSF of next quiet period (TU) #define AR_QUIET1_NEXT_QUIET_M 0x0000ffff #define AR_QUIET1_QUIET_ENABLE 0x00010000 // Enable Quiet time operation #endif #define AR_QUIET1_QUIET_ACK_CTS_ENABLE 0x00020000 // ack/cts in quiet period #define AR_QUIET2 0x8100 // More Quiet programming #if 0 #define AR_QUIET2_QUIET_PERIOD_S 0 // Periodicity of quiet period (TU) #define AR_QUIET2_QUIET_PERIOD_M 0x0000ffff #endif #define AR_QUIET2_QUIET_DURATION_S 16 // quiet period (TU) #define AR_QUIET2_QUIET_DURATION 0xffff0000 #define AR_TSF_PARM 0x8104 // TSF parameters #define AR_TSF_INCREMENT_M 0x000000ff #define AR_TSF_INCREMENT_S 0x00 #define AR_QOS_NO_ACK 0x8108 // locate no_ack in qos #define AR_QOS_NO_ACK_TWO_BIT 0x0000000f // 2 bit sentinel for no-ack #define AR_QOS_NO_ACK_TWO_BIT_S 0 #define AR_QOS_NO_ACK_BIT_OFF 0x00000070 // offset for no-ack #define AR_QOS_NO_ACK_BIT_OFF_S 4 #define AR_QOS_NO_ACK_BYTE_OFF 0x00000180 // from end of header #define AR_QOS_NO_ACK_BYTE_OFF_S 7 #define AR_PHY_ERR 0x810c // Phy errors to be filtered /* XXX validate! XXX */ #define AR_PHY_ERR_DCHIRP 0x00000008 // Bit 3 enables double chirp #define AR_PHY_ERR_RADAR 0x00000020 // Bit 5 is Radar signal #define AR_PHY_ERR_OFDM_TIMING 0x00020000 // Bit 17 is false detect for OFDM #define AR_PHY_ERR_CCK_TIMING 0x02000000 // Bit 25 is false detect for CCK #define AR_RXFIFO_CFG 0x8114 /* XXX sub-fields? XXX */ #define AR_MIC_QOS_CONTROL 0x8118 #define AR_MIC_QOS_SELECT 0x811c #define AR_PCU_MISC 0x8120 // PCU Miscellaneous Mode #define AR_PCU_FORCE_BSSID_MATCH 0x00000001 // force bssid to match #define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 // tx/rx mic key are together #define AR_PCU_TX_ADD_TSF 0x00000008 // add tx_tsf + int_tsf #define AR_PCU_CCK_SIFS_MODE 0x00000010 // assume 11b sifs programmed #define AR_PCU_RX_ANT_UPDT 0x00000800 // KC_RX_ANT_UPDATE #define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 // enforce txop / tbtt #define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 // count bmiss's when sleeping #define AR_PCU_BUG_12306_FIX_ENA 0x00020000 // use rx_clear to count sifs #define AR_PCU_FORCE_QUIET_COLL 0x00040000 // kill xmit for channel change #define AR_PCU_BT_ANT_PREVENT_RX 0x00100000 #define AR_PCU_TBTT_PROTECT 0x00200000 // no xmit upto tbtt + 20 uS #define AR_PCU_CLEAR_VMF 0x01000000 // clear vmf mode (fast cc) #define AR_PCU_CLEAR_BA_VALID 0x04000000 // clear ba state #define AR_FILT_OFDM 0x8124 #define AR_FILT_OFDM_COUNT 0x00FFFFFF // count of filtered ofdm #define AR_FILT_CCK 0x8128 #define AR_FILT_CCK_COUNT 0x00FFFFFF // count of filtered cck #define AR_PHY_ERR_1 0x812c #define AR_PHY_ERR_1_COUNT 0x00FFFFFF // phy errs that pass mask_1 #define AR_PHY_ERR_MASK_1 0x8130 // mask for err_1_count #define AR_PHY_ERR_2 0x8134 #define AR_PHY_ERR_2_COUNT 0x00FFFFFF // phy errs that pass mask_2 #define AR_PHY_ERR_MASK_2 0x8138 // mask for err_2_count #define AR_PHY_COUNTMAX (3 << 22) // Max counted before intr #define AR_MIBCNT_INTRMASK (3 << 22) // Mask top 2 bits of counters #define AR_TSF_THRESHOLD 0x813c // interrupt if rx_tsf-int_tsf #define AR_TSF_THRESHOLD_VAL 0x0000FFFF // exceeds threshold #define AR_PHY_ERR_EIFS_MASK 0x8144 // phy_errs causing eifs delay #define AR_PHY_ERR_3 0x8168 #define AR_PHY_ERR_3_COUNT 0x00FFFFFF // phy errs that pass mask_3 #define AR_PHY_ERR_MASK_3 0x816c // mask for err_3_count #define AR_BT_COEX_MODE 0x8170 #define AR_BT_TIME_EXTEND 0x000000ff #define AR_BT_TIME_EXTEND_S 0 #define AR_BT_TXSTATE_EXTEND 0x00000100 #define AR_BT_TXSTATE_EXTEND_S 8 #define AR_BT_TX_FRAME_EXTEND 0x00000200 #define AR_BT_TX_FRAME_EXTEND_S 9 #define AR_BT_MODE 0x00000c00 #define AR_BT_MODE_S 10 #define AR_BT_QUIET 0x00001000 #define AR_BT_QUIET_S 12 #define AR_BT_QCU_THRESH 0x0001e000 #define AR_BT_QCU_THRESH_S 13 #define AR_BT_RX_CLEAR_POLARITY 0x00020000 #define AR_BT_RX_CLEAR_POLARITY_S 17 #define AR_BT_PRIORITY_TIME 0x00fc0000 #define AR_BT_PRIORITY_TIME_S 18 #define AR_BT_FIRST_SLOT_TIME 0xff000000 #define AR_BT_FIRST_SLOT_TIME_S 24 #define AR_BT_COEX_WEIGHT 0x8174 #define AR_BT_BT_WGHT 0x0000ffff #define AR_BT_BT_WGHT_S 0 #define AR_BT_WL_WGHT 0xffff0000 #define AR_BT_WL_WGHT_S 16 #define AR_TXSIFS 0x81d0 #define AR_TXSIFS_TIME 0x000000FF // uS in SIFS #define AR_TXSIFS_TX_LATENCY 0x00000F00 // uS for transmission thru bb #define AR_TXSIFS_TX_LATENCY_S 8 #define AR_TXSIFS_ACK_SHIFT 0x00007000 // chan width for ack #define AR_TXSIFS_ACK_SHIFT_S 12 #define AR_TXOP_X 0x81ec // txop for legacy non-qos #define AR_TXOP_X_VAL 0x000000FF /* on-demand subfields */ #define AR_TXOP_0_3 0x81f0 // txop for various tid's #define AR_TXOP_4_7 0x81f4 #define AR_TXOP_8_11 0x81f8 #define AR_TXOP_12_15 0x81fc #if 0 #define AR_KC_MASK 0x81c4 // MAC Key Cache Mask for words 0x10 0x14 // 0 is write allow 1 is write blocked #define AR_KC_MASK_TYPE_M 0x00000007 // MAC Key Cache Type Mask #define AR_KC_MASK_LAST_TX_ANT 0x00000008 // MAC Key Cache Last Tx Ant Mask #define AR_KC_MASK_ASYNC_MASK_M 0x000001f0 // MAC Key Cache Async Rate Offset Mask #define AR_KC_MASK_UPDT_BF 0x00000200 // MAC Key Cache Update Bf coef Mask #define AR_KC_MASK_RX_CHAIN0_ACK 0x00000400 // MAC Key Cache Ack Ant Ch 0 Mask #define AR_KC_MASK_RX_CHAIN1_ACK 0x00000800 // MAC Key Cache Ack Ant Ch 1 Mask #define AR_KC_MASK_TX_CHAIN0_SEL 0x00001000 // MAC Key Cache Tx Sel Ant Ch 0 Mask #define AR_KC_MASK_TX_CHAIN1_SEL 0x00002000 // MAC Key Cache Tx Sel Ant Ch 1 Mask #define AR_KC_MASK_CHAIN_SEL 0x00004000 // MAC Key Cache Chain Sel Mask #define AR_KC_MASK_WORD_10 0x00010000 // MAC Key Cache Word 0x10 Mask #endif /* generic timers based on tsf - all uS */ #define AR_NEXT_TBTT_TIMER 0x8200 #define AR_NEXT_DMA_BEACON_ALERT 0x8204 #define AR_NEXT_SWBA 0x8208 #define AR_NEXT_CFP 0x8208 #define AR_NEXT_HCF 0x820C #define AR_NEXT_TIM 0x8210 #define AR_NEXT_DTIM 0x8214 #define AR_NEXT_QUIET_TIMER 0x8218 #define AR_NEXT_NDP_TIMER 0x821C #define AR_BEACON_PERIOD 0x8220 #define AR_DMA_BEACON_PERIOD 0x8224 #define AR_SWBA_PERIOD 0x8228 #define AR_HCF_PERIOD 0x822C #define AR_TIM_PERIOD 0x8230 #define AR_DTIM_PERIOD 0x8234 #define AR_QUIET_PERIOD 0x8238 #define AR_NDP_PERIOD 0x823C #define AR_TIMER_MODE 0x8240 #define AR_TBTT_TIMER_EN 0x00000001 #define AR_DBA_TIMER_EN 0x00000002 #define AR_SWBA_TIMER_EN 0x00000004 #define AR_HCF_TIMER_EN 0x00000008 #define AR_TIM_TIMER_EN 0x00000010 #define AR_DTIM_TIMER_EN 0x00000020 #define AR_QUIET_TIMER_EN 0x00000040 #define AR_NDP_TIMER_EN 0x00000080 #define AR_TIMER_OVERFLOW_INDEX 0x00000700 #define AR_TIMER_OVERFLOW_INDEX_S 8 #define AR_TIMER_THRESH 0xFFFFF000 #define AR_TIMER_THRESH_S 12 #define AR_SLP32_MODE 0x8244 #define AR_SLP32_HALF_CLK_LATENCY 0x000FFFFF // rising <-> falling edge #define AR_SLP32_ENA 0x00100000 #define AR_SLP32_TSF_WRITE_STATUS 0x00200000 // tsf update in progress #define AR_SLP32_WAKE 0x8248 #define AR_SLP32_WAKE_XTL_TIME 0x0000FFFF // time to wake crystal #define AR_SLP32_INC 0x824c #define AR_SLP32_TST_INC 0x000FFFFF #define AR_SLP_CNT 0x8250 // 32kHz cycles for which mac is asleep #define AR_SLP_CYCLE_CNT 0x8254 // absolute number of 32kHz cycles #define AR_SLP_MIB_CTRL 0x8258 #define AR_SLP_MIB_CLEAR 0x00000001 // clear pending #define AR_SLP_MIB_PENDING 0x00000002 // clear counters #ifdef AR5416_EMULATION // MAC trace buffer registers (emulation only) #define AR_MAC_PCU_LOGIC_ANALYZER 0x8264 #define AR_MAC_PCU_LOGIC_ANALYZER_CTL 0x0000000F #define AR_MAC_PCU_LOGIC_ANALYZER_HOLD 0x00000001 #define AR_MAC_PCU_LOGIC_ANALYZER_CLEAR 0x00000002 #define AR_MAC_PCU_LOGIC_ANALYZER_STATE 0x00000004 #define AR_MAC_PCU_LOGIC_ANALYZER_ENABLE 0x00000008 #define AR_MAC_PCU_LOGIC_ANALYZER_QCU_SEL 0x000000F0 #define AR_MAC_PCU_LOGIC_ANALYZER_QCU_SEL_S 4 #define AR_MAC_PCU_LOGIC_ANALYZER_INT_ADDR 0x0003FF00 #define AR_MAC_PCU_LOGIC_ANALYZER_INT_ADDR_S 8 #define AR_MAC_PCU_LOGIC_ANALYZER_DIAG_MODE 0xFFFC0000 #define AR_MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_S 18 #define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20614 0x00040000 #define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768 0x20000000 #define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20803 0x40000000 #define AR_MAC_PCU_LOGIC_ANALYZER_32L 0x8268 #define AR_MAC_PCU_LOGIC_ANALYZER_16U 0x826C #define AR_MAC_PCU_TRACE_REG_START 0xE000 #define AR_MAC_PCU_TRACE_REG_END 0xFFFC #define AR_MAC_PCU_TRACE_BUFFER_LENGTH (AR_MAC_PCU_TRACE_REG_END - AR_MAC_PCU_TRACE_REG_START + sizeof(a_uint32_t)) #endif // AR5416_EMULATION #define AR_2040_MODE 0x8318 #define AR_2040_JOINED_RX_CLEAR 0x00000001 // use ctl + ext rx_clear for cca /* Additional cycle counter. See also AR_CCCNT */ #define AR_EXTRCCNT 0x8328 // extension channel rx clear count // counts number of cycles rx_clear (ext) is low (i.e. busy) // when the MAC is not actively transmitting/receiving #define AR_SELFGEN_MASK 0x832c #if 0 #define AR_FRM_TYPE_CAP_TBL 0x8500 // Frame Type Capabilities Table #define AR_FRM_TYPE_CAP_SIZE 64 // Frame Type Cap. Table Size #define AR_FTC_BF_RX_UPDT_NORM 0x00000001 // BFCOEF_RX_UPDATE_NORMAL #define AR_FTC_BF_RX_UPDT_SELF 0x00000002 // BFCOEF_RX_UPDATE_SELF_GEN #define AR_FTC_BF_TX_ENB_NORM 0x00000004 // BFCOEF_TX_ENABLE_NORMAL #define AR_FTC_BF_TX_ENB_SELF 0x00000008 // BFCOEF_TX_ENABLE_SELF_GEN #define AR_FTC_BF_TX_ENB_GEN 0x00000010 // BFCOEF_TX_ENABLE_GEN #define AR_FTC_BF_TX_ENB_MCAST 0x00000020 // BFCOEF_TX_ENABLE_MCAST // rate duration registers - used for Multi-rate retry. #define AR_RATE_DURATION_0 0x8700 // 32 registers from 0x8700 to 0x87CC #define AR_RATE_DURATION_31 0x87CC #endif #define AR_KEYTABLE_0 0x8800 /* MAC Key Cache */ #define AR_KEYTABLE(_n) (AR_KEYTABLE_0 + ((_n)*32)) #define AR_KEY_CACHE_SIZE 128 #define AR_RSVD_KEYTABLE_ENTRIES 4 #define AR_KEY_TYPE 0x00000007 // MAC Key Type Mask #define AR_KEYTABLE_TYPE_40 0x00000000 /* WEP 40 bit key */ #define AR_KEYTABLE_TYPE_104 0x00000001 /* WEP 104 bit key */ #define AR_KEYTABLE_TYPE_128 0x00000003 /* WEP 128 bit key */ #define AR_KEYTABLE_TYPE_TKIP 0x00000004 /* TKIP and Michael */ #define AR_KEYTABLE_TYPE_AES 0x00000005 /* AES/OCB 128 bit key */ #define AR_KEYTABLE_TYPE_CCM 0x00000006 /* AES/CCM 128 bit key */ #define AR_KEYTABLE_TYPE_CLR 0x00000007 /* no encryption */ #define AR_KEYTABLE_ANT 0x00000008 /* previous transmit antenna */ #define AR_KEYTABLE_VALID 0x00008000 /* key and MAC address valid */ #define AR_KEYTABLE_KEY0(_n) (AR_KEYTABLE(_n) + 0) /* key bit 0-31 */ #define AR_KEYTABLE_KEY1(_n) (AR_KEYTABLE(_n) + 4) /* key bit 32-47 */ #define AR_KEYTABLE_KEY2(_n) (AR_KEYTABLE(_n) + 8) /* key bit 48-79 */ #define AR_KEYTABLE_KEY3(_n) (AR_KEYTABLE(_n) + 12) /* key bit 80-95 */ #define AR_KEYTABLE_KEY4(_n) (AR_KEYTABLE(_n) + 16) /* key bit 96-127 */ #define AR_KEYTABLE_TYPE(_n) (AR_KEYTABLE(_n) + 20) /* key type */ #define AR_KEYTABLE_MAC0(_n) (AR_KEYTABLE(_n) + 24) /* MAC address 1-32 */ #define AR_KEYTABLE_MAC1(_n) (AR_KEYTABLE(_n) + 28) /* MAC address 33-47 */ #define BT_WGHT 0xff55 #define STOMP_ALL_WLAN_WGHT 0xfcfc #define STOMP_LOW_WLAN_WGHT 0xa8a8 #define STOMP_NONE_WLAN_WGHT 0x0000 #endif open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/ieee80211.h000077500000000000000000001272641321570333100262210ustar00rootroot00000000000000/*- * Copyright (c) 2001 Atsushi Onoe * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * Alternatively, this software may be distributed under the terms of the * GNU General Public License ("GPL") version 2 as published by the Free * Software Foundation. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD: src/sys/net80211/ieee80211.h,v 1.8 2004/12/31 22:44:26 sam Exp $ */ #ifndef _NET80211_IEEE80211_H_ #define _NET80211_IEEE80211_H_ /* * 802.11 protocol definitions. */ #define IEEE80211_ADDR_LEN 6 /* size of 802.11 address */ /* is 802.11 address multicast/broadcast? */ #define IEEE80211_IS_MULTICAST(_a) (*(_a) & 0x01) #ifdef __CARRIER_PLATFORM__ #include #endif /* IEEE 802.11 PLCP header */ struct ieee80211_plcp_hdr { a_uint16_t i_sfd; a_uint8_t i_signal; a_uint8_t i_service; a_uint16_t i_length; a_uint16_t i_crc; } adf_os_packed; #define IEEE80211_PLCP_SFD 0xF3A0 #define IEEE80211_PLCP_SERVICE 0x00 /* * generic definitions for IEEE 802.11 frames */ struct ieee80211_frame { a_uint8_t i_fc[2]; a_uint8_t i_dur[2]; a_uint8_t i_addr1[IEEE80211_ADDR_LEN]; a_uint8_t i_addr2[IEEE80211_ADDR_LEN]; a_uint8_t i_addr3[IEEE80211_ADDR_LEN]; a_uint8_t i_seq[2]; /* possibly followed by addr4[IEEE80211_ADDR_LEN]; */ /* see below */ } adf_os_packed; struct ieee80211_qosframe { a_uint8_t i_fc[2]; a_uint8_t i_dur[2]; a_uint8_t i_addr1[IEEE80211_ADDR_LEN]; a_uint8_t i_addr2[IEEE80211_ADDR_LEN]; a_uint8_t i_addr3[IEEE80211_ADDR_LEN]; a_uint8_t i_seq[2]; a_uint8_t i_qos[2]; /* possibly followed by addr4[IEEE80211_ADDR_LEN]; */ /* see below */ } adf_os_packed; struct ieee80211_qoscntl { a_uint8_t i_qos[2]; }; struct ieee80211_frame_addr4 { a_uint8_t i_fc[2]; a_uint8_t i_dur[2]; a_uint8_t i_addr1[IEEE80211_ADDR_LEN]; a_uint8_t i_addr2[IEEE80211_ADDR_LEN]; a_uint8_t i_addr3[IEEE80211_ADDR_LEN]; a_uint8_t i_seq[2]; a_uint8_t i_addr4[IEEE80211_ADDR_LEN]; } adf_os_packed; struct ieee80211_qosframe_addr4 { a_uint8_t i_fc[2]; a_uint8_t i_dur[2]; a_uint8_t i_addr1[IEEE80211_ADDR_LEN]; a_uint8_t i_addr2[IEEE80211_ADDR_LEN]; a_uint8_t i_addr3[IEEE80211_ADDR_LEN]; a_uint8_t i_seq[2]; a_uint8_t i_addr4[IEEE80211_ADDR_LEN]; a_uint8_t i_qos[2]; } adf_os_packed; struct ieee80211_ctlframe_addr2 { a_uint8_t i_fc[2]; a_uint8_t i_aidordur[2]; /* AID or duration */ a_uint8_t i_addr1[IEEE80211_ADDR_LEN]; a_uint8_t i_addr2[IEEE80211_ADDR_LEN]; } adf_os_packed; #define IEEE80211_FC0_VERSION_MASK 0x03 #define IEEE80211_FC0_VERSION_SHIFT 0 #define IEEE80211_FC0_VERSION_0 0x00 #define IEEE80211_FC0_TYPE_MASK 0x0c #define IEEE80211_FC0_TYPE_SHIFT 2 #define IEEE80211_FC0_TYPE_MGT 0x00 #define IEEE80211_FC0_TYPE_CTL 0x04 #define IEEE80211_FC0_TYPE_DATA 0x08 #define IEEE80211_FC0_SUBTYPE_MASK 0xf0 #define IEEE80211_FC0_SUBTYPE_SHIFT 4 /* for TYPE_MGT */ #define IEEE80211_FC0_SUBTYPE_ASSOC_REQ 0x00 #define IEEE80211_FC0_SUBTYPE_ASSOC_RESP 0x10 #define IEEE80211_FC0_SUBTYPE_REASSOC_REQ 0x20 #define IEEE80211_FC0_SUBTYPE_REASSOC_RESP 0x30 #define IEEE80211_FC0_SUBTYPE_PROBE_REQ 0x40 #define IEEE80211_FC0_SUBTYPE_PROBE_RESP 0x50 #define IEEE80211_FC0_SUBTYPE_BEACON 0x80 #define IEEE80211_FC0_SUBTYPE_ATIM 0x90 #define IEEE80211_FC0_SUBTYPE_DISASSOC 0xa0 #define IEEE80211_FC0_SUBTYPE_AUTH 0xb0 #define IEEE80211_FC0_SUBTYPE_DEAUTH 0xc0 #define IEEE80211_FC0_SUBTYPE_ACTION 0xd0 /* for TYPE_CTL */ #define IEEE80211_FC0_SUBTYPE_BAR 0x80 #define IEEE80211_FC0_SUBTYPE_PS_POLL 0xa0 #define IEEE80211_FC0_SUBTYPE_RTS 0xb0 #define IEEE80211_FC0_SUBTYPE_CTS 0xc0 #define IEEE80211_FC0_SUBTYPE_ACK 0xd0 #define IEEE80211_FC0_SUBTYPE_CF_END 0xe0 #define IEEE80211_FC0_SUBTYPE_CF_END_ACK 0xf0 /* for TYPE_DATA (bit combination) */ #define IEEE80211_FC0_SUBTYPE_DATA 0x00 #define IEEE80211_FC0_SUBTYPE_CF_ACK 0x10 #define IEEE80211_FC0_SUBTYPE_CF_POLL 0x20 #define IEEE80211_FC0_SUBTYPE_CF_ACPL 0x30 #define IEEE80211_FC0_SUBTYPE_NODATA 0x40 #define IEEE80211_FC0_SUBTYPE_CFACK 0x50 #define IEEE80211_FC0_SUBTYPE_CFPOLL 0x60 #define IEEE80211_FC0_SUBTYPE_CF_ACK_CF_ACK 0x70 #define IEEE80211_FC0_SUBTYPE_QOS 0x80 #define IEEE80211_FC0_SUBTYPE_QOS_NULL 0xc0 #define IEEE80211_FC1_DIR_MASK 0x03 #define IEEE80211_FC1_DIR_NODS 0x00 /* STA->STA */ #define IEEE80211_FC1_DIR_TODS 0x01 /* STA->AP */ #define IEEE80211_FC1_DIR_FROMDS 0x02 /* AP ->STA */ #define IEEE80211_FC1_DIR_DSTODS 0x03 /* AP ->AP */ #define IEEE80211_FC1_MORE_FRAG 0x04 #define IEEE80211_FC1_RETRY 0x08 #define IEEE80211_FC1_PWR_MGT 0x10 #define IEEE80211_FC1_MORE_DATA 0x20 #define IEEE80211_FC1_WEP 0x40 #define IEEE80211_FC1_ORDER 0x80 #define IEEE80211_SEQ_FRAG_MASK 0x000f #define IEEE80211_SEQ_FRAG_SHIFT 0 #define IEEE80211_SEQ_SEQ_MASK 0xfff0 #define IEEE80211_SEQ_SEQ_SHIFT 4 #define IEEE80211_SEQ_LEQ(a,b) ((a_int32_t)((a)-(b)) <= 0) #define IEEE80211_NWID_LEN 32 #define IEEE80211_QOS_TXOP 0x00ff #define IEEE80211_QOS_AMSDU 0x80 #define IEEE80211_QOS_AMSDU_S 7 #define IEEE80211_QOS_ACKPOLICY 0x60 #define IEEE80211_QOS_ACKPOLICY_S 5 #define IEEE80211_QOS_EOSP 0x10 #define IEEE80211_QOS_EOSP_S 4 #define IEEE80211_QOS_TID 0x0f /* * Country/Region Codes from MS WINNLS.H * Numbering from ISO 3166 * XXX belongs elsewhere */ enum CountryCode { CTRY_ALBANIA = 8, /* Albania */ CTRY_ALGERIA = 12, /* Algeria */ CTRY_ARGENTINA = 32, /* Argentina */ CTRY_ARMENIA = 51, /* Armenia */ CTRY_AUSTRALIA = 36, /* Australia */ CTRY_AUSTRIA = 40, /* Austria */ CTRY_AZERBAIJAN = 31, /* Azerbaijan */ CTRY_BAHRAIN = 48, /* Bahrain */ CTRY_BELARUS = 112, /* Belarus */ CTRY_BELGIUM = 56, /* Belgium */ CTRY_BELIZE = 84, /* Belize */ CTRY_BOLIVIA = 68, /* Bolivia */ CTRY_BOSNIA_HERZEGOWINA = 70, /* Bosnia and Herzegowina */ CTRY_BRAZIL = 76, /* Brazil */ CTRY_BRUNEI_DARUSSALAM = 96, /* Brunei Darussalam */ CTRY_BULGARIA = 100, /* Bulgaria */ CTRY_CANADA = 124, /* Canada */ CTRY_CHILE = 152, /* Chile */ CTRY_CHINA = 156, /* People's Republic of China */ CTRY_COLOMBIA = 170, /* Colombia */ CTRY_COSTA_RICA = 188, /* Costa Rica */ CTRY_CROATIA = 191, /* Croatia */ CTRY_CYPRUS = 196, CTRY_CZECH = 203, /* Czech Republic */ CTRY_DENMARK = 208, /* Denmark */ CTRY_DOMINICAN_REPUBLIC = 214, /* Dominican Republic */ CTRY_ECUADOR = 218, /* Ecuador */ CTRY_EGYPT = 818, /* Egypt */ CTRY_EL_SALVADOR = 222, /* El Salvador */ CTRY_ESTONIA = 233, /* Estonia */ CTRY_FAEROE_ISLANDS = 234, /* Faeroe Islands */ CTRY_FINLAND = 246, /* Finland */ CTRY_FRANCE = 250, /* France */ CTRY_FRANCE2 = 255, /* France2 */ CTRY_GEORGIA = 268, /* Georgia */ CTRY_GERMANY = 276, /* Germany */ CTRY_GREECE = 300, /* Greece */ CTRY_GUATEMALA = 320, /* Guatemala */ CTRY_HONDURAS = 340, /* Honduras */ CTRY_HONG_KONG = 344, /* Hong Kong S.A.R., P.R.C. */ CTRY_HUNGARY = 348, /* Hungary */ CTRY_ICELAND = 352, /* Iceland */ CTRY_INDIA = 356, /* India */ CTRY_INDONESIA = 360, /* Indonesia */ CTRY_IRAN = 364, /* Iran */ CTRY_IRAQ = 368, /* Iraq */ CTRY_IRELAND = 372, /* Ireland */ CTRY_ISRAEL = 376, /* Israel */ CTRY_ITALY = 380, /* Italy */ CTRY_JAMAICA = 388, /* Jamaica */ CTRY_JAPAN = 392, /* Japan */ CTRY_JAPAN1 = 393, /* Japan (JP1) */ CTRY_JAPAN2 = 394, /* Japan (JP0) */ CTRY_JAPAN3 = 395, /* Japan (JP1-1) */ CTRY_JAPAN4 = 396, /* Japan (JE1) */ CTRY_JAPAN5 = 397, /* Japan (JE2) */ CTRY_JAPAN6 = 399, /* Japan (JP6) */ CTRY_JAPAN7 = 4007, /* Japan */ CTRY_JAPAN8 = 4008, /* Japan */ CTRY_JAPAN9 = 4009, /* Japan */ CTRY_JAPAN10 = 4010, /* Japan */ CTRY_JAPAN11 = 4011, /* Japan */ CTRY_JAPAN12 = 4012, /* Japan */ CTRY_JAPAN13 = 4013, /* Japan */ CTRY_JAPAN14 = 4014, /* Japan */ CTRY_JAPAN15 = 4015, /* Japan */ CTRY_JAPAN16 = 4016, /* Japan */ CTRY_JAPAN17 = 4017, /* Japan */ CTRY_JAPAN18 = 4018, /* Japan */ CTRY_JAPAN19 = 4019, /* Japan */ CTRY_JAPAN20 = 4020, /* Japan */ CTRY_JAPAN21 = 4021, /* Japan */ CTRY_JAPAN22 = 4022, /* Japan */ CTRY_JAPAN23 = 4023, /* Japan */ CTRY_JAPAN24 = 4024, /* Japan */ CTRY_JORDAN = 400, /* Jordan */ CTRY_KAZAKHSTAN = 398, /* Kazakhstan */ CTRY_KENYA = 404, /* Kenya */ CTRY_KOREA_NORTH = 408, /* North Korea */ CTRY_KOREA_ROC = 410, /* South Korea */ CTRY_KOREA_ROC2 = 411, /* South Korea */ CTRY_KUWAIT = 414, /* Kuwait */ CTRY_LATVIA = 428, /* Latvia */ CTRY_LEBANON = 422, /* Lebanon */ CTRY_LIBYA = 434, /* Libya */ CTRY_LIECHTENSTEIN = 438, /* Liechtenstein */ CTRY_LITHUANIA = 440, /* Lithuania */ CTRY_LUXEMBOURG = 442, /* Luxembourg */ CTRY_MACAU = 446, /* Macau */ CTRY_MACEDONIA = 807, /* the Former Yugoslav Republic of Macedonia */ CTRY_MALAYSIA = 458, /* Malaysia */ CTRY_MEXICO = 484, /* Mexico */ CTRY_MONACO = 492, /* Principality of Monaco */ CTRY_MOROCCO = 504, /* Morocco */ CTRY_NETHERLANDS = 528, /* Netherlands */ CTRY_NEW_ZEALAND = 554, /* New Zealand */ CTRY_NICARAGUA = 558, /* Nicaragua */ CTRY_NORWAY = 578, /* Norway */ CTRY_OMAN = 512, /* Oman */ CTRY_PAKISTAN = 586, /* Islamic Republic of Pakistan */ CTRY_PANAMA = 591, /* Panama */ CTRY_PARAGUAY = 600, /* Paraguay */ CTRY_PERU = 604, /* Peru */ CTRY_PHILIPPINES = 608, /* Republic of the Philippines */ CTRY_POLAND = 616, /* Poland */ CTRY_PORTUGAL = 620, /* Portugal */ CTRY_PUERTO_RICO = 630, /* Puerto Rico */ CTRY_QATAR = 634, /* Qatar */ CTRY_ROMANIA = 642, /* Romania */ CTRY_RUSSIA = 643, /* Russia */ CTRY_SAUDI_ARABIA = 682, /* Saudi Arabia */ CTRY_SINGAPORE = 702, /* Singapore */ CTRY_SLOVAKIA = 703, /* Slovak Republic */ CTRY_SLOVENIA = 705, /* Slovenia */ CTRY_SOUTH_AFRICA = 710, /* South Africa */ CTRY_SPAIN = 724, /* Spain */ CTRY_SRI_LANKA = 144, /* Sri Lanka */ CTRY_SWEDEN = 752, /* Sweden */ CTRY_SWITZERLAND = 756, /* Switzerland */ CTRY_SYRIA = 760, /* Syria */ CTRY_TAIWAN = 158, /* Taiwan */ CTRY_THAILAND = 764, /* Thailand */ CTRY_TRINIDAD_Y_TOBAGO = 780, /* Trinidad y Tobago */ CTRY_TUNISIA = 788, /* Tunisia */ CTRY_TURKEY = 792, /* Turkey */ CTRY_UAE = 784, /* U.A.E. */ CTRY_UKRAINE = 804, /* Ukraine */ CTRY_UNITED_KINGDOM = 826, /* United Kingdom */ CTRY_UNITED_STATES = 840, /* United States */ CTRY_UNITED_STATES_FCC49 = 842, /* United States (Public Safety)*/ CTRY_URUGUAY = 858, /* Uruguay */ CTRY_UZBEKISTAN = 860, /* Uzbekistan */ CTRY_VENEZUELA = 862, /* Venezuela */ CTRY_VIET_NAM = 704, /* Viet Nam */ CTRY_YEMEN = 887, /* Yemen */ CTRY_ZIMBABWE = 716, /* Zimbabwe */ CTRY_AUSTRALIA2 = 5000, /* Australia */ CTRY_CANADA2 = 5001 /* Canada */ }; /* * Country information element. */ #define IEEE80211_COUNTRY_MAX_TRIPLETS (83) struct ieee80211_ie_country { a_uint8_t country_id; a_uint8_t country_len; a_uint8_t country_str[3]; a_uint8_t country_triplet[IEEE80211_COUNTRY_MAX_TRIPLETS*3]; } adf_os_packed; /* does frame have QoS sequence control data */ #define IEEE80211_QOS_HAS_SEQ(wh) \ (((wh)->i_fc[0] & \ (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_QOS)) == \ (IEEE80211_FC0_TYPE_DATA | IEEE80211_FC0_SUBTYPE_QOS)) #define WME_QOSINFO_COUNT 0x0f /* Mask for Param Set Count field */ /* * WME/802.11e information element. */ struct ieee80211_ie_wme { a_uint8_t wme_id; /* IEEE80211_ELEMID_VENDOR */ a_uint8_t wme_len; /* length in bytes */ a_uint8_t wme_oui[3]; /* 0x00, 0x50, 0xf2 */ a_uint8_t wme_type; /* OUI type */ a_uint8_t wme_subtype; /* OUI subtype */ a_uint8_t wme_version; /* spec revision */ a_uint8_t wme_info; /* QoS info */ } adf_os_packed; /* * WME/802.11e Tspec Element */ struct ieee80211_wme_tspec { a_uint8_t ts_id; a_uint8_t ts_len; a_uint8_t ts_oui[3]; a_uint8_t ts_oui_type; a_uint8_t ts_oui_subtype; a_uint8_t ts_version; a_uint8_t ts_tsinfo[3]; a_uint8_t ts_nom_msdu[2]; a_uint8_t ts_max_msdu[2]; a_uint8_t ts_min_svc[4]; a_uint8_t ts_max_svc[4]; a_uint8_t ts_inactv_intv[4]; a_uint8_t ts_susp_intv[4]; a_uint8_t ts_start_svc[4]; a_uint8_t ts_min_rate[4]; a_uint8_t ts_mean_rate[4]; a_uint8_t ts_max_burst[4]; a_uint8_t ts_min_phy[4]; a_uint8_t ts_peak_rate[4]; a_uint8_t ts_delay[4]; a_uint8_t ts_surplus[2]; a_uint8_t ts_medium_time[2]; } adf_os_packed; /* * WME AC parameter field */ struct ieee80211_wme_acparams { a_uint8_t acp_aci_aifsn; a_uint8_t acp_logcwminmax; a_uint16_t acp_txop; } adf_os_packed; #define IEEE80211_WME_PARAM_LEN 24 #define WME_NUM_AC 4 /* 4 AC categories */ #define WME_PARAM_ACI 0x60 /* Mask for ACI field */ #define WME_PARAM_ACI_S 5 /* Shift for ACI field */ #define WME_PARAM_ACM 0x10 /* Mask for ACM bit */ #define WME_PARAM_ACM_S 4 /* Shift for ACM bit */ #define WME_PARAM_AIFSN 0x0f /* Mask for aifsn field */ #define WME_PARAM_AIFSN_S 0 /* Shift for aifsn field */ #define WME_PARAM_LOGCWMIN 0x0f /* Mask for CwMin field (in log) */ #define WME_PARAM_LOGCWMIN_S 0 /* Shift for CwMin field */ #define WME_PARAM_LOGCWMAX 0xf0 /* Mask for CwMax field (in log) */ #define WME_PARAM_LOGCWMAX_S 4 /* Shift for CwMax field */ #define WME_AC_TO_TID(_ac) ( \ ((_ac) == WME_AC_VO) ? 6 : \ ((_ac) == WME_AC_VI) ? 5 : \ ((_ac) == WME_AC_BK) ? 1 : \ 0) #define TID_TO_WME_AC(_tid) ( \ (((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \ (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \ (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \ WME_AC_VO) /* * WME Parameter Element */ struct ieee80211_wme_param { a_uint8_t param_id; a_uint8_t param_len; a_uint8_t param_oui[3]; a_uint8_t param_oui_type; a_uint8_t param_oui_sybtype; a_uint8_t param_version; a_uint8_t param_qosInfo; a_uint8_t param_reserved; struct ieee80211_wme_acparams params_acParams[WME_NUM_AC]; } adf_os_packed; /* * WME U-APSD qos info field defines */ #define WME_CAPINFO_UAPSD_EN 0x00000080 #define WME_CAPINFO_UAPSD_VO 0x00000001 #define WME_CAPINFO_UAPSD_VI 0x00000002 #define WME_CAPINFO_UAPSD_BK 0x00000004 #define WME_CAPINFO_UAPSD_BE 0x00000008 #define WME_CAPINFO_UAPSD_ACFLAGS_SHIFT 0 #define WME_CAPINFO_UAPSD_ACFLAGS_MASK 0xF #define WME_CAPINFO_UAPSD_MAXSP_SHIFT 5 #define WME_CAPINFO_UAPSD_MAXSP_MASK 0x3 #define WME_CAPINFO_IE_OFFSET 8 #define WME_UAPSD_MAXSP(_qosinfo) (((_qosinfo) >> WME_CAPINFO_UAPSD_MAXSP_SHIFT) & WME_CAPINFO_UAPSD_MAXSP_MASK) #define WME_UAPSD_AC_ENABLED(_ac, _qosinfo) ( (1<<(3 - (_ac))) & \ (((_qosinfo) >> WME_CAPINFO_UAPSD_ACFLAGS_SHIFT) & WME_CAPINFO_UAPSD_ACFLAGS_MASK) ) /* * Atheros Advanced Capability information element. */ struct ieee80211_ie_athAdvCap { a_uint8_t athAdvCap_id; /* IEEE80211_ELEMID_VENDOR */ a_uint8_t athAdvCap_len; /* length in bytes */ a_uint8_t athAdvCap_oui[3]; /* 0x00, 0x03, 0x7f */ a_uint8_t athAdvCap_type; /* OUI type */ a_uint8_t athAdvCap_subtype; /* OUI subtype */ a_uint8_t athAdvCap_version; /* spec revision */ a_uint8_t athAdvCap_capability; /* Capability info */ a_uint16_t athAdvCap_defKeyIndex; } adf_os_packed; /* * Atheros Extended Capability information element. */ struct ieee80211_ie_ath_extcap { a_uint8_t ath_extcap_id; /* IEEE80211_ELEMID_VENDOR */ a_uint8_t ath_extcap_len; /* length in bytes */ a_uint8_t ath_extcap_oui[3]; /* 0x00, 0x03, 0x7f */ a_uint8_t ath_extcap_type; /* OUI type */ a_uint8_t ath_extcap_subtype; /* OUI subtype */ a_uint8_t ath_extcap_version; /* spec revision */ a_uint32_t ath_extcap_data; /* Data */ } adf_os_packed; /* * Atheros XR information element. */ struct ieee80211_xr_param { a_uint8_t param_id; a_uint8_t param_len; a_uint8_t param_oui[3]; a_uint8_t param_oui_type; a_uint8_t param_oui_sybtype; a_uint8_t param_version; a_uint8_t param_Info; a_uint8_t param_base_bssid[IEEE80211_ADDR_LEN]; a_uint8_t param_xr_bssid[IEEE80211_ADDR_LEN]; a_uint16_t param_xr_beacon_interval; a_uint8_t param_base_ath_capability; a_uint8_t param_xr_ath_capability; } adf_os_packed; /* * Management Action Frames */ /* generic frame format */ struct ieee80211_action { a_uint8_t ia_category; a_uint8_t ia_action; } adf_os_packed; /* categories */ #define IEEE80211_ACTION_CAT_QOS 0 /* qos */ #define IEEE80211_ACTION_CAT_BA 3 /* BA */ #define IEEE80211_ACTION_CAT_HT 7 /* HT per IEEE802.11n-D1.06 */ /* HT actions */ #define IEEE80211_ACTION_HT_TXCHWIDTH 0 /* recommended transmission channel width */ #define IEEE80211_ACTION_HT_SMPOWERSAVE 1 /* Spatial Multiplexing (SM) Power Save */ /* HT - recommended transmission channel width */ struct ieee80211_action_ht_txchwidth { struct ieee80211_action at_header; a_uint8_t at_chwidth; } adf_os_packed; #define IEEE80211_A_HT_TXCHWIDTH_20 0 #define IEEE80211_A_HT_TXCHWIDTH_2040 1 /* HT - Spatial Multiplexing (SM) Power Save */ struct ieee80211_action_ht_smpowersave { struct ieee80211_action as_header; a_uint8_t as_control; } adf_os_packed; /* values defined for 'as_control' field per 802.11n-D1.06 */ #define IEEE80211_A_HT_SMPOWERSAVE_DISABLED 0x00 /* SM Power Save Disabled, SM packets ok */ #define IEEE80211_A_HT_SMPOWERSAVE_ENABLED 0x01 /* SM Power Save Enabled bit */ #define IEEE80211_A_HT_SMPOWERSAVE_MODE 0x02 /* SM Power Save Mode bit */ #define IEEE80211_A_HT_SMPOWERSAVE_RESERVED 0xFC /* SM Power Save Reserved bits */ /* values defined for SM Power Save Mode bit */ #define IEEE80211_A_HT_SMPOWERSAVE_STATIC 0x00 /* Static, SM packets not ok */ #define IEEE80211_A_HT_SMPOWERSAVE_DYNAMIC 0x02 /* Dynamic, SM packets ok if preceded by RTS */ /* BA actions */ #define IEEE80211_ACTION_BA_ADDBA_REQUEST 0 /* ADDBA request */ #define IEEE80211_ACTION_BA_ADDBA_RESPONSE 1 /* ADDBA response */ #define IEEE80211_ACTION_BA_DELBA 2 /* DELBA */ struct ieee80211_ba_parameterset { #if _BYTE_ORDER == _BIG_ENDIAN a_uint16_t buffersize : 10, /* B6-15 buffer size */ tid : 4, /* B2-5 TID */ bapolicy : 1, /* B1 block ack policy */ reserved0 : 1; /* B0 reserved */ #else a_uint16_t reserved0 : 1, /* B0 reserved */ bapolicy : 1, /* B1 block ack policy */ tid : 4, /* B2-5 TID */ buffersize : 10; /* B6-15 buffer size */ #endif } adf_os_packed; #define IEEE80211_BA_POLICY_DELAYED 0 #define IEEE80211_BA_POLICY_IMMEDIATE 1 struct ieee80211_ba_seqctrl { a_uint16_t startseq; } adf_os_packed; struct ieee80211_delba_parameterset { #if _BYTE_ORDER == _BIG_ENDIAN a_uint16_t tid : 4, /* B12-15 tid */ initiator : 1, /* B11 initiator */ reserved0 : 11; /* B0-10 reserved */ #else a_uint16_t reserved0 : 11, /* B0-10 reserved */ initiator : 1, /* B11 initiator */ tid : 4; /* B12-15 tid */ #endif } adf_os_packed; /* BA - ADDBA request */ struct ieee80211_action_ba_addbarequest { struct ieee80211_action rq_header; a_uint8_t rq_dialogtoken; struct ieee80211_ba_parameterset rq_baparamset; a_uint16_t rq_batimeout; /* in TUs */ struct ieee80211_ba_seqctrl rq_basequencectrl; } adf_os_packed; /* BA - ADDBA response */ struct ieee80211_action_ba_addbaresponse { struct ieee80211_action rs_header; a_uint8_t rs_dialogtoken; a_uint16_t rs_statuscode; struct ieee80211_ba_parameterset rs_baparamset; a_uint16_t rs_batimeout; /* in TUs */ } adf_os_packed; /* BA - DELBA */ struct ieee80211_action_ba_delba { struct ieee80211_action dl_header; struct ieee80211_delba_parameterset dl_delbaparamset; a_uint16_t dl_reasoncode; } adf_os_packed; /* * Control frames. */ struct ieee80211_frame_min { a_uint8_t i_fc[2]; a_uint8_t i_dur[2]; a_uint8_t i_addr1[IEEE80211_ADDR_LEN]; a_uint8_t i_addr2[IEEE80211_ADDR_LEN]; /* FCS */ } adf_os_packed; /* * BAR frame format */ #define IEEE80211_BAR_CTL_TID_M 0xF000 /* tid mask */ #define IEEE80211_BAR_CTL_TID_S 12 /* tid shift */ #define IEEE80211_BAR_CTL_NOACK 0x0001 /* no-ack policy */ #define IEEE80211_BAR_CTL_COMBA 0x0004 /* compressed block-ack */ struct ieee80211_frame_bar { a_uint8_t i_fc[2]; a_uint8_t i_dur[2]; a_uint8_t i_ra[IEEE80211_ADDR_LEN]; a_uint8_t i_ta[IEEE80211_ADDR_LEN]; a_uint16_t i_ctl; a_uint16_t i_seq; /* FCS */ } adf_os_packed; struct ieee80211_frame_rts { a_uint8_t i_fc[2]; a_uint8_t i_dur[2]; a_uint8_t i_ra[IEEE80211_ADDR_LEN]; a_uint8_t i_ta[IEEE80211_ADDR_LEN]; /* FCS */ } adf_os_packed; struct ieee80211_frame_cts { a_uint8_t i_fc[2]; a_uint8_t i_dur[2]; a_uint8_t i_ra[IEEE80211_ADDR_LEN]; /* FCS */ } adf_os_packed; struct ieee80211_frame_ack { a_uint8_t i_fc[2]; a_uint8_t i_dur[2]; a_uint8_t i_ra[IEEE80211_ADDR_LEN]; /* FCS */ } adf_os_packed; struct ieee80211_frame_pspoll { a_uint8_t i_fc[2]; a_uint8_t i_aid[2]; a_uint8_t i_bssid[IEEE80211_ADDR_LEN]; a_uint8_t i_ta[IEEE80211_ADDR_LEN]; /* FCS */ } adf_os_packed; struct ieee80211_frame_cfend { /* NB: also CF-End+CF-Ack */ a_uint8_t i_fc[2]; a_uint8_t i_dur[2]; /* should be zero */ a_uint8_t i_ra[IEEE80211_ADDR_LEN]; a_uint8_t i_bssid[IEEE80211_ADDR_LEN]; /* FCS */ } adf_os_packed; /* * BEACON management packets * * octet timestamp[8] * octet beacon interval[2] * octet capability information[2] * information element * octet elemid * octet length * octet information[length] */ typedef a_uint8_t *ieee80211_mgt_beacon_t; #define IEEE80211_BEACON_INTERVAL(beacon) \ ((beacon)[8] | ((beacon)[9] << 8)) #define IEEE80211_BEACON_CAPABILITY(beacon) \ ((beacon)[10] | ((beacon)[11] << 8)) #define IEEE80211_CAPINFO_ESS 0x0001 #define IEEE80211_CAPINFO_IBSS 0x0002 #define IEEE80211_CAPINFO_CF_POLLABLE 0x0004 #define IEEE80211_CAPINFO_CF_POLLREQ 0x0008 #define IEEE80211_CAPINFO_PRIVACY 0x0010 #define IEEE80211_CAPINFO_SHORT_PREAMBLE 0x0020 #define IEEE80211_CAPINFO_PBCC 0x0040 #define IEEE80211_CAPINFO_CHNL_AGILITY 0x0080 /* bits 8-9 are reserved (8 now for specturm management) */ #define IEEE80211_CAPINFO_SPECTRUM_MGMT 0x0100 #define IEEE80211_CAPINFO_SHORT_SLOTTIME 0x0400 #define IEEE80211_CAPINFO_RSN 0x0800 /* bit 12 is reserved */ #define IEEE80211_CAPINFO_DSSSOFDM 0x2000 /* bits 14-15 are reserved */ /* * 802.11i/WPA information element (maximally sized). */ struct ieee80211_ie_wpa { a_uint8_t wpa_id; /* IEEE80211_ELEMID_VENDOR */ a_uint8_t wpa_len; /* length in bytes */ a_uint8_t wpa_oui[3]; /* 0x00, 0x50, 0xf2 */ a_uint8_t wpa_type; /* OUI type */ a_uint16_t wpa_version; /* spec revision */ a_uint32_t wpa_mcipher[1]; /* multicast/group key cipher */ a_uint16_t wpa_uciphercnt; /* # pairwise key ciphers */ a_uint32_t wpa_uciphers[8];/* ciphers */ a_uint16_t wpa_authselcnt; /* authentication selector cnt*/ a_uint32_t wpa_authsels[8];/* selectors */ a_uint16_t wpa_caps; /* 802.11i capabilities */ a_uint16_t wpa_pmkidcnt; /* 802.11i pmkid count */ a_uint16_t wpa_pmkids[8]; /* 802.11i pmkids */ } adf_os_packed; #ifndef _BYTE_ORDER #error "Don't know native byte order" #endif #ifndef IEEE80211N_IE /* Temporary vendor specific IE for 11n pre-standard interoperability */ #define HT_OUI 0x4c9000 #endif struct ieee80211_ie_htcap_cmn { a_uint16_t hc_cap; /* HT capabilities */ #if _BYTE_ORDER == _BIG_ENDIAN a_uint8_t hc_reserved : 3, /* B5-7 reserved */ hc_mpdudensity : 3, /* B2-4 MPDU density (aka Minimum MPDU Start Spacing) */ hc_maxampdu : 2; /* B0-1 maximum rx A-MPDU factor */ #else a_uint8_t hc_maxampdu : 2, /* B0-1 maximum rx A-MPDU factor */ hc_mpdudensity : 3, /* B2-4 MPDU density (aka Minimum MPDU Start Spacing) */ hc_reserved : 3; /* B5-7 reserved */ #endif a_uint8_t hc_mcsset[16]; /* supported MCS set */ a_uint16_t hc_extcap; /* extended HT capabilities */ a_uint32_t hc_txbf; /* txbf capabilities */ a_uint8_t hc_antenna; /* antenna capabilities */ } adf_os_packed; /* * 802.11n HT Capability IE */ struct ieee80211_ie_htcap { a_uint8_t hc_id; /* element ID */ a_uint8_t hc_len; /* length in bytes */ struct ieee80211_ie_htcap_cmn hc_ie; } adf_os_packed; /* * Temporary vendor private HT Capability IE */ struct vendor_ie_htcap { a_uint8_t hc_id; /* element ID */ a_uint8_t hc_len; /* length in bytes */ a_uint8_t hc_oui[3]; a_uint8_t hc_ouitype; struct ieee80211_ie_htcap_cmn hc_ie; } adf_os_packed; /* HT capability flags */ #define IEEE80211_HTCAP_C_ADVCODING 0x0001 #define IEEE80211_HTCAP_C_CHWIDTH40 0x0002 #define IEEE80211_HTCAP_C_SMPOWERSAVE_STATIC 0x0000 /* Capable of SM Power Save (Static) */ #define IEEE80211_HTCAP_C_SMPOWERSAVE_DYNAMIC 0x0004 /* Capable of SM Power Save (Dynamic) */ #define IEEE80211_HTCAP_C_SM_RESERVED 0x0008 /* Reserved */ #define IEEE80211_HTCAP_C_SM_ENABLED 0x000c /* SM enabled, no SM Power Save */ #define IEEE80211_HTCAP_C_GREENFIELD 0x0010 #define IEEE80211_HTCAP_C_SHORTGI20 0x0020 #define IEEE80211_HTCAP_C_SHORTGI40 0x0040 #define IEEE80211_HTCAP_C_TXSTBC 0x0080 #define IEEE80211_HTCAP_C_RXSTBC 0x0100 /* 2 bits */ #define IEEE80211_HTCAP_C_DELAYEDBLKACK 0x0400 #define IEEE80211_HTCAP_C_MAXAMSDUSIZE 0x0800 /* 1 = 8K, 0 = 3839B */ #define IEEE80211_HTCAP_C_DSSSCCK40 0x1000 #define IEEE80211_HTCAP_C_PSMP 0x2000 #define IEEE80211_HTCAP_C_INTOLERANT40 0x4000 #define IEEE80211_HTCAP_C_LSIGTXOPPROT 0x8000 #define IEEE80211_HTCAP_C_SM_MASK 0x000c /* Spatial Multiplexing (SM) capabitlity bitmask */ /* B0-1 maximum rx A-MPDU factor 2^(13+Max Rx A-MPDU Factor) */ enum { IEEE80211_HTCAP_MAXRXAMPDU_8192, /* 2 ^ 13 */ IEEE80211_HTCAP_MAXRXAMPDU_16384, /* 2 ^ 14 */ IEEE80211_HTCAP_MAXRXAMPDU_32768, /* 2 ^ 15 */ IEEE80211_HTCAP_MAXRXAMPDU_65536, /* 2 ^ 16 */ }; #define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13 /* B2-4 MPDU density (usec) */ enum { IEEE80211_HTCAP_MPDUDENSITY_NA, /* No time restriction */ IEEE80211_HTCAP_MPDUDENSITY_0_25, /* 1/4 usec */ IEEE80211_HTCAP_MPDUDENSITY_0_5, /* 1/2 usec */ IEEE80211_HTCAP_MPDUDENSITY_1, /* 1 usec */ IEEE80211_HTCAP_MPDUDENSITY_2, /* 2 usec */ IEEE80211_HTCAP_MPDUDENSITY_4, /* 4 usec */ IEEE80211_HTCAP_MPDUDENSITY_8, /* 8 usec */ IEEE80211_HTCAP_MPDUDENSITY_16, /* 16 usec */ }; /* HT extended capability flags */ #define IEEE80211_HTCAP_EXTC_PCO 0x0001 #define IEEE80211_HTCAP_EXTC_TRANS_TIME_RSVD 0x0000 #define IEEE80211_HTCAP_EXTC_TRANS_TIME_400 0x0002 /* 20-40 switch time */ #define IEEE80211_HTCAP_EXTC_TRANS_TIME_1500 0x0004 /* in us */ #define IEEE80211_HTCAP_EXTC_TRANS_TIME_5000 0x0006 #define IEEE80211_HTCAP_EXTC_RSVD_1 0x00f8 #define IEEE80211_HTCAP_EXTC_MCS_FEEDBACK_NONE 0x0000 #define IEEE80211_HTCAP_EXTC_MCS_FEEDBACK_RSVD 0x0100 #define IEEE80211_HTCAP_EXTC_MCS_FEEDBACK_UNSOL 0x0200 #define IEEE80211_HTCAP_EXTC_MCS_FEEDBACK_FULL 0x0300 #define IEEE80211_HTCAP_EXTC_RSVD_2 0xfc00 struct ieee80211_ie_htinfo_cmn { a_uint8_t hi_ctrlchannel; /* control channel */ #if _BYTE_ORDER == _BIG_ENDIAN a_uint8_t hi_serviceinterval : 3, /* B5-7 svc interval granularity */ hi_ctrlaccess : 1, /* B4 controlled access only */ hi_rifsmode : 1, /* B3 rifs mode */ hi_txchwidth : 1, /* B2 recommended xmiss width set */ hi_extchoff : 2; /* B0-1 extension channel offset */ #else a_uint8_t hi_extchoff : 2, /* B0-1 extension channel offset */ hi_txchwidth : 1, /* B2 recommended xmiss width set */ hi_rifsmode : 1, /* B3 rifs mode */ hi_ctrlaccess : 1, /* B4 controlled access only */ hi_serviceinterval : 3; /* B5-7 svc interval granularity */ #endif #if _BYTE_ORDER == _BIG_ENDIAN a_uint8_t hi_reserved0 : 3, /* B5-7 Reserved */ hi_obssnonhtpresent: 1, /* B4 OBSS Non-HT STAs Present */ hi_txburstlimit : 1, /* B3 Transmit Burst Limit */ hi_nongfpresent : 1, /* B2 Non-greenfield STAs present */ hi_opmode : 2; /* B0-1 Operating Mode */ #else a_uint8_t hi_opmode : 2, /* B0-1 Operating Mode */ hi_nongfpresent : 1, /* B2 Non-greenfield STAs present */ hi_txburstlimit : 1, /* B3 Transmit Burst Limit */ hi_obssnonhtpresent: 1, /* B4 OBSS Non-HT STAs Present */ hi_reserved0 : 3; /* B5-7 Reserved */ #endif a_uint8_t hi_reserved1; a_uint16_t hi_miscflags; a_uint8_t hi_basicmcsset[16]; /* basic MCS set */ } adf_os_packed; /* * 802.11n HT Information IE */ struct ieee80211_ie_htinfo { a_uint8_t hi_id; /* element ID */ a_uint8_t hi_len; /* length in bytes */ struct ieee80211_ie_htinfo_cmn hi_ie; } adf_os_packed; /* * Temporary vendor private HT Information IE */ struct vendor_ie_htinfo { a_uint8_t hi_id; /* element ID */ a_uint8_t hi_len; /* length in bytes */ a_uint8_t hi_oui[3]; a_uint8_t hi_ouitype; struct ieee80211_ie_htinfo_cmn hi_ie; } adf_os_packed; /* extension channel offset (2 bit signed number) */ enum { IEEE80211_HTINFO_EXTOFFSET_NA = 0, /* 0 no extension channel is present */ IEEE80211_HTINFO_EXTOFFSET_ABOVE = 1, /* +1 extension channel above control channel */ IEEE80211_HTINFO_EXTOFFSET_UNDEF = 2, /* -2 undefined */ IEEE80211_HTINFO_EXTOFFSET_BELOW = 3 /* -1 extension channel below control channel*/ }; /* recommended transmission width set */ enum { IEEE80211_HTINFO_TXWIDTH_20, IEEE80211_HTINFO_TXWIDTH_2040 }; /* operating flags */ #define IEEE80211_HTINFO_OPMODE_PURE 0x00 /* no protection */ #define IEEE80211_HTINFO_OPMODE_MIXED_PROT_OPT 0x01 /* prot optional (legacy device maybe present) */ #define IEEE80211_HTINFO_OPMODE_MIXED_PROT_40 0x02 /* prot required (20 MHz) */ #define IEEE80211_HTINFO_OPMODE_MIXED_PROT_ALL 0x03 /* prot required (legacy devices present) */ #define IEEE80211_HTINFO_OPMODE_MASK 0x03 /* For protection 0x00-0x03 */ /* Non-greenfield STAs present */ enum { IEEE80211_HTINFO_NON_GF_NOT_PRESENT, /* Non-greenfield STAs not present */ IEEE80211_HTINFO_NON_GF_PRESENT, /* Non-greenfield STAs present */ }; /* Transmit Burst Limit */ enum { IEEE80211_HTINFO_TXBURST_UNLIMITED, /* Transmit Burst is unlimited */ IEEE80211_HTINFO_TXBURST_LIMITED, /* Transmit Burst is limited */ }; /* OBSS Non-HT STAs present */ enum { IEEE80211_HTINFO_OBBSS_NONHT_NOT_PRESENT, /* OBSS Non-HT STAs not present */ IEEE80211_HTINFO_OBBSS_NONHT_PRESENT, /* OBSS Non-HT STAs present */ }; /* misc flags */ #define IEEE80211_HTINFO_BASICSTBCMCS 0x007F /* B0-6 basic STBC MCS */ #define IEEE80211_HTINFO_DUALSTBCPROT 0x0080 /* B7 dual stbc protection */ #define IEEE80211_HTINFO_SECONDARYBEACON 0x0100 /* B8 secondary beacon */ #define IEEE80211_HTINFO_LSIGTXOPPROT 0x0200 /* B9 lsig txop prot full support */ #define IEEE80211_HTINFO_PCOACTIVE 0x0400 /* B10 pco active */ #define IEEE80211_HTINFO_PCOPHASE 0x0800 /* B11 pco phase */ /* RIFS mode */ enum { IEEE80211_HTINFO_RIFSMODE_PROHIBITED, /* use of rifs prohibited */ IEEE80211_HTINFO_RIFSMODE_ALLOWED, /* use of rifs permitted */ }; /* * Management information element payloads. */ enum { IEEE80211_ELEMID_SSID = 0, IEEE80211_ELEMID_RATES = 1, IEEE80211_ELEMID_FHPARMS = 2, IEEE80211_ELEMID_DSPARMS = 3, IEEE80211_ELEMID_CFPARMS = 4, IEEE80211_ELEMID_TIM = 5, IEEE80211_ELEMID_IBSSPARMS = 6, IEEE80211_ELEMID_COUNTRY = 7, IEEE80211_ELEMID_REQINFO = 10, IEEE80211_ELEMID_CHALLENGE = 16, /* 17-31 reserved for challenge text extension */ IEEE80211_ELEMID_PWRCNSTR = 32, IEEE80211_ELEMID_PWRCAP = 33, IEEE80211_ELEMID_TPCREQ = 34, IEEE80211_ELEMID_TPCREP = 35, IEEE80211_ELEMID_SUPPCHAN = 36, IEEE80211_ELEMID_CHANSWITCHANN = 37, IEEE80211_ELEMID_MEASREQ = 38, IEEE80211_ELEMID_MEASREP = 39, IEEE80211_ELEMID_QUIET = 40, IEEE80211_ELEMID_IBSSDFS = 41, IEEE80211_ELEMID_ERP = 42, IEEE80211_ELEMID_HTCAP_ANA = 45, IEEE80211_ELEMID_RSN = 48, IEEE80211_ELEMID_XRATES = 50, IEEE80211_ELEMID_HTCAP = 51, IEEE80211_ELEMID_HTINFO = 52, IEEE80211_ELEMID_EXTCHANSWITCHANN = 60, /* Fix this later as per ANA definition */ IEEE80211_ELEMID_HTINFO_ANA = 61, IEEE80211_ELEMID_TPC = 150, IEEE80211_ELEMID_CCKM = 156, IEEE80211_ELEMID_VENDOR = 221, /* vendor private */ }; #define IEEE80211_CHANSWITCHANN_BYTES 5 #define IEEE80211_EXTCHANSWITCHANN_BYTES 6 struct ieee80211_tim_ie { a_uint8_t tim_ie; /* IEEE80211_ELEMID_TIM */ a_uint8_t tim_len; a_uint8_t tim_count; /* DTIM count */ a_uint8_t tim_period; /* DTIM period */ a_uint8_t tim_bitctl; /* bitmap control */ a_uint8_t tim_bitmap[1]; /* variable-length bitmap */ } adf_os_packed; struct ieee80211_country_ie { a_uint8_t ie; /* IEEE80211_ELEMID_COUNTRY */ a_uint8_t len; a_uint8_t cc[3]; /* ISO CC+(I)ndoor/(O)utdoor */ struct { a_uint8_t schan; /* starting channel */ a_uint8_t nchan; /* number channels */ a_uint8_t maxtxpwr; /* tx power cap */ } adf_os_packed band[4]; /* up to 4 sub bands */ } adf_os_packed; #define IEEE80211_CHALLENGE_LEN 128 #define IEEE80211_SUPPCHAN_LEN 26 #define IEEE80211_RATE_BASIC 0x80 #define IEEE80211_RATE_VAL 0x7f /* EPR information element flags */ #define IEEE80211_ERP_NON_ERP_PRESENT 0x01 #define IEEE80211_ERP_USE_PROTECTION 0x02 #define IEEE80211_ERP_LONG_PREAMBLE 0x04 /* Atheros private advanced capabilities info */ #define ATHEROS_CAP_TURBO_PRIME 0x01 #define ATHEROS_CAP_COMPRESSION 0x02 #define ATHEROS_CAP_FAST_FRAME 0x04 /* bits 3-6 reserved */ #define ATHEROS_CAP_BOOST 0x80 #define ATH_OUI 0x7f0300 /* Atheros OUI */ #define ATH_OUI_TYPE 0x01 #define ATH_OUI_SUBTYPE 0x01 #define ATH_OUI_VERSION 0x00 #define ATH_OUI_TYPE_XR 0x03 #define ATH_OUI_VER_XR 0x01 #define ATH_OUI_EXTCAP_TYPE 0x04 /* Atheros Extended Cap Type */ #define ATH_OUI_EXTCAP_SUBTYPE 0x01 /* Atheros Extended Cap Sub-type */ #define ATH_OUI_EXTCAP_VERSION 0x00 /* Atheros Extended Cap Version */ #define WPA_OUI 0xf25000 #define WPA_OUI_TYPE 0x01 #define WPA_VERSION 1 /* current supported version */ #define WSC_OUI 0x0050f204 #define WPA_CSE_NULL 0x00 #define WPA_CSE_WEP40 0x01 #define WPA_CSE_TKIP 0x02 #define WPA_CSE_CCMP 0x04 #define WPA_CSE_WEP104 0x05 #define WPA_ASE_NONE 0x00 #define WPA_ASE_8021X_UNSPEC 0x01 #define WPA_ASE_8021X_PSK 0x02 #define RSN_OUI 0xac0f00 #define RSN_VERSION 1 /* current supported version */ #define RSN_CSE_NULL 0x00 #define RSN_CSE_WEP40 0x01 #define RSN_CSE_TKIP 0x02 #define RSN_CSE_WRAP 0x03 #define RSN_CSE_CCMP 0x04 #define RSN_CSE_WEP104 0x05 #define RSN_ASE_NONE 0x00 #define RSN_ASE_8021X_UNSPEC 0x01 #define RSN_ASE_8021X_PSK 0x02 #define RSN_CAP_PREAUTH 0x01 #define WME_OUI 0xf25000 #define WME_OUI_TYPE 0x02 #define WME_INFO_OUI_SUBTYPE 0x00 #define WME_PARAM_OUI_SUBTYPE 0x01 #define WME_VERSION 1 /* WME stream classes */ #define WME_AC_BE 0 /* best effort */ #define WME_AC_BK 1 /* background */ #define WME_AC_VI 2 /* video */ #define WME_AC_VO 3 /* voice */ /* * AUTH management packets * * octet algo[2] * octet seq[2] * octet status[2] * octet chal.id * octet chal.length * octet chal.text[253] */ typedef a_uint8_t *ieee80211_mgt_auth_t; #define IEEE80211_AUTH_ALGORITHM(auth) \ ((auth)[0] | ((auth)[1] << 8)) #define IEEE80211_AUTH_TRANSACTION(auth) \ ((auth)[2] | ((auth)[3] << 8)) #define IEEE80211_AUTH_STATUS(auth) \ ((auth)[4] | ((auth)[5] << 8)) #define IEEE80211_AUTH_ALG_OPEN 0x0000 #define IEEE80211_AUTH_ALG_SHARED 0x0001 #define IEEE80211_AUTH_ALG_LEAP 0x0080 enum { IEEE80211_AUTH_OPEN_REQUEST = 1, IEEE80211_AUTH_OPEN_RESPONSE = 2, }; enum { IEEE80211_AUTH_SHARED_REQUEST = 1, IEEE80211_AUTH_SHARED_CHALLENGE = 2, IEEE80211_AUTH_SHARED_RESPONSE = 3, IEEE80211_AUTH_SHARED_PASS = 4, }; /* * Reason codes * * Unlisted codes are reserved */ enum { IEEE80211_REASON_UNSPECIFIED = 1, IEEE80211_REASON_AUTH_EXPIRE = 2, IEEE80211_REASON_AUTH_LEAVE = 3, IEEE80211_REASON_ASSOC_EXPIRE = 4, IEEE80211_REASON_ASSOC_TOOMANY = 5, IEEE80211_REASON_NOT_AUTHED = 6, IEEE80211_REASON_NOT_ASSOCED = 7, IEEE80211_REASON_ASSOC_LEAVE = 8, IEEE80211_REASON_ASSOC_NOT_AUTHED = 9, IEEE80211_REASON_RSN_REQUIRED = 11, IEEE80211_REASON_RSN_INCONSISTENT = 12, IEEE80211_REASON_IE_INVALID = 13, IEEE80211_REASON_MIC_FAILURE = 14, IEEE80211_STATUS_SUCCESS = 0, IEEE80211_STATUS_UNSPECIFIED = 1, IEEE80211_STATUS_CAPINFO = 10, IEEE80211_STATUS_NOT_ASSOCED = 11, IEEE80211_STATUS_OTHER = 12, IEEE80211_STATUS_ALG = 13, IEEE80211_STATUS_SEQUENCE = 14, IEEE80211_STATUS_CHALLENGE = 15, IEEE80211_STATUS_TIMEOUT = 16, IEEE80211_STATUS_TOOMANY = 17, IEEE80211_STATUS_BASIC_RATE = 18, IEEE80211_STATUS_SP_REQUIRED = 19, IEEE80211_STATUS_PBCC_REQUIRED = 20, IEEE80211_STATUS_CA_REQUIRED = 21, IEEE80211_STATUS_TOO_MANY_STATIONS = 22, IEEE80211_STATUS_RATES = 23, IEEE80211_STATUS_SHORTSLOT_REQUIRED = 25, IEEE80211_STATUS_DSSSOFDM_REQUIRED = 26, IEEE80211_STATUS_REFUSED = 37, IEEE80211_STATUS_INVALID_PARAM = 38, }; #define IEEE80211_WEP_KEYLEN 5 /* 40bit */ #define IEEE80211_WEP_IVLEN 3 /* 24bit */ #define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ #define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ #define IEEE80211_WEP_NKID 4 /* number of key ids */ /* * 802.11i defines an extended IV for use with non-WEP ciphers. * When the EXTIV bit is set in the key id byte an additional * 4 bytes immediately follow the IV for TKIP. For CCMP the * EXTIV bit is likewise set but the 8 bytes represent the * CCMP header rather than IV+extended-IV. */ #define IEEE80211_WEP_EXTIV 0x20 #define IEEE80211_WEP_EXTIVLEN 4 /* extended IV length */ #define IEEE80211_WEP_MICLEN 8 /* trailing MIC */ #define IEEE80211_WEP_ICVLEN 4 #define IEEE80211_WAPI_MICLEN 16 /* trailing MIC */ #define IEEE80211_WAPI_IVLEN 16 #define IEEE80211_CRC_LEN 4 /* * Maximum acceptable MTU is: * IEEE80211_MAX_LEN - WEP overhead - CRC - * QoS overhead - RSN/WPA overhead * Min is arbitrarily chosen > IEEE80211_MIN_LEN. The default * mtu is Ethernet-compatible; it's set by ether_ifattach. */ #define IEEE80211_MTU_MAX 2290 #define IEEE80211_MTU_MIN 32 #define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) #define IEEE80211_ACK_LEN \ (sizeof(struct ieee80211_frame_ack) + IEEE80211_CRC_LEN) #define IEEE80211_MIN_LEN \ (sizeof(struct ieee80211_frame_min) + IEEE80211_CRC_LEN) /* An 802.11 data frame can be one of three types: 1. An unaggregated frame: The maximum length of an unaggregated data frame is 2324 bytes + headers. 2. A data frame that is part of an AMPDU: The maximum length of an AMPDU may be upto 65535 bytes, but data frame is limited to 2324 bytes + header. 3. An AMSDU: The maximum length of an AMSDU is eihther 3839 or 7095 bytes. The maximum frame length supported by hardware is 4095 bytes. A length of 3839 bytes is chosen here to support unaggregated data frames, any size AMPDUs and 3839 byte AMSDUs. */ #define IEEE80211N_MAX_FRAMELEN 3839 #define IEEE80211N_MAX_LEN (IEEE80211N_MAX_FRAMELEN + IEEE80211_CRC_LEN + \ (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) #define IEEE80211_TX_CHAINMASK_MIN 1 #define IEEE80211_TX_CHAINMASK_MAX 7 #define IEEE80211_RX_CHAINMASK_MIN 1 #define IEEE80211_RX_CHAINMASK_MAX 7 /* * The 802.11 spec says at most 2007 stations may be * associated at once. For most AP's this is way more * than is feasible so we use a default of 128. This * number may be overridden by the driver and/or by * user configuration. */ #define IEEE80211_AID_MAX 2007 #define IEEE80211_AID_DEF 128 #define IEEE80211_AID(b) ((b) &~ 0xc000) /* * RTS frame length parameters. The default is specified in * the 802.11 spec. The max may be wrong for jumbo frames. */ #define IEEE80211_RTS_DEFAULT 512 #define IEEE80211_RTS_MIN 1 #define IEEE80211_RTS_MAX 2346 /* * Regulatory extention identifier for country IE. */ #define IEEE80211_REG_EXT_ID 201 #endif /* _NET80211_IEEE80211_H_ */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/ieee80211_linux.h000077500000000000000000000040141321570333100274230ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #define _LITTLE_ENDIAN 1234 /* LSB first: i386, vax */ #define _BIG_ENDIAN 4321 /* MSB first: 68000, ibm, net */ #if defined(ADF_LITTLE_ENDIAN_MACHINE) #define _BYTE_ORDER _LITTLE_ENDIAN #elif defined(ADF_BIG_ENDIAN_MACHINE) #define _BYTE_ORDER _BIG_ENDIAN #else #error "Please fix asm/byteorder.h" #endif open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/ieee80211_node.h000077500000000000000000000047451321570333100272240ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _NET80211_IEEE80211_NODE_H_ #define _NET80211_IEEE80211_NODE_H_ #include "_ieee80211.h" #include "ieee80211.h" #include /* for proto macros on node */ #include #define IEEE80211_NODE_HASHSIZE 32 /* Node Table information for the Target */ struct ieee80211_node_table { asf_tailq_head(, ieee80211_node) nt_node; /* information of all nodes */ asf_list_head(, ieee80211_node) nt_hash[IEEE80211_NODE_HASHSIZE]; asf_list_head(, ieee80211_wds_addr) nt_wds_hash[IEEE80211_NODE_HASHSIZE]; }; #define IEEE80211_KEYBUF_SIZE 16 #define IEEE80211_TID_SIZE 17 #define IEEE80211_MICBUF_SIZE (8+8) /* space for both tx+rx keys */ struct ieee80211_key_target { a_int32_t dummy ; }; #endif open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/ieee80211_output.c000077500000000000000000000075541321570333100276330ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "ieee80211_var.h" #include "ieee80211.h" #include a_status_t ieee80211_tgt_crypto_encap(struct ieee80211_frame *wh, struct ieee80211_node_target *ni, a_uint8_t keytype) { #define CRYPTO_KEY_TYPE_AES 2 #define CRYPTO_KEY_TYPE_TKIP 3 #define CRYPTO_KEY_TYPE_WAPI 4 #define IEEE80211_WLAN_HDR_LEN 24 a_uint8_t *iv = NULL; a_uint16_t tmp; a_uint16_t offset = IEEE80211_WLAN_HDR_LEN; a_uint8_t b1, b2; struct ieee80211_qosframe_addr4 *wh_mesh; if (IEEE80211_QOS_HAS_SEQ(wh)) offset += 4; // pad for 4 byte alignment /* set the offset to 32 if the mesh control field is present */ wh_mesh = (struct ieee80211_qosframe_addr4 *)wh; if (wh_mesh->i_qos[1] & 0x01) offset = 32; iv = (a_uint8_t *) wh; iv = iv + offset; switch (keytype) { case CRYPTO_KEY_TYPE_AES: ni->ni_iv16++; if (ni->ni_iv16 == 0) { ni->ni_iv32++; } *iv++ = (a_uint8_t) ni->ni_iv16; *iv++ = (a_uint8_t) (ni->ni_iv16 >> 8); *iv++ = 0x00; *iv++ |= 0x20; tmp = (a_uint16_t) ni->ni_iv32; *iv++ = (a_uint8_t) tmp; *iv++ = (a_uint8_t) (tmp >> 8); tmp = (a_uint16_t) (ni->ni_iv32 >> 16); *iv++ = (a_uint8_t) tmp; *iv = (a_uint8_t) (tmp >> 8); break; case CRYPTO_KEY_TYPE_TKIP: ni->ni_iv16++; if (ni->ni_iv16 == 0) { ni->ni_iv32++; } b1 = (a_uint8_t) (ni->ni_iv16 >> 8); b2 = (b1 | 0x20) & 0x7f; *iv++ = b1; *iv++ = b2; *iv++ = (a_uint8_t) ni->ni_iv16; *iv++ |= 0x20; tmp = (a_uint16_t) ni->ni_iv32; *iv++ = (a_uint8_t) tmp; *iv++ = (a_uint8_t) (tmp >> 8); tmp = (a_uint16_t) (ni->ni_iv32 >> 16); *iv++ = (a_uint8_t) tmp; *iv = (a_uint8_t) (tmp >> 8); break; default: break; } return 1; #undef CRYPTO_KEY_TYPE_TKIP #undef CRYPTO_KEY_TYPE_AES #undef CRYPTO_KEY_TYPE_WAPI #undef IEEE80211_WLAN_HDR_LEN } #undef IEEE80211_ADDR_LEN open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/ieee80211_proto.h000077500000000000000000000042561321570333100274370ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _NET80211_IEEE80211_PROTO_H_ #define _NET80211_IEEE80211_PROTO_H_ #define IEEE80211_TXOP_TO_US(_txop) (a_uint32_t)(_txop) << 5 /* * 802.11 protocol implementation definitions. */ enum ieee80211_state { IEEE80211_S_INIT = 0, /* default state */ IEEE80211_S_SCAN = 1, /* scanning */ IEEE80211_S_JOIN = 2, /* join */ IEEE80211_S_AUTH = 3, /* try to authenticate */ IEEE80211_S_ASSOC = 4, /* try to assoc */ IEEE80211_S_RUN = 5, /* associated */ }; #endif open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/ieee80211_var.h000077500000000000000000000264521321570333100270660ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _NET80211_IEEE80211_VAR_H_ #define _NET80211_IEEE80211_VAR_H_ #include"ieee80211_linux.h" #include #include"_ieee80211.h" #include"ieee80211.h" #include"ieee80211_node.h" #include #define ieee80211_tgt_free_nbuf( _nbuf) adf_nbuf_free( _nbuf) /* * Built-in implementation for local skb free. Only interesting for platforms * that pass skbs between OS instances. */ #define ieee80211_tgt_free_local_nbuf( _nbuf) ieee80211_tgt_free_nbuf( _nbuf) #define IEEE80211_ADDR_EQ(a1,a2) (adf_os_mem_cmp(a1,a2,IEEE80211_ADDR_LEN) == 0) #define IEEE80211_ADDR_COPY(dst,src) adf_os_mem_copy(dst, src, IEEE80211_ADDR_LEN) /* ic_flags */ #define IEEE80211_F_FF 0x00000001 /* CONF: ATH FF enabled */ #define IEEE80211_F_TURBOP 0x00000002 /* CONF: ATH Turbo enabled*/ #define IEEE80211_F_PROMISC 0x00000004 /* STATUS: promiscuous mode */ #define IEEE80211_F_ALLMULTI 0x00000008 /* STATUS: all multicast mode */ /* NB: this is intentionally setup to be IEEE80211_CAPINFO_PRIVACY */ #define IEEE80211_F_PRIVACY 0x00000010 /* CONF: privacy enabled */ #define IEEE80211_F_PUREG 0x00000020 /* CONF: 11g w/o 11b sta's */ #define IEEE80211_F_XRUPDATE 0x00000040 /* CONF: update beacon XR element*/ #define IEEE80211_F_SCAN 0x00000080 /* STATUS: scanning */ #define IEEE80211_F_XR 0x00000100 /* CONF: operate in XR mode */ #define IEEE80211_F_SIBSS 0x00000200 /* STATUS: start IBSS */ /* NB: this is intentionally setup to be IEEE80211_CAPINFO_SHORT_SLOTTIME */ #define IEEE80211_F_SHSLOT 0x00000400 /* STATUS: use short slot time*/ #define IEEE80211_F_PMGTON 0x00000800 /* CONF: Power mgmt enable */ #define IEEE80211_F_DESBSSID 0x00001000 /* CONF: des_bssid is set */ #define IEEE80211_F_WME 0x00002000 /* CONF: enable WME use */ #define IEEE80211_F_BGSCAN 0x00004000 /* CONF: bg scan enabled */ #define IEEE80211_F_SWRETRY 0x00008000 /* CONF: sw tx retry enabled */ #define IEEE80211_F_TXPOW_FIXED 0x00010000 /* TX Power: fixed rate */ #define IEEE80211_F_IBSSON 0x00020000 /* CONF: IBSS creation enable */ #define IEEE80211_F_SHPREAMBLE 0x00040000 /* STATUS: use short preamble */ #define IEEE80211_F_DATAPAD 0x00080000 /* CONF: do alignment pad */ #define IEEE80211_F_USEPROT 0x00100000 /* STATUS: protection enabled */ #define IEEE80211_F_USEBARKER 0x00200000 /* STATUS: use barker preamble*/ #define IEEE80211_F_TIMUPDATE 0x00400000 /* STATUS: update beacon tim */ #define IEEE80211_F_WPA1 0x00800000 /* CONF: WPA enabled */ #define IEEE80211_F_WPA2 0x01000000 /* CONF: WPA2 enabled */ #define IEEE80211_F_WPA 0x01800000 /* CONF: WPA/WPA2 enabled */ #define IEEE80211_F_DROPUNENC 0x02000000 /* CONF: drop unencrypted */ #define IEEE80211_F_COUNTERM 0x04000000 /* CONF: TKIP countermeasures */ #define IEEE80211_F_HIDESSID 0x08000000 /* CONF: hide SSID in beacon */ #define IEEE80211_F_NOBRIDGE 0x10000000 /* CONF: disable internal bridge */ #define IEEE80211_F_WMEUPDATE 0x20000000 /* STATUS: update beacon wme */ #define IEEE80211_F_DOTH 0x40000000 /* enable 11.h */ #define IEEE80211_F_CHANSWITCH 0x80000000 /* force chanswitch */ /* ic_flags_ext */ #define IEEE80211_FEXT_WDS 0x00000001 /* CONF: 4 addr allowed */ #define IEEE80211_FEXT_COUNTRYIE 0x00000002 /* CONF: enable country IE */ #define IEEE80211_FEXT_SCAN_PENDING 0x00000004 /* STATE: scan pending */ #define IEEE80211_FEXT_BGSCAN 0x00000008 /* STATE: enable full bgscan completion */ #define IEEE80211_FEXT_UAPSD 0x00000010 /* CONF: enable U-APSD */ #define IEEE80211_FEXT_SLEEP 0x00000020 /* STATUS: sleeping */ #define IEEE80211_FEXT_EOSPDROP 0x00000040 /* drop uapsd EOSP frames for test */ #define IEEE80211_FEXT_MARKDFS 0x00000080 /* Enable marking of dfs interfernce */ #define IEEE80211_FEXT_REGCLASS 0x00000100 /* CONF: send regclassids in country ie */ #define IEEE80211_FEXT_MARKDFS 0x00000080 /* Enable marking of dfs interfernce */ #define IEEE80211_FEXT_ERPUPDATE 0x00000200 /* STATUS: update ERP element */ #define IEEE80211_FEXT_SWBMISS 0x00000400 /* CONF: use software beacon timer */ #define IEEE80211_FEXT_BLKDFSCHAN 0x00000800 /* CONF: block the use of DFS channels */ #define IEEE80211_FEXT_APPIE_UPDATE 0x00001000 /* STATE: beacon APP IE updated */ #define IEEE80211_FAST_CC 0x00002000 /* CONF: Fast channel change */ #define IEEE80211_C_AMPDU 0x00004000 /* CONF: A-MPDU supported */ #define IEEE80211_C_AMSDU 0x00008000 /* CONF: A-MSDU supported */ #define IEEE80211_C_HTPROT 0x00010000 /* CONF: HT traffic protected */ #define IEEE80211_C_RESET 0x00020000 /* CONF: Reset once */ #define IEEE80211_F_NONHT_AP 0x00040000 /* STATUS: HT traffic protected */ #define IEEE80211_FEXT_HTUPDATE 0x00080000 /* STATUS: update HT element */ #define IEEE80211_C_WDS_AUTODETECT 0x00100000 /* CONF: WDS auto Detect/DELBA */ #define IEEE80211_C_RB 0x00200000 /* CONF: RB control */ #define IEEE80211_C_RB_DETECT 0x00400000 /* CONF: RB auto detection */ #define IEEE80211_C_NO_HTIE 0x00800000 /* CONF: No HT IE sending/parsing */ /* ic_caps */ #define IEEE80211_C_WEP 0x00000001 /* CAPABILITY: WEP available */ #define IEEE80211_C_TKIP 0x00000002 /* CAPABILITY: TKIP available */ #define IEEE80211_C_AES 0x00000004 /* CAPABILITY: AES OCB avail */ #define IEEE80211_C_AES_CCM 0x00000008 /* CAPABILITY: AES CCM avail */ #define IEEE80211_C_CKIP 0x00000020 /* CAPABILITY: CKIP available */ #define IEEE80211_C_FF 0x00000040 /* CAPABILITY: ATH FF avail */ #define IEEE80211_C_TURBOP 0x00000080 /* CAPABILITY: ATH Turbo avail*/ #define IEEE80211_C_IBSS 0x00000100 /* CAPABILITY: IBSS available */ #define IEEE80211_C_PMGT 0x00000200 /* CAPABILITY: Power mgmt */ #define IEEE80211_C_HOSTAP 0x00000400 /* CAPABILITY: HOSTAP avail */ #define IEEE80211_C_AHDEMO 0x00000800 /* CAPABILITY: Old Adhoc Demo */ #define IEEE80211_C_SWRETRY 0x00001000 /* CAPABILITY: sw tx retry */ #define IEEE80211_C_TXPMGT 0x00002000 /* CAPABILITY: tx power mgmt */ #define IEEE80211_C_SHSLOT 0x00004000 /* CAPABILITY: short slottime */ #define IEEE80211_C_SHPREAMBLE 0x00008000 /* CAPABILITY: short preamble */ #define IEEE80211_C_MONITOR 0x00010000 /* CAPABILITY: monitor mode */ #define IEEE80211_C_TKIPMIC 0x00020000 /* CAPABILITY: TKIP MIC avail */ #define IEEE80211_C_WPA1 0x00800000 /* CAPABILITY: WPA1 avail */ #define IEEE80211_C_WPA2 0x01000000 /* CAPABILITY: WPA2 avail */ #define IEEE80211_C_WPA 0x01800000 /* CAPABILITY: WPA1+WPA2 avail*/ #define IEEE80211_C_BURST 0x02000000 /* CAPABILITY: frame bursting */ #define IEEE80211_C_WME 0x04000000 /* CAPABILITY: WME avail */ #define IEEE80211_C_WDS 0x08000000 /* CAPABILITY: 4-addr support */ #define IEEE80211_C_WME_TKIPMIC 0x10000000 /* CAPABILITY: TKIP MIC for QoS frame */ #define IEEE80211_C_BGSCAN 0x20000000 /* CAPABILITY: bg scanning */ #define IEEE80211_C_UAPSD 0x40000000 /* CAPABILITY: UAPSD */ #define IEEE80211_C_FASTCC 0x80000000 /* CAPABILITY: fast channel change */ /* XXX protection/barker? */ #define IEEE80211_C_CRYPTO 0x0000002f /* CAPABILITY: crypto alg's */ /* Atheros ABOLT definitions */ #define IEEE80211_ABOLT_TURBO_G 0x01 /* Legacy Turbo G */ #define IEEE80211_ABOLT_TURBO_PRIME 0x02 /* Turbo Prime */ #define IEEE80211_ABOLT_COMPRESSION 0x04 /* Compression */ #define IEEE80211_ABOLT_FAST_FRAME 0x08 /* Fast Frames */ #define IEEE80211_ABOLT_BURST 0x10 /* Bursting */ #define IEEE80211_ABOLT_WME_ELE 0x20 /* WME based cwmin/max/burst tuning */ #define IEEE80211_ABOLT_XR 0x40 /* XR */ #define IEEE80211_ABOLT_AR 0x80 /* AR switches out based on adjaced non-turbo traffic */ /* Atheros Advanced Capabilities ABOLT definition */ #define IEEE80211_ABOLT_ADVCAP (IEEE80211_ABOLT_TURBO_PRIME | \ IEEE80211_ABOLT_COMPRESSION | \ IEEE80211_ABOLT_FAST_FRAME | \ IEEE80211_ABOLT_XR | \ IEEE80211_ABOLT_AR | \ IEEE80211_ABOLT_BURST | \ IEEE80211_ABOLT_WME_ELE) /* check if a capability was negotiated for use */ #define IEEE80211_ATH_CAP(vap, ni, bit) \ ((ni)->ni_ath_flags & (vap)->iv_ath_cap & (bit)) /* flags to VAP create function */ #define IEEE80211_VAP_XR 0x10000 /* create a XR VAP without registering net device with OS*/ /* HT flags */ #define IEEE80211_HTF_SHORTGI 0x0001 /*************** Utility Routines ***/ /* * Return the size of the 802.11 header for a management or data frame. */ static __inline a_int32_t ieee80211_hdrsize(const void *data) { const struct ieee80211_frame *wh = data; a_int32_t size = sizeof(struct ieee80211_frame); /* NB: we don't handle control frames */ adf_os_assert((wh->i_fc[0]&IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL); if ((wh->i_fc[1] & IEEE80211_FC1_DIR_MASK) == IEEE80211_FC1_DIR_DSTODS) size += IEEE80211_ADDR_LEN; if (IEEE80211_QOS_HAS_SEQ(wh)) size += sizeof(a_uint16_t); return size; } /* * Like ieee80211_hdrsize, but handles any type of frame. */ static __inline a_int32_t ieee80211_anyhdrsize(const void *data) { const struct ieee80211_frame *wh = data; if ((wh->i_fc[0]&IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_CTL) { switch (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) { case IEEE80211_FC0_SUBTYPE_CTS: case IEEE80211_FC0_SUBTYPE_ACK: return sizeof(struct ieee80211_frame_ack); } return sizeof(struct ieee80211_frame_min); } else return ieee80211_hdrsize(data); } a_status_t ieee80211_tgt_crypto_encap(struct ieee80211_frame *wh, struct ieee80211_node_target *ni, a_uint8_t keytype); #endif open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/if_ath.c000077500000000000000000001511611321570333100261340ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "if_llc.h" #include "ieee80211_var.h" #include "if_athrate.h" #include "if_athvar.h" #include "ah_desc.h" #include "ah.h" #include "ratectrl.h" #include "ah_internal.h" static a_int32_t ath_numrxbufs = -1; static a_int32_t ath_numrxdescs = -1; #if defined(PROJECT_MAGPIE) uint32_t *init_htc_handle = 0; #endif #define RX_ENDPOINT_ID 3 #define ATH_CABQ_HANDLING_THRESHOLD 9000 #define UAPSDQ_NUM 9 #define CABQ_NUM 8 void owl_tgt_tx_tasklet(TQUEUE_ARG data); static void ath_tgt_send_beacon(struct ath_softc_tgt *sc,adf_nbuf_t bc_hdr,adf_nbuf_t nbuf,HTC_ENDPOINT_ID EndPt); static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen); static void ath_hal_reg_rmw_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen); extern struct ath_tx_buf* ath_tgt_tx_prepare(struct ath_softc_tgt *sc, adf_nbuf_t skb, ath_data_hdr_t *dh); extern void ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t mgt_hdr, adf_nbuf_t skb,HTC_ENDPOINT_ID EndPt); extern HAL_BOOL ath_hal_wait(struct ath_hal *ah, a_uint32_t reg, a_uint32_t mask, a_uint32_t val); extern void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq, owl_txq_state_t txqstate); void owl_tgt_node_init(struct ath_node_target * an); void ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, struct ath_buf *bf); void ath_tgt_tx_sched_nonaggr(struct ath_softc_tgt *sc,struct ath_buf * bf_host); /* * Extend a 32 bit TSF to nearest 64 bit TSF value. * When the adapter is a STATION, its local TSF is periodically modified by * the hardware to match the BSS TSF (as received in beacon packets), and * rstamp may appear to be from the future or from the past (with reference * to the current local TSF) because of jitter. This is mostly noticable in * highly congested channels. The code uses signed modulo arithmetic to * handle both past/future cases and signed-extension to avoid branches. * Test cases: * extend(0x0000001200000004, 0x00000006) == 0x0000001200000006 * extend(0x0000001200000004, 0x00000002) == 0x0000001200000002 * extend(0x0000001200000004, 0xfffffffe) == 0x00000011fffffffe ! tsfhigh-- * extend(0x000000127ffffffe, 0x80000002) == 0x0000001280000002 * extend(0x0000001280000002, 0x7ffffffe) == 0x000000127ffffffe * extend(0x00000012fffffffc, 0xfffffffe) == 0x00000012fffffffe * extend(0x00000012fffffffc, 0xfffffffa) == 0x00000012fffffffa * extend(0x00000012fffffffc, 0x00000002) == 0x0000001300000002 ! tsfhigh++ */ static u_int64_t ath_extend_tsf(struct ath_softc_tgt *sc, u_int32_t rstamp) { struct ath_hal *ah = sc->sc_ah; u_int64_t tsf; u_int32_t tsf_low; a_int64_t tsf_delta; /* signed int64 */ tsf = ah->ah_getTsf64(ah); tsf_low = tsf & 0xffffffffUL; tsf_delta = (a_int32_t)((rstamp - tsf_low) & 0xffffffffUL); return (tsf + (u_int64_t)tsf_delta); } static a_int32_t ath_rate_setup(struct ath_softc_tgt *sc, a_uint32_t mode) { struct ath_hal *ah = sc->sc_ah; const HAL_RATE_TABLE *rt; switch (mode) { case IEEE80211_MODE_11NA: sc->sc_rates[mode] = ah->ah_getRateTable(ah, HAL_MODE_11NA); break; case IEEE80211_MODE_11NG: sc->sc_rates[mode] = ah->ah_getRateTable(ah, HAL_MODE_11NG); break; default: return 0; } rt = sc->sc_rates[mode]; if (rt == NULL) return 0; return 1; } static void ath_setcurmode(struct ath_softc_tgt *sc, enum ieee80211_phymode mode) { const HAL_RATE_TABLE *rt; a_int32_t i; adf_os_mem_set(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); rt = sc->sc_rates[mode]; adf_os_assert(rt != NULL); for (i = 0; i < rt->rateCount; i++) { sc->sc_rixmap[rt->info[i].rateCode] = i; } sc->sc_currates = rt; sc->sc_curmode = mode; sc->sc_protrix = ((mode == IEEE80211_MODE_11NG) ? 3 : 0); } void wmi_event(wmi_handle_t handle, WMI_EVENT_ID evt_id, void *buffer, a_int32_t Length) { adf_nbuf_t netbuf = ADF_NBUF_NULL; a_uint8_t *pData; netbuf = WMI_AllocEvent(handle, WMI_EVT_CLASS_CMD_EVENT, sizeof(WMI_CMD_HDR) + Length); if (netbuf == ADF_NBUF_NULL) { adf_os_print("Buf null\n"); return; } if (buffer != NULL && Length != 0 && Length < WMI_SVC_MAX_BUFFERED_EVENT_SIZE) { pData = adf_nbuf_put_tail(netbuf, Length); adf_os_mem_copy(pData, buffer, Length); } WMI_SendEvent(handle, netbuf, evt_id, 0, Length); } void wmi_cmd_rsp(void *pContext, WMI_COMMAND_ID cmd_id, A_UINT16 SeqNo, void *buffer, a_int32_t Length) { adf_nbuf_t netbuf = ADF_NBUF_NULL; A_UINT8 *pData; netbuf = WMI_AllocEvent(pContext, WMI_EVT_CLASS_CMD_REPLY, sizeof(WMI_CMD_HDR) + Length); if (netbuf == ADF_NBUF_NULL) { adf_os_assert(0); return; } if (Length != 0 && buffer != NULL) { pData = (A_UINT8 *)adf_nbuf_put_tail(netbuf, Length); adf_os_mem_copy(pData, buffer, Length); } WMI_SendEvent(pContext, netbuf, cmd_id, SeqNo, Length); } static void ath_node_vdelete_tgt(struct ath_softc_tgt *sc, a_uint8_t vap_index) { a_int32_t i; for (i = 0; i < TARGET_NODE_MAX; i++) { if(sc->sc_sta[i].ni.ni_vapindex == vap_index) sc->sc_sta[i].an_valid = 0; } } a_uint8_t ath_get_minrateidx(struct ath_softc_tgt *sc, struct ath_vap_target *avp) { if (sc->sc_curmode == IEEE80211_MODE_11NG) return avp->av_minrateidx[0]; else if (sc->sc_curmode == IEEE80211_MODE_11NA) return avp->av_minrateidx[1]; return 0; } /******/ /* RX */ /******/ static adf_nbuf_t ath_alloc_skb_align(struct ath_softc_tgt *sc, a_uint32_t size, a_uint32_t align) { adf_nbuf_t skb; skb = BUF_Pool_alloc_buf_align(sc->pool_handle, POOL_ID_WLAN_RX_BUF, RX_HEADER_SPACE, align); return skb; } static a_int32_t ath_rxdesc_init(struct ath_softc_tgt *sc, struct ath_rx_desc *ds) { struct ath_hal *ah = sc->sc_ah; struct ath_rx_desc *ds_held; a_uint8_t *anbdata; a_uint32_t anblen; if (!sc->sc_rxdesc_held) { sc->sc_rxdesc_held = ds; return 0; } ds_held = sc->sc_rxdesc_held; sc->sc_rxdesc_held = ds; ds = ds_held; if (ds->ds_nbuf == ADF_NBUF_NULL) { ds->ds_nbuf = ath_alloc_skb_align(sc, sc->sc_rxbufsize, sc->sc_cachelsz); if (ds->ds_nbuf == ADF_NBUF_NULL) { sc->sc_rxdesc_held = ds; sc->sc_rx_stats.ast_rx_nobuf++; return ENOMEM; } adf_nbuf_map(sc->sc_dev, ds->ds_dmap, ds->ds_nbuf, ADF_OS_DMA_FROM_DEVICE); adf_nbuf_dmamap_info(ds->ds_dmap, &ds->ds_dmap_info); ds->ds_data = ds->ds_dmap_info.dma_segs[0].paddr; } ds->ds_link = 0; adf_nbuf_peek_header(ds->ds_nbuf, &anbdata, &anblen); ah->ah_setupRxDesc(ds, adf_nbuf_tailroom(ds->ds_nbuf), 0); if (sc->sc_rxlink == NULL) { ah->ah_setRxDP(ah, ds->ds_daddr); } else { *sc->sc_rxlink = ds->ds_daddr; } sc->sc_rxlink = &ds->ds_link; ah->ah_enableReceive(ah); return 0; } static void ath_rx_complete(struct ath_softc_tgt *sc, adf_nbuf_t buf) { struct ath_rx_desc *ds; adf_nbuf_t buf_tmp; adf_nbuf_queue_t nbuf_head; adf_nbuf_split_to_frag(buf, &nbuf_head); ds = asf_tailq_first(&sc->sc_rxdesc_idle); while (ds) { struct ath_rx_desc *ds_tmp; buf_tmp = adf_nbuf_queue_remove(&nbuf_head); if (buf_tmp == NULL) { break; } BUF_Pool_free_buf(sc->pool_handle, POOL_ID_WLAN_RX_BUF, buf_tmp); ds_tmp = ds; ds = asf_tailq_next(ds, ds_list); ath_rxdesc_init(sc, ds_tmp); asf_tailq_remove(&sc->sc_rxdesc_idle, ds_tmp, ds_list); asf_tailq_insert_tail(&sc->sc_rxdesc, ds_tmp, ds_list); } } static void tgt_HTCSendCompleteHandler(HTC_ENDPOINT_ID Endpt, adf_nbuf_t buf, void *ServiceCtx) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx; if (Endpt == RX_ENDPOINT_ID) { sc->sc_rx_stats.ast_rx_done++; ath_rx_complete(sc, buf); } } static void ath_uapsd_processtriggers(struct ath_softc_tgt *sc) { struct ath_hal *ah = sc->sc_ah; struct ath_rx_buf *bf = NULL; struct ath_rx_desc *ds, *ds_head, *ds_tail, *ds_tmp; a_int32_t retval; a_uint32_t cnt = 0; a_uint16_t frame_len = 0; #define PA2DESC(_sc, _pa) \ ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) bf = asf_tailq_first(&sc->sc_rxbuf); ds = asf_tailq_first(&sc->sc_rxdesc); ds_head = ds; while(ds) { ++cnt; if (cnt == ath_numrxbufs - 1) { adf_os_print("VERY LONG PACKET!!!!!\n"); ds_tail = ds; ds_tmp = ds_head; while (ds_tmp) { struct ath_rx_desc *ds_rmv; adf_nbuf_unmap(sc->sc_dev, ds_tmp->ds_dmap, ADF_OS_DMA_FROM_DEVICE); ds_rmv = ds_tmp; ds_tmp = asf_tailq_next(ds_tmp, ds_list); if (ds_tmp == NULL) { adf_os_print("ds_tmp is NULL\n"); adf_os_assert(0); } BUF_Pool_free_buf(sc->pool_handle, POOL_ID_WLAN_RX_BUF, ds_rmv->ds_nbuf); ds_rmv->ds_nbuf = ADF_NBUF_NULL; if (ath_rxdesc_init(sc, ds_rmv) == 0) { asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list); asf_tailq_insert_tail(&sc->sc_rxdesc, ds_rmv, ds_list); } else { asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list); asf_tailq_insert_tail(&sc->sc_rxdesc_idle, ds_rmv, ds_list); } if (ds_rmv == ds_tail) { break; } } break; } if (ds->ds_link == 0) { break; } if (bf->bf_status & ATH_BUFSTATUS_DONE) { continue; } retval = ah->ah_procRxDescFast(ah, ds, ds->ds_daddr, PA2DESC(sc, ds->ds_link), &bf->bf_rx_status); if (HAL_EINPROGRESS == retval) { break; } if (adf_nbuf_len(ds->ds_nbuf) == 0) { adf_nbuf_put_tail(ds->ds_nbuf, bf->bf_rx_status.rs_datalen); } frame_len += bf->bf_rx_status.rs_datalen; if (bf->bf_rx_status.rs_more == 0) { adf_nbuf_queue_t nbuf_head; adf_nbuf_queue_init(&nbuf_head); cnt = 0; ds_tail = ds; ds = asf_tailq_next(ds, ds_list); ds_tmp = ds_head; ds_head = asf_tailq_next(ds_tail, ds_list); while (ds_tmp) { struct ath_rx_desc *ds_rmv; adf_nbuf_unmap(sc->sc_dev, ds_tmp->ds_dmap, ADF_OS_DMA_FROM_DEVICE); adf_nbuf_queue_add(&nbuf_head, ds_tmp->ds_nbuf); ds_tmp->ds_nbuf = ADF_NBUF_NULL; ds_rmv = ds_tmp; ds_tmp = asf_tailq_next(ds_tmp, ds_list); if (ds_tmp == NULL) { adf_os_assert(0); } if (ath_rxdesc_init(sc, ds_rmv) == 0) { asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list); asf_tailq_insert_tail(&sc->sc_rxdesc, ds_rmv, ds_list); } else { asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list); asf_tailq_insert_tail(&sc->sc_rxdesc_idle, ds_rmv, ds_list); } if (ds_rmv == ds_tail) { break; } } bf->bf_rx_status.rs_datalen = frame_len; frame_len = 0; bf->bf_skb = adf_nbuf_create_frm_frag(&nbuf_head); bf->bf_status |= ATH_BUFSTATUS_DONE; bf = (struct ath_rx_buf *)asf_tailq_next(bf, bf_list); } else { ds = asf_tailq_next(ds, ds_list); } } #undef PA2DESC } static a_int32_t ath_startrecv(struct ath_softc_tgt *sc) { struct ath_hal *ah = sc->sc_ah; struct ath_rx_desc *ds; sc->sc_rxbufsize = 1024+512+128; sc->sc_rxlink = NULL; sc->sc_rxdesc_held = NULL; asf_tailq_foreach(ds, &sc->sc_rxdesc, ds_list) { a_int32_t error = ath_rxdesc_init(sc, ds); if (error != 0) { return error; } } ds = asf_tailq_first(&sc->sc_rxdesc); ah->ah_setRxDP(ah, ds->ds_daddr); return 0; } static void ath_tgt_rx_tasklet(TQUEUE_ARG data) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data; struct ath_rx_buf *bf = NULL; struct ath_hal *ah = sc->sc_ah; struct rx_frame_header *rxhdr; struct ath_rx_status *rxstats; adf_nbuf_t skb = ADF_NBUF_NULL; do { bf = asf_tailq_first(&sc->sc_rxbuf); if (bf == NULL) { break; } if (!(bf->bf_status & ATH_BUFSTATUS_DONE)) { break; } skb = bf->bf_skb; if (skb == NULL) { continue; } asf_tailq_remove(&sc->sc_rxbuf, bf, bf_list); bf->bf_skb = NULL; rxhdr = (struct rx_frame_header *)adf_nbuf_push_head(skb, sizeof(struct rx_frame_header)); rxstats = (struct ath_rx_status *)(&rxhdr->rx_stats[0]); adf_os_mem_copy(rxstats, &(bf->bf_rx_status), sizeof(struct ath_rx_status)); rxstats->rs_tstamp = ath_extend_tsf(sc, (u_int32_t)rxstats->rs_tstamp); HTC_SendMsg(sc->tgt_htc_handle, RX_ENDPOINT_ID, skb); sc->sc_rx_stats.ast_rx_send++; bf->bf_status &= ~ATH_BUFSTATUS_DONE; asf_tailq_insert_tail(&sc->sc_rxbuf, bf, bf_list); } while(1); sc->sc_imask |= HAL_INT_RX; ah->ah_setInterrupts(ah, sc->sc_imask); } /*******************/ /* Beacon Handling */ /*******************/ /* * Setup the beacon frame for transmit. * FIXME: Short Preamble. */ static void ath_beacon_setup(struct ath_softc_tgt *sc, struct ath_tx_buf *bf, struct ath_vap_target *avp) { adf_nbuf_t skb = bf->bf_skb; struct ath_hal *ah = sc->sc_ah; struct ath_tx_desc *ds; a_int32_t flags; const HAL_RATE_TABLE *rt; a_uint8_t rix, rate; HAL_11N_RATE_SERIES series[4] = {{ 0 }}; flags = HAL_TXDESC_NOACK; ds = bf->bf_desc; ds->ds_link = 0; ds->ds_data = bf->bf_dmamap_info.dma_segs[0].paddr; rix = ath_get_minrateidx(sc, avp); rt = sc->sc_currates; rate = rt->info[rix].rateCode; ah->ah_setupTxDesc(ds , adf_nbuf_len(skb) + IEEE80211_CRC_LEN , sizeof(struct ieee80211_frame) , HAL_PKT_TYPE_BEACON , MAX_RATE_POWER , rate, 1 , HAL_TXKEYIX_INVALID , flags , 0 , 0); ah->ah_fillTxDesc(ds , asf_roundup(adf_nbuf_len(skb), 4) , AH_TRUE , AH_TRUE , ds); series[0].Tries = 1; series[0].Rate = rate; series[0].ChSel = sc->sc_ic.ic_tx_chainmask; series[0].RateFlags = 0; ah->ah_set11nRateScenario(ds, 0, 0, series, 4, 0); } static void ath_tgt_send_beacon(struct ath_softc_tgt *sc, adf_nbuf_t bc_hdr, adf_nbuf_t nbuf, HTC_ENDPOINT_ID EndPt) { struct ath_hal *ah = sc->sc_ah; struct ath_tx_buf *bf; a_uint8_t vap_index, *anbdata; ath_beacon_hdr_t *bhdr = NULL; a_uint32_t anblen; if (!bc_hdr) { adf_nbuf_peek_header(nbuf, &anbdata, &anblen); bhdr = (ath_beacon_hdr_t *)anbdata; } else { adf_os_print("found bc_hdr! 0x%x\n", bc_hdr); adf_os_assert(0); } vap_index = bhdr->vap_index; adf_os_assert(vap_index < TARGET_VAP_MAX); adf_nbuf_pull_head(nbuf, sizeof(ath_beacon_hdr_t)); bf = sc->sc_vap[vap_index].av_bcbuf; adf_os_assert(bf); bf->bf_endpt = EndPt; if (bf->bf_skb) { adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap, ADF_OS_DMA_TO_DEVICE); adf_nbuf_push_head(bf->bf_skb, sizeof(ath_beacon_hdr_t)); ath_free_tx_skb(sc->tgt_htc_handle, bf->bf_endpt, bf->bf_skb); } bf->bf_skb = nbuf; adf_nbuf_map(sc->sc_dev, bf->bf_dmamap, nbuf, ADF_OS_DMA_TO_DEVICE); adf_nbuf_dmamap_info(bf->bf_dmamap,&bf->bf_dmamap_info); ath_beacon_setup(sc, bf, &sc->sc_vap[vap_index]); ah->ah_stopTxDma(ah, sc->sc_bhalq); ah->ah_setTxDP(ah, sc->sc_bhalq, ATH_BUF_GET_DESC_PHY_ADDR(bf)); ah->ah_startTxDma(ah, sc->sc_bhalq); } /******/ /* TX */ /******/ static void ath_tx_stopdma(struct ath_softc_tgt *sc, struct ath_txq *txq) { struct ath_hal *ah = sc->sc_ah; ah->ah_stopTxDma(ah, txq->axq_qnum); } static void owltgt_txq_drain(struct ath_softc_tgt *sc, struct ath_txq *txq) { owltgt_tx_processq(sc, txq, OWL_TXQ_STOPPED); } static void ath_tx_draintxq(struct ath_softc_tgt *sc, struct ath_txq *txq) { owltgt_txq_drain(sc, txq); } static void ath_draintxq(struct ath_softc_tgt *sc, HAL_BOOL drain_softq) { struct ath_hal *ah = sc->sc_ah; a_uint16_t i; struct ath_txq *txq = NULL; struct ath_atx_tid *tid = NULL; ath_tx_status_clear(sc); sc->sc_tx_draining = 1; ah->ah_stopTxDma(ah, sc->sc_bhalq); for (i = 0; i < HAL_NUM_TX_QUEUES; i++) if (ATH_TXQ_SETUP(sc, i)) ath_tx_stopdma(sc, ATH_TXQ(sc, i)); for (i = 0; i < HAL_NUM_TX_QUEUES; i++) if (ATH_TXQ_SETUP(sc, i)) { owltgt_tx_processq(sc, ATH_TXQ(sc,i), OWL_TXQ_STOPPED); txq = ATH_TXQ(sc,i); while (!asf_tailq_empty(&txq->axq_tidq)){ TAILQ_DEQ(&txq->axq_tidq, tid, tid_qelem); if(tid == NULL) break; tid->sched = AH_FALSE; ath_tgt_tid_drain(sc,tid); } } sc->sc_tx_draining = 0; } static void ath_tgt_txq_setup(struct ath_softc_tgt *sc) { a_int32_t qnum; struct ath_txq *txq; sc->sc_txqsetup=0; for (qnum=0;qnumsc_txq[qnum]; txq->axq_qnum = qnum; txq->axq_link = NULL; asf_tailq_init(&txq->axq_q); txq->axq_depth = 0; txq->axq_linkbuf = NULL; asf_tailq_init(&txq->axq_tidq); sc->sc_txqsetup |= 1<sc_uapsdq = &sc->sc_txq[UAPSDQ_NUM]; sc->sc_cabq = &sc->sc_txq[CABQ_NUM]; sc->sc_ac2q[WME_AC_BE] = &sc->sc_txq[0]; sc->sc_ac2q[WME_AC_BK] = &sc->sc_txq[1]; sc->sc_ac2q[WME_AC_VI] = &sc->sc_txq[2]; sc->sc_ac2q[WME_AC_VO] = &sc->sc_txq[3]; return; #undef N } static void tgt_HTCRecv_beaconhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf, adf_nbuf_t buf, void *ServiceCtx) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx; ath_tgt_send_beacon(sc, hdr_buf, buf, EndPt); } static void tgt_HTCRecv_uapsdhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf, adf_nbuf_t buf, void *ServiceCtx) { } static void tgt_HTCRecv_mgmthandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf, adf_nbuf_t buf, void *ServiceCtx) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx; ath_tgt_send_mgt(sc,hdr_buf,buf,EndPt); } static void tgt_HTCRecvMessageHandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf, adf_nbuf_t buf, void *ServiceCtx) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx; struct ath_tx_buf *bf; a_uint8_t *data; a_uint32_t len; ath_data_hdr_t *dh; struct ath_node_target *an; struct ath_atx_tid *tid; if (!hdr_buf) { adf_nbuf_peek_header(buf, &data, &len); adf_nbuf_pull_head(buf, sizeof(ath_data_hdr_t)); } else { adf_nbuf_peek_header(hdr_buf, &data, &len); } adf_os_assert(len >= sizeof(ath_data_hdr_t)); dh = (ath_data_hdr_t *)data; an = &sc->sc_sta[dh->ni_index]; tid = ATH_AN_2_TID(an, dh->tidno); sc->sc_tx_stats.tx_tgt++; bf = ath_tgt_tx_prepare(sc, buf, dh); if (!bf) { ath_free_tx_skb(sc->tgt_htc_handle,EndPt,buf); return; } bf->bf_endpt = EndPt; bf->bf_cookie = dh->cookie; bf->vap_index = dh->vap_index; if (tid->flag & TID_AGGR_ENABLED) ath_tgt_handle_aggr(sc, bf); else ath_tgt_handle_normal(sc, bf); } static void tgt_HTCRecv_cabhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf, adf_nbuf_t buf, void *ServiceCtx) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx; struct ath_hal *ah = sc->sc_ah; a_uint64_t tsf; a_uint32_t tmp; #ifdef ATH_ENABLE_CABQ tsf = ah->ah_getTsf64(ah); tmp = tsf - sc->sc_swba_tsf; if ( tmp > ATH_CABQ_HANDLING_THRESHOLD ) { HTC_ReturnBuffers(sc->tgt_htc_handle, EndPt, buf); return; } tgt_HTCRecvMessageHandler(EndPt, hdr_buf, buf, ServiceCtx); #endif } /***********************/ /* Descriptor Handling */ /***********************/ static a_int32_t ath_descdma_setup(struct ath_softc_tgt *sc, struct ath_descdma *dd, ath_bufhead *head, const char *name, a_int32_t nbuf, a_int32_t ndesc, a_uint32_t bfSize, a_uint32_t descSize) { #define DS2PHYS(_dd, _ds) \ ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) struct ath_desc *ds; struct ath_buf *bf; a_int32_t i, bsize, error; a_uint8_t *bf_addr; a_uint8_t *ds_addr; dd->dd_name = name; dd->dd_desc_len = descSize * nbuf * ndesc; dd->dd_desc = adf_os_dmamem_alloc(sc->sc_dev, dd->dd_desc_len, 1, &dd->dd_desc_dmamap); dd->dd_desc_paddr = adf_os_dmamem_map2addr(dd->dd_desc_dmamap); if (dd->dd_desc == NULL) { error = -ENOMEM; goto fail; } ds = dd->dd_desc; bsize = bfSize * nbuf; bf = adf_os_mem_alloc(bsize); if (bf == NULL) { error = -ENOMEM; goto fail2; } adf_os_mem_set(bf, 0, bsize); dd->dd_bufptr = bf; bf_addr = (a_uint8_t *)bf; ds_addr = (a_uint8_t *)ds; asf_tailq_init(head); for (i = 0; i < nbuf; i++) { a_int32_t j; if (adf_nbuf_dmamap_create( sc->sc_dev, &bf->bf_dmamap) != A_STATUS_OK) { goto fail2; } bf->bf_desc = bf->bf_descarr = bf->bf_lastds = ds; for (j = 0; j < ndesc; j++) ATH_BUF_SET_DESC_PHY_ADDR_WITH_IDX(bf, j, (ds_addr + (j*descSize))); ATH_BUF_SET_DESC_PHY_ADDR(bf, ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, 0)); adf_nbuf_queue_init(&bf->bf_skbhead); asf_tailq_insert_tail(head, bf, bf_list); bf_addr += bfSize; ds_addr += (ndesc * descSize); bf = (struct ath_buf *)bf_addr; ds = (struct ath_desc *)ds_addr; } return 0; fail2: adf_os_dmamem_free(sc->sc_dev, dd->dd_desc_len, 1, dd->dd_desc, dd->dd_desc_dmamap); fail: adf_os_mem_set(dd, 0, sizeof(*dd)); adf_os_assert(0); return error; #undef DS2PHYS } static void ath_descdma_cleanup(struct ath_softc_tgt *sc, struct ath_descdma *dd, ath_bufhead *head, a_int32_t dir) { struct ath_buf *bf; asf_tailq_foreach(bf, head, bf_list) { if (adf_nbuf_queue_len(&bf->bf_skbhead) != 0) { adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap, dir); while(adf_nbuf_queue_len(&bf->bf_skbhead) != 0) { ath_free_rx_skb(sc, adf_nbuf_queue_remove(&bf->bf_skbhead)); } bf->bf_skb = NULL; } else if (bf->bf_skb != NULL) { adf_nbuf_unmap(sc->sc_dev,bf->bf_dmamap, dir); ath_free_rx_skb(sc, bf->bf_skb); bf->bf_skb = NULL; } adf_nbuf_dmamap_destroy(sc->sc_dev, bf->bf_dmamap); bf->bf_node = NULL; } adf_os_dmamem_free(sc->sc_dev, dd->dd_desc_len, 1, dd->dd_desc, dd->dd_desc_dmamap); asf_tailq_init(head); adf_os_mem_free(dd->dd_bufptr); adf_os_mem_set(dd, 0, sizeof(*dd)); } static a_int32_t ath_desc_alloc(struct ath_softc_tgt *sc) { #define DS2PHYS(_dd, _ds) \ ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) a_int32_t error; struct ath_tx_buf *bf; if(ath_numrxbufs == -1) ath_numrxbufs = ATH_RXBUF; if (ath_numrxdescs == -1) ath_numrxdescs = ATH_RXDESC; error = ath_descdma_setup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf, "rx", ath_numrxdescs, 1, sizeof(struct ath_rx_buf), sizeof(struct ath_rx_desc)); if (error != 0) return error; a_uint32_t i; struct ath_descdma *dd = &sc->sc_rxdma; struct ath_rx_desc *ds = (struct ath_rx_desc *)dd->dd_desc; struct ath_rx_desc *ds_prev = NULL; asf_tailq_init(&sc->sc_rxdesc); asf_tailq_init(&sc->sc_rxdesc_idle); for (i = 0; i < ath_numrxdescs; i++, ds++) { if (ds->ds_nbuf != ADF_NBUF_NULL) { ds->ds_nbuf = ADF_NBUF_NULL; } if (adf_nbuf_dmamap_create(sc->sc_dev, &ds->ds_dmap) != A_STATUS_OK) { adf_os_assert(0); } ds->ds_daddr = DS2PHYS(&sc->sc_rxdma, ds); if (ds_prev) { ds_prev->ds_link = ds->ds_daddr; } ds->ds_link = 0; ds_prev = ds; asf_tailq_insert_tail(&sc->sc_rxdesc, ds, ds_list); } error = ath_descdma_setup(sc, &sc->sc_txdma, (ath_bufhead *)&sc->sc_txbuf, "tx", ATH_TXBUF + 1, ATH_TXDESC, sizeof(struct ath_tx_buf), sizeof(struct ath_tx_desc)); if (error != 0) { ath_descdma_cleanup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf, ADF_OS_DMA_FROM_DEVICE); return error; } error = ath_descdma_setup(sc, &sc->sc_bdma, (ath_bufhead *)&sc->sc_bbuf, "beacon", ATH_BCBUF, 1, sizeof(struct ath_tx_buf), sizeof(struct ath_tx_desc)); if (error != 0) { ath_descdma_cleanup(sc, &sc->sc_txdma, (ath_bufhead *)&sc->sc_txbuf, ADF_OS_DMA_TO_DEVICE); ath_descdma_cleanup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf, ADF_OS_DMA_FROM_DEVICE); return error; } bf = asf_tailq_first(&sc->sc_txbuf); bf->bf_isaggr = bf->bf_isretried = bf->bf_retries = 0; asf_tailq_remove(&sc->sc_txbuf, bf, bf_list); sc->sc_txbuf_held = bf; return 0; #undef DS2PHYS } static void ath_desc_free(struct ath_softc_tgt *sc) { asf_tailq_insert_tail(&sc->sc_txbuf, sc->sc_txbuf_held, bf_list); sc->sc_txbuf_held = NULL; if (sc->sc_txdma.dd_desc_len != 0) ath_descdma_cleanup(sc, &sc->sc_txdma, (ath_bufhead *)&sc->sc_txbuf, ADF_OS_DMA_TO_DEVICE); if (sc->sc_rxdma.dd_desc_len != 0) ath_descdma_cleanup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf, ADF_OS_DMA_FROM_DEVICE); } /**********************/ /* Interrupt Handling */ /**********************/ adf_os_irq_resp_t ath_intr(adf_drv_handle_t hdl) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)hdl; struct ath_hal *ah = sc->sc_ah; HAL_INT status; if (sc->sc_invalid) return ADF_OS_IRQ_NONE; if (!ah->ah_isInterruptPending(ah)) return ADF_OS_IRQ_NONE; ah->ah_getPendingInterrupts(ah, &status); status &= sc->sc_imask; if (status & HAL_INT_FATAL) { ah->ah_setInterrupts(ah, 0); ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_fataltq); } else { if (status & HAL_INT_SWBA) { WMI_SWBA_EVENT swbaEvt; struct ath_txq *txq = ATH_TXQ(sc, 8); swbaEvt.tsf = ah->ah_getTsf64(ah); swbaEvt.beaconPendingCount = ah->ah_numTxPending(ah, sc->sc_bhalq); sc->sc_swba_tsf = ah->ah_getTsf64(ah); wmi_event(sc->tgt_wmi_handle, WMI_SWBA_EVENTID, &swbaEvt, sizeof(WMI_SWBA_EVENT)); ath_tx_draintxq(sc, txq); } if (status & HAL_INT_RXORN) sc->sc_int_stats.ast_rxorn++; if (status & HAL_INT_RXEOL) sc->sc_int_stats.ast_rxeol++; if (status & (HAL_INT_RX | HAL_INT_RXEOL | HAL_INT_RXORN)) { if (status & HAL_INT_RX) sc->sc_int_stats.ast_rx++; ath_uapsd_processtriggers(sc); sc->sc_imask &= ~HAL_INT_RX; ah->ah_setInterrupts(ah, sc->sc_imask); ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_rxtq); } if (status & HAL_INT_TXURN) { sc->sc_int_stats.ast_txurn++; ah->ah_updateTxTrigLevel(ah, AH_TRUE); } ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_txtq); if (status & HAL_INT_BMISS) { ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_bmisstq); } if (status & HAL_INT_GTT) sc->sc_int_stats.ast_txto++; if (status & HAL_INT_CST) sc->sc_int_stats.ast_cst++; } return ADF_OS_IRQ_HANDLED; } static void ath_fatal_tasklet(TQUEUE_ARG data ) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data; wmi_event(sc->tgt_wmi_handle, WMI_FATAL_EVENTID, NULL, 0); } static void ath_bmiss_tasklet(TQUEUE_ARG data) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data; wmi_event(sc->tgt_wmi_handle, WMI_BMISS_EVENTID, NULL, 0); } /****************/ /* WMI Commands */ /****************/ static void ath_enable_intr_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; struct ath_hal *ah = sc->sc_ah; a_uint32_t intr = 0; if (datalen == 4) intr = (*(a_uint32_t *)data); intr = adf_os_ntohl(intr); if (intr & HAL_INT_SWBA) { sc->sc_imask |= HAL_INT_SWBA; } else { sc->sc_imask &= ~HAL_INT_SWBA; } if (intr & HAL_INT_BMISS) { sc->sc_imask |= HAL_INT_BMISS; } ah->ah_setInterrupts(ah, sc->sc_imask); wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0); } static void ath_init_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; struct ath_hal *ah = sc->sc_ah; sc->sc_imask = HAL_INT_RX | HAL_INT_TX | HAL_INT_RXEOL | HAL_INT_RXORN | HAL_INT_FATAL | HAL_INT_GLOBAL; sc->sc_imask |= HAL_INT_GTT; if (ath_hal_getcapability(ah, HAL_CAP_HT)) sc->sc_imask |= HAL_INT_CST; adf_os_setup_intr(sc->sc_dev, ath_intr); ah->ah_setInterrupts(ah, sc->sc_imask); wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); } static void ath_int_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; struct fusion_stats { a_uint32_t ast_rx; a_uint32_t ast_rxorn; a_uint32_t ast_rxeol; a_uint32_t ast_txurn; a_uint32_t ast_txto; a_uint32_t ast_cst; }; struct fusion_stats stats; stats.ast_rx = sc->sc_int_stats.ast_rx; stats.ast_rxorn = sc->sc_int_stats.ast_rxorn; stats.ast_rxeol = sc->sc_int_stats.ast_rxeol; stats.ast_txurn = sc->sc_int_stats.ast_txurn; stats.ast_txto = sc->sc_int_stats.ast_txto; stats.ast_cst = sc->sc_int_stats.ast_cst; wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats)); } static void ath_tx_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; struct fusion_stats { a_uint32_t ast_tx_xretries; a_uint32_t ast_tx_fifoerr; a_uint32_t ast_tx_filtered; a_uint32_t ast_tx_timer_exp; a_uint32_t ast_tx_shortretry; a_uint32_t ast_tx_longretry; a_uint32_t tx_qnull; a_uint32_t tx_noskbs; a_uint32_t tx_nobufs; }; struct fusion_stats stats; stats.ast_tx_xretries = sc->sc_tx_stats.ast_tx_xretries; stats.ast_tx_fifoerr = sc->sc_tx_stats.ast_tx_fifoerr; stats.ast_tx_filtered = sc->sc_tx_stats.ast_tx_filtered; stats.ast_tx_timer_exp = sc->sc_tx_stats.ast_tx_timer_exp; stats.ast_tx_shortretry = sc->sc_tx_stats.ast_tx_shortretry; stats.ast_tx_longretry = sc->sc_tx_stats.ast_tx_longretry; stats.tx_qnull = sc->sc_tx_stats.tx_qnull; stats.tx_noskbs = sc->sc_tx_stats.tx_noskbs; stats.tx_nobufs = sc->sc_tx_stats.tx_nobufs; wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats)); } static void ath_rx_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; struct fusion_stats { a_uint32_t ast_rx_nobuf; a_uint32_t ast_rx_send; a_uint32_t ast_rx_done; }; struct fusion_stats stats; stats.ast_rx_nobuf = sc->sc_rx_stats.ast_rx_nobuf; stats.ast_rx_send = sc->sc_rx_stats.ast_rx_send; stats.ast_rx_done = sc->sc_rx_stats.ast_rx_done; wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats)); } static void ath_get_tgt_version(void *Context,A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; struct wmi_fw_version ver; ver.major = ATH_VERSION_MAJOR; ver.minor = ATH_VERSION_MINOR; wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &ver, sizeof(ver)); } static void ath_enable_aggr_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; struct ath_aggr_info *aggr = (struct ath_aggr_info *)data; a_uint8_t nodeindex = aggr->nodeindex; a_uint8_t tidno = aggr->tidno; struct ath_node_target *an = NULL ; struct ath_atx_tid *tid = NULL; if (nodeindex >= TARGET_NODE_MAX) { goto done; } an = &sc->sc_sta[nodeindex]; if (!an->an_valid) { goto done; } if (tidno >= WME_NUM_TID) { adf_os_print("[%s] enable_aggr with invalid tid %d(node = %d)\n", __FUNCTION__, tidno, nodeindex); goto done; } tid = ATH_AN_2_TID(an, tidno); if (aggr->aggr_enable) { tid->flag |= TID_AGGR_ENABLED; } else if ( tid->flag & TID_AGGR_ENABLED ) { tid->flag &= ~TID_AGGR_ENABLED; ath_tgt_tx_cleanup(sc, an, tid, 1); } done: wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); } static void ath_ic_update_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; struct ieee80211com_target *ic = (struct ieee80211com_target * )data; struct ieee80211com_target *ictgt = &sc->sc_ic ; adf_os_mem_copy(ictgt, ic, sizeof(struct ieee80211com_target)); ictgt->ic_ampdu_limit = adf_os_ntohl(ic->ic_ampdu_limit); wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); } static void ath_vap_create_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; struct ieee80211vap_target *vap; a_uint8_t vap_index; vap = (struct ieee80211vap_target *)data; vap->iv_rtsthreshold = adf_os_ntohs(vap->iv_rtsthreshold); vap->iv_opmode = adf_os_ntohl(vap->iv_opmode); vap_index = vap->iv_vapindex; adf_os_assert(sc->sc_vap[vap_index].av_valid == 0); adf_os_mem_copy(&(sc->sc_vap[vap_index].av_vap), vap, VAP_TARGET_SIZE); sc->sc_vap[vap_index].av_bcbuf = asf_tailq_first(&(sc->sc_bbuf)); sc->sc_vap[vap_index].av_valid = 1; wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); } static void ath_node_create_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; struct ieee80211_node_target *node; a_uint8_t vap_index; a_uint8_t node_index; node = (struct ieee80211_node_target *)data; node_index = node->ni_nodeindex; node->ni_htcap = adf_os_ntohs(node->ni_htcap); node->ni_flags = adf_os_ntohs(node->ni_flags); node->ni_maxampdu = adf_os_ntohs(node->ni_maxampdu); adf_os_mem_copy(&(sc->sc_sta[node_index].ni), node, NODE_TARGET_SIZE); vap_index = sc->sc_sta[node_index].ni.ni_vapindex; sc->sc_sta[node_index].ni.ni_vap = &(sc->sc_vap[vap_index].av_vap); if(sc->sc_sta[node_index].ni.ni_is_vapnode == 1) sc->sc_vap[vap_index].av_vap.iv_nodeindex = node_index; sc->sc_sta[node_index].an_valid = 1; sc->sc_sta[node_index].ni.ni_txseqmgmt = 0; sc->sc_sta[node_index].ni.ni_iv16 = 0; sc->sc_sta[node_index].ni.ni_iv32 = 0; owl_tgt_node_init(&sc->sc_sta[node_index]); wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); } static void ath_node_cleanup_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; a_uint8_t node_index; a_uint8_t *nodedata; nodedata = (a_uint8_t *)data; node_index = *nodedata; sc->sc_sta[node_index].an_valid = 0; wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); } static void ath_node_update_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; struct ieee80211_node_target *node; a_uint8_t vap_index; a_uint8_t node_index; node = (struct ieee80211_node_target *)data; node_index = node->ni_nodeindex; node->ni_htcap = adf_os_ntohs(node->ni_htcap); node->ni_flags = adf_os_ntohs(node->ni_flags); node->ni_maxampdu = adf_os_ntohs(node->ni_maxampdu); adf_os_mem_copy(&(sc->sc_sta[node_index].ni), node, NODE_TARGET_SIZE); vap_index = sc->sc_sta[node_index].ni.ni_vapindex; sc->sc_sta[node_index].ni.ni_vap = &(sc->sc_vap[vap_index].av_vap); sc->sc_sta[node_index].ni.ni_txseqmgmt = 0; sc->sc_sta[node_index].ni.ni_iv16 = 0; sc->sc_sta[node_index].ni.ni_iv32 = 0; wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); } static a_int32_t ath_reg_read_filter(struct ath_hal *ah, a_int32_t addr) { if ((addr & 0xffffe000) == 0x2000) { /* SEEPROM registers */ ioread32_mac(addr); if (!ath_hal_wait(ah, 0x407c, 0x00030000, 0)) adf_os_print("SEEPROM Read fail: 0x%08x\n", addr); return ioread32_mac(0x407c) & 0x0000ffff; } else if (addr > 0xffff) /* SoC registers */ return ioread32(addr); else /* MAC registers */ return ioread32_mac(addr); } static void ath_hal_reg_read_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; struct ath_hal *ah = sc->sc_ah; a_uint32_t addr; a_uint32_t val[32]; int i; for (i = 0; i < datalen; i += sizeof(a_int32_t)) { addr = *(a_uint32_t *)(data + i); addr = adf_os_ntohl(addr); val[i/sizeof(a_int32_t)] = adf_os_ntohl(ath_reg_read_filter(ah, addr)); } wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &val[0], datalen); } static void ath_pll_reset_ones(struct ath_hal *ah) { static uint8_t reset_pll = 0; if(reset_pll == 0) { #if defined(PROJECT_K2) /* here we write to core register */ iowrite32(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0); /* and here to mac register */ iowrite32_mac(0x786c, ioread32_mac(0x786c) | 0x6000000); iowrite32_mac(0x786c, ioread32_mac(0x786c) & (~0x6000000)); iowrite32(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x20); #elif defined(PROJECT_MAGPIE) && !defined (FPGA) iowrite32_mac(0x7890, ioread32_mac(0x7890) | 0x1800000); iowrite32_mac(0x7890, ioread32_mac(0x7890) & (~0x1800000)); #endif reset_pll = 1; } } static void ath_hal_reg_write_filter(struct ath_hal *ah, a_uint32_t reg, a_uint32_t val) { if(reg > 0xffff) { iowrite32(reg, val); #if defined(PROJECT_K2) if(reg == 0x50040) { static uint8_t flg=0; if(flg == 0) { /* reinit clock and uart. * TODO: Independent on what host will * here set. We do our own decision. Why? */ A_CLOCK_INIT(117); A_UART_HWINIT(117*1000*1000, 19200); flg = 1; } } #endif } else { if(reg == 0x7014) ath_pll_reset_ones(ah); iowrite32_mac(reg, val); } } static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; struct ath_hal *ah = sc->sc_ah; int i; struct registerWrite { a_uint32_t reg; a_uint32_t val; }*t; for (i = 0; i < datalen; i += sizeof(struct registerWrite)) { t = (struct registerWrite *)(data+i); ath_hal_reg_write_filter(ah, t->reg, t->val); } wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); } static void ath_hal_reg_rmw_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; struct ath_hal *ah = sc->sc_ah; struct register_rmw *buf = (struct register_rmw *)data; int i; for (i = 0; i < datalen; i += sizeof(struct register_rmw)) { a_uint32_t val; buf = (struct register_rmw *)(data + i); val = ath_reg_read_filter(ah, buf->reg); val &= ~buf->clr; val |= buf->set; ath_hal_reg_write_filter(ah, buf->reg, val); } wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); } static void ath_vap_delete_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; a_uint8_t vap_index; vap_index = *(a_uint8_t *)data; sc->sc_vap[vap_index].av_valid = 0; sc->sc_vap[vap_index].av_bcbuf = NULL; ath_node_vdelete_tgt(sc, vap_index); wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); } static void ath_disable_intr_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; struct ath_hal *ah = sc->sc_ah; ah->ah_setInterrupts(ah, 0); wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0); } static void ath_flushrecv_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; struct ath_rx_buf *bf; asf_tailq_foreach(bf, &sc->sc_rxbuf, bf_list) if (bf->bf_skb != NULL) { adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap, ADF_OS_DMA_FROM_DEVICE); ath_free_rx_skb(sc, adf_nbuf_queue_remove(&bf->bf_skbhead)); bf->bf_skb = NULL; } wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); } static void ath_tx_draintxq_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; a_uint32_t q = *(a_uint32_t *)data; struct ath_txq *txq = NULL; q = adf_os_ntohl(q); txq = ATH_TXQ(sc, q); ath_tx_draintxq(sc, txq); wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); } static void ath_draintxq_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; HAL_BOOL b = (HAL_BOOL) *(a_int32_t *)data; ath_draintxq(Context, b); wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); } static void ath_aborttx_dma_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; struct ath_hal *ah = sc->sc_ah; ah->ah_abortTxDma(sc->sc_ah); wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); } static void ath_aborttxq_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; a_uint16_t i; for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { if (ATH_TXQ_SETUP(sc, i)) ath_tx_draintxq(sc, ATH_TXQ(sc,i)); } wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); } static void ath_stop_tx_dma_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; struct ath_hal *ah = sc->sc_ah; a_uint32_t q; if (!datalen) goto done; q = *(a_uint32_t *)data; q = adf_os_ntohl(q); ah->ah_stopTxDma(ah, q); done: wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); } static void ath_startrecv_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; ath_startrecv(sc); wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); } static void ath_stoprecv_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; struct ath_hal *ah = sc->sc_ah; ah->ah_stopPcuReceive(ah); ah->ah_setRxFilter(ah, 0); ah->ah_stopDmaReceive(ah); sc->sc_rxlink = NULL; wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); } static void ath_setcurmode_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; a_uint16_t mode; mode= *((a_uint16_t *)data); mode = adf_os_ntohs(mode); ath_setcurmode(sc, mode); wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); } static void ath_detach_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; struct ath_hal *ah = sc->sc_ah; ath_desc_free(sc); ah->ah_detach(ah); wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); adf_os_mem_free(sc); } static void handle_echo_command(void *pContext, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length) { wmi_cmd_rsp(pContext, WMI_ECHO_CMDID, SeqNo, buffer, Length); } static void handle_rc_state_change_cmd(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; struct wmi_rc_state_change_cmd *wmi_data = (struct wmi_rc_state_change_cmd *)buffer; a_uint32_t capflag = adf_os_ntohl(wmi_data->capflag); ath_rate_newstate(sc, &sc->sc_vap[wmi_data->vap_index].av_vap, wmi_data->vap_state, capflag, &wmi_data->rs); wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); } static void handle_rc_rate_update_cmd(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; struct wmi_rc_rate_update_cmd *wmi_data = (struct wmi_rc_rate_update_cmd *)buffer; a_uint32_t capflag = adf_os_ntohl(wmi_data->capflag); ath_rate_node_update(sc, &sc->sc_sta[wmi_data->node_index], wmi_data->isNew, capflag, &wmi_data->rs); wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); } static void dispatch_magpie_sys_cmds(void *pContext, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length) { adf_os_assert(0); } static void ath_rc_mask_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; struct wmi_rc_rate_mask_cmd *wmi_data = (struct wmi_rc_rate_mask_cmd *)buffer; int idx, band, i; idx = wmi_data->vap_index; band = wmi_data->band; sc->sc_vap[idx].av_rate_mask[band] = adf_os_ntohl(wmi_data->mask); if (sc->sc_vap[idx].av_rate_mask[band]) { for (i = 0; i < RATE_TABLE_SIZE; i++) { if ((1 << i) & sc->sc_vap[idx].av_rate_mask[band]) { sc->sc_vap[idx].av_minrateidx[band] = i; break; } } } else { sc->sc_vap[idx].av_minrateidx[band] = 0; } wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); } static WMI_DISPATCH_ENTRY Magpie_Sys_DispatchEntries[] = { {handle_echo_command, WMI_ECHO_CMDID, 0}, {dispatch_magpie_sys_cmds, WMI_ACCESS_MEMORY_CMDID, 0}, {ath_get_tgt_version, WMI_GET_FW_VERSION, 0}, {ath_disable_intr_tgt, WMI_DISABLE_INTR_CMDID, 0}, {ath_enable_intr_tgt, WMI_ENABLE_INTR_CMDID, 0}, {ath_init_tgt, WMI_ATH_INIT_CMDID, 0}, {ath_aborttxq_tgt, WMI_ABORT_TXQ_CMDID, 0}, {ath_stop_tx_dma_tgt, WMI_STOP_TX_DMA_CMDID, 0}, {ath_aborttx_dma_tgt, WMI_ABORT_TX_DMA_CMDID, 0}, {ath_tx_draintxq_tgt, WMI_DRAIN_TXQ_CMDID, 0}, {ath_draintxq_tgt, WMI_DRAIN_TXQ_ALL_CMDID, 0}, {ath_startrecv_tgt, WMI_START_RECV_CMDID, 0}, {ath_stoprecv_tgt, WMI_STOP_RECV_CMDID, 0}, {ath_flushrecv_tgt, WMI_FLUSH_RECV_CMDID, 0}, {ath_setcurmode_tgt, WMI_SET_MODE_CMDID, 0}, {ath_node_create_tgt, WMI_NODE_CREATE_CMDID, 0}, {ath_node_cleanup_tgt, WMI_NODE_REMOVE_CMDID, 0}, {ath_vap_delete_tgt, WMI_VAP_REMOVE_CMDID, 0}, {ath_vap_create_tgt, WMI_VAP_CREATE_CMDID, 0}, {ath_hal_reg_read_tgt, WMI_REG_READ_CMDID, 0}, {ath_hal_reg_write_tgt, WMI_REG_WRITE_CMDID, 0}, {handle_rc_state_change_cmd, WMI_RC_STATE_CHANGE_CMDID, 0}, {handle_rc_rate_update_cmd, WMI_RC_RATE_UPDATE_CMDID, 0}, {ath_ic_update_tgt, WMI_TARGET_IC_UPDATE_CMDID, 0}, {ath_enable_aggr_tgt, WMI_TX_AGGR_ENABLE_CMDID, 0}, {ath_detach_tgt, WMI_TGT_DETACH_CMDID, 0}, {ath_node_update_tgt, WMI_NODE_UPDATE_CMDID, 0}, {ath_int_stats_tgt, WMI_INT_STATS_CMDID, 0}, {ath_tx_stats_tgt, WMI_TX_STATS_CMDID, 0}, {ath_rx_stats_tgt, WMI_RX_STATS_CMDID, 0}, {ath_rc_mask_tgt, WMI_BITRATE_MASK_CMDID, 0}, {ath_hal_reg_rmw_tgt, WMI_REG_RMW_CMDID, 0}, }; /*****************/ /* Init / Deinit */ /*****************/ static void htc_setup_comp(void) { } static A_UINT8 tgt_ServiceConnect(HTC_SERVICE *pService, HTC_ENDPOINT_ID eid, A_UINT8 *pDataIn, a_int32_t LengthIn, A_UINT8 *pDataOut, a_int32_t *pLengthOut) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)pService->ServiceCtx; switch(pService->ServiceID) { case WMI_CONTROL_SVC: sc->wmi_command_ep= eid; break; case WMI_BEACON_SVC: sc->beacon_ep= eid; break; case WMI_CAB_SVC: sc->cab_ep= eid; break; case WMI_UAPSD_SVC: sc->uapsd_ep= eid; break; case WMI_MGMT_SVC: sc->mgmt_ep= eid; break; case WMI_DATA_VO_SVC: sc->data_VO_ep = eid; break; case WMI_DATA_VI_SVC: sc->data_VI_ep = eid; break; case WMI_DATA_BE_SVC: sc->data_BE_ep = eid; break; case WMI_DATA_BK_SVC: sc->data_BK_ep = eid; break; default: adf_os_assert(0); } return HTC_SERVICE_SUCCESS; } static void tgt_reg_service(struct ath_softc_tgt *sc, HTC_SERVICE *svc, int svcId, HTC_SERVICE_ProcessRecvMsg recvMsg) { svc->ProcessRecvMsg = recvMsg; svc->ProcessSendBufferComplete = tgt_HTCSendCompleteHandler; svc->ProcessConnect = tgt_ServiceConnect; svc->MaxSvcMsgSize = 1600; svc->TrailerSpcCheckLimit = 0; svc->ServiceID = svcId; svc->ServiceCtx = sc; HTC_RegisterService(sc->tgt_htc_handle, svc); } static void tgt_hif_htc_wmi_init(struct ath_softc_tgt *sc) { HTC_CONFIG htc_conf; WMI_SVC_CONFIG wmiConfig; WMI_DISPATCH_TABLE *Magpie_Sys_Commands_Tbl; /* Init dynamic buf pool */ sc->pool_handle = BUF_Pool_init(sc->sc_hdl); /* Init target-side HIF */ sc->tgt_hif_handle = HIF_init(0); /* Init target-side HTC */ htc_conf.HIFHandle = sc->tgt_hif_handle; htc_conf.CreditSize = 320; htc_conf.CreditNumber = ATH_TXBUF; htc_conf.OSHandle = sc->sc_hdl; htc_conf.PoolHandle = sc->pool_handle; sc->tgt_htc_handle = HTC_init(htc_setup_comp, &htc_conf); #if defined(PROJECT_MAGPIE) init_htc_handle = sc->tgt_htc_handle; #endif tgt_reg_service(sc, &sc->htc_beacon_service, WMI_BEACON_SVC, tgt_HTCRecv_beaconhandler); tgt_reg_service(sc, &sc->htc_cab_service, WMI_CAB_SVC, tgt_HTCRecv_cabhandler); tgt_reg_service(sc, &sc->htc_uapsd_service, WMI_UAPSD_SVC, tgt_HTCRecv_uapsdhandler); tgt_reg_service(sc, &sc->htc_mgmt_service, WMI_MGMT_SVC, tgt_HTCRecv_mgmthandler); tgt_reg_service(sc, &sc->htc_data_BE_service, WMI_DATA_BE_SVC, tgt_HTCRecvMessageHandler); tgt_reg_service(sc, &sc->htc_data_BK_service, WMI_DATA_BK_SVC, tgt_HTCRecvMessageHandler); tgt_reg_service(sc, &sc->htc_data_VI_service, WMI_DATA_VI_SVC, tgt_HTCRecvMessageHandler); tgt_reg_service(sc, &sc->htc_data_VO_service, WMI_DATA_VO_SVC, tgt_HTCRecvMessageHandler); /* Init target-side WMI */ Magpie_Sys_Commands_Tbl = (WMI_DISPATCH_TABLE *)adf_os_mem_alloc(sizeof(WMI_DISPATCH_TABLE)); adf_os_mem_zero(Magpie_Sys_Commands_Tbl, sizeof(WMI_DISPATCH_TABLE)); Magpie_Sys_Commands_Tbl->NumberOfEntries = WMI_DISPATCH_ENTRY_COUNT(Magpie_Sys_DispatchEntries); Magpie_Sys_Commands_Tbl->pTable = Magpie_Sys_DispatchEntries; adf_os_mem_zero(&wmiConfig, sizeof(WMI_SVC_CONFIG)); wmiConfig.HtcHandle = sc->tgt_htc_handle; wmiConfig.PoolHandle = sc->pool_handle; wmiConfig.MaxCmdReplyEvts = ATH_WMI_MAX_CMD_REPLY; wmiConfig.MaxEventEvts = ATH_WMI_MAX_EVENTS; sc->tgt_wmi_handle = WMI_Init(&wmiConfig); Magpie_Sys_Commands_Tbl->pContext = sc; WMI_RegisterDispatchTable(sc->tgt_wmi_handle, Magpie_Sys_Commands_Tbl); HTC_NotifyTargetInserted(sc->tgt_htc_handle); /* Start HTC messages exchange */ HTC_Ready(sc->tgt_htc_handle); } a_int32_t ath_tgt_attach(a_uint32_t devid, struct ath_softc_tgt *sc, adf_os_device_t osdev) { struct ath_hal *ah; HAL_STATUS status; a_int32_t error = 0, i, flags = 0; a_uint8_t csz; adf_os_pci_config_read8(osdev, ATH_PCI_CACHE_LINE_SIZE, &csz); if (csz == 0) csz = 16; sc->sc_cachelsz = csz << 2; sc->sc_dev = osdev; sc->sc_hdl = osdev; ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_rxtq, ath_tgt_rx_tasklet, sc); ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_txtq, owl_tgt_tx_tasklet, sc); ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_bmisstq, ath_bmiss_tasklet, sc); ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_fataltq, ath_fatal_tasklet, sc); flags |= AH_USE_EEPROM; ah = _ath_hal_attach_tgt(devid, sc, sc->sc_dev, flags, &status); if (ah == NULL) { error = ENXIO; goto bad; } sc->sc_ah = ah; tgt_hif_htc_wmi_init(sc); sc->sc_bhalq = HAL_NUM_TX_QUEUES - 1; ath_rate_setup(sc, IEEE80211_MODE_11NA); ath_rate_setup(sc, IEEE80211_MODE_11NG); sc->sc_rc = ath_rate_attach(sc); if (sc->sc_rc == NULL) { error = EIO; goto bad2; } for (i=0; i < TARGET_NODE_MAX; i++) { sc->sc_sta[i].an_rcnode = adf_os_mem_alloc(sc->sc_rc->arc_space); } error = ath_desc_alloc(sc); if (error != 0) { goto bad; } BUF_Pool_create_pool(sc->pool_handle, POOL_ID_WLAN_RX_BUF, ath_numrxdescs, 1664); ath_tgt_txq_setup(sc); sc->sc_imask =0; ah->ah_setInterrupts(ah, 0); return 0; bad: bad2: ath_desc_free(sc); if (ah) ah->ah_detach(ah); } static void tgt_hif_htc_wmi_shutdown(struct ath_softc_tgt *sc) { HTC_NotifyTargetDetached(sc->tgt_htc_handle); WMI_Shutdown(sc->tgt_wmi_handle); HTC_Shutdown(sc->tgt_htc_handle); HIF_shutdown(sc->tgt_hif_handle); BUF_Pool_shutdown(sc->pool_handle); } a_int32_t ath_detach(struct ath_softc_tgt *sc) { tgt_hif_htc_wmi_shutdown(sc); } open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/if_ath_pci.c000077500000000000000000000151101321570333100267600ustar00rootroot00000000000000/*- * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting * Copyright (c) 2004 Atheros Communications, Inc. * Copyright (c) 2013 Qualcomm Atheros, Inc. * * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * Alternatively, this software may be distributed under the terms of the * GNU General Public License ("GPL") version 2 as published by the Free * Software Foundation. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef EXPORT_SYMTAB #define EXPORT_SYMTAB #endif #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "if_athvar.h" #include "if_ath_pci.h" extern a_int32_t ath_tgt_attach(a_uint32_t devid, struct ath_softc_tgt *sc, adf_os_device_t osdev); extern a_int32_t ath_detach(void *); extern adf_os_irq_resp_t ath_intr(adf_drv_handle_t hdl); struct ath_pci_softc { struct ath_softc_tgt aps_sc; #ifdef CONFIG_PM u32 ps_pmstate[16]; #endif }; /* * User a static table of PCI id's for now. While this is the * "new way" to do things, we may want to switch back to having * the HAL check them by defining a probe method. */ #ifdef ATH_SUPPORT_XB_ONLY static adf_os_pci_dev_id_t ath_pci_id_table[] = { { 0x168c, 0x0024, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, /* PCI-E (XB) */ { 0 }, }; #else static adf_os_pci_dev_id_t ath_pci_id_table[] = { { 0x168c, 0x0007, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, { 0x168c, 0x0012, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, { 0x168c, 0x0013, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, { 0xa727, 0x0013, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, /* 3com */ { 0x10b7, 0x0013, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, /* 3com 3CRDAG675 */ { 0x168c, 0x1014, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, /* IBM minipci 5212 */ { 0x168c, 0x101a, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, /* some Griffin-Lite */ { 0x168c, 0x0015, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, { 0x168c, 0x0016, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, { 0x168c, 0x0017, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, { 0x168c, 0x0018, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, { 0x168c, 0x0019, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, { 0x168c, 0x001a, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, { 0x168c, 0x001b, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, { 0x168c, 0x001c, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, { 0x168c, 0x001d, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, { 0x168c, 0xff1d, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, /* owl emulation */ { 0x168c, 0xff1c, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, /* owl emulation */ { 0x168c, 0x0023, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, /* PCI (MB/CB) */ { 0x168c, 0x0024, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, /* PCI-E (XB) */ { 0x168c, 0x0027, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, /* Sowl PCI */ { 0 }, }; #endif void exit_ath_pci(void); a_int32_t init_ath_pci(void); static adf_drv_handle_t ath_pci_probe(adf_os_resource_t *res,a_int32_t count, adf_os_attach_data_t *data, adf_os_device_t osdev) { struct ath_pci_softc *sc; a_uint8_t csz = 32; adf_os_pci_dev_id_t *id = (adf_os_pci_dev_id_t *)data; adf_os_pci_config_write8(osdev, ATH_PCI_CACHE_LINE_SIZE, csz); adf_os_pci_config_write8(osdev, ATH_PCI_LATENCY_TIMER, 0xa8); sc = adf_os_mem_alloc(sizeof(struct ath_pci_softc)); if (sc == NULL) { adf_os_print("ath_pci: no memory for device state\n"); goto bad2; } adf_os_mem_set(sc, 0, sizeof(struct ath_pci_softc)); /* * Mark the device as detached to avoid processing * interrupts until setup is complete. */ sc->aps_sc.sc_invalid = 1; adf_os_print("ath_pci_probe %x\n",id->device); if (ath_tgt_attach(id->device, &sc->aps_sc, osdev) != 0) goto bad3; /* ready to process interrupts */ sc->aps_sc.sc_invalid = 0; adf_os_setup_intr(osdev, ath_intr); return (adf_drv_handle_t)sc; bad3: bad2: return NULL; } static void ath_pci_remove(adf_drv_handle_t hdl) { struct ath_softc_tgt *sc = hdl; ath_detach((struct ath_softc_tgt *)hdl); adf_os_free_intr(sc->sc_dev); } static void ath_pci_suspend(adf_drv_handle_t hdl, adf_os_pm_t pm) { } static void ath_pci_resume(adf_drv_handle_t hdl) { } static adf_drv_info_t ath_drv_info = adf_os_pci_set_drv_info(ath_pci_tgt,&ath_pci_id_table[0], ath_pci_probe, ath_pci_remove, ath_pci_suspend, ath_pci_resume); a_int32_t init_ath_pci(void) { return adf_net_register_drv( &ath_drv_info ); } void exit_ath_pci(void) { adf_net_unregister_drv("ath_pci"); } adf_os_pci_module_init(init_ath_pci); adf_os_pci_module_exit(exit_ath_pci); adf_os_module_dep(ath_pci_tgt, adf_net); adf_os_module_dep(ath_pci_tgt, hal); adf_os_module_dep(ath_pci_tgt, ath_pci); adf_os_module_dep(ath_pci_tgt, wlan_tgt); adf_os_module_dep(ath_pci_tgt, htc_tgt); adf_os_module_dep(ath_pci_tgt, inproc_hif); open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/if_ath_pci.h000077500000000000000000000042241321570333100267710ustar00rootroot00000000000000/*- * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting * Copyright (c) 2004 Atheros Communications, Inc. * Copyright (c) 2013 Qualcomm Atheros, Inc. * * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * Alternatively, this software may be distributed under the terms of the * GNU General Public License ("GPL") version 2 as published by the Free * Software Foundation. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _DEV_ATH_PCI_H_ #define _DEV_ATH_PCI_H_ #define ATH_PCI_CACHE_LINE_SIZE 0x0c #define ATH_PCI_LATENCY_TIMER 0x0d #endif /* _DEV_ATH_PCI_H_ */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/if_athrate.h000077500000000000000000000106101321570333100270060ustar00rootroot00000000000000/*- * Copyright (c) 2004 Sam Leffler, Errno Consulting * Copyright (c) 2004 Video54 Technologies, Inc. * Copyright (c) 2013 Qualcomm Atheros, Inc. * * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * Alternatively, this software may be distributed under the terms of the * GNU General Public License ("GPL") version 2 as published by the Free * Software Foundation. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _ATH_RATECTRL_H_ #define _ATH_RATECTRL_H_ struct ath_softc_tgt; struct ath_node; struct ath_node_target; struct ath_desc; struct ieee80211vap; struct ieee80211com_target; struct ath_tx_desc; struct ath_ratectrl { size_t arc_space; /* space required for per-node state */ }; #define ATH_RC_DS_FLAG 0x01 #define ATH_RC_CW40_FLAG 0x02 #define ATH_RC_HT40_SGI_FLAG 0x04 #define ATH_RC_HT_FLAG 0x08 #define ATH_RC_RTSCTS_FLAG 0x10 #define ATH_RC_TX_STBC_FLAG 0x20 /* TX STBC */ #define ATH_RC_RX_STBC_FLAG 0xC0 /* RX STBC ,2 bits */ #define ATH_RC_RX_STBC_FLAG_S 6 #define ATH_RC_WEP_TKIP_FLAG 0x100 /* WEP/TKIP encryption */ enum ath_rc_cwmode{ ATH_RC_CW20_MODE, ATH_RC_CW40_MODE, }; #define ATH_RC_PROBE_ALLOWED 0x00000001 #define ATH_RC_MINRATE_LASTRATE 0x00000002 struct ath_rc_series { a_uint8_t rix; a_uint8_t tries; u_int8_t tx_chainmask; a_uint8_t flags; a_uint32_t max4msframelen; a_uint32_t txrateKbps; }; /* * Attach/detach a rate control module. */ struct ath_ratectrl *ath_rate_attach(struct ath_softc_tgt *); /* * Return the transmit info for a data packet. If multi-rate state * is to be setup then try0 should contain a value other than ATH_TXMATRY * and ath_rate_setupxtxdesc will be called after deciding if the frame * can be transmitted with multi-rate retry. */ void ath_rate_findrate(struct ath_softc_tgt *sc, struct ath_node_target *an, a_int32_t shortPreamble, size_t frameLen, a_int32_t numTries, a_int32_t numRates, a_int32_t stepDnInc, a_uint32_t rcflag, struct ath_rc_series series[], a_int32_t *isProbe); /* * Update rate control state for a packet associated with the * supplied transmit descriptor. The routine is invoked both * for packets that were successfully sent and for those that * failed (consult the descriptor for details). */ void ath_rate_tx_complete(struct ath_softc_tgt *, struct ath_node_target *, struct ath_tx_desc *, struct ath_rc_series series[], a_int32_t nframes, a_int32_t nbad); void ath_rate_stateupdate(struct ath_softc_tgt *sc, struct ath_node_target *an, enum ath_rc_cwmode cwmode); void ath_tx_status_update_rate(struct ath_softc_tgt *sc, struct ath_rc_series rcs[], int series, WMI_TXSTATUS_EVENT *txs); #endif /* _ATH_RATECTRL_H_ */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/if_athvar.h000077500000000000000000000412341321570333100266510ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _DEV_ATH_ATHVAR_H #define _DEV_ATH_ATHVAR_H #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "ah.h" #include "ieee80211_var.h" #include "ieee80211_node.h" #include "if_athrate.h" #include #include #include #include #include #include #define tq_struct adf_os_bh_t #define ATH_INIT_TQUEUE(a,b,c,d) adf_os_init_bh((a),(b),(c),(void *)(d)) #define ATH_SCHEDULE_TQUEUE(a,b) adf_os_sched_bh((a),(b)) typedef void * TQUEUE_ARG; #define ATH_MIN(a,b) ((a) < (b) ? (a) : (b)) #define ATH_AC_2_TXQ(_sc, _ac) (_sc)->sc_ac2q[(_ac)] #define TID_TO_ACTXQ(tidno) sc->sc_ac2q[ TID_TO_WME_AC(tidno)] #define RATE_TABLE_SIZE 32 #define INCR(_l, _sz) (_l) ++; (_l) &= ((_sz) - 1) #define IEEE80211_SEQ_MAX 4096 #define SEQNO_FROM_BF_SEQNO(_x) (_x >> IEEE80211_SEQ_SEQ_SHIFT) #define BAW_WITHIN(_start, _bawsz, _seqno) \ ((((_seqno) - (_start)) & 4095) < (_bawsz)) #define __stats(sc, _x) sc->sc_tx_stats._x ++ #define __statsn(sc, _x, _n) sc->sc_tx_stats._x += _n #define IS_HT_RATE(_rate) ((_rate) & 0x80) typedef enum { ATH_TGT_AGGR_DONE, ATH_TGT_AGGR_BAW_CLOSED, ATH_TGT_AGGR_LIMITED, ATH_AGGR_SHORTPKT, ATH_AGGR_8K_LIMITED, } ATH_AGGR_STATUS; #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \ ((_bm)[(_n) >> 5] & (1 << ((_n) & 31)))) #define ATH_DS_BA_SEQ(_ds) ((struct ath_tx_desc *)_ds)->ds_us.tx.ts_seqnum #define ATH_DS_BA_BITMAP(_ds) (&((struct ath_tx_desc *)_ds)->ds_us.tx.ba_low) #define ATH_DS_TX_BA(_ds) (((struct ath_tx_desc *)_ds)->ds_us.tx.ts_flags & HAL_TX_BA) #define ATH_DS_TX_STATUS(_ds) ((struct ath_tx_desc *)_ds)->ds_us.tx.ts_status #define ATH_DS_TX_FLAGS(_ds) ((struct ath_tx_desc *)_ds)->ds_us.tx.ts_flags #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1)) #define ATH_AGGR_DELIM_SZ 4 #define ATH_AGGR_MINPLEN 256 #define ATH_AGGR_ENCRYPTDELIM 10 #define ATH_AGGR_GET_NDELIM(_len) \ (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \ (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2) #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4) #define OWLMAX_RETRIES 10 #define OWLMAX_BAR_RETRIES 10 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)]) #define ATH_TXDESC 1 #define ATH_TXMAXTRY 11 #define TARGET_NODE_MAX ATH_NODE_MAX #define TARGET_VAP_MAX ATH_VAP_MAX #define MAX_RATE_POWER 63 #define ATH_COMP_PROC_NO_COMP_NO_CCS 3 #define ATH_BUFSTATUS_DONE 0x00000001 /* hw processing complete, desc processed by hal */ #define ATH_AGGR_MIN_QDEPTH 1 struct ath_softc_tgt; struct ath_buf; struct ath_txq; #define ATH_TXQ(_sc, _qi) (&(_sc)->sc_txq[(_qi)]) #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<pool_handle, POOL_ID_WLAN_RX_BUF, _skb) #define ath_free_tx_skb(_htc_handle, endpt, _skb) HTC_ReturnBuffers(_htc_handle, endpt, _skb); struct ath_tx_buf; typedef void (*ath_txq_add_fn_t)(struct ath_softc_tgt *sc, struct ath_tx_buf *bf); typedef void (*ath_tx_comp_fn_t)(struct ath_softc_tgt *sc, struct ath_tx_buf *bf); struct ath_buf_state { ath_tx_comp_fn_t bfs_comp; /* completion function */ ath_txq_add_fn_t bfs_txq_add; /* txq buffer add function */ a_uint16_t bfs_pktlen; /* pktlen including crc */ a_uint16_t bfs_seqno; /* sequence nuber */ a_uint8_t bfs_hdrlen; /* header length */ a_uint8_t bfs_keyix; /* key index */ a_uint8_t bfs_atype; /* packet type */ a_uint8_t bfs_ndelim; /* # delims for padding */ a_uint8_t bfs_nframes; /* # frames in aggregate */ a_uint8_t bfs_tidno; /* tid of the buffer */ a_uint16_t bfs_al; /* length of aggregate */ struct ath_rc_series bfs_rcs[4]; /* rate series */ struct ath_txq *bfs_txq; /* transmit h/w queue */ a_uint8_t bfs_protmode; /* protection mode */ a_uint8_t bfs_keytype; /* encr key type */ a_uint8_t bfs_retries; /* current retries */ a_uint32_t bfs_ismcast : 1; /* is multicast */ a_uint32_t bfs_shpream : 1; /* use short preamble */ a_uint32_t bfs_isaggr : 1; /* is an aggregate */ a_uint32_t bfs_isretried: 1; /* is retried */ }; #define bf_comp bf_state.bfs_comp #define bf_txq_add bf_state.bfs_txq_add #define bf_pktlen bf_state.bfs_pktlen #define bf_hdrlen bf_state.bfs_hdrlen #define bf_keyix bf_state.bfs_keyix #define bf_atype bf_state.bfs_atype #define bf_seqno bf_state.bfs_seqno #define bf_ndelim bf_state.bfs_ndelim #define bf_nframes bf_state.bfs_nframes #define bf_al bf_state.bfs_al #define bf_tidno bf_state.bfs_tidno #define bf_rcs bf_state.bfs_rcs #define bf_txq bf_state.bfs_txq #define bf_protmode bf_state.bfs_protmode #define bf_keytype bf_state.bfs_keytype #define bf_ismcast bf_state.bfs_ismcast #define bf_shpream bf_state.bfs_shpream #define bf_isaggr bf_state.bfs_isaggr #define bf_isretried bf_state.bfs_isretried #define bf_retries bf_state.bfs_retries #define ATH_GENERIC_BUF \ adf_os_dma_map_t bf_dmamap; \ adf_os_dmamap_info_t bf_dmamap_info; \ struct ieee80211_node_target *bf_node; \ adf_nbuf_queue_t bf_skbhead; \ adf_nbuf_t bf_skb; struct ath_buf { ATH_GENERIC_BUF asf_tailq_entry(ath_buf) bf_list; struct ath_buf *bf_next; struct ath_desc *bf_lastds; struct ath_desc *bf_desc; struct ath_desc *bf_descarr; }; struct ath_tx_buf { ATH_GENERIC_BUF asf_tailq_entry(ath_tx_buf) bf_list; struct ath_tx_buf *bf_next; struct ath_tx_desc *bf_desc; struct ath_tx_desc *bf_descarr; struct ath_tx_desc *bf_lastds; struct ath_buf_state bf_state; a_uint16_t bf_flags; HTC_ENDPOINT_ID bf_endpt; a_uint16_t al_delta; a_uint8_t bf_cookie; a_uint8_t vap_index; }; struct ath_rx_buf { ATH_GENERIC_BUF asf_tailq_entry(ath_rx_buf) bf_list; struct ath_rx_buf *bf_next; struct ath_rx_desc *bf_desc; struct ath_rx_desc *bf_descarr; struct ath_rx_desc *bf_lastds; a_uint32_t bf_status; struct ath_rx_status bf_rx_status; }; #define ATH_BUF_GET_DESC_PHY_ADDR(bf) (a_uint32_t)bf->bf_desc #define ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, idx) (adf_os_dma_addr_t)(&bf->bf_descarr[idx]) #define ATH_BUF_SET_DESC_PHY_ADDR(bf, addr) #define ATH_BUF_SET_DESC_PHY_ADDR_WITH_IDX(bf, idx, addr) typedef asf_tailq_head(ath_deschead_s, ath_rx_desc) ath_deschead; typedef asf_tailq_head(ath_bufhead_s, ath_buf) ath_bufhead; typedef asf_tailq_head(ath_rx_bufhead_s, ath_rx_buf) ath_rx_bufhead; typedef asf_tailq_head(ath_tx_bufhead_s, ath_tx_buf) ath_tx_bufhead; #define WME_NUM_TID 8 #define WME_BA_BMP_SIZE 64 #define WME_MAX_BA WME_BA_BMP_SIZE #define ATH_TID_MAX_BUFS (2 * WME_MAX_BA) #define TID_CLEANUP_INPROGRES 0x1 #define TID_AGGR_ENABLED 0x2 #define TID_REINITIALIZE 0x4 #define TAILQ_DEQ(_q, _elm, _field) do { \ (_elm) = asf_tailq_first((_q)); \ if (_elm) { \ asf_tailq_remove((_q), (_elm), _field); \ } \ } while (0) #define TX_BUF_BITMAP_SIZE 32 #define TX_BUF_BITMAP_SET(bitmap, i) bitmap[i>>5] |= ((a_uint32_t)1 << (i&0x1f)) #define TX_BUF_BITMAP_CLR(bitmap, i) bitmap[i>>5] &= (~((a_uint32_t)1 << (i&0x1f))) #define TX_BUF_BITMAP_IS_SET(bitmap, i) ((bitmap[i>>5] & ((a_uint32_t)1 << (i&0x1f))) != 0) typedef struct ath_atx_tid { a_int32_t tidno; a_uint16_t seq_start; a_uint16_t seq_next; a_uint16_t baw_size; a_int32_t baw_head; a_int32_t baw_tail; a_uint32_t tx_buf_bitmap[ATH_TID_MAX_BUFS/TX_BUF_BITMAP_SIZE]; asf_tailq_entry(ath_atx_tid) tid_qelem; asf_tailq_head(ath_tid_rbq,ath_tx_buf) buf_q; a_int8_t paused; a_int8_t sched; a_uint8_t flag; a_int8_t incomp; struct ath_node_target *an; } ath_atx_tid_t; struct ath_node_target { struct ieee80211_node_target ni; struct ath_atx_tid tid[WME_NUM_TID]; a_int8_t an_valid; void *an_rcnode; }; struct ath_descdma { const a_int8_t *dd_name; struct ath_desc *dd_desc; adf_os_dma_map_t dd_desc_dmamap; adf_os_dma_addr_t dd_desc_paddr; adf_os_size_t dd_desc_len; struct ath_buf *dd_bufptr; }; struct ath_txq { a_uint32_t axq_qnum; a_uint32_t *axq_link; asf_tailq_head(,ath_tx_buf) axq_q; a_uint32_t axq_depth; struct ath_tx_buf *axq_linkbuf; asf_tailq_head(,ath_atx_tid) axq_tidq; }; struct wmi_rc_rate_mask_cmd { a_uint8_t vap_index; a_uint8_t band; a_uint32_t mask; a_uint16_t pad; } POSTPACK; struct ath_vap_target { struct ieee80211vap_target av_vap; struct ath_txq av_mcastq; struct ath_tx_buf *av_bcbuf; a_uint32_t av_rate_mask[2]; /* 0 - 2G, 1 - 5G */ a_uint8_t av_minrateidx[2]; /* 0 - 2G, 1 - 5G */ a_int8_t av_valid; }; #define ATH_RXBUF_RESET(bf) \ bf->bf_status=0 struct ath_softc_tgt { /* Target-side HTC/HIF/WMI related data structure */ pool_handle_t pool_handle; hif_handle_t tgt_hif_handle; htc_handle_t tgt_htc_handle; wmi_handle_t tgt_wmi_handle; /* Target HTC Service IDs */ HTC_SERVICE htc_beacon_service; HTC_SERVICE htc_cab_service; HTC_SERVICE htc_uapsd_service; HTC_SERVICE htc_mgmt_service; HTC_SERVICE htc_data_VO_service; HTC_SERVICE htc_data_VI_service; HTC_SERVICE htc_data_BE_service; HTC_SERVICE htc_data_BK_service; /* Target HTC Endpoint IDs */ HTC_ENDPOINT_ID wmi_command_ep; HTC_ENDPOINT_ID beacon_ep; HTC_ENDPOINT_ID cab_ep; HTC_ENDPOINT_ID uapsd_ep; HTC_ENDPOINT_ID mgmt_ep; HTC_ENDPOINT_ID data_VO_ep; HTC_ENDPOINT_ID data_VI_ep; HTC_ENDPOINT_ID data_BE_ep; HTC_ENDPOINT_ID data_BK_ep; adf_os_handle_t sc_hdl; adf_os_device_t sc_dev; a_uint8_t sc_bhalq; struct ath_ratectrl *sc_rc; a_uint32_t sc_invalid : 1, sc_tx_draining : 1, sc_enable_coex : 1; a_int32_t sc_rxbufsize; a_uint16_t sc_cachelsz; struct ath_interrupt_stats sc_int_stats; struct ath_tx_stats sc_tx_stats; struct ath_rx_stats sc_rx_stats; const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; const HAL_RATE_TABLE *sc_currates; a_uint8_t sc_rixmap[256]; enum ieee80211_phymode sc_curmode; a_uint8_t sc_protrix; HAL_INT sc_imask; tq_struct sc_rxtq; tq_struct sc_bmisstq; tq_struct sc_txtotq; tq_struct sc_fataltq; ath_rx_bufhead sc_rxbuf; ath_deschead sc_rxdesc_idle; ath_deschead sc_rxdesc; struct ath_rx_desc *sc_rxdesc_held; struct ath_tx_buf *sc_txbuf_held; struct ath_descdma sc_rxdma; struct ath_descdma sc_txdma; struct ath_descdma sc_bdma; a_uint32_t *sc_rxlink; ath_tx_bufhead sc_txbuf; a_uint8_t sc_txqsetup; struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; struct ath_txq *sc_ac2q[WME_NUM_AC]; tq_struct sc_txtq; struct ath_hal *sc_ah; struct ath_txq *sc_cabq; struct ath_txq *sc_uapsdq; struct ath_node_target sc_sta[TARGET_NODE_MAX]; struct ath_vap_target sc_vap[TARGET_VAP_MAX]; struct ieee80211com_target sc_ic; ath_tx_bufhead sc_bbuf; a_uint64_t sc_swba_tsf; WMI_TXSTATUS_EVENT tx_status[2]; }; #define SM(_v, _f) (((_v) << _f##_S) & _f) #define MS(_v, _f) (((_v) & _f) >> _f##_S) #define ATH9K_HTC_TXSTAT_ACK 1<<0 #define ATH9K_HTC_TXSTAT_FILT 1<<1 #define ATH9K_HTC_TXSTAT_RTC_CTS 1<<2 #define ATH9K_HTC_TXSTAT_MCS 1<<3 #define ATH9K_HTC_TXSTAT_CW40 1<<4 #define ATH9K_HTC_TXSTAT_SGI 1<<5 #define ATH9K_HTC_TXSTAT_RATE 0x0f #define ATH9K_HTC_TXSTAT_RATE_S 0 #define ATH9K_HTC_TXSTAT_EPID 0xf0 #define ATH9K_HTC_TXSTAT_EPID_S 4 #define TAILQ_INSERTQ_HEAD(head, tq, field) do { \ if ((head)->tqh_first) { \ *(tq)->tqh_last = (head)->tqh_first; \ (head)->tqh_first->field.tqe_prev = (tq)->tqh_last; \ } else { \ (head)->tqh_last = (tq)->tqh_last; \ } \ (head)->tqh_first = (tq)->tqh_first; \ (tq)->tqh_first->field.tqe_prev = &(head)->tqh_first; \ } while (0) #define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ asf_tailq_insert_tail( &(_tq)->axq_q, (_elm), _field); \ (_tq)->axq_depth++; \ (_tq)->axq_linkbuf = (_elm); \ } while (0) #define ATH_TXQ_REMOVE_HEAD(_tq, _elm, _field) do { \ asf_tailq_remove(&(_tq)->axq_q, (_elm), _field); \ (_tq)->axq_depth--; \ } while (0) struct ieee80211_rate { struct ieee80211_rateset rates; struct ieee80211_rateset htrates; } __attribute__((packed)); struct wmi_rc_state_change_cmd { a_uint8_t vap_index; a_uint8_t vap_state; a_uint8_t pad[2]; a_uint32_t capflag; struct ieee80211_rate rs; } __attribute__((packed)); struct wmi_rc_rate_update_cmd { a_uint8_t node_index; a_uint8_t isNew; a_uint8_t pad[2]; a_uint32_t capflag; struct ieee80211_rate rs; } __attribute__((packed)); typedef enum { OWL_TXQ_ACTIVE = 0, OWL_TXQ_STOPPED, OWL_TXQ_FILTERED, } owl_txq_state_t; a_uint8_t ath_get_minrateidx(struct ath_softc_tgt *sc, struct ath_vap_target *avp); void ath_tgt_tx_cleanup(struct ath_softc_tgt *sc, struct ath_node_target *an, ath_atx_tid_t *tid, a_uint8_t discard_all); void ath_tgt_handle_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf); void ath_tgt_handle_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf); void ath_tgt_tid_drain(struct ath_softc_tgt *sc, struct ath_atx_tid *tid); void ath_tx_status_clear(struct ath_softc_tgt *sc); void wmi_event(wmi_handle_t handle, WMI_EVENT_ID evt_id, void *buffer, a_int32_t Length); #endif /* _DEV_ATH_ATHVAR_H */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/if_llc.h000077500000000000000000000152031321570333100261330ustar00rootroot00000000000000/*- * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting * Copyright (c) 2013 Qualcomm Atheros, Inc. * * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * Alternatively, this software may be distributed under the terms of the * GNU General Public License ("GPL") version 2 as published by the Free * Software Foundation. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * Copyright (c) 1988, 1993 * The Regents of the University of California. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by the University of * California, Berkeley and its contributors. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * @(#)if_llc.h 8.1 (Berkeley) 6/10/93 * $FreeBSD: src/sys/net/if_llc.h,v 1.9 2002/09/23 06:25:08 alfred Exp $ */ #ifndef _NET_IF_LLC_H_ #define _NET_IF_LLC_H_ /* * IEEE 802.2 Link Level Control headers, for use in conjunction with * 802.{3,4,5} media access control methods. * * Headers here do not use bit fields due to shortcommings in many * compilers. */ struct llc { a_uint8_t llc_dsap; a_uint8_t llc_ssap; union { struct { a_uint8_t control; a_uint8_t format_id; a_uint8_t class; a_uint8_t window_x2; } adf_os_packed type_u; struct { a_uint8_t num_snd_x2; a_uint8_t num_rcv_x2; } adf_os_packed type_i; struct { a_uint8_t control; a_uint8_t num_rcv_x2; } adf_os_packed type_s; struct { a_uint8_t control; /* * We cannot put the following fields in a structure because * the structure rounding might cause padding. */ a_uint8_t frmr_rej_pdu0; a_uint8_t frmr_rej_pdu1; a_uint8_t frmr_control; a_uint8_t frmr_control_ext; a_uint8_t frmr_cause; } adf_os_packed type_frmr; struct { a_uint8_t control; a_uint8_t org_code[3]; a_uint16_t ether_type; } adf_os_packed type_snap; struct { a_uint8_t control; a_uint8_t control_ext; } adf_os_packed type_raw; } llc_un /* XXX adf_os_packed ??? */; } adf_os_packed; struct frmrinfo { a_uint8_t frmr_rej_pdu0; a_uint8_t frmr_rej_pdu1; a_uint8_t frmr_control; a_uint8_t frmr_control_ext; a_uint8_t frmr_cause; } adf_os_packed; #define llc_control llc_un.type_u.control #define llc_control_ext llc_un.type_raw.control_ext #define llc_fid llc_un.type_u.format_id #define llc_class llc_un.type_u.class #define llc_window llc_un.type_u.window_x2 #define llc_frmrinfo llc_un.type_frmr.frmr_rej_pdu0 #define llc_frmr_pdu0 llc_un.type_frmr.frmr_rej_pdu0 #define llc_frmr_pdu1 llc_un.type_frmr.frmr_rej_pdu1 #define llc_frmr_control llc_un.type_frmr.frmr_control #define llc_frmr_control_ext llc_un.type_frmr.frmr_control_ext #define llc_frmr_cause llc_un.type_frmr.frmr_cause #define llc_snap llc_un.type_snap /* * Don't use sizeof(struct llc_un) for LLC header sizes */ #define LLC_ISFRAMELEN 4 #define LLC_UFRAMELEN 3 #define LLC_FRMRLEN 7 #define LLC_SNAPFRAMELEN 8 /* * Unnumbered LLC format commands */ #define LLC_UI 0x3 #define LLC_UI_P 0x13 #define LLC_DISC 0x43 #define LLC_DISC_P 0x53 #define LLC_UA 0x63 #define LLC_UA_P 0x73 #define LLC_TEST 0xe3 #define LLC_TEST_P 0xf3 #define LLC_FRMR 0x87 #define LLC_FRMR_P 0x97 #define LLC_DM 0x0f #define LLC_DM_P 0x1f #define LLC_XID 0xaf #define LLC_XID_P 0xbf #define LLC_SABME 0x6f #define LLC_SABME_P 0x7f /* * Supervisory LLC commands */ #define LLC_RR 0x01 #define LLC_RNR 0x05 #define LLC_REJ 0x09 /* * Info format - dummy only */ #define LLC_INFO 0x00 /* * ISO PDTR 10178 contains among others */ #define LLC_X25_LSAP 0x7e #define LLC_SNAP_LSAP 0xaa #define LLC_ISO_LSAP 0xfe #endif /* _NET_IF_LLC_H_ */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/if_owl.c000077500000000000000000001507701321570333100261660ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include "if_llc.h" #ifdef USE_HEADERLEN_RESV #include #endif #include #include "if_athrate.h" #include "if_athvar.h" #include "ah_desc.h" #include "ah_internal.h" #define ath_tgt_free_skb adf_nbuf_free #define OFDM_PLCP_BITS 22 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f) #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) #define L_STF 8 #define L_LTF 8 #define L_SIG 4 #define HT_SIG 8 #define HT_STF 4 #define HT_LTF(_ns) (4 * (_ns)) #define SYMBOL_TIME(_ns) ((_ns) << 2) // ns * 4 us #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) // ns * 3.6 us static a_uint16_t bits_per_symbol[][2] = { /* 20MHz 40MHz */ { 26, 54 }, // 0: BPSK { 52, 108 }, // 1: QPSK 1/2 { 78, 162 }, // 2: QPSK 3/4 { 104, 216 }, // 3: 16-QAM 1/2 { 156, 324 }, // 4: 16-QAM 3/4 { 208, 432 }, // 5: 64-QAM 2/3 { 234, 486 }, // 6: 64-QAM 3/4 { 260, 540 }, // 7: 64-QAM 5/6 { 52, 108 }, // 8: BPSK { 104, 216 }, // 9: QPSK 1/2 { 156, 324 }, // 10: QPSK 3/4 { 208, 432 }, // 11: 16-QAM 1/2 { 312, 648 }, // 12: 16-QAM 3/4 { 416, 864 }, // 13: 64-QAM 2/3 { 468, 972 }, // 14: 64-QAM 3/4 { 520, 1080 }, // 15: 64-QAM 5/6 }; void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq, owl_txq_state_t txqstate); static void ath_tgt_txqaddbuf(struct ath_softc_tgt *sc, struct ath_txq *txq, struct ath_tx_buf *bf, struct ath_tx_desc *lastds); void ath_rate_findrate_11n_Hardcoded(struct ath_softc_tgt *sc, struct ath_rc_series series[]); void ath_buf_set_rate_Hardcoded(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) ; static a_int32_t ath_tgt_txbuf_setup(struct ath_softc_tgt *sc, struct ath_tx_buf *bf, ath_data_hdr_t *dh); static void ath_tx_freebuf(struct ath_softc_tgt *sc, struct ath_tx_buf *bf); static void ath_tx_uc_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf); static void ath_update_stats(struct ath_softc_tgt *sc, struct ath_tx_buf *bf); void adf_print_buf(adf_nbuf_t buf); static void ath_tgt_tx_enqueue(struct ath_txq *txq, struct ath_atx_tid *tid); void ath_tgt_tx_comp_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf); struct ieee80211_frame *ATH_SKB_2_WH(adf_nbuf_t skb); void ath_tgt_tx_send_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf); static void ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, ath_atx_tid_t *tid); static void ath_tgt_tx_sched_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid); extern a_int32_t ath_chainmask_sel_logic(void *); static a_int32_t ath_get_pktlen(struct ath_tx_buf *bf, a_int32_t hdrlen); static void ath_tgt_txq_schedule(struct ath_softc_tgt *sc, struct ath_txq *txq); typedef void (*ath_ft_set_atype_t)(struct ath_softc_tgt *sc, struct ath_buf *bf); static void ath_tx_set_retry(struct ath_softc_tgt *sc, struct ath_tx_buf *bf); static void ath_bar_tx(struct ath_softc_tgt *sc, ath_atx_tid_t *tid, struct ath_tx_buf *bf); static void ath_tx_update_baw(ath_atx_tid_t *tid, int seqno); static void ath_tx_retry_subframe(struct ath_softc_tgt *sc, struct ath_tx_buf *bf, ath_tx_bufhead *bf_q, struct ath_tx_buf **bar); static void ath_tx_comp_aggr_error(struct ath_softc_tgt *sc, struct ath_tx_buf *bf, ath_atx_tid_t *tid); void ath_tx_addto_baw(ath_atx_tid_t *tid, struct ath_tx_buf *bf); static inline void ath_tx_retry_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf); static void ath_tx_comp_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf); static void ath_update_aggr_stats(struct ath_softc_tgt *sc, struct ath_tx_desc *ds, int nframes, int nbad); static inline void ath_aggr_resume_tid(struct ath_softc_tgt *sc, ath_atx_tid_t *tid); static void ath_tx_comp_cleanup(struct ath_softc_tgt *sc, struct ath_tx_buf *bf); int ath_tgt_tx_add_to_aggr(struct ath_softc_tgt *sc, struct ath_buf *bf,int datatype, ath_atx_tid_t *tid, int is_burst); int ath_tgt_tx_form_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid, ath_tx_bufhead *bf_q); struct ieee80211_frame *ATH_SKB_2_WH(adf_nbuf_t skb) { a_uint8_t *anbdata; a_uint32_t anblen; adf_nbuf_peek_header(skb, &anbdata, &anblen); return((struct ieee80211_frame *)anbdata); } #undef adf_os_cpu_to_le16 static a_uint16_t adf_os_cpu_to_le16(a_uint16_t x) { return ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8)); } static inline void ath_aggr_resume_tid(struct ath_softc_tgt *sc, ath_atx_tid_t *tid) { struct ath_txq *txq; txq = TID_TO_ACTXQ(tid->tidno); tid->paused = 0; if (asf_tailq_empty(&tid->buf_q)) return; ath_tgt_tx_enqueue(txq, tid); ath_tgt_txq_schedule(sc, txq); } static inline void ath_aggr_pause_tid(struct ath_softc_tgt *sc, ath_atx_tid_t *tid) { tid->paused =1; } static a_uint32_t ath_pkt_duration(struct ath_softc_tgt *sc, a_uint8_t rix, struct ath_tx_buf *bf, a_int32_t width, a_int32_t half_gi) { const HAL_RATE_TABLE *rt = sc->sc_currates; a_uint32_t nbits, nsymbits, duration, nsymbols; a_uint8_t rc; a_int32_t streams; a_int32_t pktlen; pktlen = bf->bf_isaggr ? bf->bf_al : bf->bf_pktlen; rc = rt->info[rix].rateCode; if (!IS_HT_RATE(rc)) return ath_hal_computetxtime(sc->sc_ah, rt, pktlen, rix, bf->bf_shpream); nbits = (pktlen << 3) + OFDM_PLCP_BITS; nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width]; nsymbols = (nbits + nsymbits - 1) / nsymbits; if (!half_gi) duration = SYMBOL_TIME(nsymbols); else duration = SYMBOL_TIME_HALFGI(nsymbols); streams = HT_RC_2_STREAMS(rc); duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); return duration; } static void ath_dma_map(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) { adf_nbuf_t skb = bf->bf_skb; skb = adf_nbuf_queue_first(&bf->bf_skbhead); adf_nbuf_map(sc->sc_dev, bf->bf_dmamap, skb, ADF_OS_DMA_TO_DEVICE); } static void ath_dma_unmap(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) { adf_nbuf_queue_first(&bf->bf_skbhead); adf_nbuf_unmap( sc->sc_dev, bf->bf_dmamap, ADF_OS_DMA_TO_DEVICE); } static void ath_filltxdesc(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) { struct ath_tx_desc *ds0, *ds = bf->bf_desc; struct ath_hal *ah = sc->sc_ah; a_uint8_t i; ds0 = ds; adf_nbuf_dmamap_info(bf->bf_dmamap, &bf->bf_dmamap_info); for (i = 0; i < bf->bf_dmamap_info.nsegs; i++, ds++) { ds->ds_data = bf->bf_dmamap_info.dma_segs[i].paddr; if (i == (bf->bf_dmamap_info.nsegs - 1)) { ds->ds_link = 0; bf->bf_lastds = ds; } else ds->ds_link = ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, i+1); ah->ah_fillTxDesc(ds , bf->bf_dmamap_info.dma_segs[i].len , i == 0 , i == (bf->bf_dmamap_info.nsegs - 1) , ds0); } } static void ath_tx_tgt_setds(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) { struct ath_tx_desc *ds = bf->bf_desc; struct ath_hal *ah = sc->sc_ah; switch (bf->bf_protmode) { case IEEE80211_PROT_RTSCTS: bf->bf_flags |= HAL_TXDESC_RTSENA; break; case IEEE80211_PROT_CTSONLY: bf->bf_flags |= HAL_TXDESC_CTSENA; break; default: break; } ah->ah_set11nTxDesc(ds , bf->bf_pktlen , bf->bf_atype , 60 , bf->bf_keyix , bf->bf_keytype , bf->bf_flags | HAL_TXDESC_INTREQ); ath_filltxdesc(sc, bf); } static struct ath_tx_buf *ath_buf_toggle(struct ath_softc_tgt *sc, struct ath_tx_buf *bf, a_uint8_t retry) { struct ath_tx_buf *tmp = NULL; adf_nbuf_t buf = NULL; adf_os_assert(sc->sc_txbuf_held != NULL); tmp = sc->sc_txbuf_held; if (retry) { ath_dma_unmap(sc, bf); adf_nbuf_queue_init(&tmp->bf_skbhead); buf = adf_nbuf_queue_remove(&bf->bf_skbhead); adf_os_assert(buf); adf_nbuf_queue_add(&tmp->bf_skbhead, buf); adf_os_assert(adf_nbuf_queue_len(&bf->bf_skbhead) == 0); tmp->bf_next = bf->bf_next; tmp->bf_endpt = bf->bf_endpt; tmp->bf_tidno = bf->bf_tidno; tmp->bf_skb = bf->bf_skb; tmp->bf_node = bf->bf_node; tmp->bf_isaggr = bf->bf_isaggr; tmp->bf_flags = bf->bf_flags; tmp->bf_state = bf->bf_state; tmp->bf_retries = bf->bf_retries; tmp->bf_comp = bf->bf_comp; tmp->bf_nframes = bf->bf_nframes; tmp->bf_cookie = bf->bf_cookie; bf->bf_isaggr = 0; bf->bf_next = NULL; bf->bf_skb = NULL; bf->bf_node = NULL; bf->bf_flags = 0; bf->bf_comp = NULL; bf->bf_retries = 0; bf->bf_nframes = 0; ath_dma_map(sc, tmp); ath_tx_tgt_setds(sc, tmp); } sc->sc_txbuf_held = bf; return tmp; } static void ath_tgt_skb_free(struct ath_softc_tgt *sc, adf_nbuf_queue_t *head, HTC_ENDPOINT_ID endpt) { adf_nbuf_t tskb; while (adf_nbuf_queue_len(head) != 0) { tskb = adf_nbuf_queue_remove(head); ath_free_tx_skb(sc->tgt_htc_handle,endpt,tskb); } } static void ath_buf_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) { ath_dma_unmap(sc, bf); ath_tgt_skb_free(sc, &bf->bf_skbhead,bf->bf_endpt); bf->bf_skb = NULL; bf->bf_node = NULL; bf = ath_buf_toggle(sc, bf, 0); if (bf != NULL) { asf_tailq_insert_tail(&sc->sc_txbuf, bf, bf_list); } } static void ath_buf_set_rate(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) { struct ath_hal *ah = sc->sc_ah; const HAL_RATE_TABLE *rt; struct ath_tx_desc *ds = bf->bf_desc; HAL_11N_RATE_SERIES series[4]; a_int32_t i, flags; a_uint8_t rix, cix, rtsctsrate; a_int32_t prot_mode = AH_FALSE; rt = sc->sc_currates; rix = bf->bf_rcs[0].rix; flags = (bf->bf_flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)); cix = rt->info[sc->sc_protrix].controlRate; if (bf->bf_protmode != IEEE80211_PROT_NONE && (rt->info[rix].phy == IEEE80211_T_OFDM || rt->info[rix].phy == IEEE80211_T_HT) && (bf->bf_flags & HAL_TXDESC_NOACK) == 0) { cix = rt->info[sc->sc_protrix].controlRate; prot_mode = AH_TRUE; } else { if (ath_hal_getcapability(ah, HAL_CAP_HT) && (!bf->bf_ismcast)) flags = HAL_TXDESC_RTSENA; for (i = 4; i--;) { if (bf->bf_rcs[i].tries) { cix = rt->info[bf->bf_rcs[i].rix].controlRate; break; } } } adf_os_mem_set(series, 0, sizeof(HAL_11N_RATE_SERIES) * 4); for (i = 0; i < 4; i++) { if (!bf->bf_rcs[i].tries) continue; rix = bf->bf_rcs[i].rix; series[i].Rate = rt->info[rix].rateCode | (bf->bf_shpream ? rt->info[rix].shortPreamble : 0); series[i].Tries = bf->bf_rcs[i].tries; #ifdef MAGPIE_MERLIN series[i].RateFlags = ((bf->bf_rcs[i].flags & ATH_RC_RTSCTS_FLAG) ? HAL_RATESERIES_RTS_CTS : 0 ) | ((bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) ? HAL_RATESERIES_2040 : 0 ) | ((bf->bf_rcs[i].flags & ATH_RC_HT40_SGI_FLAG) ? HAL_RATESERIES_HALFGI : 0 ) | ((bf->bf_rcs[i].flags & ATH_RC_TX_STBC_FLAG) ? HAL_RATESERIES_STBC: 0); #else series[i].RateFlags = ((bf->bf_rcs[i].flags & ATH_RC_RTSCTS_FLAG) ? HAL_RATESERIES_RTS_CTS : 0 ) | ((bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) ? HAL_RATESERIES_2040 : 0 ) | ((bf->bf_rcs[i].flags & ATH_RC_HT40_SGI_FLAG) ? HAL_RATESERIES_HALFGI : 0 ); #endif series[i].PktDuration = ath_pkt_duration(sc, rix, bf, (bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) != 0, (bf->bf_rcs[i].flags & ATH_RC_HT40_SGI_FLAG)); series[i].ChSel = sc->sc_ic.ic_tx_chainmask; if (prot_mode) series[i].RateFlags |= HAL_RATESERIES_RTS_CTS; if (bf->bf_rcs[i].flags & ATH_RC_DS_FLAG) series[i].RateFlags |= HAL_RATESERIES_RTS_CTS; } rtsctsrate = rt->info[cix].rateCode | (bf->bf_shpream ? rt->info[cix].shortPreamble : 0); ah->ah_set11nRateScenario(ds, 1, rtsctsrate, series, 4, flags); } static void ath_tgt_rate_findrate(struct ath_softc_tgt *sc, struct ath_node_target *an, a_int32_t shortPreamble, size_t frameLen, a_int32_t numTries, a_int32_t numRates, a_int32_t stepDnInc, a_uint32_t rcflag, struct ath_rc_series series[], a_int32_t *isProbe) { ath_rate_findrate(sc, an, 1, frameLen, 10, 4, 1, ATH_RC_PROBE_ALLOWED, series, isProbe); } static void owl_tgt_tid_init(struct ath_atx_tid *tid) { int i; tid->seq_start = tid->seq_next = 0; tid->baw_size = WME_MAX_BA; tid->baw_head = tid->baw_tail = 0; tid->paused = 0; tid->flag = 0; tid->sched = AH_FALSE; asf_tailq_init(&tid->buf_q); for (i = 0; i < ATH_TID_MAX_BUFS; i++) { TX_BUF_BITMAP_CLR(tid->tx_buf_bitmap, i); } } static void owl_tgt_tid_cleanup(struct ath_softc_tgt *sc, struct ath_atx_tid *tid) { tid->incomp--; if (tid->incomp) { return; } tid->flag &= ~TID_CLEANUP_INPROGRES; if (tid->flag & TID_REINITIALIZE) { adf_os_print("TID REINIT DONE for tid %p\n", tid); tid->flag &= ~TID_REINITIALIZE; owl_tgt_tid_init(tid); } else { ath_aggr_resume_tid(sc, tid); } } void owl_tgt_node_init(struct ath_node_target * an) { struct ath_atx_tid *tid; int tidno; for (tidno = 0, tid = &an->tid[tidno]; tidno < WME_NUM_TID;tidno++, tid++) { tid->tidno = tidno; tid->an = an; if ( tid->flag & TID_CLEANUP_INPROGRES ) { tid->flag |= TID_REINITIALIZE; adf_os_print("tid[%p]->incomp is not 0: %d\n", tid, tid->incomp); } else { owl_tgt_tid_init(tid); } } } void ath_tx_status_clear(struct ath_softc_tgt *sc) { int i; for (i = 0; i < 2; i++) { sc->tx_status[i].cnt = 0; } } static WMI_TXSTATUS_EVENT *ath_tx_status_get(struct ath_softc_tgt *sc) { WMI_TXSTATUS_EVENT *txs = NULL; int i; for (i = 0; i < 2; i++) { if (sc->tx_status[i].cnt < HTC_MAX_TX_STATUS) { txs = &sc->tx_status[i]; break; } } return txs; } void ath_tx_status_update(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) { struct ath_tx_desc *ds = bf->bf_lastds; WMI_TXSTATUS_EVENT *txs; if (sc->sc_tx_draining) return; txs = ath_tx_status_get(sc); if (txs == NULL) return; txs->txstatus[txs->cnt].ts_flags = 0; txs->txstatus[txs->cnt].cookie = bf->bf_cookie; txs->txstatus[txs->cnt].ts_rate = SM(bf->bf_endpt, ATH9K_HTC_TXSTAT_EPID); if (ds->ds_txstat.ts_status & HAL_TXERR_FILT) txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_FILT; if (!(ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) && !(ds->ds_txstat.ts_status & HAL_TXERR_FIFO) && !(ds->ds_txstat.ts_status & HAL_TXERR_TIMER_EXPIRED) && !(ds->ds_txstat.ts_status & HAL_TXERR_FILT)) txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_ACK; ath_tx_status_update_rate(sc, bf->bf_rcs, ds->ds_txstat.ts_rate, txs); txs->cnt++; } void ath_tx_status_update_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf, struct ath_tx_desc *ds, struct ath_rc_series rcs[], int txok) { WMI_TXSTATUS_EVENT *txs; if (sc->sc_tx_draining) return; txs = ath_tx_status_get(sc); if (txs == NULL) return; txs->txstatus[txs->cnt].cookie = bf->bf_cookie; txs->txstatus[txs->cnt].ts_rate = SM(bf->bf_endpt, ATH9K_HTC_TXSTAT_EPID); if (txok) txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_ACK; if (rcs) ath_tx_status_update_rate(sc, rcs, ds->ds_txstat.ts_rate, txs); txs->cnt++; } void ath_tx_status_send(struct ath_softc_tgt *sc) { int i; if (sc->sc_tx_draining) return; for (i = 0; i < 2; i++) { if (sc->tx_status[i].cnt) { wmi_event(sc->tgt_wmi_handle, WMI_TXSTATUS_EVENTID, &sc->tx_status[i], sizeof(WMI_TXSTATUS_EVENT)); /* FIXME: Handle failures. */ sc->tx_status[i].cnt = 0; } } } static void owltgt_tx_process_cabq(struct ath_softc_tgt *sc, struct ath_txq *txq) { struct ath_hal *ah = sc->sc_ah; ah->ah_setInterrupts(ah, sc->sc_imask & ~HAL_INT_SWBA); owltgt_tx_processq(sc, txq, OWL_TXQ_ACTIVE); ah->ah_setInterrupts(ah, sc->sc_imask); } void owl_tgt_tx_tasklet(TQUEUE_ARG data) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data; a_int32_t i; struct ath_txq *txq; ath_tx_status_clear(sc); for (i = 0; i < (HAL_NUM_TX_QUEUES - 6); i++) { txq = ATH_TXQ(sc, i); if (ATH_TXQ_SETUP(sc, i)) { if (txq == sc->sc_cabq) owltgt_tx_process_cabq(sc, txq); else owltgt_tx_processq(sc, txq, OWL_TXQ_ACTIVE); } } ath_tx_status_send(sc); } void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq, owl_txq_state_t txqstate) { struct ath_tx_buf *bf; struct ath_tx_desc *ds; struct ath_hal *ah = sc->sc_ah; HAL_STATUS status; for (;;) { if (asf_tailq_empty(&txq->axq_q)) { txq->axq_link = NULL; txq->axq_linkbuf = NULL; break; } bf = asf_tailq_first(&txq->axq_q); ds = bf->bf_lastds; status = ah->ah_procTxDesc(ah, ds); if (status == HAL_EINPROGRESS) { if (txqstate == OWL_TXQ_ACTIVE) break; else if (txqstate == OWL_TXQ_STOPPED) { __stats(sc, tx_stopfiltered); ds->ds_txstat.ts_flags = 0; ds->ds_txstat.ts_status = HAL_OK; } else { ds->ds_txstat.ts_flags = HAL_TX_SW_FILTERED; } } ATH_TXQ_REMOVE_HEAD(txq, bf, bf_list); if ((asf_tailq_empty(&txq->axq_q))) { __stats(sc, tx_qnull); txq->axq_link = NULL; txq->axq_linkbuf = NULL; } if (bf->bf_comp) { bf->bf_comp(sc, bf); } else { ath_tx_status_update(sc, bf); ath_buf_comp(sc, bf); } if (txqstate == OWL_TXQ_ACTIVE) { ath_tgt_txq_schedule(sc, txq); } } } static struct ieee80211_frame* ATH_SKB2_WH(adf_nbuf_t skb) { a_uint8_t *anbdata; a_uint32_t anblen; adf_nbuf_peek_header(skb, &anbdata, &anblen); return((struct ieee80211_frame *)anbdata); } void ath_tgt_tid_drain(struct ath_softc_tgt *sc, struct ath_atx_tid *tid) { struct ath_tx_buf *bf; while (!asf_tailq_empty(&tid->buf_q)) { TAILQ_DEQ(&tid->buf_q, bf, bf_list); ath_tx_freebuf(sc, bf); } tid->seq_next = tid->seq_start; tid->baw_tail = tid->baw_head; } static void ath_tgt_tx_comp_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) { struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node); ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno); if (tid->flag & TID_CLEANUP_INPROGRES) { owl_tgt_tid_cleanup(sc, tid); } if (bf->bf_node) { ath_tx_uc_comp(sc, bf); } ath_tx_freebuf(sc, bf); } static struct ieee80211_node_target * ath_tgt_find_node(struct ath_softc_tgt *sc, a_int32_t node_index) { struct ath_node_target *an; struct ieee80211_node_target *ni; if (node_index > TARGET_NODE_MAX) return NULL; an = &sc->sc_sta[node_index]; ni = &an->ni; if (an->an_valid) { if (ni->ni_vap == NULL) { return NULL; } return ni; } return NULL; } static struct ath_tx_buf* ath_tx_buf_alloc(struct ath_softc_tgt *sc) { struct ath_tx_buf *bf = NULL; bf = asf_tailq_first(&sc->sc_txbuf); if (bf != NULL) { adf_os_mem_set(&bf->bf_state, 0, sizeof(struct ath_buf_state)); asf_tailq_remove(&sc->sc_txbuf, bf, bf_list); } else { adf_os_assert(0); } return bf; } struct ath_tx_buf* ath_tgt_tx_prepare(struct ath_softc_tgt *sc, adf_nbuf_t skb, ath_data_hdr_t *dh) { struct ath_tx_buf *bf; struct ieee80211_node_target *ni; struct ath_atx_tid *tid; ni = ath_tgt_find_node(sc, dh->ni_index); if (ni == NULL) return NULL; tid = ATH_AN_2_TID(ATH_NODE_TARGET(ni), dh->tidno); if (tid->flag & TID_REINITIALIZE) { adf_os_print("drop frame due to TID reinit\n"); return NULL; } bf = ath_tx_buf_alloc(sc); if (!bf) { __stats(sc, tx_nobufs); return NULL; } bf->bf_tidno = dh->tidno; bf->bf_txq = TID_TO_ACTXQ(bf->bf_tidno); bf->bf_keytype = dh->keytype; bf->bf_keyix = dh->keyix; bf->bf_protmode = dh->flags & (IEEE80211_PROT_RTSCTS | IEEE80211_PROT_CTSONLY); bf->bf_node = ni; adf_nbuf_queue_add(&bf->bf_skbhead, skb); skb = adf_nbuf_queue_first(&(bf->bf_skbhead)); if (adf_nbuf_queue_len(&(bf->bf_skbhead)) == 0) { __stats(sc, tx_noskbs); return NULL; } adf_os_assert(skb); bf->bf_skb = skb; ath_tgt_txbuf_setup(sc, bf, dh); ath_dma_map(sc, bf); ath_tx_tgt_setds(sc, bf); return bf; } static void ath_tgt_tx_seqno_normal(struct ath_tx_buf *bf) { struct ieee80211_node_target *ni = bf->bf_node; struct ath_node_target *an = ATH_NODE_TARGET(ni); struct ieee80211_frame *wh = ATH_SKB_2_WH(bf->bf_skb); struct ath_atx_tid *tid = ATH_AN_2_TID(an, bf->bf_tidno); u_int8_t fragno = (wh->i_seq[0] & 0xf); INCR(ni->ni_txseqmgmt, IEEE80211_SEQ_MAX); bf->bf_seqno = (tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT); *(u_int16_t *)wh->i_seq = adf_os_cpu_to_le16(bf->bf_seqno); wh->i_seq[0] |= fragno; if (!(wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG)) INCR(tid->seq_next, IEEE80211_SEQ_MAX); } static a_int32_t ath_key_setup(struct ieee80211_node_target *ni, struct ath_tx_buf *bf) { struct ieee80211_frame *wh = ATH_SKB_2_WH(bf->bf_skb); if (!(wh->i_fc[1] & IEEE80211_FC1_WEP)) { bf->bf_keytype = HAL_KEY_TYPE_CLEAR; bf->bf_keyix = HAL_TXKEYIX_INVALID; return 0; } switch (bf->bf_keytype) { case HAL_KEY_TYPE_WEP: bf->bf_pktlen += IEEE80211_WEP_ICVLEN; break; case HAL_KEY_TYPE_AES: bf->bf_pktlen += IEEE80211_WEP_MICLEN; break; case HAL_KEY_TYPE_TKIP: bf->bf_pktlen += IEEE80211_WEP_ICVLEN; break; default: break; } if (bf->bf_keytype == HAL_KEY_TYPE_AES || bf->bf_keytype == HAL_KEY_TYPE_TKIP) ieee80211_tgt_crypto_encap(wh, ni, bf->bf_keytype); return 0; } static void ath_tgt_txq_add_ucast(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) { struct ath_hal *ah = sc->sc_ah; struct ath_txq *txq; volatile a_int32_t txe_val; adf_os_assert(bf); txq = bf->bf_txq; ah->ah_procTxDesc(ah, bf->bf_lastds); ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); if (txq->axq_link == NULL) { ah->ah_setTxDP(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf)); } else { *txq->axq_link = ATH_BUF_GET_DESC_PHY_ADDR(bf); txe_val = ioread32_mac(0x0840); if (!(txe_val & (1<< txq->axq_qnum))) ah->ah_setTxDP(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf)); } txq->axq_link = &bf->bf_lastds->ds_link; ah->ah_startTxDma(ah, txq->axq_qnum); } static a_int32_t ath_tgt_txbuf_setup(struct ath_softc_tgt *sc, struct ath_tx_buf *bf, ath_data_hdr_t *dh) { struct ieee80211_frame *wh = ATH_SKB2_WH(bf->bf_skb); a_int32_t retval; a_uint32_t flags = adf_os_ntohl(dh->flags); ath_tgt_tx_seqno_normal(bf); bf->bf_txq_add = ath_tgt_txq_add_ucast; bf->bf_hdrlen = ieee80211_anyhdrsize(wh); bf->bf_pktlen = ath_get_pktlen(bf, bf->bf_hdrlen); bf->bf_ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); if ((retval = ath_key_setup(bf->bf_node, bf)) < 0) return retval; if (flags & ATH_SHORT_PREAMBLE) bf->bf_shpream = AH_TRUE; else bf->bf_shpream = AH_FALSE; bf->bf_flags = HAL_TXDESC_CLRDMASK; bf->bf_atype = HAL_PKT_TYPE_NORMAL; return 0; } static a_int32_t ath_get_pktlen(struct ath_tx_buf *bf, a_int32_t hdrlen) { adf_nbuf_t skb = bf->bf_skb; a_int32_t pktlen; skb = adf_nbuf_queue_first(&bf->bf_skbhead); pktlen = adf_nbuf_len(skb); pktlen -= (hdrlen & 3); pktlen += IEEE80211_CRC_LEN; return pktlen; } void ath_tgt_tx_send_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) { struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node); struct ath_rc_series rcs[4]; struct ath_rc_series mrcs[4]; a_int32_t shortPreamble = 0; a_int32_t isProbe = 0; adf_os_mem_set(rcs, 0, sizeof(struct ath_rc_series)*4 ); adf_os_mem_set(mrcs, 0, sizeof(struct ath_rc_series)*4 ); if (!bf->bf_ismcast) { ath_tgt_rate_findrate(sc, an, shortPreamble, 0, 0, 0, 0, 0, rcs, &isProbe); ath_hal_memcpy(bf->bf_rcs, rcs, sizeof(rcs)); } else { struct ath_vap_target *avp; avp = &sc->sc_vap[bf->vap_index]; mrcs[1].tries = mrcs[2].tries = mrcs[3].tries = 0; mrcs[1].rix = mrcs[2].rix = mrcs[3].rix = 0; mrcs[0].rix = ath_get_minrateidx(sc, avp); mrcs[0].tries = 1; mrcs[0].flags = 0; ath_hal_memcpy(bf->bf_rcs, mrcs, sizeof(mrcs)); } ath_buf_set_rate(sc, bf); bf->bf_txq_add(sc, bf); } static void ath_tx_freebuf(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) { a_int32_t i ; struct ath_tx_desc *bfd = NULL; struct ath_hal *ah = sc->sc_ah; for (bfd = bf->bf_desc, i = 0; i < bf->bf_dmamap_info.nsegs; bfd++, i++) { ah->ah_clr11nAggr(bfd); ah->ah_set11nBurstDuration(bfd, 0); ah->ah_set11nVirtualMoreFrag(bfd, 0); } ath_dma_unmap(sc, bf); ath_tgt_skb_free(sc, &bf->bf_skbhead,bf->bf_endpt); bf->bf_skb = NULL; bf->bf_comp = NULL; bf->bf_node = NULL; bf->bf_next = NULL; bf = ath_buf_toggle(sc, bf, 0); bf->bf_retries = 0; bf->bf_isretried = 0; if (bf != NULL) asf_tailq_insert_tail(&sc->sc_txbuf, bf, bf_list); } static void ath_tx_uc_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) { ath_tx_status_update(sc, bf); ath_update_stats(sc, bf); ath_rate_tx_complete(sc, ATH_NODE_TARGET(bf->bf_node), bf->bf_lastds, bf->bf_rcs, 1, 0); } static void ath_update_stats(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) { struct ath_tx_desc *ds = bf->bf_desc; struct ieee80211_frame *wh = ATH_SKB2_WH(bf->bf_skb); u_int32_t sr, lr; if (ds->ds_txstat.ts_status == 0) { if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE) sc->sc_tx_stats.ast_tx_altrate++; } else { if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY && !IEEE80211_IS_MULTICAST(wh->i_addr1)) sc->sc_tx_stats.ast_tx_xretries++; if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO) sc->sc_tx_stats.ast_tx_fifoerr++; if (ds->ds_txstat.ts_status & HAL_TXERR_FILT) sc->sc_tx_stats.ast_tx_filtered++; if (ds->ds_txstat.ts_status & HAL_TXERR_TIMER_EXPIRED) sc->sc_tx_stats.ast_tx_timer_exp++; } sr = ds->ds_txstat.ts_shortretry; lr = ds->ds_txstat.ts_longretry; sc->sc_tx_stats.ast_tx_shortretry += sr; sc->sc_tx_stats.ast_tx_longretry += lr; } void ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t hdr_buf, adf_nbuf_t skb, HTC_ENDPOINT_ID endpt) { struct ieee80211_node_target *ni; struct ieee80211vap_target *vap; struct ath_vap_target *avp; struct ath_hal *ah = sc->sc_ah; a_uint8_t rix, txrate, ctsrate, cix = 0xff, *data; a_uint32_t subtype, flags, ctsduration; a_int32_t i, iswep, ismcast, hdrlen, pktlen, try0, len; struct ath_tx_desc *ds=NULL; struct ath_txq *txq=NULL; struct ath_tx_buf *bf; HAL_PKT_TYPE atype; const HAL_RATE_TABLE *rt; HAL_BOOL shortPreamble; struct ieee80211_frame *wh; struct ath_rc_series rcs[4]; HAL_11N_RATE_SERIES series[4]; ath_mgt_hdr_t *mh; a_int8_t keyix; if (!hdr_buf) { adf_nbuf_peek_header(skb, &data, &len); adf_nbuf_pull_head(skb, sizeof(ath_mgt_hdr_t)); } else { adf_nbuf_peek_header(hdr_buf, &data, &len); } adf_os_assert(len >= sizeof(ath_mgt_hdr_t)); mh = (ath_mgt_hdr_t *)data; adf_nbuf_peek_header(skb, &data, &len); wh = (struct ieee80211_frame *)data; adf_os_mem_set(rcs, 0, sizeof(struct ath_rc_series)*4); adf_os_mem_set(series, 0, sizeof(HAL_11N_RATE_SERIES)*4); bf = asf_tailq_first(&sc->sc_txbuf); if (!bf) goto fail; asf_tailq_remove(&sc->sc_txbuf, bf, bf_list); ni = ath_tgt_find_node(sc, mh->ni_index); if (!ni) goto fail; bf->bf_endpt = endpt; bf->bf_cookie = mh->cookie; bf->bf_protmode = mh->flags & (IEEE80211_PROT_RTSCTS | IEEE80211_PROT_CTSONLY); txq = &sc->sc_txq[1]; iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); hdrlen = ieee80211_anyhdrsize(wh); pktlen = len; keyix = HAL_TXKEYIX_INVALID; pktlen -= (hdrlen & 3); pktlen += IEEE80211_CRC_LEN; if (iswep) keyix = mh->keyix; adf_nbuf_map(sc->sc_dev, bf->bf_dmamap, skb, ADF_OS_DMA_TO_DEVICE); bf->bf_skb = skb; adf_nbuf_queue_add(&bf->bf_skbhead, skb); ds = bf->bf_desc; rt = sc->sc_currates; adf_os_assert(rt != NULL); if (mh->flags == ATH_SHORT_PREAMBLE) shortPreamble = AH_TRUE; else shortPreamble = AH_FALSE; flags = HAL_TXDESC_CLRDMASK; switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { case IEEE80211_FC0_TYPE_MGT: subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) atype = HAL_PKT_TYPE_PROBE_RESP; else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) atype = HAL_PKT_TYPE_ATIM; else atype = HAL_PKT_TYPE_NORMAL; break; default: atype = HAL_PKT_TYPE_NORMAL; break; } avp = &sc->sc_vap[mh->vap_index]; rcs[0].rix = ath_get_minrateidx(sc, avp); rcs[0].tries = ATH_TXMAXTRY; rcs[0].flags = 0; adf_os_mem_copy(bf->bf_rcs, rcs, sizeof(rcs)); rix = rcs[0].rix; try0 = rcs[0].tries; txrate = rt->info[rix].rateCode; if (shortPreamble){ txrate |= rt->info[rix].shortPreamble; } vap = ni->ni_vap; bf->bf_node = ni; if (ismcast) { flags |= HAL_TXDESC_NOACK; try0 = 1; } else if (pktlen > vap->iv_rtsthreshold) { flags |= HAL_TXDESC_RTSENA; cix = rt->info[rix].controlRate; } if ((bf->bf_protmode != IEEE80211_PROT_NONE) && rt->info[rix].phy == IEEE80211_T_OFDM && (flags & HAL_TXDESC_NOACK) == 0) { cix = rt->info[sc->sc_protrix].controlRate; sc->sc_tx_stats.ast_tx_protect++; } *(a_uint16_t *)&wh->i_seq[0] = adf_os_cpu_to_le16(ni->ni_txseqmgmt << IEEE80211_SEQ_SEQ_SHIFT); INCR(ni->ni_txseqmgmt, IEEE80211_SEQ_MAX); ctsduration = 0; if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { adf_os_assert(cix != 0xff); ctsrate = rt->info[cix].rateCode; if (shortPreamble) { ctsrate |= rt->info[cix].shortPreamble; if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ ctsduration += rt->info[cix].spAckDuration; if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ ctsduration += rt->info[cix].spAckDuration; } else { if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ ctsduration += rt->info[cix].lpAckDuration; if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ ctsduration += rt->info[cix].lpAckDuration; } ctsduration += ath_hal_computetxtime(ah, rt, pktlen, rix, shortPreamble); try0 = 1; } else ctsrate = 0; flags |= HAL_TXDESC_INTREQ; ah->ah_setupTxDesc(ds , pktlen , hdrlen , atype , 60 , txrate, try0 , keyix , flags , ctsrate , ctsduration); bf->bf_flags = flags; /* * Set key type in tx desc while sending the encrypted challenge to AP * in Auth frame 3 of Shared Authentication, owl needs this. */ if (iswep && (keyix != HAL_TXKEYIX_INVALID) && (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == IEEE80211_FC0_SUBTYPE_AUTH) ah->ah_fillKeyTxDesc(ds, mh->keytype); ath_filltxdesc(sc, bf); for (i=0; i<4; i++) { series[i].Tries = 2; series[i].Rate = txrate; series[i].ChSel = sc->sc_ic.ic_tx_chainmask; series[i].RateFlags = 0; } ah->ah_set11nRateScenario(ds, 0, ctsrate, series, 4, 0); ath_tgt_txqaddbuf(sc, txq, bf, bf->bf_lastds); return; fail: HTC_ReturnBuffers(sc->tgt_htc_handle, endpt, skb); return; } static void ath_tgt_txqaddbuf(struct ath_softc_tgt *sc, struct ath_txq *txq, struct ath_tx_buf *bf, struct ath_tx_desc *lastds) { struct ath_hal *ah = sc->sc_ah; ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); if (txq->axq_link == NULL) { ah->ah_setTxDP(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf)); } else { *txq->axq_link = ATH_BUF_GET_DESC_PHY_ADDR(bf); } txq->axq_link = &lastds->ds_link; ah->ah_startTxDma(ah, txq->axq_qnum); } void ath_tgt_handle_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) { ath_atx_tid_t *tid; struct ath_node_target *an; an = (struct ath_node_target *)bf->bf_node; adf_os_assert(an); tid = &an->tid[bf->bf_tidno]; adf_os_assert(tid); bf->bf_comp = ath_tgt_tx_comp_normal; INCR(tid->seq_start, IEEE80211_SEQ_MAX); ath_tgt_tx_send_normal(sc, bf); } static void ath_tgt_tx_enqueue(struct ath_txq *txq, struct ath_atx_tid *tid) { if (tid->paused) return; if (tid->sched) return; tid->sched = AH_TRUE; asf_tailq_insert_tail(&txq->axq_tidq, tid, tid_qelem); } static void ath_tgt_txq_schedule(struct ath_softc_tgt *sc, struct ath_txq *txq) { struct ath_atx_tid *tid; u_int8_t bdone; bdone = AH_FALSE; do { TAILQ_DEQ(&txq->axq_tidq, tid, tid_qelem); if (tid == NULL) return; tid->sched = AH_FALSE; if (tid->paused) continue; if (!(tid->flag & TID_AGGR_ENABLED)) ath_tgt_tx_sched_normal(sc,tid); else ath_tgt_tx_sched_aggr(sc,tid); bdone = AH_TRUE; if (!asf_tailq_empty(&tid->buf_q)) { ath_tgt_tx_enqueue(txq, tid); } } while (!asf_tailq_empty(&txq->axq_tidq) && !bdone); } void ath_tgt_handle_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) { ath_atx_tid_t *tid; struct ath_node_target *an; struct ath_txq *txq = bf->bf_txq; a_bool_t queue_frame, within_baw; an = (struct ath_node_target *)bf->bf_node; adf_os_assert(an); tid = &an->tid[bf->bf_tidno]; adf_os_assert(tid); bf->bf_comp = ath_tgt_tx_comp_aggr; within_baw = BAW_WITHIN(tid->seq_start, tid->baw_size, SEQNO_FROM_BF_SEQNO(bf->bf_seqno)); queue_frame = ( (txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) || (!asf_tailq_empty(&tid->buf_q)) || (tid->paused) || (!within_baw) ); if (queue_frame) { asf_tailq_insert_tail(&tid->buf_q, bf, bf_list); ath_tgt_tx_enqueue(txq, tid); } else { ath_tx_addto_baw(tid, bf); __stats(sc, txaggr_nframes); ath_tgt_tx_send_normal(sc, bf); } } static void ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, ath_atx_tid_t *tid) { struct ath_tx_buf *bf; struct ath_txq *txq =TID_TO_ACTXQ(tid->tidno);; do { if (asf_tailq_empty(&tid->buf_q)) break; bf = asf_tailq_first(&tid->buf_q); asf_tailq_remove(&tid->buf_q, bf, bf_list); ath_tgt_tx_send_normal(sc, bf); } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH); } static void ath_tgt_tx_sched_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid) { struct ath_tx_buf *bf, *bf_last; ATH_AGGR_STATUS status; ath_tx_bufhead bf_q; struct ath_txq *txq = TID_TO_ACTXQ(tid->tidno); struct ath_tx_desc *ds = NULL; struct ath_hal *ah = sc->sc_ah; int i; if (asf_tailq_empty(&tid->buf_q)) return; do { if (asf_tailq_empty(&tid->buf_q)) break; asf_tailq_init(&bf_q); status = ath_tgt_tx_form_aggr(sc, tid, &bf_q); if (asf_tailq_empty(&bf_q)) break; bf = asf_tailq_first(&bf_q); bf_last = asf_tailq_last(&bf_q, ath_tx_bufhead_s); if (bf->bf_nframes == 1) { if(bf->bf_retries == 0) __stats(sc, txaggr_single); bf->bf_isaggr = 0; bf->bf_lastds = &(bf->bf_descarr[bf->bf_dmamap_info.nsegs -1]); bf->bf_lastds->ds_link = 0; bf->bf_next = NULL; for(ds = bf->bf_desc; ds <= bf->bf_lastds; ds++) ah->ah_clr11nAggr(ds); ath_buf_set_rate(sc, bf); bf->bf_txq_add(sc, bf); continue; } bf_last->bf_next = NULL; bf_last->bf_lastds->ds_link = 0; bf_last->bf_ndelim = 0; bf->bf_isaggr = 1; ath_buf_set_rate(sc, bf); ah->ah_set11nAggrFirst(bf->bf_desc, bf->bf_al, bf->bf_ndelim); bf->bf_lastds = bf_last->bf_lastds; for (i = 0; i < bf_last->bf_dmamap_info.nsegs; i++) ah->ah_set11nAggrLast(&bf_last->bf_descarr[i]); if (status == ATH_AGGR_8K_LIMITED) { adf_os_assert(0); break; } bf->bf_txq_add(sc, bf); } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH && status != ATH_TGT_AGGR_BAW_CLOSED); } static u_int32_t ath_lookup_rate(struct ath_softc_tgt *sc, struct ath_node_target *an, struct ath_tx_buf *bf) { int i, prate; u_int32_t max4msframelen, frame_length; u_int16_t aggr_limit, legacy=0; const HAL_RATE_TABLE *rt = sc->sc_currates; struct ieee80211_node_target *ieee_node = (struct ieee80211_node_target *)an; if (bf->bf_ismcast) { bf->bf_rcs[1].tries = bf->bf_rcs[2].tries = bf->bf_rcs[3].tries = 0; bf->bf_rcs[0].rix = 0xb; bf->bf_rcs[0].tries = ATH_TXMAXTRY - 1; bf->bf_rcs[0].flags = 0; } else { ath_tgt_rate_findrate(sc, an, AH_TRUE, 0, ATH_TXMAXTRY-1, 4, 1, ATH_RC_PROBE_ALLOWED, bf->bf_rcs, &prate); } max4msframelen = IEEE80211_AMPDU_LIMIT_MAX; for (i = 0; i < 4; i++) { if (bf->bf_rcs[i].tries) { frame_length = bf->bf_rcs[i].max4msframelen; if (rt->info[bf->bf_rcs[i].rix].phy != IEEE80211_T_HT) { legacy = 1; break; } max4msframelen = ATH_MIN(max4msframelen, frame_length); } } if (prate || legacy) return 0; if (sc->sc_ic.ic_enable_coex) aggr_limit = ATH_MIN((max4msframelen*3)/8, sc->sc_ic.ic_ampdu_limit); else aggr_limit = ATH_MIN(max4msframelen, sc->sc_ic.ic_ampdu_limit); if (ieee_node->ni_maxampdu) aggr_limit = ATH_MIN(aggr_limit, ieee_node->ni_maxampdu); return aggr_limit; } int ath_tgt_tx_form_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid, ath_tx_bufhead *bf_q) { struct ath_tx_buf *bf_first ,*bf_prev = NULL; int nframes = 0, rl = 0;; struct ath_tx_desc *ds = NULL; struct ath_tx_buf *bf; struct ath_hal *ah = sc->sc_ah; u_int16_t aggr_limit = (64*1024 -1), al = 0, bpad = 0, al_delta; u_int16_t h_baw = tid->baw_size/2, prev_al = 0, prev_frames = 0; bf_first = asf_tailq_first(&tid->buf_q); do { bf = asf_tailq_first(&tid->buf_q); adf_os_assert(bf); if (!BAW_WITHIN(tid->seq_start, tid->baw_size, SEQNO_FROM_BF_SEQNO(bf->bf_seqno))) { bf_first->bf_al= al; bf_first->bf_nframes = nframes; return ATH_TGT_AGGR_BAW_CLOSED; } if (!rl) { aggr_limit = ath_lookup_rate(sc, tid->an, bf); rl = 1; } al_delta = ATH_AGGR_DELIM_SZ + bf->bf_pktlen; if (nframes && (aggr_limit < (al + bpad + al_delta + prev_al))) { bf_first->bf_al= al; bf_first->bf_nframes = nframes; return ATH_TGT_AGGR_LIMITED; } #ifdef PROJECT_K2 if ((nframes + prev_frames) >= ATH_MIN((h_baw), 17)) { #else if ((nframes + prev_frames) >= ATH_MIN((h_baw), 22)) { #endif bf_first->bf_al= al; bf_first->bf_nframes = nframes; return ATH_TGT_AGGR_LIMITED; } ath_tx_addto_baw(tid, bf); asf_tailq_remove(&tid->buf_q, bf, bf_list); asf_tailq_insert_tail(bf_q, bf, bf_list); nframes ++; adf_os_assert(bf); adf_os_assert(bf->bf_comp == ath_tgt_tx_comp_aggr); al += bpad + al_delta; bf->bf_ndelim = ATH_AGGR_GET_NDELIM(bf->bf_pktlen); switch (bf->bf_keytype) { case HAL_KEY_TYPE_AES: bf->bf_ndelim += ATH_AGGR_ENCRYPTDELIM; break; case HAL_KEY_TYPE_WEP: case HAL_KEY_TYPE_TKIP: bf->bf_ndelim += 64; break; case HAL_KEY_TYPE_WAPI: bf->bf_ndelim += 12; break; default: break; } bpad = PADBYTES(al_delta) + (bf->bf_ndelim << 2); if (bf_prev) { bf_prev->bf_next = bf; bf_prev->bf_lastds->ds_link = ATH_BUF_GET_DESC_PHY_ADDR(bf); } bf_prev = bf; for(ds = bf->bf_desc; ds <= bf->bf_lastds; ds++) ah->ah_set11nAggrMiddle(ds, bf->bf_ndelim); } while (!asf_tailq_empty(&tid->buf_q)); bf_first->bf_al= al; bf_first->bf_nframes = nframes; return ATH_TGT_AGGR_DONE; } void ath_tx_addto_baw(ath_atx_tid_t *tid, struct ath_tx_buf *bf) { int index, cindex; if (bf->bf_isretried) { return; } index = ATH_BA_INDEX(tid->seq_start, SEQNO_FROM_BF_SEQNO(bf->bf_seqno)); cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); TX_BUF_BITMAP_SET(tid->tx_buf_bitmap, cindex); if (index >= ((tid->baw_tail - tid->baw_head) & (ATH_TID_MAX_BUFS - 1))) { tid->baw_tail = cindex; INCR(tid->baw_tail, ATH_TID_MAX_BUFS); } } void ath_tgt_tx_comp_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) { struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node); ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno); struct ath_tx_desc lastds; struct ath_tx_desc *ds = &lastds; struct ath_rc_series rcs[4]; u_int16_t seq_st; u_int32_t *ba; int ba_index; int nbad = 0; int nframes = bf->bf_nframes; struct ath_tx_buf *bf_next; ath_tx_bufhead bf_q; int tx_ok = 1; struct ath_tx_buf *bar = NULL; struct ath_txq *txq; txq = bf->bf_txq; if (tid->flag & TID_CLEANUP_INPROGRES) { ath_tx_comp_cleanup(sc, bf); return; } adf_os_mem_copy(ds, bf->bf_lastds, sizeof (struct ath_tx_desc)); adf_os_mem_copy(rcs, bf->bf_rcs, sizeof(rcs)); if (ds->ds_txstat.ts_flags == HAL_TX_SW_FILTERED) { adf_os_assert(0); return; } if (!bf->bf_isaggr) { ath_tx_comp_unaggr(sc, bf); return; } __stats(sc, tx_compaggr); asf_tailq_init(&bf_q); seq_st = ATH_DS_BA_SEQ(ds); ba = ATH_DS_BA_BITMAP(ds); tx_ok = (ATH_DS_TX_STATUS(ds) == HAL_OK); if (ATH_DS_TX_STATUS(ds) & HAL_TXERR_XRETRY) { ath_tx_comp_aggr_error(sc, bf, tid); return; } if (tx_ok && !ATH_DS_TX_BA(ds)) { __stats(sc, txaggr_babug); adf_os_print("BA Bug?\n"); ath_tx_comp_aggr_error(sc, bf, tid); return; } while (bf) { ba_index = ATH_BA_INDEX(seq_st, SEQNO_FROM_BF_SEQNO(bf->bf_seqno)); bf_next = bf->bf_next; if (tx_ok && ATH_BA_ISSET(ba, ba_index)) { __stats(sc, txaggr_compgood); ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno)); ath_tx_status_update_aggr(sc, bf, ds, rcs, 1); ath_tx_freebuf(sc, bf); } else { ath_tx_retry_subframe(sc, bf, &bf_q, &bar); nbad ++; } bf = bf_next; } ath_update_aggr_stats(sc, ds, nframes, nbad); ath_rate_tx_complete(sc, an, ds, rcs, nframes, nbad); if (bar) { ath_bar_tx(sc, tid, bar); } if (!asf_tailq_empty(&bf_q)) { __stats(sc, txaggr_prepends); TAILQ_INSERTQ_HEAD(&tid->buf_q, &bf_q, bf_list); ath_tgt_tx_enqueue(txq, tid); } } static void ath_tx_comp_aggr_error(struct ath_softc_tgt *sc, struct ath_tx_buf *bf, ath_atx_tid_t *tid) { struct ath_tx_desc lastds; struct ath_tx_desc *ds = &lastds; struct ath_rc_series rcs[4]; struct ath_tx_buf *bar = NULL; struct ath_tx_buf *bf_next; int nframes = bf->bf_nframes; ath_tx_bufhead bf_q; struct ath_txq *txq; asf_tailq_init(&bf_q); txq = bf->bf_txq; adf_os_mem_copy(ds, bf->bf_lastds, sizeof (struct ath_tx_desc)); adf_os_mem_copy(rcs, bf->bf_rcs, sizeof(rcs)); while (bf) { bf_next = bf->bf_next; ath_tx_retry_subframe(sc, bf, &bf_q, &bar); bf = bf_next; } ath_update_aggr_stats(sc, ds, nframes, nframes); ath_rate_tx_complete(sc, tid->an, ds, rcs, nframes, nframes); if (bar) { ath_bar_tx(sc, tid, bar); } if (!asf_tailq_empty(&bf_q)) { __stats(sc, txaggr_prepends); TAILQ_INSERTQ_HEAD(&tid->buf_q, &bf_q, bf_list); ath_tgt_tx_enqueue(txq, tid); } } static void ath_tx_comp_cleanup(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) { struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node); ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno); struct ath_tx_desc lastds; struct ath_tx_desc *ds = &lastds; struct ath_rc_series rcs[4]; int nbad = 0; int nframes = bf->bf_nframes; struct ath_tx_buf *bf_next; adf_os_mem_copy(ds, bf->bf_lastds, sizeof (struct ath_tx_desc)); adf_os_mem_copy(rcs, bf->bf_rcs, sizeof(rcs)); if (!bf->bf_isaggr) { ath_update_stats(sc, bf); __stats(sc, tx_compunaggr); ath_tx_status_update(sc, bf); ath_tx_freebuf(sc, bf); if (tid->flag & TID_CLEANUP_INPROGRES) { owl_tgt_tid_cleanup(sc, tid); } return; } while (bf) { bf_next = bf->bf_next; ath_tx_status_update_aggr(sc, bf, ds, rcs, 0); ath_tx_freebuf(sc, bf); tid->incomp--; if (!tid->incomp) { tid->flag &= ~TID_CLEANUP_INPROGRES; ath_aggr_resume_tid(sc, tid); break; } bf = bf_next; } ath_update_aggr_stats(sc, ds, nframes, nbad); ath_rate_tx_complete(sc, an, ds, rcs, nframes, nbad); } static void ath_tx_retry_subframe(struct ath_softc_tgt *sc, struct ath_tx_buf *bf, ath_tx_bufhead *bf_q, struct ath_tx_buf **bar) { struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node); ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno); struct ath_tx_desc *ds = NULL; struct ath_hal *ah = sc->sc_ah; int i = 0; __stats(sc, txaggr_compretries); for(ds = bf->bf_desc, i = 0; i < bf->bf_dmamap_info.nsegs; ds++, i++) { ah->ah_clr11nAggr(ds); ah->ah_set11nBurstDuration(ds, 0); ah->ah_set11nVirtualMoreFrag(ds, 0); } if (bf->bf_retries >= OWLMAX_RETRIES) { __stats(sc, txaggr_xretries); ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno)); ath_tx_status_update_aggr(sc, bf, bf->bf_lastds, NULL, 0); if (!*bar) *bar = bf; else ath_tx_freebuf(sc, bf); return; } if (!bf->bf_next) { __stats(sc, txaggr_errlast); bf = ath_buf_toggle(sc, bf, 1); } else bf->bf_lastds = &(bf->bf_descarr[bf->bf_dmamap_info.nsegs - 1]); ath_tx_set_retry(sc, bf); asf_tailq_insert_tail(bf_q, bf, bf_list); } static void ath_update_aggr_stats(struct ath_softc_tgt *sc, struct ath_tx_desc *ds, int nframes, int nbad) { u_int8_t status = ATH_DS_TX_STATUS(ds); u_int8_t txflags = ATH_DS_TX_FLAGS(ds); __statsn(sc, txaggr_longretries, ds->ds_txstat.ts_longretry); __statsn(sc, txaggr_shortretries, ds->ds_txstat.ts_shortretry); if (txflags & HAL_TX_DESC_CFG_ERR) __stats(sc, txaggr_desc_cfgerr); if (txflags & HAL_TX_DATA_UNDERRUN) __stats(sc, txaggr_data_urun); if (txflags & HAL_TX_DELIM_UNDERRUN) __stats(sc, txaggr_delim_urun); if (!status) { return; } if (status & HAL_TXERR_XRETRY) __stats(sc, txaggr_compxretry); if (status & HAL_TXERR_FILT) __stats(sc, txaggr_filtered); if (status & HAL_TXERR_FIFO) __stats(sc, txaggr_fifo); if (status & HAL_TXERR_XTXOP) __stats(sc, txaggr_xtxop); if (status & HAL_TXERR_TIMER_EXPIRED) __stats(sc, txaggr_timer_exp); } static void ath_tx_comp_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) { struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node); ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno); struct ath_tx_desc *ds = bf->bf_lastds; ath_update_stats(sc, bf); ath_rate_tx_complete(sc, an, ds, bf->bf_rcs, 1, 0); if (ATH_DS_TX_STATUS(ds) & HAL_TXERR_XRETRY) { ath_tx_retry_unaggr(sc, bf); return; } __stats(sc, tx_compunaggr); ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno)); ath_tx_status_update(sc, bf); ath_tx_freebuf(sc, bf); } static inline void ath_tx_retry_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) { struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node); ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno); struct ath_txq *txq; txq = bf->bf_txq; if (bf->bf_retries >= OWLMAX_RETRIES) { __stats(sc, txunaggr_xretry); ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno)); ath_tx_status_update(sc, bf); ath_bar_tx(sc, tid, bf); return; } __stats(sc, txunaggr_compretries); if (!bf->bf_lastds->ds_link) { __stats(sc, txunaggr_errlast); bf = ath_buf_toggle(sc, bf, 1); } ath_tx_set_retry(sc, bf); asf_tailq_insert_head(&tid->buf_q, bf, bf_list); ath_tgt_tx_enqueue(txq, tid); } static void ath_tx_update_baw(ath_atx_tid_t *tid, int seqno) { int index; int cindex; index = ATH_BA_INDEX(tid->seq_start, seqno); cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); TX_BUF_BITMAP_CLR(tid->tx_buf_bitmap, cindex); while (tid->baw_head != tid->baw_tail && (!TX_BUF_BITMAP_IS_SET(tid->tx_buf_bitmap, tid->baw_head))) { INCR(tid->seq_start, IEEE80211_SEQ_MAX); INCR(tid->baw_head, ATH_TID_MAX_BUFS); } } static void ath_tx_set_retry(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) { struct ieee80211_frame *wh; __stats(sc, txaggr_retries); bf->bf_isretried = 1; bf->bf_retries ++; wh = ATH_SKB_2_WH(bf->bf_skb); wh->i_fc[1] |= IEEE80211_FC1_RETRY; } void ath_tgt_tx_cleanup(struct ath_softc_tgt *sc, struct ath_node_target *an, ath_atx_tid_t *tid, a_uint8_t discard_all) { struct ath_tx_buf *bf; struct ath_tx_buf *bf_next; bf = asf_tailq_first(&tid->buf_q); while (bf) { if (discard_all || bf->bf_isretried) { bf_next = asf_tailq_next(bf, bf_list); TAILQ_DEQ(&tid->buf_q, bf, bf_list); if (bf->bf_isretried) ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno)); ath_tx_freebuf(sc, bf); bf = bf_next; continue; } bf->bf_comp = ath_tgt_tx_comp_normal; bf = asf_tailq_next(bf, bf_list); } ath_aggr_pause_tid(sc, tid); while (tid->baw_head != tid->baw_tail) { if (TX_BUF_BITMAP_IS_SET(tid->tx_buf_bitmap, tid->baw_head)) { tid->incomp++; tid->flag |= TID_CLEANUP_INPROGRES; TX_BUF_BITMAP_CLR(tid->tx_buf_bitmap, tid->baw_head); } INCR(tid->baw_head, ATH_TID_MAX_BUFS); INCR(tid->seq_start, IEEE80211_SEQ_MAX); } if (!(tid->flag & TID_CLEANUP_INPROGRES)) { ath_aggr_resume_tid(sc, tid); } } /******************/ /* BAR Management */ /******************/ static void ath_tgt_delba_send(struct ath_softc_tgt *sc, struct ieee80211_node_target *ni, a_uint8_t tidno, a_uint8_t initiator, a_uint16_t reasoncode) { struct ath_node_target *an = ATH_NODE_TARGET(ni); ath_atx_tid_t *tid = ATH_AN_2_TID(an, tidno); struct wmi_data_delba wmi_delba; tid->flag &= ~TID_AGGR_ENABLED; ath_tgt_tx_cleanup(sc, an, tid, 1); wmi_delba.ni_nodeindex = ni->ni_nodeindex; wmi_delba.tidno = tid->tidno; wmi_delba.initiator = 1; wmi_delba.reasoncode = IEEE80211_REASON_UNSPECIFIED; __stats(sc, txbar_xretry); wmi_event(sc->tgt_wmi_handle, WMI_DELBA_EVENTID, &wmi_delba, sizeof(wmi_delba)); } static void ath_bar_retry(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) { struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node); ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno); if (bf->bf_retries >= OWLMAX_BAR_RETRIES) { ath_tgt_delba_send(sc, bf->bf_node, tid->tidno, 1, IEEE80211_REASON_UNSPECIFIED); ath_tgt_tid_drain(sc, tid); bf->bf_comp = NULL; ath_buf_comp(sc, bf); return; } __stats(sc, txbar_compretries); if (!bf->bf_lastds->ds_link) { __stats(sc, txbar_errlast); bf = ath_buf_toggle(sc, bf, 1); } bf->bf_lastds->ds_link = 0; ath_tx_set_retry(sc, bf); ath_tgt_txq_add_ucast(sc, bf); } static void ath_bar_tx_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) { struct ath_tx_desc *ds = bf->bf_lastds; struct ath_node_target *an; ath_atx_tid_t *tid; an = (struct ath_node_target *)bf->bf_node; tid = &an->tid[bf->bf_tidno]; if (ATH_DS_TX_STATUS(ds) & HAL_TXERR_XRETRY) { ath_bar_retry(sc, bf); return; } ath_aggr_resume_tid(sc, tid); bf->bf_comp = NULL; ath_buf_comp(sc, bf); } static void ath_bar_tx(struct ath_softc_tgt *sc, ath_atx_tid_t *tid, struct ath_tx_buf *bf) { adf_nbuf_t skb; struct ieee80211_frame_bar *bar; u_int8_t min_rate; struct ath_tx_desc *ds, *ds0; struct ath_hal *ah = sc->sc_ah; HAL_11N_RATE_SERIES series[4]; int i = 0; a_uint8_t *anbdata; a_uint32_t anblen; __stats(sc, tx_bars); adf_os_mem_set(&series, 0, sizeof(series)); ath_aggr_pause_tid(sc, tid); skb = adf_nbuf_queue_remove(&bf->bf_skbhead); adf_nbuf_peek_header(skb, &anbdata, &anblen); adf_nbuf_trim_tail(skb, anblen); bar = (struct ieee80211_frame_bar *) anbdata; min_rate = 0x0b; ath_dma_unmap(sc, bf); adf_nbuf_queue_add(&bf->bf_skbhead, skb); bar->i_fc[1] = IEEE80211_FC1_DIR_NODS; bar->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR; bar->i_ctl = tid->tidno << IEEE80211_BAR_CTL_TID_S | IEEE80211_BAR_CTL_COMBA; bar->i_seq = adf_os_cpu_to_le16(tid->seq_start << IEEE80211_SEQ_SEQ_SHIFT); bf->bf_seqno = tid->seq_start << IEEE80211_SEQ_SEQ_SHIFT; adf_nbuf_put_tail(skb, sizeof(struct ieee80211_frame_bar)); bf->bf_comp = ath_bar_tx_comp; bf->bf_tidno = tid->tidno; bf->bf_node = &tid->an->ni; ath_dma_map(sc, bf); adf_nbuf_dmamap_info(bf->bf_dmamap, &bf->bf_dmamap_info); ds = bf->bf_desc; ah->ah_setupTxDesc(ds , adf_nbuf_len(skb) + IEEE80211_CRC_LEN , 0 , HAL_PKT_TYPE_NORMAL , ATH_MIN(60, 60) , min_rate , ATH_TXMAXTRY , bf->bf_keyix , HAL_TXDESC_INTREQ | HAL_TXDESC_CLRDMASK , 0, 0); bf->bf_isaggr = 0; bf->bf_next = NULL; for (ds0 = ds, i=0; i < bf->bf_dmamap_info.nsegs; ds0++, i++) { ah->ah_clr11nAggr(ds0); } ath_filltxdesc(sc, bf); for (i = 0 ; i < 4; i++) { series[i].Tries = ATH_TXMAXTRY; series[i].Rate = min_rate; series[i].ChSel = sc->sc_ic.ic_tx_chainmask; } ah->ah_set11nRateScenario(bf->bf_desc, 0, 0, series, 4, 4); ath_tgt_txq_add_ucast(sc, bf); } open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/include/000077500000000000000000000000001321570333100261515ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/include/athdefs.h000077500000000000000000000110651321570333100277460ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __ATHDEFS_H__ #define __ATHDEFS_H__ /* * This file contains definitions that may be used across both * Host and Target software. Nothing here is module-dependent * or platform-dependent. */ /* * Generic error codes that can be used by hw, sta, ap, sim, dk * and any other environments. Since these are enums, feel free to * add any more codes that you need. */ typedef enum { A_ERROR = -1, /* Generic error return */ A_OK = 0, /* success */ /* Following values start at 1 */ A_DEVICE_NOT_FOUND, /* not able to find PCI device */ A_NO_MEMORY, /* not able to allocate memory, not available */ A_MEMORY_NOT_AVAIL, /* memory region is not free for mapping */ A_NO_FREE_DESC, /* no free descriptors available */ A_BAD_ADDRESS, /* address does not match descriptor */ A_WIN_DRIVER_ERROR, /* used in NT_HW version, if problem at init */ A_REGS_NOT_MAPPED, /* registers not correctly mapped */ A_EPERM, /* Not superuser */ A_EACCES, /* Access denied */ A_ENOENT, /* No such entry, search failed, etc. */ A_EEXIST, /* The object already exists (can't create) */ A_EFAULT, /* Bad address fault */ A_EBUSY, /* Object is busy */ A_EINVAL, /* Invalid parameter */ A_EMSGSIZE, /* Inappropriate message buffer length */ A_ECANCELED, /* Operation canceled */ A_ENOTSUP, /* Operation not supported */ A_ECOMM, /* Communication error on send */ A_EPROTO, /* Protocol error */ A_ENODEV, /* No such device */ A_EDEVNOTUP, /* device is not UP */ A_NO_RESOURCE, /* No resources for requested operation */ A_HARDWARE, /* Hardware failure */ A_PENDING, /* Asynchronous routine; will send up results la ter (typically in callback) */ A_EBADCHANNEL, /* The channel cannot be used */ A_DECRYPT_ERROR, /* Decryption error */ A_PHY_ERROR, /* RX PHY error */ A_CONSUMED /* Object was consumed */ } A_STATUS; #define A_SUCCESS(x) (x == A_OK) #define A_FAILED(x) (!A_SUCCESS(x)) #ifndef TRUE #define TRUE 1 #endif #ifndef FALSE #define FALSE 0 #endif #ifndef NULL #define NULL ((void *)0) #endif /* * The following definition is WLAN specific definition */ typedef enum { MODE_11A = 0, /* 11a Mode */ MODE_11G = 1, /* 11g + 11b Mode */ MODE_11B = 2, /* 11b Mode */ MODE_11GONLY = 3, /* 11g only Mode */ MODE_UNKNOWN = 4, MODE_MAX = 4 } WLAN_PHY_MODE; typedef enum { WLAN_11A_CAPABILITY = 1, WLAN_11G_CAPABILITY = 2, WLAN_11AG_CAPABILITY = 3, } WLAN_CAPABILITY; #endif /* __ATHDEFS_H__ */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/include/htc.h000077500000000000000000000215771321570333100271170ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __HTC_H__ #define __HTC_H__ #ifndef ATH_TARGET #endif #define A_OFFSETOF(type,field) ((int)(&(((type *)NULL)->field))) #define ASSEMBLE_UNALIGNED_UINT16(p,highbyte,lowbyte) \ (((a_uint16_t)(((a_uint8_t *)(p))[(highbyte)])) << 8 | (a_uint16_t)(((a_uint8_t *)(p))[(lowbyte)])) /* alignment independent macros (little-endian) to fetch UINT16s or UINT8s from a * structure using only the type and field name. * Use these macros if there is the potential for unaligned buffer accesses. */ #define A_GET_UINT16_FIELD(p,type,field) \ ASSEMBLE_UNALIGNED_UINT16(p, \ A_OFFSETOF(type,field) + 1, \ A_OFFSETOF(type,field)) #define A_SET_UINT16_FIELD(p,type,field,value) \ { \ ((a_uint8_t *)(p))[A_OFFSETOF(type,field)] = (a_uint8_t)((value) >> 8); \ ((a_uint8_t *)(p))[A_OFFSETOF(type,field) + 1] = (a_uint8_t)(value); \ } #define A_GET_UINT8_FIELD(p,type,field) \ ((a_uint8_t *)(p))[A_OFFSETOF(type,field)] #define A_SET_UINT8_FIELD(p,type,field,value) \ ((a_uint8_t *)(p))[A_OFFSETOF(type,field)] = (value) /****** DANGER DANGER *************** * * The frame header length and message formats defined herein were * selected to accommodate optimal alignment for target processing. This reduces code * size and improves performance. * * Any changes to the header length may alter the alignment and cause exceptions * on the target. When adding to the message structures insure that fields are * properly aligned. * */ /* endpoint defines */ typedef enum { ENDPOINT_UNUSED = -1, ENDPOINT0 = 0, /* this is reserved for the control endpoint */ ENDPOINT1 = 1, ENDPOINT2 = 2, ENDPOINT3 = 3, ENDPOINT4, ENDPOINT5, ENDPOINT6, ENDPOINT7, ENDPOINT8, ENDPOINT_MAX = 22 /* maximum number of endpoints for this firmware build, max application endpoints = (ENDPOINT_MAX - 1) */ } HTC_ENDPOINT_ID; /* HTC frame header */ typedef PREPACK struct _HTC_FRAME_HDR{ /* do not remove or re-arrange these fields, these are minimally required * to take advantage of 4-byte lookaheads in some hardware implementations */ a_uint8_t EndpointID; a_uint8_t Flags; a_uint16_t PayloadLen; /* length of data (including trailer) that follows the header */ /***** end of 4-byte lookahead ****/ a_uint8_t ControlBytes[4]; /* message payload starts after the header */ } POSTPACK HTC_FRAME_HDR; /* frame header flags */ #define HTC_FLAGS_NEED_CREDIT_UPDATE (1 << 0) #define HTC_FLAGS_RECV_TRAILER (1 << 1) #define HTC_FLAGS_CREDIT_REDISTRIBUTION (1 << 2) #define HTC_HDR_LENGTH (sizeof(HTC_FRAME_HDR)) #define HTC_MAX_TRAILER_LENGTH 255 #define HTC_MAX_PAYLOAD_LENGTH (2048 - sizeof(HTC_FRAME_HDR)) /* HTC control message IDs */ typedef enum { HTC_MSG_READY_ID = 1, HTC_MSG_CONNECT_SERVICE_ID = 2, HTC_MSG_CONNECT_SERVICE_RESPONSE_ID = 3, HTC_MSG_SETUP_COMPLETE_ID = 4, HTC_MSG_CONFIG_PIPE_ID = 5, HTC_MSG_CONFIG_PIPE_RESPONSE_ID = 6, } HTC_MSG_IDS; #define HTC_MAX_CONTROL_MESSAGE_LENGTH 256 /* base message ID header */ typedef PREPACK struct { a_uint16_t MessageID; } POSTPACK HTC_UNKNOWN_MSG; /* HTC ready message * direction : target-to-host */ typedef PREPACK struct { a_uint16_t MessageID; /* ID */ a_uint16_t CreditCount; /* number of credits the target can offer */ a_uint16_t CreditSize; /* size of each credit */ a_uint8_t MaxEndpoints; /* maximum number of endpoints the target has resources for */ a_uint8_t _Pad1; } POSTPACK HTC_READY_MSG; #define HTC_SERVICE_META_DATA_MAX_LENGTH 128 /* connect service * direction : host-to-target */ typedef PREPACK struct { a_uint16_t MessageID; a_uint16_t ServiceID; /* service ID of the service to connect to */ a_uint16_t ConnectionFlags; /* connection flags */ a_uint8_t DownLinkPipeID; a_uint8_t UpLinkPipeID; #define HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE (1 << 2) /* reduce credit dribbling when the host needs credits */ #define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK (0x3) #define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH 0x0 #define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF 0x1 #define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS 0x2 #define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_UNITY 0x3 a_uint8_t ServiceMetaLength; /* length of meta data that follows */ a_uint8_t _Pad1; /* service-specific meta data starts after the header */ } POSTPACK HTC_CONNECT_SERVICE_MSG; /* connect response * direction : target-to-host */ typedef PREPACK struct { a_uint16_t MessageID; a_uint16_t ServiceID; /* service ID that the connection request was made */ a_uint8_t Status; /* service connection status */ a_uint8_t EndpointID; /* assigned endpoint ID */ a_uint16_t MaxMsgSize; /* maximum expected message size on this endpoint */ a_uint8_t ServiceMetaLength; /* length of meta data that follows */ a_uint8_t _Pad1; /* service-specific meta data starts after the header */ } POSTPACK HTC_CONNECT_SERVICE_RESPONSE_MSG; typedef PREPACK struct { a_uint16_t MessageID; /* currently, no other fields */ } POSTPACK HTC_SETUP_COMPLETE_MSG; /* config pipe * direction : host-to-target */ typedef PREPACK struct { a_uint16_t MessageID; a_uint8_t PipeID; /* Pipe ID of the service to connect to */ a_uint8_t CreditCount; /* CreditCount */ //a_uint8_t _Pad1; } POSTPACK HTC_CONFIG_PIPE_MSG; /* config pipe * direction : host-to-target */ typedef PREPACK struct { a_uint16_t MessageID; a_uint8_t PipeID; /* Pipe ID of the service to connect to */ a_uint8_t Status; /* status */ //a_uint8_t _Pad1; } POSTPACK HTC_CONFIG_PIPE_RESPONSE_MSG; /* connect response status codes */ #define HTC_SERVICE_SUCCESS 0 /* success */ #define HTC_SERVICE_NOT_FOUND 1 /* service could not be found */ #define HTC_SERVICE_FAILED 2 /* specific service failed the connect */ #define HTC_SERVICE_NO_RESOURCES 3 /* no resources (i.e. no more endpoints) */ #define HTC_SERVICE_NO_MORE_EP 4 /* specific service is not allowing any more endpoints */ /* shihhung: config pipe response status code */ #define HTC_CONFIGPIPE_SUCCESS 0 #define HTC_CONFIGPIPE_NOSUCHPIPE 1 #define HTC_CONFIGPIPE_NORESOURCE 2 /* report record IDs */ typedef enum { HTC_RECORD_NULL = 0, HTC_RECORD_CREDITS = 1, HTC_RECORD_LOOKAHEAD = 2, } HTC_RPT_IDS; typedef PREPACK struct { a_uint8_t RecordID; /* Record ID */ a_uint8_t Length; /* Length of record */ } POSTPACK HTC_RECORD_HDR; typedef PREPACK struct { a_uint8_t EndpointID; /* Endpoint that owns these credits */ a_uint8_t Credits; /* credits to report since last report */ } POSTPACK HTC_CREDIT_REPORT; typedef PREPACK struct { a_uint8_t PreValid; /* pre valid guard */ a_uint8_t LookAhead[4]; /* 4 byte lookahead */ a_uint8_t PostValid; /* post valid guard */ /* NOTE: the LookAhead array is guarded by a PreValid and Post Valid guard bytes. * The PreValid bytes must equal the inverse of the PostValid byte */ } POSTPACK HTC_LOOKAHEAD_REPORT; #ifndef ATH_TARGET //#include "athendpack.h" #endif #endif /* __HTC_H__ */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/include/htc_services.h000077500000000000000000000056471321570333100310220ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __HTC_SERVICES_H__ #define __HTC_SERVICES_H__ /* Current service IDs */ typedef enum { RSVD_SERVICE_GROUP = 0, WMI_SERVICE_GROUP = 1, HTC_TEST_GROUP = 254, HTC_SERVICE_GROUP_LAST = 255 } HTC_SERVICE_GROUP_IDS; #define MAKE_SERVICE_ID(group,index) \ (int)(((int)group << 8) | (int)(index)) /* NOTE: service ID of 0x0000 is reserved and should never be used */ #define HTC_CTRL_RSVD_SVC MAKE_SERVICE_ID(RSVD_SERVICE_GROUP,1) #define HTC_LOOPBACK_RSVD_SVC MAKE_SERVICE_ID(RSVD_SERVICE_GROUP,2) #define WMI_CONTROL_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,0) #define WMI_BEACON_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,1) #define WMI_CAB_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,2) #define WMI_UAPSD_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,3) #define WMI_MGMT_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,4) #define WMI_DATA_VO_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,5) #define WMI_DATA_VI_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,6) #define WMI_DATA_BE_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,7) #define WMI_DATA_BK_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,8) /* raw stream service (i.e. flash, tcmd, calibration apps) */ #define HTC_RAW_STREAMS_SVC MAKE_SERVICE_ID(HTC_TEST_GROUP,0) #endif /*HTC_SERVICES_H_*/ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/include/k2/000077500000000000000000000000001321570333100264655ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/include/k2/wlan_cfg.h000077500000000000000000000061421321570333100304240ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _WLAN_CFG_H_ #define _WLAN_CFG_H_ /************************** ATH configurations **************************/ #ifdef _DEBUG_BUILD_ #ifdef RX_SCATTER #define ATH_RXDESC 30 /* number of RX descriptors */ #endif #ifdef RX_SCATTER #define ATH_RXBUF ATH_RXDESC /* number of RX buffers */ #else #define ATH_RXBUF 15 /* number of RX buffers */ #endif #define ATH_TXBUF 26 /* number of TX buffers */ #else #ifdef RX_SCATTER #define ATH_RXDESC 11 /* number of RX descriptors */ #endif // end of _DEBUG_BUILD #ifdef RX_SCATTER #define ATH_RXBUF ATH_RXDESC /* number of RX buffers */ #else #define ATH_RXBUF 15 /* number of RX buffers */ #endif #define ATH_TXBUF 30 /* number of TX buffers */ #endif #ifdef FUSION_USB_FW #undef ATH_RXBUF #undef ATH_TXBUF #define ATH_RXBUF 11 #define ATH_TXBUF 33 #endif #define ATH_BCBUF 1 /* number of beacon buffers */ #define ATH_WMI_MAX_CMD_REPLY 2 #define ATH_WMI_MAX_EVENTS 8 //#define ATH_DISABLE_RC /* Use fixed rate instead of rate control */ #define ATH_BUF_OPTIMIZATION #define ATH_NO_VIRTUAL_MEMORY #define ATH_SUPPORT_XB_ONLY #define ATH_ENABLE_WLAN_FOR_K2 #define ATH_VERSION_MAJOR 1 #define ATH_VERSION_MINOR 4 /************************** HAL configurations **************************/ #define HAL_DESC_OPTIMIZATION #endif /* _WLAN_CFG_H_ */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/include/magpie/000077500000000000000000000000001321570333100274135ustar00rootroot00000000000000open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/include/magpie/wlan_cfg.h000077500000000000000000000053661321570333100313610ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _WLAN_CFG_H_ #define _WLAN_CFG_H_ /************************** ATH configurations **************************/ #ifdef RX_SCATTER #define ATH_RXDESC 40 /* number of RX descriptors */ #endif #ifdef RX_SCATTER #define ATH_RXBUF 40 /* number of RX buffers */ #else #define ATH_RXBUF 20 /* number of RX buffers */ #endif #define ATH_TXBUF 45 /* number of TX buffers */ #define ATH_BCBUF 1 /* number of beacon buffers */ #define ATH_WMI_MAX_CMD_REPLY 2 #define ATH_WMI_MAX_EVENTS 8 #ifdef FUSION_USB_FW #undef ATH_RXBUF #undef ATH_RXDESC #define ATH_RXDESC 20 #define ATH_RXBUF 20 #endif //#define ATH_DISABLE_RC /* Use fixed rate instead of rate control */ #define ATH_BUF_OPTIMIZATION #define ATH_NO_VIRTUAL_MEMORY //#define ATH_SUPPORT_XB_ONLY #define ATH_SUPPORT_A_MODE #define ATH_VERSION_MAJOR 1 #define ATH_VERSION_MINOR 4 /************************** HAL configurations **************************/ #define HAL_DESC_OPTIMIZATION #endif /* _WLAN_CFG_H_ */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/include/wlan_hdr.h000077500000000000000000000202321321570333100301220ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _WLAN_HDR_H #define _WLAN_HDR_H /* Please make sure the size of ALL headers is on word alignment */ #define M_FF 0x02 /* fast frame */ #define RX_STATS_SIZE 10 struct rx_frame_header { a_uint32_t rx_stats[RX_STATS_SIZE]; }; #define ATH_DATA_TYPE_AGGR 0x1 #define ATH_DATA_TYPE_NON_AGGR 0x2 #define ATH_SHORT_PREAMBLE 0x1 typedef struct _mgt_header { a_uint8_t ni_index; a_uint8_t vap_index; a_uint8_t tidno; a_uint8_t flags; a_int8_t keytype; a_int8_t keyix; a_uint8_t cookie; a_uint8_t pad; } POSTPACK ath_mgt_hdr_t; typedef struct _beacon_header { a_uint8_t vap_index; a_uint8_t len_changed; a_uint16_t reserved; } ath_beacon_hdr_t; #define M_LINK0 0x01 /* frame needs WEP encryption */ #define M_UAPSD 0x08 /* frame flagged for u-apsd handling */ /* Tx frame header flags definition */ //Reserved bit-0 for selfCTS //Reserved bit-1 for RTS #define TFH_FLAGS_USE_MIN_RATE 0x100 typedef struct __data_header { a_uint8_t datatype; a_uint8_t ni_index; a_uint8_t vap_index; a_uint8_t tidno; a_uint32_t flags; a_int8_t keytype; a_int8_t keyix; a_uint8_t cookie; a_uint8_t pad; } POSTPACK ath_data_hdr_t; #define RX_HEADER_SPACE HTC_HDR_LENGTH + sizeof(struct rx_frame_header) struct ieee80211com_target { a_uint32_t ic_ampdu_limit; a_uint8_t ic_ampdu_subframes; a_uint8_t ic_enable_coex; a_uint8_t ic_tx_chainmask; a_uint8_t pad; }; #define ATH_NODE_MAX 8 /* max no. of nodes */ #define ATH_VAP_MAX 2 /* max no. of vaps */ #define VAP_TARGET_SIZE 12 struct ieee80211vap_target { a_uint8_t iv_vapindex; a_uint8_t iv_opmode; /* enum ieee80211_opmode */ a_uint8_t iv_myaddr[IEEE80211_ADDR_LEN]; a_uint8_t iv_ath_cap; a_uint16_t iv_rtsthreshold; a_uint8_t pad; /* Internal */ a_uint8_t iv_nodeindex; struct ieee80211_node_target *iv_bss; }; /* NB: this must have the same value as IEEE80211_FC1_PWR_MGT */ #define IEEE80211_NODE_PWR_MGT 0x0010 /* power save mode enabled */ #define IEEE80211_NODE_AREF 0x0020 /* authentication ref held */ #define IEEE80211_NODE_UAPSD 0x0040 /* U-APSD power save enabled */ #define IEEE80211_NODE_UAPSD_TRIG 0x0080 /* U-APSD triggerable state */ #define IEEE80211_NODE_UAPSD_SP 0x0100 /* U-APSD SP in progress */ #define IEEE80211_NODE_ATH 0x0200 /* Atheros Owl or follow-on device */ #define IEEE80211_NODE_OWL_WORKAROUND 0x0400 /* Owl WDS workaround needed*/ #define IEEE80211_NODE_WDS 0x0800 /* WDS link */ #define NODE_TARGET_SIZE 22 struct ieee80211_node_target { a_uint8_t ni_macaddr[IEEE80211_ADDR_LEN]; a_uint8_t ni_bssid[IEEE80211_ADDR_LEN]; a_uint8_t ni_nodeindex; a_uint8_t ni_vapindex; a_uint8_t ni_is_vapnode; a_uint16_t ni_flags; a_uint16_t ni_htcap; a_uint16_t ni_maxampdu; a_uint8_t pad; /* * Internal. * Should move to ath_node_target later on ... */ a_uint16_t ni_txseqmgmt; a_uint16_t ni_iv16; a_uint32_t ni_iv32; struct ieee80211vap_target *ni_vap; }; struct ath_interrupt_stats { a_uint32_t ast_rx; a_uint32_t ast_rxorn; a_uint32_t ast_rxeol; a_uint32_t ast_txurn; a_uint32_t ast_txto; a_uint32_t ast_cst; }; struct ath_tx_stats { a_uint32_t ast_tx_xretries; /* tx failed 'cuz too many retries */ a_uint32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */ a_uint32_t ast_tx_filtered; /* tx failed 'cuz xmit filtered */ a_uint32_t ast_tx_timer_exp; /* tx timer expired */ a_uint32_t ast_tx_shortretry; /* tx on-chip retries (short) */ a_uint32_t ast_tx_longretry; /* tx on-chip retries (long) */ a_uint32_t ast_tx_rts; /* tx frames with rts enabled */ a_uint32_t ast_tx_altrate; /* tx frames with alternate rate */ a_uint32_t ast_tx_protect; /* tx frames with protection */ a_uint32_t tx_tgt; /* tx data pkts recieved on target */ a_uint32_t tx_qnull; /* txq empty occurences */ a_uint32_t txaggr_nframes; /* no. of frames aggregated */ a_uint32_t tx_compunaggr; /* tx unaggregated frame completions */ a_uint32_t tx_compaggr; /* tx aggregated completions */ a_uint32_t txaggr_retries; /* tx retries of sub frames */ a_uint32_t txaggr_single; /* tx frames not aggregated */ a_uint32_t txaggr_compgood; /* tx aggr good completions */ a_uint32_t txaggr_compretries; /* tx aggr unacked subframes */ a_uint32_t txaggr_prepends; /* tx aggr old frames requeued */ a_uint32_t txaggr_data_urun; /* data underrun for an aggregate */ a_uint32_t txaggr_delim_urun; /* delimiter underrun for an aggr */ a_uint32_t txaggr_errlast; /* tx aggr: last sub-frame failed */ a_uint32_t txaggr_longretries; /* tx aggr h/w long retries */ a_uint32_t txaggr_babug; /* tx aggr : BA bug */ a_uint32_t txaggr_compxretry; /* tx aggr excessive retries */ a_uint32_t txaggr_shortretries;/* tx aggr h/w short retries */ a_uint32_t txaggr_timer_exp; /* tx aggr : tx timer expired */ a_uint32_t txunaggr_compretries; /* tx non-aggr unacked subframes */ a_uint32_t txaggr_filtered; /* filtered aggr packet */ a_uint32_t txaggr_fifo; /* fifo underrun of aggregate */ a_uint32_t txaggr_xtxop; /* txop exceeded for an aggregate */ a_uint32_t txaggr_desc_cfgerr; /* aggr descriptor config error */ a_uint32_t txunaggr_errlast; /* tx non-aggr: last frame failed */ a_uint32_t txunaggr_xretry; /* tx unaggregated excessive retries */ a_uint32_t txaggr_xretries; /* tx excessive retries of aggr */ a_uint32_t tx_stopfiltered; /* tx pkts filtered for requeueing */ a_uint32_t tx_noskbs; /* tx no skbs for encapsulations */ a_uint32_t tx_nobufs; /* tx no descriptors */ a_uint32_t tx_bars; /* tx bars sent */ a_uint32_t txbar_xretry; /* tx bars excessively retried */ a_uint32_t txbar_compretries; /* tx bars retried */ a_uint32_t txbar_errlast; /* tx bars last frame failed */ }; struct ath_rx_stats { a_uint32_t ast_rx_nobuf; /* rx setup failed 'cuz no skbuff */ a_uint32_t ast_rx_send; a_uint32_t ast_rx_done; }; struct ath_aggr_info { a_uint8_t nodeindex; a_uint8_t tidno; a_uint8_t aggr_enable; a_uint8_t padding; }; struct wmi_data_delba { a_uint8_t ni_nodeindex; a_uint8_t tidno; a_uint8_t initiator; a_uint8_t reasoncode; }; struct wmi_fw_version { a_uint16_t major; a_uint16_t minor; }; #endif open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/include/wmi.h000077500000000000000000000202561321570333100271260ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * This file contains the definitions of the WMI protocol specified in the * Wireless Module Interface (WMI). It includes definitions of all the * commands and events. Commands are messages from the host to the WM. * Events and Replies are messages from the WM to the host. * * Ownership of correctness in regards to WMI commands * belongs to the host driver and the WM is not required to validate * parameters for value, proper range, or any other checking. * * $Id: //depot/sw/branches/fusion_usb/target_firmware/wlan/include/wmi.h#6 $ */ #ifndef _WMI_H_ #define _WMI_H_ #include "athdefs.h" #ifdef __cplusplus extern "C" { #endif #define HTC_PROTOCOL_VERSION 0x0002 #define HTC_PROTOCOL_REVISION 0x0000 #define WMI_PROTOCOL_VERSION 0x0002 #define WMI_PROTOCOL_REVISION 0x0000 #define ATH_MAC_LEN 6 /* length of mac in bytes */ #define WMI_CMD_MAX_LEN 100 #define WMI_CONTROL_MSG_MAX_LEN 256 #define WMI_OPT_CONTROL_MSG_MAX_LEN 1536 #define IS_ETHERTYPE(_typeOrLen) ((_typeOrLen) >= 0x0600) #define RFC1042OUI {0x00, 0x00, 0x00} #define IP_ETHERTYPE 0x0800 #define WMI_IMPLICIT_PSTREAM 0xFF #define WMI_MAX_THINSTREAM 15 struct host_app_area_s { a_uint32_t wmi_protocol_ver; }; /* * Data Path */ typedef PREPACK struct { a_uint8_t dstMac[ATH_MAC_LEN]; a_uint8_t srcMac[ATH_MAC_LEN]; a_uint16_t typeOrLen; } POSTPACK ATH_MAC_HDR; typedef PREPACK struct { a_uint8_t dsap; a_uint8_t ssap; a_uint8_t cntl; a_uint8_t orgCode[3]; a_uint16_t etherType; } POSTPACK ATH_LLC_SNAP_HDR; typedef enum { DATA_MSGTYPE = 0x0, CNTL_MSGTYPE, SYNC_MSGTYPE, OPT_MSGTYPE, } WMI_MSG_TYPE; typedef PREPACK struct { a_int8_t rssi; a_uint8_t info; /* WMI_MSG_TYPE in lower 2 bits - b1b0 */ /* UP in next 3 bits - b4b3b2 */ #define WMI_DATA_HDR_MSG_TYPE_MASK 0x03 #define WMI_DATA_HDR_MSG_TYPE_SHIFT 0 #define WMI_DATA_HDR_UP_MASK 0x07 #define WMI_DATA_HDR_UP_SHIFT 2 #define WMI_DATA_HDR_IS_MSG_TYPE(h, t) (((h)->info & (WMI_DATA_HDR_MSG_TYPE_MASK)) == (t)) } POSTPACK WMI_DATA_HDR; #define WMI_DATA_HDR_SET_MSG_TYPE(h, t) (h)->info = (((h)->info & ~(WMI_DATA_HDR_MSG_TYPE_MASK << WMI_DATA_HDR_MSG_TYPE_SHIFT)) | (t << WMI_DATA_HDR_MSG_TYPE_SHIFT)) #define WMI_DATA_HDR_SET_UP(h, p) (h)->info = (((h)->info & ~(WMI_DATA_HDR_UP_MASK << WMI_DATA_HDR_UP_SHIFT)) | (p << WMI_DATA_HDR_UP_SHIFT)) /* * Control Path */ typedef PREPACK struct { a_uint16_t commandId; a_uint16_t seqNo; } POSTPACK WMI_CMD_HDR; /* used for commands and events */ /* * List of Commnands */ typedef enum { WMI_ECHO_CMDID = 0x0001, WMI_ACCESS_MEMORY_CMDID, /* Commands to Target */ WMI_GET_FW_VERSION, WMI_DISABLE_INTR_CMDID, WMI_ENABLE_INTR_CMDID, WMI_ATH_INIT_CMDID, WMI_ABORT_TXQ_CMDID, WMI_STOP_TX_DMA_CMDID, WMI_ABORT_TX_DMA_CMDID, WMI_DRAIN_TXQ_CMDID, WMI_DRAIN_TXQ_ALL_CMDID, WMI_START_RECV_CMDID, WMI_STOP_RECV_CMDID, WMI_FLUSH_RECV_CMDID, WMI_SET_MODE_CMDID, WMI_NODE_CREATE_CMDID, WMI_NODE_REMOVE_CMDID, WMI_VAP_REMOVE_CMDID, WMI_VAP_CREATE_CMDID, WMI_REG_READ_CMDID, WMI_REG_WRITE_CMDID, WMI_RC_STATE_CHANGE_CMDID, WMI_RC_RATE_UPDATE_CMDID, WMI_TARGET_IC_UPDATE_CMDID, WMI_TX_AGGR_ENABLE_CMDID, WMI_TGT_DETACH_CMDID, WMI_NODE_UPDATE_CMDID, WMI_INT_STATS_CMDID, WMI_TX_STATS_CMDID, WMI_RX_STATS_CMDID, WMI_BITRATE_MASK_CMDID, WMI_REG_RMW_CMDID, } WMI_COMMAND_ID; /* * Frame Types */ typedef enum { WMI_FRAME_BEACON = 0, WMI_FRAME_PROBE_REQ, WMI_FRAME_PROBE_RESP, WMI_FRAME_ASSOC_REQ, WMI_FRAME_ASSOC_RESP, WMI_NUM_MGMT_FRAME } WMI_MGMT_FRAME_TYPE; /* * Connect Command */ typedef enum { INFRA_NETWORK = 0x01, ADHOC_NETWORK = 0x02, ADHOC_CREATOR = 0x04, OPT_NETWORK = 0x08, } NETWORK_TYPE; typedef enum { OPEN_AUTH = 0x01, SHARED_AUTH = 0x02, LEAP_AUTH = 0x04, /* different from IEEE_AUTH_MODE definitions */ } DOT11_AUTH_MODE; typedef enum { NONE_AUTH = 0x01, WPA_AUTH = 0x02, WPA_PSK_AUTH = 0x03, WPA2_AUTH = 0x04, WPA2_PSK_AUTH = 0x05, WPA_AUTH_CCKM = 0x06, WPA2_AUTH_CCKM = 0x07, } AUTH_MODE; typedef enum { NONE_CRYPT = 0x01, WEP_CRYPT = 0x02, TKIP_CRYPT = 0x03, AES_CRYPT = 0x04, } CRYPTO_TYPE; #define WMI_MIN_CRYPTO_TYPE NONE_CRYPT #define WMI_MAX_CRYPTO_TYPE (AES_CRYPT + 1) #define WMI_MIN_KEY_INDEX 0 #define WMI_MAX_KEY_INDEX 3 #define WMI_MAX_KEY_LEN 32 #define WMI_MAX_SSID_LEN 32 typedef enum { CONNECT_ASSOC_POLICY_USER = 0x0001, CONNECT_SEND_REASSOC = 0x0002, CONNECT_IGNORE_WPAx_GROUP_CIPHER = 0x0004, CONNECT_PROFILE_MATCH_DONE = 0x0008, CONNECT_IGNORE_AAC_BEACON = 0x0010, CONNECT_CSA_FOLLOW_BSS = 0x0020, } WMI_CONNECT_CTRL_FLAGS_BITS; #define DEFAULT_CONNECT_CTRL_FLAGS (CONNECT_CSA_FOLLOW_BSS) /* * WMI_ECHO_CMDID */ #define WMI_ECHOCMD_MSG_MAX_LEN 53//64 - HTC_HDR_LENGTH + sizeof(WMI_CMD_HDR) - 1 typedef PREPACK struct { a_uint8_t msgSize; a_uint8_t msgData[1]; } POSTPACK WMI_ECHO_CMD; /* * WMI_ACCESS_MEMORY_CMDID */ #define WMI_ACCESS_MEMORY_MAX_TUPLES 8 typedef PREPACK struct { a_uint16_t addressL; a_uint16_t addressH; a_uint16_t valueL; a_uint16_t valueH; } POSTPACK WMI_AVT; typedef PREPACK struct { a_uint16_t tupleNumL; a_uint16_t tupleNumH; WMI_AVT avt[1]; } POSTPACK WMI_ACCESS_MEMORY_CMD; /* * List of Events (target to host) */ typedef enum { WMI_TGT_RDY_EVENTID = 0x1001, WMI_SWBA_EVENTID, WMI_FATAL_EVENTID, WMI_TXTO_EVENTID, WMI_BMISS_EVENTID, WMI_DELBA_EVENTID, WMI_TXSTATUS_EVENTID } WMI_EVENT_ID; typedef PREPACK struct { a_uint64_t tsf; a_uint8_t beaconPendingCount; } POSTPACK WMI_SWBA_EVENT; typedef PREPACK struct { a_uint8_t cookie; a_uint8_t ts_rate; a_uint8_t ts_flags; } POSTPACK __WMI_TXSTATUS_EVENT; #define HTC_MAX_TX_STATUS 12 typedef PREPACK struct { a_uint8_t cnt; __WMI_TXSTATUS_EVENT txstatus[HTC_MAX_TX_STATUS]; } POSTPACK WMI_TXSTATUS_EVENT; struct register_rmw { a_uint32_t reg; a_uint32_t set; a_uint32_t clr; }; #ifndef ATH_TARGET //#include "athendpack.h" #endif #ifdef __cplusplus } #endif #endif /* _WMI_H_ */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/ratectrl.h000077500000000000000000000233211321570333100265230ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _RATECTRL_H_ #define _RATECTRL_H_ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "if_athrate.h" #include "if_athvar.h" #define FALSE 0 #define TRUE 1 typedef int8_t A_RSSI; typedef int32_t A_RSSI32; typedef u_int8_t WLAN_PHY; #ifndef INLINE #define INLINE __inline #endif #ifndef A_MIN #define A_MIN(a,b) ((a)<(b)?(a):(b)) #endif #ifndef A_MAX #define A_MAX(a,b) ((a)>(b)?(a):(b)) #endif /* * Use the hal os glue code to get ms time; we supply * a null arg because we know it's not needed. */ #define A_MS_TICKGET() OS_GETUPTIME(NULL) #define WLAN_PHY_OFDM IEEE80211_T_OFDM #define WLAN_PHY_TURBO IEEE80211_T_TURBO #define WLAN_PHY_CCK IEEE80211_T_CCK #define WLAN_PHY_XR (IEEE80211_T_TURBO+1) enum { WLAN_RC_PHY_CCK, WLAN_RC_PHY_OFDM, WLAN_RC_PHY_TURBO, WLAN_RC_PHY_XR, WLAN_RC_PHY_HT_20_SS, WLAN_RC_PHY_HT_20_DS, WLAN_RC_PHY_HT_40_SS, WLAN_RC_PHY_HT_40_DS, WLAN_RC_PHY_HT_20_SS_HGI, WLAN_RC_PHY_HT_20_DS_HGI, WLAN_RC_PHY_HT_40_SS_HGI, WLAN_RC_PHY_HT_40_DS_HGI, WLAN_RC_PHY_MAX }; #define IS_CHAN_TURBO(_c) (((_c)->channelFlags & CHANNEL_TURBO) != 0) #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0) #define PKTLOG_RATE_CTL_FIND(_sc, log_data, flags) ath_log_rcfind(_sc, log_data, flags); #define PKTLOG_RATE_CTL_UPDATE(_sc, log_data, flags) ath_log_rcupdate(_sc, log_data, flags); #define ASSERT(condition) #define WIRELESS_MODE_11NA IEEE80211_MODE_11NA #define WIRELESS_MODE_11NG IEEE80211_MODE_11NG #define WIRELESS_MODE_MAX IEEE80211_MODE_MAX #define RX_FLIP_THRESHOLD 3 /* XXX */ #ifdef MAGPIE_MERLIN #define MAX_TX_RATE_TBL 46 #else #define MAX_TX_RATE_TBL 54//46 #endif /* * State structures for new rate adaptation code * * NOTE: Modifying these structures will impact * the Perl script that parses packet logging data. * See the packet logging module for more information. */ typedef struct TxRateCrtlState_s { A_UINT8 per; /* recent estimate of packet error rate (%) */ } TxRateCtrlState; typedef struct TxRateCtrl_s { TxRateCtrlState state[MAX_TX_RATE_TBL]; /* state for each rate */ A_UINT8 rateTableSize; /* rate table size */ A_UINT8 probeRate; /* rate we are probing at */ A_UINT32 rssiTime; /* msec timestamp for last ack rssi */ A_UINT32 probeTime; /* msec timestamp for last probe */ A_UINT8 hwMaxRetryPktCnt; /* num packets since we got HW max retry error */ A_UINT8 maxValidRate; /* maximum number of valid rate */ A_UINT8 validRateIndex[MAX_TX_RATE_TBL]; /* rc Index is valid for this Sib */ A_UINT32 perDownTime; /* msec timstamp for last PER down step */ A_UINT8 rcPhyMode; A_UINT8 rateMaxPhy; /* Phy index for the max rate */ } TX_RATE_CTRL; typedef struct phy_rate_ctrl { /* 11n state */ A_UINT8 validPhyRateCount[WLAN_RC_PHY_MAX]; /* valid rate count */ A_UINT8 validPhyRateIndex[WLAN_RC_PHY_MAX][MAX_TX_RATE_TBL]; /* index */ }PHY_STATE_CTRL; /* per-node state */ struct atheros_node { TX_RATE_CTRL txRateCtrl; /* rate control state proper */ A_UINT32 lastRateKbps; /* last rate in Kb/s */ A_UINT8 singleStream :1, /* When TRUE, only single stream Tx possible */ stbc :2; /* Rx stbc capability */ }; #define ATH_NODE_ATHEROS(an) (an->an_rcnode) /* * Rate Table structure for various modes - 'b', 'a', 'g', 'xr'; * order of fields in info structure is important because hardcoded * structures are initialized within the hal for these */ typedef struct { int rateCount; A_UINT8 rateCodeToIndex[RATE_TABLE_SIZE]; /* backward mapping */ struct { int valid; /* Valid for use in rate control */ WLAN_PHY phy; /* CCK/OFDM/TURBO/XR */ A_UINT16 rateKbps; /* Rate in Kbits per second */ A_UINT16 userRateKbps; /* User rate in KBits per second */ A_UINT8 rateCode; /* rate that goes into hw descriptors */ A_UINT8 shortPreamble; /* Mask for enabling short preamble in rate code for CCK */ A_UINT8 dot11Rate; /* Value that goes into supported rates info element of MLME */ A_UINT8 controlRate; /* Index of next lower basic rate, used for duration computation */ A_RSSI rssiAckValidMin; /* Rate control related information */ A_RSSI rssiAckDeltaMin; /* Rate control related information */ A_UINT16 lpAckDuration; /* long preamble ACK duration */ A_UINT16 spAckDuration; /* short preamble ACK duration*/ A_UINT32 max4msFrameLen; /* Maximum frame length(bytes) for 4ms tx duration */ struct { A_UINT32 word4Retries; A_UINT32 word5Rates; } normalSched; struct { A_UINT32 word4Retries; A_UINT32 word5Rates; } shortSched; struct { A_UINT32 word4Retries; A_UINT32 word5Rates; } probeSched; struct { A_UINT32 word4Retries; A_UINT32 word5Rates; } probeShortSched; struct { A_UINT32 word4Retries; A_UINT32 word5Rates; } uapsd_normalSched; struct { A_UINT32 word4Retries; A_UINT32 word5Rates; } uapsd_shortSched; #ifdef ATH_REMOVE_5G_RATE_TABLE #ifdef ATH_REMOVE_TURBO_RATE_TABLE #ifdef ATH_REMOVE_XR_RATE_TABLE } info[12]; #else } info[32]; #endif #else } info[32]; #endif #else } info[32]; #endif A_UINT32 probeInterval; /* interval for ratectrl to probe for other rates */ A_UINT32 rssiReduceInterval; /* interval for ratectrl to reduce RSSI */ A_UINT8 regularToTurboThresh; /* upperbound on regular (11a or 11g) mode's rate before switching to turbo*/ A_UINT8 turboToRegularThresh; /* lowerbound on turbo mode's rate before switching to regular */ A_UINT8 pktCountThresh; /* mode switch recommendation criterion: number of consecutive packets sent at rate beyond the rate threshold */ A_UINT8 initialRateMax; /* the initial rateMax value used in rcSibUpdate() */ A_UINT8 numTurboRates; /* number of Turbo rates in the rateTable */ A_UINT8 xrToRegularThresh; /* threshold to switch to Normal mode */ } RATE_TABLE; /* per-device state */ struct atheros_softc { struct ath_ratectrl arc; /* phy tables that contain rate control data */ void *hwRateTable[WIRELESS_MODE_MAX]; A_UINT32 tx_chainmask; A_UINT32 currentTxRateKbps; A_UINT32 currentTxRateIndex; }; /* * Update the SIB's rate control information * * This should be called when the supported rates change * (e.g. SME operation, wireless mode change) * * It will determine which rates are valid for use. */ void rcSibUpdate(struct ath_softc_tgt *sc, struct ath_node_target *an, A_BOOL keepState, struct ieee80211_rateset *pRateSet); /* * This routine is called to initialize the rate control parameters * in the SIB. It is called initially during system initialization * or when a station is associated with the AP. */ void rcSibInit(struct ath_softc_tgt *, struct ath_node_target *); /* * Determines and returns the new Tx rate index. */ A_UINT16 rcRateFind(struct ath_softc_tgt *, struct atheros_node *, A_UINT32 frameLen,const RATE_TABLE *pRateTable); struct fusion_rate_info { A_UINT32 txrate; A_UINT8 rssi; A_UINT8 per; }; void ar5416AttachRateTables(struct atheros_softc *sc); void ath_rate_node_update(struct ath_softc_tgt *sc, struct ath_node_target *an, a_int32_t isnew, a_uint32_t capflag, struct ieee80211_rate *rs); void ath_rate_newstate(struct ath_softc_tgt *sc, struct ieee80211vap_target *vap, enum ieee80211_state state, a_uint32_t capflag, struct ieee80211_rate *rs); #endif /* _RATECTRL_H_ */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/ratectrl11n.h000077500000000000000000000162551321570333100270530ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _RATECTRL11N_H_ #define _RATECTRL11N_H_ /* HT 20/40 rates. If 20 bit is enabled then that rate is * used only in 20 mode. If both 20/40 bits are enabled * then that rate can be used for both 20 and 40 mode */ #define TRUE_20 0x2 #define TRUE_40 0x4 #define TRUE_2040 (TRUE_20|TRUE_40) #define TRUE_ALL_11N (TRUE_2040|TRUE) enum { WLAN_RC_DS = 0x01, WLAN_RC_40 = 0x02, WLAN_RC_SGI = 0x04, WLAN_RC_HT = 0x08, }; typedef enum { WLAN_RC_LEGACY = 0, WLAN_RC_HT_LNPHY = 1, WLAN_RC_HT_PLPHY = 2, WLAN_RC_MAX = 3 } WLAN_RC_VERS; #define WLAN_RC_PHY_DS(_phy) ((_phy == WLAN_RC_PHY_HT_20_DS) \ || (_phy == WLAN_RC_PHY_HT_40_DS) \ || (_phy == WLAN_RC_PHY_HT_20_DS_HGI) \ || (_phy == WLAN_RC_PHY_HT_40_DS_HGI)) #define WLAN_RC_PHY_40(_phy) ((_phy == WLAN_RC_PHY_HT_40_SS) \ || (_phy == WLAN_RC_PHY_HT_40_DS) \ || (_phy == WLAN_RC_PHY_HT_40_SS_HGI) \ || (_phy == WLAN_RC_PHY_HT_40_DS_HGI)) #define WLAN_RC_PHY_20(_phy) ((_phy == WLAN_RC_PHY_HT_20_SS) \ || (_phy == WLAN_RC_PHY_HT_20_DS) \ || (_phy == WLAN_RC_PHY_HT_20_SS_HGI) \ || (_phy == WLAN_RC_PHY_HT_20_DS_HGI)) #define WLAN_RC_PHY_SGI(_phy) ((_phy == WLAN_RC_PHY_HT_20_SS_HGI) \ || (_phy == WLAN_RC_PHY_HT_20_DS_HGI) \ || (_phy == WLAN_RC_PHY_HT_40_SS_HGI) \ || (_phy == WLAN_RC_PHY_HT_40_DS_HGI)) #define WLAN_RC_PHY_HT(_phy) (_phy >= WLAN_RC_PHY_HT_20_SS) /* Returns the capflag mode */ #define WLAN_RC_CAP_MODE(capflag) (((capflag & WLAN_RC_HT_FLAG)? \ (capflag & WLAN_RC_40_FLAG)?TRUE_40:TRUE_20: \ TRUE)) /* Return TRUE if flag supports HT20 && client supports HT20 or * return TRUE if flag supports HT40 && client supports HT40. * This is used becos some rates overlap between HT20/HT40. */ #define WLAN_RC_PHY_HT_VALID(flag, capflag) (((flag & TRUE_20) && !(capflag \ & WLAN_RC_40_FLAG)) || ((flag & TRUE_40) && \ (capflag & WLAN_RC_40_FLAG))) #define WLAN_RC_DS_FLAG (0x01) #define WLAN_RC_40_FLAG (0x02) #define WLAN_RC_HT40_SGI_FLAG (0x04) #define WLAN_RC_HT_FLAG (0x08) #define WLAN_RC_STBC_FLAG (0x30) /* 2 bits */ #define WLAN_RC_STBC_FLAG_S ( 4) #define WLAN_RC_WEP_TKIP_FLAG (0x100) /* Index into the rate table */ #define INIT_RATE_MAX_20 23 #define INIT_RATE_MAX_40 40 /* * Rate Table structure for various modes - 'b', 'a', 'g', 'xr'; * order of fields in info structure is important because hardcoded * structures are initialized within the hal for these */ #ifndef MAGPIE_MERLIN // K2 #define RATE_TABLE_11N_SIZE 54 #else #define RATE_TABLE_11N_SIZE 64 #endif #define MAX_SUPPORTED_MCS 128 typedef struct regDataLenTable { A_UINT8 numEntries; A_UINT16 frameLenRateIndex[RATE_TABLE_11N_SIZE]; } REG_DATALEN_TABLE; typedef struct { A_BOOL valid; /* Valid for use in rate control */ A_BOOL validSingleStream;/* Valid for use in rate control for single stream operation */ #ifdef MAGPIE_MERLIN A_BOOL validSTBC; /* Valid for use in rate control for single stream operation */ #endif WLAN_PHY phy; /* CCK/OFDM/TURBO/XR */ A_UINT32 rateKbps; /* Rate in Kbits per second */ A_UINT32 userRateKbps; /* User rate in KBits per second */ A_UINT8 rateCode; /* rate that goes into hw descriptors */ A_UINT8 shortPreamble; /* Mask for enabling short preamble in rate code for CCK */ A_UINT8 dot11Rate; /* Value that goes into supported rates info element of MLME */ A_UINT8 controlRate; /* Index of next lower basic rate, used for duration computation */ A_RSSI rssiAckValidMin; /* Rate control related information */ A_RSSI rssiAckDeltaMin; /* Rate control related information */ A_UINT8 baseIndex; /* base rate index */ A_UINT8 cw40Index; /* 40cap rate index */ A_UINT8 sgiIndex; /* shortgi rate index */ A_UINT8 htIndex; /* shortgi rate index */ A_UINT8 txChainMask_2ch; /* transmit chain mask */ A_UINT8 txChainMask_3ch; /* transmit chain mask */ A_UINT32 max4msframelen; /* Maximum frame length(bytes) for 4ms tx duration */ A_BOOL uapsdvalid; /* Valid for UAPSD nodes */ } rc11n_info_t; typedef struct { A_UINT8 rateCount; A_UINT8 probeInterval; /* interval for ratectrl to probe for other rates */ A_UINT8 rssiReduceInterval; /* interval for ratectrl to reduce RSSI */ A_UINT8 initialRateMax; /* the initial rateMax value used in rcSibUpdate() */ rc11n_info_t info[]; } RATE_TABLE_11N; /* * Determines and returns the new Tx rate index. */ void rcRateFind_11n(struct ath_softc_tgt *sc, struct ath_node_target *an, int numTries, int numRates, int stepDnInc, unsigned int rcflag, struct ath_rc_series series[], int *isProbe); /* * This routine is called by the Tx interrupt service routine to give * the status of previous frames. */ void rcUpdate_11n(struct ath_softc_tgt *sc, struct ath_node_target *an, A_UINT8 curTxAnt, int finalTSIdx, int Xretries, struct ath_rc_series rcs[], int nFrames, int nBad, int sh_lo_retry); #endif /* _RATECTRL11N_H_ */ open-ath9k-htc-firmware-1.4.0-97-g75b3e59+dfsg/target_firmware/wlan/ratectrl_11n_ln.c000077500000000000000000001005741321570333100276740ustar00rootroot00000000000000/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * * Neither the name of Qualcomm Atheros nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "ah_desc.h" #include "ratectrl.h" #include "ratectrl11n.h" static void ath_rate_newassoc_11n(struct ath_softc_tgt *sc, struct ath_node_target *an, int isnew, unsigned int capflag, struct ieee80211_rate *rs); static void ath_rate_tx_complete_11n(struct ath_softc_tgt *sc, struct ath_node_target *an, struct ath_tx_desc *ds, struct ath_rc_series rcs[], int nframes, int nbad); static void ath_rate_findrate_11n(struct ath_softc_tgt *sc, struct ath_node_target *an, size_t frameLen, int numTries, int numRates, int stepDnInc, unsigned int rcflag, struct ath_rc_series series[], int *isProbe); static void rcSortValidRates(const RATE_TABLE_11N *pRateTable, TX_RATE_CTRL *pRc) { A_UINT8 i,j; for (i=pRc->maxValidRate-1; i > 0; i--) { for (j=0; j <= i-1; j++) { #ifdef MAGPIE_MERLIN if (pRateTable->info[pRc->validRateIndex[j]].rateKbps > pRateTable->info[pRc->validRateIndex[j+1]].rateKbps) #else // K2 if (pRateTable->info[pRc->validRateIndex[j]].userRateKbps > pRateTable->info[pRc->validRateIndex[j+1]].userRateKbps) #endif { A_UINT8 tmp=0; tmp = pRc->validRateIndex[j]; pRc->validRateIndex[j] = pRc->validRateIndex[j+1]; pRc->validRateIndex[j+1] = tmp; } } } } /* Access functions for validTxRateMask */ static void rcInitValidTxMask(TX_RATE_CTRL *pRc) { A_UINT8 i; for (i = 0; i < pRc->rateTableSize; i++) { pRc->validRateIndex[i] = FALSE; } } static INLINE void rcSetValidTxMask(TX_RATE_CTRL *pRc, A_UINT8 index, A_BOOL validTxRate) { ASSERT(index < pRc->rateTableSize); pRc->validRateIndex[index] = validTxRate ? TRUE : FALSE; } /* Iterators for validTxRateMask */ static INLINE A_BOOL rcGetNextValidTxRate(const RATE_TABLE_11N *pRateTable, TX_RATE_CTRL *pRc, A_UINT8 curValidTxRate, A_UINT8 *pNextIndex) { A_UINT8 i; for (i = 0; i < pRc->maxValidRate-1; i++) { if (pRc->validRateIndex[i] == curValidTxRate) { *pNextIndex = pRc->validRateIndex[i+1]; return TRUE; } } /* No more valid rates */ *pNextIndex = 0; return FALSE; } static INLINE A_BOOL rcGetNextLowerValidTxRate(const RATE_TABLE_11N *pRateTable, TX_RATE_CTRL *pRc, A_UINT8 curValidTxRate, A_UINT8 *pNextIndex) { A_INT8 i; for (i = 1; i < pRc->maxValidRate ; i++) { if (pRc->validRateIndex[i] == curValidTxRate) { *pNextIndex = pRc->validRateIndex[i-1]; return TRUE; } } return FALSE; } /* Return true only for single stream */ static A_BOOL rcIsValidPhyRate(A_UINT32 phy, A_UINT32 capflag, A_BOOL ignoreCW) { if (WLAN_RC_PHY_HT(phy) && !(capflag & WLAN_RC_HT_FLAG)) { return FALSE; } if (WLAN_RC_PHY_DS(phy) && !(capflag & WLAN_RC_DS_FLAG)) { return FALSE; } if (WLAN_RC_PHY_SGI(phy) && !(capflag & WLAN_RC_HT40_SGI_FLAG)) { return FALSE; } if (!ignoreCW && WLAN_RC_PHY_HT(phy)) { if (WLAN_RC_PHY_40(phy) && !(capflag & WLAN_RC_40_FLAG)) { return FALSE; } if (!WLAN_RC_PHY_40(phy) && (capflag & WLAN_RC_40_FLAG)) { return FALSE; } } return TRUE; } /* * Initialize the Valid Rate Index from valid entries in Rate Table */ static A_UINT8 rcSibInitValidRates(const RATE_TABLE_11N *pRateTable, TX_RATE_CTRL *pRc, A_UINT32 capflag, PHY_STATE_CTRL *pPhyStateCtrl) { A_UINT8 i, hi = 0; A_UINT8 singleStream = (capflag & WLAN_RC_DS_FLAG) ? 0 : 1; A_UINT8 valid; for (i = 0; i < pRateTable->rateCount; i++) { if (singleStream) { valid = pRateTable->info[i].validSingleStream; } else { valid = pRateTable->info[i].valid; } if (valid == TRUE) { A_UINT32 phy = pRateTable->info[i].phy; if (!rcIsValidPhyRate(phy, capflag, FALSE)) continue; pPhyStateCtrl->validPhyRateIndex[phy][pPhyStateCtrl->validPhyRateCount[phy]] = i; pPhyStateCtrl->validPhyRateCount[phy] += 1; rcSetValidTxMask(pRc, i, TRUE); hi = A_MAX(hi, i); } } return hi; } /* * Initialize the Valid Rate Index from Rate Set */ static A_UINT8 rcSibSetValidRates(const RATE_TABLE_11N *pRateTable, TX_RATE_CTRL *pRc, struct ieee80211_rateset *pRateSet, A_UINT32 capflag, struct ath_node_target *an, PHY_STATE_CTRL *pPhyStateCtrl) { A_UINT8 i, j, hi = 0; A_UINT8 singleStream = (capflag & WLAN_RC_DS_FLAG) ? 0 : 1; A_UINT32 valid; /* Use intersection of working rates and valid rates */ for (i = 0; i < pRateSet->rs_nrates; i++) { for (j = 0; j < pRateTable->rateCount; j++) { A_UINT32 phy = pRateTable->info[j].phy; #ifdef MAGPIE_MERLIN struct atheros_node *pSib = ATH_NODE_ATHEROS(an); if (pSib->stbc) { valid = pRateTable->info[j].validSTBC; } else if (singleStream) { #else if (singleStream) { #endif valid = pRateTable->info[j].validSingleStream; } else { valid = pRateTable->info[j].valid; } /* * We allow a rate only if its valid and the capflag matches one of * the validity (TRUE/TRUE_20/TRUE_40) flags */ if (((pRateSet->rs_rates[i] & 0x7F) == (pRateTable->info[j].dot11Rate & 0x7F)) && ((valid & WLAN_RC_CAP_MODE(capflag)) == WLAN_RC_CAP_MODE(capflag)) && !WLAN_RC_PHY_HT(phy)) { if (!rcIsValidPhyRate(phy, capflag, FALSE)) continue; pPhyStateCtrl->validPhyRateIndex[phy][pPhyStateCtrl->validPhyRateCount[phy]] = j; pPhyStateCtrl->validPhyRateCount[phy] += 1; rcSetValidTxMask(pRc, j, TRUE); hi = A_MAX(hi, j); } } } return hi; } static A_UINT8 rcSibSetValidHtRates(const RATE_TABLE_11N *pRateTable, TX_RATE_CTRL *pRc, A_UINT8 *pMcsSet, A_UINT32 capflag, struct ath_node_target *an, PHY_STATE_CTRL *pPhyStateCtrl) { A_UINT8 i, j, hi = 0; A_UINT8 singleStream = (capflag & WLAN_RC_DS_FLAG) ? 0 : 1; A_UINT8 valid; /* Use intersection of working rates and valid rates */ for (i = 0; i < ((struct ieee80211_rateset *)pMcsSet)->rs_nrates; i++) { for (j = 0; j < pRateTable->rateCount; j++) { A_UINT32 phy = pRateTable->info[j].phy; #ifdef MAGPIE_MERLIN struct atheros_node *pSib = ATH_NODE_ATHEROS(an); if (pSib->stbc) { valid = pRateTable->info[j].validSTBC; } else if (singleStream) { #else if (singleStream) { #endif valid = pRateTable->info[j].validSingleStream; } else { valid = pRateTable->info[j].valid; } if (((((struct ieee80211_rateset *)pMcsSet)->rs_rates[i] & 0x7F) != (pRateTable->info[j].dot11Rate & 0x7F)) || !WLAN_RC_PHY_HT(phy) || !WLAN_RC_PHY_HT_VALID(valid, capflag) || ((pRateTable->info[j].dot11Rate == 15) && (valid & TRUE_20) && (capflag & WLAN_RC_WEP_TKIP_FLAG)) ) { continue; } if (!rcIsValidPhyRate(phy, capflag, FALSE)) continue; pPhyStateCtrl->validPhyRateIndex[phy][pPhyStateCtrl->validPhyRateCount[phy]] = j; pPhyStateCtrl->validPhyRateCount[phy] += 1; rcSetValidTxMask(pRc, j, TRUE); hi = A_MAX(hi, j); } } return hi; } /* * Update the SIB's rate control information * * This should be called when the supported rates change * (e.g. SME operation, wireless mode change) * * It will determine which rates are valid for use. */ static void rcSibUpdate_ht(struct ath_softc_tgt *sc, struct ath_node_target *an, A_UINT32 capflag, A_BOOL keepState, struct ieee80211_rate *pRateSet) { RATE_TABLE_11N *pRateTable = 0; struct atheros_node *pSib = ATH_NODE_ATHEROS(an); struct atheros_softc *asc = (struct atheros_softc*)sc->sc_rc; A_UINT8 *phtMcs = (A_UINT8*)&pRateSet->htrates; TX_RATE_CTRL *pRc = (TX_RATE_CTRL *)(pSib); PHY_STATE_CTRL mPhyCtrlState; A_UINT8 i, j, k, hi = 0, htHi = 0; pRateTable = (RATE_TABLE_11N*)asc->hwRateTable[sc->sc_curmode]; /* Initial rate table size. Will change depending on the working rate set */ pRc->rateTableSize = MAX_TX_RATE_TBL; /* Initialize thresholds according to the global rate table */ for (i = 0 ; (i < pRc->rateTableSize) && (!keepState); i++) { pRc->state[i].per = 0; } /* Determine the valid rates */ rcInitValidTxMask(pRc); for (i = 0; i < WLAN_RC_PHY_MAX; i++) { for (j = 0; j < MAX_TX_RATE_TBL; j++) { mPhyCtrlState.validPhyRateIndex[i][j] = 0; } mPhyCtrlState.validPhyRateCount[i] = 0; } pRc->rcPhyMode = (capflag & WLAN_RC_40_FLAG); if (pRateSet == NULL || !pRateSet->rates.rs_nrates) { /* No working rate, just initialize valid rates */ hi = rcSibInitValidRates(pRateTable, pRc, capflag, &mPhyCtrlState); } else { /* Use intersection of working rates and valid rates */ hi = rcSibSetValidRates(pRateTable, pRc, &(pRateSet->rates), capflag, an, &mPhyCtrlState); if (capflag & WLAN_RC_HT_FLAG) { htHi = rcSibSetValidHtRates(pRateTable, pRc, phtMcs, capflag, an, &mPhyCtrlState); } hi = A_MAX(hi, htHi); } pRc->rateTableSize = hi + 1; pRc->rateMaxPhy = 0; ASSERT(pRc->rateTableSize <= MAX_TX_RATE_TBL); for (i = 0, k = 0; i < WLAN_RC_PHY_MAX; i++) { for (j = 0; j < mPhyCtrlState.validPhyRateCount[i]; j++) { pRc->validRateIndex[k++] = mPhyCtrlState.validPhyRateIndex[i][j]; } if (!rcIsValidPhyRate(i, pRateTable->initialRateMax, TRUE) || !mPhyCtrlState.validPhyRateCount[i]) continue; pRc->rateMaxPhy = mPhyCtrlState.validPhyRateIndex[i][j-1]; } ASSERT(pRc->rateTableSize <= MAX_TX_RATE_TBL); ASSERT(k <= MAX_TX_RATE_TBL); pRc->rateMaxPhy = pRc->validRateIndex[k-4]; pRc->maxValidRate = k; rcSortValidRates(pRateTable, pRc); } static A_UINT8 rcRateFind_ht(struct ath_softc_tgt *sc, struct atheros_node *pSib, const RATE_TABLE_11N *pRateTable, A_BOOL probeAllowed, A_BOOL *isProbing) { A_UINT32 bestThruput, thisThruput; A_UINT32 nowMsec; A_UINT8 rate, nextRate, bestRate; A_UINT8 maxIndex, minIndex; A_INT8 index; TX_RATE_CTRL *pRc = NULL; pRc = (TX_RATE_CTRL *)(pSib ? (pSib) : NULL); *isProbing = FALSE; /* * Age (reduce) last ack rssi based on how old it is. * The bizarre numbers are so the delta is 160msec, * meaning we divide by 16. * 0msec <= dt <= 25msec: don't derate * 25msec <= dt <= 185msec: derate linearly from 0 to 10dB * 185msec <= dt: derate by 10dB */ nowMsec = A_MS_TICKGET(); /* * Now look up the rate in the rssi table and return it. * If no rates match then we return 0 (lowest rate) */ bestThruput = 0; maxIndex = pRc->maxValidRate-1; minIndex = 0; bestRate = minIndex; /* * Try the higher rate first. It will reduce memory moving time * if we have very good channel characteristics. */ for (index = maxIndex; index >= minIndex ; index--) { A_UINT8 perThres; rate = pRc->validRateIndex[index]; if (rate > pRc->rateMaxPhy) { continue; } /* if the best throughput is already larger than the userRateKbps.. * then we could skip of rest of calculation.. */ if( bestThruput >= pRateTable->info[rate].userRateKbps) break; /* * For TCP the average collision rate is around 11%, * so we ignore PERs less than this. This is to * prevent the rate we are currently using (whose * PER might be in the 10-15 range because of TCP * collisions) looking worse than the next lower * rate whose PER has decayed close to 0. If we * used to next lower rate, its PER would grow to * 10-15 and we would be worse off then staying * at the current rate. */ perThres = pRc->state[rate].per; if ( perThres < 12 ) { perThres = 12; } thisThruput = pRateTable->info[rate].userRateKbps * (100 - perThres); if (bestThruput <= thisThruput) { bestThruput = thisThruput; bestRate = rate; } } rate = bestRate; /* * Must check the actual rate (rateKbps) to account for non-monoticity of * 11g's rate table */ if (rate >= pRc->rateMaxPhy && probeAllowed) { rate = pRc->rateMaxPhy; /* Probe the next allowed phy state */ /* FIXME: Check to make sure ratMax is checked properly */ if (rcGetNextValidTxRate( pRateTable, pRc, rate, &nextRate) && (nowMsec - pRc->probeTime > pRateTable->probeInterval) && (pRc->hwMaxRetryPktCnt >= 1)) { rate = nextRate; pRc->probeRate = rate; pRc->probeTime = nowMsec; pRc->hwMaxRetryPktCnt = 0; *isProbing = TRUE; } } /* * Make sure rate is not higher than the allowed maximum. * We should also enforce the min, but I suspect the min is * normally 1 rather than 0 because of the rate 9 vs 6 issue * in the old code. */ if (rate > (pRc->rateTableSize - 1)) { rate = pRc->rateTableSize - 1; } /* record selected rate, which is used to decide if we want to do fast frame */ if (!(*isProbing) && pSib) { pSib->lastRateKbps = pRateTable->info[rate].rateKbps; ((struct atheros_softc*)sc->sc_rc)->currentTxRateKbps = pSib->lastRateKbps; ((struct atheros_softc*)sc->sc_rc)->currentTxRateIndex = rate; } return rate; } static void rcRateSetseries(const RATE_TABLE_11N *pRateTable , struct ath_rc_series *series, A_UINT8 tries, A_UINT8 rix, A_BOOL rtsctsenable, A_UINT32 chainmask,int stbc) { series->tries = tries; series->flags = (rtsctsenable? ATH_RC_RTSCTS_FLAG : 0) | (WLAN_RC_PHY_DS(pRateTable->info[rix].phy) ? ATH_RC_DS_FLAG : 0) | (WLAN_RC_PHY_40(pRateTable->info[rix].phy) ? ATH_RC_CW40_FLAG : 0) | (WLAN_RC_PHY_SGI(pRateTable->info[rix].phy) ? ATH_RC_HT40_SGI_FLAG : 0); #ifdef MAGPIE_MERLIN if (stbc) { /* For now, only single stream STBC is supported */ if (pRateTable->info[rix].rateCode >= 0x80 && pRateTable->info[rix].rateCode <= 0x87) { series->flags |= ATH_RC_TX_STBC_FLAG; } } #endif series->rix = pRateTable->info[rix].baseIndex; series->max4msframelen = pRateTable->info[rix].max4msframelen; series->txrateKbps = pRateTable->info[rix].rateKbps; /* If the hardware is capable of multiple transmit chains (chainmask is 3, 5 or 7), * then choose the number of transmit chains dynamically based on entries in the rate table. */ #ifndef ATH_ENABLE_WLAN_FOR_K2 if(chainmask == 7) series->tx_chainmask = pRateTable->info[rix].txChainMask_3ch; else if(chainmask == 1) series->tx_chainmask = 1; else series->tx_chainmask = pRateTable->info[rix].txChainMask_2ch; /*Chainmask is 3 or 5*/ #else series->tx_chainmask = 1; #endif } static A_UINT8 rcRateGetIndex(struct ath_softc_tgt *sc, struct ath_node_target *an, const RATE_TABLE_11N *pRateTable , A_UINT8 rix, A_UINT16 stepDown, A_UINT16 minRate) { A_UINT32 j; A_UINT8 nextIndex; struct atheros_node *pSib = ATH_NODE_ATHEROS(an); TX_RATE_CTRL *pRc = (TX_RATE_CTRL *)(pSib); if (minRate) { for (j = RATE_TABLE_11N_SIZE; j > 0; j-- ) { if (rcGetNextLowerValidTxRate(pRateTable, pRc, rix, &nextIndex)) { rix = nextIndex; } else { break; } } } else { for (j = stepDown; j > 0; j-- ) { if (rcGetNextLowerValidTxRate(pRateTable, pRc, rix, &nextIndex)) { rix = nextIndex; } else { break; } } } return rix; } void rcRateFind_11n(struct ath_softc_tgt *sc, struct ath_node_target *an, int numTries, int numRates, int stepDnInc, unsigned int rcflag, struct ath_rc_series series[], int *isProbe) { A_UINT8 i = 0; A_UINT8 tryPerRate = 0; struct atheros_softc *asc = (struct atheros_softc*)sc->sc_rc; RATE_TABLE_11N *pRateTable = (RATE_TABLE_11N *)asc->hwRateTable[sc->sc_curmode]; struct atheros_node *asn = ATH_NODE_ATHEROS(an); A_UINT8 rix, nrix; A_UINT8 dot11Rate; WLAN_PHY phy; rix = rcRateFind_ht(sc, asn, pRateTable, (rcflag & ATH_RC_PROBE_ALLOWED) ? 1 : 0, isProbe); nrix = rix; if ((rcflag & ATH_RC_PROBE_ALLOWED) && (*isProbe)) { /* set one try for probe rates. For the probes don't enable rts */ rcRateSetseries(pRateTable, &series[i++], 1, nrix, FALSE, asc->tx_chainmask, asn->stbc); /* * Get the next tried/allowed rate. No RTS for the next series * after the probe rate */ nrix = rcRateGetIndex( sc, an, pRateTable, nrix, 1, FALSE); } tryPerRate = (numTries/numRates); /* Set the choosen rate. No RTS for first series entry. */ rcRateSetseries(pRateTable, &series[i++], tryPerRate, nrix, FALSE, asc->tx_chainmask, asn->stbc); /* Fill in the other rates for multirate retry */ for (; i < numRates; i++) { A_UINT8 tryNum; A_UINT8 minRate; tryNum = ((i + 1) == numRates) ? numTries - (tryPerRate * i) : tryPerRate ; minRate = (((i + 1) == numRates) && (rcflag & ATH_RC_MINRATE_LASTRATE)) ? 1 : 0; nrix = rcRateGetIndex(sc, an, pRateTable, nrix, stepDnInc, minRate); /* All other rates in the series have RTS enabled */ rcRateSetseries(pRateTable, &series[i], tryNum, nrix, TRUE, asc->tx_chainmask, asn->stbc); } /* * BUG 26545: * Change rate series to enable aggregation when operating at lower MCS rates. * When first rate in series is MCS2 in HT40 @ 2.4GHz, series should look like: * {MCS2, MCS1, MCS0, MCS0}. * When first rate in series is MCS3 in HT20 @ 2.4GHz, series should look like: * {MCS3, MCS2, MCS1, MCS1} * So, set fourth rate in series to be same as third one for above conditions. */ if (sc->sc_curmode == IEEE80211_MODE_11NG) { dot11Rate = pRateTable->info[rix].dot11Rate; phy = pRateTable->info[rix].phy; if (i == 4 && ((dot11Rate == 2 && phy == WLAN_RC_PHY_HT_40_SS) || (dot11Rate == 3 && phy == WLAN_RC_PHY_HT_20_SS))) { series[3].rix = series[2].rix; series[3].flags = series[2].flags; series[3].max4msframelen = series[2].max4msframelen; } } /* * 2009/02/06 * AP91 Kite: NetGear OTA location-4 downlink. * Enable RTS/CTS at MCS 3-0 for downlink throughput. */ if (sc->sc_curmode == IEEE80211_MODE_11NG) { dot11Rate = pRateTable->info[rix].dot11Rate; if (dot11Rate <= 3 ) { series[0].flags |= ATH_RC_RTSCTS_FLAG; } } } static void rcUpdate_ht(struct ath_softc_tgt *sc, struct ath_node_target *an, int txRate, A_BOOL Xretries, int retries, A_UINT8 curTxAnt, A_UINT16 nFrames, A_UINT16 nBad) { TX_RATE_CTRL *pRc; A_UINT32 nowMsec = A_MS_TICKGET(); A_UINT8 lastPer; int rate,count; struct atheros_node *pSib = ATH_NODE_ATHEROS(an); struct atheros_softc *asc = (struct atheros_softc*)sc->sc_rc; RATE_TABLE_11N *pRateTable = (RATE_TABLE_11N *)asc->hwRateTable[sc->sc_curmode]; static A_UINT32 nRetry2PerLookup[10] = { 100 * 0 / 1, // 0 100 * 1 / 4, // 25 100 * 1 / 2, // 50 100 * 3 / 4, // 75 100 * 4 / 5, // 80 100 * 5 / 6, // 83.3 100 * 6 / 7, // 85.7 100 * 7 / 8, // 87.5 100 * 8 / 9, // 88.8 100 * 9 / 10 // 90 }; if (!pSib) return; pRc = (TX_RATE_CTRL *)(pSib); ASSERT(retries >= 0 && retries < MAX_TX_RETRIES); ASSERT(txRate >= 0); if (txRate < 0) { return; } lastPer = pRc->state[txRate].per; if (Xretries) { /* Update the PER. */ if (Xretries == 1) { pRc->state[txRate].per += 30; if (pRc->state[txRate].per > 100) { pRc->state[txRate].per = 100; } } else { /* Xretries == 2 */ count = sizeof(nRetry2PerLookup) / sizeof(nRetry2PerLookup[0]); if (retries >= count) { retries = count - 1; } /* new_PER = 7/8*old_PER + 1/8*(currentPER) */ pRc->state[txRate].per = (A_UINT8)(pRc->state[txRate].per - (pRc->state[txRate].per / 8) + ((100) / 8)); } /* Xretries == 1 or 2 */ if (pRc->probeRate == txRate) pRc->probeRate = 0; } else { /* Xretries == 0 */ /* * Update the PER. Make sure it doesn't index out of array's bounds. */ count = sizeof(nRetry2PerLookup) / sizeof(nRetry2PerLookup[0]); if (retries >= count) { retries = count - 1; } if (nBad) { /* new_PER = 7/8*old_PER + 1/8*(currentPER) */ /* * Assuming that nFrames is not 0. The current PER * from the retries is 100 * retries / (retries+1), * since the first retries attempts failed, and the * next one worked. For the one that worked, nBad * subframes out of nFrames wored, so the PER for * that part is 100 * nBad / nFrames, and it contributes * 100 * nBad / (nFrames * (retries+1)) to the above * PER. The expression below is a simplified version * of the sum of these two terms. */ if (nFrames > 0) pRc->state[txRate].per = (A_UINT8)(pRc->state[txRate].per - (pRc->state[txRate].per / 8) + ((100*(retries*nFrames + nBad)/(nFrames*(retries+1))) / 8)); } else { /* new_PER = 7/8*old_PER + 1/8*(currentPER) */ pRc->state[txRate].per = (A_UINT8)(pRc->state[txRate].per - (pRc->state[txRate].per / 8) + (nRetry2PerLookup[retries] / 8)); } /* * If we got at most one retry then increase the max rate if * this was a probe. Otherwise, ignore the probe. */ if (pRc->probeRate && pRc->probeRate == txRate) { if (retries > 0 || 2 * nBad > nFrames) { /* * Since we probed with just a single attempt, * any retries means the probe failed. Also, * if the attempt worked, but more than half * the subframes were bad then also consider * the probe a failure. */ pRc->probeRate = 0; } else { pRc->rateMaxPhy = pRc->probeRate; if (pRc->state[pRc->probeRate].per > 30) { pRc->state[pRc->probeRate].per = 20; } pRc->probeRate = 0; /* * Since this probe succeeded, we allow the next probe * twice as soon. This allows the maxRate to move up * faster if the probes are succesful. */ pRc->probeTime = nowMsec - pRateTable->probeInterval / 2; } } if (retries > 0) { /* * Don't update anything. We don't know if this was because * of collisions or poor signal. * * Later: if rssiAck is close to pRc->state[txRate].rssiThres * and we see lots of retries, then we could increase * pRc->state[txRate].rssiThres. */ pRc->hwMaxRetryPktCnt = 0; } else { /* * It worked with no retries. First ignore bogus (small) * rssiAck values. */ if (txRate == pRc->rateMaxPhy && pRc->hwMaxRetryPktCnt < 255) { pRc->hwMaxRetryPktCnt++; } } } /* For all cases */ ASSERT((pRc->rateMaxPhy >= 0 && pRc->rateMaxPhy <= pRc->rateTableSize && pRc->rateMaxPhy != INVALID_RATE_MAX)); /* * If this rate looks bad (high PER) then stop using it for * a while (except if we are probing). */ if (pRc->state[txRate].per >= 55 && txRate > 0 && pRateTable->info[txRate].rateKbps <= pRateTable->info[pRc->rateMaxPhy].rateKbps) { rcGetNextLowerValidTxRate(pRateTable, pRc, (A_UINT8) txRate, &pRc->rateMaxPhy); /* Don't probe for a little while. */ pRc->probeTime = nowMsec; } /* Make sure the rates below this have lower PER */ /* Monotonicity is kept only for rates below the current rate. */ if (pRc->state[txRate].per < lastPer) { for (rate = txRate - 1; rate >= 0; rate--) { if (pRateTable->info[rate].phy != pRateTable->info[txRate].phy) { break; } if (pRc->state[rate].per > pRc->state[rate+1].per) { pRc->state[rate].per = pRc->state[rate+1].per; } } } /* Maintain monotonicity for rates above the current rate*/ for (rate = txRate; rate < pRc->rateTableSize - 1; rate++) { if (pRc->state[rate+1].per < pRc->state[rate].per) { pRc->state[rate+1].per = pRc->state[rate].per; } } /* Every so often, we reduce the thresholds and PER (different for CCK and OFDM). */ if (nowMsec - pRc->perDownTime >= pRateTable->rssiReduceInterval) { for (rate = 0; rate < pRc->rateTableSize; rate++) { pRc->state[rate].per = 7*pRc->state[rate].per/8; } pRc->perDownTime = nowMsec; } } /* * This routine is called by the Tx interrupt service routine to give * the status of previous frames. */ void rcUpdate_11n(struct ath_softc_tgt *sc, struct ath_node_target *an, A_UINT8 curTxAnt, int finalTSIdx, int Xretries, struct ath_rc_series rcs[], int nFrames, int nBad, int long_retry) { A_UINT32 series = 0; A_UINT32 rix; struct atheros_softc *asc = (struct atheros_softc*)sc->sc_rc; RATE_TABLE_11N *pRateTable = (RATE_TABLE_11N *)asc->hwRateTable[sc->sc_curmode]; struct atheros_node *pSib = ATH_NODE_ATHEROS(an); TX_RATE_CTRL *pRc = (TX_RATE_CTRL *)(pSib); A_UINT8 flags; if (!an) { adf_os_assert(0); return; } ASSERT (rcs[0].tries != 0); /* * If the first rate is not the final index, there are intermediate rate failures * to be processed. */ if (finalTSIdx != 0) { /* Process intermediate rates that failed.*/ for (series = 0; series < finalTSIdx ; series++) { if (rcs[series].tries != 0) { flags = rcs[series].flags; /* If HT40 and we have switched mode from 40 to 20 => don't update */ if ((flags & ATH_RC_CW40_FLAG) && (pRc->rcPhyMode != (flags & ATH_RC_CW40_FLAG))) { return; } if ((flags & ATH_RC_CW40_FLAG) && (flags & ATH_RC_HT40_SGI_FLAG)) { rix = pRateTable->info[rcs[series].rix].htIndex; } else if (flags & ATH_RC_HT40_SGI_FLAG) { rix = pRateTable->info[rcs[series].rix].sgiIndex; } else if (flags & ATH_RC_CW40_FLAG) { rix = pRateTable->info[rcs[series].rix].cw40Index; } else { rix = pRateTable->info[rcs[series].rix].baseIndex; } /* FIXME:XXXX, too many args! */ rcUpdate_ht(sc, an, rix, Xretries? 1 : 2, rcs[series].tries, curTxAnt, nFrames, nFrames); } } } else { /* * Handle the special case of MIMO PS burst, where the second aggregate is sent * out with only one rate and one try. Treating it as an excessive retry penalizes * the rate inordinately. */ if (rcs[0].tries == 1 && Xretries == 1) { Xretries = 2; } } flags = rcs[series].flags; /* If HT40 and we have switched mode from 40 to 20 => don't update */ if ((flags & ATH_RC_CW40_FLAG) && (pRc->rcPhyMode != (flags & ATH_RC_CW40_FLAG))) { return; } if ((flags & ATH_RC_CW40_FLAG) && (flags & ATH_RC_HT40_SGI_FLAG)) { rix = pRateTable->info[rcs[series].rix].htIndex; } else if (flags & ATH_RC_HT40_SGI_FLAG) { rix = pRateTable->info[rcs[series].rix].sgiIndex; } else if (flags & ATH_RC_CW40_FLAG) { rix = pRateTable->info[rcs[series].rix].cw40Index; } else { rix = pRateTable->info[rcs[series].rix].baseIndex; } /* FIXME:XXXX, too many args! */ rcUpdate_ht(sc, an, rix, Xretries, long_retry, curTxAnt, nFrames, nBad); } void ath_tx_status_update_rate(struct ath_softc_tgt *sc, struct ath_rc_series rcs[], int series, WMI_TXSTATUS_EVENT *txs) { struct atheros_softc *asc = (struct atheros_softc*)sc->sc_rc; RATE_TABLE_11N *pRateTable = (RATE_TABLE_11N *)asc->hwRateTable[sc->sc_curmode]; /* HT Rate */ if (pRateTable->info[rcs[series].rix].rateCode & 0x80) { txs->txstatus[txs->cnt].ts_rate |= SM(pRateTable->info[rcs[series].rix].dot11Rate, ATH9K_HTC_TXSTAT_RATE); txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_MCS; if (rcs[series].flags & ATH_RC_CW40_FLAG) txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_CW40; if (rcs[series].flags & ATH_RC_HT40_SGI_FLAG) txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_SGI; } else { txs->txstatus[txs->cnt].ts_rate |= SM(rcs[series].rix, ATH9K_HTC_TXSTAT_RATE); } if (rcs[series].flags & ATH_RC_RTSCTS_FLAG) txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_RTC_CTS; } struct ath_ratectrl * ath_rate_attach(struct ath_softc_tgt *sc) { struct atheros_softc *asc; asc = adf_os_mem_alloc(sizeof(struct atheros_softc)); if (asc == NULL) return NULL; adf_os_mem_set(asc, 0, sizeof(struct atheros_softc)); asc->arc.arc_space = sizeof(struct atheros_node); ar5416AttachRateTables(asc); asc->tx_chainmask = 1; return &asc->arc; } void ath_rate_findrate(struct ath_softc_tgt *sc, struct ath_node_target *an, int shortPreamble, size_t frameLen, int numTries, int numRates, int stepDnInc, unsigned int rcflag, struct ath_rc_series series[], int *isProbe) { *isProbe = 0; if (!numRates || !numTries) { return; } ath_rate_findrate_11n(sc, an, frameLen, numTries, numRates, stepDnInc, rcflag, series, isProbe); } #define MS(_v, _f) (((_v) & _f) >> _f##_S) void ath_rate_tx_complete(struct ath_softc_tgt *sc, struct ath_node_target *an, struct ath_tx_desc *ds, struct ath_rc_series rcs[], int nframes, int nbad) { ath_rate_tx_complete_11n(sc, an, ds, rcs, nframes, nbad); } void ath_rate_newassoc(struct ath_softc_tgt *sc, struct ath_node_target *an, int isnew, unsigned int capflag, struct ieee80211_rate *rs) { ath_rate_newassoc_11n(sc, an, isnew, capflag, rs); } void ath_rate_node_update(struct ath_softc_tgt *sc, struct ath_node_target *an, a_int32_t isnew, a_uint32_t capflag, struct ieee80211_rate *rs) { struct ieee80211_node_target *ni = &an->ni; ath_rate_newassoc(sc, ATH_NODE_TARGET(ni), isnew, capflag, rs); } static int init_ath_rate_atheros(void); static void exit_ath_rate_atheros(void); void ath_rate_newstate(struct ath_softc_tgt *sc, struct ieee80211vap_target *vap, enum ieee80211_state state, a_uint32_t capflag, struct ieee80211_rate *rs) { struct ieee80211_node_target *ni = vap->iv_bss; struct atheros_softc *asc = (struct atheros_softc *) sc->sc_rc; asc->tx_chainmask = sc->sc_ic.ic_tx_chainmask; ath_rate_newassoc(sc, ATH_NODE_TARGET(ni), 1, capflag, rs); } static void ath_rate_findrate_11n(struct ath_softc_tgt *sc, struct ath_node_target *an, size_t frameLen, int numTries, int numRates, int stepDnInc, unsigned int rcflag, struct ath_rc_series series[], int *isProbe) { *isProbe = 0; if (!numRates || !numTries) { return; } rcRateFind_11n(sc, an, numTries, numRates, stepDnInc, rcflag, series, isProbe); } static void ath_rate_tx_complete_11n(struct ath_softc_tgt *sc, struct ath_node_target *an, struct ath_tx_desc *ds, struct ath_rc_series rcs[], int nframes, int nbad) { int finalTSIdx = ds->ds_txstat.ts_rate; int tx_status = 0; if ((ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) || (ds->ds_txstat.ts_status & HAL_TXERR_FIFO) || (ds->ds_txstat.ts_flags & HAL_TX_DATA_UNDERRUN) || (ds->ds_txstat.ts_flags & HAL_TX_DELIM_UNDERRUN)) { tx_status = 1; } rcUpdate_11n(sc, an, ds->ds_txstat.ts_antenna, finalTSIdx, tx_status, rcs, nframes , nbad, ds->ds_txstat.ts_longretry); } static void ath_rate_newassoc_11n(struct ath_softc_tgt *sc, struct ath_node_target *an, int isnew, unsigned int capflag, struct ieee80211_rate *rs) { if (isnew) { #ifdef MAGPIE_MERLIN struct atheros_node *oan = ATH_NODE_ATHEROS(an); /* Only MERLIN can send STBC */ oan->stbc = (capflag & ATH_RC_TX_STBC_FLAG) ? 1 : 0; #endif rcSibUpdate_ht(sc, an, capflag, 0, rs); } }