pax_global_header 0000666 0000000 0000000 00000000064 14735055600 0014517 g ustar 00root root 0000000 0000000 52 comment=650c387aaef3c7d0173e9e03faec1f36050dd976
openFPGALoader-0.13.1/ 0000775 0000000 0000000 00000000000 14735055600 0014327 5 ustar 00root root 0000000 0000000 openFPGALoader-0.13.1/.btd.yml 0000664 0000000 0000000 00000000243 14735055600 0015700 0 ustar 00root root 0000000 0000000 input: doc
output: _build
requirements: requirements.txt
target: gh-pages
formats: [ html ]
theme: https://codeload.github.com/buildthedocs/sphinx.theme/tar.gz/v1
openFPGALoader-0.13.1/.github/ 0000775 0000000 0000000 00000000000 14735055600 0015667 5 ustar 00root root 0000000 0000000 openFPGALoader-0.13.1/.github/workflows/ 0000775 0000000 0000000 00000000000 14735055600 0017724 5 ustar 00root root 0000000 0000000 openFPGALoader-0.13.1/.github/workflows/Test.yml 0000664 0000000 0000000 00000011363 14735055600 0021372 0 ustar 00root root 0000000 0000000 name: Test
on:
push:
pull_request:
workflow_dispatch:
jobs:
doc:
runs-on: ubuntu-latest
name: '๐ Docs'
steps:
- name: '๐งฐ Checkout'
uses: actions/checkout@v4
- name: '๐ BuildTheDocs (BTD)'
uses: buildthedocs/btd@v0
with:
token: ${{ github.token }}
skip-deploy: ${{ github.event_name == 'pull_request' }}
- name: '๐งน Clean HTML build'
if: ${{ github.event_name != 'pull_request' }}
run: sudo rm -rf doc/_build/html/.git
- name: '๐ค Upload artifact: HTML'
uses: actions/upload-artifact@v4
with:
name: openFPGALoader-Documentation
path: doc/_build/html
lin-build:
strategy:
fail-fast: false
matrix:
os:
- 20
- 22
name: '๐ง๐ง Ubuntu ${{ matrix.os }} | build'
runs-on: ubuntu-${{ matrix.os }}.04
steps:
- name: '๐งฐ Checkout'
uses: actions/checkout@v4
- name: 'โ๏ธ Install dependencies'
run: |
sudo apt update -qq
sudo apt install -y \
cmake \
gzip \
libftdi1-2 \
libftdi1-dev \
libhidapi-libusb0 \
libhidapi-dev \
libudev-dev \
pkg-config \
tree \
zlib1g-dev
- name: '๐ง Build tarball'
run: |
mkdir build
cd build
cmake ..
cmake --build .
make DESTDIR=$(pwd)/dist install
_rulesdir='dist/etc/udev/rules.d/'
mkdir -p "${_rulesdir}"
cp ../99-openfpgaloader.rules "${_rulesdir}"
_licenses="dist/usr/local/share/licenses/openFPGALoader"
mkdir -p "${_licenses}"
install -m 644 ../LICENSE "${_licenses}"
tar -cvzf ../ubtuntu${{ matrix.os }}.04-openFPGALoader.tgz -C dist .
- name: '๐ค Upload artifact: tarball'
uses: actions/upload-artifact@v4
with:
name: ubtuntu${{ matrix.os }}.04-openFPGALoader
path: ubtuntu${{ matrix.os }}.04-openFPGALoader.tgz
- name: '๐ Show package content'
run: |
mkdir tmp
cd tmp
tar -xf ../ubtuntu${{ matrix.os }}.04-openFPGALoader.tgz
tree .
mac-build:
strategy:
fail-fast: false
name: '๐ง๐ง macOS latest | build'
runs-on: macos-latest
steps:
- name: '๐งฐ Checkout'
uses: actions/checkout@v4
- name: 'โ๏ธ Install dependencies'
run: |
#brew update
brew install --only-dependencies openFPGALoader
- name: '๐ง Build tarball'
run: |
mkdir build
cd build
cmake ..
cmake --build .
lin-test:
needs: lin-build
strategy:
fail-fast: false
matrix:
os:
- 20
- 22
name: '๐ฆ๐ง Ubuntu ${{ matrix.os }} | test'
runs-on: ubuntu-${{ matrix.os }}.04
steps:
- name: 'โ๏ธ Install dependencies'
run: |
sudo apt update -qq
sudo apt install -y \
libftdi1-2 \
libhidapi-libusb0 \
udev \
zlib1g
- name: '๐ฅ Download artifact: package'
uses: actions/download-artifact@v4.1.7
with:
name: ubtuntu${{ matrix.os }}.04-openFPGALoader
- name: '๐ ๏ธ Install package'
run: sudo tar -xvzf *.tgz -C /
- name: '๐ฆ Test package'
run: |
openFPGALoader --help
openFPGALoader --detect || true
win-jobs:
name: โฌ Generate list of MSYS2 jobs
runs-on: ubuntu-latest
outputs:
jobs: ${{ steps.matrix.outputs.jobs }}
steps:
- id: matrix
uses: msys2/setup-msys2/matrix@main
with:
systems: >-
mingw64
ucrt64
clang64
win:
needs: win-jobs
uses: msys2/setup-msys2/.github/workflows/PKGBUILD.yml@main
with:
name: openFPGALoader
matrix: ${{ needs.win-jobs.outputs.jobs }}
path: scripts/msys2
test: |
uname -a
which openFPGALoader
openFPGALoader --help
openFPGALoader --detect || true
Release:
if: github.event_name != 'pull_request' && (github.ref == 'refs/heads/master' || contains(github.ref, 'refs/tags/'))
needs: [ lin-test, win ]
runs-on: ubuntu-latest
name: '๐ฆ Release'
steps:
- name: '๐ฅ Download artifacts'
uses: actions/download-artifact@v4.1.7
with:
path: artifact
- name: 'โ๏ธ Package Documentation'
run: |
cd artifact
tar cvzf openFPGALoader-Documentation.tar.gz openFPGALoader-Documentation
rm -rf openFPGALoader-Documentation
# Tagged: create a pre-release or a release (semver)
# Untagged: update the assets of pre-release 'nightly'
- uses: pyTooling/Actions/releaser@r0
with:
token: ${{ github.token }}
tag: 'nightly'
files: artifact/**/*
openFPGALoader-0.13.1/.gitignore 0000664 0000000 0000000 00000001010 14735055600 0016307 0 ustar 00root root 0000000 0000000 # Prerequisites
*.d
# Compiled Object files
*.slo
*.lo
*.o
*.obj
# Precompiled Headers
*.gch
*.pch
# Compiled Dynamic libraries
*.so
*.dylib
*.dll
# Fortran module files
*.mod
*.smod
# Compiled Static libraries
*.lai
*.la
*.a
*.lib
# Executables
*.exe
*.out
*.app
cycloader
openFPGALoader
*.swp
# Build directory
build/
# Documentation
/doc/__pycache__/
/doc/_build/
/doc/_theme/
/doc/compatibility/boards.inc
/doc/compatibility/cable.inc
/doc/compatibility/fpga.inc
# VSCode local settings directory
/.vscode/ openFPGALoader-0.13.1/99-openfpgaloader.rules 0000664 0000000 0000000 00000004703 14735055600 0020634 0 ustar 00root root 0000000 0000000 # Copy this file to /etc/udev/rules.d/
ACTION!="add|change", GOTO="openfpgaloader_rules_end"
# gpiochip subsystem
SUBSYSTEM=="gpio", MODE="0664", GROUP="plugdev", TAG+="uaccess"
SUBSYSTEM!="usb|tty|hidraw", GOTO="openfpgaloader_rules_end"
# Original FT232/FT245 VID:PID
ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6001", MODE="664", GROUP="plugdev", TAG+="uaccess"
# Original FT2232 VID:PID
ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6010", MODE="664", GROUP="plugdev", TAG+="uaccess"
# Original FT4232 VID:PID
ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6011", MODE="664", GROUP="plugdev", TAG+="uaccess"
# Original FT232H VID:PID
ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6014", MODE="664", GROUP="plugdev", TAG+="uaccess"
# Original FT231X VID:PID
ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6015", MODE="664", GROUP="plugdev", TAG+="uaccess"
# anlogic cable
ATTRS{idVendor}=="0547", ATTRS{idProduct}=="1002", MODE="664", GROUP="plugdev", TAG+="uaccess"
# altera usb-blaster
ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6001", MODE="664", GROUP="plugdev", TAG+="uaccess"
ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6002", MODE="664", GROUP="plugdev", TAG+="uaccess"
ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6003", MODE="664", GROUP="plugdev", TAG+="uaccess"
# altera usb-blasterII - uninitialized
ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6810", MODE="664", GROUP="plugdev", TAG+="uaccess"
# altera usb-blasterII - initialized
ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6010", MODE="664", GROUP="plugdev", TAG+="uaccess"
# dirtyJTAG
ATTRS{idVendor}=="1209", ATTRS{idProduct}=="c0ca", MODE="664", GROUP="plugdev", TAG+="uaccess"
# Jlink
ATTRS{idVendor}=="1366", ATTRS{idProduct}=="0105", MODE="664", GROUP="plugdev", TAG+="uaccess"
# NXP LPC-Link2
ATTRS{idVendor}=="1fc9", ATTRS{idProduct}=="0090", MODE="664", GROUP="plugdev", TAG+="uaccess"
# NXP ARM mbed
ATTRS{idVendor}=="0d28", ATTRS{idProduct}=="0204", MODE="664", GROUP="plugdev", TAG+="uaccess"
# icebreaker bitsy
ATTRS{idVendor}=="1d50", ATTRS{idProduct}=="6146", MODE="664", GROUP="plugdev", TAG+="uaccess"
# numato systems
ATTRS{idVendor}=="2a19", ATTRS{idProduct}=="1009", MODE="644", GROUP="plugdev", TAG+="uaccess"
# orbtrace-mini dfu
ATTRS{idVendor}=="1209", ATTRS{idProduct}=="3442", MODE="664", GROUP="plugdev", TAG+="uaccess"
# QinHeng Electronics USB To UART+JTAG (ch347)
ATTRS{idVendor}=="1a86", ATTRS{idProduct}=="55dd", MODE="664", GROUP="plugdev", TAG+="uaccess"
LABEL="openfpgaloader_rules_end"
openFPGALoader-0.13.1/CMakeLists.txt 0000664 0000000 0000000 00000024275 14735055600 0017101 0 ustar 00root root 0000000 0000000 cmake_minimum_required(VERSION 3.5)
# set the project name
project(openFPGALoader VERSION "0.13.1" LANGUAGES CXX)
add_definitions(-DVERSION=\"v${PROJECT_VERSION}\")
option(ENABLE_OPTIM "Enable build with -O3 optimization level" ON)
option(BUILD_STATIC "Whether or not to build with static libraries" OFF)
if (${CMAKE_SYSTEM_NAME} MATCHES "Windows")
set(ENABLE_UDEV OFF)
else()
option(ENABLE_UDEV "use udev to search JTAG adapter from /dev/xx" ON)
endif()
option(ENABLE_CMSISDAP "enable cmsis DAP interface (requires hidapi)" ON)
option(ENABLE_GOWIN_GWU2X "enable Gowin GWU2X interface" ON)
if (${CMAKE_SYSTEM_NAME} MATCHES "Linux")
option(ENABLE_LIBGPIOD "enable libgpiod bitbang driver (requires libgpiod)" ON)
option(ENABLE_REMOTEBITBANG "enable remote bitbang driver" ON)
else()
set(ENABLE_LIBGPIOD OFF)
set(ENABLE_REMOTEBITBANG OFF)
endif()
option(USE_PKGCONFIG "Use pkgconfig to find libraries" ON)
option(LINK_CMAKE_THREADS "Use CMake find_package to link the threading library" OFF)
set(BLASTERII_PATH "" CACHE STRING "usbBlasterII firmware directory")
set(ISE_PATH "/opt/Xilinx/14.7" CACHE STRING "ise root directory (default: /opt/Xilinx/14.7)")
## specify the C++ standard
set(CMAKE_CXX_STANDARD 11)
set(CMAKE_CXX_STANDARD_REQUIRED True)
set(CMAKE_CXX_FLAGS_DEBUG "-g -Wall -Wextra ${CMAKE_CXX_FLAGS_DEBUG}")
if (ENABLE_OPTIM)
set(CMAKE_CXX_FLAGS "-O3 ${CMAKE_CXX_FLAGS}")
endif()
if (BUILD_STATIC)
set(CMAKE_EXE_LINKER_FLAGS "-static-libstdc++ -static ${CMAKE_EXE_LINKER_FLAGS}")
set(BUILD_SHARED_LIBS OFF)
endif()
include(GNUInstallDirs)
# By default: DATA_DIR="/usr/local/share"
add_definitions(-DDATA_DIR=\"${CMAKE_INSTALL_FULL_DATAROOTDIR}\")
add_definitions(-DISE_DIR=\"${ISE_PATH}\")
add_definitions(-DBLASTERII_DIR=\"${BLASTERII_PATH}\")
if (USE_PKGCONFIG)
find_package(PkgConfig REQUIRED)
pkg_check_modules(LIBFTDI REQUIRED libftdi1)
pkg_check_modules(LIBUSB REQUIRED libusb-1.0)
pkg_check_modules(HIDAPI hidapi-libusb)
# if libusb not found try with hidraw
if (NOT HIDAPI_FOUND)
pkg_check_modules(HIDAPI hidapi-hidraw)
endif()
if (NOT HIDAPI_FOUND)
pkg_check_modules(HIDAPI hidapi)
endif()
# zlib support (gzip)
pkg_check_modules(ZLIB zlib)
if (NOT ZLIB_FOUND)
# try zlib-ng
pkg_check_modules(ZLIB zlib-ng)
if (ZLIB_FOUND)
add_definitions(-DHAS_ZLIBNG)
else()
message(FATAL_ERROR "Could find ZLIB")
endif()
endif(NOT ZLIB_FOUND)
if (ENABLE_UDEV)
pkg_check_modules(LIBUDEV libudev)
if (LIBUDEV_FOUND)
add_definitions(-DUSE_UDEV)
else()
message("libudev not found, disabling udev support and -D parameter")
set(ENABLE_UDEV OFF)
endif()
endif()
if (ENABLE_LIBGPIOD)
pkg_check_modules(LIBGPIOD libgpiod)
if (NOT LIBGPIOD_FOUND)
message("libgpiod not found, disabling gpiod support")
set(ENABLE_LIBGPIOD OFF)
endif()
endif()
endif()
set(OPENFPGALOADER_SOURCE
src/anlogic.cpp
src/anlogicBitParser.cpp
src/anlogicCable.cpp
src/ch552_jtag.cpp
src/common.cpp
src/dfu.cpp
src/dfuFileParser.cpp
src/dirtyJtag.cpp
src/ch347jtag.cpp
src/efinix.cpp
src/efinixHexParser.cpp
src/fx2_ll.cpp
src/ice40.cpp
src/ihexParser.cpp
src/pofParser.cpp
src/rawParser.cpp
src/spiFlash.cpp
src/spiInterface.cpp
src/usbBlaster.cpp
src/epcq.cpp
src/svf_jtag.cpp
src/jedParser.cpp
src/feaparser.cpp
src/display.cpp
src/jtag.cpp
src/ftdiJtagBitbang.cpp
src/ftdiJtagMPSSE.cpp
src/configBitstreamParser.cpp
src/ftdipp_mpsse.cpp
src/main.cpp
src/latticeBitParser.cpp
src/libusb_ll.cpp
src/gowin.cpp
src/device.cpp
src/jlink.cpp
src/lattice.cpp
src/progressBar.cpp
src/fsparser.cpp
src/mcsParser.cpp
src/ftdispi.cpp
src/altera.cpp
src/bitparser.cpp
src/xilinx.cpp
src/xilinxMapParser.cpp
src/colognechip.cpp
src/colognechipCfgParser.cpp
)
set(OPENFPGALOADER_HEADERS
src/altera.hpp
src/anlogic.hpp
src/anlogicBitParser.hpp
src/anlogicCable.hpp
src/ch552_jtag.hpp
src/common.hpp
src/cxxopts.hpp
src/dfu.hpp
src/dfuFileParser.hpp
src/dirtyJtag.hpp
src/ch347jtag.hpp
src/efinix.hpp
src/efinixHexParser.hpp
src/fx2_ll.hpp
src/ice40.hpp
src/ihexParser.hpp
src/pofParser.hpp
src/progressBar.hpp
src/rawParser.hpp
src/usbBlaster.hpp
src/bitparser.hpp
src/ftdiJtagBitbang.hpp
src/ftdiJtagMPSSE.hpp
src/jlink.hpp
src/jtag.hpp
src/jtagInterface.hpp
src/libusb_ll.hpp
src/fsparser.hpp
src/part.hpp
src/board.hpp
src/jedParser.hpp
src/feaparser.hpp
src/display.hpp
src/mcsParser.hpp
src/ftdipp_mpsse.hpp
src/spiFlash.hpp
src/spiFlashdb.hpp
src/epcq.hpp
src/spiInterface.hpp
src/svf_jtag.hpp
src/configBitstreamParser.hpp
src/device.hpp
src/gowin.hpp
src/cable.hpp
src/ftdispi.hpp
src/lattice.hpp
src/latticeBitParser.hpp
src/xilinx.hpp
src/xilinxMapParser.hpp
src/colognechip.hpp
src/colognechipCfgParser.hpp
)
link_directories(
${LIBUSB_LIBRARY_DIRS}
${LIBFTDI_LIBRARY_DIRS}
)
if (ENABLE_LIBGPIOD)
link_directories(${LIBGPIOD_LIBRARY_DIRS})
endif()
if (ENABLE_CMSISDAP AND HIDAPI_FOUND)
link_directories(${HIDAPI_LIBRARY_DIRS})
endif()
add_executable(openFPGALoader
${OPENFPGALOADER_SOURCE}
${OPENFPGALOADER_HEADERS}
)
include_directories(
${LIBUSB_INCLUDE_DIRS}
${LIBFTDI_INCLUDE_DIRS}
)
target_link_libraries(openFPGALoader
${LIBUSB_LIBRARIES}
${LIBFTDI_LIBRARIES}
)
# Gowin GWU2X JTAG interface
if(ENABLE_GOWIN_GWU2X)
target_sources(openFPGALoader PRIVATE src/gwu2x_jtag.cpp)
list (APPEND OPENFPGALOADER_HEADERS src/gwu2x_jtag.hpp)
add_definitions(-DENABLE_GOWIN_GWU2X=1)
message("Gowin GWU2X support enabled")
else()
message("Gowin GWU2X support disabled")
endif()
if (${CMAKE_SYSTEM_NAME} MATCHES "Windows")
# winsock provides ntohs
target_link_libraries(openFPGALoader ws2_32)
target_sources(openFPGALoader PRIVATE src/pathHelper.cpp)
list(APPEND OPENFPGALOADER_HEADERS src/pathHelper.hpp)
endif()
# libusb_attach_kernel_driver is only available on Linux.
if (${CMAKE_SYSTEM_NAME} MATCHES "Linux")
add_definitions(-DATTACH_KERNEL)
endif()
if (ENABLE_UDEV)
include_directories(${LIBUDEV_INCLUDE_DIRS})
target_link_libraries(openFPGALoader ${LIBUDEV_LIBRARIES})
endif()
if (ENABLE_LIBGPIOD)
include_directories(${LIBGPIOD_INCLUDE_DIRS})
target_link_libraries(openFPGALoader ${LIBGPIOD_LIBRARIES})
add_definitions(-DENABLE_LIBGPIOD=1)
target_sources(openFPGALoader PRIVATE src/libgpiodJtagBitbang.cpp)
list (APPEND OPENFPGALOADER_HEADERS src/libgpiodJtagBitbang.hpp)
if (LIBGPIOD_VERSION VERSION_GREATER_EQUAL 2)
message("libgpiod v2 support enabled")
add_definitions(-DGPIOD_APIV2)
else()
message("libgpiod v1 support enabled")
endif()
endif(ENABLE_LIBGPIOD)
if (ENABLE_JETSONNANOGPIO)
add_definitions(-DENABLE_JETSONNANOGPIO=1)
target_sources(openFPGALoader PRIVATE src/jetsonNanoJtagBitbang.cpp)
list (APPEND OPENFPGALOADER_HEADERS src/jetsonNanoJtagBitbang.hpp)
message("Jetson Nano GPIO support enabled")
endif(ENABLE_JETSONNANOGPIO)
if (ENABLE_UDEV OR ENABLE_LIBGPIOD OR ENABLE_JETSONNANOGPIO)
add_definitions(-DUSE_DEVICE_ARG)
endif(ENABLE_UDEV OR ENABLE_LIBGPIOD OR ENABLE_JETSONNANOGPIO)
if (BUILD_STATIC)
set_target_properties(openFPGALoader PROPERTIES LINK_SEARCH_END_STATIC 1)
endif()
if (ENABLE_CMSISDAP)
if (HIDAPI_FOUND)
include_directories(${HIDAPI_INCLUDE_DIRS})
target_link_libraries(openFPGALoader ${HIDAPI_LIBRARIES})
add_definitions(-DENABLE_CMSISDAP=1)
target_sources(openFPGALoader PRIVATE src/cmsisDAP.cpp)
list (APPEND OPENFPGALOADER_HEADERS src/cmsisDAP.hpp)
message("cmsis_dap support enabled")
else()
message("hidapi-libusb not found: cmsis_dap support disabled")
endif()
endif(ENABLE_CMSISDAP)
if (${CMAKE_SYSTEM_NAME} MATCHES "Linux")
add_definitions(-DENABLE_XVC=1)
target_sources(openFPGALoader PRIVATE src/xvc_client.cpp src/xvc_server.cpp)
list (APPEND OPENFPGALOADER_HEADERS src/xvc_client.hpp src/xvc_server.hpp)
set(CMAKE_EXE_LINKER_FLAGS "-pthread ${CMAKE_EXE_LINKER_FLAGS}")
message("Xilinx Virtual Server support enabled")
else()
message("Xilinx Virtual Server support disabled")
endif()
if (ENABLE_REMOTEBITBANG)
add_definitions(-DENABLE_REMOTEBITBANG=1)
target_sources(openFPGALoader PRIVATE src/remoteBitbang_client.cpp)
list (APPEND OPENFPGALOADER_HEADERS src/remoteBitbang_client.hpp)
message("Remote bitbang client support enabled")
else()
message("Remote bitbang client support disabled")
endif()
if (ZLIB_FOUND)
include_directories(${ZLIB_INCLUDE_DIRS})
target_link_libraries(openFPGALoader ${ZLIB_LIBRARIES})
add_definitions(-DHAS_ZLIB=1)
else()
message("zlib library not found: can't flash intel/altera devices")
endif()
if (LINK_CMAKE_THREADS)
find_package(Threads REQUIRED)
target_link_libraries(openFPGALoader Threads::Threads)
endif()
# libftdi < 1.4 as no usb_addr
# libftdi >= 1.5 as purge_buffer obsolete
string(REPLACE "." ";" VERSION_LIST ${LIBFTDI_VERSION})
list(GET VERSION_LIST 0 LIBFTDI_VERSION_MAJOR)
list(GET VERSION_LIST 1 LIBFTDI_VERSION_MINOR)
math(EXPR FTDI_VAL "${LIBFTDI_VERSION_MAJOR} * 100 + ${LIBFTDI_VERSION_MINOR}")
add_definitions(-DFTDI_VERSION=${FTDI_VAL})
install(TARGETS openFPGALoader DESTINATION bin)
file(GLOB GZ_FILES spiOverJtag/spiOverJtag_*.*.gz)
# Compress rbf and bit files present into repository
# TODO: test compat with Windows and MacOS
list(INSERT CMAKE_MODULE_PATH 0 ${PROJECT_SOURCE_DIR}/cmake/Modules)
include(FindGZIP)
if (NOT ${CMAKE_SYSTEM_NAME} MATCHES "Windows" AND GZIP_PRG)
set(SPIOVERJTAG_DIR "${CMAKE_CURRENT_SOURCE_DIR}/spiOverJtag")
file(GLOB BITS_FILES RELATIVE ${SPIOVERJTAG_DIR} spiOverJtag/spiOverJtag_*.bit)
file(GLOB RBF_FILES RELATIVE ${SPIOVERJTAG_DIR} spiOverJtag/spiOverJtag_*.rbf)
STRING(REGEX REPLACE ".bit" ".bit.gz" BIT_GZ_FILES "${BITS_FILES}")
STRING(REGEX REPLACE ".rbf" ".rbf.gz" RBF_GZ_FILES "${RBF_FILES}")
FOREACH(bit ${BITS_FILES} ${RBF_FILES})
ADD_CUSTOM_COMMAND(OUTPUT ${bit}.gz
COMMAND ${GZIP_PRG} -9 -c ${bit} > ${CMAKE_CURRENT_BINARY_DIR}/${bit}.gz
DEPENDS ${SPIOVERJTAG_DIR}/${bit}
WORKING_DIRECTORY ${SPIOVERJTAG_DIR}
COMMENT "Building ${bit}.gz")
list(APPEND GZ_FILES ${CMAKE_CURRENT_BINARY_DIR}/${bit}.gz)
ENDFOREACH(bit)
ADD_CUSTOM_TARGET(bit ALL DEPENDS ${BIT_GZ_FILES} ${RBF_GZ_FILES})
else()
file(GLOB BITS_FILES spiOverJtag/spiOverJtag_*.bit)
file(GLOB RBF_FILES spiOverJtag/spiOverJtag_*.rbf)
install(FILES
${BITS_FILES}
${RBF_FILES}
DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/openFPGALoader
)
endif()
install(FILES
${GZ_FILES}
DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/openFPGALoader
)
openFPGALoader-0.13.1/LICENSE 0000664 0000000 0000000 00000026135 14735055600 0015343 0 ustar 00root root 0000000 0000000 Apache License
Version 2.0, January 2004
http://www.apache.org/licenses/
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
1. Definitions.
"License" shall mean the terms and conditions for use, reproduction,
and distribution as defined by Sections 1 through 9 of this document.
"Licensor" shall mean the copyright owner or entity authorized by
the copyright owner that is granting the License.
"Legal Entity" shall mean the union of the acting entity and all
other entities that control, are controlled by, or are under common
control with that entity. For the purposes of this definition,
"control" means (i) the power, direct or indirect, to cause the
direction or management of such entity, whether by contract or
otherwise, or (ii) ownership of fifty percent (50%) or more of the
outstanding shares, or (iii) beneficial ownership of such entity.
"You" (or "Your") shall mean an individual or Legal Entity
exercising permissions granted by this License.
"Source" form shall mean the preferred form for making modifications,
including but not limited to software source code, documentation
source, and configuration files.
"Object" form shall mean any form resulting from mechanical
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openFPGALoader-0.13.1/README.md 0000664 0000000 0000000 00000020623 14735055600 0015611 0 ustar 00root root 0000000 0000000 # openFPGALoader
First steps โข Install โข Troubleshooting โข Advanced usage
Universal utility for programming FPGAs. Compatible with many boards, cables and FPGA from major manufacturers (Xilinx, Altera/Intel, Lattice, Gowin, Efinix, Anlogic, Cologne Chip). openFPGALoader works on Linux, Windows and macOS.
Not sure if your hardware is supported? Check the hardware compatibility lists:
* [FPGA compatibility list](https://trabucayre.github.io/openFPGALoader/compatibility/fpga.html)
* [Board compatibility list](https://trabucayre.github.io/openFPGALoader/compatibility/board.html)
* [Cable compatibility list](https://trabucayre.github.io/openFPGALoader/compatibility/cable.html)
Also checkout the vendor-specific documentation:
[Anlogic](https://trabucayre.github.io/openFPGALoader/vendors/anlogic.html),
[Cologne Chip](https://trabucayre.github.io/openFPGALoader/vendors/colognechip.html),
[Efinix](https://trabucayre.github.io/openFPGALoader/vendors/efinix.html),
[Gowin](https://trabucayre.github.io/openFPGALoader/vendors/gowin.html),
[Intel/Altera](https://trabucayre.github.io/openFPGALoader/vendors/intel.html),
[Lattice](https://trabucayre.github.io/openFPGALoader/vendors/lattice.html),
[Xilinx](https://trabucayre.github.io/openFPGALoader/vendors/xilinx.html).
OpenFPGALoader has a dedicated channel: [#openFPGALoader at libera.chat](https://web.libera.chat/#openFPGALoader).
## Quick Usage
`arty` in the example below is one of the many FPGA board configurations listed [here](https://trabucayre.github.io/openFPGALoader/compatibility/board.html).
```bash
openFPGALoader -b arty arty_bitstream.bit # Loading in SRAM
openFPGALoader -b arty -f arty_bitstream.bit # Writing in flash
```
You can also specify a JTAG cable model (complete list [here](https://trabucayre.github.io/openFPGALoader/compatibility/cable.html)) instead of the board model:
```bash
openFPGALoader -c cmsisdap fpga_bitstream.bit
```
## Usage
```
Usage: openFPGALoader [OPTION...] BIT_FILE
openFPGALoader -- a program to flash FPGA
--altsetting arg DFU interface altsetting (only for DFU mode)
--bitstream arg bitstream
--secondary-bitstream arg
secondary bitstream (some Xilinx UltraScale
boards)
-b, --board arg board name, may be used instead of cable
-B, --bridge arg disable spiOverJtag model detection by
providing bitstream(intel/xilinx)
-c, --cable arg jtag interface
--status-pin arg JTAG mode / FTDI: GPIO pin number to use as a
status indicator (active low)
--invert-read-edge JTAG mode / FTDI: read on negative edge
instead of positive
--vid arg probe Vendor ID
--pid arg probe Product ID
--cable-index arg probe index (FTDI and cmsisDAP)
--busdev-num arg select a probe by it bus and device number
(bus_num:device_addr)
--ftdi-serial arg FTDI chip serial number
--ftdi-channel arg FTDI chip channel number (channels 0-3 map to
A-D)
-d, --device arg device to use (/dev/ttyUSBx)
--detect detect FPGA, add -f to show connected flash
--dfu DFU mode
--dump-flash Dump flash mode
--bulk-erase Bulk erase flash
--enable-quad Enable quad mode for SPI Flash
--disable-quad Disable quad mode for SPI Flash
--target-flash arg for boards with multiple flash chips (some
Xilinx UltraScale boards), select the target
flash: primary (default), secondary or both
--external-flash select ext flash for device with internal and
external storage
--file-size arg provides size in Byte to dump, must be used
with dump-flash
--file-type arg provides file type instead of let's deduced
by using extension
--flash-sector arg flash sector (Lattice parts only)
--fpga-part arg fpga model flavor + package
--freq arg jtag frequency (Hz)
-f, --write-flash write bitstream in flash (default: false)
--index-chain arg device index in JTAG-chain
--misc-device arg add JTAG non-FPGA devices
--ip arg IP address (XVC and remote bitbang client)
--list-boards list all supported boards
--list-cables list all supported cables
--list-fpga list all supported FPGA
-m, --write-sram write bitstream in SRAM (default: true)
-o, --offset arg Start address (in bytes) for read/write into
non volatile memory (default: 0)
--pins arg pin config TDI:TDO:TCK:TMS
--probe-firmware arg firmware for JTAG probe (usbBlasterII)
--protect-flash arg protect SPI flash area
--quiet Produce quiet output (no progress bar)
-r, --reset reset FPGA after operations
--scan-usb scan USB to display connected probes
--skip-load-bridge skip writing bridge to SRAM when in
write-flash mode
--skip-reset skip resetting the device when in write-flash
mode
--spi SPI mode (only for FTDI in serial mode)
--unprotect-flash Unprotect flash blocks
-v, --verbose Produce verbose output
--verbose-level arg verbose level -1: quiet, 0: normal,
1:verbose, 2:debug
-h, --help Give this help list
--verify Verify write operation (SPI Flash only)
--xvc Xilinx Virtual Cable Functions
--port arg Xilinx Virtual Cable and remote bitbang Port
(default 3721)
--mcufw arg Microcontroller firmware
--conmcu Connect JTAG to MCU
-D, --read-dna Read DNA (Xilinx FPGA only)
-X, --read-xadc Read XADC (Xilinx FPGA only)
--read-register arg Read Status Register(Xilinx FPGA only)
-V, --Version Print program version
Mandatory or optional arguments to long options are also mandatory or optional
for any corresponding short options.
Report bugs to .
```
By default **spiOverJtag** are search into `${CMAKE_INSTALL_FULL_DATAROOTDIR}`
(*/usr/local/share/* by default). It's possible to change this behaviour by
using an environment variable:
```bash
export OPENFPGALOADER_SOJ_DIR=/somewhere
openFPGALoader xxxx
```
or
```
OPENFPGALOADER_SOJ_DIR=/somewhere openFPGALoader xxxx
```
`OPENFPGALOADER_SOJ_DIR` must point to directory containing **spiOverJtag**
bitstreams.
openFPGALoader-0.13.1/cmake/ 0000775 0000000 0000000 00000000000 14735055600 0015407 5 ustar 00root root 0000000 0000000 openFPGALoader-0.13.1/cmake/Modules/ 0000775 0000000 0000000 00000000000 14735055600 0017017 5 ustar 00root root 0000000 0000000 openFPGALoader-0.13.1/cmake/Modules/FindGZIP.cmake 0000664 0000000 0000000 00000000332 14735055600 0021371 0 ustar 00root root 0000000 0000000 FIND_PROGRAM(GZIP_PRG
NAMES gzip
PATHS /bin
/usr/bin
/usr/local/bin
${CYGWIN_INSTALL_PATH}/bin
${MSYS_INSTALL_PATH}/usr/bin
)
IF(NOT GZIP_PRG)
message("Unable to find 'gzip' program")
ENDIF(NOT GZIP_PRG)
openFPGALoader-0.13.1/doc/ 0000775 0000000 0000000 00000000000 14735055600 0015074 5 ustar 00root root 0000000 0000000 openFPGALoader-0.13.1/doc/FPGAs.yml 0000664 0000000 0000000 00000020047 14735055600 0016522 0 ustar 00root root 0000000 0000000 Anlogic:
- Description: EG4
Model: S20
URL: http://www.anlogic.com/prod_view.aspx?TypeId=10&Id=168&FId=t3:10:3
Memory: OK
Flash: AS
- Description: SALELF 2
Model: EF2M45
URL: http://www.anlogic.com/prod_view.aspx?TypeId=12&Id=170&FId=t3:12:3
Memory: OK
Flash: OK
Cologne Chip:
- Description: GateMate Series
Model:
- CCGM1A1
- CCGM1A2
- CCGM1A4
- CCGM1A9
- CCGM1A16
- CCGM1A25
URL: https://colognechip.com/programmable-logic/gatemate/
Memory: OK
Flash: OK
Efinix:
- Description: Trion
Model:
- T8
- T13
URL: https://www.efinixinc.com/products-trion.html
Memory: NA
Flash: OK
- Description: Titanium
Model:
- Ti60
- Ti180
URL: https://www.efinixinc.com/products-titanium.html
Memory: NA
Flash: OK
Gowin:
- Description: GW1N
Model:
- GW1N-1
- GW1N-4
- GW1NR-9
- GW1NR-9C
- GW1NS-2C
- GW1NSR-4C
- GW1NZ-1
- GW2A-18C
- GW2A-55
- GW5AST-138
- GW5AT-138
- GW5A-25
URL: https://www.gowinsemi.com/en/product/detail/2/
Memory: OK
Flash: IF / EF
Intel:
- Description: Max II(CPLD)
Model: EPM240T100C5N
URL: https://www.intel.com/content/www/us/en/support/programmable/support-resources/devices/max-ii-support.html
Memory: OK
Flash: OK
- Description: Cyclone II
Model: EP2C5T144C8N
URL: https://www.intel.com/content/www/us/en/support/programmable/support-resources/devices/cyclone-ii-support.html
Memory: OK
Flash: OK
- Description: Cyclone III
Model: EP3C16
URL: https://www.intel.com/content/www/us/en/programmable/products/fpga/cyclone-series/cyclone-iii/support.html
Memory: OK
Flash: OK
- Description: Cyclone IV CE
Model:
- EP4CE22
- EP4CE115
URL: https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-iv/features.html
Memory: OK
Flash: OK
- Description: Cyclone IV GX
Model:
- EP4CGX150
URL: https://www.intel.com/content/www/us/en/products/details/fpga/cyclone/iv/gx/products.html
Memory: OK
Flash: OK
- Description: Cyclone V E
Model:
- 5CEA2
- 5CEA5
- 5CEBA4
- 5CEBA9
URL: https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-v.html
Memory: OK
Flash: OK
- Description: Cyclone V SE SoC
Model:
- 5CSEBA6
- 5CSEMA4
- 5CSEMA5
URL: https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-v.html
Memory: OK
Flash: NT
- Description: Stratix V GS
Model:
- 5SGSD5
URL: https://www.intel.de/content/www/de/de/products/sku/210318/stratix-v-5sgsd5-fpga/specifications.html
Memory: OK
Flash: OK
- Description: Cyclone 10 LP
Model: 10CL025
URL: https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-10.html
Memory: OK
Flash: OK
- Description: Max 10
Model: 10M08
URL: https://www.intel.fr/content/www/fr/fr/products/details/fpga/max/10.html
Memory: SVF
Flash: POF
Lattice:
- Description: Certus-NX
Model: LFD2NX-40
URL: https://www.latticesemi.com/Products/FPGAandCPLD/Certus-NX
Memory: OK
Flash: OK
- Description: CertusPro-NX
Model: LFCPNX-100
URL: https://www.latticesemi.com/Products/FPGAandCPLD/Certus-NX
Memory: OK
Flash: OK
- Description: CrossLink-NX
Model: LIFCL-40
URL: https://www.latticesemi.com/en/Products/FPGAandCPLD/CrossLink-NX
Memory: OK
Flash: OK
- Description: ECP5
Model:
- LFE5U-12
- LFE5U-25
- LFE5U-45
- LFE5U-85
- LFE5UM-25
- LFE5UM-45
- LFE5UM-85
- LFE5UM5G-25
- LFE5UM5G-45
- LFE5UM5G-85
URL: http://www.latticesemi.com/Products/FPGAandCPLD/ECP5
Memory: OK
Flash: OK
- Description: iCE40
Model:
- HX1K
- HX4K
- HX8K
- UP5K
URL: https://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40
Memory: OK
Flash: AS
- Description: MachXO2
Model:
- '256'
- '640'
- '640U'
- '1200'
- '1200U'
- '2000'
- '2000U'
- '4000'
- '7000'
URL: https://www.latticesemi.com/en/Products/FPGAandCPLD/MachXO2
Memory: OK
Flash: OK
- Description: MachXO3D
Model:
- '4300'
- '9400'
URL: http://www.latticesemi.com/en/Products/FPGAandCPLD/MachXO3D.aspx
Memory: OK
Flash: OK
- Description: MachXO3LF
Model:
- '640'
- '1300'
- '2100'
- '4300'
- '6900'
- '9400'
URL: http://www.latticesemi.com/en/Products/FPGAandCPLD/MachXO3.aspx
Memory: OK
Flash: OK
Xilinx:
- Description: Artix 7
Model:
- xc7a25t
- xc7a35ti
- xc7a50t
- xc7a75t
- xc7a100t
- xc7a200t
URL: https://www.xilinx.com/products/silicon-devices/fpga/artix-7.html
Memory: OK
Flash: OK
- Description: Kintex 7
Model:
- xc7k70t
- xc7k160t
- xc7k325t
- xc7k410t
- xc7k420t
URL: https://www.xilinx.com/products/silicon-devices/fpga/kintex-7.html#productTable
Memory: OK
Flash: OK
- Description: Virtex 7
Model:
- xc7v585t
- xc7v2000t
- xc7vx330t
- xc7vx415t
- xc7vx485t
- xc7vx550t
- xc7vx690t
- xc7vx980t
- xc7vx1140t
- xc7vh580t
- xc7vh870t
URL: https://www.xilinx.com/products/silicon-devices/fpga/virtex-7.html#productTable
Memory: OK
Flash: OK
- Description: Artix UltraScale+
Model:
- xcau15p
- xcau25p
URL: https://www.xilinx.com/products/silicon-devices/fpga/artix-ultrascale-plus.html
Memory: OK
Flash: TBD
- Description: Kintex UltraScale
Model:
- xcku035
- xcku040
- xcku060
- xcku115
URL: https://www.xilinx.com/products/silicon-devices/fpga/kintex-ultrascale.html#productTable
Memory: OK
Flash: OK (primary)
- Description: Virtex 6
Model:
- xc6vlx130t
URL: https://www.xilinx.com/products/silicon-devices/fpga/virtex-6.html
Memory: OK
Flash: OK
- Description: Virtex UltraScale
Model:
- xcvu095
URL: https://www.amd.com/en/products/adaptive-socs-and-fpgas/fpga/virtex-ultrascale.html#productTable
Memory: OK
Flash: TBD
- Description: Virtex UltraScale+
Model:
- xcvu9p
URL: https://www.xilinx.com/products/silicon-devices/fpga/virtex-ultrascale-plus.html#productTable
Memory: OK
Flash: OK
- Description: Spartan 3
Model:
- xc3s200
- xc3s500e
URL: https://www.xilinx.com/products/silicon-devices/fpga/spartan-3.html
Memory: OK
Flash: OK
- Description: Spartan 6
Model:
- xc6slx9
- xc6slx16
- xc6slx25
- xc6slx45
- xc6slx45T
- xc6slx150T
URL: https://www.xilinx.com/products/silicon-devices/fpga/spartan-6.html
Memory: OK
Flash: OK
- Description: Spartan 7
Model:
- xc7s15
- xc7s25
- xc7s50
URL: https://www.xilinx.com/products/silicon-devices/fpga/spartan-7.html
Memory: OK
Flash: OK
- Description: XC9500XL
Model:
- xc9536xl
- xc9572xl
- xc95144xl
- xc95188xl
URL: https://www.xilinx.com/support/documentation/data_sheets/ds054.pdf
Memory: NA
Flash: OK
- Description: XC2C/XA2C (coolrunner II)
Model:
- xc2c32a
- xa2c64a
URL: https://www.xilinx.com/support/documentation/data_sheets/ds090.pdf
Memory: TBD
Flash: OK
- Description: XCF
Model:
- xcf01s
- xcf02s
- xcf04s
URL: https://www.xilinx.com/products/silicon-devices/configuration-memory/platform-flash.html
Memory: NA
Flash: OK
- Description: Zynq7000
Model:
- xc7z010
- xc7z020
URL: https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html
Memory: OK
Flash: NA
- Description: ZynqMPSoC
Model:
- xczu2cg
- xczu9eg
- xczu11eg
- xczu17eg
URL: https://www.xilinx.com/products/silicon-devices/soc/zynq-ultrascale-mpsoc.html
Memory: OK
Flash: NA
openFPGALoader-0.13.1/doc/Makefile 0000664 0000000 0000000 00000000506 14735055600 0016535 0 ustar 00root root 0000000 0000000 SPHINXOPTS =
SPHINXBUILD = sphinx-build
PAPER =
BUILDDIR = _build
PAPEROPT_a4 = -D latex_paper_size=a4
PAPEROPT_letter = -D latex_paper_size=letter
ALLSPHINXOPTS = -d $(BUILDDIR)/doctrees -T -D language=en $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) .
%:
$(SPHINXBUILD) -b $@ $(ALLSPHINXOPTS) $(BUILDDIR)/$@
openFPGALoader-0.13.1/doc/boards.yml 0000664 0000000 0000000 00000063472 14735055600 0017105 0 ustar 00root root 0000000 0000000 - ID: ac701
Description: Xilinx Artix-7 FPGA AC701 Evaluation Kit
URL: https://www.xilinx.com/products/boards-and-kits/ek-a7-ac701-g.html
FPGA: Artix xc7a200t2fbg676c
Memory: OK
Flash: NT
Constraints: AC701
- ID: acornCle215
Description: Acorn CLE 215+
URL: http://squirrelsresearch.com/acorn-cle-215
FPGA: Artix xc7a200tsbg484
Memory: OK
Flash: OK
- ID: litex-acorn-baseboard-mini
Description: The LiteX-Acorn-Baseboards are baseboards developed around the SQRL's Acorn board (or Nite/LiteFury)
URL: https://github.com/enjoy-digital/litex-acorn-baseboard/
FPGA: Artix xc7a200tsbg484
Memory: OK
Flash: OK
- ID: alchitry_au
Description: Alchitry Au
URL: https://alchitry.com/products/alchitry-au-fpga-development-board
FPGA: Artix xc7a35tftg256
Memory: OK
Flash: OK
- ID: alchitry_au_plus
Description: Alchitry Au+ (Plus)
URL: https://www.sparkfun.com/products/17514
FPGA: Artix xc7a100tftg256
Memory: OK
Flash: OK
- ID: alinx_ax516
Description: ALINX AX516
URL: https://www.alinx.com/en/detail/281
FPGA: Spartan6 xc6slx16csg324
Memory: OK
Flash: OK
- ID: alinx_ax7101
Description: ALINX AX/7101
URL: https://alinx.com/en/detail/494
FPGA: Artix xc7a100tfgg484
Memory: OK
Flash: OK
- ID: alinx_ax7102
Description: ALINX AX/7102
URL: https://alinx.com/en/detail/493
FPGA: Artix xc7a100tfgg484
Memory: OK
Flash: OK
- ID: analogMax
Description: Trenz TEI0010 - AnalogMax
URL: https://wiki.trenz-electronic.de/display/PD/TEI0010+-+AnalogMax
FPGA: Max 10 10M08SAU169C8G
Memory: SVF
Flash: SVF
- ID: antmicro_ddr4_tester
Description: Antmicro Data Center DRAM Tester
URL: https://opensource.antmicro.com/projects/data-center-dram-tester
FPGA: Kintex7 xc7k160t
Memory: OK
Flash: OK
- ID: antmicro_ddr5_tester
Description: Antmicro DDR5 Tester
URL: https://opensource.antmicro.com/projects/ddr5-tester
FPGA: Kintex7 xc7k160t
Memory: OK
Flash: OK
- ID: antmicro_lpddr4_tester
Description: Antmicro LPDDR4 Test Board
URL: https://opensource.antmicro.com/projects/lpddr4-test-board
FPGA: Kintex7 xc7k70t
Memory: OK
Flash: OK
- ID: arty_a7_35t
Description: Digilent Arty A7
URL: https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start
FPGA: Artix xc7a35ticsg324
SPIFlash: (N25Q128 v1)
Memory: OK
Flash: OK
Constraints: Arty-A7-35T
- ID: arty_a7_100t
Description: Digilent Arty A7
URL: https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start
FPGA: Artix xc7a100tcsg324
Memory: OK
Flash: OK
Constraints: Arty-A7-100T
- ID: arty_s7_25
Description: Digilent Arty S7
URL: https://reference.digilentinc.com/reference/programmable-logic/arty-s7/start
FPGA: Spartan7 xc7s25csga324
Memory: OK
Flash: OK
Constraints: Arty-S7-25
- ID: arty_s7_50
Description: Digilent Arty S7
URL: https://reference.digilentinc.com/reference/programmable-logic/arty-s7/start
FPGA: Spartan7 xc7s50csga324
Memory: OK
Flash: OK
Constraints: Arty-S7-50
- ID: arty_z7_10
Description: Digilent Arty S7
URL: https://reference.digilentinc.com/reference/programmable-logic/arty-z7/start
FPGA: Zynq7000 xc7z010csg400
Memory: OK
Flash: NA
- ID: arty_z7_20
Description: Digilent Arty S7
URL: https://reference.digilentinc.com/reference/programmable-logic/arty-z7/start
FPGA: Zynq7000 xc7z020csg400
Memory: OK
Flash: NA
- ID: arty
Description: Digilent Analog Discovery 2
URL: https://reference.digilentinc.com/test-and-measurement/analog-discovery-2/start
FPGA: Spartan6 xc6slx25
Memory: OK
Flash: NT
- ID: arty
Description: Digilent Digital Discovery
URL: https://reference.digilentinc.com/test-and-measurement/digital-discovery/start
FPGA: Spartan6 xc6slx25
Memory: OK
Flash: NT
- ID: axu2cga
Description: Alinx AXU2CGA Zynq MPSoC Dev Board
URL: http://www.alinx.com/en/index.php/default/content/101.html
FPGA: ZynqMPSoC XCZU2CG
Memory: OK
Flash: NA
- ID: basys3
Description: Digilent Basys3
URL: https://reference.digilentinc.com/reference/programmable-logic/basys-3/start
FPGA: Artix xc7a35tcpg236
Memory: OK
Flash: OK
- ID: cmod_s7
Description: Digilent Cmod S7
URL: https://https://digilent.com/reference/programmable-logic/cmod-s7/start
FPGA: Spartan7 xc7s25csga225
Memory: NA
Flash: OK
- ID: gatemate_evb_jtag
Description: Cologne Chip GateMate FPGA Evaluation Board (JTAG mode)
URL: https://colognechip.com/programmable-logic/gatemate-evaluation-board/
FPGA: Cologne Chip GateMate Series
Memory: OK
Flash: OK
- ID: gatemate_evb_spi
Description: Cologne Chip GateMate FPGA Evaluation Board (SPI mode)
URL: https://colognechip.com/programmable-logic/gatemate-evaluation-board/
FPGA: Cologne Chip GateMate Series
Memory: OK
Flash: OK
- ID: gatemate_pgm_spi
Description: Cologne Chip GateMate FPGA Programmer (SPI mode)
URL: https://colognechip.com/programmable-logic/gatemate/
FPGA: Cologne Chip GateMate Series
Memory: OK
Flash: OK
- ID: certusnx_versa_evn
Description: Certus-NX Versa Evaluation Board
URL: https://www.latticesemi.com/products/developmentboardsandkits/certuspro-nx-versa-board
FPGA: Certus LFD2NX-40
Memory: OK
Flash: OK
- ID: certuspronx_evn
Description: CertusPro-NX Evaluation Board
URL: https://www.latticesemi.com/products/developmentboardsandkits/certuspro-nxevaluationboard
FPGA: CertusPro-NX LFCPNX-100
Memory: OK
Flash: OK
- ID: certuspronx_versa_evn
Description: CertusPro-NX Versa
URL: https://www.latticesemi.com/products/developmentboardsandkits/certuspro-nx-versa-board
FPGA: CertusPro-NX LFCPNX-100
Memory: OK
Flash: OK
- ID: cmoda7_15t
Description: Digilent CmodA7
URL: https://digilent.com/reference/programmable-logic/cmod-a7/start
FPGA: Artix xc7a15tcpg236
Memory: OK
Flash: OK
- ID: cmoda7_35t
Description: Digilent CmodA7
URL: https://digilent.com/reference/programmable-logic/cmod-a7/start
FPGA: Artix xc7a35tcpg236
Memory: OK
Flash: OK
- ID: colorlight
Description: Colorlight 5A-75B (version 7)
URL: https://fr.aliexpress.com/item/32281130824.html
FPGA: ECP5 LFE5U-25F-6BG256C
Memory: OK
Flash: OK
- ID: colorlight-i5
Description: Colorlight I5
URL: https://www.colorlight-led.com/product/colorlight-i5-led-display-receiver-card.html
FPGA: ECP5 LFE5U-25F-6BG381C
Memory: OK
Flash: OK
Constraints: Colorlight-i5-v7.0
- ID: colorlight-i9
Description: Colorlight I9
URL: https://www.colorlightinside.com/Products/i%20Receiving-series/34_101.html
FPGA: ECP5 LFE5U-45F-6BG381C
Memory: OK
Flash: OK
Constraints: Colorlight-i9-v7.2
- ID: colorlight-i9+
Description: Colorlight I9+
URL: https://www.colorlight-led.tech/colorlight-i9-2/
FPGA: Artix xc7a50tfgg484
Memory: OK
Flash: OK
- ID: crosslinknx_evn
Description: Lattice CrossLink-NX Evaluation Board
URL: https://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/CrossLink-NXEvaluationBoard
FPGA: Nexus LIFCL-40
Memory: OK
Flash: OK
- ID: cyc1000
Description: Trenz cyc1000
URL: https://shop.trenz-electronic.de/en/TEI0003-02-CYC1000-with-Cyclone-10-FPGA-8-MByte-SDRAM
FPGA: Cyclone 10 LP 10CL025YU256C8G
Memory: OK
Flash: OK
- ID: cyc5000
Description: Trenz CYC5000
URL: https://shop.trenz-electronic.de/en/TEI0050-01-AAH13A-CYC5000-with-Cyclone-V-FPGA-25kLE-8-MByte-SDRAM
FPGA: Cyclone V 5CEBA2U15C8
Memory: OK
Flash: OK
- ID: c10lp-refkit
Description: Trenz c10lp-refkit
URL: https://shop.trenz-electronic.de/en/TEI0009-02-055-8CA-Cyclone-10-LP-RefKit-10CL055-Development-Board-32-MByte-SDRAM-16-MByte-Flash
FPGA: Cyclone 10 LP 10CL055YU484C8G
Memory: OK
Flash: OK
- ID: c5g
Description: Terasic C5G (Cyclone V GX Starter Kit)
URL: https://www.terasic.com.tw/cgi-bin/page/archive.pl?No=830
FPGA: Cyclone V GX 5CGXFC5C6F27C7N
Memory: OK
Flash: NT
- ID: de0
Description: Terasic DE0
URL: https://www.terasic.com.tw/cgi-bin/page/archive.pl?No=364
FPGA: Cyclone III EP3C16F484C6
Memory: OK
Flash: NT
- ID: de0nano
Description: Terasic de0nano
URL: https://www.terasic.com.tw/cgi-bin/page/archive.pl?No=593
FPGA: Cyclone IV E EP4CE22F17C6
Memory: OK
Flash: OK
- ID: de0nanoSoc
Description: Terasic de0nanoSoc
URL: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=205&No=941
FPGA: Cyclone V SoC 5CSEMA4U23C6
Memory: OK
- ID: de10lite
Description: Terasic de10lite
URL: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=218&No=1021&PartNo=1
FPGA: MAX 10 10M50DAF484C7G
Memory: OK
- ID: de10nano
Description: Terasic de10Nano
URL: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=205&No=1046
FPGA: Cyclone V SoC 5CSEBA6U23I7
Memory: OK
- ID: de1Soc
Description: Terasic DE1-SoC
URL: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=836
FPGA: Cyclone V SoC 5CSEMA5F31C6
Memory: OK
- ID: deca
Description: Arrow/Terasic DECA
URL: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=&No=944&PartNo=1
FPGA: MAX 10 10M50DAF484C6GES
Memory: OK
- ID: dragonL
Description: KNJN Dragon-L PCI Express & HDMI FPGA board
URL: https://www.knjn.com/FPGA-Dragon-L.html
FPGA: Spartan6 xc6slx25Tcsg324
Memory: OK
Flash: OK
- ID: ecp5_evn
Description: Lattice ECP5 5G Evaluation Board
URL: https://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/ECP5EvaluationBoard
FPGA: ECP5G LFE5UM5G-85F
Memory: OK
Flash: OK
Constraints: ECP5-EVN
- ID: ecpix5
Description: LambdaConcept ECPIX-5 (FT2232)
URL: https://shop.lambdaconcept.com/home/46-2-ecpix-5.html#/2-ecpix_5_fpga-ecpix_5_85f
FPGA: ECP5 LFE5UM5G-85F
Memory: OK
Flash: OK
Constraints:
- ECPIX-5-45F
- ECPIX-5-85F
- ID: ecpix5_r03
Description: LambdaConcept ECPIX-5 (FT4232)
URL: https://shop.lambdaconcept.com/home/46-2-ecpix-5.html#/2-ecpix_5_fpga-ecpix_5_85f
FPGA: ECP5 LFE5UM5G-85F
Memory: OK
Flash: OK
Constraints:
- ECPIX-5-45F
- ECPIX-5-85F
- ID: fireant
Description: Fireant Trion T8
URL: https://www.crowdsupply.com/jungle-elec/fireant
FPGA: Trion T8F81
Memory: NA
Flash: AS
- ID: fomu
Description: Fomu PVT
URL: https://tomu.im/fomu.html
FPGA: iCE40UltraPlus UP5K
Memory: NA
Flash: OK
Constraints: Fomu-PVT
- ID: gr740-mini
Description: GR740-MINI
URL: https://gaisler.com/index.php/products/boards/gr740-mini
FPGA: CertusPro-NX LFCPNX-100
Memory: OK
Flash: NA
- ID: honeycomb
Description: honeycomb
URL: https://github.com/Disasm/honeycomb-pcb
FPGA: littleBee GW1NS-2C
Memory: OK
Flash: IF
- ID: hseda-xc6slx16
Description: XILINX SPARTAN6 XC6SLX16 Microblaze SDRAM USB2.0 FPGA
URL: http://hseda.com/product/xilinx/XC6SLX16/XC6SLX16.htm
FPGA: Spartan6 xc6slx16-ftg256
Memory: OK
Flash: OK
- ID: ice40_generic
Description: iCEBreaker
URL: https://1bitsquared.com/collections/fpga/products/icebreaker
FPGA: iCE40UltraPlus UP5K
Memory: NA
Flash: AS
Constraints: iCEBreaker
- ID: icebreaker-bitsy
Description: iCEBreaker-bitsy
URL: https://1bitsquared.com/collections/fpga/products/icebreaker-bitsy
FPGA: iCE40UltraPlus UP5K
Memory: NA
Flash: OK
Constraints:
- iCEBreaker-bitsy-v0
- iCEBreaker-bitsy-v1
- ID: ice40_generic
Description: icestick
URL: https://www.latticesemi.com/icestick
FPGA: iCE40 HX1k
Memory: NA
Flash: AS
Constraints: IceStick
- ID: ice40_generic
Description: iCE40-HX8K
URL: https://www.latticesemi.com/Products/DevelopmentBoardsAndKits/iCE40HX8KBreakoutBoard.aspx
FPGA: iCE40 HX8k
Memory: OK
Flash: AS
Constraints: iCE40-HX8K
- ID: ice40_generic
Description: Olimex iCE40HX1K-EVB
URL: https://www.olimex.com/Products/FPGA/iCE40/iCE40HX1K-EVB/open-source-hardware
FPGA: iCE40 HX1k
Memory: NT
Flash: AS
Constraints: iCE40HX1K-EVB
- ID: ice40_generic
Description: Olimex iCE40HX8K-EVB
URL: https://www.olimex.com/Products/FPGA/iCE40/iCE40HX8K-EVB/open-source-hardware
FPGA: iCE40 HX8k
Memory: NT
Flash: AS
Constraints: iCE40HX8K-EVB
- ID: ice40_generic
Description: iCE40 UltraPlus Breakout Board (iCE40UP5K-B-EVN)
URL: https://www.latticesemi.com/Products/DevelopmentBoardsAndKits/iCE40UltraPlusBreakoutBoard
FPGA: iCE40-UP5K
Memory: NT
Flash: AS
Constraints: iCE40-UP
- ID: ice40_generic
Description: Icezum Alhambra II
URL: https://alhambrabits.com/alhambra
FPGA: iCE40 HX4k
Memory: NT
Flash: AS
Constraints: IceZumAlhambraII
- ID: kc705
Description: Xilinx KC705
URL: https://www.xilinx.com/products/boards-and-kits/ek-k7-kc705-g.html
FPGA: Kintex7 xc7k325t
Memory: OK
Flash: NT
Constraints: KC705
- ID: kcu105
Description: Xilinx KCU105
URL: https://www.xilinx.com/products/boards-and-kits/kcu105.html
FPGA: Kintex UltraScale xcku040-ffva1156
Memory: OK
Flash: OK
- ID: kcu116
Description: Xilinx KCU116
URL: https://www.xilinx.com/products/boards-and-kits/kcu116.html
FPGA: Kintex UltraScale+ xcku5p-ffvb676
Memory: OK
Flash: OK
- ID: LD-KONFEKT
Description: Lone Dynamics Corporation - Machdyne Konfekt computer
URL: https://machdyne.com/product/konfekt-computer/
FPGA: ECP5 LFE5U-12F-6BG256C
Memory: OK
Flash: OK
- ID: LD-SCHOKO
Description: Lone Dynamics Corporation - Machdyne Schoko computer
URL: https://machdyne.com/product/schoko-computer/
FPGA: ECP5 LFE5U-45F-6CABGA256
Memory: OK
Flash: OK
- ID: licheeTang
Description: Sipeed Lichee Tang
URL: https://tang.sipeed.com/en/hardware-overview/lichee-tang/
FPGA: eagle s20 EG4S20BG256
Memory: OK
Flash: OK
- ID: lilygo-t-fpga
Description: Lilygo T-FPGA
URL: https://www.lilygo.cc/products/t-fpga
FPGA: Gowin GW1NSR-LV4CQN48PC6/15
Memory: OK
Flash: OK
- ID: machXO2EVN
Description: Lattice MachXO2 Breakout Board Evaluation Kit
URL: https://www.latticesemi.com/products/developmentboardsandkits/machxo2breakoutboard
FPGA: MachXO2 LCMXO2-7000HE
Memory: OK
Flash: OK
- ID: machXO3EVN
Description: Lattice MachXO3D Development Board
URL: https://www.latticesemi.com/products/developmentboardsandkits/machxo3d_development_board
FPGA: MachXO3D LCMXO3D-9400HC
Memory: OK
Flash: NT
- ID: machXO3SK
Description: Lattice MachXO3LF Starter Kit
URL: https://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/MachXO3LFStarterKit
FPGA: MachXO3 LCMX03LF-6900C
Memory: OK
Flash: OK
- ID: mini_itx
Description: Avnet Mini-ITX Base Kit
URL: https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/mini-itx/
FPGA: AMD Xilinx XC7Z045/XC7Z100-2FFG900
Memory: OK
Flash: NA
- ID: mimas_a7
Description: Numato Systems Mimas A7
URL: https://numato.com/product/mimas-a7-artix-7-fpga-development-board/
FPGA: Artix xc7a50tfgg484
Memory: OK
Flash: OK
- ID: nexys_a7_50
Description: Digilent Nexys A7(Nexys 4 DDR)
URL: https://digilent.com/reference/programmable-logic/nexys-a7/start
FPGA: Artix xc7a50tcsg324
Memory: OK
Flash: OK
Constraints: Nexys4DDR
- ID: nexys_a7_100
Description: Digilent Nexys A7(Nexys 4 DDR)
URL: https://digilent.com/reference/programmable-logic/nexys-a7/start
FPGA: Artix nexys_a7_100
Memory: OK
Flash: OK
Constraints: Nexys4DDR
- ID: nexysVideo
Description: Digilent Nexys Video
URL: https://reference.digilentinc.com/reference/programmable-logic/nexys-video/start
FPGA: Artix xc7a200tsbg484
Memory: OK
Flash: OK
- ID: xem8320
Description: Opal Kelly XEM8320
URL: https://opalkelly.com/products/xem8320/
FPGA: Artix UltraScale+ xcau25p-2ffvb676e
Memory: OK
Flash: TBD
- ID: olimex_gatemateevb
Description: Olimex CCGMA1 Cologne Chip GateMate FPGA Evaluation Board
URL: https://www.olimex.com/Products/FPGA/GateMate/GateMateA1-EVB/open-source-hardware
FPGA: Cologne Chip GateMate Series (GM1A1)
Memory: OK
Flash: NT
- ID: orbtrace_dfu
Description: ORBTrace mini (dfu mode)
URL: https://store.zyp.no/product/orbtrace-mini
FPGA: ECP5 LFE5U-25F-8BG256C
Memory: NA
Flash: OK (DFU)
- ID: orangeCrab
Description: Orange Crab
URL: https://github.com/gregdavill/OrangeCrab
FPGA: ECP5 LFE5U-25F-8MG285C
Memory: OK (JTAG)
Flash: OK (DFU)
Constraints: OrangeCrab-r0.2
- ID: papilio_one
Description: Papilio One
URL: https://papilio.cc/index.php?n=Papilio.PapilioOne
FPGA: Spartan3E xc3s500e-vq100
Memory: OK
Flash: OK
- ID: pipistrello
Description: Saanlima Pipistrello LX45
URL: http://pipistrello.saanlima.com/index.php?title=Welcome_to_Pipistrello
FPGA: Spartan6 xc6slx45-csg324
Memory: OK
Flash: OK
- ID: pynq_z1
Description: PYNQ-Z1
URL: https://digilent.com/reference/programmable-logic/pynq-z1/start
FPGA: Zynq7000 xc7z020clg400
Memory: OK
Flash: NA
- ID: pynq_z2
Description: PYNQ-Z2
URL: https://www.tulembedded.com/FPGA/ProductsPYNQ-Z2.html
FPGA: Zynq7000 xc7z020clg400
Memory: OK
Flash: NA
- ID: qmtechCyclone10
Description: QMTech Cyclone 10 Starter Kit
URL: http://www.chinaqmtech.com/productinfo/1858435.html
FPGA: Cyclone 10 LP 10CL016YU484C8G
Memory: OK
Flash: OK
- ID: qmtechCycloneIV
Description: QMTech CycloneIV Core Board
URL: https://fr.aliexpress.com/item/32949281189.html
FPGA: Cyclone IV EP4CE15F23C8N
Memory: OK
Flash: OK
- ID: qmtechCycloneV
Description: QMTech CycloneV Core Board
URL: https://fr.aliexpress.com/i/1000006622149.html
FPGA: Cyclone V 5CEFA2F23I7
Memory: OK
Flash: OK
- ID: qmtechCycloneV_5ce523
Description: QMTech CycloneV Core Board
URL: https://fr.aliexpress.com/item/1005001782703399.html
FPGA: Cyclone V 5CEFA5F23I7
Memory: OK
Flash: OK
- ID: qmtechKintex7
Description: QMTech Kintex7 Core Board
URL: https://www.aliexpress.com/item/1005003668804223.html
FPGA: Kintex xc7k325tffg676
Memory: OK
Flash: OK
- ID: genesys2
Description: Digilent Kintex7 Evaluation Board
URL: https://digilent.com/reference/programmable-logic/genesys-2/start
FPGA: Kintex xc7k325tffg900
Memory: OK
Flash: OK
- ID: redpitaya14
Description: Redpitaya/STEMlab xc7z7010 with 125MHz 14 bits ADC
URL: https://redpitaya.com/stemlab-125-14/
FPGA: Zynq7000 xc7z010clg400
Memory: OK
Flash: NA
- ID: runber
Description: SeeedStudio Gowin RUNBER
URL: https://www.seeedstudio.com/Gowin-RUNBER-Development-Board-p-4779.html
FPGA: littleBee GW1N-4
Memory: OK
Flash: IF/EF
- ID: runber
Description: Scarab Hardware MiniSpartan6+
URL: https://www.kickstarter.com/projects/1812459948/minispartan6-a-powerful-fpga-board-and-easy-to-use
FPGA: Spartan6 xc6slx25-3-ftg256
Memory: OK
Flash: NT
- ID: spartanEdgeAccelBoard
Description: SeeedStudio Spartan Edge Accelerator Board
URL: http://wiki.seeedstudio.com/Spartan-Edge-Accelerator-Board
FPGA: Spartan7 xc7s15ftgb196
Memory: OK
Flash: NA
- ID: SPEC45
Description: CERN Simple PCIe FMC carrier SPEC
URL: https://ohwr.org/project/spec150/wikis/home
FPGA: Spartan6 xc6slx45Tfgg484
Memory: OK
Flash: OK
- ID: SPEC150
Description: CERN Simple PCIe FMC carrier SPEC
URL: https://ohwr.org/project/spec150/wikis/home
FPGA: Spartan6 xc6slx150Tfgg484
Memory: OK
Flash: OK
- ID: stlv7325
Description: Sitlinv STLV7325 Board
URL: https://www.aliexpress.com/item/1005001275162791.html
FPGA: Kintex xc7k325tffg676
Memory: OK
Flash: OK
- ID: tangnano
Description: Sipeed Tang Nano
URL: https://tangnano.sipeed.com/en/
FPGA: littleBee GW1N-1
Memory: OK
- ID: tangnano1k
Description: Sipeed Tang Nano 1K
URL: https://tangnano.sipeed.com/en/
FPGA: littleBee GW1NZ-1
Memory: OK
Flash: IF
- ID: tangnano4k
Description: Sipeed Tang Nano 4K
URL: https://tangnano.sipeed.com/en/
FPGA: littleBee GW1NSR-4C
Memory: OK
Flash: IF/EF
- ID: tangnano9k
Description: Sipeed Tang Nano 9K
URL: https://tangnano.sipeed.com/en/
FPGA: littleBee GW1NR-9C
Memory: OK
Flash: IF/EF
- ID: tangnano20k
Description: Sipeed Tang Nano 20k
URL: https://wiki.sipeed.com/nano20k
FPGA: Gowin Arora GW2A(R)-18(C)
Memory: OK
Flash: EF
- ID: tangprimer20k
Description: Sipeed Tang Primer 20k
URL: https://wiki.sipeed.com/en/primer20k
FPGA: Gowin Arora GW2A(R)-18(C)
Memory: OK
Flash: EF
- ID: tangprimer25k
Description: Sipeed Tang Primer 25k
URL: https://wiki.sipeed.com/hardware/zh/tang/tang-primer-25k/primer-25k.html
FPGA: Gowin Arora V GW5A-25A (GW5A-LV25MG121)
Memory: OK
Flash: TBD
- ID: tangmega138k
Description: Sipeed Tang Mega 138k
URL: https://wiki.sipeed.com/hardware/zh/tang/tang-mega-138k/mega-138k.html
FPGA: Gowin Arora V GW5AST-138B (GW5AST-LV138FPG676A)
Memory: OK
Flash: TBD
- ID: te0712_8
Description: Trenz Electronic TE0712 FPGA-Module mit AMD Artixโข 7(TE0712)
URL: https://shop.trenz-electronic.de/en/TE0712-03-81I36-A-FPGA-Module-with-AMD-Artix-7-XC7A200T-1FBG484I-1-GByte-DDR3-4-x-5-cm
FPGA: XC7A200TFBG484
Memory: OK
Flash: OK
- ID: tec0117
Description: Trenz Gowin LittleBee (TEC0117)
URL: https://shop.trenz-electronic.de/en/TEC0117-01-FPGA-Module-with-GOWIN-LittleBee-and-8-MByte-internal-SDRAM
FPGA: littleBee GW1NR-9
Memory: OK
Flash: IF
- ID: trion_t20_bga256_jtag
Description: Efinix Trion T20 BGA256 Dev Kit
URL: https://www.efinixinc.com/products-devkits-triont20.html
FPGA: Trion T20BGA256
Memory: OK
Flash: NT
- ID: tec0330
Description: PCIe FMC Carrier with Xilinx Virtex-7 FPGA (TEC0330)
URL: https://shop.trenz-electronic.de//TEC0330-05-PCIe-FMC-Carrier-with-Xilinx-Virtex-7-FPGA-8-Lane-PCIe-GEN2-SODIMM-SDRAM
FPGA: XC7VX330T-2FFG1157C
Memory: OK
Flash: OK
- ID: trion_t120_bga576
Description: Efinix Trion T120 BGA576 Dev Kit (SPI mode)
URL: https://www.efinixinc.com/products-devkits-triont120bga576.html
FPGA: Trion T120BGA576
Memory: NA
Flash: AS
- ID: trion_t120_bga576_jtag
Description: Efinix Trion T120 BGA576 Dev Kit (JTAG mode)
URL: https://www.efinixinc.com/products-devkits-triont120bga576.html
FPGA: Trion T120BGA576
Memory: OK
Flash: OK
- ID: trion_ti60_f225
Description: Efinix Titanium F225 Dev Kit (SPI mode)
URL: https://www.efinixinc.com/products-devkits-titaniumti60f225.html
FPGA: Titanium Ti60F225
Memory: NA
Flash: AS
- ID: trion_ti60_f225_jtag
Description: Efinix Titanium F225 Dev Kit (JTAG mode)
URL: https://www.efinixinc.com/products-devkits-titaniumti60f225.html
FPGA: Titanium Ti60F225
Memory: OK
Flash: OK
- ID: ulx3s
Description: Radiona ULX3S
URL: https://radiona.org/ulx3s/
FPGA: ECP5 LFE5U
Memory: OK
Flash: OK
Constraints:
- ULX3S-12F
- ULX3S-25F
- ULX3S-45F
- ULX3S-85F
- ID: ulx3s_dfu
Description: Radiona ULX3S DFU mode
URL: https://github.com/emard/had2019-playground
FPGA: ECP5 LFE5U
Memory: NA
Flash: OK
- ID: vec_v6
Description: Xilinx VCU118
URL: https://vmm-srs.docs.cern.ch/
FPGA: xc6vlx130tff784
Memory: OK
Flash: OK
- ID: vc709
Description: AMD Virtex-7 FPGA VC709 Connectivity Kit
URL: https://www.xilinx.com/products/boards-and-kits/dk-v7-vc709-g.html
FPGA: Virtex7 xc7vx690tffg1761
Memory: OK
Flash: NA
- ID: vcu108
Description: Xilinx VCU108
URL: https://www.xilinx.com/products/boards-and-kits/vcu108.html
FPGA: Virtex UltraScale xcvu095-ffva2104
Memory: OK
Flash: TBD
- ID: vcu118
Description: Xilinx VCU118
URL: https://www.xilinx.com/products/boards-and-kits/vcu118.html
FPGA: Virtex UltraScale+ xcvu9p-flga2104
Memory: OK
Flash: OK
- ID: vcu128
Description: Xilinx VCU128
URL: https://www.xilinx.com/products/boards-and-kits/vcu128.html
FPGA: Virtex UltraScale+ xcvu37p-fsvh2892
Memory: OK
Flash: OK
- ID: vcu1525
Description: AMD Virtex UltraScale+ FPGA VCU1525 Acceleration Development Kit
URL: https://www.xilinx.com/products/boards-and-kits/vcu1525-a.html
FPGA: Virtex UltraScale+ xcvu9p-fsgd2104
Memory: OK
Flash: NT
- ID: xtrx
Description: FairWaves XTRXPro
URL: https://www.crowdsupply.com/fairwaves/xtrx
FPGA: Artix xc7a50tcpg236
SPIFlash: N25Q256
Memory: OK
Flash: OK
- ID: xyloni_spi
Description: Efinix Xyloni
URL: https://www.efinixinc.com/products-devkits-xyloni.html
FPGA: Trion T8F81
Memory: NA
Flash: AS
- ID: usrpx300
Description: Ettus Research USRP X300
URL: https://www.ettus.com/all-products/x300-kit/
FPGA: Kintex xc7k325tffg900
Memory: OK
Flash: NA
- ID: usrpx310
Description: Ettus Research USRP X300
URL: https://www.ettus.com/all-products/x310-kit/
FPGA: Kintex xc7k410tffg900
Memory: OK
Flash: NA
- ID: xmf3
Description: PLDkit XMF3
URL: https://pldkit.com/xilinx/xmf3
FPGA: Xilinx xc3s200ft256, xcf01s
Memory: OK
Flash: OK
- ID: zc702
Description: Xilinx ZC702
URL: https://www.xilinx.com/products/boards-and-kits/ek-z7-zc702-g.html
FPGA: zynq7000 xc7z020clg484
Memory: OK
Flash: NA
- ID: zc706
Description: Xilinx ZC706
URL: https://www.xilinx.com/products/boards-and-kits/ek-z7-zc706-g.html
FPGA: zynq7000 xc7z045ffg900
Memory: OK
Flash: NA
Constraints: ZC706
- ID: zcu102
Description: Xilinx ZCU102
URL: https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html
FPGA: zynqMPSoC XCZU9EG
Memory: OK
Flash: NA
- ID: zcu106
Description: Xilinx ZCU106
URL: https://www.xilinx.com/products/boards-and-kits/zcu106.html
FPGA: zynqMPSoC XCZU7EV
Memory: OK
Flash: NA
- ID: zedboard
Description: Avnet ZedBoard
URL: https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/zedboard/
FPGA: zynq7000 xc7z020clg484
Memory: OK
Flash: NA
Constraints: ZedBoard
- ID: zybo_z7_10
Description: Digilent Zybo Z7-10
URL: https://reference.digilentinc.com/reference/programmable-logic/zybo-z7/start
FPGA: zynq7000 xc7z010clg400
Memory: OK
Flash: NA
- ID: zybo_z7_20
Description: Digilent Zybo Z7-20
URL: https://reference.digilentinc.com/reference/programmable-logic/zybo-z7/start
FPGA: zynq7000 xc7z020clg400
Memory: OK
Flash: NA
- ID: VMM3
Description: CERN board with VMM3
URL: https://vmm-srs.docs.cern.ch/
FPGA: xc7s50csga324?
Memory: OK
Flash: OK
- ID: efinix_jtag_ft2232
Description: Efinix FT2232 development boards with JTAG on port 2 (Ti180J484 EVK, etc)
URL: https://www.efinixinc.com/products-devkits-titaniumti180j484.html
FPGA: Titanium Ti180J484 (and others)
Memory: OK
Flash: NA
openFPGALoader-0.13.1/doc/cable.yml 0000664 0000000 0000000 00000020250 14735055600 0016664 0 ustar 00root root 0000000 0000000 anlogicCable:
- Name: anlogic JTAG adapter
Description: JTAG adapter firmware for stm32
URL: https://github.com/AnlogicInfo/anlogic-usbjtag
arm-usb-ocd-h:
- Name: Olimex ARM-USB-OCD-H adapter
Description: High-speed 3-IN-1 fast USB ARM JTAG, USB-to-RS232 virtual port and power supply 5VDC device
URL: https://www.olimex.com/Products/ARM/JTAG/ARM-USB-OCD-H/
bus_blaster:
- Name: Dangerousprototypes Bus Blaster
Description: Jtag adapter based on ft2232
URL: http://dangerousprototypes.com/docs/Bus_Blaster
bus_blaster_b:
- Name: Dangerousprototypes Bus Blaster
Description: Jtag adapter based on ft2232 (interface B)
URL: http://dangerousprototypes.com/docs/Bus_Blaster
ch347_jtag:
- Name: ch347 JTAG adapter
Description: QinHeng Electronics USB To UART+JTAG (mode 3)
URL: https://www.wch-ic.com/products/CH347.html
ch552_jtag:
- Name: ch552 JTAG adapter
Description: Tang Nano USB-JTAG interface. FT2232C clone firmware for CH552 microcontroler
URL: https://github.com/diodep/ch55x_jtag
cmsisdap:
- Name: ARM CMSIS DAP protocol interface
Description: ARM CMSIS DAP protocol interface (hid only)
URL: https://os.mbed.com/docs/mbed-os/v6.11/debug-test/daplink.html
gatemate_pgm:
- Name: gatemate pgm
Description: Cologne Chip GateMate FPGA Programmer. FT232H-based JTAG/SPI programmer cable
URL: https://colognechip.com/programmable-logic/gatemate/
gatemate_evb_jtag:
- Name: gatemate evb JTAG
Description: Cologne Chip GateMate JTAG programmer
URL: https://colognechip.com/programmable-logic/gatemate/
gatemate_evb_spi:
- Name: gatemate evb spi
Description: Cologne Chip GateMate SPI programmer
URL: https://colognechip.com/programmable-logic/gatemate/
gwu2x:
- Name: gwu2x
Description: Gowin GWUX2X
URL: https://www.gowinsemi.com/en/product/detail/55/
dfu:
- Name: DFU interface
Description: DFU (Device Firmware Upgrade) USB device compatible with DFU protocol
URL: http://www.usb.org/developers/docs/devclass_docs/DFU_1.1.pdf
digilent:
- Name: digilent cable
Description: FT2232 JTAG / UART cable
diglent_b:
- Name: digilent cable
Description: digilent FT2232 JTAG / UART cable (interface B)
digilent_hs2:
- Name: digilent hs2 cable
Description: FT232H JTAG programmer cable from digilent
URL: https://store.digilentinc.com/jtag-hs2-programming-cable/
digilent_hs3:
- Name: digilent hs3
Description: JTAG programmer cable from digilent
URL: https://digilent.com/shop/jtag-hs3-programming-cable/
dirtyJtag:
- Name: dirty Jtag
Description: JTAG probe firmware for STM32F1
URL: https://github.com/jeanthom/DirtyJTAG
Note: Best to use release (1.4 or newer) or limit the --freq to 600000 with older releases.
New version `dirtyjtag2 `__ is also supported
efinix_spi_ft4232:
- Name: efinix SPI (ft4232)
Description: efinix SPI interface (FTDI4232 interface A)
efinix_jtag_ft4232:
- Name: efinix JTAG (ft4232)
Description: efinix JTAG interface (FTDI4232 interface B)
efinix_spi_ft2232:
- Name: efinix SPI (ft2232)
Description: efinix SPI interface (FTDI2232 interface A)
efinix_jtag_ft2232:
- Name: efinix JTAG (ft2232)
Description: efinix JTAG interface (FTDI2232 interface B)
ft2232:
- Name: FT2232 C/D/H
Description: generic programmer cable based on Ftdi FT2232 (interface A)
- Name: Tang Nano (1k, 4k, 8k) USB-JTAG interface
Description: USB-JTAG/UART debugger based on BL702 microcontroler.
URL: https://github.com/sipeed/RV-Debugger-BL702
- Name: Sipeed RV-Debugger-BL702
Description: RV-Debugger-BL702 is an opensource project that implement a JTAG+UART debugger with BL702C-A0.
URL: https://github.com/sipeed/RV-Debugger-BL702
- Name: honeycomb USB-JTAG interface.
Description: FT2232C clone based on STM32F042 microcontroler
URL: https://github.com/Disasm/f042-ftdi
ft2232_b:
- Name: FT2232 C/D/H
Description: generic programmer cable based on Ftdi FT2232 (interface B)
ft231X:
- Name: FT231X
Description: generic USB<->UART converters in bitbang mode (with some limitations and workaround)
URL: https://www.ftdichip.com/old2020/Products/ICs/FT231X.html
ft232:
- Name: FT232H
Description: generic programmer cable based on Ftdi FT232Hx. One interface, MPSSE capable
URL: https://ftdichip.com/products/ft232hl/
ft232RL:
- Name: FT232RL
Description: generic USB<->UART converters in bitbang mode (with some limitations and workaround)
URL: https://ftdichip.com/products/ft232rl/
ft4232:
- Name: FT4232
Description: quad interface programmer cable. MPSSE capable.
URL: https://ftdichip.com/products/ft4232h-56q/
ft4232hp:
- Name: FT4232HP (interface A)
Description: quad interface programmer cable. MPSSE capable. High Speed USB Bridge with Type-C/PD3.0 Controller
URL: https://ftdichip.com/wp-content/uploads/2023/02/DS_FT4233HP.pdf
ft4232hp_b:
- Name: FT4232HP (interface B)
Description: quad interface programmer cable. MPSSE capable. High Speed USB Bridge with Type-C/PD3.0 Controller
URL: https://ftdichip.com/wp-content/uploads/2023/02/DS_FT4233HP.pdf
ecpix5-debug:
- Name: ecpix5-debug
Description: LambdaConcept ECPIX5 (45k/85k) UART/JTAG interface
URL: https://shop.lambdaconcept.com/home/46-ecpix-5.html
jlink:
- Name: jlink
Description: SEGGER J-Link Debug Probes
URL: https://www.segger.com/products/debug-probes/j-link
- Name: jlink_base
Description: SEGGER J-Link BASE Debug Probes
- Name: jtrace_pro
Description: SEGGER J-Trace PRO Debug Probes
jtag-smt2-nc:
- Name: jtag-smt2-nc
Description: JTAG-SMT2-NC Surface-mount Programming Module
URL: https://digilent.com/shop/jtag-smt2-nc-surface-mount-programming-module
lpc-link2:
- Name: lpc-link2
Description: LPC-Link2 (OM13054) cmsisDAP firmware
URL: https://www.nxp.com/design/microcontrollers-developer-resources/lpc-link2:OM13054
numato:
- Name: numato
Description: Embedded cable for Numato Systems Mimas-A7 board
orbtrace:
- Name: orbtrace interface
Description: Open source FPGA-based debug and trace interface
URL: https://github.com/orbcode/orbtrace
papilio:
- Name: papilio
Description: Papilio FPGA Platform
URL: https://papilio.cc/
steppenprobe:
- Name: steppenprobe
Description: Open Source Hardware JTAG/SWD/UART/SWO interface board based on FTDI FT2232H
URL: https://github.com/diegoherranz/steppenprobe
remote-bitgang:
- Name: OpenOCD remote bitbang
Description: The remote_bitbang JTAG driver is used to drive JTAG from a remote (TCP) process
URL: https://github.com/openocd-org/openocd/blob/master/doc/manual/jtag/drivers/remote_bitbang.txt
tigard:
- Name: tigard
Description: SWD/JTAG/UART/SPI programmer based on Ftdi FT2232HQ
URL: https://www.crowdsupply.com/securinghw/tigard
usb-blaster:
- Name: intel USB Blaster I interface
Description: JTAG programmer cable from intel/altera (FT245 + EPM7064)
usb-blasterII:
- Name: intel USB Blaster II interface
Description: JTAG programmer cable from intel/altera (EZ-USB FX2 + EPM570)
URL: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_usb_blstr_ii_cable.pdf
xvc-client:
- Name: Xilinx Virtual Cable
Description: Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable.
URL: https://github.com/Xilinx/XilinxVirtualCable
xvc-server:
- Name: Xilinx Virtual Cable (server side)
Description: Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable.
URL: https://github.com/Xilinx/XilinxVirtualCable
libgpiod:
- Name: Bitbang GPIO
Description: Bitbang GPIO pins on Linux host.
URL: https://git.kernel.org/pub/scm/libs/libgpiod/libgpiod.git/
jetson-nano-gpio:
- Name: Bitbang GPIO
Description: Bitbang GPIO pins on Jetson Nano Linux host. Use /dev/mem to have a faster clock.
URL: https://github.com/jwatte/jetson-gpio-example
ch347:
- Name: CH347
Description: CH347 is a USB HS bus converter with UART, I2C, SPI and JTAG interfaces
URL: https://github.com/wuxx/USB-HS-Bridge
openFPGALoader-0.13.1/doc/compatibility/ 0000775 0000000 0000000 00000000000 14735055600 0017745 5 ustar 00root root 0000000 0000000 openFPGALoader-0.13.1/doc/compatibility/board.rst 0000664 0000000 0000000 00000000645 14735055600 0021573 0 ustar 00root root 0000000 0000000 .. _compatibility:boards:
Boards
######
.. NOTE::
`arty` can be any of the board names from the first column.
.. code-block:: bash
openFPGALoader -b arty bitstream.bit # Loading in SRAM (volatile)
openFPGALoader -b arty -f bitstream.bit # Writing in flash (non-volatile)
.. include:: boards.inc
* IF: Internal Flash
* EF: External Flash
* AS: Active Serial flash mode
* NA: Not Available
* NT: Not Tested
openFPGALoader-0.13.1/doc/compatibility/cable.rst 0000664 0000000 0000000 00000000101 14735055600 0021535 0 ustar 00root root 0000000 0000000 .. _compatibility:cables:
Cables
######
.. include:: cable.inc
openFPGALoader-0.13.1/doc/compatibility/fpga.rst 0000664 0000000 0000000 00000000227 14735055600 0021415 0 ustar 00root root 0000000 0000000 .. _compatibility:fpgas:
FPGAs
#####
.. include:: fpga.inc
* IF: Internal Flash
* AS: Active Serial flash mode
* NA: Not Available
* NT: Not Tested
openFPGALoader-0.13.1/doc/conf.py 0000664 0000000 0000000 00000007236 14735055600 0016403 0 ustar 00root root 0000000 0000000 # -*- coding: utf-8 -*-
from sys import path as sys_path
from os.path import abspath
from pathlib import Path
from json import loads
ROOT = Path(__file__).resolve().parent
sys_path.insert(0, abspath("."))
from data import (
ReadBoardDataFromYAML,
BoardDataToTable,
ReadFPGADataFromYAML,
FPGADataToTable,
ReadCableDataFromYAML,
CableDataToTable
)
# -- General configuration ------------------------------------------------
extensions = [
# Standard Sphinx extensions
"sphinx.ext.extlinks",
"sphinx.ext.intersphinx",
]
templates_path = ["_templates"]
source_suffix = {
".rst": "restructuredtext",
}
master_doc = "index"
project = u"openFPGALoader: universal utility for programming FPGA"
copyright = u"2019-2022, Gwenhael Goavec-Merou and contributors"
author = u"Gwenhael Goavec-Merou and contributors"
version = "latest"
release = version # The full version, including alpha/beta/rc tags.
language = None
exclude_patterns = []
numfig = True
# -- Options for HTML output ----------------------------------------------
html_context = {}
ctx = ROOT / "context.json"
if ctx.is_file():
html_context.update(loads(ctx.open("r").read()))
if (ROOT / "_theme").is_dir():
html_theme_path = ["."]
html_theme = "_theme"
html_theme_options = {
"home_breadcrumbs": False,
"vcs_pageview_mode": "blob",
}
else:
html_theme = "alabaster"
htmlhelp_basename = "OFLDoc"
# -- Options for LaTeX output ---------------------------------------------
latex_elements = {
"papersize": "a4paper",
}
latex_documents = [
(master_doc, "OFLDoc.tex", u"openFPGALoader: universal utility for programming FPGA (Documentation)", author, "manual"),
]
# -- Options for manual page output ---------------------------------------
# One entry per manual page. List of tuples
# (source start file, name, description, authors, manual section).
man_pages = [(master_doc, "openFPGALoader", u"Universal utility for programming FPGA (Documentation)", [author], 1)]
# -- Options for Texinfo output -------------------------------------------
texinfo_documents = [
(
master_doc,
"openFPGALoader",
u"Universal utility for programming FPGA (Documentation)",
author,
"openFPGALoader",
"HDL verification.",
"Miscellaneous",
),
]
# -- Sphinx.Ext.InterSphinx -----------------------------------------------
intersphinx_mapping = {
"python": ("https://docs.python.org/3/", None),
"constraints": ("https://hdl.github.io/constraints", None)
}
# -- Sphinx.Ext.ExtLinks --------------------------------------------------
extlinks = {
"wikipedia": ("https://en.wikipedia.org/wiki/%s", None),
"ghsharp": ("https://github.com/trabucayre/openFPGALoader/issues/%s", "#"),
"ghissue": ("https://github.com/trabucayre/openFPGALoader/issues/%s", "issue #"),
"ghpull": ("https://github.com/trabucayre/openFPGALoader/pull/%s", "pull request #"),
"ghsrc": ("https://github.com/trabucayre/openFPGALoader/blob/master/%s", None),
}
# -- Generate partial board compatibility page (`board.inc`) with data from `boards.yml`
with (ROOT / "compatibility/boards.inc").open("w", encoding="utf-8") as wptr:
wptr.write(BoardDataToTable(ReadBoardDataFromYAML()))
# -- Generate partial FPGA compatibility page (`fpga.inc`) with data from `FPGAs.yml`
with (ROOT / "compatibility/fpga.inc").open("w", encoding="utf-8") as wptr:
wptr.write(FPGADataToTable(ReadFPGADataFromYAML()))
# -- Generate partial Cable compatibility page (`cable.inc`) with data from `cable.yml`
with (ROOT / "compatibility/cable.inc").open("w", encoding="utf-8") as wptr:
wptr.write(CableDataToTable(ReadCableDataFromYAML()))
openFPGALoader-0.13.1/doc/data.py 0000664 0000000 0000000 00000006245 14735055600 0016366 0 ustar 00root root 0000000 0000000 from typing import List, Union
from pathlib import Path
from dataclasses import dataclass
from yaml import load as yaml_load, Loader as yaml_loader, dump as yaml_dump
from tabulate import tabulate
ROOT = Path(__file__).resolve().parent
@dataclass
class Board:
ID: str
Description: str = None
URL: str = None
FPGA: str = None
Memory: str = None
Flash: str = None
Constraints: str = None
SPIFlash: str = None
def ReadBoardDataFromYAML():
with (ROOT / 'boards.yml').open('r', encoding='utf-8') as fptr:
data = [Board(**item) for item in yaml_load(fptr, yaml_loader)]
return data
def BoardDataToTable(data, tablefmt: str = "rst"):
def processConstraints(constraints):
if constraints is None:
return None
if isinstance(constraints, str):
constraints = [constraints]
return " ".join([f":ref:`{item} โ `" for item in constraints])
return tabulate(
[
[
item.ID,
f"`{item.Description} <{item.URL}>`__",
item.FPGA,
item.Memory,
item.Flash,
processConstraints(item.Constraints)
] for item in data
],
headers=["Board name", "Description", "FPGA", "Memory", "Flash", "Constraints"],
tablefmt=tablefmt
)
@dataclass
class FPGA:
Model: Union[str, List[str]]
Description: str
URL: str = None
Memory: str = None
Flash: str = None
def ReadFPGADataFromYAML():
with (ROOT / 'FPGAs.yml').open('r', encoding='utf-8') as fptr:
data = yaml_load(fptr, yaml_loader)
for vendor, content in data.items():
data[vendor] = [FPGA(**item) for item in content]
return data
def FPGADataToTable(data, tablefmt: str = "rst"):
return tabulate(
[
[
f":ref:`{vendor} <{vendor.lower().replace(' ','')}>`",
f"`{item.Description} <{item.URL}>`__",
item.Model if isinstance(item.Model, str) else ', '.join(item.Model),
item.Memory,
item.Flash
] for vendor, content in data.items() for item in content
],
headers=["Vendor", "Description", "Model", "Memory", "Flash"],
tablefmt=tablefmt
)
@dataclass
class Cable:
Name: str
Description: str
URL: str = None
Note: str = None
def ReadCableDataFromYAML():
with (ROOT / 'cable.yml').open('r', encoding='utf-8') as fptr:
data = yaml_load(fptr, yaml_loader)
for keyword, content in data.items():
data[keyword] = [Cable(**item) for item in content]
return data
def CableDataToTable(data, tablefmt: str = "rst"):
def processURL(name, url):
if url is None:
return f"{name}"
else:
return f"`{name} <{url}>`__"
return tabulate(
[
[
f"{vendor}",
processURL(item.Name, item.URL),
item.Description
] for vendor, content in data.items() for item in content
],
headers=["keyword", "Name", "Description"],
tablefmt=tablefmt
)
openFPGALoader-0.13.1/doc/guide/ 0000775 0000000 0000000 00000000000 14735055600 0016171 5 ustar 00root root 0000000 0000000 openFPGALoader-0.13.1/doc/guide/advanced.rst 0000664 0000000 0000000 00000004445 14735055600 0020477 0 ustar 00root root 0000000 0000000 .. _advanced-usage:
Advanced usage of openFPGALoader
################################
Resetting an FPGA
=================
.. code-block:: bash
openFPGALoader [options] -r
Using negative edge for TDO's sampling
======================================
If transaction are unstable you can try to change read edge by using
.. code-block:: bash
openFPGALoader [options] --invert-read-edge
Reading the bitstream from STDIN
================================
.. code-block:: bash
cat /path/to/bitstream.ext | openFPGALoader --file-type ext [options]
``--file-type`` is required to detect file type.
.. NOTE::
It's possible to load a bitstream through network:
.. code-block:: bash
# FPGA side
nc -lp port | openFPGALoader --file-type xxx [option
# Bitstream side
nc -q 0 host port < /path/to/bitstream.ext
Automatic file type detection bypass
====================================
Default behavior is to use file extension to determine file parser.
To avoid this mechanism ``--file-type type`` must be used.
FT231/FT232 bitbang mode and pins configuration
===============================================
FT232R and ft231X may be used as JTAG programmer.
JTAG communications are emulated in bitbang mode.
To use these devices user needs to provides both the cable and the pin mapping:
.. code-block:: bash
openFPGALoader [options] -cft23XXX --pins=TDI:TDO:TCK:TMS /path/to/bitstream.ext
where:
* ft23XXX may be ``ft232RL`` or ``ft231X``.
* TDI:TDO:TCK:TMS may be the pin ID (0 <= id <= 7) or string value.
allowed values are:
===== ==
value ID
===== ==
TXD 0
RXD 1
RTS 2
CTS 3
DTR 4
DSR 5
DCD 6
RI 7
===== ==
Writing to an arbitrary address in flash memory
===============================================
With FPGA using an external SPI flash (*xilinx*, *lattice ECP5/nexus/ice40*, *anlogic*, *efinix*) option ``-o`` allows
one to write raw binary file to an arbitrary adress in FLASH.
Using an alternative directory for *spiOverJtag*
================================================
By setting ``OPENFPGALOADER_SOJ_DIR`` it's possible to override default
*spiOverJtag* bitstreams directory:
.. code-block:: bash
export OPENFPGALOADER_SOJ_DIR=/somewhere
openFPGALoader xxxx
or
.. code-block:: bash
OPENFPGALOADER_SOJ_DIR=/somewhere openFPGALoader xxxx
openFPGALoader-0.13.1/doc/guide/first-steps.rst 0000664 0000000 0000000 00000004274 14735055600 0021215 0 ustar 00root root 0000000 0000000 .. _first-steps:
First steps with openFPGALoader
###############################
Install
=======
Packages are available for Linux distributions, Windows (MSYS2) and macOS:
* *Arch Linux*: ``sudo pacman -S openfpgaloader``
* *Fedora*: ``sudo dnf copr enable mobicarte/openFPGALoader; sudo dnf install openFPGALoader``
* *MSYS2*: ``pacman -S mingw-w64-ucrt-x86_64-openFPGALoader``
* *macOS*: ``brew install openfpgaloader``
More instructions for other installation scenarios are available in :ref:`install`.
Programming a development board
===============================
Just simply replace ``my_fpga_board`` with any FPGA board from :ref:`compatibility:boards`
(or ``openFPGALoader --list-boards``) in any of the two commands below, depending on if you want to program the volatile
part of your FPGA (faster but not persistent) or the flash part of your FPGA (slower but persistent):
.. code-block:: bash
openFPGALoader -b my_fpga_board my_bitstream.bit # Program to SRAM
openFPGALoader -b my_fpga_board -f my_bitstream.bit # Program to flash
.. NOTE::
When a bitstream file is compatible with both memory load and FLASH write, the default behavior is to load bitstream
in memory.
Programming an "standalone" FPGA
================================
If your FPGA doesn't come with a built-in programmer or if you prefer to use an external cable, you can specify a cable
to use from :ref:`compatibility:cables` (or ``openFPGALoader --list-cables``):
.. code-block:: bash
openFPGALoader -c my_cable my_bitstream.bit # Program to SRAM
openFPGALoader -c my_cable -f my_bitstream.bit # Program to flash
.. NOTE::
For some cable (like digilent adapters) signals from the converter are not just directly to the FPGA.
For this case, the ``-c`` must be added.
.. HINT::
FTDI/FTDI-compatible cable users: the ``-d`` option lets you specify a specific FTDI device:
.. code-block:: bash
openFPGALoader -d /dev/ttyUSBX
When the ``-d`` option is not provided, openFPGALoader will opens the first FTDI adapter it finds.
Therefore it is preferable to use this flag if your computer is connected to multiple FTDI devices.
Troubleshooting
===============
Please refer to :ref:`troubleshooting`.
openFPGALoader-0.13.1/doc/guide/install.rst 0000664 0000000 0000000 00000011167 14735055600 0020377 0 ustar 00root root 0000000 0000000 .. _install:
Installing openFPGALoader
#########################
Linux
=====
Debian/Ubuntu
----------
openFPGALoader is available in the default repositories:
.. code-block:: bash
sudo apt install openfpgaloader
Guix
----------
openFPGALoader is available in the default repositories:
.. code-block:: bash
guix install openfpgaloader
Arch Linux
----------
openFPGALoader is available in the default repositories:
.. code-block:: bash
sudo pacman -S openfpgaloader
Alternatively, you could build from source. First: install required libraries:
.. code-block:: bash
sudo pacman -S git cmake make gcc pkgconf libftdi libusb zlib hidapi gzip
Build step is similar as Debian
Fedora
------
openFPGALoader is available as a Copr repository:
.. code-block:: bash
sudo dnf copr enable mobicarte/openFPGALoader
sudo dnf install openFPGALoader
From source
----------------------------
This application uses ``libftdi1``, so this library must be installed (and, depending on the distribution, headers too):
.. code-block:: bash
sudo apt install \
git \
gzip \
libftdi1-2 \
libftdi1-dev \
libhidapi-hidraw0 \
libhidapi-dev \
libudev-dev \
zlib1g-dev \
cmake \
pkg-config \
make \
g++
.. HINT::
``libudev-dev`` is optional, may be replaced by ``eudev-dev`` or just not installed.
By default, ``(e)udev`` support is enabled (used to open a device by his ``/dev/xx`` node).
If you don't want this option, use:
.. code-block:: bash
-DENABLE_UDEV=OFF
By default, ``cmsisdap`` support is enabled (used for colorlight I5, I9).
If you don't want this option, use:
.. code-block:: bash
-DENABLE_CMSISDAP=OFF
Alternatively you can manually specify the location of ``libusb`` and ``libftdi1``:
.. code-block:: bash
-DUSE_PKGCONFIG=OFF \
-DLIBUSB_LIBRARIES= \
-DLIBFTDI_LIBRARIES= \
-DLIBFTDI_VERSION= \
-DCMAKE_CXX_FLAGS="-I -I"
You may also need to add this if you see link errors between ``libusb`` and ``pthread``:
.. code-block:: bash
-DLINK_CMAKE_THREADS=ON
By default, ``libgpiod`` support is enabled
If you don't want this option, use:
.. code-block:: bash
-DENABLE_LIBGPIOD=OFF
Additionaly you have to install ``libgpiod``
To build the app:
.. code-block:: bash
git clone https://github.com/trabucayre/openFPGALoader
cd openFPGALoader
mkdir build
cd build
cmake .. # add -DBUILD_STATIC=ON to build a static version
# add -DENABLE_UDEV=OFF to disable udev support and -d /dev/xxx
# add -DENABLE_CMSISDAP=OFF to disable CMSIS DAP support
cmake --build .
# or
make -j$(nproc)
To install
.. code-block:: bash
$ sudo make install
The default install path is ``/usr/local``, to change it, use ``-DCMAKE_INSTALL_PREFIX=myInstallDir`` in cmake invokation.
Udev rules
----------
By default, users have no access to converters.
A rule file (:ghsrc:`99-openfpgaloader.rules <99-openfpgaloader.rules>`) for ``udev`` is provided at the root directory
of this repository.
These rules set access right and group (``plugdev``) when a converter is plugged.
.. code-block:: bash
sudo cp 99-openfpgaloader.rules /etc/udev/rules.d/
sudo udevadm control --reload-rules && sudo udevadm trigger # force udev to take new rule
sudo usermod -a $USER -G plugdev # add user to plugdev group
After that you need to unplug and replug your device.
.. HINT::
``usermod`` is used to add ``$USER`` as a member of ``plugdev`` group.
However this update is not taken into account immediately: it's required to
logout from current session and login again.
Check, by using ``id $USER``, if ``plugdev`` is mentioned after ``groups=``.
An alternate (and temporary) solution is to use ``sudo - $USER`` to have
your user seen as a member of ``plugdev`` group (works only for the current terminal).
macOS
=====
openFPGALoader is available as a `Homebrew `__ formula:
.. code-block:: bash
brew install openfpgaloader
Alternatively, if you want to build it by hand:
.. code-block:: bash
brew install --only-dependencies openfpgaloader
brew install cmake pkg-config zlib gzip
git clone https://github.com/trabucayre/openFPGALoader
cd openFPGALoader
mkdir build
cd build
cmake ..
make -j
Windows
=======
Common
======
Bitstreams for *XC2C (coolrunner-II)* needs to be remapped using ``.map`` shipped with *ISE*.
*ISE* path is set at configure time using:
.. code-block:: bash
-DISE_PATH=/somewhere/Xilinx/ISE_VERS/
default: ``/opt/Xilinx/14.7``.
openFPGALoader-0.13.1/doc/guide/troubleshooting.rst 0000664 0000000 0000000 00000004401 14735055600 0022151 0 ustar 00root root 0000000 0000000 .. _troubleshooting:
Troubleshooting
###############
I installed openFPGALoader but it says `command not found` when I try to launch it
==================================================================================
The correct spelling of the program is *openFPGALoader* with FPGA and the "L" of "Loader" in uppercase.
Ensure the spelling of the program is correct.
Gowin device could not communicate since last bitstream flashed. (issue `#206 `_)
==========================================================================================================================================
Gowin's FPGA may fails to be detected if **JTAGSEL_N** (pin 08 for *GW1N-4K*) is used as a GPIO.
To recover you have to pull down this pin (before power up) to recover JTAG interface (*UG292 - JTAGSELL_N section*).
JTAG init failed
================
Avoid using USB hubs and connect it directly to your PC USB port.
Tang Primer 20k program slow and stucked (issue `#250 `_)
==================================================================================================================
Check your openFPGALoader version:
.. code:: bash
openFPGALoader -V
If it is older than release then v0.9.0, install the most recent version (from commit `f5b89bff68a5e2147404a895c075773884077438 `_ or later).
Cannot flash Tang Nano 9k (issue `#251 `_)
===================================================================================================
This is a device issue, erase its Embedded Flash using Official GoWin Programmer (preferentially in Windows) and SRAM too, then you can use openFPGALoader again.
Unable to open FTDI device: -4 (usb_open() failed) (issue `#245 `_)
============================================================================================================================
Edit your `/etc/udev/rules.d/99-ftdi.rules` file exchanging your programming device permissions.
For more information, check the udev section from `this guide `_ openFPGALoader-0.13.1/doc/index.rst 0000664 0000000 0000000 00000003213 14735055600 0016734 0 ustar 00root root 0000000 0000000 openFPGALoader: universal utility for programming FPGA
######################################################
Welcome to the documentation of openFPGALoader!
openFPGALoader is a universal utility for programming FPGAs.
Compatible with many boards, cables and FPGA from major manufacturers (Xilinx, Altera/Intel, Lattice, Gowin, Efinix, Anlogic, Cologne Chip).
openFPGALoader works on Linux, Windows and macOS.
Not sure if your hardware is supported? Check the hardware compatibility lists:
* :ref:`compatibility:fpgas`
* :ref:`compatibility:boards`
* :ref:`compatibility:cables`
Also checkout the vendor-specific documentation:
* `Anlogic `__
* `Cologne Chip `__
* `Efinix `__
* `Gowin `__
* `Intel/Altera `__
* `Lattice `__
* `Xilinx `__
.. toctree::
:caption: User Guide
:hidden:
guide/first-steps
guide/install
guide/troubleshooting
guide/advanced
.. toctree::
:caption: Compatibility
:hidden:
compatibility/fpga
compatibility/board
compatibility/cable
.. toctree::
:caption: Vendors
:hidden:
vendors/anlogic
vendors/colognechip
vendors/efinix
vendors/gowin
vendors/intel
vendors/lattice
vendors/xilinx
.. toctree::
:caption: Development
:hidden:
todo
openFPGALoader-0.13.1/doc/requirements.txt 0000664 0000000 0000000 00000000027 14735055600 0020357 0 ustar 00root root 0000000 0000000 pyyaml
sphinx
tabulate
openFPGALoader-0.13.1/doc/todo.rst 0000664 0000000 0000000 00000001266 14735055600 0016600 0 ustar 00root root 0000000 0000000 .. _todo:
To Do
#####
Global
======
* improve error message (be more precise)
* catch all exception
* documentation (code + API)
Cable
=====
* fix *ch552* (*Sipeed tangNano*): works with *SRAM*, fails with *Flash*
* *busblaster* support
* *anlogic* cable support
Devices/boards
==============
* improve frequency configuration. Use FPGA, cable or --freq args maximum frequency
* rework *cyclone10* eeprom access to avoid using FT2232 interfaceB Spi emulation (only supported by trenz board)
* fix checksum computation with *gowin GW2A*
* add support for *tangPrimer* (*anlogic EG4S20*)
Misc
====
* fix spiFlash class to be able to write everywhere (currently offset is hardcoded to 0)
openFPGALoader-0.13.1/doc/vendors/ 0000775 0000000 0000000 00000000000 14735055600 0016554 5 ustar 00root root 0000000 0000000 openFPGALoader-0.13.1/doc/vendors/anlogic.rst 0000664 0000000 0000000 00000001760 14735055600 0020726 0 ustar 00root root 0000000 0000000 .. _anlogic:
Anlogic notes
#############
Sipeed Lichee Tang
==================
For this target, *openFPGALoader* supports *svf* and *bit*.
bit file load (memory)
----------------------
.. code-block:: bash
openFPGALoader -m -b licheeTang /somewhere/project/prj/*.bit
Since ``-m`` is the default, this argument is optional.
bit file load (spi flash)
-------------------------
.. code-block:: bash
openFPGALoader -f -b licheeTang /somewhere/project/prj/*.bit
svf file load
-------------
It's possible to produce this file by using *TD*:
* Tools->Device Chain
* Add your bit file
* Option : Create svf
or by using `prjtang project `__:
.. code-block:: bash
mkdir build
cd build
cmake ../
make
Now a file called *tangbit* is present in current directory and has to be used as follows:
.. code-block:: bash
tangbit --input /somewhere.bit --svf bitstream.svf
.. code-block:: bash
openFPGALoader -b licheeTang /somewhere/*.svf
openFPGALoader-0.13.1/doc/vendors/colognechip.rst 0000664 0000000 0000000 00000005225 14735055600 0021604 0 ustar 00root root 0000000 0000000 .. _colognechip:
Cologne Chip notes
##################
Supported Boards/Cables
=======================
* GateMate Evaluation Board using board parameters ``-b gatemate_evb_jtag`` or ``-b gatemate_evb_spi``
* GateMate Programmer using cable parameter ``-c gatemate_pgm``
Programming Modes
=================
Supported configuration files are bitfiles ``*.bit`` and it's ASCII equivalents ``*.cfg``.
JTAG Configuration
------------------
Performs an active hardware reset and writes the configuration into the FPGA latches via JTAG. The configuration mode pins ``CFG_MD[3:0]`` must be set to 0xC (JTAG).
1. Program using Evaluation Board:
.. code-block:: bash
openFPGALoader -b gatemate_evb_jtag .cfg.bit
2. Program using Programmer Cable:
.. code-block:: bash
openFPGALoader -c gatemate_pgm .cfg.bit
SPI Configuration
-----------------
Performs an active hardware reset and writes the configuration into the FPGA latches via SPI. The configuration mode pins ``CFG_MD[3:0]`` must be set to 0x4 (SPI passive).
1. Program using Evaluation Board:
.. code-block:: bash
openFPGALoader -b gatemate_evb_spi .cfg.bit
2. Program using Programmer Cable:
.. code-block:: bash
openFPGALoader -b gatemate_pgm_spi .cfg.bit
JTAG Flash Access
-----------------
It is possible to access external flashes via the internal JTAG-SPI-bypass. The configuration mode pins ``CFG_MD[3:0]`` must be set to 0xC (JTAG). Note that the FPGA will not start automatically.
1. Write to flash using Evaluation Board:
.. code-block:: bash
openFPGALoader -b gatemate_evb_jtag .cfg.bit
2. Write to flash using Programmer Cable:
.. code-block:: bash
openFPGALoader -c gatemate_pgm -f .cfg.bit
The `offset` parameter can be used to store data at any point in the flash, e.g.:
.. code-block:: bash
openFPGALoader -b gatemate_evb_jtag -o .cfg.bit
SPI Flash Access
----------------
If the programming device and FPGA share the same SPI signals, it is possible to hold the FPGA in reset and write data to the flash. The configuration mode can be set as desired. If the FPGA should start from the external memory after reset, the configuration mode pins ``CFG_MD[3:0]`` set to 0x0 (SPI active).
1. Write to flash using Evaluation Board:
.. code-block:: bash
openFPGALoader -b gatemate_evb_spi -f .cfg.bit
2. Write to flash using Programmer Cable:
.. code-block:: bash
openFPGALoader -b gatemate_pgm_spi -f .cfg.bit
The `offset` parameter can be used to store data at any point in the flash, e.g.:
.. code-block:: bash
openFPGALoader -b gatemate_evb_spi -o .cfg.bit
openFPGALoader-0.13.1/doc/vendors/efinix.rst 0000664 0000000 0000000 00000002352 14735055600 0020572 0 ustar 00root root 0000000 0000000 .. _efinix:
Efinix notes
############
Firant and Xyloni boards (efinix trion T8)
==========================================
``.hex`` file is the default format generated by *Efinity IDE*, so nothing special must be done to generates this file.
*openFPGALoader* supports only active mode (SPI) (*JTAG* is WIP).
hex file load
-------------
.. code-block:: bash
openFPGALoader -b fireant /somewhere/project/outflow/*.hex
or, for xyloni board
.. code-block:: bash
openFPGALoader -b xyloni_spi /somewhere/project/outflow/*.hex
Since openFPGALoader access the flash directly in SPI mode the ``-b fireant``, ``-b xyloni_spi`` is required (no
autodetection possible).
Trion and Titanium JTAG usage
==========================================
*openFPGALoader* supports loading to RAM and SPI Flash with JTAG
Tested with J-Link BASE
bin file load
-------------
.. code-block:: bash
openFPGALoader --cable jlink_base -m /somewhere/project/outflow/*.bin
hex file flash
-------------
Example for ti60f225.
NOTE: JTAG chains with more than one device (eg --index-chain) are currently not supported for writing to SPI flash
.. code-block:: bash
openFPGALoader --cable jlink_base --fpga-part ti60f225 -f /somewhere/project/outflow/*.hex openFPGALoader-0.13.1/doc/vendors/gowin.rst 0000664 0000000 0000000 00000003346 14735055600 0020437 0 ustar 00root root 0000000 0000000 .. _gowin:
Gowin notes
###########
GOWIN GW1N
==========
.. NOTE::
* Trenz TEC0117
* Sipeed Tang Nano
* Sipeed Tang Nano 4K
* Honeycomb
* RUNBER
``.fs`` file is the default format generated by *Gowin IDE*, so nothing special must be done to generates this file.
Since the same file is used for SRAM and Flash a CLI argument is used to specify the destination.
Flash SRAM
----------
with ``-m``:
.. code-block:: bash
openFPGALoader -m -b BOARD_NAME impl/pnr/*.fs
where ``BOARD_NAME`` is:
* ``tec0117``
* ``tangnano``
* ``tangnano1k``
* ``tangnano4k``
* ``tangnano9k``
* ``tangnano20k``
* ``tangprimer20k``
* ``runber``
Flash
-----
.. ATTENTION::
Only with Trenz TEC0117 and runber.
with ``-f``, file load:
.. code-block:: bash
openFPGALoader -f -b BOARD_NAME impl/pnr/*.fs
where ``BOARD_NAME`` is:
* ``tec0117``
* ``runber``
It's possible to flash external SPI Flash (connected to MSPI) in bscan mode by using ``--external-flash`` instead of
``-f``.
.. NOTE::
Gowin's FPGA may fails to be detected if **JTAGSEL_N** (pin 08 for *GW1N-4K*) is used as a GPIO.
To recover you have to pull down this pin (before power up) to recover JTAG interface (*UG292 - JTAGSELL_N section*).
User Flash
----------
.. ATTENTION::
User Flash support is based on reverse engineering of the JTAG protocol. This functionality should be considered
experimental as it hasn't been thoroughly tested, and may in some circumstances destroy your device.
Gowin FPGA come with extra flash space that can be read and written from the programmable logic ("User Flash"). This
flash section can also be programmed via the JTAG interface:
.. code-block:: bash
openFPGALoader --write-flash /path/to/bitstream.fs --user-flash /path/to/flash.bin
openFPGALoader-0.13.1/doc/vendors/intel.rst 0000664 0000000 0000000 00000004473 14735055600 0020431 0 ustar 00root root 0000000 0000000 .. _intel:
Intel notes
###########
Intel/Altera
============
.. NOTE::
* CYC1000
* C10LP-RefKit
* DE0
* de0nano
Loading a bitstream
-------------------
SVF and RBF files are supported.
``sof`` to ``svf`` generation:
.. code-block:: bash
quartus_cpf -c -q 12.0MHz -g 3.3 -n p project_name.sof project_name.svf
``sof`` to ``rbf`` generation:
.. code-block:: bash
quartus_cpf --option=bitstream_compression=off -c project_name.sof project_name.rbf
.. WARNING::
As mentioned in ``cyclone`` handbooks, real-time decompression is not supported by FPGA in JTAG mode.
Keep in mind to disable this option.
You can have Quartus automatically generate SVF and RBF files by adding these lines to the ``qsf`` file, or include them in a ``tcl`` file in FuseSoC
.. code-block::
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name GENERATE_SVF_FILE ON
file load:
.. code-block:: bash
openFPGALoader -b boardname project_name.svf
# or
openFPGALoader -b boardname project_name.rbf
with ``boardname`` = ``de0``, ``cyc1000``, ``c10lp-refkit``, ``de0nano``, ``de0nanoSoc`` or ``qmtechCycloneV``.
SPI flash
---------
RPD and RBF are supported. POF is only supported for MAX10 (internal flash).
``pof`` to ``rpd``:
.. code-block:: bash
quartus_cpf -c project_name.pof project_name.rpd
``sof`` to ``rpd``:
.. code-block:: bash
# CYC1000
quartus_cpf -o auto_create_rpd=on -c -d EPCQ16A -s 10CL025YU256C8G project_name.svf project_name.jic
# C10LP-RefKit
quartus_cpf -o auto_create_rpd=on -c -d EPCQ16A -s 10CL055YU484C8G project_name.svf project_name.jic
file load:
.. code-block:: bash
openFPGALoader -b boardname -r project_name_auto.rpd
# or
openFPGALoader -b boardname -r project_name.rbf
with ``boardname`` = ``cyc1000``, ``c10lp-refkit``.
MAX10:
.. code-block:: bash
openFPGALoader -b boardname project_name_auto.pof
Intel/Altera (Old Boards)
=========================
.. NOTE::
* Cyclone II (FPGA) (Tested OK: EP2C5T144C8N)
* Max II (CPLD) (Tested OK: EPM240T100C5N)
Loading a Serial Vector Format (.svf)
-------------------------------------
SVF files are supported.
To load the file:
.. code-block:: bash
openFPGALoader -c usb-blaster project_name.svf
openFPGALoader-0.13.1/doc/vendors/lattice.rst 0000664 0000000 0000000 00000004133 14735055600 0020734 0 ustar 00root root 0000000 0000000 .. _lattice:
Lattice notes
#############
MachXO2/MachXO3
===============
Flash memory
------------
``.jed`` file is the default format generated by *Lattice Diamond*, so nothing special must be done to generates this
file.
File load:
.. code-block:: bash
openFPGALoader [-b yourboard] [--flash-sector CFG0] impl1/*.jed
where ``yourboard`` may be:
* ``machX02EVN``
* ``machX03EVN``
* ``machXO3SK``
and where ``--flash-sector CFG0`` is needed for the MachXO3D Breakout Board.
``.bit`` may also be used for *machXO2*
SRAM
----
To generates ``.bit`` file *Bitstream file* must be checked under *Exports Files* in *Lattice Diamond* left panel.
File load:
.. code-block:: bash
openFPGALoader [-b yourboard] impl1/*.bit
where ``yourboard`` may be:
* ``machX02EVN``
* ``machX03EVN``
* ``machXO3SK``
iCE40
=====
``.bin`` is the default format generated by *nextpnr*, so nothing special must be done.
Since most ice40 boards uses the same pinout between *FTDI* and *SPI flash* a generic *ice40_generic* board is provided.
For the specific case of the *iCE40HXXK-EVB* where no onboard programmer is present, please use this:
============= ===============
FTDI iCE40HXXK-EVB
============= ===============
SI (ADBUS1) Pin 8
SCK (ADBUS0) Pin 9
SO (ADBUS2) Pin 7
CS (ABDUS4) Pin 10
RST (ADBUS6 Pin 6
DONE (ADBUS7) Pin 5
============= ===============
Bin file load:
.. code-block:: bash
openFPGALoader -b ice40_generic /somewhere/*.bin
Since it's a direct access to the flash (SPI) the ``-b`` option is required.
ECP5/Crosslink-NX
=================
SRAM
----
.. code-block:: bash
openFPGALoader [-b yourBoard] [-c yourCable] -m project_name/*.bit
.. HINT::
By default, openFPGALoader loads bitstream in memory, so the ``-m`` argument is optional.
SPI Flash
---------
BIT:
.. code-block:: bash
openFPGALoader [-b yourBoard] [-c yourCable] -f project_name/*.bit # or *.bin
MCS:
To generate ``.mcs`` file *PROM File* must be checked under *Exports Files* in *Lattice Diamond* left panel.
.. code-block:: bash
openFPGALoader [-b yourBoard] [-c yourCable] project_name/*.mcs
openFPGALoader-0.13.1/doc/vendors/xilinx.rst 0000664 0000000 0000000 00000010420 14735055600 0020616 0 ustar 00root root 0000000 0000000 .. _xilinx:
Xilinx notes
############
To simplify further explanations, we consider the project is generated in the current directory.
.. NOTE::
1. Spartan Edge Accelerator Board has only pinheader, so the cable must be provided
2. A *JTAG* <-> *SPI* bridge (used to write bitstream in FLASH) is available for some device, see
:ghsrc:`spiOverJtag ` to check if your model is supported.
3. Board provides the device/package model, but if the targeted board is not officially supported but the FPGA yes,
you can use ``--fpga-part`` to provide the model.
4. With spartan3, the flash is an independent JTAG device.
User has to use ``--index-chain`` to access FPGA (RAM only) or flash (write/read only).
.. WARNING::
``*.bin`` may be loaded in memory or in flash, but this extension is a classic extension for CPU firmware and, by
default, *openFPGALoader* loads file in memory.
Double check ``-m`` / ``-f`` when you want to use a firmware for a softcore (or anything, other than a bitstream) to
write somewhere in the FLASH device).
``.bit`` file is the default format generated by *vivado*, so nothing special task must be done to generate this
bitstream.
``.bin`` is not, by default, produced.
To have access to this file you need to configure the tool:
- GUI: *Tools* -> *Settings* -> *Bitstreams* -> check ``-bin_file``.
- TCL: append your *TCL* file with ``set_property STEPS.WRITE_BITSTREAM.ARGS.BIN_FILE true [get_runs impl_1]``.
.. WARNING::
For alchitry board the bitstream must be configured with a buswidth of 1 or 2.
Quad mode can't be used with alchitry's FLASH.
.. WARNING::
For boards based on a Zynq (7000 or MPSoC), boot mode must be configured for JTAG (for Zedboard JP7->JP11 must be
to GND).
Loading a bitstream
===================
``.bit`` and ``.bin`` are allowed to be loaded in memory.
File load:
.. code-block:: bash
openFPGALoader [-m] -b arty *.runs/impl_1/*.bit (or *.bin)
or
.. code-block:: bash
openFPGALoader [-m] -b spartanEdgeAccelBoard -c digilent_hs2 *.runs/impl_1/*.bit (or *.bin)
SPI flash
---------
.. NOTE::
``.bit``, ``.bin``, and ``.mcs`` are supported for FLASH.
``.mcs`` must be generated through Vivado with a tcl script like:
.. WARNING::
For boards based on Zynq device (7000 and MPSoC) SPI flash is not accessible through PL.
.. code-block:: tcl
set project [lindex $argv 0]
set bitfile "${project}.runs/impl_1/${project}.bit"
set mcsfile "${project}.runs/impl_1/${project}.mcs"
write_cfgmem -format mcs -interface spix4 -size 16 \
-loadbit "up 0x0 $bitfile" -loaddata "" \
-file $mcsfile -force
.. NOTE::
``-interface spix4`` and ``-size 16`` depends on SPI flash capability and size.
The tcl script is used with:
.. code-block:: bash
vivado -nolog -nojournal -mode batch -source script.tcl -tclargs myproject
File load:
.. code-block:: bash
openFPGALoader [--fpga-part xxxx] -f -b arty *.runs/impl_1/*.mcs (or .bit / .bin)
.. NOTE::
``-f`` is required to write bitstream (without them ``.bit`` and ``.bin`` are loaded in memory).
.. NOTE::
``--fpga-part`` is only required if this information is not provided at ``board.hpp`` level or if the board is not
officially supported.
device/package format is something like xc7a35tcsg324 (arty model).
See :ghsrc:`src/board.hpp `, or :ghsrc:`spiOverJtag ` directory for examples.
Some boards with UltraScale FPGAs, like the VCU118 and KCU16, support the SPIx8 (Dual Quad SPI) configuration.
In this case, the ``spix8`` option ``write_cfgmem`` on the above example can be used to generate two ``.mcs`` files,
to fit bigger designs or for faster programming. Only ``.mcs`` files can be used to program the FPGA in this case.
In this case, to load the two ``.mcs`` files:
.. code-block:: bash
openFPGALoader --board vcu118 -f --target-flash both --bitstream *.runs/impl_1/*_primary.mcs --secondary-bitstream *.runs/impl_1/*_secondary.mcs
On these boards, each SPI flash can be programmed independently with the ``--target-flash`` option.
The default target is the ``primary`` flash.
For example, to program only the secondary flash with arbitrary data not related to FPGA configuration:
.. code-block:: bash
openFPGALoader --board vcu118 -f --target-flash secondary --bitstream arbitrary_data
openFPGALoader-0.13.1/scripts/ 0000775 0000000 0000000 00000000000 14735055600 0016016 5 ustar 00root root 0000000 0000000 openFPGALoader-0.13.1/scripts/msys2/ 0000775 0000000 0000000 00000000000 14735055600 0017073 5 ustar 00root root 0000000 0000000 openFPGALoader-0.13.1/scripts/msys2/PKGBUILD 0000664 0000000 0000000 00000001723 14735055600 0020222 0 ustar 00root root 0000000 0000000 _realname=openFPGALoader
pkgbase=mingw-w64-${_realname}
pkgname="${MINGW_PACKAGE_PREFIX}-${_realname}"
pkgver=ci
pkgrel=1
pkgdesc="openFPGALoader: universal utility for programming FPGA (mingw-w64)"
arch=('any')
url="https://github.com/trabucayre/openFPGALoader"
license=('Apache-2.0')
depends=(
"${MINGW_PACKAGE_PREFIX}-libftdi"
"${MINGW_PACKAGE_PREFIX}-zlib"
)
makedepends=(
"${MINGW_PACKAGE_PREFIX}-cc"
"${MINGW_PACKAGE_PREFIX}-cmake"
)
source=()
sha256sums=()
build() {
cd "${srcdir}"
mkdir build
cd build
MSYS2_ARG_CONV_EXCL=- cmake \
-G "MSYS Makefiles" \
-DCMAKE_INSTALL_PREFIX="${MINGW_PREFIX}" \
../../../..
MSYS2_ARG_CONV_EXCL="-DDATA_DIR=" cmake --build .
}
check() {
"${srcdir}"/build/openFPGALoader.exe --help
}
package() {
cd "${srcdir}"/build
make DESTDIR="${pkgdir}" install
_licenses="${pkgdir}${MINGW_PREFIX}/share/licenses/${_realname}"
mkdir -p "${_licenses}"
install -m 644 ../../../../LICENSE "${_licenses}"
}
openFPGALoader-0.13.1/spiOverJtag/ 0000775 0000000 0000000 00000000000 14735055600 0016564 5 ustar 00root root 0000000 0000000 openFPGALoader-0.13.1/spiOverJtag/.gitignore 0000664 0000000 0000000 00000000022 14735055600 0020546 0 ustar 00root root 0000000 0000000 tmp_*
*.bit
*.rbf
openFPGALoader-0.13.1/spiOverJtag/Makefile 0000664 0000000 0000000 00000003652 14735055600 0020232 0 ustar 00root root 0000000 0000000 XILINX_PARTS := xc3s500evq100 \
xc6slx9tqg144 xc6slx9csg324 \
xc6slx16ftg256 xc6slx16csg324 xc6slx25csg324 xc6slx45csg324 xc6slx100fgg484 \
xc6slx25tcsg324 xc6slx45tfgg484 xc6slx150tfgg484 xc6slx150tcsg484 \
xc6vlx130tff784 \
xc7a15tcpg236 \
xc7a25tcpg238 xc7a25tcsg325 \
xc7a35tcpg236 xc7a35tcsg324 xc7a35tftg256 xc7a35tfgg484 \
xc7a50tcsg324 xc7a50tfgg484 xc7a50tcpg236 xc7a75tfgg484 \
xc7a100tcsg324 xc7a100tfgg484 xc7a100tfgg676\
xc7a200tsbg484 xc7a200tfbg484 xc7a200tfbg676\
xc7s6ftgb196 xc7s25csga225 xc7s25csga324 xc7s50csga324 \
xc7k70tfbg484 xc7k70tfbg676 \
xc7k160tffg676 \
xc7k325tffg676 xc7k325tffg900 \
xc7k420tffg901 \
xcku3p-ffva676 \
xc7vx330tffg1157 \
xcku040-ffva1156 xcku060-ffva1156 \
xcku5p-ffvb676 \
xcvu9p-flga2104 xcvu37p-fsvh2892
XILINX_BIT_FILES := $(addsuffix .bit.gz,$(addprefix spiOverJtag_, $(XILINX_PARTS)))
ALTERA_PARTS := 10cl025256 10cl016484 10cl055484 \
ep4ce622 ep4ce1017 ep4ce2217 ep4ce1523 ep4ce11523 ep4cgx15027 5ce215 5ce223 5ce423 5ce523 5ce927 5sgsd5
ALTERA_BIT_FILES := $(addsuffix .rbf.gz, $(addprefix spiOverJtag_, $(ALTERA_PARTS)))
EFINIX_PARTS := t8f81 t13f256 ti180j484
EFINIX_BIT_FILES := $(addsuffix .bit.gz, $(addprefix spiOverJtag_efinix_, $(EFINIX_PARTS)))
BIT_FILES := $(ALTERA_BIT_FILES) $(EFINIX_BIT_FILES) $(XILINX_BIT_FILES)
all: $(BIT_FILES)
$(EFINIX_BIT_FILES) : spiOverJtag_efinix_%.bit.gz : tmp_efinix_%/efinix_spiOverJtag.bit
gzip -9 -c $< > $@
tmp_efinix_%/efinix_spiOverJtag.bit : efinix_spiOverJtag.v
./efinix_build.py --device $*
$(XILINX_BIT_FILES) : spiOverJtag_%.bit.gz : tmp_%/spiOverJtag.bit
gzip -9 -c $< > $@
tmp_%/spiOverJtag.bit : xilinx_spiOverJtag.v
./build.py $*
$(ALTERA_BIT_FILES): spiOverJtag_%.rbf.gz: tmp_%/spiOverJtag.rbf
gzip -9 -c $< > $@
tmp_%/spiOverJtag.rbf: tmp_%/spiOverJtag.sof
quartus_cpf --option=bitstream_compression=off -c $< $@
tmp_%/spiOverJtag.sof: altera_spiOverJtag.v
./build.py $*
clean:
-rm -rf tmp_* *.jou *.log .Xil
openFPGALoader-0.13.1/spiOverJtag/altera_spiOverJtag.sdc 0000664 0000000 0000000 00000000637 14735055600 0023052 0 ustar 00root root 0000000 0000000 #*********************
# Create Clock
#*********************
set jtag_t_period 83
create_clock -name {altera_reserved_tck} -period 83ns [get_ports {altera_reserved_tck}]
set_clock_groups -asynchronous -group {altera_reserved_tck}
#*********************
# Create Generated Clock
#*********************
derive_pll_clocks
#*********************
# Set Clock Uncertainty
#*********************
derive_clock_uncertainty
openFPGALoader-0.13.1/spiOverJtag/altera_spiOverJtag.v 0000664 0000000 0000000 00000003713 14735055600 0022544 0 ustar 00root root 0000000 0000000 module spiOverJtag ();
wire tdi, tdo, tck;
wire [8:0] ir_in;
wire vs_cdr, vs_sdr, vs_uir;
sld_virtual_jtag #(.sld_auto_instance_index("YES"),
.sld_instance_index(0), .sld_ir_width (9)
) jtag_ctrl (
.tdi(tdi), .tdo(tdo), .tck(tck), .ir_in(ir_in),
.virtual_state_cdr(vs_cdr), .virtual_state_sdr(vs_sdr),
.virtual_state_uir(vs_uir));
wire spi_csn, spi_si, spi_clk, spi_so;
altserial_flash_loader #(
`ifdef cyclone10lp
.INTENDED_DEVICE_FAMILY ("Cyclone 10 LP"),
`elsif cycloneive
.INTENDED_DEVICE_FAMILY ("Cyclone IV E"),
`elsif cyclonev
.INTENDED_DEVICE_FAMILY ("Cyclone V"),
`elsif stratixv
.INTENDED_DEVICE_FAMILY ("Stratix V"),
`endif
.ENHANCED_MODE (1),
.ENABLE_SHARED_ACCESS ("ON"),
.ENABLE_QUAD_SPI_SUPPORT (0),
.NCSO_WIDTH (1)
) serial_flash_loader (
.dclkin(spi_clk), .scein(spi_csn), .sdoin(spi_si), .data0out(spi_so),
.data_in(), .data_oe(), .data_out(), .noe(1'b0),
.asmi_access_granted (1'b1), .asmi_access_request ()
);
/* vs_uir is used to send
* command to the flash
* and number of byte to generate
*/
reg [7:0] spi_cmd_s;
reg sdr_d, cdr_d;
always @(negedge tck) begin
if (vs_uir) begin
spi_cmd_s <= ir_in[7:0];
end
/* virtual state are updated on rising edge
* and sampled at falling edge
* => latch on negedge to use after on falling
*/
sdr_d <= vs_sdr;
cdr_d <= vs_cdr;
end
/* data in vs_sdr must be sampled on
* rising edge but use state dealyed by
* 1/2 clock cycle
*/
reg [7:0] test_s;
reg tdi_d0_s;
always @(posedge tck) begin
if (cdr_d) begin
test_s <= spi_cmd_s;
end else if (sdr_d) begin
test_s <= {tdi, test_s[7:1]};
end
tdi_d0_s <= tdi;
end
reg spi_si_d;
always @(negedge tck) begin
if (vs_sdr | sdr_d)
spi_si_d <= test_s[0];
end
assign spi_csn = !sdr_d;
assign spi_si = (sdr_d) ? spi_si_d : 1'b0;
assign spi_clk = sdr_d ? tck : 1'b0;
assign tdo = sdr_d ? spi_so : tdi_d0_s;
endmodule
openFPGALoader-0.13.1/spiOverJtag/build.py 0000775 0000000 0000000 00000021464 14735055600 0020247 0 ustar 00root root 0000000 0000000 #!/usr/bin/env python3
from edalize.edatool import get_edatool
import os
if len(os.sys.argv) != 2:
print("missing board param")
os.sys.exit()
part = os.sys.argv[1]
build_dir="tmp_" + part
if not os.path.isdir(build_dir):
try:
os.mkdir(build_dir)
except OSError:
print ("Creation of the directory %s failed" % build_dir)
else:
print ("Successfully created the directory %s " % build_dir)
currDir = os.path.abspath(os.path.curdir) + '/'
files = []
parameters = {}
subpart = part[0:4].lower()
if subpart == '10cl':
family = "Cyclone 10 LP"
tool = "quartus"
elif subpart == 'ep4c':
family = "Cyclone IV E"
tool = "quartus"
elif subpart[0:2] == '5c':
family = "Cyclone V"
tool = "quartus"
files.append({'name': currDir + 'constr_cycloneV.tcl',
'file_type': 'tclSource'})
elif subpart[0:2] == '5s':
family = "Stratix V"
tool = "quartus"
files.append({'name': currDir + 'constr_cycloneV.tcl',
'file_type': 'tclSource'})
elif subpart == "xc7a":
family = "Artix"
tool = "vivado"
elif subpart == "xc7v":
family = "Virtex 7"
tool = "vivado"
elif subpart == "xc7k":
device_size = int(part.split('k')[1].split('t')[0])
if device_size <= 160:
family = "Kintex 7"
tool = "vivado"
else:
family = "Kintex7"
tool = "ise"
speed = -2
elif subpart == "xc7s":
family = "Spartan 7"
tool = "vivado"
elif subpart == "xc6s":
family = "Spartan6"
tool = "ise"
speed = -3
elif subpart == "xc3s":
family = "Spartan3E"
tool = "ise"
speed = -4
elif subpart == "xc6v":
family = "Virtex6"
tool = "ise"
speed = -1
elif subpart in ["xcvu", "xcku"]:
family = "Xilinx UltraScale"
tool = "vivado"
else:
print("Error: unknown device")
os.sys.exit()
if tool in ["ise", "vivado"]:
pkg_name = {
"xc3s500evq100" : "xc3s_vq100",
"xc6slx9tqg144" : "xc6s_tqg144",
"xc6slx9csg324" : "xc6s_csg324",
"xc6slx16ftg256" : "xc6s_ftg256",
"xc6slx16csg324" : "xc6s_csg324",
"xc6slx25csg324" : "xc6s_csg324",
"xc6slx25tcsg324" : "xc6s_t_csg324",
"xc6slx45csg324" : "xc6s_csg324",
"xc6slx45tfgg484" : "xc6s_t_fgg484",
"xc6slx100fgg484" : "xc6s_fgg484",
"xc6slx150tcsg484" : "xc6s_csg484",
"xc6slx150tfgg484" : "xc6s_t_fgg484",
"xc6vlx130tff784" : "xc6v_ff784",
"xc7a15tcpg236" : "xc7a_cpg236",
"xc7a25tcpg238" : "xc7a_cpg238",
"xc7a25tcsg325" : "xc7a_csg325",
"xc7a35tcpg236" : "xc7a_cpg236",
"xc7a35tcsg324" : "xc7a_csg324",
"xc7a35tftg256" : "xc7a_ftg256",
"xc7a35tfgg484" : "xc7a_fgg484",
"xc7a50tcpg236" : "xc7a_cpg236",
"xc7a50tcsg324" : "xc7a_csg324",
"xc7a50tfgg484" : "xc7a_fgg484",
"xc7a75tfgg484" : "xc7a_fgg484",
"xc7a100tcsg324" : "xc7a_csg324",
"xc7a100tfgg484" : "xc7a_fgg484",
"xc7a100tfgg676" : "xc7a_fgg676",
"xc7a200tsbg484" : "xc7a_sbg484",
"xc7a200tfbg484" : "xc7a_fbg484",
"xc7a200tfbg676" : "xc7a_fbg676",
"xc7k70tfbg484" : "xc7k_fbg484",
"xc7k70tfbg676" : "xc7k_fbg676",
"xc7k160tffg676" : "xc7k_ffg676",
"xc7k325tffg676" : "xc7k_ffg676",
"xc7k325tffg900" : "xc7k_ffg900",
"xc7k420tffg901" : "xc7k_ffg901",
"xc7vx330tffg1157" : "xc7v_ffg1157",
"xc7s6ftgb196" : "xc7s_ftgb196",
"xc7s25csga225" : "xc7s_csga225",
"xc7s25csga324" : "xc7s_csga324",
"xc7s50csga324" : "xc7s_csga324",
"xcku040-ffva1156" : "xcku040_ffva1156",
"xcku060-ffva1156" : "xcku060_ffva1156",
"xcvu9p-flga2104" : "xcvu9p_flga2104",
"xcvu37p-fsvh2892" : "xcvu37p_fsvh2892",
"xcku3p-ffva676" : "xcku3p_ffva676",
"xcku5p-ffvb676" : "xcku5p_ffvb676",
}[part]
if tool == "ise":
cst_type = "UCF"
tool_options = {'family': family,
'device': {
"xc3s500evq100": "xc3s500e",
"xc6slx9tqg144": "xc6slx9",
"xc6slx9csg324": "xc6slx9",
"xc6slx16ftg256": "xc6slx16",
"xc6slx16csg324": "xc6slx16",
"xc6slx25csg324": "xc6slx25",
"xc6slx25tcsg324": "xc6slx25t",
"xc6slx45csg324": "xc6slx45",
"xc6slx45tfgg484": "xc6slx45t",
"xc6slx100fgg484": "xc6slx100",
"xc6slx150tcsg484": "xc6slx150t",
"xc6slx150tfgg484": "xc6slx150t",
"xc6vlx130tff784": "xc6vlx130t",
"xc7k325tffg676": "xc7k325t",
"xc7k325tffg900": "xc7k325t",
"xc7k420tffg901": "xc7k420t",
}[part],
'package': {
"xc3s500evq100": "vq100",
"xc6slx9tqg144": "tqg144",
"xc6slx9csg324": "csg324",
"xc6slx16ftg256": "ftg256",
"xc6slx16csg324": "csg324",
"xc6slx25csg324": "csg324",
"xc6slx25tcsg324": "csg324",
"xc6slx45csg324": "csg324",
"xc6slx45tfgg484": "fgg484",
"xc6slx100fgg484": "fgg484",
"xc6slx150tcsg484": "csg484",
"xc6slx150tfgg484": "fgg484",
"xc6vlx130tff784": "ff784",
"xc7k325tffg676": "ffg676",
"xc7k325tffg900": "ffg900",
"xc7k420tffg901": "ffg901",
}[part],
'speed' : speed
}
else:
cst_type = "xdc"
if family == "Xilinx UltraScale":
if part in ["xcvu9p-flga2104", "xcku5p-ffvb676"]:
tool_options = {'part': part + '-1-e'}
parameters["secondaryflash"]= {
'datatype': 'int',
'paramtype': 'vlogdefine',
'description': 'secondary flash',
'default': 1}
elif part == "xcku3p-ffva676":
tool_options = {'part': part + '-2-e'}
elif part == "xcvu37p-fsvh2892":
tool_options = {'part': part + '-2L-e'}
elif part in ["xcku040-ffva1156", "xcku060-ffva1156"]:
tool_options = {'part': part + '-2-e'}
parameters["secondaryflash"]= {
'datatype': 'int',
'paramtype': 'vlogdefine',
'description': 'secondary flash',
'default': 1}
else:
tool_options = {'part': part + '-1'}
cst_file = currDir + "constr_" + pkg_name + "." + cst_type.lower()
files.append({'name': currDir + 'xilinx_spiOverJtag.v',
'file_type': 'verilogSource'})
files.append({'name': cst_file, 'file_type': cst_type})
else:
full_part = {
"10cl016484" : "10CL016YU484C8G",
"10cl025256" : "10CL025YU256C8G",
"10cl055484" : "10CL055YU484C8G",
"ep4cgx15027": "EP4CGX150DF27I7",
"ep4ce11523" : "EP4CE115F23C7",
"ep4ce2217" : "EP4CE22F17C6",
"ep4ce1523" : "EP4CE15F23C8",
"ep4ce1017" : "EP4CE10F17C8",
"ep4ce622" : "EP4CE6E22C8",
"5ce215" : "5CEBA2U15C8",
"5ce223" : "5CEFA2F23I7",
"5ce523" : "5CEFA5F23I7",
"5ce423" : "5CEBA4F23C8",
"5ce927" : "5CEBA9F27C7",
"5cse423" : "5CSEMA4U23C6",
"5cse623" : "5CSEBA6U23I7",
"5sgsd5" : "5SGSMD5K2F40I3"}[part]
files.append({'name': currDir + 'altera_spiOverJtag.v',
'file_type': 'verilogSource'})
files.append({'name': currDir + 'altera_spiOverJtag.sdc',
'file_type': 'SDC'})
tool_options = {'device': full_part, 'family':family}
parameters[family.lower().replace(' ', '')]= {
'datatype': 'int',
'paramtype': 'vlogdefine',
'description': 'fpga family',
'default': 1}
edam = {'name' : "spiOverJtag",
'files': files,
'tool_options': {tool: tool_options},
'parameters': parameters,
'toplevel' : 'spiOverJtag',
}
backend = get_edatool(tool)(edam=edam, work_root=build_dir)
backend.configure()
backend.build()
if tool == "vivado":
import shutil
shutil.copy("tmp_" + part + "/spiOverJtag.runs/impl_1/spiOverJtag.bit",
"tmp_" + part);
openFPGALoader-0.13.1/spiOverJtag/constr_cycloneV.tcl 0000664 0000000 0000000 00000000303 14735055600 0022436 0 ustar 00root root 0000000 0000000 set_global_assignment -name ENABLE_INIT_DONE_OUTPUT ON
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4"
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION ON
openFPGALoader-0.13.1/spiOverJtag/constr_xc3s_vq100.ucf 0000664 0000000 0000000 00000000311 14735055600 0022455 0 ustar 00root root 0000000 0000000 NET "sdi_dq0" LOC = P27 | IOSTANDARD = LVCMOS33;
NET "sdo_dq1" LOC = P44 | IOSTANDARD = LVCMOS33;
NET "csn" LOC = P24 | IOSTANDARD = LVCMOS33;
NET "sck" LOC = P50 | IOSTANDARD = LVCMOS33;
openFPGALoader-0.13.1/spiOverJtag/constr_xc6s_csg324.ucf 0000664 0000000 0000000 00000000504 14735055600 0022622 0 ustar 00root root 0000000 0000000 CONFIG VCCAUX = "2.5";
NET "sdi_dq0" LOC = T13 | IOSTANDARD = LVCMOS33;
NET "sdo_dq1" LOC = R13 | IOSTANDARD = LVCMOS33;
NET "wpn_dq2" LOC = T14 | IOSTANDARD = LVCMOS33;
NET "hldn_dq3" LOC = V14 | IOSTANDARD = LVCMOS33;
NET "csn" LOC = V3 | IOSTANDARD = LVCMOS33;
NET "sck" LOC = R15 | IOSTANDARD = LVCMOS33;
openFPGALoader-0.13.1/spiOverJtag/constr_xc6s_csg484.ucf 0000664 0000000 0000000 00000000512 14735055600 0022630 0 ustar 00root root 0000000 0000000 CONFIG VCCAUX = "2.5";
NET "sdi_dq0" LOC = AB17 | IOSTANDARD = LVCMOS33;
NET "sdo_dq1" LOC = Y17 | IOSTANDARD = LVCMOS33;
NET "wpn_dq2" LOC = V13 | IOSTANDARD = LVCMOS33;
NET "hldn_dq3" LOC = W13 | IOSTANDARD = LVCMOS33;
NET "csn" LOC = AB5 | IOSTANDARD = LVCMOS33;
NET "sck" LOC = W17 | IOSTANDARD = LVCMOS33;
openFPGALoader-0.13.1/spiOverJtag/constr_xc6s_fgg484.ucf 0000664 0000000 0000000 00000000512 14735055600 0022617 0 ustar 00root root 0000000 0000000 CONFIG VCCAUX = "2.5";
NET "sdi_dq0" LOC = AB20 | IOSTANDARD = LVCMOS25;
NET "sdo_dq1" LOC = AA20 | IOSTANDARD = LVCMOS25;
NET "wpn_dq2" LOC = U14 | IOSTANDARD = LVCMOS25;
NET "hldn_dq3" LOC = U13 | IOSTANDARD = LVCMOS25;
NET "csn" LOC = T5 | IOSTANDARD = LVCMOS25;
NET "sck" LOC = Y21 | IOSTANDARD = LVCMOS25;
openFPGALoader-0.13.1/spiOverJtag/constr_xc6s_ftg256.ucf 0000664 0000000 0000000 00000000504 14735055600 0022632 0 ustar 00root root 0000000 0000000 CONFIG VCCAUX = "2.5";
NET "sdi_dq0" LOC = T10 | IOSTANDARD = LVCMOS33;
NET "sdo_dq1" LOC = P10 | IOSTANDARD = LVCMOS33;
NET "wpn_dq2" LOC = N12 | IOSTANDARD = LVCMOS33;
NET "hldn_dq3" LOC = P12 | IOSTANDARD = LVCMOS33;
NET "csn" LOC = T3 | IOSTANDARD = LVCMOS33;
NET "sck" LOC = R11 | IOSTANDARD = LVCMOS33;
openFPGALoader-0.13.1/spiOverJtag/constr_xc6s_t_csg324.ucf 0000664 0000000 0000000 00000000625 14735055600 0023151 0 ustar 00root root 0000000 0000000 CONFIG VCCAUX = "2.5";
NET "sdi_dq0" LOC = T13 | IOSTANDARD = LVCMOS25;
NET "sdo_dq1" LOC = R13 | IOSTANDARD = LVCMOS25;
NET "wpn_dq2" LOC = T14 | IOSTANDARD = LVCMOS25;
NET "hldn_dq3" LOC = V14 | IOSTANDARD = LVCMOS25;
NET "csn" LOC = V3 | IOSTANDARD = LVCMOS25;
NET "sck" LOC = R15 | IOSTANDARD = LVCMOS25;
NET "sck" TNM_NET = "PRDsck";
TIMESPEC "TSsck" = PERIOD "PRDsck" 6 ns HIGH 50%;
openFPGALoader-0.13.1/spiOverJtag/constr_xc6s_t_fgg484.ucf 0000664 0000000 0000000 00000000512 14735055600 0023142 0 ustar 00root root 0000000 0000000 CONFIG VCCAUX = "2.5";
NET "sdi_dq0" LOC = AB20 | IOSTANDARD = LVCMOS25;
NET "sdo_dq1" LOC = AA20 | IOSTANDARD = LVCMOS25;
NET "wpn_dq2" LOC = R13 | IOSTANDARD = LVCMOS25;
NET "hldn_dq3" LOC = T14 | IOSTANDARD = LVCMOS25;
NET "csn" LOC = AA3 | IOSTANDARD = LVCMOS25;
NET "sck" LOC = Y20 | IOSTANDARD = LVCMOS25;
openFPGALoader-0.13.1/spiOverJtag/constr_xc6s_tqg144.ucf 0000664 0000000 0000000 00000000504 14735055600 0022641 0 ustar 00root root 0000000 0000000 CONFIG VCCAUX = "2.5";
NET "sdi_dq0" LOC = P64 | IOSTANDARD = LVCMOS33;
NET "sdo_dq1" LOC = P65 | IOSTANDARD = LVCMOS33;
NET "wpn_dq2" LOC = P62 | IOSTANDARD = LVCMOS33;
NET "hldn_dq3" LOC = P61 | IOSTANDARD = LVCMOS33;
NET "csn" LOC = P38 | IOSTANDARD = LVCMOS33;
NET "sck" LOC = P70 | IOSTANDARD = LVCMOS33;
openFPGALoader-0.13.1/spiOverJtag/constr_xc6v_ff784.ucf 0000664 0000000 0000000 00000000146 14735055600 0022460 0 ustar 00root root 0000000 0000000 NET "sdi_dq0" LOC = AF24 | IOSTANDARD = LVCMOS25;
NET "csn" LOC = AE24 | IOSTANDARD = LVCMOS25;
openFPGALoader-0.13.1/spiOverJtag/constr_xc7a_cpg236.xdc 0000664 0000000 0000000 00000001147 14735055600 0022605 0 ustar 00root root 0000000 0000000 set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS33} [get_ports {csn}];
set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}];
set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}];
set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}];
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}];
openFPGALoader-0.13.1/spiOverJtag/constr_xc7a_cpg238.xdc 0000664 0000000 0000000 00000001150 14735055600 0022601 0 ustar 00root root 0000000 0000000 set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS33} [get_ports {csn}];
set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}];
set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}];
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}];
set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}];
openFPGALoader-0.13.1/spiOverJtag/constr_xc7a_csg324.xdc 0000664 0000000 0000000 00000001147 14735055600 0022606 0 ustar 00root root 0000000 0000000 set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS33} [get_ports {csn}];
set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}];
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}];
set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}];
set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}];
openFPGALoader-0.13.1/spiOverJtag/constr_xc7a_csg325.xdc 0000664 0000000 0000000 00000001150 14735055600 0022601 0 ustar 00root root 0000000 0000000 set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS33} [get_ports {csn}];
set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}];
set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}];
set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}];
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}];
openFPGALoader-0.13.1/spiOverJtag/constr_xc7a_fbg484.xdc 0000664 0000000 0000000 00000001124 14735055600 0022572 0 ustar 00root root 0000000 0000000 set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVTTL} [get_ports {csn}]
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVTTL} [get_ports {sdi_dq0}]
set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVTTL} [get_ports {sdo_dq1}]
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVTTL} [get_ports {wpn_dq2}]
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVTTL} [get_ports {hldn_dq3}]
openFPGALoader-0.13.1/spiOverJtag/constr_xc7a_fbg676.xdc 0000664 0000000 0000000 00000001123 14735055600 0022574 0 ustar 00root root 0000000 0000000 set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVTTL} [get_ports {csn}]
set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVTTL} [get_ports {sdi_dq0}]
set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVTTL} [get_ports {sdo_dq1}]
set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVTTL} [get_ports {wpn_dq2}]
set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVTTL} [get_ports {hldn_dq3}]
openFPGALoader-0.13.1/spiOverJtag/constr_xc7a_fgg484.xdc 0000664 0000000 0000000 00000001026 14735055600 0022600 0 ustar 00root root 0000000 0000000 set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVTTL} [get_ports {csn}]
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVTTL} [get_ports {sdi_dq0}]
set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVTTL} [get_ports {sdo_dq1}]
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVTTL} [get_ports {wpn_dq2}]
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVTTL} [get_ports {hldn_dq3}]
openFPGALoader-0.13.1/spiOverJtag/constr_xc7a_fgg676.xdc 0000664 0000000 0000000 00000001124 14735055600 0022602 0 ustar 00root root 0000000 0000000 set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVTTL} [get_ports {csn}]
set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVTTL} [get_ports {sdi_dq0}]
set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVTTL} [get_ports {sdo_dq1}]
set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVTTL} [get_ports {wpn_dq2}]
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVTTL} [get_ports {hldn_dq3}]
openFPGALoader-0.13.1/spiOverJtag/constr_xc7a_ftg256.xdc 0000664 0000000 0000000 00000001147 14735055600 0022616 0 ustar 00root root 0000000 0000000 set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS33} [get_ports {csn}];
set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}];
set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}];
set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}];
set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}];
openFPGALoader-0.13.1/spiOverJtag/constr_xc7a_sbg384.xdc 0000664 0000000 0000000 00000001043 14735055600 0022606 0 ustar 00root root 0000000 0000000 set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS33} [get_ports {csn}]
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}]
set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}]
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}]
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}] openFPGALoader-0.13.1/spiOverJtag/constr_xc7k_fbg484.ucf 0000664 0000000 0000000 00000000400 14735055600 0022577 0 ustar 00root root 0000000 0000000 NET "csn" LOC = L18 | IOSTANDARD = LVCMOS33;
NET "sdi_dq0" LOC = H18 | IOSTANDARD = LVCMOS33;
NET "sdo_dq1" LOC = H19 | IOSTANDARD = LVCMOS33;
NET "wpn_dq2" LOC = G18 | IOSTANDARD = LVCMOS33;
NET "hldn_dq3" LOC = F19 | IOSTANDARD = LVCMOS33;
openFPGALoader-0.13.1/spiOverJtag/constr_xc7k_fbg484.xdc 0000664 0000000 0000000 00000001026 14735055600 0022605 0 ustar 00root root 0000000 0000000 set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVTTL} [get_ports {csn}]
set_property -dict {PACKAGE_PIN H18 IOSTANDARD LVTTL} [get_ports {sdi_dq0}]
set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVTTL} [get_ports {sdo_dq1}]
set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVTTL} [get_ports {wpn_dq2}]
set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVTTL} [get_ports {hldn_dq3}]
openFPGALoader-0.13.1/spiOverJtag/constr_xc7k_fbg676.xdc 0000664 0000000 0000000 00000001026 14735055600 0022610 0 ustar 00root root 0000000 0000000 set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
set_property -dict {PACKAGE_PIN C23 IOSTANDARD LVTTL} [get_ports {csn}]
set_property -dict {PACKAGE_PIN B24 IOSTANDARD LVTTL} [get_ports {sdi_dq0}]
set_property -dict {PACKAGE_PIN A25 IOSTANDARD LVTTL} [get_ports {sdo_dq1}]
set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVTTL} [get_ports {wpn_dq2}]
set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVTTL} [get_ports {hldn_dq3}]
openFPGALoader-0.13.1/spiOverJtag/constr_xc7k_ffg676.ucf 0000664 0000000 0000000 00000000400 14735055600 0022606 0 ustar 00root root 0000000 0000000 NET "csn" LOC = C23 | IOSTANDARD = LVCMOS33;
NET "sdi_dq0" LOC = B24 | IOSTANDARD = LVCMOS33;
NET "sdo_dq1" LOC = A25 | IOSTANDARD = LVCMOS33;
NET "wpn_dq2" LOC = B22 | IOSTANDARD = LVCMOS33;
NET "hldn_dq3" LOC = A22 | IOSTANDARD = LVCMOS33;
openFPGALoader-0.13.1/spiOverJtag/constr_xc7k_ffg676.xdc 0000664 0000000 0000000 00000001221 14735055600 0022611 0 ustar 00root root 0000000 0000000 set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
set_property -dict {PACKAGE_PIN C23 IOSTANDARD LVTTL} [get_ports {csn}]
set_property -dict {PACKAGE_PIN B24 IOSTANDARD LVTTL} [get_ports {sdi_dq0}]
set_property -dict {PACKAGE_PIN A25 IOSTANDARD LVTTL} [get_ports {sdo_dq1}]
set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVTTL} [get_ports {wpn_dq2}]
set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVTTL} [get_ports {hldn_dq3}]
openFPGALoader-0.13.1/spiOverJtag/constr_xc7k_ffg900.ucf 0000664 0000000 0000000 00000000400 14735055600 0022574 0 ustar 00root root 0000000 0000000 NET "csn" LOC = U19 | IOSTANDARD = LVCMOS33;
NET "sdi_dq0" LOC = P24 | IOSTANDARD = LVCMOS33;
NET "sdo_dq1" LOC = R25 | IOSTANDARD = LVCMOS33;
NET "wpn_dq2" LOC = R20 | IOSTANDARD = LVCMOS33;
NET "hldn_dq3" LOC = R21 | IOSTANDARD = LVCMOS33;
openFPGALoader-0.13.1/spiOverJtag/constr_xc7k_ffg900.xdc 0000664 0000000 0000000 00000001221 14735055600 0022577 0 ustar 00root root 0000000 0000000 set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVTTL} [get_ports {csn}]
set_property -dict {PACKAGE_PIN P24 IOSTANDARD LVTTL} [get_ports {sdi_dq0}]
set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVTTL} [get_ports {sdo_dq1}]
set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVTTL} [get_ports {wpn_dq2}]
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVTTL} [get_ports {hldn_dq3}]
openFPGALoader-0.13.1/spiOverJtag/constr_xc7k_ffg901.ucf 0000664 0000000 0000000 00000000400 14735055600 0022575 0 ustar 00root root 0000000 0000000 NET "csn" LOC = V26 | IOSTANDARD = LVCMOS33;
NET "sdi_dq0" LOC = R30 | IOSTANDARD = LVCMOS33;
NET "sdo_dq1" LOC = T30 | IOSTANDARD = LVCMOS33;
NET "wpn_dq2" LOC = R28 | IOSTANDARD = LVCMOS33;
NET "hldn_dq3" LOC = T28 | IOSTANDARD = LVCMOS33;
openFPGALoader-0.13.1/spiOverJtag/constr_xc7s_csga225.xdc 0000664 0000000 0000000 00000001147 14735055600 0022771 0 ustar 00root root 0000000 0000000 set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property -dict {PACKAGE_PIN L11 IOSTANDARD LVCMOS33} [get_ports {csn}];
set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}];
set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}];
set_property -dict {PACKAGE_PIN J12 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}];
set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}];
openFPGALoader-0.13.1/spiOverJtag/constr_xc7s_csga324.xdc 0000664 0000000 0000000 00000001147 14735055600 0022771 0 ustar 00root root 0000000 0000000 set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS33} [get_ports {csn}];
set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}];
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}];
set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}];
set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}];
openFPGALoader-0.13.1/spiOverJtag/constr_xc7s_ftgb196.xdc 0000664 0000000 0000000 00000001147 14735055600 0023005 0 ustar 00root root 0000000 0000000 set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS33} [get_ports {csn}];
set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}];
set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}];
set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}];
set_property -dict {PACKAGE_PIN C10 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}];
openFPGALoader-0.13.1/spiOverJtag/constr_xc7v_ffg1157.ucf 0000664 0000000 0000000 00000000404 14735055600 0022700 0 ustar 00root root 0000000 0000000 NET "csn" LOC = AL33 | IOSTANDARD = LVCMOS18;
NET "sdi_dq0" LOC = AN33 | IOSTANDARD = LVCMOS18;
NET "sdo_dq1" LOC = AN34 | IOSTANDARD = LVCMOS18;
NET "wpn_dq2" LOC = AK34 | IOSTANDARD = LVCMOS18;
NET "hldn_dq3" LOC = AL34 | IOSTANDARD = LVCMOS18;
openFPGALoader-0.13.1/spiOverJtag/constr_xc7v_ffg1157.xdc 0000664 0000000 0000000 00000001172 14735055600 0022704 0 ustar 00root root 0000000 0000000 set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
# Table 1-2 from UG570
set_property CFGBVS GND [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
set_property -dict {PACKAGE_PIN AL33 IOSTANDARD LVCMOS18} [get_ports {csn}]
set_property -dict {PACKAGE_PIN AN33 IOSTANDARD LVCMOS18} [get_ports {sdi_dq0}]
set_property -dict {PACKAGE_PIN AN34 IOSTANDARD LVCMOS18} [get_ports {sdo_dq1}]
set_property -dict {PACKAGE_PIN AK34 IOSTANDARD LVCMOS18} [get_ports {wpn_dq2}]
set_property -dict {PACKAGE_PIN AL34 IOSTANDARD LVCMOS18} [get_ports {hldn_dq3}]
openFPGALoader-0.13.1/spiOverJtag/constr_xcku040_ffva1156.xdc 0000664 0000000 0000000 00000003636 14735055600 0023401 0 ustar 00root root 0000000 0000000 set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
# Table 1-5 from UG917
set_property CFGBVS GND [current_design]
# Primary QSPI flash
# Connection done through the STARTUPE3 block
# sdi_dq0 - PACKAGE_PIN AC7 - QSPI0_IO0 Bank 0 - D00_MOSI_0
# sdo_dq1 - PACKAGE_PIN AB7 - QSPI0_IO1 Bank 0 - D01_DIN_0
# wpn_dq2 - PACKAGE_PIN AA7 - QSPI0_IO2 Bank 0 - D02_0
# hldn_dq3 - PACKAGE_PIN Y7 - QSPI0_IO3 Bank 0 - D03_0
# csn - PACKAGE_PIN U7 - QSPI0_CSB Bank 0 - RDWR_FCS_B_0
# sck - PACKAGE_PIN AA9 - FPGA_CCLK Bank 0 - CCLK_0
# Secondary QSPI flash
set_property PACKAGE_PIN M20 [get_ports "sdi_sec_dq0"] ;# Bank 65 VCCO - VCC1V8 - IO_L22P_T3U_N6_DBC_AD0P_D04_65
set_property IOSTANDARD LVCMOS18 [get_ports "sdi_sec_dq0"] ;# Bank 65 VCCO - VCC1V8 - IO_L22P_T3U_N6_DBC_AD0P_D04_65
set_property PACKAGE_PIN L20 [get_ports "sdo_sec_dq1"] ;# Bank 65 VCCO - VCC1V8 - IO_L22N_T3U_N7_DBC_AD0N_D05_65
set_property IOSTANDARD LVCMOS18 [get_ports "sdo_sec_dq1"] ;# Bank 65 VCCO - VCC1V8 - IO_L22N_T3U_N7_DBC_AD0N_D05_65
set_property PACKAGE_PIN R21 [get_ports "wpn_sec_dq2"] ;# Bank 65 VCCO - VCC1V8 - IO_L21P_T3L_N4_AD8P_D06_65
set_property IOSTANDARD LVCMOS18 [get_ports "wpn_sec_dq2"] ;# Bank 65 VCCO - VCC1V8 - IO_L21P_T3L_N4_AD8P_D06_65
set_property PACKAGE_PIN R22 [get_ports "hldn_sec_dq3"] ;# Bank 65 VCCO - VCC1V8 - IO_L21N_T3L_N5_AD8N_D07_65
set_property IOSTANDARD LVCMOS18 [get_ports "hldn_sec_dq3"] ;# Bank 65 VCCO - VCC1V8 - IO_L21N_T3L_N5_AD8N_D07_65
set_property PACKAGE_PIN G26 [get_ports "csn_sec"] ;# Bank 65 VCCO - VCC1V8 - IO_L2N_T0L_N3_FWE_FCS2_B_65
set_property IOSTANDARD LVCMOS18 [get_ports "csn_sec"] ;# Bank 65 VCCO - VCC1V8 - IO_L2N_T0L_N3_FWE_FCS2_B_65
openFPGALoader-0.13.1/spiOverJtag/constr_xcku060_ffva1156.xdc 0000664 0000000 0000000 00000003636 14735055600 0023403 0 ustar 00root root 0000000 0000000 set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
# Table 1-5 from UG917
set_property CFGBVS GND [current_design]
# Primary QSPI flash
# Connection done through the STARTUPE3 block
# sdi_dq0 - PACKAGE_PIN AC7 - QSPI0_IO0 Bank 0 - D00_MOSI_0
# sdo_dq1 - PACKAGE_PIN AB7 - QSPI0_IO1 Bank 0 - D01_DIN_0
# wpn_dq2 - PACKAGE_PIN AA7 - QSPI0_IO2 Bank 0 - D02_0
# hldn_dq3 - PACKAGE_PIN Y7 - QSPI0_IO3 Bank 0 - D03_0
# csn - PACKAGE_PIN U7 - QSPI0_CSB Bank 0 - RDWR_FCS_B_0
# sck - PACKAGE_PIN AA9 - FPGA_CCLK Bank 0 - CCLK_0
# Secondary QSPI flash
set_property PACKAGE_PIN M20 [get_ports "sdi_sec_dq0"] ;# Bank 65 VCCO - VCC1V8 - IO_L22P_T3U_N6_DBC_AD0P_D04_65
set_property IOSTANDARD LVCMOS18 [get_ports "sdi_sec_dq0"] ;# Bank 65 VCCO - VCC1V8 - IO_L22P_T3U_N6_DBC_AD0P_D04_65
set_property PACKAGE_PIN L20 [get_ports "sdo_sec_dq1"] ;# Bank 65 VCCO - VCC1V8 - IO_L22N_T3U_N7_DBC_AD0N_D05_65
set_property IOSTANDARD LVCMOS18 [get_ports "sdo_sec_dq1"] ;# Bank 65 VCCO - VCC1V8 - IO_L22N_T3U_N7_DBC_AD0N_D05_65
set_property PACKAGE_PIN R21 [get_ports "wpn_sec_dq2"] ;# Bank 65 VCCO - VCC1V8 - IO_L21P_T3L_N4_AD8P_D06_65
set_property IOSTANDARD LVCMOS18 [get_ports "wpn_sec_dq2"] ;# Bank 65 VCCO - VCC1V8 - IO_L21P_T3L_N4_AD8P_D06_65
set_property PACKAGE_PIN R22 [get_ports "hldn_sec_dq3"] ;# Bank 65 VCCO - VCC1V8 - IO_L21N_T3L_N5_AD8N_D07_65
set_property IOSTANDARD LVCMOS18 [get_ports "hldn_sec_dq3"] ;# Bank 65 VCCO - VCC1V8 - IO_L21N_T3L_N5_AD8N_D07_65
set_property PACKAGE_PIN G26 [get_ports "csn_sec"] ;# Bank 65 VCCO - VCC1V8 - IO_L2N_T0L_N3_FWE_FCS2_B_65
set_property IOSTANDARD LVCMOS18 [get_ports "csn_sec"] ;# Bank 65 VCCO - VCC1V8 - IO_L2N_T0L_N3_FWE_FCS2_B_65
openFPGALoader-0.13.1/spiOverJtag/constr_xcku3p_ffva676.xdc 0000664 0000000 0000000 00000000363 14735055600 0023340 0 ustar 00root root 0000000 0000000 set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
# Table 1-2 from UG570
set_property CFGBVS GND [current_design]
# Primary QSPI flash
# Connection done through the STARTUPE3 block
openFPGALoader-0.13.1/spiOverJtag/constr_xcku5p_ffvb676.xdc 0000664 0000000 0000000 00000002662 14735055600 0023347 0 ustar 00root root 0000000 0000000 set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
# Table 1-2 from UG570
set_property CFGBVS GND [current_design]
# Primary QSPI flash
# Connection done through the STARTUPE3 block
# Secondary QSPI flash
set_property PACKAGE_PIN N23 [get_ports "sdi_sec_dq0"] ;# Bank 65 VCCO - VCC1V8 - IO_L22P_T3U_N6_DBC_AD0P_D04_65
set_property IOSTANDARD LVCMOS18 [get_ports "sdi_sec_dq0"] ;# Bank 65 VCCO - VCC1V8 - IO_L22P_T3U_N6_DBC_AD0P_D04_65
set_property PACKAGE_PIN P23 [get_ports "sdo_sec_dq1"] ;# Bank 65 VCCO - VCC1V8 - IO_L22N_T3U_N7_DBC_AD0N_D05_65
set_property IOSTANDARD LVCMOS18 [get_ports "sdo_sec_dq1"] ;# Bank 65 VCCO - VCC1V8 - IO_L22N_T3U_N7_DBC_AD0N_D05_65
set_property PACKAGE_PIN R20 [get_ports "wpn_sec_dq2"] ;# Bank 65 VCCO - VCC1V8 - IO_L21P_T3L_N4_AD8P_D06_65
set_property IOSTANDARD LVCMOS18 [get_ports "wpn_sec_dq2"] ;# Bank 65 VCCO - VCC1V8 - IO_L21P_T3L_N4_AD8P_D06_65
set_property PACKAGE_PIN R21 [get_ports "hldn_sec_dq3"] ;# Bank 65 VCCO - VCC1V8 - IO_L21N_T3L_N5_AD8N_D07_65
set_property IOSTANDARD LVCMOS18 [get_ports "hldn_sec_dq3"] ;# Bank 65 VCCO - VCC1V8 - IO_L21N_T3L_N5_AD8N_D07_65
set_property PACKAGE_PIN U22 [get_ports "csn_sec"] ;# Bank 65 VCCO - VCC1V8 - IO_L2N_T0L_N3_FWE_FCS2_B_65
set_property IOSTANDARD LVCMOS18 [get_ports "csn_sec"] ;# Bank 65 VCCO - VCC1V8 - IO_L2N_T0L_N3_FWE_FCS2_B_65 openFPGALoader-0.13.1/spiOverJtag/constr_xcvu37p_fsvh2892.xdc 0000664 0000000 0000000 00000001336 14735055600 0023551 0 ustar 00root root 0000000 0000000 set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
# Table 3-5 from UG1302
set_property CFGBVS GND [current_design]
# Primary QSPI flash
# Connection done through the STARTUPE3 block
# sdi_dq0 - PACKAGE_PIN AW15 - QSPI0_DQ0 Bank 0 - D00_MOSI_0
# sdo_dq1 - PACKAGE_PIN AY15 - QSPI0_DQ1 Bank 0 - D01_DIN_0
# wpn_dq2 - PACKAGE_PIN AY14 - QSPI0_DQ2 Bank 0 - D02_0
# hldn_dq3 - PACKAGE_PIN AY13 - QSPI0_DQ3 Bank 0 - D03_0
# csn - PACKAGE_PIN BC15 - QSPI0_CS_B Bank 0 - RDWR_FCS_B_0
# sck - PACKAGE_PIN BD14 - QSPI_CCLK Bank 0 - CCLK_0 openFPGALoader-0.13.1/spiOverJtag/constr_xcvu9p_flga2104.xdc 0000664 0000000 0000000 00000002522 14735055600 0023413 0 ustar 00root root 0000000 0000000 set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
# Table 1-2 from UG570
set_property CFGBVS GND [current_design]
# Primary QSPI flash
# Connection done through the STARTUPE3 block
# sdi_dq0 - PACKAGE_PIN AP11 - QSPI0_DQ0 Bank 0 - D00_MOSI_0
# sdo_dq1 - PACKAGE_PIN AN11 - QSPI0_DQ1 Bank 0 - D01_DIN_0
# wpn_dq2 - PACKAGE_PIN AM11 - QSPI0_DQ2 Bank 0 - D02_0
# hldn_dq3 - PACKAGE_PIN AL11 - QSPI0_DQ3 Bank 0 - D03_0
# csn - PACKAGE_PIN AJ11 - QSPI0_CS_B Bank 0 - RDWR_FCS_B_0
# sck - PACKAGE_PIN AF13 - QSPI_CCLK Bank 0 - CCLK_0
# Secondary QSPI flash
set_property PACKAGE_PIN AM19 [get_ports "sdi_sec_dq0"];
set_property IOSTANDARD LVCMOS18 [get_ports "sdi_sec_dq0"];
set_property PACKAGE_PIN AM18 [get_ports "sdo_sec_dq1"];
set_property IOSTANDARD LVCMOS18 [get_ports "sdo_sec_dq1"];
set_property PACKAGE_PIN AN20 [get_ports "wpn_sec_dq2"];
set_property IOSTANDARD LVCMOS18 [get_ports "wpn_sec_dq2"];
set_property PACKAGE_PIN AP20 [get_ports "hldn_sec_dq3"];
set_property IOSTANDARD LVCMOS18 [get_ports "hldn_sec_dq3"];
set_property PACKAGE_PIN BF16 [get_ports "csn_sec"];
set_property IOSTANDARD LVCMOS18 [get_ports "csn_sec"];
openFPGALoader-0.13.1/spiOverJtag/efinix_build.py 0000775 0000000 0000000 00000013716 14735055600 0021612 0 ustar 00root root 0000000 0000000 #!/usr/bin/env python3
import argparse
import datetime
import os
import pathlib
import pprint
import re
import sys
from edalize.edatool import get_edatool
from edalize.flows.efinity import Efinity
#from xml.dom import expatbuilder
#import xml.etree.ElementTree as et
#efinity_home = os.environ["EFINITY_HOME"]
#script_path = efinity_home + "/scripts"
curr_path = os.getcwd()
efinix_pinout = {
"Trion": {
"F49": { # t4/t8
"ss_n": "G3", "cclk": "F3", "cdi0": "F2", "cdi1": "F1", "cdi2": "E2", "cdi3": "D2",
},
"F81": { # t4/t8
"ss_n": "J4", "cclk": "H4", "cdi0": "F4", "cdi1": "H3", "cdi2": "J2", "cdi3": "F3",
},
"F169": { # t13/t20
"ss_n": "L1", "cclk": "K1", "cdi0": "J1", "cdi1": "J2", "cdi2": "F1", "cdi3": "G2",
},
"F256": { # t13/t20
"ss_n": "P3", "cclk": "H3", "cdi0": "L3", "cdi1": "N1", "cdi2": "K4", "cdi3": "L2",
},
"F324": { # t20/t85/t120
"ss_n": "P15", "cclk": "N13", "cdi0": "M13", "cdi1": "N14", "cdi2": "K14", "cdi3": "K18",
},
"F400": { # t20/
"ss_n": "W18", "cclk": "W19", "cdi0": "Y17", "cdi1": "Y18", "cdi2": "P15", "cdi3": "R17",
},
"Q100": { # t13/t20
"ss_n": "24", "cclk": "26", "cdi0": "19", "cdi1": "18", "cdi2": "8", "cdi3": "14",
},
"Q144": { # t20/
"ss_n": "31", "cclk": "30", "cdi0": "29", "cdi1": "28", "cdi2": "20", "cdi3": "19",
},
"W80": { # t20/
"ss_n": "K3", "cclk": "K2", "cdi0": "J1", "cdi1": "J2", "cdi2": "F1", "cdi3": "G2",
},
},
"Titanium": {
"J484": { # ti180, ...
"ss_n": "E2", "cclk": "J2", "cdi0": "G2", "cdi1": "H2", "cdi2": "F3", "cdi3": "G3",
},
},
}
timing_models = {
"T8F81": "C2",
"T13F256": "C3",
"TI180J484": "C3",
}
def gen_isf_constr(gateware_name, build_path, device_name, family, pkg):
# Basic settings
isf_array = [
"# Device setting",
"design.set_device_property(\"1A\",\"VOLTAGE\",\"3.3\",\"IOBANK\")",
"design.set_device_property(\"1B\",\"VOLTAGE\",\"3.3\",\"IOBANK\")",
"design.set_device_property(\"1C\",\"VOLTAGE\",\"1.1\",\"IOBANK\")",
"design.set_device_property(\"2A\",\"VOLTAGE\",\"3.3\",\"IOBANK\")",
"design.set_device_property(\"2B\",\"VOLTAGE\",\"3.3\",\"IOBANK\")",
"",
]
# JTAG settings
isf_array.append("# ---------- JTAG 1 ---------")
isf_array.append("design.create_block(\"jtag_soc\", block_type=\"JTAG\")")
isf_array.append("design.assign_resource(\"jtag_soc\", \"JTAG_USER1\", \"JTAG\")")
jtag_pads = [
"CAPTURE", "DRCK", "RESET", "RUNTEST", "SEL", "SHIFT", "TCK", "TDI", "TMS", "UPDATE", "TDO"
]
for pad in jtag_pads:
isf_array.append(f"design.set_property(\"jtag_soc\", \"{pad}\", \"jtag_1_{pad}\", \"JTAG\")")
# SPI pins settings
pins = efinix_pinout.get(family).get(pkg, None)
assert pins is not None
pin_lst = [
{"name" : "csn", "dir": "out", "pin": pins["ss_n"], "io_std": "3.3 V LVTTL / LVCMOS"},
{"name" : "sck", "dir": "out", "pin": pins["cclk"], "io_std": "3.3 V LVTTL / LVCMOS"},
{"name" : "sdi_dq0", "dir": "out", "pin": pins["cdi0"], "io_std": "3.3 V LVTTL / LVCMOS"},
{"name" : "sdo_dq1", "dir": "in", "pin": pins["cdi1"], "io_std": "3.3 V LVTTL / LVCMOS"},
]
for pin_cfg in pin_lst:
name = pin_cfg["name"]
pin_loc = pin_cfg["pin"]
if pin_cfg["dir"] == "in":
isf_array.append(f"design.create_input_gpio(\"{name}\")")
else:
isf_array.append(f"design.create_output_gpio(\"{name}\")")
isf_array.append(f"design.assign_pkg_pin(\"{name}\", \"{pin_loc}\")")
isf_array.append("")
# Save ISF file
with open(os.path.join(build_dir, build_name+".isf"), "w") as fd:
fd.write("\n".join(isf_array))
if __name__ == "__main__":
parser = argparse.ArgumentParser("SpiOverJtag for Efinix devices")
parser.add_argument("--device", help="Efinix Device")
args = parser.parse_args()
assert args.device is not None
device = args.device.upper()
build_name = "efinix_spiOverJtag"
build_dir = os.path.join(curr_path, f"tmp_efinix_{device.lower()}")
timing_model = timing_models.get(device, "C3")
sources = [
{
'name': os.path.join(curr_path, "efinix_spiOverJtag.v"),
"file_type": "verilogSource",
},
{
'name': os.path.join(build_dir, "efinix_spiOverJtag.isf"),
"file_type": "ISF",
},
]
force_restart = False
t = re.compile(r"(T[I]*)(\d+)(\w\d+)")
tt = t.match(device)
if tt is None:
print("fails")
else:
(fam, size, package) = tt.groups()
assert fam in ["TI", "T"]
family = {True:"Titanium", False:"Trion"}[fam == "TI"]
if fam == "TI":
device = device.replace("TI", "Ti")
if os.path.exists(build_dir) and force_restart:
os.rmdir(build_dir)
if not os.path.exists(build_dir):
try:
os.mkdir(build_dir)
except FileExistsError:
pass
gen_isf_constr(
gateware_name = build_name,
build_path = build_dir,
device_name = device,
family = family,
pkg = package
)
tool_options = {
'part' : device,
'family' : family,
'timing' : timing_model,
}
edam = {
'name' : build_name,
'files' : sources,
'flow_options' : tool_options,
'toplevel' : 'spiOverJtag',
}
backend = Efinity(edam=edam, work_root=build_dir)
backend.configure()
backend.build()
import shutil
shutil.copy(os.path.join(build_dir, "outflow", "efinix_spiOverJtag.bit"), build_dir)
openFPGALoader-0.13.1/spiOverJtag/efinix_spiOverJtag.v 0000664 0000000 0000000 00000002246 14735055600 0022556 0 ustar 00root root 0000000 0000000 module spiOverJtag (
input jtag_1_CAPTURE,
input jtag_1_DRCK,
input jtag_1_RESET,
input jtag_1_RUNTEST,
input jtag_1_SEL,
input jtag_1_SHIFT,
input jtag_1_TCK,
input jtag_1_TDI,
input jtag_1_TMS,
input jtag_1_UPDATE,
output jtag_1_TDO,
output csn,
output sck,
output sdi_dq0,
input sdo_dq1,
output wpn_dq2,
output hldn_dq3
);
wire capture, drck, sel, update;
wire runtest;
wire tdi;
reg fsm_csn;
assign wpn_dq2 = 1'b1;
assign hldn_dq3 = 1'b1;
// jtag -> spi flash
assign sdi_dq0 = tdi;
wire tdo = (sel) ? sdo_dq1 : tdi;
assign csn = fsm_csn;
wire tmp_cap_s = capture && sel;
wire tmp_up_s = update && sel;
always @(posedge drck, posedge runtest) begin
if (runtest) begin
fsm_csn <= 1'b1;
end else begin
if (tmp_cap_s) begin
fsm_csn <= 1'b0;
end else if (tmp_up_s) begin
fsm_csn <= 1'b1;
end else begin
fsm_csn <= fsm_csn;
end
end
end
assign sck = drck;
assign capture = jtag_1_CAPTURE;
assign drck = jtag_1_DRCK;
assign runtest = jtag_1_RUNTEST;
assign sel = jtag_1_SEL;
assign tdi = jtag_1_TDI;
assign update = jtag_1_UPDATE;
assign jtag_1_TDO = tdo;
endmodule
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